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technology</title> <meta name="description" content="Search results for: CMOS technology"> <meta name="keywords" content="CMOS technology"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> <button class="d-block d-lg-none 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action="https://publications.waset.org/abstracts/search"> <div id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="CMOS technology"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 7758</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: CMOS technology</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7758</span> A Fault-Tolerant Full Adder in Double Pass CMOS Transistor</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abdelmonaem%20Ayachi">Abdelmonaem Ayachi</a>, <a href="https://publications.waset.org/abstracts/search?q=Belgacem%20Hamdi"> Belgacem Hamdi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=digital%20electronics" title="digital electronics">digital electronics</a>, <a href="https://publications.waset.org/abstracts/search?q=integrated%20circuits" title=" integrated circuits"> integrated circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=full%20adder" title=" full adder"> full adder</a>, <a href="https://publications.waset.org/abstracts/search?q=32nm%20CMOS%20tehnology" title=" 32nm CMOS tehnology"> 32nm CMOS tehnology</a>, <a href="https://publications.waset.org/abstracts/search?q=double%20pass%20transistor%20technology" title=" double pass transistor technology"> double pass transistor technology</a>, <a href="https://publications.waset.org/abstracts/search?q=fault%20toleance" title=" fault toleance"> fault toleance</a>, <a href="https://publications.waset.org/abstracts/search?q=self-checking" title=" self-checking"> self-checking</a> </p> <a href="https://publications.waset.org/abstracts/40794/a-fault-tolerant-full-adder-in-double-pass-cmos-transistor" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/40794.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">346</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7757</span> Performance Analysis of 180 nm Low Voltage Low Power CMOS OTA for High Frequency Application</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=D.%20J.%20Dahigaonkar">D. J. Dahigaonkar</a>, <a href="https://publications.waset.org/abstracts/search?q=D.%20G.%20Wakde"> D. G. Wakde</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The performance analysis of low voltage low power CMOS OTA is presented in this paper. The differential input single output OTA is simulated in 180nm CMOS process technology. The simulation results indicate high bandwidth of the order of 7.04GHz with 0.766mW power consumption and transconductance of -71.20dB. The total harmonic distortion for 100mV input at a frequency of 1MHz is found to be 2.3603%. In addition to this, to establish comparative analysis of designed OTA and analyze effect of technology scaling, the differential input single output OTA is further simulated using 350nm CMOS process technology and the comparative analysis is presented in this paper. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Operational%20Transconductance%20Amplifier" title="Operational Transconductance Amplifier">Operational Transconductance Amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=Total%20Harmonic%20Distortions" title=" Total Harmonic Distortions"> Total Harmonic Distortions</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20voltage%2Flow%20power" title=" low voltage/low power"> low voltage/low power</a>, <a href="https://publications.waset.org/abstracts/search?q=power%20dissipation" title=" power dissipation"> power dissipation</a> </p> <a href="https://publications.waset.org/abstracts/3085/performance-analysis-of-180-nm-low-voltage-low-power-cmos-ota-for-high-frequency-application" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/3085.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">408</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7756</span> High Power Low Loss CMOS SPDT Antenna Switch for LTE-A Front End Module</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ki-Jin%20Kim">Ki-Jin Kim</a>, <a href="https://publications.waset.org/abstracts/search?q=Suk-Hui%20LEE"> Suk-Hui LEE</a>, <a href="https://publications.waset.org/abstracts/search?q=Sanghoon%20Park"> Sanghoon Park</a>, <a href="https://publications.waset.org/abstracts/search?q=K.%20H.%20Ahn"> K. H. Ahn</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A high power, low loss asymmetric single pole double through(SPDT) antenna switch for LTE-A Front-End Module(FEM) is presented in this paper by using CMOS technology. For the usage of LTE-A applications, low loss and high linearity are the key features which are very challenging works under CMOS process. To enhance insertion loss(IL) and power handling capability, this paper adopts asymmetric Transmitter (TX) and RX (Receiver) structure, floating body technique, multi-stacked structure, and feed forward capacitor technique. The designed SPDT switch shows TX IL 0.34 dB, RX IL 0.73 dB, P1dB 38.9 dBm at 0.9 GHz and TX IL 0.37 dB, RX IL 0.95 dB, P1dB 39.1 dBm at 2.5 GHz respectively. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS%20switch" title="CMOS switch">CMOS switch</a>, <a href="https://publications.waset.org/abstracts/search?q=SPDT%20switch" title=" SPDT switch"> SPDT switch</a>, <a href="https://publications.waset.org/abstracts/search?q=high%20power%20CMOS%20switch" title=" high power CMOS switch"> high power CMOS switch</a>, <a href="https://publications.waset.org/abstracts/search?q=LTE-A%20FEM" title=" LTE-A FEM "> LTE-A FEM </a> </p> <a href="https://publications.waset.org/abstracts/22508/high-power-low-loss-cmos-spdt-antenna-switch-for-lte-a-front-end-module" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/22508.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">364</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7755</span> Design of a High Performance T/R Switch for 2.4 GHz RF Wireless Transceiver in 0.13 µm CMOS Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mohammad%20Arif%20Sobhan%20Bhuiyan">Mohammad Arif Sobhan Bhuiyan</a>, <a href="https://publications.waset.org/abstracts/search?q=Mamun%20Bin%20Ibne%20Reaz"> Mamun Bin Ibne Reaz</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The rapid advancement of CMOS technology, in the recent years, has led the scientists to fabricate wireless transceivers fully on-chip which results in smaller size and lower cost wireless communication devices with acceptable performance characteristics. Moreover, the performance of the wireless transceivers rigorously depends on the performance of its first block T/R switch. This article proposes a design of a high performance T/R switch for 2.4 GHz RF wireless transceivers in 0.13 µm CMOS technology. The switch exhibits 1- dB insertion loss, 37.2-dB isolation in transmit mode and 1.4-dB insertion loss, 25.6-dB isolation in receive mode. The switch has a power handling capacity (P1dB) of 30.9-dBm. Besides, by avoiding bulky inductors and capacitors, the size of the switch is drastically reduced and it occupies only (0.00296) mm2 which is the lowest ever reported in this frequency band. Therefore, simplicity and low chip area of the circuit will trim down the cost of fabrication as well as the whole transceiver. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS" title="CMOS">CMOS</a>, <a href="https://publications.waset.org/abstracts/search?q=ISM%20band" title=" ISM band"> ISM band</a>, <a href="https://publications.waset.org/abstracts/search?q=SPDT" title=" SPDT"> SPDT</a>, <a href="https://publications.waset.org/abstracts/search?q=t%2Fr%20switch" title=" t/r switch"> t/r switch</a>, <a href="https://publications.waset.org/abstracts/search?q=transceiver" title=" transceiver"> transceiver</a> </p> <a href="https://publications.waset.org/abstracts/28930/design-of-a-high-performance-tr-switch-for-24-ghz-rf-wireless-transceiver-in-013-m-cmos-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/28930.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">448</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7754</span> 0.13-μm CMOS Vector Modulator for Wireless Backhaul System</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=J.%20S.%20Kim">J. S. Kim</a>, <a href="https://publications.waset.org/abstracts/search?q=N.%20P.%20Hong"> N. P. Hong</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, a CMOS vector modulator designed for wireless backhaul system based on 802.11ac is presented. A poly phase filter and sign select switches yield two orthogonal signal paths. Two variable gain amplifiers with strongly reduced phase shift of only ±5 ° are used to weight these paths. It has a phase control range of 360 ° and a gain range of -10 dB to 10 dB. The current drawn from a 1.2 V supply amounts 20.4 mA. Using a 0.13 mm technology, the chip die area amounts 1.47x0.75 mm². <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS" title="CMOS">CMOS</a>, <a href="https://publications.waset.org/abstracts/search?q=phase%20shifter" title=" phase shifter"> phase shifter</a>, <a href="https://publications.waset.org/abstracts/search?q=backhaul" title=" backhaul"> backhaul</a>, <a href="https://publications.waset.org/abstracts/search?q=802.11ac" title=" 802.11ac"> 802.11ac</a> </p> <a href="https://publications.waset.org/abstracts/48871/013-mm-cmos-vector-modulator-for-wireless-backhaul-system" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/48871.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">386</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7753</span> Design and Characterization of a CMOS Process Sensor Utilizing Vth Extractor Circuit</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Rohana%20Musa">Rohana Musa</a>, <a href="https://publications.waset.org/abstracts/search?q=Yuzman%20Yusoff"> Yuzman Yusoff</a>, <a href="https://publications.waset.org/abstracts/search?q=Chia%20Chieu%20Yin"> Chia Chieu Yin</a>, <a href="https://publications.waset.org/abstracts/search?q=Hanif%20Che%20Lah"> Hanif Che Lah</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (V<sub>th</sub>) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS%20process%20sensor" title="CMOS process sensor">CMOS process sensor</a>, <a href="https://publications.waset.org/abstracts/search?q=PVT%20sensor" title=" PVT sensor"> PVT sensor</a>, <a href="https://publications.waset.org/abstracts/search?q=threshold%20extractor%20circuit" title=" threshold extractor circuit"> threshold extractor circuit</a>, <a href="https://publications.waset.org/abstracts/search?q=Vth%20extractor%20circuit" title=" Vth extractor circuit"> Vth extractor circuit</a> </p> <a href="https://publications.waset.org/abstracts/129672/design-and-characterization-of-a-cmos-process-sensor-utilizing-vth-extractor-circuit" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/129672.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">175</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7752</span> Inverter Based Gain-Boosting Fully Differential CMOS Amplifier</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Alpana%20Agarwal">Alpana Agarwal</a>, <a href="https://publications.waset.org/abstracts/search?q=Akhil%20Sharma"> Akhil Sharma</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7<sup>o</sup> with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS%20amplifier" title="CMOS amplifier">CMOS amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=gain%20boosting" title=" gain boosting"> gain boosting</a>, <a href="https://publications.waset.org/abstracts/search?q=inverter-based%20amplifier" title=" inverter-based amplifier"> inverter-based amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=self-biased%20inverter" title=" self-biased inverter"> self-biased inverter</a> </p> <a href="https://publications.waset.org/abstracts/64250/inverter-based-gain-boosting-fully-differential-cmos-amplifier" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/64250.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">303</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7751</span> Voltage Controlled Ring Oscillator for RF Applications in 0.18 µm CMOS Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mohammad%20Arif%20Sobhan%20Bhuiyan">Mohammad Arif Sobhan Bhuiyan</a>, <a href="https://publications.waset.org/abstracts/search?q=Zainal%20Abidin%20Nordin"> Zainal Abidin Nordin</a>, <a href="https://publications.waset.org/abstracts/search?q=Mamun%20Bin%20Ibne%20Reaz"> Mamun Bin Ibne Reaz</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A compact and power efficient high performance Voltage Controlled Oscillator (VCO) is a must in analog and digital circuits especially in the communication system, but the best trade-off among the performance parameters is a challenge for researchers. In this paper, a design of a compact 3-stage differential voltage controlled ring oscillator (VCRO) with low phase noise, low power and higher tuning bandwidth is proposed in 0.18 µm CMOS technology. The VCRO is designed with symmetric load and positive feedback techniques to achieve higher gain and minimum delay. The proposed VCRO can operate at tuning range of 3.9-5.0 GHz at 1.6 V supply voltage. The circuit consumes only 1.0757 mW of power and produces -129 dbc/Hz. The total active area of the proposed VCRO is only 11.74 x 37.73 µm2. Such a VCO can be the best choice for compact and low-power RF applications. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS" title="CMOS">CMOS</a>, <a href="https://publications.waset.org/abstracts/search?q=VCO" title=" VCO"> VCO</a>, <a href="https://publications.waset.org/abstracts/search?q=VCRO" title=" VCRO"> VCRO</a>, <a href="https://publications.waset.org/abstracts/search?q=oscillator" title=" oscillator"> oscillator</a> </p> <a href="https://publications.waset.org/abstracts/2797/voltage-controlled-ring-oscillator-for-rf-applications-in-018-m-cmos-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/2797.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">475</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7750</span> An Approach for Modeling CMOS Gates</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Spyridon%20Nikolaidis">Spyridon Nikolaidis</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS%20gate%20modeling" title="CMOS gate modeling">CMOS gate modeling</a>, <a href="https://publications.waset.org/abstracts/search?q=inverter%20modeling" title=" inverter modeling"> inverter modeling</a>, <a href="https://publications.waset.org/abstracts/search?q=transistor%20current%20mode" title=" transistor current mode"> transistor current mode</a>, <a href="https://publications.waset.org/abstracts/search?q=timing%20model" title=" timing model "> timing model </a> </p> <a href="https://publications.waset.org/abstracts/16511/an-approach-for-modeling-cmos-gates" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/16511.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">423</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7749</span> The Design of PFM Mode DC-DC Converter with DT-CMOS Switch</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jae-Chang%20Kwak">Jae-Chang Kwak</a>, <a href="https://publications.waset.org/abstracts/search?q=Yong-Seo%20Koo"> Yong-Seo Koo</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=DT-CMOS" title="DT-CMOS">DT-CMOS</a>, <a href="https://publications.waset.org/abstracts/search?q=PMIC" title=" PMIC"> PMIC</a>, <a href="https://publications.waset.org/abstracts/search?q=PFM" title=" PFM"> PFM</a>, <a href="https://publications.waset.org/abstracts/search?q=DC-DC%20converter" title=" DC-DC converter"> DC-DC converter</a> </p> <a href="https://publications.waset.org/abstracts/11839/the-design-of-pfm-mode-dc-dc-converter-with-dt-cmos-switch" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/11839.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">451</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7748</span> A CMOS-Integrated Hall Plate with High Sensitivity</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jin%20Sup%20Kim">Jin Sup Kim</a>, <a href="https://publications.waset.org/abstracts/search?q=Min%20Seo"> Min Seo</a> </p> <p class="card-text"><strong>Abstract:</strong></p> An improved cross-shaped hall plate with high sensitivity is described in this paper. Among different geometries that have been simulated and measured using Helmholtz coil. The paper describes the physical hall plate design and implementation in a 0.18-µm CMOS technology. In this paper, the biasing is a constant voltage mode. In the voltage mode, magnetic field is converted into an output voltage. The output voltage is typically in the order of micro- to millivolt and therefore, it must be amplified before being transmitted to the outside world. The study, design and performance optimization of hall plate has been carried out with the COMSOL Multiphysics. It is used to estimate the voltage distribution in the hall plate with and without magnetic field and to optimize the geometry. The simulation uses the nominal bias current of 1mA. The applied magnetic field is in the range from 0 mT to 20 mT. Measured results of the one structure over the 10 available samples show for the best sensitivity of 2.5 %/T at 20mT. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cross-shaped%20hall%20plate" title="cross-shaped hall plate">cross-shaped hall plate</a>, <a href="https://publications.waset.org/abstracts/search?q=sensitivity" title=" sensitivity"> sensitivity</a>, <a href="https://publications.waset.org/abstracts/search?q=CMOS%20technology" title=" CMOS technology"> CMOS technology</a>, <a href="https://publications.waset.org/abstracts/search?q=Helmholtz%20coil" title=" Helmholtz coil"> Helmholtz coil</a> </p> <a href="https://publications.waset.org/abstracts/79041/a-cmos-integrated-hall-plate-with-high-sensitivity" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/79041.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">197</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7747</span> Design of CMOS CFOA Based on Pseudo Operational Transconductance Amplifier</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hassan%20Jassim%20Motlak">Hassan Jassim Motlak </a> </p> <p class="card-text"><strong>Abstract:</strong></p> A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption whivh has a very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to symmetrical input stage. P-Spice simulation results using 0.18µm MIETEC CMOS process parameters using supply voltage of ±1.2V and 50μA biasing current. The P-Spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, open-loop gain-bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/µS, THD of -63dB and DC consumption power (PC) of 2mW. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=pseudo-OTA%20used%20CMOS%20CFOA" title="pseudo-OTA used CMOS CFOA">pseudo-OTA used CMOS CFOA</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20power%20CFOA" title=" low power CFOA"> low power CFOA</a>, <a href="https://publications.waset.org/abstracts/search?q=high-performance%20CFOA" title=" high-performance CFOA"> high-performance CFOA</a>, <a href="https://publications.waset.org/abstracts/search?q=novel%20CFOA" title=" novel CFOA"> novel CFOA</a> </p> <a href="https://publications.waset.org/abstracts/2597/design-of-cmos-cfoa-based-on-pseudo-operational-transconductance-amplifier" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/2597.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">316</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7746</span> Design and Simulation a Low Phase Noise CMOS LC VCO for IEEE802.11a WLAN Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hooman%20Kaabi">Hooman Kaabi</a>, <a href="https://publications.waset.org/abstracts/search?q=Raziyeh%20Karkoub"> Raziyeh Karkoub</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This work proposes a structure of AMOS-varactors. A 5GHz LC-VCO designed in TSMC 0.18μm CMOS to improve phase noise and tuning range performance. The tuning range is from 5.05GHZ to 5.88GHz.The phase noise is -154.9dBc/Hz at 1MHz offset from the carrier. It meets the requirements for IEEE 802.11a WLAN standard. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS%20LC%20VCO" title="CMOS LC VCO">CMOS LC VCO</a>, <a href="https://publications.waset.org/abstracts/search?q=spiral%20inductor" title=" spiral inductor"> spiral inductor</a>, <a href="https://publications.waset.org/abstracts/search?q=varactor" title=" varactor"> varactor</a>, <a href="https://publications.waset.org/abstracts/search?q=phase%20noise" title=" phase noise"> phase noise</a>, <a href="https://publications.waset.org/abstracts/search?q=tuning%20range" title=" tuning range"> tuning range</a> </p> <a href="https://publications.waset.org/abstracts/25972/design-and-simulation-a-low-phase-noise-cmos-lc-vco-for-ieee80211a-wlan-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/25972.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">536</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7745</span> A Low-Power, Low-Noise and High-Gain 58~66 GHz CMOS Receiver Front-End for Short-Range High-Speed Wireless Communications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yo-Sheng%20Lin">Yo-Sheng Lin</a>, <a href="https://publications.waset.org/abstracts/search?q=Jen-How%20Lee"> Jen-How Lee</a>, <a href="https://publications.waset.org/abstracts/search?q=Chien-Chin%20Wang"> Chien-Chin Wang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A 60-GHz receiver front-end using standard 90-nm CMOS technology is reported. The receiver front-end comprises a wideband low-noise amplifier (LNA), and a double-balanced Gilbert cell mixer with a current-reused RF single-to-differential (STD) converter, an LO Marchand balun and a baseband amplifier. The receiver front-end consumes 34.4 mW and achieves LO-RF isolation of 60.7 dB, LO-IF isolation of 45.3 dB and RF-IF isolation of 41.9 dB at RF of 60 GHz and LO of 59.9 GHz. At IF of 0.1 GHz, the receiver front-end achieves maximum conversion gain (CG) of 26.1 dB at RF of 64 GHz and CG of 25.2 dB at RF of 60 GHz. The corresponding 3-dB bandwidth of RF is 7.3 GHz (58.4 GHz to 65.7 GHz). The measured minimum noise figure was 5.6 dB at 64 GHz, one of the best results ever reported for a 60 GHz CMOS receiver front-end. In addition, the measured input 1-dB compression point and input third-order inter-modulation point are -33.1 dBm and -23.3 dBm, respectively, at 60 GHz. These results demonstrate the proposed receiver front-end architecture is very promising for 60 GHz direct-conversion transceiver applications. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS" title="CMOS">CMOS</a>, <a href="https://publications.waset.org/abstracts/search?q=60%20GHz" title=" 60 GHz"> 60 GHz</a>, <a href="https://publications.waset.org/abstracts/search?q=direct-conversion%20transceiver" title=" direct-conversion transceiver"> direct-conversion transceiver</a>, <a href="https://publications.waset.org/abstracts/search?q=LNA" title=" LNA"> LNA</a>, <a href="https://publications.waset.org/abstracts/search?q=down-conversion%20mixer" title=" down-conversion mixer"> down-conversion mixer</a>, <a href="https://publications.waset.org/abstracts/search?q=marchand%20balun" title=" marchand balun"> marchand balun</a>, <a href="https://publications.waset.org/abstracts/search?q=current-reused" title=" current-reused"> current-reused</a> </p> <a href="https://publications.waset.org/abstracts/32604/a-low-power-low-noise-and-high-gain-5866-ghz-cmos-receiver-front-end-for-short-range-high-speed-wireless-communications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/32604.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">452</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7744</span> A CMOS Capacitor Array for ESPAR with Fast Switching Time</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jin-Sup%20Kim">Jin-Sup Kim</a>, <a href="https://publications.waset.org/abstracts/search?q=Se-Hwan%20Choi"> Se-Hwan Choi</a>, <a href="https://publications.waset.org/abstracts/search?q=Jae-Young%20Lee"> Jae-Young Lee</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A 8-bit CMOS capacitor array is designed for using in electrically steerable passive array radiator (ESPAR). The proposed capacitor array shows the fast response time in rising and falling characteristics. Compared to other works in silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technologies, it shows a comparable tuning range and switching time with low power consumption. Using the 0.18um CMOS, the capacitor array features a tuning range of 1.5 to 12.9 pF at 2.4GHz. Including the 2X4 decoder for control interface, the Chip size is 350um X 145um. Current consumption is about 80 nA at 1.8 V operation. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS%20capacitor%20array" title="CMOS capacitor array">CMOS capacitor array</a>, <a href="https://publications.waset.org/abstracts/search?q=ESPAR" title=" ESPAR"> ESPAR</a>, <a href="https://publications.waset.org/abstracts/search?q=SOI" title=" SOI"> SOI</a>, <a href="https://publications.waset.org/abstracts/search?q=SOS" title=" SOS"> SOS</a>, <a href="https://publications.waset.org/abstracts/search?q=switching%20time" title=" switching time"> switching time</a> </p> <a href="https://publications.waset.org/abstracts/24058/a-cmos-capacitor-array-for-espar-with-fast-switching-time" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/24058.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">589</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7743</span> Design and Implementation of A 10-bit SAR ADC with A Programmable Reference</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hasmayadi%20Abdul%20Majid">Hasmayadi Abdul Majid</a>, <a href="https://publications.waset.org/abstracts/search?q=Yuzman%20Yusoff"> Yuzman Yusoff</a>, <a href="https://publications.waset.org/abstracts/search?q=Noor%20Shelida%20Salleh"> Noor Shelida Salleh</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents the development of a single-ended 38.5 kS/s 10-bit programmable reference SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and a SAR digital logic to create 10 effective bits ADC. A programmable reference circuitry allows the ADC to operate with different input range from 0.6 V to 2.1 V. A single ended 38.5 kS/s 10-bit programmable reference SAR ADC was proposed and implemented in a 0.35 µm CMOS technology and consumed less than 7.5 mW power with a 3 V supply. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=successive%20approximation%20register%20analog-to-digital%20converter" title="successive approximation register analog-to-digital converter">successive approximation register analog-to-digital converter</a>, <a href="https://publications.waset.org/abstracts/search?q=SAR%20ADC" title=" SAR ADC"> SAR ADC</a>, <a href="https://publications.waset.org/abstracts/search?q=resistive%20DAC" title=" resistive DAC"> resistive DAC</a>, <a href="https://publications.waset.org/abstracts/search?q=programmable%20reference" title=" programmable reference"> programmable reference</a> </p> <a href="https://publications.waset.org/abstracts/19760/design-and-implementation-of-a-10-bit-sar-adc-with-a-programmable-reference" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/19760.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">518</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7742</span> Design of Speedy, Scanty Adder for Lossy Application Using QCA</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=T.%20Angeline%20Priyanka">T. Angeline Priyanka</a>, <a href="https://publications.waset.org/abstracts/search?q=R.%20Ganesan"> R. Ganesan</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Recent trends in microelectronics technology have gradually changed the strategies used in very large scale integration (VLSI) circuits. Complementary Metal Oxide Semiconductor (CMOS) technology has been the industry standard for implementing VLSI device for the past two decades, but due to scale-down issues of ultra-low dimension achievement is not achieved so far. Hence it paved a way for Quantum Cellular Automata (QCA). It is only one of the many alternative technologies proposed as a replacement solution to the fundamental limit problem that CMOS technology will impose in the years to come. In this brief, presented a new adder that possesses high speed of operation occupying less area is proposed. This adder is designed especially for error tolerant application. Hence in the proposed adder, the overall area (cell count) and simulation time are reduced by 88 and 73 percent respectively. Various results of the proposed adder are shown and described. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=quantum%20cellular%20automata" title="quantum cellular automata">quantum cellular automata</a>, <a href="https://publications.waset.org/abstracts/search?q=carry%20look%20ahead%20adder" title=" carry look ahead adder"> carry look ahead adder</a>, <a href="https://publications.waset.org/abstracts/search?q=ripple%20carry%20adder" title=" ripple carry adder"> ripple carry adder</a>, <a href="https://publications.waset.org/abstracts/search?q=lossy%20application" title=" lossy application"> lossy application</a>, <a href="https://publications.waset.org/abstracts/search?q=majority%20gate" title=" majority gate"> majority gate</a>, <a href="https://publications.waset.org/abstracts/search?q=crossover" title=" crossover"> crossover</a> </p> <a href="https://publications.waset.org/abstracts/32396/design-of-speedy-scanty-adder-for-lossy-application-using-qca" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/32396.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">556</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7741</span> Leakage Current Analysis of FinFET Based 7T SRAM at 32nm Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Chhavi%20Saxena">Chhavi Saxena</a> </p> <p class="card-text"><strong>Abstract:</strong></p> FinFETs can be a replacement for bulk-CMOS transistors in many different designs. Its low leakage/standby power property makes FinFETs a desirable option for memory sub-systems. Memory modules are widely used in most digital and computer systems. Leakage power is very important in memory cells since most memory applications access only one or very few memory rows at a given time. As technology scales down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the 32nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs efficiency, called variable supply voltage schemes. In this paper, we’ve illustrated the design and implementation of FinFET based 4x4 SRAM cell array by means of one bit 7T SRAM. FinFET based 7T SRAM has been designed and analysis have been carried out for leakage current, dynamic power and delay. For the validation of our design approach, the output of FinFET SRAM array have been compared with standard CMOS SRAM and significant improvements are obtained in proposed model. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=FinFET" title="FinFET">FinFET</a>, <a href="https://publications.waset.org/abstracts/search?q=7T%20SRAM%20cell" title=" 7T SRAM cell"> 7T SRAM cell</a>, <a href="https://publications.waset.org/abstracts/search?q=leakage%20current" title=" leakage current"> leakage current</a>, <a href="https://publications.waset.org/abstracts/search?q=delay" title=" delay "> delay </a> </p> <a href="https://publications.waset.org/abstracts/16196/leakage-current-analysis-of-finfet-based-7t-sram-at-32nm-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/16196.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">455</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7740</span> Low Power CMOS Amplifier Design for Wearable Electrocardiogram Sensor</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ow%20Tze%20Weng">Ow Tze Weng</a>, <a href="https://publications.waset.org/abstracts/search?q=Suhaila%20Isaak"> Suhaila Isaak</a>, <a href="https://publications.waset.org/abstracts/search?q=Yusmeeraz%20Yusof"> Yusmeeraz Yusof</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The trend of health care screening devices in the world is increasingly towards the favor of portability and wearability, especially in the most common electrocardiogram (ECG) monitoring system. This is because these wearable screening devices are not restricting the patient’s freedom and daily activities. While the demand of low power and low cost biomedical system on chip (SoC) is increasing in exponential way, the front end ECG sensors are still suffering from flicker noise for low frequency cardiac signal acquisition, 50 Hz power line electromagnetic interference, and the large unstable input offsets due to the electrode-skin interface is not attached properly. In this paper, a high performance CMOS amplifier for ECG sensors that suitable for low power wearable cardiac screening is proposed. The amplifier adopts the highly stable folded cascode topology and later being implemented into RC feedback circuit for low frequency DC offset cancellation. By using 0.13 µm CMOS technology from Silterra, the simulation results show that this front end circuit can achieve a very low input referred noise of 1 pV/√Hz and high common mode rejection ratio (CMRR) of 174.05 dB. It also gives voltage gain of 75.45 dB with good power supply rejection ratio (PSSR) of 92.12 dB. The total power consumption is only 3 µW and thus suitable to be implemented with further signal processing and classification back end for low power biomedical SoC. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS" title="CMOS">CMOS</a>, <a href="https://publications.waset.org/abstracts/search?q=ECG" title=" ECG"> ECG</a>, <a href="https://publications.waset.org/abstracts/search?q=amplifier" title=" amplifier"> amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20power" title=" low power"> low power</a> </p> <a href="https://publications.waset.org/abstracts/78090/low-power-cmos-amplifier-design-for-wearable-electrocardiogram-sensor" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/78090.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">248</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7739</span> Microfabrication of Three-Dimensional SU-8 Structures Using Positive SPR Photoresist as a Sacrificial Layer for Integration of Microfluidic Components on Biosensors</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Su%20Yin%20Chiam">Su Yin Chiam</a>, <a href="https://publications.waset.org/abstracts/search?q=Qing%20Xin%20Zhang"> Qing Xin Zhang</a>, <a href="https://publications.waset.org/abstracts/search?q=Jaehoon%20Chung"> Jaehoon Chung</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) have obtained increased attention in the biosensor community because CMOS technology provides cost-effective and high-performance signal processing at a mass-production level. In order to supply biological samples and reagents effectively to the sensing elements, there are increasing demands for seamless integration of microfluidic components on the fabricated CMOS wafers by post-processing. Although the PDMS microfluidic channels replicated from separately prepared silicon mold can be typically aligned and bonded onto the CMOS wafers, it remains challenging owing the inherently limited aligning accuracy ( > ± 10 μm) between the two layers. Here we present a new post-processing method to create three-dimensional microfluidic components using two different polarities of photoresists, an epoxy-based negative SU-8 photoresist and positive SPR220-7 photoresist. The positive photoresist serves as a sacrificial layer and the negative photoresist was utilized as a structural material to generate three-dimensional structures. Because both photoresists are patterned using a standard photolithography technology, the dimensions of the structures can be effectively controlled as well as the alignment accuracy, moreover, is dramatically improved (< ± 2 μm) and appropriately can be adopted as an alternative post-processing method. To validate the proposed processing method, we applied this technique to build cell-trapping structures. The SU8 photoresist was mainly used to generate structures and the SPR photoresist was used as a sacrificial layer to generate sub-channel in the SU8, allowing fluid to pass through. The sub-channel generated by etching the sacrificial layer works as a cell-capturing site. The well-controlled dimensions enabled single-cell capturing on each site and high-accuracy alignment made cells trapped exactly on the sensing units of CMOS biosensors. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SU-8" title="SU-8">SU-8</a>, <a href="https://publications.waset.org/abstracts/search?q=microfluidic" title=" microfluidic"> microfluidic</a>, <a href="https://publications.waset.org/abstracts/search?q=MEMS" title=" MEMS"> MEMS</a>, <a href="https://publications.waset.org/abstracts/search?q=microfabrication" title=" microfabrication"> microfabrication</a> </p> <a href="https://publications.waset.org/abstracts/32017/microfabrication-of-three-dimensional-su-8-structures-using-positive-spr-photoresist-as-a-sacrificial-layer-for-integration-of-microfluidic-components-on-biosensors" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/32017.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">522</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7738</span> Design and Implementation of a 94 GHz CMOS Double-Balanced Up-Conversion Mixer for 94 GHz Imaging Radar Sensors</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yo-Sheng%20Lin">Yo-Sheng Lin</a>, <a href="https://publications.waset.org/abstracts/search?q=Run-Chi%20Liu"> Run-Chi Liu</a>, <a href="https://publications.waset.org/abstracts/search?q=Chien-Chu%20Ji"> Chien-Chu Ji</a>, <a href="https://publications.waset.org/abstracts/search?q=Chih-Chung%20Chen"> Chih-Chung Chen</a>, <a href="https://publications.waset.org/abstracts/search?q=Chien-Chin%20Wang"> Chien-Chin Wang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A W-band double-balanced mixer for direct up-conversion using standard 90 nm CMOS technology is reported. The mixer comprises an enhanced double-balanced Gilbert cell with PMOS negative resistance compensation for conversion gain (CG) enhancement and current injection for power consumption reduction and linearity improvement, a Marchand balun for converting the single LO input signal to differential signal, another Marchand balun for converting the differential RF output signal to single signal, and an output buffer amplifier for loading effect suppression, power consumption reduction and CG enhancement. The mixer consumes low power of 6.9 mW and achieves LO-port input reflection coefficient of -17.8~ -38.7 dB and RF-port input reflection coefficient of -16.8~ -27.9 dB for frequencies of 90~100 GHz. The mixer achieves maximum CG of 3.6 dB at 95 GHz, and CG of 2.1±1.5 dB for frequencies of 91.9~99.4 GHz. That is, the corresponding 3 dB CG bandwidth is 7.5 GHz. In addition, the mixer achieves LO-RF isolation of 36.8 dB at 94 GHz. To the authors’ knowledge, the CG, LO-RF isolation and power dissipation results are the best data ever reported for a 94 GHz CMOS/BiCMOS up-conversion mixer. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS" title="CMOS">CMOS</a>, <a href="https://publications.waset.org/abstracts/search?q=W-band" title=" W-band"> W-band</a>, <a href="https://publications.waset.org/abstracts/search?q=up-conversion%20mixer" title=" up-conversion mixer"> up-conversion mixer</a>, <a href="https://publications.waset.org/abstracts/search?q=conversion%20gain" title=" conversion gain"> conversion gain</a>, <a href="https://publications.waset.org/abstracts/search?q=negative%20resistance%20compensation" title=" negative resistance compensation"> negative resistance compensation</a>, <a href="https://publications.waset.org/abstracts/search?q=output%20buffer%20amplifier" title=" output buffer amplifier"> output buffer amplifier</a> </p> <a href="https://publications.waset.org/abstracts/32066/design-and-implementation-of-a-94-ghz-cmos-double-balanced-up-conversion-mixer-for-94-ghz-imaging-radar-sensors" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/32066.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">531</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7737</span> Design and Simulation of 3-Transistor Active Pixel Sensor Using MATLAB Simulink</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=H.%20Alheeh">H. Alheeh</a>, <a href="https://publications.waset.org/abstracts/search?q=M.%20Alameri"> M. Alameri</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Al%20Tarabsheh"> A. Al Tarabsheh</a> </p> <p class="card-text"><strong>Abstract:</strong></p> There has been a growing interest in CMOS-based sensors technology in cameras as they afford low-power, small-size, and cost-effective imaging systems. This article describes the CMOS image sensor pixel categories and presents the design and the simulation of the 3-Transistor (3T) Active Pixel Sensor (APS) in MATLAB/Simulink tool. The analysis investigates the conversion of the light into an electrical signal for a single pixel sensing circuit, which consists of a photodiode and three NMOS transistors. The paper also proposes three modes for the pixel operation; reset, integration, and readout modes. The simulations of the electrical signals for each of the studied modes of operation show how the output electrical signals are correlated to the input light intensities. The charging/discharging speed for the photodiodes is also investigated. The output voltage for different light intensities, including in dark case, is calculated and showed its inverse proportionality with the light intensity. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=APS" title="APS">APS</a>, <a href="https://publications.waset.org/abstracts/search?q=CMOS%20image%20sensor" title=" CMOS image sensor"> CMOS image sensor</a>, <a href="https://publications.waset.org/abstracts/search?q=light%20intensities%20photodiode" title=" light intensities photodiode"> light intensities photodiode</a>, <a href="https://publications.waset.org/abstracts/search?q=simulation" title=" simulation"> simulation</a> </p> <a href="https://publications.waset.org/abstracts/131973/design-and-simulation-of-3-transistor-active-pixel-sensor-using-matlab-simulink" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/131973.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">177</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7736</span> Dual-Rail Logic Unit in Double Pass Transistor Logic</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hamdi%20Belgacem">Hamdi Belgacem</a>, <a href="https://publications.waset.org/abstracts/search?q=Fradi%20Aymen"> Fradi Aymen</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper we present a low power, low cost differential logic unit (LU). The proposed LU receives dual-rail inputs and generates dual-rail outputs. The proposed circuit can be used in Arithmetic and Logic Units (ALU) of processor. It can be also dedicated for self-checking applications based on dual duplication code. Four logic functions as well as their inverses are implemented within a single Logic Unit. The hardware overhead for the implementation of the proposed LU is lower than the hardware overhead required for standard LU implemented with standard CMOS logic style. This new implementation is attractive as fewer transistors are required to implement important logic functions. The proposed differential logic unit can perform 8 Boolean logical operations by using only 16 transistors. Spice simulations using a 32 nm technology was utilized to evaluate the performance of the proposed circuit and to prove its acceptable electrical behaviour. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=differential%20logic%20unit" title="differential logic unit">differential logic unit</a>, <a href="https://publications.waset.org/abstracts/search?q=double%20pass%20transistor%20logic" title=" double pass transistor logic"> double pass transistor logic</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20power%20CMOS%20design" title=" low power CMOS design"> low power CMOS design</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20cost%20CMOS%20design" title=" low cost CMOS design"> low cost CMOS design</a> </p> <a href="https://publications.waset.org/abstracts/35814/dual-rail-logic-unit-in-double-pass-transistor-logic" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/35814.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">452</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7735</span> High Precision 65nm CMOS Rectifier for Energy Harvesting using Threshold Voltage Minimization in Telemedicine Embedded System</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hafez%20Fouad">Hafez Fouad</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Telemedicine applications have very low voltage which required High Precision Rectifier Design with high Sensitivity to operate at minimum input Voltage. In this work, we targeted 0.2V input voltage using 65 nm CMOS rectifier for Energy Harvesting Telemedicine application. The proposed rectifier which designed at 2.4GHz using two-stage structure found to perform in a better case where minimum operation voltage is lower than previous published paper and the rectifier can work at a wide range of low input voltage amplitude. The Performance Summary of Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2 V are 490.9 mV and 1.997 V, maximum VCE = 99.85 % and maximum PCE = 46.86 %. The Performance Summary of Differential drive CMOS rectifier with external bootstrapping circuit rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2V are 265.5 mV (0.265V) and 1.467 V respectively, maximum VCE = 93.9 % and maximum PCE= 15.8 %. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=energy%20harvesting" title="energy harvesting">energy harvesting</a>, <a href="https://publications.waset.org/abstracts/search?q=embedded%20system" title=" embedded system"> embedded system</a>, <a href="https://publications.waset.org/abstracts/search?q=IoT%20telemedicine%20system" title=" IoT telemedicine system"> IoT telemedicine system</a>, <a href="https://publications.waset.org/abstracts/search?q=threshold%20voltage%20minimization" title=" threshold voltage minimization"> threshold voltage minimization</a>, <a href="https://publications.waset.org/abstracts/search?q=differential%20drive%20cmos%20rectifier" title=" differential drive cmos rectifier"> differential drive cmos rectifier</a>, <a href="https://publications.waset.org/abstracts/search?q=full-wave%20fully%20gate%20cross-coupled%20rectifiers%20CMOS%20rectifier" title=" full-wave fully gate cross-coupled rectifiers CMOS rectifier"> full-wave fully gate cross-coupled rectifiers CMOS rectifier</a> </p> <a href="https://publications.waset.org/abstracts/150296/high-precision-65nm-cmos-rectifier-for-energy-harvesting-using-threshold-voltage-minimization-in-telemedicine-embedded-system" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/150296.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">162</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7734</span> 70% Ultra-Wide Tuning CMOS VCO Based on Magnetic Energy Adjustment</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Tai-Hsing%20Lee">Tai-Hsing Lee</a>, <a href="https://publications.waset.org/abstracts/search?q=Zhe-Wei%20Lin"> Zhe-Wei Lin</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper demonstrates an ultra-wide tuning VCO implemented by CMOS 0.18μm process technology. By employing the proposed technique of magnetic energy adjustment in the oscillator tank, our proposed VCO achieves a wide frequency tuning range of 69.46% from 0.9 GHz to 1.86 GHz. The phase noise at an operating frequency of 1.86 GHz is -110 dBc/Hz (Offset frequency=1MHz). Furthermore, it achieves an excellent FOMT of 190.03 dBc/Hz. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=VCO" title="VCO">VCO</a>, <a href="https://publications.waset.org/abstracts/search?q=Ultra-wide%20tuning" title=" Ultra-wide tuning"> Ultra-wide tuning</a>, <a href="https://publications.waset.org/abstracts/search?q=Frequency%20tuning%20range" title=" Frequency tuning range"> Frequency tuning range</a>, <a href="https://publications.waset.org/abstracts/search?q=phase%20noise" title=" phase noise"> phase noise</a>, <a href="https://publications.waset.org/abstracts/search?q=Magnetic%20energy%20adjustment" title=" Magnetic energy adjustment"> Magnetic energy adjustment</a> </p> <a href="https://publications.waset.org/abstracts/190304/70-ultra-wide-tuning-cmos-vco-based-on-magnetic-energy-adjustment" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/190304.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">39</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7733</span> A High Linear and Low Power with 71dB 35.1MHz/4.38GHz Variable Gain Amplifier in 180nm CMOS Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Sina%20Mahdavi">Sina Mahdavi</a>, <a href="https://publications.waset.org/abstracts/search?q=Faeze%20Noruzpur"> Faeze Noruzpur</a>, <a href="https://publications.waset.org/abstracts/search?q=Aysuda%20Noruzpur"> Aysuda Noruzpur</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper proposes a high linear, low power and wideband Variable Gain Amplifier (VGA) with a direct current (DC) gain range of -10.2dB to 60.7dB. By applying the proposed idea to the folded cascade amplifier, it is possible to achieve a 71dB DC gain, 35MHz (-3dB) bandwidth, accompanied by high linearity and low sensitivity as well. It is noteworthy that the proposed idea can be able to apply on every differential amplifier, too. Moreover, the total power consumption and unity gain bandwidth of the proposed VGA is 1.41mW with a power supply of 1.8 volts and 4.37GHz, respectively, and 0.8pF capacitor load is applied at the output nodes of the amplifier. Furthermore, the proposed structure is simulated in whole process corners and different temperatures in the region of -60 to +90 ºC. Simulations are performed for all corner conditions by HSPICE using the BSIM3 model of the 180nm CMOS technology and MATLAB software. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=variable%20gain%20amplifier" title="variable gain amplifier">variable gain amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20power" title=" low power"> low power</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20voltage" title=" low voltage"> low voltage</a>, <a href="https://publications.waset.org/abstracts/search?q=folded%20cascade" title=" folded cascade"> folded cascade</a>, <a href="https://publications.waset.org/abstracts/search?q=amplifier" title=" amplifier"> amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=DC%20gain" title=" DC gain"> DC gain</a> </p> <a href="https://publications.waset.org/abstracts/174867/a-high-linear-and-low-power-with-71db-351mhz438ghz-variable-gain-amplifier-in-180nm-cmos-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/174867.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">119</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7732</span> Low Power, Highly Linear, Wideband LNA in Wireless SOC</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Amir%20Mahdavi">Amir Mahdavi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper a highly linear CMOS low noise amplifier (LNA) for ultra-wideband (UWB) applications is proposed. The proposed LNA uses a linearization technique to improve second and third-order intercept points (IIP3). The linearity is cured by repealing the common-mode section of all intermodulation components from the cascade topology current with optimization of biasing current use symmetrical and asymmetrical circuits for biasing. Simulation results show that maximum gain and noise figure are 6.9dB and 3.03-4.1dB over a 3.1–10.6 GHz, respectively. Power consumption of the LNA core and IIP3 are 2.64 mW and +4.9dBm respectively. The wideband input impedance matching of LNA is obtained by employing a degenerating inductor (|S11|<-9.1 dB). The circuit proposed UWB LNA is implemented using 0.18 μm based CMOS technology. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=highly%20linear%20LNA" title="highly linear LNA">highly linear LNA</a>, <a href="https://publications.waset.org/abstracts/search?q=low-power%20LNA" title=" low-power LNA"> low-power LNA</a>, <a href="https://publications.waset.org/abstracts/search?q=optimal%20bias%20techniques" title=" optimal bias techniques"> optimal bias techniques</a> </p> <a href="https://publications.waset.org/abstracts/75554/low-power-highly-linear-wideband-lna-in-wireless-soc" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/75554.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">280</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7731</span> An 8-Bit, 100-MSPS Fully Dynamic SAR ADC for Ultra-High Speed Image Sensor</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=F.%20Rarbi">F. Rarbi</a>, <a href="https://publications.waset.org/abstracts/search?q=D.%20Dzahini"> D. Dzahini</a>, <a href="https://publications.waset.org/abstracts/search?q=W.%20Uhring"> W. Uhring</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, a dynamic and power efficient 8-bit and 100-MSPS Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is presented. The circuit uses a non-differential capacitive Digital-to-Analog (DAC) architecture segmented by 2. The prototype is produced in a commercial 65-nm 1P7M CMOS technology with 1.2-V supply voltage. The size of the core ADC is 208.6 x 103.6 µm<sup>2</sup>. The post-layout noise simulation results feature a SNR of 46.9 dB at Nyquist frequency, which means an effective number of bit (ENOB) of 7.5-b. The total power consumption of this SAR ADC is only 1.55 mW at 100-MSPS. It achieves then a figure of merit of 85.6 fJ/step. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS%20analog%20to%20digital%20converter" title="CMOS analog to digital converter">CMOS analog to digital converter</a>, <a href="https://publications.waset.org/abstracts/search?q=dynamic%20comparator" title=" dynamic comparator"> dynamic comparator</a>, <a href="https://publications.waset.org/abstracts/search?q=image%20sensor%20application" title=" image sensor application"> image sensor application</a>, <a href="https://publications.waset.org/abstracts/search?q=successive%20approximation%20register" title=" successive approximation register"> successive approximation register</a> </p> <a href="https://publications.waset.org/abstracts/75988/an-8-bit-100-msps-fully-dynamic-sar-adc-for-ultra-high-speed-image-sensor" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/75988.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">418</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7730</span> Analysis of Vertical Hall Effect Device Using Current-Mode</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Kim%20Jin%20Sup">Kim Jin Sup</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a vertical hall effect device using current-mode. Among different geometries that have been studied and simulated using COMSOL Multiphysics, optimized cross-shaped model displayed the best sensitivity. The cross-shaped model emerged as the optimum plate to fit the lowest noise and residual offset and the best sensitivity. The symmetrical cross-shaped hall plate is widely used because of its high sensitivity and immunity to alignment tolerances resulting from the fabrication process. The hall effect device has been designed using a 0.18-μm CMOS technology. The simulation uses the nominal bias current of 12μA. The applied magnetic field is from 0 mT to 20 mT. Simulation results achieved in COMSOL and validated with respect to the electrical behavior of equivalent circuit for Cadence. Simulation results of the one structure over the 13 available samples shows for the best geometry a current-mode sensitivity of 6.6 %/T at 20mT. Acknowledgment: This work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (No. R7117-16-0165, Development of Hall Effect Semiconductor for Smart Car and Device). <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=vertical%20hall%20device" title="vertical hall device">vertical hall device</a>, <a href="https://publications.waset.org/abstracts/search?q=current-mode" title=" current-mode"> current-mode</a>, <a href="https://publications.waset.org/abstracts/search?q=crossed-shaped%20model" title=" crossed-shaped model"> crossed-shaped model</a>, <a href="https://publications.waset.org/abstracts/search?q=CMOS%20technology" title=" CMOS technology"> CMOS technology</a> </p> <a href="https://publications.waset.org/abstracts/59413/analysis-of-vertical-hall-effect-device-using-current-mode" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/59413.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">292</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7729</span> Modeling and Simulation of a CMOS-Based Analog Function Generator</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Madina%20Hamiane">Madina Hamiane</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Modelling and simulation of an analogy function generator is presented based on a polynomial expansion model. The proposed function generator model is based on a 10th order polynomial approximation of any of the required functions. The polynomial approximations of these functions can then be implemented using basic CMOS circuit blocks. In this paper, a circuit model is proposed that can simultaneously generate many different mathematical functions. The circuit model is designed and simulated with HSPICE and its performance is demonstrated through the simulation of a number of non-linear functions. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=modelling%20and%20simulation" title="modelling and simulation">modelling and simulation</a>, <a href="https://publications.waset.org/abstracts/search?q=analog%20function%20generator" title=" analog function generator"> analog function generator</a>, <a href="https://publications.waset.org/abstracts/search?q=polynomial%20approximation" title=" polynomial approximation"> polynomial approximation</a>, <a href="https://publications.waset.org/abstracts/search?q=CMOS%20transistors" title=" CMOS transistors"> CMOS transistors</a> </p> <a href="https://publications.waset.org/abstracts/7108/modeling-and-simulation-of-a-cmos-based-analog-function-generator" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/7108.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">458</span> </span> </div> </div> <ul class="pagination"> <li class="page-item disabled"><span class="page-link">&lsaquo;</span></li> <li class="page-item active"><span class="page-link">1</span></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=CMOS%20technology&page=2">2</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=CMOS%20technology&page=3">3</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=CMOS%20technology&page=4">4</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=CMOS%20technology&page=5">5</a></li> <li class="page-item"><a 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