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href="https://cs.wikipedia.org/wiki/Pascal_(mikroarchitektura)" title="Pascal (mikroarchitektura) – Czech" lang="cs" hreflang="cs" data-title="Pascal (mikroarchitektura)" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/Pascal_(mikroarhitektuur)" title="Pascal (mikroarhitektuur) – Estonian" lang="et" hreflang="et" data-title="Pascal (mikroarhitektuur)" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Pascal_(microarquitectura)" title="Pascal (microarquitectura) – Spanish" lang="es" hreflang="es" data-title="Pascal (microarquitectura)" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Pascal_(microarchitecture)" title="Pascal (microarchitecture) – French" lang="fr" hreflang="fr" data-title="Pascal (microarchitecture)" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%ED%8C%8C%EC%8A%A4%EC%B9%BC_(%EB%A7%88%EC%9D%B4%ED%81%AC%EB%A1%9C%EC%95%84%ED%82%A4%ED%85%8D%EC%B2%98)" title="파스칼 (마이크로아키텍처) – Korean" lang="ko" hreflang="ko" data-title="파스칼 (마이크로아키텍처)" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Pascal_(microarchitettura)" title="Pascal (microarchitettura) – Italian" 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searchaux" style="display:none">GPU microarchitecture by Nvidia</div> <p class="mw-empty-elt"> </p> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">Pascal</caption><tbody><tr><td colspan="2" class="infobox-image"><span typeof="mw:File"><a href="/wiki/File:NVIDIA-GTX-1070-FoundersEdition-FL.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/62/NVIDIA-GTX-1070-FoundersEdition-FL.jpg/300px-NVIDIA-GTX-1070-FoundersEdition-FL.jpg" decoding="async" width="300" height="223" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/62/NVIDIA-GTX-1070-FoundersEdition-FL.jpg/450px-NVIDIA-GTX-1070-FoundersEdition-FL.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/62/NVIDIA-GTX-1070-FoundersEdition-FL.jpg/600px-NVIDIA-GTX-1070-FoundersEdition-FL.jpg 2x" data-file-width="4700" data-file-height="3500" /></a></span><div class="infobox-caption">A GTX 1070 Founders Edition graphics based on the Pascal architecture</div></td></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">May 27, 2016<span class="noprint">; 8 years ago</span><span style="display:none"> (<span class="bday dtstart published updated">2016-05-27</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data"><a href="/wiki/Nvidia" title="Nvidia">Nvidia</a></td></tr><tr><th scope="row" class="infobox-label">Manufactured by</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/TSMC" title="TSMC">TSMC</a></li><li><a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a></li></ul></div></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Fabrication process</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>TSMC <a href="/wiki/14_nm_process" title="14 nm process">16FF</a></li><li>Samsung <a href="/wiki/14_nm_process" title="14 nm process">14<span class="nowrap"> </span>nm</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Codename(s)</th><td class="infobox-data">GP10x</td></tr><tr><th colspan="2" class="infobox-header" style="font-size:105%;">Product Series</th></tr><tr><th scope="row" class="infobox-label">Desktop</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/GeForce_10_series" title="GeForce 10 series">GeForce GTX 10 series</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Professional/workstation</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/Quadro" title="Quadro">Quadro P</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Server/datacenter</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/Nvidia_Tesla" title="Nvidia Tesla">Tesla P4</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header" style="font-size:105%;">Specifications</th></tr><tr><th scope="row" class="infobox-label">L1 cache</th><td class="infobox-data">24<span class="nowrap"> </span>KB (per SM)</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">256<span class="nowrap"> </span>KB—4<span class="nowrap"> </span>MB</td></tr><tr><th scope="row" class="infobox-label">Memory support</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/GDDR5_SDRAM" title="GDDR5 SDRAM">GDDR5</a></li><li><a href="/wiki/GDDR5_SDRAM#GDDR5X" title="GDDR5 SDRAM">GDDR5X</a></li><li><a href="/wiki/High_Bandwidth_Memory#HBM_2" title="High Bandwidth Memory">HBM2</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> support</th><td class="infobox-data"><a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a></td></tr><tr><th colspan="2" class="infobox-header" style="font-size:105%;">Supported Graphics <a href="/wiki/API" title="API">APIs</a></th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/DirectX" title="DirectX">DirectX</a></th><td class="infobox-data"><a href="/wiki/DirectX#DirectX_12" title="DirectX">DirectX 12 (12.1)</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Direct3D" title="Direct3D">Direct3D</a></th><td class="infobox-data"><a href="/wiki/Direct3D#Direct3D_12" title="Direct3D">Direct3D 12.0</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/High-Level_Shader_Language" title="High-Level Shader Language">Shader Model</a></th><td class="infobox-data"><a href="/wiki/High-Level_Shader_Language" title="High-Level Shader Language">Shader Model 6.7</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/OpenCL" title="OpenCL">OpenCL</a></th><td class="infobox-data"><a href="/wiki/OpenCL#OpenCL_3.0" title="OpenCL">OpenCL 3.0</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/OpenGL" title="OpenGL">OpenGL</a></th><td class="infobox-data"><a href="/wiki/OpenGL#OpenGL_4.6" title="OpenGL">OpenGL 4.6</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CUDA" title="CUDA">CUDA</a></th><td class="infobox-data"><a href="/wiki/CUDA#Version_features_and_specifications" title="CUDA">Compute Capability 6.0</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Vulkan" title="Vulkan">Vulkan</a></th><td class="infobox-data"><a href="/wiki/Vulkan#Vulkan_1.3" title="Vulkan">Vulkan 1.3</a></td></tr><tr><th colspan="2" class="infobox-header" style="font-size:105%;">Media Engine</th></tr><tr><th scope="row" class="infobox-label">Encode codecs</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output .hlist dt::after{content:": "}.mw-parser-output .hlist dd::after,.mw-parser-output .hlist li::after{content:" · ";font-weight:bold}.mw-parser-output .hlist dd:last-child::after,.mw-parser-output .hlist dt:last-child::after,.mw-parser-output .hlist li:last-child::after{content:none}.mw-parser-output .hlist dd dd:first-child::before,.mw-parser-output .hlist dd dt:first-child::before,.mw-parser-output .hlist dd li:first-child::before,.mw-parser-output .hlist dt dd:first-child::before,.mw-parser-output .hlist dt dt:first-child::before,.mw-parser-output .hlist dt li:first-child::before,.mw-parser-output .hlist li dd:first-child::before,.mw-parser-output .hlist li dt:first-child::before,.mw-parser-output .hlist li li:first-child::before{content:" (";font-weight:normal}.mw-parser-output .hlist dd dd:last-child::after,.mw-parser-output .hlist dd dt:last-child::after,.mw-parser-output .hlist dd li:last-child::after,.mw-parser-output .hlist dt dd:last-child::after,.mw-parser-output .hlist dt dt:last-child::after,.mw-parser-output .hlist dt li:last-child::after,.mw-parser-output .hlist li dd:last-child::after,.mw-parser-output .hlist li dt:last-child::after,.mw-parser-output .hlist li li:last-child::after{content:")";font-weight:normal}.mw-parser-output .hlist ol{counter-reset:listitem}.mw-parser-output .hlist ol>li{counter-increment:listitem}.mw-parser-output .hlist ol>li::before{content:" "counter(listitem)"\a0 "}.mw-parser-output .hlist dd ol>li:first-child::before,.mw-parser-output .hlist dt ol>li:first-child::before,.mw-parser-output .hlist li ol>li:first-child::before{content:" ("counter(listitem)"\a0 "}</style><div class="hlist"><ul><li><a href="/wiki/Advanced_Video_Coding" title="Advanced Video Coding">H.264</a></li><li><a href="/wiki/High_Efficiency_Video_Coding" title="High Efficiency Video Coding">H.265</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Decode codecs</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><div class="hlist"><ul><li><a href="/wiki/Advanced_Video_Coding" title="Advanced Video Coding">H.264</a></li><li><a href="/wiki/High_Efficiency_Video_Coding" title="High Efficiency Video Coding">H.265</a></li><li><a href="/wiki/VP9" title="VP9">VP9</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Color bit-depth</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><div class="hlist"><ul><li>8-bit</li><li>10-bit</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Encoder(s) supported</th><td class="infobox-data"><a href="/wiki/NVENC" class="mw-redirect" title="NVENC">NVENC</a></td></tr><tr><th scope="row" class="infobox-label">Display outputs</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/DisplayPort#1.4" title="DisplayPort">DisplayPort 1.4a</a></li><li><a href="/wiki/HDMI#Version_2.0" title="HDMI">HDMI 2.0b</a></li><li><a href="/wiki/Digital_Visual_Interface" title="Digital Visual Interface">DVI</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header" style="font-size:105%;">History</th></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="/wiki/Maxwell_(microarchitecture)" title="Maxwell (microarchitecture)">Maxwell</a></td></tr><tr><th scope="row" class="infobox-label">Successor</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><span class="nowrap"><a href="/wiki/Turing_(microarchitecture)" title="Turing (microarchitecture)">Turing</a> (consumer)</span></li><li><span class="nowrap"><a href="/wiki/Volta_(microarchitecture)" title="Volta (microarchitecture)">Volta</a> (professional)</span></li></ul></div></td></tr></tbody></table> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Blaise_Pascal_Versailles.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/98/Blaise_Pascal_Versailles.JPG/220px-Blaise_Pascal_Versailles.JPG" decoding="async" width="220" height="262" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/98/Blaise_Pascal_Versailles.JPG/330px-Blaise_Pascal_Versailles.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/98/Blaise_Pascal_Versailles.JPG/440px-Blaise_Pascal_Versailles.JPG 2x" data-file-width="2365" data-file-height="2817" /></a><figcaption>Painting of Blaise Pascal, eponym of architecture</figcaption></figure> <p><b>Pascal</b> is the codename for a <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a> developed by <a href="/wiki/Nvidia" title="Nvidia">Nvidia</a>, as the successor to the <a href="/wiki/Maxwell_(microarchitecture)" title="Maxwell (microarchitecture)">Maxwell</a> architecture. The architecture was first introduced in April 2016 with the release of the Tesla P100 (GP100) on April 5, 2016, and is primarily used in the <a href="/wiki/GeForce_10_series" title="GeForce 10 series">GeForce 10 series</a>, starting with the GeForce GTX 1080 and GTX 1070 (both using the GP104 GPU), which were released on May 27, 2016, and June 10, 2016, respectively. Pascal was manufactured using <a href="/wiki/TSMC" title="TSMC">TSMC</a>'s <a href="/wiki/14_nm_process" title="14 nm process">16 nm</a> <a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a> process,<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> and later <a href="/wiki/Samsung" title="Samsung">Samsung</a>'s <a href="/wiki/14_nanometer" class="mw-redirect" title="14 nanometer">14<span class="nowrap"> </span>nm</a> FinFET process.<sup id="cite_ref-techpowerup2_2-0" class="reference"><a href="#cite_note-techpowerup2-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p>The architecture is named after the 17th century French mathematician and physicist, <a href="/wiki/Blaise_Pascal" title="Blaise Pascal">Blaise Pascal</a>. </p><p>In April 2019, Nvidia enabled a software implementation of <a href="/wiki/DirectX_Raytracing" title="DirectX Raytracing">DirectX Raytracing</a> on Pascal-based cards starting with the GTX 1060 6 GB, and in the <a href="/wiki/GeForce_16_series" title="GeForce 16 series">16 series</a> cards, a feature reserved to the Turing-based RTX series up to that point.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Details">Details</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Pascal_(microarchitecture)&action=edit&section=1" title="Edit section: Details"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Nvidia@16nm@Pascal@GP100@Tesla_P100@T_Taiwan_1912A1_PN9G70.S6W_GP100-897-A1_DSCx07_poly(photoshopped)@5x.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/5/5f/Nvidia%4016nm%40Pascal%40GP100%40Tesla_P100%40T_Taiwan_1912A1_PN9G70.S6W_GP100-897-A1_DSCx07_poly%28photoshopped%29%405x.jpg/220px-Nvidia%4016nm%40Pascal%40GP100%40Tesla_P100%40T_Taiwan_1912A1_PN9G70.S6W_GP100-897-A1_DSCx07_poly%28photoshopped%29%405x.jpg" decoding="async" width="220" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/5f/Nvidia%4016nm%40Pascal%40GP100%40Tesla_P100%40T_Taiwan_1912A1_PN9G70.S6W_GP100-897-A1_DSCx07_poly%28photoshopped%29%405x.jpg/330px-Nvidia%4016nm%40Pascal%40GP100%40Tesla_P100%40T_Taiwan_1912A1_PN9G70.S6W_GP100-897-A1_DSCx07_poly%28photoshopped%29%405x.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/5f/Nvidia%4016nm%40Pascal%40GP100%40Tesla_P100%40T_Taiwan_1912A1_PN9G70.S6W_GP100-897-A1_DSCx07_poly%28photoshopped%29%405x.jpg/440px-Nvidia%4016nm%40Pascal%40GP100%40Tesla_P100%40T_Taiwan_1912A1_PN9G70.S6W_GP100-897-A1_DSCx07_poly%28photoshopped%29%405x.jpg 2x" data-file-width="24083" data-file-height="19731" /></a><figcaption>Die shot of the GP100 GPU used in Nvidia Tesla P100 cards</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Nvidia@16nm@Pascal@GP102@GeForce_GTX_1080_Ti@A_TAIWAN_1653A1_PBFV81.C00_GP102-350-K1-A1_DSCx4_polysilicon@5x.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/0e/Nvidia%4016nm%40Pascal%40GP102%40GeForce_GTX_1080_Ti%40A_TAIWAN_1653A1_PBFV81.C00_GP102-350-K1-A1_DSCx4_polysilicon%405x.jpg/220px-Nvidia%4016nm%40Pascal%40GP102%40GeForce_GTX_1080_Ti%40A_TAIWAN_1653A1_PBFV81.C00_GP102-350-K1-A1_DSCx4_polysilicon%405x.jpg" decoding="async" width="220" height="177" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/0e/Nvidia%4016nm%40Pascal%40GP102%40GeForce_GTX_1080_Ti%40A_TAIWAN_1653A1_PBFV81.C00_GP102-350-K1-A1_DSCx4_polysilicon%405x.jpg/330px-Nvidia%4016nm%40Pascal%40GP102%40GeForce_GTX_1080_Ti%40A_TAIWAN_1653A1_PBFV81.C00_GP102-350-K1-A1_DSCx4_polysilicon%405x.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/0e/Nvidia%4016nm%40Pascal%40GP102%40GeForce_GTX_1080_Ti%40A_TAIWAN_1653A1_PBFV81.C00_GP102-350-K1-A1_DSCx4_polysilicon%405x.jpg/440px-Nvidia%4016nm%40Pascal%40GP102%40GeForce_GTX_1080_Ti%40A_TAIWAN_1653A1_PBFV81.C00_GP102-350-K1-A1_DSCx4_polysilicon%405x.jpg 2x" data-file-width="10993" data-file-height="8835" /></a><figcaption>Die shot of the GP102 GPU found inside GeForce GTX 1080 Ti cards</figcaption></figure> <figure typeof="mw:File/Thumb"><a href="/wiki/File:NVIDIA@16nm@Pascal@GP106@GeForce_GTX_1060@A_TAIWAN_1634A1_PAUS02.001_GP106-400-A1_Stack-DSC01157-DSC01189_-_ZS-DMap_(36138678331).jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/41/NVIDIA%4016nm%40Pascal%40GP106%40GeForce_GTX_1060%40A_TAIWAN_1634A1_PAUS02.001_GP106-400-A1_Stack-DSC01157-DSC01189_-_ZS-DMap_%2836138678331%29.jpg/150px-NVIDIA%4016nm%40Pascal%40GP106%40GeForce_GTX_1060%40A_TAIWAN_1634A1_PAUS02.001_GP106-400-A1_Stack-DSC01157-DSC01189_-_ZS-DMap_%2836138678331%29.jpg" decoding="async" width="150" height="230" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/41/NVIDIA%4016nm%40Pascal%40GP106%40GeForce_GTX_1060%40A_TAIWAN_1634A1_PAUS02.001_GP106-400-A1_Stack-DSC01157-DSC01189_-_ZS-DMap_%2836138678331%29.jpg/225px-NVIDIA%4016nm%40Pascal%40GP106%40GeForce_GTX_1060%40A_TAIWAN_1634A1_PAUS02.001_GP106-400-A1_Stack-DSC01157-DSC01189_-_ZS-DMap_%2836138678331%29.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/41/NVIDIA%4016nm%40Pascal%40GP106%40GeForce_GTX_1060%40A_TAIWAN_1634A1_PAUS02.001_GP106-400-A1_Stack-DSC01157-DSC01189_-_ZS-DMap_%2836138678331%29.jpg/300px-NVIDIA%4016nm%40Pascal%40GP106%40GeForce_GTX_1060%40A_TAIWAN_1634A1_PAUS02.001_GP106-400-A1_Stack-DSC01157-DSC01189_-_ZS-DMap_%2836138678331%29.jpg 2x" data-file-width="3361" data-file-height="5155" /></a><figcaption>Die shot of the GP106 GPU found inside GTX 1060 cards</figcaption></figure> <p>In March 2014, Nvidia announced that the successor to <a href="/wiki/Maxwell_(microarchitecture)" title="Maxwell (microarchitecture)">Maxwell</a> would be the Pascal microarchitecture; announced on May 6, 2016, and released on May 27 of the same year. The Tesla P100 (GP100 chip) has a different version of the Pascal architecture compared to the GTX GPUs (GP104 chip). The <a href="/wiki/Shader" title="Shader">shader units</a> in GP104 have a <a href="/wiki/Maxwell_(microarchitecture)" title="Maxwell (microarchitecture)">Maxwell</a>-like design.<sup id="cite_ref-GTX1080WhitePaper_5-0" class="reference"><a href="#cite_note-GTX1080WhitePaper-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p><p>Architectural improvements of the GP100 architecture include the following:<sup id="cite_ref-nvidia-blog-20140325_6-0" class="reference"><a href="#cite_note-nvidia-blog-20140325-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p> <ul><li>In Pascal, a SM (streaming multiprocessor) consists of between 64-128 CUDA cores, depending on if it is GP100 or GP104. <a href="/wiki/Maxwell_(microarchitecture)" title="Maxwell (microarchitecture)">Maxwell</a> contained 128 CUDA cores per SM; Kepler had 192, Fermi 32 and Tesla 8. The GP100 SM is partitioned into two processing blocks, each having 32 single-precision CUDA cores, an instruction buffer, a warp scheduler, 2 texture mapping units and 2 dispatch units.</li> <li><a href="/wiki/CUDA" title="CUDA">CUDA</a> Compute Capability 6.0.</li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a> 2 — some cards feature 16 GiB HBM2 in four stacks with a total bus width of 4096 bits and a memory bandwidth of 720 GB/s.</li> <li>Unified memory — a memory architecture where the CPU and GPU can access both main system memory and memory on the graphics card with the help of a technology called "Page Migration Engine".</li> <li><a href="/wiki/NVLink" title="NVLink">NVLink</a> — a high-bandwidth bus between the CPU and GPU, and between multiple GPUs. Allows much higher transfer speeds than those achievable by using PCI Express; estimated to provide between 80 and 200 GB/s.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup></li> <li>16-bit (<a href="/wiki/Half-precision_floating-point_format" title="Half-precision floating-point format">FP16</a>) floating-point operations (colloquially "half precision") can be executed at twice the rate of 32-bit floating-point operations ("single precision")<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> and 64-bit floating-point operations (colloquially "double precision") executed at half the rate of 32-bit floating point operations.<sup id="cite_ref-anandtech_pascal1_12-0" class="reference"><a href="#cite_note-anandtech_pascal1-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup></li> <li>More registers — twice the amount of registers per CUDA core compared to Maxwell.</li> <li>More shared memory.</li> <li>Dynamic load balancing scheduling system.<sup id="cite_ref-RyanSmithDynamicScheduling_13-0" class="reference"><a href="#cite_note-RyanSmithDynamicScheduling-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> This allows the scheduler to dynamically adjust the amount of the GPU assigned to multiple tasks, ensuring that the GPU remains saturated with work except when there is no more work that can safely be distributed to distribute.<sup id="cite_ref-RyanSmithDynamicScheduling_13-1" class="reference"><a href="#cite_note-RyanSmithDynamicScheduling-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> Nvidia therefore has safely enabled asynchronous compute in Pascal's driver.<sup id="cite_ref-RyanSmithDynamicScheduling_13-2" class="reference"><a href="#cite_note-RyanSmithDynamicScheduling-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup></li> <li>Instruction-level and thread-level preemption.<sup id="cite_ref-RyanSmithPreemption_14-0" class="reference"><a href="#cite_note-RyanSmithPreemption-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></li></ul> <p>Architectural improvements of the GP104 architecture include the following:<sup id="cite_ref-GTX1080WhitePaper_5-1" class="reference"><a href="#cite_note-GTX1080WhitePaper-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p> <ul><li>CUDA Compute Capability 6.1.</li> <li><a href="/wiki/GDDR5X#GDDR5X" class="mw-redirect" title="GDDR5X">GDDR5X</a> — new memory standard supporting 10Gbit/s data rates, updated memory controller.<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></li> <li>Simultaneous Multi-Projection - generating multiple projections of a single geometry stream, as it enters the SMP engine from upstream shader stages.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a> 1.4, <a href="/wiki/HDMI" title="HDMI">HDMI</a> 2.0b.</li> <li>Fourth generation Delta Color Compression.</li> <li>Enhanced SLI Interface — SLI interface with higher bandwidth compared to the previous versions.</li> <li><a href="/wiki/Nvidia_PureVideo" title="Nvidia PureVideo">PureVideo</a> Feature Set H hardware video decoding HEVC Main10 (10-bit), Main12 (12-bit) and VP9 hardware decoding.</li> <li><a href="/wiki/High-bandwidth_Digital_Content_Protection" title="High-bandwidth Digital Content Protection">HDCP</a> 2.2 support for 4K DRM protected content playback and streaming (Maxwell GM200 and GM204 lack HDCP 2.2 support, GM206 supports HDCP 2.2).<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Nvidia_NVENC" title="Nvidia NVENC">NVENC</a> HEVC Main10 10bit hardware encoding.</li> <li>GPU Boost 3.0.</li> <li>Instruction-level preemption.<sup id="cite_ref-RyanSmithPreemption_14-1" class="reference"><a href="#cite_note-RyanSmithPreemption-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> In graphics tasks, the driver restricts preemption to the pixel-level, because pixel tasks typically finish quickly and the overhead costs of doing pixel-level preemption are lower than instruction-level preemption (which is expensive).<sup id="cite_ref-RyanSmithPreemption_14-2" class="reference"><a href="#cite_note-RyanSmithPreemption-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> Compute tasks get thread-level or instruction-level preemption,<sup id="cite_ref-RyanSmithPreemption_14-3" class="reference"><a href="#cite_note-RyanSmithPreemption-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> because they can take longer times to finish and there are no guarantees on when a compute task finishes. Therefore the driver enables the expensive instruction-level preemption for these tasks.<sup id="cite_ref-RyanSmithPreemption_14-4" class="reference"><a href="#cite_note-RyanSmithPreemption-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading2"><h2 id="Overview"><span class="anchor" id="SMP"></span> Overview</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Pascal_(microarchitecture)&action=edit&section=2" title="Edit section: Overview"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Graphics_Processor_Cluster">Graphics Processor Cluster</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Pascal_(microarchitecture)&action=edit&section=3" title="Edit section: Graphics Processor Cluster"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A chip is partitioned into Graphics Processor Clusters (GPCs). For the GP104 chips, a GPC encompasses 5 SMs. </p> <div class="mw-heading mw-heading3"><h3 id="Streaming_Multiprocessor_"Pascal""><span id="Streaming_Multiprocessor_.22Pascal.22"></span>Streaming Multiprocessor "Pascal"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Pascal_(microarchitecture)&action=edit&section=4" title="Edit section: Streaming Multiprocessor "Pascal""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A "Streaming Multiprocessor" is analogous to AMD's <a href="/wiki/Shader_processing_units" class="mw-redirect" title="Shader processing units">Compute Unit</a>. An SM encompasses 128 single-precision ALUs ("CUDA cores") on GP104 chips and 64 single-precision ALUs on GP100 chips. While all CU versions consist of 64 shader processors (i.e. 4 SIMD Vector Units, each 16 lanes wide), Nvidia experimented with very different numbers of CUDA cores: </p> <ul><li>On <a href="/wiki/Tesla_(microarchitecture)" title="Tesla (microarchitecture)">Tesla</a>, 1 SM combines 8 <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">single-precision (FP32)</a> shader processors</li> <li>On <a href="/wiki/Fermi_(microarchitecture)" title="Fermi (microarchitecture)">Fermi</a>, 1 SM combines 32 single-precision (FP32) shader processors</li> <li>On <a href="/wiki/Kepler_(microarchitecture)" title="Kepler (microarchitecture)">Kepler</a>, 1 SM combines 192 single-precision (FP32) shader processors and 64 double-precision (FP64) units (on GK110 GPUs)</li> <li>On <a href="/wiki/Maxwell_(microarchitecture)" title="Maxwell (microarchitecture)">Maxwell</a>, 1 SM combines 128 single-precision (FP32) shader processors</li> <li>On Pascal, it depends: <ul><li>On GP100, 1 SM combines 64 single-precision (FP32) shader processors and also 32 <a href="/wiki/Double-precision_floating-point_format" title="Double-precision floating-point format">double-precision (FP64)</a> providing a 2:1 ratio of single- to double-precision throughput. The GP100 uses more flexible FP32 cores that are able to process one single-precision or two half-precision numbers in a two-element vector.<sup id="cite_ref-RyanSmithPrecision_18-0" class="reference"><a href="#cite_note-RyanSmithPrecision-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> This is intended to better serve <a href="/wiki/Machine_learning" title="Machine learning">machine learning</a> tasks.</li> <li>On GP104, 1 SM combines 128 single-precision ALUs, 4 double-precision ALUs (providing a 32:1 ratio), and one half-precision ALU which contains a vector of two half-precision floats which can execute the same instruction on both floats, providing a 64:1 ratio if the same instruction is used on both elements.</li></ul></li></ul> <div class="mw-heading mw-heading3"><h3 id="Polymorph-Engine_4.0">Polymorph-Engine 4.0</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Pascal_(microarchitecture)&action=edit&section=5" title="Edit section: Polymorph-Engine 4.0"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Polymorph Engine version 4.0 is the unit responsible for <a href="/wiki/Tessellation_(computer_graphics)" title="Tessellation (computer graphics)">Tessellation</a>. It corresponds functionally with AMD's <a href="/wiki/Graphics_Core_Next#Geometric_processor" title="Graphics Core Next">Geometric Processor</a>. It has been moved from the shader module to the TPC to allow one Polymorph engine to feed multiple SMs within the TPC.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Chips">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Pascal_(microarchitecture)&action=edit&section=6" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:NVidia_1080_Ti_reference_PCB_front.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3e/NVidia_1080_Ti_reference_PCB_front.jpg/220px-NVidia_1080_Ti_reference_PCB_front.jpg" decoding="async" width="220" height="102" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3e/NVidia_1080_Ti_reference_PCB_front.jpg/330px-NVidia_1080_Ti_reference_PCB_front.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3e/NVidia_1080_Ti_reference_PCB_front.jpg/440px-NVidia_1080_Ti_reference_PCB_front.jpg 2x" data-file-width="13497" data-file-height="6259" /></a><figcaption>GTX 1080 Ti PCB and die</figcaption></figure> <ul><li>GP100: Nvidia's Tesla P100 GPU accelerator is targeted at <a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a> applications such as FP64 double precision compute and deep learning training that uses FP16. It uses <a href="/wiki/HBM_2" class="mw-redirect" title="HBM 2">HBM2 memory</a>.<sup id="cite_ref-InsidePascal_20-0" class="reference"><a href="#cite_note-InsidePascal-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> Quadro GP100 also uses the GP100 GPU.</li> <li>GP102: This GPU is used in the Titan Xp,<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> Titan X Pascal<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> and the GeForce GTX 1080 Ti. It is also used in the Quadro P6000<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> & Tesla P40.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup></li> <li>GP104: This GPU is used in the GeForce GTX 1070, GTX 1070 Ti, GTX 1080, and some GTX 1060 6 GB's. The GTX 1070 has 15/20 and the GTX 1070 Ti has 19/20 of its SMs enabled; both utilize GDDR5 memory. The GTX 1080 is a fully unlocked chip and uses GDDR5X memory. Some GTX 1060 6 GB's use GP104 with 10/20 SMs enabled and GDDR5X memory.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> It is also used in the Quadro P5000, Quadro P4000, Quadro P3200 (mobile applications) and Tesla P4.</li> <li>GP106: This GPU is used in the GeForce GTX 1060 with GDDR5<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> memory.<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> It is also used in the Quadro P2000.</li> <li>GP107: This GPU is used in the GeForce GTX 1050 and 1050 Ti. It is also used in the Quadro P1000, Quadro P600, Quadro P620 & Quadro P400.</li> <li>GP108: This GPU is used in the GeForce GT 1010 and GeForce GT 1030.</li></ul> <table class="wikitable" style="text-align: right;"> <caption>Comparison table of some Kepler, Maxwell, and Pascal chips </caption> <tbody><tr> <th></th> <th>GK104</th> <th>GK110</th> <th>GM204 (GTX 970)</th> <th>GM204 (GTX 980)</th> <th>GM200</th> <th>GP104</th> <th>GP100 </th></tr> <tr> <td>Dedicated texture cache per SM</td> <td>48 KiB</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td>Texture (graphics or compute) or read-only data (compute only) cache per SM</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td>48 KiB<sup id="cite_ref-GK110_29-0" class="reference"><a href="#cite_note-GK110-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td rowspan="3">Programmer-selectable shared memory/L1 partitions per SM</td> <td>48 KiB shared memory + 16 KiB L1 cache (default)<sup id="cite_ref-CudaCProgrammingGuide_30-0" class="reference"><a href="#cite_note-CudaCProgrammingGuide-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></td> <td>48 KiB shared memory + 16 KiB L1 cache (default)<sup id="cite_ref-CudaCProgrammingGuide_30-1" class="reference"><a href="#cite_note-CudaCProgrammingGuide-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td>32 KiB shared memory + 32 KiB L1 cache<sup id="cite_ref-CudaCProgrammingGuide_30-2" class="reference"><a href="#cite_note-CudaCProgrammingGuide-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></td> <td>32 KiB shared memory + 32 KiB L1 cache<sup id="cite_ref-CudaCProgrammingGuide_30-3" class="reference"><a href="#cite_note-CudaCProgrammingGuide-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>16 KiB shared memory + 48 KiB L1 cache<sup id="cite_ref-CudaCProgrammingGuide_30-4" class="reference"><a href="#cite_note-CudaCProgrammingGuide-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></td> <td>16 KiB shared memory + 48 KiB L1 cache<sup id="cite_ref-CudaCProgrammingGuide_30-5" class="reference"><a href="#cite_note-CudaCProgrammingGuide-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>Unified L1 cache/texture cache per SM</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td>48 KiB<sup id="cite_ref-hardware.fr_31-0" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>48 KiB<sup id="cite_ref-hardware.fr_31-1" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>48 KiB<sup id="cite_ref-hardware.fr_31-2" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>48 KiB<sup id="cite_ref-hardware.fr_31-3" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>24 KiB<sup id="cite_ref-hardware.fr_31-4" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>Dedicated shared memory per SM</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td>96 KiB<sup id="cite_ref-hardware.fr_31-5" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>96 KiB<sup id="cite_ref-hardware.fr_31-6" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>96 KiB<sup id="cite_ref-hardware.fr_31-7" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>96 KiB<sup id="cite_ref-hardware.fr_31-8" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>64 KiB<sup id="cite_ref-hardware.fr_31-9" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>L2 cache per chip</td> <td>512 KiB<sup id="cite_ref-hardware.fr_31-10" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>1536 KiB<sup id="cite_ref-hardware.fr_31-11" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>1792 KiB<sup id="cite_ref-GTX970FraudCorrections_32-0" class="reference"><a href="#cite_note-GTX970FraudCorrections-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup></td> <td>2048 KiB<sup id="cite_ref-GTX970FraudCorrections_32-1" class="reference"><a href="#cite_note-GTX970FraudCorrections-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup></td> <td>3072 KiB<sup id="cite_ref-hardware.fr_31-12" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>2048 KiB<sup id="cite_ref-hardware.fr_31-13" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></td> <td>4096 KiB<sup id="cite_ref-hardware.fr_31-14" class="reference"><a href="#cite_note-hardware.fr-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Performance">Performance</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Pascal_(microarchitecture)&action=edit&section=7" title="Edit section: Performance"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The theoretical single-precision processing power of a Pascal GPU in <a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a> is computed as 2 × operations per FMA instruction per CUDA core per cycle × number of CUDA cores × core clock speed (in GHz). </p><p>The theoretical double-precision processing power of a Pascal GPU is 1/2 of the single precision performance on Nvidia GP100, and 1/32 of Nvidia GP102, GP104, GP106, GP107 & GP108. </p><p>The theoretical half-precision processing power of a Pascal GPU is 2× of the single precision performance on GP100<sup id="cite_ref-anandtech_pascal1_12-1" class="reference"><a href="#cite_note-anandtech_pascal1-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> and 1/64 on GP104, GP106, GP107 & GP108.<sup id="cite_ref-RyanSmithPrecision_18-1" class="reference"><a href="#cite_note-RyanSmithPrecision-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Successor">Successor</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Pascal_(microarchitecture)&action=edit&section=8" title="Edit section: Successor"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Pascal architecture was succeeded in 2017 by <a href="/wiki/Volta_(microarchitecture)" title="Volta (microarchitecture)">Volta</a> in the <a href="/wiki/High_Performance_Computing" class="mw-redirect" title="High Performance Computing">HPC</a>, <a href="/wiki/Cloud_computing" title="Cloud computing">cloud computing</a>, and <a href="/wiki/Self-driving_car" title="Self-driving car">self-driving car</a> markets, and in 2018 by <a href="/wiki/Turing_(microarchitecture)" title="Turing (microarchitecture)">Turing</a> in the consumer and business market.<sup id="cite_ref-Techradar_33-0" class="reference"><a href="#cite_note-Techradar-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="P100_accelerator_and_DGX-1">P100 accelerator and DGX-1</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Pascal_(microarchitecture)&action=edit&section=9" title="Edit section: P100 accelerator and DGX-1"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Comparison of accelerators used in DGX:<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> </p> <table> <tbody><tr><td></td></tr></tbody></table> <div style="overflow-x:auto; white-space:nowrap;"> <table class="wikitable" style="margin:0;"> <tbody><tr> <th>Model</th> <th>Architecture</th> <th>Socket</th> <th>FP32<br />CUDA<br />cores</th> <th>FP64 cores<br />(excl. tensor)</th> <th>Mixed<br />INT32/FP32<br />cores</th> <th>INT32<br />cores</th> <th>Boost<br />clock</th> <th>Memory<br />clock</th> <th>Memory<br />bus width</th> <th>Memory<br />bandwidth</th> <th>VRAM</th> <th>Single<br />precision<br />(FP32)</th> <th>Double<br />precision<br />(FP64)</th> <th>INT8<br />(non-tensor)</th> <th>INT8<br />dense tensor</th> <th>INT32</th> <th>FP4<br /> dense tensor</th> <th>FP16</th> <th>FP16<br />dense tensor</th> <th>bfloat16<br />dense tensor</th> <th>TensorFloat-32<br />(TF32)<br />dense tensor</th> <th>FP64<br />dense tensor</th> <th>Interconnect<br />(NVLink)</th> <th>GPU</th> <th>L1 Cache</th> <th>L2 Cache</th> <th>TDP</th> <th>Die size</th> <th>Transistor<br />count</th> <th>Process</th> <th>Launched </th></tr> <tr> <th>B200 </th> <td><a href="/wiki/Blackwell_(microarchitecture)" title="Blackwell (microarchitecture)">Blackwell</a></td> <td>SXM6</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>8 Gbit/s HBM3e</td> <td>8192-bit</td> <td>8 TB/sec</td> <td>192 GB HBM3e</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>4.5 POPS</td> <td>N/A</td> <td>9 PFLOPS</td> <td>N/A</td> <td>2.25 PFLOPS</td> <td>2.25 PFLOPS</td> <td>1.2 PFLOPS</td> <td>40 TFLOPS</td> <td>1.8 TB/sec</td> <td>GB100</td> <td>N/A</td> <td>N/A</td> <td>1000 W</td> <td>N/A</td> <td>208 B</td> <td>TSMC 4NP</td> <td rowspan="2">Q4 2024 (expected) </td></tr> <tr> <th>B100 </th> <td><a href="/wiki/Blackwell_(microarchitecture)" title="Blackwell (microarchitecture)">Blackwell</a></td> <td>SXM6</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>8 Gbit/s HBM3e</td> <td>8192-bit</td> <td>8 TB/sec</td> <td>192 GB HBM3e</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>3.5 POPS</td> <td>N/A</td> <td>7 PFLOPS</td> <td>N/A</td> <td>1.98 PFLOPS</td> <td>1.98 PFLOPS</td> <td>989 TFLOPS</td> <td>30 TFLOPS</td> <td>1.8 TB/sec</td> <td>GB100</td> <td>N/A</td> <td>N/A</td> <td>700 W</td> <td>N/A</td> <td>208 B</td> <td>TSMC 4NP </td></tr> <tr> <th>H200 </th> <td><a href="/wiki/Hopper_(microarchitecture)" title="Hopper (microarchitecture)">Hopper</a></td> <td>SXM5</td> <td>16896</td> <td>4608</td> <td>16896</td> <td>N/A</td> <td>1980 MHz</td> <td>6.3 Gbit/s HBM3e</td> <td>6144-bit</td> <td>4.8 TB/sec</td> <td>141 GB HBM3e</td> <td>67 TFLOPS</td> <td>34 TFLOPS</td> <td>N/A</td> <td>1.98 POPS</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>990 TFLOPS</td> <td>990 TFLOPS</td> <td>495 TFLOPS</td> <td>67 TFLOPS</td> <td>900 GB/sec</td> <td>GH100</td> <td>25344 KB (192 KB × 132)</td> <td>51200 KB</td> <td>1000 W</td> <td>814 mm<sup>2</sup></td> <td>80 B</td> <td>TSMC 4N</td> <td>Q3 2023 </td></tr> <tr> <th>H100 </th> <td><a href="/wiki/Hopper_(microarchitecture)" title="Hopper (microarchitecture)">Hopper</a></td> <td>SXM5</td> <td>16896</td> <td>4608</td> <td>16896</td> <td>N/A</td> <td>1980 MHz</td> <td>5.2 Gbit/s HBM3</td> <td>5120-bit</td> <td>3.35 TB/sec</td> <td>80 GB HBM3</td> <td>67 TFLOPS</td> <td>34 TFLOPS</td> <td>N/A</td> <td>1.98 POPS</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>990 TFLOPS</td> <td>990 TFLOPS</td> <td>495 TFLOPS</td> <td>67 TFLOPS</td> <td>900 GB/sec</td> <td>GH100</td> <td>25344 KB (192 KB × 132)</td> <td>51200 KB</td> <td>700 W</td> <td>814 mm<sup>2</sup></td> <td>80 B</td> <td>TSMC 4N</td> <td>Q3 2022 </td></tr> <tr> <th>A100 80GB </th> <td><a href="/wiki/Ampere_(microarchitecture)" title="Ampere (microarchitecture)">Ampere</a></td> <td>SXM4</td> <td>6912</td> <td>3456</td> <td>6912</td> <td>N/A</td> <td>1410 MHz</td> <td>3.2 Gbit/s HBM2e</td> <td>5120-bit</td> <td>1.52 TB/sec</td> <td>80 GB HBM2e</td> <td>19.5 TFLOPS</td> <td>9.7 TFLOPS</td> <td>N/A</td> <td>624 TOPS</td> <td>19.5 TOPS</td> <td>N/A</td> <td>78 TFLOPS</td> <td>312 TFLOPS</td> <td>312 TFLOPS</td> <td>156 TFLOPS</td> <td>19.5 TFLOPS</td> <td>600 GB/sec</td> <td>GA100</td> <td>20736 KB (192 KB × 108)</td> <td>40960 KB</td> <td>400 W</td> <td>826 mm<sup>2</sup></td> <td>54.2 B</td> <td>TSMC N7</td> <td rowspan="2">Q1 2020 </td></tr> <tr> <th>A100 40GB </th> <td><a href="/wiki/Ampere_(microarchitecture)" title="Ampere (microarchitecture)">Ampere</a></td> <td>SXM4</td> <td>6912</td> <td>3456</td> <td>6912</td> <td>N/A</td> <td>1410 MHz</td> <td>2.4 Gbit/s HBM2</td> <td>5120-bit</td> <td>1.52 TB/sec</td> <td>40 GB HBM2</td> <td>19.5 TFLOPS</td> <td>9.7 TFLOPS</td> <td>N/A</td> <td>624 TOPS</td> <td>19.5 TOPS</td> <td>N/A</td> <td>78 TFLOPS</td> <td>312 TFLOPS</td> <td>312 TFLOPS</td> <td>156 TFLOPS</td> <td>19.5 TFLOPS</td> <td>600 GB/sec</td> <td>GA100</td> <td>20736 KB (192 KB × 108)</td> <td>40960 KB</td> <td>400 W</td> <td>826 mm<sup>2</sup></td> <td>54.2 B</td> <td>TSMC N7 </td></tr> <tr> <th>V100 32GB </th> <td><a href="/wiki/Volta_(microarchitecture)" title="Volta (microarchitecture)">Volta</a></td> <td>SXM3</td> <td>5120</td> <td>2560</td> <td>N/A</td> <td>5120</td> <td>1530 MHz</td> <td>1.75 Gbit/s HBM2</td> <td>4096-bit</td> <td>900 GB/sec</td> <td>32 GB HBM2</td> <td>15.7 TFLOPS</td> <td>7.8 TFLOPS</td> <td>62 TOPS</td> <td>N/A</td> <td>15.7 TOPS</td> <td>N/A</td> <td>31.4 TFLOPS</td> <td>125 TFLOPS</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>300 GB/sec</td> <td>GV100</td> <td>10240 KB (128 KB × 80)</td> <td>6144 KB</td> <td>350 W</td> <td>815 mm<sup>2</sup></td> <td>21.1 B</td> <td>TSMC 12FFN</td> <td rowspan="2">Q3 2017 </td></tr> <tr> <th>V100 16GB </th> <td><a href="/wiki/Volta_(microarchitecture)" title="Volta (microarchitecture)">Volta</a></td> <td>SXM2</td> <td>5120</td> <td>2560</td> <td>N/A</td> <td>5120</td> <td>1530 MHz</td> <td>1.75 Gbit/s HBM2</td> <td>4096-bit</td> <td>900 GB/sec</td> <td>16 GB HBM2</td> <td>15.7 TFLOPS</td> <td>7.8 TFLOPS</td> <td>62 TOPS</td> <td>N/A</td> <td>15.7 TOPS</td> <td>N/A</td> <td>31.4 TFLOPS</td> <td>125 TFLOPS</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>300 GB/sec</td> <td>GV100</td> <td>10240 KB (128 KB × 80)</td> <td>6144 KB</td> <td>300 W</td> <td>815 mm<sup>2</sup></td> <td>21.1 B</td> <td>TSMC 12FFN </td></tr> <tr> <th>P100 </th> <td><a class="mw-selflink selflink">Pascal</a></td> <td>SXM/SXM2</td> <td>N/A</td> <td>1792</td> <td>3584</td> <td>N/A</td> <td>1480 MHz</td> <td>1.4 Gbit/s HBM2</td> <td>4096-bit</td> <td>720 GB/sec</td> <td>16 GB HBM2</td> <td>10.6 TFLOPS</td> <td>5.3 TFLOPS</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>21.2 TFLOPS</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>N/A</td> <td>160 GB/sec</td> <td>GP100</td> <td>1344 KB (24 KB × 56)</td> <td>4096 KB</td> <td>300 W</td> <td>610 mm<sup>2</sup></td> <td>15.3 B</td> <td>TSMC 16FF+</td> <td>Q2 2016 </td></tr></tbody></table></div><div style="clear:both"></div> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Pascal_(microarchitecture)&action=edit&section=10" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/List_of_eponyms_of_Nvidia_GPU_microarchitectures" title="List of eponyms of Nvidia GPU microarchitectures">List of eponyms of Nvidia GPU microarchitectures</a></li> <li><a href="/wiki/List_of_Nvidia_graphics_processing_units" title="List of Nvidia graphics processing units">List of Nvidia graphics processing units</a></li> <li><a href="/wiki/Nvidia_NVDEC" title="Nvidia NVDEC">Nvidia NVDEC</a></li> <li><a href="/wiki/Nvidia_NVENC" title="Nvidia NVENC">Nvidia NVENC</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Pascal_(microarchitecture)&action=edit&section=11" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation news cs1"><a rel="nofollow" class="external text" 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AnandTech.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=NVIDIA+Ampere+Unleashed%3A+NVIDIA+Announces+New+GPU+Architecture%2C+A100+GPU%2C+and+Accelerator&rft.date=2020-05-14&rft.aulast=Smith&rft.aufirst=Ryan&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F15801%2Fnvidia-announces-ampere-architecture-and-a100-products&rfr_id=info%3Asid%2Fen.wikipedia.org%3APascal+%28microarchitecture%29" class="Z3988"></span></span> </li> <li id="cite_note-36"><span class="mw-cite-backlink"><b><a href="#cite_ref-36">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.tweaktown.com/news/59155/nvidia-tesla-v100-tested-near-unbelievable-gpu-power/index.html">"NVIDIA Tesla V100 tested: near unbelievable GPU power"</a>. <i>TweakTown</i>. September 17, 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TweakTown&rft.atitle=NVIDIA+Tesla+V100+tested%3A+near+unbelievable+GPU+power&rft.date=2017-09-17&rft_id=https%3A%2F%2Fwww.tweaktown.com%2Fnews%2F59155%2Fnvidia-tesla-v100-tested-near-unbelievable-gpu-power%2Findex.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3APascal+%28microarchitecture%29" class="Z3988"></span></span> </li> </ol></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1236075235">.mw-parser-output .navbox{box-sizing:border-box;border:1px solid #a2a9b1;width:100%;clear:both;font-size:88%;text-align:center;padding:1px;margin:1em auto 0}.mw-parser-output .navbox .navbox{margin-top:0}.mw-parser-output .navbox+.navbox,.mw-parser-output .navbox+.navbox-styles+.navbox{margin-top:-1px}.mw-parser-output .navbox-inner,.mw-parser-output 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0.25em"></div><table class="nowraplinks mw-collapsible mw-collapsed navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="GeForce_(List_of_GPUs)" style="font-size:114%;margin:0 4em"><a href="/wiki/GeForce" title="GeForce">GeForce</a> <small>(<a href="/wiki/List_of_Nvidia_graphics_processing_units" title="List of Nvidia graphics processing units">List of GPUs</a>)</small></div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Fixed pixel pipeline</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="Pre-GeForce" scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_Nvidia_graphics_processing_units#Pre-GeForce" title="List of Nvidia graphics processing units">Pre-GeForce</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"><div class="hlist"> <ul><li><a href="/wiki/NV1" title="NV1">NV1</a></li> <li><a href="/wiki/NV2" class="mw-redirect" title="NV2">NV2</a></li></ul> </div> <div class="hlist"> <ul><li><a href="/wiki/RIVA_128" title="RIVA 128">RIVA 128</a></li> <li><a href="/wiki/RIVA_TNT" title="RIVA TNT">RIVA TNT</a></li> <li><a href="/wiki/RIVA_TNT2" title="RIVA TNT2">TNT2</a></li></ul> </div></div></td></tr></tbody></table><div> <ul><li> <a href="/wiki/GeForce_256" title="GeForce 256">GeForce 256</a></li> <li><a href="/wiki/GeForce_2_series" title="GeForce 2 series">2</a></li> <li><a href="/wiki/GeForce_4_series" title="GeForce 4 series">4 MX</a></li></ul></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Vertex_shader" class="mw-redirect" title="Vertex shader">Vertex</a> and <a href="/wiki/Pixel_shader" class="mw-redirect" title="Pixel shader">pixel</a> shaders</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <li><a href="/wiki/GeForce_3_series" title="GeForce 3 series">GeForce 3</a></li> <li><a href="/wiki/GeForce_4_series" title="GeForce 4 series">4 Ti</a></li> <li><a href="/wiki/GeForce_FX_series" title="GeForce FX series">FX</a></li> <li><a href="/wiki/GeForce_6_series" title="GeForce 6 series">6</a></li> <li><a href="/wiki/GeForce_7_series" title="GeForce 7 series">7</a></li> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Unified_Shader_Model" class="mw-redirect" title="Unified Shader Model">Unified shaders</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/GeForce_8_series" title="GeForce 8 series">GeForce 8</a></li> <li><a href="/wiki/GeForce_9_series" title="GeForce 9 series">9</a></li> <li><a href="/wiki/GeForce_100_series" title="GeForce 100 series">100</a></li> <li><a href="/wiki/GeForce_200_series" title="GeForce 200 series">200</a></li> <li><a href="/wiki/GeForce_300_series" title="GeForce 300 series">300</a></li> <li><a href="/wiki/GeForce_400_series" title="GeForce 400 series">400</a></li> <li><a href="/wiki/GeForce_500_series" title="GeForce 500 series">500</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Unified shaders & <a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/GeForce_600_series" title="GeForce 600 series">GeForce 600</a></li> <li><a href="/wiki/GeForce_700_series" title="GeForce 700 series">700</a></li> <li><a href="/wiki/GeForce_800M_series" title="GeForce 800M series">800M</a></li> <li><a href="/wiki/GeForce_900_series" title="GeForce 900 series">900</a></li> <li><a href="/wiki/GeForce_10_series" title="GeForce 10 series">10</a></li> <li><a href="/wiki/GeForce_16_series" title="GeForce 16 series">16</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Ray_tracing_(graphics)" title="Ray tracing (graphics)">Ray tracing</a> & tensor cores</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/GeForce_20_series" title="GeForce 20 series">GeForce 20</a></li> <li><a href="/wiki/GeForce_30_series" title="GeForce 30 series">30</a></li> <li><a href="/wiki/GeForce_40_series" title="GeForce 40 series">40</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><td colspan="2" class="navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks mw-collapsible mw-collapsed navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Software_and_technologies" style="font-size:114%;margin:0 4em">Software and technologies</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Multimedia acceleration</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Nvidia_NVENC" title="Nvidia NVENC">NVENC</a> (video encoding)</li> <li><a href="/wiki/Nvidia_NVDEC" title="Nvidia NVDEC">NVDEC</a> (video decoding)</li> <li><a href="/wiki/Nvidia_PureVideo" title="Nvidia PureVideo">PureVideo</a> (video decoding)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Cg_(programming_language)" title="Cg (programming language)">Cg</a> (shading language)</li> <li><a href="/wiki/CUDA" title="CUDA">CUDA</a></li> <li><a href="/wiki/Nvidia_GameWorks" title="Nvidia GameWorks">Nvidia GameWorks</a> <ul><li><a href="/wiki/OptiX" title="OptiX">OptiX</a> (ray tracing API)</li> <li><a href="/wiki/PhysX" title="PhysX">PhysX</a> (physics SDK)</li></ul></li> <li><a href="/wiki/Nvidia_Omniverse" title="Nvidia Omniverse">Nvidia Omniverse</a> (3D graphics)</li> <li><a href="/wiki/Nvidia_RTX" title="Nvidia RTX">Nvidia RTX</a> (ray tracing platform)</li> <li><a href="/wiki/Nvidia_System_Tools" title="Nvidia System Tools">Nvidia System Tools</a></li> <li><a href="/wiki/VDPAU" title="VDPAU">VDPAU</a> (video decode API)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Technologies</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Nvidia_3D_Vision" title="Nvidia 3D Vision">Nvidia 3D Vision</a> (stereo 3D)</li> <li><a href="/wiki/Nvidia_G-Sync" title="Nvidia G-Sync">Nvidia G-Sync</a> (variable refresh rate)</li> <li><a href="/wiki/Nvidia_Optimus" title="Nvidia Optimus">Nvidia Optimus</a> (GPU switching)</li> <li><a href="/wiki/Nvidia_Surround" class="mw-redirect" title="Nvidia Surround">Nvidia Surround</a> (multi-monitor)</li> <li><a href="/wiki/Mobile_PCI_Express_Module" title="Mobile PCI Express Module">MXM</a> (module/socket)</li> <li><a href="/wiki/SXM_(socket)" title="SXM (socket)">SXM</a> (module/socket)</li> <li><a href="/wiki/NVLink" title="NVLink">NVLink</a> (protocol)</li> <li><a href="/wiki/Scalable_Link_Interface" title="Scalable Link Interface">Scalable Link Interface</a> (multi-GPU)</li> <li><a href="/wiki/TurboCache" title="TurboCache">TurboCache</a> (framebuffer in system memory)</li> <li><a href="/wiki/Video_Super_Resolution" title="Video Super Resolution">Video Super Resolution</a> (live video upscaling)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">GPU microarchitectures</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Celsius_(microarchitecture)" title="Celsius (microarchitecture)">Celsius</a></li> <li><a href="/wiki/Kelvin_(microarchitecture)" title="Kelvin (microarchitecture)">Kelvin</a></li> <li><a href="/wiki/Rankine_(microarchitecture)" title="Rankine (microarchitecture)">Rankine</a></li> <li><a href="/wiki/Curie_(microarchitecture)" title="Curie (microarchitecture)">Curie</a></li> <li><a href="/wiki/Tesla_(microarchitecture)" title="Tesla (microarchitecture)">Tesla</a></li> <li><a href="/wiki/Fermi_(microarchitecture)" title="Fermi (microarchitecture)">Fermi</a></li> <li><a href="/wiki/Kepler_(microarchitecture)" title="Kepler (microarchitecture)">Kepler</a></li> <li><a href="/wiki/Maxwell_(microarchitecture)" title="Maxwell (microarchitecture)">Maxwell</a></li> <li><a class="mw-selflink selflink">Pascal</a></li> <li><a href="/wiki/Volta_(microarchitecture)" title="Volta (microarchitecture)">Volta</a></li> <li><a href="/wiki/Turing_(microarchitecture)" title="Turing (microarchitecture)">Turing</a></li> <li><a href="/wiki/Ampere_(microarchitecture)" title="Ampere (microarchitecture)">Ampere</a></li> <li><a href="/wiki/Hopper_(microarchitecture)" title="Hopper (microarchitecture)">Hopper</a></li> <li><a href="/wiki/Ada_Lovelace_(microarchitecture)" title="Ada Lovelace (microarchitecture)">Ada Lovelace</a></li> <li><a href="/wiki/Blackwell_(microarchitecture)" title="Blackwell (microarchitecture)">Blackwell</a></li> <li><a href="/wiki/Rubin_(microarchitecture)" title="Rubin (microarchitecture)">Rubin</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><td colspan="2" class="navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks mw-collapsible mw-collapsed navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Other_products" style="font-size:114%;margin:0 4em">Other products</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Graphics <a href="/wiki/Workstation" title="Workstation">Workstation</a> cards</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Quadro" title="Quadro">Nvidia Quadro</a> <ul><li><a href="/wiki/Nvidia_Quadro_Plex" title="Nvidia Quadro Plex">Quadro Plex</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Nvidia_Tesla" title="Nvidia Tesla">Nvidia Tesla</a></li> <li><a href="/wiki/Nvidia_DGX" title="Nvidia DGX">DGX</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Video_game_console" title="Video game console">Console</a> components</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Xbox_(console)#Technical_specifications" title="Xbox (console)">NV2A</a> <span style="font-size:85%;">(<a href="/wiki/Xbox_(console)" title="Xbox (console)">Xbox</a>)</span></li> <li><a href="/wiki/RSX_Reality_Synthesizer" title="RSX Reality Synthesizer">RSX 'Reality Synthesizer'</a> <span style="font-size:85%;">(<a href="/wiki/PlayStation_3" title="PlayStation 3">PlayStation 3</a>)</span></li> <li><a href="/wiki/Tegra#Tegra_X1" title="Tegra">Tegra NX-SoC</a> <span style="font-size:85%;">(<a href="/wiki/Nintendo_Switch" title="Nintendo Switch">Nintendo Switch</a>)</span></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Nvidia Shield</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Shield_Portable" class="mw-redirect" title="Shield Portable">Shield Portable</a></li> <li><a href="/wiki/Shield_Tablet" class="mw-redirect" title="Shield Tablet">Shield Tablet</a></li> <li><a href="/wiki/Shield_Android_TV" class="mw-redirect" title="Shield Android TV">Shield Android TV</a></li> <li><a href="/wiki/GeForce_Now" title="GeForce Now">GeForce Now</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/System_on_a_chip" title="System on a chip">SoCs</a> and embedded</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/GoForce" title="GoForce">GoForce</a></li> <li><a href="/wiki/Nvidia_Drive" title="Nvidia Drive">Drive</a></li> <li><a href="/wiki/Nvidia_Jetson" title="Nvidia Jetson">Jetson</a></li> <li><a href="/wiki/Tegra" title="Tegra">Tegra</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPUs</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Project_Denver" title="Project Denver">Project Denver</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Computer <a href="/wiki/Chipset" title="Chipset">chipsets</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Comparison_of_Nvidia_chipsets" class="mw-redirect" title="Comparison of Nvidia chipsets">nForce</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><td colspan="2" class="navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks mw-collapsible mw-collapsed navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Company" style="font-size:114%;margin:0 4em">Company</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Key people</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Jensen_Huang" title="Jensen Huang">Jen-Hsun Huang</a></li> <li><a href="/wiki/Chris_Malachowsky" title="Chris Malachowsky">Chris Malachowsky</a></li> <li><a href="/wiki/Curtis_Priem" title="Curtis Priem">Curtis Priem</a></li> <li><a href="/wiki/David_Kirk_(scientist)" title="David Kirk (scientist)">David Kirk</a></li> <li><a href="/wiki/Bill_Dally" title="Bill Dally">Bill Dally</a></li> <li>Debora Shoquist</li> <li>Ranga Jayaraman</li> <li>Jonah M. Alben</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Acquisitions</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/3dfx" title="3dfx">3dfx Interactive</a></li> <li><a href="/wiki/Ageia" title="Ageia">Ageia</a></li> <li><a href="/wiki/Acer_Laboratories_Incorporated" class="mw-redirect" title="Acer Laboratories Incorporated">ULi</a></li> <li><a href="/wiki/Bright_Computing" title="Bright Computing">Bright Computing</a></li> <li><a href="/wiki/Cumulus_Networks" title="Cumulus Networks">Cumulus Networks</a></li> <li><a href="/wiki/DeepMap" title="DeepMap">DeepMap</a></li> <li><a href="/wiki/Icera" title="Icera">Icera</a></li> <li><a href="/wiki/Mellanox_Technologies" title="Mellanox Technologies">Mellanox Technologies</a></li> <li><a href="/wiki/Mental_Images" title="Mental Images">Mental Images</a></li> <li><a href="/wiki/PortalPlayer" title="PortalPlayer">PortalPlayer</a></li> <li>Exluna</li> <li>MediaQ</li> <li>Stexar</li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=Pascal_(microarchitecture)&oldid=1253162519">https://en.wikipedia.org/w/index.php?title=Pascal_(microarchitecture)&oldid=1253162519</a>"</div></div> <div id="catlinks" class="catlinks" data-mw="interface"><div id="mw-normal-catlinks" class="mw-normal-catlinks"><a href="/wiki/Help:Category" title="Help:Category">Categories</a>: <ul><li><a href="/wiki/Category:Nvidia_microarchitectures" title="Category:Nvidia microarchitectures">Nvidia microarchitectures</a></li><li><a href="/wiki/Category:Graphics_microarchitectures" title="Category:Graphics microarchitectures">Graphics microarchitectures</a></li></ul></div><div id="mw-hidden-catlinks" class="mw-hidden-catlinks mw-hidden-cats-hidden">Hidden categories: <ul><li><a href="/wiki/Category:CS1_French-language_sources_(fr)" title="Category:CS1 French-language sources (fr)">CS1 French-language sources (fr)</a></li><li><a href="/wiki/Category:Articles_with_short_description" title="Category:Articles with short description">Articles with short description</a></li><li><a href="/wiki/Category:Short_description_is_different_from_Wikidata" title="Category:Short description is different from Wikidata">Short description is different from Wikidata</a></li><li><a href="/wiki/Category:Use_American_English_from_April_2023" title="Category:Use American English from April 2023">Use American English from April 2023</a></li><li><a href="/wiki/Category:All_Wikipedia_articles_written_in_American_English" title="Category:All Wikipedia articles written in American English">All Wikipedia articles written in American English</a></li><li><a href="/wiki/Category:Use_mdy_dates_from_April_2023" title="Category:Use mdy dates from April 2023">Use mdy dates from April 2023</a></li></ul></div></div> </div> </main> </div> <div class="mw-footer-container"> <footer id="footer" class="mw-footer" > <ul id="footer-info"> <li id="footer-info-lastmod"> This page was last edited on 24 October 2024, at 16:59<span class="anonymous-show"> (UTC)</span>.</li> <li id="footer-info-copyright">Text is available under the <a href="/wiki/Wikipedia:Text_of_the_Creative_Commons_Attribution-ShareAlike_4.0_International_License" title="Wikipedia:Text of the Creative Commons Attribution-ShareAlike 4.0 International License">Creative Commons Attribution-ShareAlike 4.0 License</a>; additional terms may apply. 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