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circuits</title> <meta name="description" content="Search results for: biasing circuits"> <meta name="keywords" content="biasing circuits"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> <button class="d-block d-lg-none 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action="https://publications.waset.org/abstracts/search"> <div id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="biasing circuits"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 325</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: biasing circuits</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">325</span> Low Power, Highly Linear, Wideband LNA in Wireless SOC</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Amir%20Mahdavi">Amir Mahdavi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper a highly linear CMOS low noise amplifier (LNA) for ultra-wideband (UWB) applications is proposed. The proposed LNA uses a linearization technique to improve second and third-order intercept points (IIP3). The linearity is cured by repealing the common-mode section of all intermodulation components from the cascade topology current with optimization of biasing current use symmetrical and asymmetrical circuits for biasing. Simulation results show that maximum gain and noise figure are 6.9dB and 3.03-4.1dB over a 3.1–10.6 GHz, respectively. Power consumption of the LNA core and IIP3 are 2.64 mW and +4.9dBm respectively. The wideband input impedance matching of LNA is obtained by employing a degenerating inductor (|S11|<-9.1 dB). The circuit proposed UWB LNA is implemented using 0.18 μm based CMOS technology. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=highly%20linear%20LNA" title="highly linear LNA">highly linear LNA</a>, <a href="https://publications.waset.org/abstracts/search?q=low-power%20LNA" title=" low-power LNA"> low-power LNA</a>, <a href="https://publications.waset.org/abstracts/search?q=optimal%20bias%20techniques" title=" optimal bias techniques"> optimal bias techniques</a> </p> <a href="https://publications.waset.org/abstracts/75554/low-power-highly-linear-wideband-lna-in-wireless-soc" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/75554.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">280</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">324</span> Internal Node Stabilization for Voltage Sense Amplifiers in Multi-Channel Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Sanghoon%20Park">Sanghoon Park</a>, <a href="https://publications.waset.org/abstracts/search?q=Ki-Jin%20Kim"> Ki-Jin Kim</a>, <a href="https://publications.waset.org/abstracts/search?q=Kwang-Ho%20Ahn"> Kwang-Ho Ahn</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper discusses the undesirable charge transfer by the parasitic capacitances of the input transistors in a voltage sense amplifier. Due to its intrinsic rail-to-rail voltage transition, the input sides are inevitably disturbed. It can possible disturb the stabilities of the reference voltage levels. Moreover, it becomes serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the systems. In order to alleviate the internal node voltage transition, the internal node stabilization technique is proposed by utilizing an additional biasing circuit. It achieves 47% and 43% improvements for node stabilization and input referred disturbance, respectively. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=voltage%20sense%20amplifier" title="voltage sense amplifier">voltage sense amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=voltage%20transition" title=" voltage transition"> voltage transition</a>, <a href="https://publications.waset.org/abstracts/search?q=node%20stabilization" title=" node stabilization"> node stabilization</a>, <a href="https://publications.waset.org/abstracts/search?q=biasing%20circuits" title=" biasing circuits"> biasing circuits</a> </p> <a href="https://publications.waset.org/abstracts/6878/internal-node-stabilization-for-voltage-sense-amplifiers-in-multi-channel-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/6878.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">479</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">323</span> One Period Loops of Memristive Circuits with Mixed-Mode Oscillations</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Wieslaw%20Marszalek">Wieslaw Marszalek</a>, <a href="https://publications.waset.org/abstracts/search?q=Zdzislaw%20Trzaska"> Zdzislaw Trzaska</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Interesting properties of various one-period loops of singularly perturbed memristive circuits with mixed-mode oscillations (MMOs) are analyzed in this paper. The analysis is mixed, both analytical and numerical and focused on the properties of pinched hysteresis of the memristive element and other one-period loops formed by pairs of time-series solutions for various circuits' variables. The memristive element is the only nonlinear element in the two circuits. A theorem on periods of mixed-mode oscillations of the circuits is formulated and proved. Replacements of memristors by parallel G-C or series R-L circuits for a MMO response with equivalent RMS values is also discussed. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=mixed-mode%20oscillations" title="mixed-mode oscillations">mixed-mode oscillations</a>, <a href="https://publications.waset.org/abstracts/search?q=memristive%20circuits" title=" memristive circuits"> memristive circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=pinched%20hysteresis" title=" pinched hysteresis"> pinched hysteresis</a>, <a href="https://publications.waset.org/abstracts/search?q=one-period%20loops" title=" one-period loops"> one-period loops</a>, <a href="https://publications.waset.org/abstracts/search?q=singularly%20perturbed%20circuits" title=" singularly perturbed circuits"> singularly perturbed circuits</a> </p> <a href="https://publications.waset.org/abstracts/20949/one-period-loops-of-memristive-circuits-with-mixed-mode-oscillations" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/20949.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">470</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">322</span> Design of 900 MHz High Gain SiGe Power Amplifier with Linearity Improved Bias Circuit</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Guiheng%20Zhang">Guiheng Zhang</a>, <a href="https://publications.waset.org/abstracts/search?q=Wei%20Zhang"> Wei Zhang</a>, <a href="https://publications.waset.org/abstracts/search?q=Jun%20Fu"> Jun Fu</a>, <a href="https://publications.waset.org/abstracts/search?q=Yudong%20Wang"> Yudong Wang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A 900 MHz three-stage SiGe power amplifier (PA) with high power gain is presented in this paper. Volterra Series is applied to analyze nonlinearity sources of SiGe HBT device model clearly. Meanwhile, the influence of operating current to IMD3 is discussed. Then a β-helper current mirror bias circuit is applied to improve linearity, since the β-helper current mirror bias circuit can offer stable base biasing voltage. Meanwhile, it can also work as predistortion circuit when biasing voltages of three bias circuits are fine-tuned, by this way, the power gain and operating current of PA are optimized for best linearity. The three power stages which fabricated by 0.18 μm SiGe technology are bonded to the printed circuit board (PCB) to obtain impedances by Load-Pull system, then matching networks are done for best linearity with discrete passive components on PCB. The final measured three-stage PA exhibits 21.1 dBm of output power at 1 dB compression point (OP1dB) with power added efficiency (PAE) of 20.6% and 33 dB power gain under 3.3 V power supply voltage. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=high%20gain%20power%20amplifier" title="high gain power amplifier">high gain power amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=linearization%20bias%20circuit" title=" linearization bias circuit"> linearization bias circuit</a>, <a href="https://publications.waset.org/abstracts/search?q=SiGe%20HBT%20model" title=" SiGe HBT model"> SiGe HBT model</a>, <a href="https://publications.waset.org/abstracts/search?q=Volterra%20series" title=" Volterra series"> Volterra series</a> </p> <a href="https://publications.waset.org/abstracts/62323/design-of-900-mhz-high-gain-sige-power-amplifier-with-linearity-improved-bias-circuit" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/62323.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">339</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">321</span> Efficient Study of Substrate Integrated Waveguide Devices</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=J.%20Hajri">J. Hajri</a>, <a href="https://publications.waset.org/abstracts/search?q=H.%20Hrizi"> H. Hrizi</a>, <a href="https://publications.waset.org/abstracts/search?q=N.%20Sboui"> N. Sboui</a>, <a href="https://publications.waset.org/abstracts/search?q=H.%20Baudrand"> H. Baudrand</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a study of SIW circuits (Substrate Integrated Waveguide) with a rigorous and fast original approach based on Iterative process (WCIP). The theoretical suggested study is validated by the simulation of two different examples of SIW circuits. The obtained results are in good agreement with those of measurement and with software HFSS. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=convergence%20study" title="convergence study">convergence study</a>, <a href="https://publications.waset.org/abstracts/search?q=HFSS" title=" HFSS"> HFSS</a>, <a href="https://publications.waset.org/abstracts/search?q=modal%20decomposition" title=" modal decomposition"> modal decomposition</a>, <a href="https://publications.waset.org/abstracts/search?q=SIW%20circuits" title=" SIW circuits"> SIW circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=WCIP%20method" title=" WCIP method"> WCIP method</a> </p> <a href="https://publications.waset.org/abstracts/22247/efficient-study-of-substrate-integrated-waveguide-devices" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/22247.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">498</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">320</span> Two Kinds of Self-Oscillating Circuits Mechanically Demonstrated</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Shiang-Hwua%20Yu">Shiang-Hwua Yu</a>, <a href="https://publications.waset.org/abstracts/search?q=Po-Hsun%20Wu"> Po-Hsun Wu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This study introduces two types of self-oscillating circuits that are frequently found in power electronics applications. Special effort is made to relate the circuits to the analogous mechanical systems of some important scientific inventions: Galileo’s pendulum clock and Coulomb’s friction model. A little touch of related history and philosophy of science will hopefully encourage curiosity, advance the understanding of self-oscillating systems and satisfy the aspiration of some students for scientific literacy. Finally, the two self-oscillating circuits are applied to design a simple class-D audio amplifier. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=self-oscillation" title="self-oscillation">self-oscillation</a>, <a href="https://publications.waset.org/abstracts/search?q=sigma-delta%20modulator" title=" sigma-delta modulator"> sigma-delta modulator</a>, <a href="https://publications.waset.org/abstracts/search?q=pendulum%20clock" title=" pendulum clock"> pendulum clock</a>, <a href="https://publications.waset.org/abstracts/search?q=Coulomb%20friction" title=" Coulomb friction"> Coulomb friction</a>, <a href="https://publications.waset.org/abstracts/search?q=class-D%20amplifier" title=" class-D amplifier"> class-D amplifier</a> </p> <a href="https://publications.waset.org/abstracts/9932/two-kinds-of-self-oscillating-circuits-mechanically-demonstrated" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/9932.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">356</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">319</span> Optimization and Design of Current-Mode Multiplier Circuits with Applications in Analog Signal Processing for Gas Industrial Package Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mohamad%20Baqer%20Heidari">Mohamad Baqer Heidari</a>, <a href="https://publications.waset.org/abstracts/search?q=Hefzollah.Mohammadian"> Hefzollah.Mohammadian </a> </p> <p class="card-text"><strong>Abstract:</strong></p> This brief presents two original implementations of improved accuracy current-mode multiplier/divider circuits. Besides the advantage of their simplicity, these original multiplier/divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.75% and 0.9%, respectively, for an extended range of the input currents). The original multiplier/divider circuits permit a facile reconfiguration, the presented structures representing the functional basis for implementing complex function synthesizer circuits. The proposed computational structures are designed for implementing in 0.18-µm CMOS technology, with a low-voltage operation (a supply voltage of 1.2 V). The circuits’ power consumptions are 60 and 75 µW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=analog%20signal%20processing" title="analog signal processing">analog signal processing</a>, <a href="https://publications.waset.org/abstracts/search?q=current-mode%20%20operation" title=" current-mode operation"> current-mode operation</a>, <a href="https://publications.waset.org/abstracts/search?q=functional%20core" title=" functional core"> functional core</a>, <a href="https://publications.waset.org/abstracts/search?q=multiplier" title=" multiplier"> multiplier</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20circuits" title=" reconfigurable circuits"> reconfigurable circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=industrial%20package%20systems" title=" industrial package systems"> industrial package systems</a> </p> <a href="https://publications.waset.org/abstracts/36406/optimization-and-design-of-current-mode-multiplier-circuits-with-applications-in-analog-signal-processing-for-gas-industrial-package-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/36406.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">374</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">318</span> Comparative Performance Analysis of Nonlinearity Cancellation Techniques for MOS-C Realization in Integrator Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hasan%20%C3%87i%C3%A7ekli">Hasan Çiçekli</a>, <a href="https://publications.waset.org/abstracts/search?q=Ahmet%20G%C3%B6k%C3%A7en"> Ahmet Gökçen</a>, <a href="https://publications.waset.org/abstracts/search?q=U%C4%9Fur%20%C3%87am"> Uğur Çam</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, a comparative performance analysis of mostly used four nonlinearity cancellation techniques used to realize the passive resistor by MOS transistors is presented. The comparison is done by using an integrator circuit which is employing sequentially Op-amp, OTRA and ICCII as active element. All of the circuits are implemented by MOS-C realization and simulated by PSPICE program using 0.35 µm process TSMC MOSIS model parameters. With MOS-C realization, the circuits became electronically tunable and fully integrable which is very important in IC design. The output waveforms, frequency responses, THD analysis results and features of the nonlinearity cancellation techniques are also given. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=integrator%20circuits" title="integrator circuits">integrator circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=MOS-C%20realization" title=" MOS-C realization"> MOS-C realization</a>, <a href="https://publications.waset.org/abstracts/search?q=nonlinearity%20cancellation" title=" nonlinearity cancellation"> nonlinearity cancellation</a>, <a href="https://publications.waset.org/abstracts/search?q=tuneable%20resistors" title=" tuneable resistors"> tuneable resistors</a> </p> <a href="https://publications.waset.org/abstracts/38167/comparative-performance-analysis-of-nonlinearity-cancellation-techniques-for-mos-c-realization-in-integrator-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/38167.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">533</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">317</span> Stabilization Technique for Multi-Inputs Voltage Sense Amplifiers in Node Sharing Converters</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Sanghoon%20Park">Sanghoon Park</a>, <a href="https://publications.waset.org/abstracts/search?q=Ki-Jin%20Kim"> Ki-Jin Kim</a>, <a href="https://publications.waset.org/abstracts/search?q=Kwang-Ho%20Ahn"> Kwang-Ho Ahn</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper discusses the undesirable charge transfer through the parasitic capacitances of the input transistors in a multi-inputs voltage sense amplifier. Its intrinsic rail-to-rail voltage transitions at the output nodes inevitably disturb the input sides through the capacitive coupling between the outputs and inputs. Then, it can possible degrade the stabilities of the reference voltage levels. Moreover, it becomes more serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the overall systems. In order to alleviate the internal node voltage transition, the internal node stabilization techniques are proposed. It achieves 45% and 40% improvements for node stabilization and input referred disturbance, respectively. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=voltage%20sense%20amplifier" title="voltage sense amplifier">voltage sense amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=multi-inputs" title=" multi-inputs"> multi-inputs</a>, <a href="https://publications.waset.org/abstracts/search?q=voltage%20transition" title=" voltage transition"> voltage transition</a>, <a href="https://publications.waset.org/abstracts/search?q=node%20stabilization" title=" node stabilization"> node stabilization</a>, <a href="https://publications.waset.org/abstracts/search?q=biasing%20circuits" title=" biasing circuits"> biasing circuits</a> </p> <a href="https://publications.waset.org/abstracts/23974/stabilization-technique-for-multi-inputs-voltage-sense-amplifiers-in-node-sharing-converters" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/23974.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">565</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">316</span> Inverter Based Gain-Boosting Fully Differential CMOS Amplifier</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Alpana%20Agarwal">Alpana Agarwal</a>, <a href="https://publications.waset.org/abstracts/search?q=Akhil%20Sharma"> Akhil Sharma</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7<sup>o</sup> with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CMOS%20amplifier" title="CMOS amplifier">CMOS amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=gain%20boosting" title=" gain boosting"> gain boosting</a>, <a href="https://publications.waset.org/abstracts/search?q=inverter-based%20amplifier" title=" inverter-based amplifier"> inverter-based amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=self-biased%20inverter" title=" self-biased inverter"> self-biased inverter</a> </p> <a href="https://publications.waset.org/abstracts/64250/inverter-based-gain-boosting-fully-differential-cmos-amplifier" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/64250.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">303</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">315</span> Tamper Resistance Evaluation Tests with Noise Resources</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Masaya%20Yoshikawa">Masaya Yoshikawa</a>, <a href="https://publications.waset.org/abstracts/search?q=Toshiya%20Asai"> Toshiya Asai</a>, <a href="https://publications.waset.org/abstracts/search?q=Ryoma%20Matsuhisa"> Ryoma Matsuhisa</a>, <a href="https://publications.waset.org/abstracts/search?q=Yusuke%20Nozaki"> Yusuke Nozaki</a>, <a href="https://publications.waset.org/abstracts/search?q=Kensaku%20Asahi"> Kensaku Asahi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Recently, side-channel attacks, which estimate secret keys using side-channel information such as power consumption and compromising emanations of cryptography circuits embedded in hardware, have become a serious problem. In particular, electromagnetic analysis attacks against cryptographic circuits between information processing and electromagnetic fields, which are related to secret keys in cryptography circuits, are the most threatening side-channel attacks. Therefore, it is important to evaluate tamper resistance against electromagnetic analysis attacks for cryptography circuits. The present study performs basic examination of the tamper resistance of cryptography circuits using electromagnetic analysis attacks with noise resources. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=tamper%20resistance" title="tamper resistance">tamper resistance</a>, <a href="https://publications.waset.org/abstracts/search?q=cryptographic%20circuit" title=" cryptographic circuit"> cryptographic circuit</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20security%20evaluation" title=" hardware security evaluation"> hardware security evaluation</a>, <a href="https://publications.waset.org/abstracts/search?q=noise%20resources" title=" noise resources "> noise resources </a> </p> <a href="https://publications.waset.org/abstracts/25852/tamper-resistance-evaluation-tests-with-noise-resources" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/25852.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">504</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">314</span> Memristor-A Promising Candidate for Neural Circuits in Neuromorphic Computing Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Juhi%20Faridi">Juhi Faridi</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohd.%20Ajmal%20Kafeel"> Mohd. Ajmal Kafeel</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The advancements in the field of Artificial Intelligence (AI) and technology has led to an evolution of an intelligent era. Neural networks, having the computational power and learning ability similar to the brain is one of the key AI technologies. Neuromorphic computing system (NCS) consists of the synaptic device, neuronal circuit, and neuromorphic architecture. Memristor are a promising candidate for neuromorphic computing systems, but when it comes to neuromorphic computing, the conductance behavior of the synaptic memristor or neuronal memristor needs to be studied thoroughly in order to fathom the neuroscience or computer science. Furthermore, there is a need of more simulation work for utilizing the existing device properties and providing guidance to the development of future devices for different performance requirements. Hence, development of NCS needs more simulation work to make use of existing device properties. This work aims to provide an insight to build neuronal circuits using memristors to achieve a Memristor based NCS.  Here we throw a light on the research conducted in the field of memristors for building analog and digital circuits in order to motivate the research in the field of NCS by building memristor based neural circuits for advanced AI applications. This literature is a step in the direction where we describe the various Key findings about memristors and its analog and digital circuits implemented over the years which can be further utilized in implementing the neuronal circuits in the NCS. This work aims to help the electronic circuit designers to understand how the research progressed in memristors and how these findings can be used in implementing the neuronal circuits meant for the recent progress in the NCS. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=analog%20circuits" title="analog circuits">analog circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=digital%20circuits" title=" digital circuits"> digital circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=memristors" title=" memristors"> memristors</a>, <a href="https://publications.waset.org/abstracts/search?q=neuromorphic%20computing%20systems" title=" neuromorphic computing systems"> neuromorphic computing systems</a> </p> <a href="https://publications.waset.org/abstracts/100057/memristor-a-promising-candidate-for-neural-circuits-in-neuromorphic-computing-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/100057.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">174</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">313</span> Characteization and Optimization of S-Parameters of Microwave Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=N.%20Ourabia">N. Ourabia</a>, <a href="https://publications.waset.org/abstracts/search?q=M.%20Boubaker%20Ourabia"> M. Boubaker Ourabia</a> </p> <p class="card-text"><strong>Abstract:</strong></p> An approach for modeling and numerical simulation of passive planar structures using the edge line concept is developed. With this method, we develop an efficient modeling technique for microstrip discontinuities. The technique obtains closed form expressions for the equivalent circuits which are used to model these discontinuities. Then, it would be easy to handle and to characterize complicated structures like T and Y junctions, truncated junctions, arbitrarily shaped junctions, cascading junctions and more generally planar multiport junctions. Another advantage of this method is that the edge line concept for arbitrary shape junctions operates with real parameters circuits. The validity of the method was further confirmed by comparing our results for various discontinuities (bend, filters) with those from HFSS as well as from other published sources. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=optimization" title="optimization">optimization</a>, <a href="https://publications.waset.org/abstracts/search?q=CAD%20analysis" title=" CAD analysis"> CAD analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=microwave%20circuits" title=" microwave circuits"> microwave circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=S-parameters" title=" S-parameters"> S-parameters</a> </p> <a href="https://publications.waset.org/abstracts/25946/characteization-and-optimization-of-s-parameters-of-microwave-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/25946.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">454</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">312</span> Paper-Based Detection Using Synthetic Gene Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Vanessa%20Funk">Vanessa Funk</a>, <a href="https://publications.waset.org/abstracts/search?q=Steven%20Blum"> Steven Blum</a>, <a href="https://publications.waset.org/abstracts/search?q=Stephanie%20Cole"> Stephanie Cole</a>, <a href="https://publications.waset.org/abstracts/search?q=Jorge%20Maciel"> Jorge Maciel</a>, <a href="https://publications.waset.org/abstracts/search?q=Matthew%20Lux"> Matthew Lux</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Paper-based synthetic gene circuits offer a new paradigm for programmable, fieldable biodetection. We demonstrate that by freeze-drying gene circuits with in vitro expression machinery, we can use complimentary RNA sequences to trigger colorimetric changes upon rehydration. We have successfully utilized both green fluorescent protein and luciferase-based reporters for easy visualization purposes in solution. Through several efforts, we are aiming to use this new platform technology to address a variety of needs in portable detection by demonstrating several more expression and reporter systems for detection functions on paper. In addition to RNA-based biodetection, we are exploring the use of various mechanisms that cells use to respond to environmental conditions to move towards all-hazards detection. Examples include explosives, heavy metals for water quality, and toxic chemicals. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cell-free%20lysates" title="cell-free lysates">cell-free lysates</a>, <a href="https://publications.waset.org/abstracts/search?q=detection" title=" detection"> detection</a>, <a href="https://publications.waset.org/abstracts/search?q=gene%20circuits" title=" gene circuits"> gene circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=in%20vitro" title=" in vitro"> in vitro</a> </p> <a href="https://publications.waset.org/abstracts/71047/paper-based-detection-using-synthetic-gene-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/71047.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">394</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">311</span> First Order Filter Based Current-Mode Sinusoidal Oscillators Using Current Differencing Transconductance Amplifiers (CDTAs)</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=S.%20Summart">S. Summart</a>, <a href="https://publications.waset.org/abstracts/search?q=C.%20Saetiaw"> C. Saetiaw</a>, <a href="https://publications.waset.org/abstracts/search?q=T.%20Thosdeekoraphat"> T. Thosdeekoraphat</a>, <a href="https://publications.waset.org/abstracts/search?q=C.%20Thongsopa"> C. Thongsopa</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This article presents new current-mode oscillator circuits using CDTAs which is designed from block diagram. The proposed circuits consist of two CDTAs and two grounded capacitors. The condition of oscillation and the frequency of oscillation can be adjusted by electronic method. The circuits have high output impedance and use only grounded capacitors without any external resistor which is very appropriate to future development into an integrated circuit. The results of PSPICE simulation program are corresponding to the theoretical analysis. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=current-mode" title="current-mode">current-mode</a>, <a href="https://publications.waset.org/abstracts/search?q=quadrature%20oscillator" title=" quadrature oscillator"> quadrature oscillator</a>, <a href="https://publications.waset.org/abstracts/search?q=block%20diagram" title=" block diagram"> block diagram</a>, <a href="https://publications.waset.org/abstracts/search?q=CDTA" title=" CDTA"> CDTA</a> </p> <a href="https://publications.waset.org/abstracts/8914/first-order-filter-based-current-mode-sinusoidal-oscillators-using-current-differencing-transconductance-amplifiers-cdtas" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/8914.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">453</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">310</span> Improving the LDMOS Temperature Compensation Bias Circuit to Optimize Back-Off</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Antonis%20Constantinides">Antonis Constantinides</a>, <a href="https://publications.waset.org/abstracts/search?q=Christos%20Yiallouras"> Christos Yiallouras</a>, <a href="https://publications.waset.org/abstracts/search?q=Christakis%20Damianou"> Christakis Damianou</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The application of today's semiconductor transistors in high power UHF DVB-T linear amplifiers has evolved significantly by utilizing LDMOS technology. This fact provides engineers with the option to design a single transistor signal amplifier which enables output power and linearity that was unobtainable previously using bipolar junction transistors or later type first generation MOSFETS. The quiescent current stability in terms of thermal variations of the LDMOS guarantees a robust operation in any topology of DVB-T signal amplifiers. Otherwise, progressively uncontrolled heat dissipation enhancement on the LDMOS case can degrade the amplifier’s crucial parameters in regards to the gain, linearity, and RF stability, resulting in dysfunctional operation or a total destruction of the unit. This paper presents one more sophisticated approach from the traditional biasing circuits used so far in LDMOS DVB-T amplifiers. It utilizes a microprocessor control technology, providing stability in topologies where IDQ must be perfectly accurate. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=LDMOS" title="LDMOS">LDMOS</a>, <a href="https://publications.waset.org/abstracts/search?q=amplifier" title=" amplifier"> amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=back-off" title=" back-off"> back-off</a>, <a href="https://publications.waset.org/abstracts/search?q=bias%20circuit" title=" bias circuit"> bias circuit</a> </p> <a href="https://publications.waset.org/abstracts/11313/improving-the-ldmos-temperature-compensation-bias-circuit-to-optimize-back-off" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/11313.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">339</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">309</span> Importance of Hardware Systems and Circuits in Secure Software Development Life Cycle</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mir%20Shahriar%20Emami">Mir Shahriar Emami</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Although it is fully impossible to ensure that a software system is quite secure, developing an acceptable secure software system in a convenient platform is not unreachable. In this paper, we attempt to analyze software development life cycle (SDLC) models from the hardware systems and circuits point of view. To date, the SDLC models pay merely attention to the software security from the software perspectives. In this paper, we present new features for SDLC stages to emphasize the role of systems and circuits in developing secure software system through the software development stages, the point that has not been considered previously in the SDLC models. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SDLC" title="SDLC">SDLC</a>, <a href="https://publications.waset.org/abstracts/search?q=SSDLC" title=" SSDLC"> SSDLC</a>, <a href="https://publications.waset.org/abstracts/search?q=software%20security" title=" software security"> software security</a>, <a href="https://publications.waset.org/abstracts/search?q=software%20process%20engineering" title=" software process engineering"> software process engineering</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20systems%20and%20circuits%20security" title=" hardware systems and circuits security"> hardware systems and circuits security</a> </p> <a href="https://publications.waset.org/abstracts/55558/importance-of-hardware-systems-and-circuits-in-secure-software-development-life-cycle" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/55558.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">261</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">308</span> Efficient Modeling Technique for Microstrip Discontinuities</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nassim%20Ourabia">Nassim Ourabia</a>, <a href="https://publications.waset.org/abstracts/search?q=Malika%20Ourabia"> Malika Ourabia</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A new and efficient method is presented for the analysis of arbitrarily shaped discontinuities. The technique obtains closed form expressions for the equivalent circuits which are used to model these discontinuities. Then it would be easy to handle and to characterize complicated structures like T and Y junctions, truncated junctions, arbitrarily shaped junctions, cascading junctions, and more generally planar multiport junctions. Another advantage of this method is that the edge line concept for arbitrary shape junctions operates with real parameters circuits. The validity of the method was further confirmed by comparing our results for various discontinuities (bend, filters) with those from HFSS as well as from other published sources. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CAD%20analysis" title="CAD analysis">CAD analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=contour%20integral%20approach" title=" contour integral approach"> contour integral approach</a>, <a href="https://publications.waset.org/abstracts/search?q=microwave%20circuits" title=" microwave circuits"> microwave circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=s-parameters" title=" s-parameters"> s-parameters</a> </p> <a href="https://publications.waset.org/abstracts/25945/efficient-modeling-technique-for-microstrip-discontinuities" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/25945.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">516</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">307</span> Design and Implementation of Testable Reversible Sequential Circuits Optimized Power</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=B.%20Manikandan">B. Manikandan</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Vijayaprabhu"> A. Vijayaprabhu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The conservative reversible gates are used to designed reversible sequential circuits. The sequential circuits are flip-flops and latches. The conservative logic gates are Feynman, Toffoli, and Fredkin. The design of two vectors testable sequential circuits based on conservative logic gates. All sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum- dot cellular automata (QCA) layout of the Fredkin gate. The conservative logic gates are in terms of complexity, speed, and area. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=DET" title="DET">DET</a>, <a href="https://publications.waset.org/abstracts/search?q=QCA" title=" QCA"> QCA</a>, <a href="https://publications.waset.org/abstracts/search?q=reversible%20logic%20gates" title=" reversible logic gates"> reversible logic gates</a>, <a href="https://publications.waset.org/abstracts/search?q=POS" title=" POS"> POS</a>, <a href="https://publications.waset.org/abstracts/search?q=SOP" title=" SOP"> SOP</a>, <a href="https://publications.waset.org/abstracts/search?q=latches" title=" latches"> latches</a>, <a href="https://publications.waset.org/abstracts/search?q=flip%20flops" title=" flip flops"> flip flops</a> </p> <a href="https://publications.waset.org/abstracts/42418/design-and-implementation-of-testable-reversible-sequential-circuits-optimized-power" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/42418.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">304</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">306</span> SPICE Modeling for Evaluation of Distribution System Reliability Indices</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=G.%20N.%20Srinivas">G. N. Srinivas</a>, <a href="https://publications.waset.org/abstracts/search?q=K.%20Raju"> K. Raju</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents Markov processes for determining the reliability indices of distribution system. The continuous Markov modeling is applied to a complex radial distribution system and electrical equivalent circuits are developed for the modeling. In general PSPICE is being used for electrical and electronic circuits and various applications of power system like fault analysis, transient analysis etc. In this paper, the SPICE modeling equivalent circuits which are developed are applied in a novel way to Distribution System reliability analysis. These circuits are simulated using PSPICE software to obtain the state probabilities, the basic and performance indices. Thus the basic indices and the performance indices obtained by this method are compared with those obtained by FMEA technique. The application of the concepts presented in this paper are illustrated and analyzed for IEEE-Roy Billinton Test System (RBTS). <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=distribution%20system" title="distribution system">distribution system</a>, <a href="https://publications.waset.org/abstracts/search?q=Markov%20Model" title=" Markov Model"> Markov Model</a>, <a href="https://publications.waset.org/abstracts/search?q=reliability%20indices" title=" reliability indices"> reliability indices</a>, <a href="https://publications.waset.org/abstracts/search?q=spice%20simulation" title=" spice simulation "> spice simulation </a> </p> <a href="https://publications.waset.org/abstracts/2903/spice-modeling-for-evaluation-of-distribution-system-reliability-indices" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/2903.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">539</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">305</span> Investigation of Threshold Voltage Shift in Gamma Irradiated N-Channel and P-Channel MOS Transistors of CD4007</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=S.%20Boorboor">S. Boorboor</a>, <a href="https://publications.waset.org/abstracts/search?q=S.%20A.%20H.%20Feghhi"> S. A. H. Feghhi</a>, <a href="https://publications.waset.org/abstracts/search?q=H.%20Jafari"> H. Jafari</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from I<sub>D</sub>-V<sub>G</sub> characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=threshold%20voltage%20shift" title="threshold voltage shift">threshold voltage shift</a>, <a href="https://publications.waset.org/abstracts/search?q=MOS%20transistor" title=" MOS transistor"> MOS transistor</a>, <a href="https://publications.waset.org/abstracts/search?q=linear%20extrapolation" title=" linear extrapolation"> linear extrapolation</a>, <a href="https://publications.waset.org/abstracts/search?q=gamma%20irradiation" title=" gamma irradiation"> gamma irradiation</a> </p> <a href="https://publications.waset.org/abstracts/55355/investigation-of-threshold-voltage-shift-in-gamma-irradiated-n-channel-and-p-channel-mos-transistors-of-cd4007" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/55355.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">283</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">304</span> 4-Channel CWDM Optical Transceiver Applying Silicon Photonics Ge-Photodiode and MZ-Modulator</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Do-Won%20Kim">Do-Won Kim</a>, <a href="https://publications.waset.org/abstracts/search?q=Andy%20Eu%20Jin%20Lim"> Andy Eu Jin Lim</a>, <a href="https://publications.waset.org/abstracts/search?q=Raja%20Muthusamy%20Kumarasamy"> Raja Muthusamy Kumarasamy</a>, <a href="https://publications.waset.org/abstracts/search?q=Vishal%20Vinayak"> Vishal Vinayak</a>, <a href="https://publications.waset.org/abstracts/search?q=Jacky%20Wang%20Yu-Shun"> Jacky Wang Yu-Shun</a>, <a href="https://publications.waset.org/abstracts/search?q=Jason%20Liow%20Tsung%20Yang"> Jason Liow Tsung Yang</a>, <a href="https://publications.waset.org/abstracts/search?q=Patrick%20Lo%20Guo%20Qiang"> Patrick Lo Guo Qiang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this study, we demonstrate 4-channel coarse wavelength division multiplexing (CWDM) optical transceiver based on silicon photonics integrated circuits (PIC) of waveguide Ge-photodiode (Ge-PD) and Mach Zehnder (MZ)-modulator. 4-channel arrayed PICs of Ge-PD and MZ-modulator are verified to operate at 25 Gbps/ch achieving 4x25 Gbps of total data rate. 4 bare dies of single-channel commercial electronics ICs (EICs) of trans-impedance amplifier (TIA) for Ge-PD and driver IC for MZ-modulator are packaged with PIC on printed circuit board (PCB) in a chip-on-board (COB) manner. Each single-channel EIC is electrically connected to the one channel of 4-channel PICs by wire bonds to trace. The PICs have 4-channel multiplexer for MZ-modulator and 4-channel demultiplexer for Ge-PD. The 4-channel multiplexer/demultiplexer have echelle gratings for4 CWDM optic signals of which center wavelengths are 1511, 1531, 1553, and 1573 nm. Its insertion loss is around 4dB with over 15dB of extinction ratio.The dimension of 4-channel Ge-PD is 3.6x1.4x0.3mm, and its responsivity is 1A/W with dark current of less than 20 nA.Its measured 3dB bandwidth is around 20GHz. The dimension of the 4-channel MZ-modulator is 3.6x4.8x0.3mm, and its 3dB bandwidth is around 11Ghz at -2V of reverse biasing voltage. It has 2.4V•cmbyVπVL of 6V for π shift to 4 mm length modulator.5x5um of Inversed tapered mode size converter with less than 2dB of coupling loss is used for the coupling of the lensed fiber which has 5um of mode field diameter.The PCB for COB packaging and signal transmission is designed to have 6 layers in the hybrid layer structure. 0.25 mm-thick Rogers Duroid RT5880 is used as the first core dielectric layer for high-speed performance over 25 Gbps. It has 0.017 mm-thick of copper layers and its dielectric constant is 2.2and dissipation factor is 0.0009 at 10 GHz. The dimension of both single ended and differential microstrip transmission lines are calculated using full-wave electromagnetic (EM) field simulator HFSS which RF industry is using most. It showed 3dB bandwidth at around 15GHz in S-parameter measurement using network analyzer. The wire bond length for transmission line and ground connection from EIC is done to have less than 300 µm to minimize the parasitic effect to the system.Single layered capacitors (SLC) of 100pF and 1000pF are connected as close as possible to the EICs for stabilizing the DC biasing voltage by decoupling. Its signal transmission performance is under measurement at 25Gbps achieving 100Gbps by 4chx25Gbps. This work can be applied for the active optical cable (AOC) and quad small form-factor pluggable (QSFP) for high-speed optical interconnections. Its demands are quite large in data centers targeting 100 Gbps, 400 Gbps, and 1 Tbps. As the demands of high-speed AOC and QSFP for the application to intra/inter data centers increase, this silicon photonics based high-speed 4 channel CWDM scheme can have advantages not only in data throughput but also cost effectiveness since it reduces fiber cost dramatically through WDM. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=active%20optical%20cable%28AOC%29" title="active optical cable(AOC)">active optical cable(AOC)</a>, <a href="https://publications.waset.org/abstracts/search?q=4-channel%20coarse%20wavelength%20division%20multiplexing%20%28CWDM%29" title=" 4-channel coarse wavelength division multiplexing (CWDM)"> 4-channel coarse wavelength division multiplexing (CWDM)</a>, <a href="https://publications.waset.org/abstracts/search?q=communication%20system" title=" communication system"> communication system</a>, <a href="https://publications.waset.org/abstracts/search?q=data%20center" title=" data center"> data center</a>, <a href="https://publications.waset.org/abstracts/search?q=ge-photodiode" title=" ge-photodiode"> ge-photodiode</a>, <a href="https://publications.waset.org/abstracts/search?q=Mach%20Zehnder%20%28MZ%29%20modulator" title=" Mach Zehnder (MZ) modulator"> Mach Zehnder (MZ) modulator</a>, <a href="https://publications.waset.org/abstracts/search?q=optical%20interconnections" title="optical interconnections">optical interconnections</a>, <a href="https://publications.waset.org/abstracts/search?q=optical%20transceiver" title=" optical transceiver"> optical transceiver</a>, <a href="https://publications.waset.org/abstracts/search?q=photonics%20integrated%20circuits%20%28PIC%29" title=" photonics integrated circuits (PIC)"> photonics integrated circuits (PIC)</a>, <a href="https://publications.waset.org/abstracts/search?q=quad%20small%20form-factor%20pluggable%20%28QSFP%29" title=" quad small form-factor pluggable (QSFP)"> quad small form-factor pluggable (QSFP)</a>, <a href="https://publications.waset.org/abstracts/search?q=silicon%20photonics" title=" silicon photonics"> silicon photonics</a> </p> <a href="https://publications.waset.org/abstracts/37795/4-channel-cwdm-optical-transceiver-applying-silicon-photonics-ge-photodiode-and-mz-modulator" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/37795.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">418</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">303</span> Design and Characterization of CMOS Readout Circuit for ISFET and ISE Based Sensors</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yuzman%20Yusoff">Yuzman Yusoff</a>, <a href="https://publications.waset.org/abstracts/search?q=Siti%20Noor%20Harun"> Siti Noor Harun</a>, <a href="https://publications.waset.org/abstracts/search?q=Noor%20Shelida%20Salleh"> Noor Shelida Salleh</a>, <a href="https://publications.waset.org/abstracts/search?q=Tan%20Kong%20Yew"> Tan Kong Yew</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=readout%20interface%20circuit%20%28ROIC%29" title="readout interface circuit (ROIC)">readout interface circuit (ROIC)</a>, <a href="https://publications.waset.org/abstracts/search?q=analog%20interface%20circuit" title=" analog interface circuit"> analog interface circuit</a>, <a href="https://publications.waset.org/abstracts/search?q=ion%20sensitive%20field%20effect%20transistor%20%28ISFET%29" title=" ion sensitive field effect transistor (ISFET)"> ion sensitive field effect transistor (ISFET)</a>, <a href="https://publications.waset.org/abstracts/search?q=ion%20selective%20electrode%20%28ISE%29" title=" ion selective electrode (ISE)"> ion selective electrode (ISE)</a>, <a href="https://publications.waset.org/abstracts/search?q=ion%20sensor%20electronics" title=" ion sensor electronics"> ion sensor electronics</a> </p> <a href="https://publications.waset.org/abstracts/1577/design-and-characterization-of-cmos-readout-circuit-for-isfet-and-ise-based-sensors" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/1577.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">314</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">302</span> An Appraisal of Grade 12 Educators’ Difficulties in Understanding Electric Circuits in South Africa: A Case Study of Umgungundlovu District of Kwazulu-Natal</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Akinrogunde%20Omolere%20Moses">Akinrogunde Omolere Moses</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A plethora of studies indicated that teaching and learning of the physical sciences in the Further Education and Training (FET) Phase (Grades 10–12) have long been declared problematic in South Africa. For instance, the results from the National Senior Certificate Matric Examination in Physical Sciences, especially in the questions related to practical skills, more specifically, electric circuits, have been unsatisfactory in the past decades. Learner difficulties in understanding electric circuits are well stated. Thus, this study appraised the difficulties Grade 12 Educators often face in understanding Electric Circuits in Umgungundlovu, District of Kwazulu-Natal, South Africa. A mixed-methods research methodology was employed, while a total of 30 schools were sampled, including Ex-Model C, Independent Exam Board, community, rural, and deep rural schools. Data were collected through semi-structured questionnaires. The findings revealed that a large percentage of the Grade 12 physical sciences educators have difficulties with the Grade 9 and 12 physical sciences content. It was also observed that most of the educators who had difficulties were unable to detect the type of difficulties learners would experience; as a result, they were unable to explain why learners experience such difficulties. The results also showed that only those educators with more experience in teaching the physical sciences were able to provide clearer explanations of both the why and how of dealing with learner difficulties with this section on electric circuits. The study recommended that there is a need to recruit more qualified educators, with at least a Bachelor of Science in Physics in particular, in order to combat the misconceptions. Also, Educators with an inadequate understanding of physical sciences should be orientated in order to meet the standard of classroom practice. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=grade%2012%20educators%27%20difficulties" title="grade 12 educators' difficulties">grade 12 educators' difficulties</a>, <a href="https://publications.waset.org/abstracts/search?q=electric%20circuits" title=" electric circuits"> electric circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=learners%27%20difficulties" title=" learners' difficulties"> learners' difficulties</a>, <a href="https://publications.waset.org/abstracts/search?q=educators%20understanding%20of%20EC." title=" educators understanding of EC."> educators understanding of EC.</a> </p> <a href="https://publications.waset.org/abstracts/189606/an-appraisal-of-grade-12-educators-difficulties-in-understanding-electric-circuits-in-south-africa-a-case-study-of-umgungundlovu-district-of-kwazulu-natal" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/189606.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">32</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">301</span> Structured-Ness and Contextual Retrieval Underlie Language Comprehension</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yao-Ying%20Lai">Yao-Ying Lai</a>, <a href="https://publications.waset.org/abstracts/search?q=Maria%20Pinango"> Maria Pinango</a>, <a href="https://publications.waset.org/abstracts/search?q=Ashwini%20Deo"> Ashwini Deo</a> </p> <p class="card-text"><strong>Abstract:</strong></p> While grammatical devices are essential to language processing, how comprehension utilizes cognitive mechanisms is less emphasized. This study addresses this issue by probing the complement coercion phenomenon: an entity-denoting complement following verbs like begin and finish receives an eventive interpretation. For example, (1) “The queen began the book” receives an agentive reading like (2) “The queen began [reading/writing/etc.…] the book.” Such sentences engender additional processing cost in real-time comprehension. The traditional account attributes this cost to an operation that coerces the entity-denoting complement to an event, assuming that these verbs require eventive complements. However, in closer examination, examples like “Chapter 1 began the book” undermine this assumption. An alternative, Structured Individual (SI) hypothesis, proposes that the complement following aspectual verbs (AspV; e.g. begin, finish) is conceptualized as a structured individual, construed as an axis along various dimensions (e.g. spatial, eventive, temporal, informational). The composition of an animate subject and an AspV such as (1) engenders an ambiguity between an agentive reading along the eventive dimension like (2), and a constitutive reading along the informational/spatial dimension like (3) “[The story of the queen] began the book,” in which the subject is interpreted as a subpart of the complement denotation. Comprehenders need to resolve the ambiguity by searching contextual information, resulting in additional cost. To evaluate the SI hypothesis, a questionnaire was employed. Method: Target AspV sentences such as “Shakespeare began the volume.” were preceded by one of the following types of context sentence: (A) Agentive-biasing, in which an event was mentioned (…writers often read…), (C) Constitutive-biasing, in which a constitutive meaning was hinted (Larry owns collections of Renaissance literature.), (N) Neutral context, which allowed both interpretations. Thirty-nine native speakers of English were asked to (i) rate each context-target sentence pair from a 1~5 scale (5=fully understandable), and (ii) choose possible interpretations for the target sentence given the context. The SI hypothesis predicts that comprehension is harder for the Neutral condition, as compared to the biasing conditions because no contextual information is provided to resolve an ambiguity. Also, comprehenders should obtain the specific interpretation corresponding to the context type. Results: (A) Agentive-biasing and (C) Constitutive-biasing were rated higher than (N) Neutral conditions (p< .001), while all conditions were within the acceptable range (> 3.5 on the 1~5 scale). This suggests that when lacking relevant contextual information, semantic ambiguity decreases comprehensibility. The interpretation task shows that the participants selected the biased agentive/constitutive reading for condition (A) and (C) respectively. For the Neutral condition, the agentive and constitutive readings were chosen equally often. Conclusion: These findings support the SI hypothesis: the meaning of AspV sentences is conceptualized as a parthood relation involving structured individuals. We argue that semantic representation makes reference to spatial structured-ness (abstracted axis). To obtain an appropriate interpretation, comprehenders utilize contextual information to enrich the conceptual representation of the sentence in question. This study connects semantic structure to human’s conceptual structure, and provides a processing model that incorporates contextual retrieval. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=ambiguity%20resolution" title="ambiguity resolution">ambiguity resolution</a>, <a href="https://publications.waset.org/abstracts/search?q=contextual%20retrieval" title=" contextual retrieval"> contextual retrieval</a>, <a href="https://publications.waset.org/abstracts/search?q=spatial%20structured-ness" title=" spatial structured-ness"> spatial structured-ness</a>, <a href="https://publications.waset.org/abstracts/search?q=structured%20individual" title=" structured individual"> structured individual</a> </p> <a href="https://publications.waset.org/abstracts/59376/structured-ness-and-contextual-retrieval-underlie-language-comprehension" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/59376.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">333</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">300</span> Deep Reinforcement Learning Model Using Parameterised Quantum Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Lokes%20Parvatha%20Kumaran%20S.">Lokes Parvatha Kumaran S.</a>, <a href="https://publications.waset.org/abstracts/search?q=Sakthi%20Jay%20Mahenthar%20C."> Sakthi Jay Mahenthar C.</a>, <a href="https://publications.waset.org/abstracts/search?q=Sathyaprakash%20P."> Sathyaprakash P.</a>, <a href="https://publications.waset.org/abstracts/search?q=Jayakumar%20V."> Jayakumar V.</a>, <a href="https://publications.waset.org/abstracts/search?q=Shobanadevi%20A."> Shobanadevi A.</a> </p> <p class="card-text"><strong>Abstract:</strong></p> With the evolution of technology, the need to solve complex computational problems like machine learning and deep learning has shot up. But even the most powerful classical supercomputers find it difficult to execute these tasks. With the recent development of quantum computing, researchers and tech-giants strive for new quantum circuits for machine learning tasks, as present works on Quantum Machine Learning (QML) ensure less memory consumption and reduced model parameters. But it is strenuous to simulate classical deep learning models on existing quantum computing platforms due to the inflexibility of deep quantum circuits. As a consequence, it is essential to design viable quantum algorithms for QML for noisy intermediate-scale quantum (NISQ) devices. The proposed work aims to explore Variational Quantum Circuits (VQC) for Deep Reinforcement Learning by remodeling the experience replay and target network into a representation of VQC. In addition, to reduce the number of model parameters, quantum information encoding schemes are used to achieve better results than the classical neural networks. VQCs are employed to approximate the deep Q-value function for decision-making and policy-selection reinforcement learning with experience replay and the target network. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=quantum%20computing" title="quantum computing">quantum computing</a>, <a href="https://publications.waset.org/abstracts/search?q=quantum%20machine%20learning" title=" quantum machine learning"> quantum machine learning</a>, <a href="https://publications.waset.org/abstracts/search?q=variational%20quantum%20circuit" title=" variational quantum circuit"> variational quantum circuit</a>, <a href="https://publications.waset.org/abstracts/search?q=deep%20reinforcement%20learning" title=" deep reinforcement learning"> deep reinforcement learning</a>, <a href="https://publications.waset.org/abstracts/search?q=quantum%20information%20encoding%20scheme" title=" quantum information encoding scheme"> quantum information encoding scheme</a> </p> <a href="https://publications.waset.org/abstracts/152629/deep-reinforcement-learning-model-using-parameterised-quantum-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/152629.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">133</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">299</span> Pushing the Boundary of Parallel Tractability for Ontology Materialization via Boolean Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Zhangquan%20Zhou">Zhangquan Zhou</a>, <a href="https://publications.waset.org/abstracts/search?q=Guilin%20Qi"> Guilin Qi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Materialization is an important reasoning service for applications built on the Web Ontology Language (OWL). To make materialization efficient in practice, current research focuses on deciding tractability of an ontology language and designing parallel reasoning algorithms. However, some well-known large-scale ontologies, such as YAGO, have been shown to have good performance for parallel reasoning, but they are expressed in ontology languages that are not parallelly tractable, i.e., the reasoning is inherently sequential in the worst case. This motivates us to study the problem of parallel tractability of ontology materialization from a theoretical perspective. That is we aim to identify the ontologies for which materialization is parallelly tractable, i.e., in the NC complexity. Since the NC complexity is defined based on Boolean circuit that is widely used to investigate parallel computing problems, we first transform the problem of materialization to evaluation of Boolean circuits, and then study the problem of parallel tractability based on circuits. In this work, we focus on datalog rewritable ontology languages. We use Boolean circuits to identify two classes of datalog rewritable ontologies (called parallelly tractable classes) such that materialization over them is parallelly tractable. We further investigate the parallel tractability of materialization of a datalog rewritable OWL fragment DHL (Description Horn Logic). Based on the above results, we analyze real-world datasets and show that many ontologies expressed in DHL belong to the parallelly tractable classes. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=ontology%20materialization" title="ontology materialization">ontology materialization</a>, <a href="https://publications.waset.org/abstracts/search?q=parallel%20reasoning" title=" parallel reasoning"> parallel reasoning</a>, <a href="https://publications.waset.org/abstracts/search?q=datalog" title=" datalog"> datalog</a>, <a href="https://publications.waset.org/abstracts/search?q=Boolean%20circuit" title=" Boolean circuit"> Boolean circuit</a> </p> <a href="https://publications.waset.org/abstracts/57402/pushing-the-boundary-of-parallel-tractability-for-ontology-materialization-via-boolean-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/57402.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">271</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">298</span> Analysis of Lightweight Register Hardware Threat</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yang%20Luo">Yang Luo</a>, <a href="https://publications.waset.org/abstracts/search?q=Beibei%20Wang"> Beibei Wang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=side-channel%20analysis" title="side-channel analysis">side-channel analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20Trojan" title=" hardware Trojan"> hardware Trojan</a>, <a href="https://publications.waset.org/abstracts/search?q=register%20transfer%20level" title=" register transfer level"> register transfer level</a>, <a href="https://publications.waset.org/abstracts/search?q=dynamic%20power" title=" dynamic power"> dynamic power</a> </p> <a href="https://publications.waset.org/abstracts/58138/analysis-of-lightweight-register-hardware-threat" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/58138.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">279</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">297</span> Experimental Partial Discharge Localization for Internal Short Circuits of Transformers Windings </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jalal%20M.%20Abdallah">Jalal M. Abdallah </a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents experimental studies carried out on a three phase transformer to investigate and develop the transformer models, which help in testing procedures, describing and evaluating the transformer dielectric conditions process and methods such as: the partial discharge (PD) localization in windings. The measurements are based on the transfer function methods in transformer windings by frequency response analysis (FRA). Numbers of tests conditions were applied to obtain the sensitivity frequency responses of a transformer for different type of faults simulated in a particular phase. The frequency responses were analyzed for the sensitivity of different test conditions to detect and identify the starting of small faults, which are sources of PD. In more detail, the aim is to explain applicability and sensitivity of advanced PD measurements for small short circuits and its localization. The experimental results presented in the paper will help in understanding the sensitivity of FRA measurements in detecting various types of internal winding short circuits in the transformer. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=frequency%20response%20analysis%20%28FRA%29" title="frequency response analysis (FRA)">frequency response analysis (FRA)</a>, <a href="https://publications.waset.org/abstracts/search?q=measurements" title=" measurements"> measurements</a>, <a href="https://publications.waset.org/abstracts/search?q=transfer%20function" title=" transfer function"> transfer function</a>, <a href="https://publications.waset.org/abstracts/search?q=transformer" title=" transformer"> transformer</a> </p> <a href="https://publications.waset.org/abstracts/7119/experimental-partial-discharge-localization-for-internal-short-circuits-of-transformers-windings" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/7119.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">281</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">296</span> A Machine Learning Approach for Detecting and Locating Hardware Trojans</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Kaiwen%20Zheng">Kaiwen Zheng</a>, <a href="https://publications.waset.org/abstracts/search?q=Wanting%20Zhou"> Wanting Zhou</a>, <a href="https://publications.waset.org/abstracts/search?q=Nan%20Tang"> Nan Tang</a>, <a href="https://publications.waset.org/abstracts/search?q=Lei%20Li"> Lei Li</a>, <a href="https://publications.waset.org/abstracts/search?q=Yuanhang%20He"> Yuanhang He</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The integrated circuit industry has become a cornerstone of the information society, finding widespread application in areas such as industry, communication, medicine, and aerospace. However, with the increasing complexity of integrated circuits, Hardware Trojans (HTs) implanted by attackers have become a significant threat to their security. In this paper, we proposed a hardware trojan detection method for large-scale circuits. As HTs introduce physical characteristic changes such as structure, area, and power consumption as additional redundant circuits, we proposed a machine-learning-based hardware trojan detection method based on the physical characteristics of gate-level netlists. This method transforms the hardware trojan detection problem into a machine-learning binary classification problem based on physical characteristics, greatly improving detection speed. To address the problem of imbalanced data, where the number of pure circuit samples is far less than that of HTs circuit samples, we used the SMOTETomek algorithm to expand the dataset and further improve the performance of the classifier. We used three machine learning algorithms, K-Nearest Neighbors, Random Forest, and Support Vector Machine, to train and validate benchmark circuits on Trust-Hub, and all achieved good results. In our case studies based on AES encryption circuits provided by trust-hub, the test results showed the effectiveness of the proposed method. To further validate the method’s effectiveness for detecting variant HTs, we designed variant HTs using open-source HTs. The proposed method can guarantee robust detection accuracy in the millisecond level detection time for IC, and FPGA design flows and has good detection performance for library variant HTs. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=hardware%20trojans" title="hardware trojans">hardware trojans</a>, <a href="https://publications.waset.org/abstracts/search?q=physical%20properties" title=" physical properties"> physical properties</a>, <a href="https://publications.waset.org/abstracts/search?q=machine%20learning" title=" machine learning"> machine learning</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20security" title=" hardware security"> hardware security</a> </p> <a href="https://publications.waset.org/abstracts/164285/a-machine-learning-approach-for-detecting-and-locating-hardware-trojans" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/164285.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">146</span> </span> </div> </div> <ul class="pagination"> <li class="page-item disabled"><span class="page-link">&lsaquo;</span></li> <li class="page-item active"><span class="page-link">1</span></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=biasing%20circuits&page=2">2</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=biasing%20circuits&page=3">3</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=biasing%20circuits&page=4">4</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=biasing%20circuits&page=5">5</a></li> <li class="page-item"><a class="page-link" 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