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id="toc-Standard_MII-sublist" class="vector-toc-list"> <li id="toc-Transmitter_signals" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Transmitter_signals"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>Transmitter signals</span> </div> </a> <ul id="toc-Transmitter_signals-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Receiver_signals" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Receiver_signals"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2</span> <span>Receiver signals</span> </div> </a> <ul id="toc-Receiver_signals-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Management_signals" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Management_signals"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.3</span> <span>Management signals</span> </div> </a> <ul id="toc-Management_signals-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Limitations" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Limitations"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4</span> <span>Limitations</span> </div> </a> <ul id="toc-Limitations-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Reduced_media-independent_interface" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Reduced_media-independent_interface"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Reduced media-independent interface</span> </div> </a> <button aria-controls="toc-Reduced_media-independent_interface-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Reduced media-independent interface subsection</span> </button> <ul id="toc-Reduced_media-independent_interface-sublist" class="vector-toc-list"> <li id="toc-Limitations_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Limitations_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Limitations</span> </div> </a> <ul id="toc-Limitations_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Signal_levels" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Signal_levels"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>Signal levels</span> </div> </a> <ul id="toc-Signal_levels-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Gigabit_media-independent_interface" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Gigabit_media-independent_interface"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Gigabit media-independent interface</span> </div> </a> <button aria-controls="toc-Gigabit_media-independent_interface-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Gigabit media-independent interface subsection</span> </button> <ul id="toc-Gigabit_media-independent_interface-sublist" class="vector-toc-list"> <li id="toc-Transmitter_signals_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Transmitter_signals_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Transmitter signals</span> </div> </a> <ul id="toc-Transmitter_signals_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Receiver_signals_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Receiver_signals_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Receiver signals</span> </div> </a> <ul id="toc-Receiver_signals_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Management_signals_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Management_signals_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Management signals</span> </div> </a> <ul id="toc-Management_signals_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Reduced_gigabit_media-independent_interface" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Reduced_gigabit_media-independent_interface"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Reduced gigabit media-independent interface</span> </div> </a> <ul id="toc-Reduced_gigabit_media-independent_interface-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Serial_gigabit_media-independent_interface" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Serial_gigabit_media-independent_interface"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Serial gigabit media-independent interface</span> </div> </a> <ul id="toc-Serial_gigabit_media-independent_interface-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-High_serial_gigabit_media_independent_interface" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#High_serial_gigabit_media_independent_interface"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>High serial gigabit media independent interface</span> </div> </a> <ul id="toc-High_serial_gigabit_media_independent_interface-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Quad_serial_gigabit_media-independent_interface" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Quad_serial_gigabit_media-independent_interface"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Quad serial gigabit media-independent interface</span> </div> </a> <ul id="toc-Quad_serial_gigabit_media-independent_interface-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-10_gigabit_media-independent_interface" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#10_gigabit_media-independent_interface"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>10 gigabit media-independent interface</span> </div> </a> <ul id="toc-10_gigabit_media-independent_interface-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" 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mw-list-item"><a href="https://de.wikipedia.org/wiki/Media_Independent_Interface" title="Media Independent Interface – German" lang="de" hreflang="de" data-title="Media Independent Interface" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Media_Independent_Interface" title="Media Independent Interface – Dutch" lang="nl" hreflang="nl" data-title="Media Independent Interface" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/Media-independent_interface" title="Media-independent interface – Japanese" lang="ja" hreflang="ja" data-title="Media-independent interface" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Media_Independent_Interface" title="Media Independent Interface – Portuguese" lang="pt" hreflang="pt" data-title="Media Independent Interface" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/MII" title="MII – Russian" lang="ru" hreflang="ru" data-title="MII" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/%E4%BB%8B%E8%B4%A8%E6%97%A0%E5%85%B3%E6%8E%A5%E5%8F%A3" title="介质无关接口 – Chinese" lang="zh" hreflang="zh" data-title="介质无关接口" data-language-autonym="中文" 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The present address (URL) is a <a href="/wiki/Help:Permanent_link" title="Help:Permanent link">permanent link</a> to this version.</b></p><div id="revision-info-current-plain" style="display: none;">Revision as of 17:22, 30 October 2024 by <a href="/wiki/User:Kvng" class="mw-userlink" title="User:Kvng" data-mw-revid="1254366369"><bdi>Kvng</bdi></a> <span class="mw-usertoollinks">(<a href="/wiki/User_talk:Kvng" class="mw-usertoollinks-talk" title="User talk:Kvng">talk</a> | <a href="/wiki/Special:Contributions/Kvng" class="mw-usertoollinks-contribs" title="Special:Contributions/Kvng">contribs</a>)</span> <span class="comment">(avoid bit/s wrap at slash)</span></div></div><div id="mw-revision-nav">(<a href="/w/index.php?title=Media-independent_interface&diff=prev&oldid=1254366369" title="Media-independent interface">diff</a>) <a href="/w/index.php?title=Media-independent_interface&direction=prev&oldid=1254366369" title="Media-independent interface">← Previous revision</a> | Latest revision (diff) | Newer revision → (diff)</div></div></div></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Type of computer networking connection</div> <p><span class="anchor" id="MII"></span><span class="anchor" id="SMII"></span> </p> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Media_independent_interface_(mii)_connector_on_sun_ultra_1.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/79/Media_independent_interface_%28mii%29_connector_on_sun_ultra_1.jpg/220px-Media_independent_interface_%28mii%29_connector_on_sun_ultra_1.jpg" decoding="async" width="220" height="63" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/79/Media_independent_interface_%28mii%29_connector_on_sun_ultra_1.jpg/330px-Media_independent_interface_%28mii%29_connector_on_sun_ultra_1.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/79/Media_independent_interface_%28mii%29_connector_on_sun_ultra_1.jpg/440px-Media_independent_interface_%28mii%29_connector_on_sun_ultra_1.jpg 2x" data-file-width="1443" data-file-height="412" /></a><figcaption>MII connector on a <a href="/wiki/Sun_Ultra_series" class="mw-redirect" title="Sun Ultra series">Sun Ultra 1</a> Creator workstation</figcaption></figure> <p>The <b>media-independent interface</b> (<b>MII</b>) was originally defined as a standard interface to connect a <a href="/wiki/Fast_Ethernet" title="Fast Ethernet">Fast Ethernet</a> (i.e., <span class="nowrap">100 Mbit/s</span>) <a href="/wiki/Medium_access_control" title="Medium access control">medium access control</a> (MAC) block to a <a href="/wiki/PHY#Ethernet_physical_transceiver" class="mw-redirect" title="PHY">PHY chip</a>. The MII is standardized by <a href="/wiki/IEEE_802.3u" class="mw-redirect" title="IEEE 802.3u">IEEE 802.3u</a> and connects different types of PHYs to MACs. Being <i>media independent</i> means that different types of PHY devices for connecting to different media (i.e. <a href="/wiki/Ethernet_over_twisted_pair" title="Ethernet over twisted pair">twisted pair</a>, <a href="/wiki/Fiber_optic" class="mw-redirect" title="Fiber optic">fiber optic</a>, etc.) can be used without redesigning or replacing the MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission medium. </p><p>The MII can be used to connect a MAC to an external PHY using a pluggable connector, or directly to a PHY chip on the same <a href="/wiki/Printed_circuit_board" title="Printed circuit board">PCB</a>. On older PCs the <a href="/wiki/Communications_and_networking_riser" title="Communications and networking riser">CNR connector</a> Type B carried MII signals. </p><p>Network data on the interface is <a href="/wiki/Ethernet_frame" title="Ethernet frame">framed</a> using the IEEE <a href="/wiki/Ethernet" title="Ethernet">Ethernet</a> standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and a <a href="/wiki/Cyclic_redundancy_check" title="Cyclic redundancy check">cyclic redundancy check</a> (CRC). The original MII transfers network data using 4-bit <a href="/wiki/Nibble" title="Nibble">nibbles</a> in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve <span class="nowrap">100 Mbit/s</span> throughput. The original MII design has been extended to support reduced signals and increased speeds. Current variants include: </p> <ul><li><a href="#RMII">Reduced media-independent interface</a> (<b>RMII</b>)</li> <li><a href="#GMII">Gigabit media-independent interface</a> (<b>GMII</b>)</li> <li><a href="#RGMII">Reduced gigabit media-independent interface</a> (<b>RGMII</b>)</li> <li>Serial media-independent interface (<b>SMII</b>)<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup></li> <li><a href="#SGMII">Serial gigabit media-independent interface</a> (<b>serial GMII</b>, <b>SGMII</b>)</li> <li><a href="#HSGMII">High serial gigabit media-independent interface</a> (<b>HSGMII</b>)</li> <li><a href="#QSGMII">Quad serial gigabit media-independent interface</a> (<b>QSGMII</b>)</li> <li><a href="#QSGMII">Penta serial gigabit media-independent interface</a> (<b>PSGMII</b>)</li> <li><a href="#XGMII">10-gigabit media-independent interface</a> (<b>XGMII</b>)</li></ul> <p>The <a href="/wiki/Management_Data_Input/Output" title="Management Data Input/Output">Management Data Input/Output</a> (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using <a href="/wiki/Autonegotiation" title="Autonegotiation">autonegotiation</a>, the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Standard_MII">Standard MII</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=1" title="Edit section: Standard MII"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The standard MII features a small set of registers:<sup id="cite_ref-802.3_2-0" class="reference"><a href="#cite_note-802.3-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Location: Section 22.2.4 "Management functions"">: Section 22.2.4 "Management functions" </span></sup> </p> <ul><li>Basic Mode Configuration (#0)</li> <li>Status Word (#1)</li> <li>PHY Identifier (#2, #3)</li> <li>Auto-Negotiation Advertisement (#4)</li> <li>Auto-Negotiation Link Partner Base Page Ability (#5)</li> <li>Auto-Negotiation Expansion (#6)</li> <li>Auto-Negotiation Next Page Transmit (#7)</li> <li>Auto-Negotiation Link Partner Received Next Page (#8)</li> <li>MASTER-SLAVE Control Register (#9)</li> <li>MASTER-SLAVE Status Register (#10)</li> <li>PSE Control register (#11)</li> <li>PSE Status register (#12)</li> <li>MMD Access Control Register (#13)</li> <li>MMD Access Address Data Register (#14)</li></ul> <p>Register #15 is reserved; registers #16 through #31 are vendor-specific. The registers are used to configure the device and to query the current operating mode.<sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify"><span title="The text near this tag needs further explanation. (June 2020)">further explanation needed</span></a></i>]</sup> </p><p>The MII Status Word is the most useful datum, since it may be used to detect whether an <a href="/wiki/Ethernet_NIC" class="mw-redirect" title="Ethernet NIC">Ethernet NIC</a> is connected to a network. It contains a <a href="/wiki/Bit_field" title="Bit field">bit field</a> with the following information:<sup id="cite_ref-802.3_2-1" class="reference"><a href="#cite_note-802.3-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Location: Section 22.2.4.2.2 "100BASE-X full duplex ability"">: Section 22.2.4.2.2 "100BASE-X full duplex ability" </span></sup> </p> <table class="wikitable"> <tbody><tr> <th>Bit value </th> <th>Meaning </th></tr> <tr> <td>0x8000</td> <td>Capable of <a href="/wiki/100BASE-T4" class="mw-redirect" title="100BASE-T4">100BASE-T4</a> </td></tr> <tr> <td>0x6000</td> <td>Capable of <a href="/wiki/100BASE-TX" class="mw-redirect" title="100BASE-TX">100BASE-TX</a> full/half duplex </td></tr> <tr> <td>0x1800</td> <td>Capable of <a href="/wiki/Classic_Ethernet" title="Classic Ethernet">10BASE-T</a> full/half duplex </td></tr> <tr> <td>0x0600</td> <td>Capable of <a href="/wiki/100BASE-T2" class="mw-redirect" title="100BASE-T2">100BASE-T2</a> full/half duplex </td></tr> <tr> <td>0x0100</td> <td>Extended status (<a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">Gigabit Ethernet</a>) register exists </td></tr> <tr> <td>0x0080</td> <td>Capable of unidirectional operation </td></tr> <tr> <td>0x0040</td> <td>Management frame preamble suppression permitted </td></tr> <tr> <td>0x0020</td> <td><a href="/wiki/Autonegotiation" title="Autonegotiation">Autonegotiation</a> complete </td></tr> <tr> <td>0x0010</td> <td>Remote fault </td></tr> <tr> <td>0x0008</td> <td>Capable of Autonegotiation </td></tr> <tr> <td>0x0004</td> <td>Link established </td></tr> <tr> <td>0x0002</td> <td><a href="/wiki/Jabber_(networking)" class="mw-redirect" title="Jabber (networking)">Jabber</a> detected </td></tr> <tr> <td>0x0001</td> <td>Extended MII registers exist </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Transmitter_signals">Transmitter signals</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=2" title="Edit section: Transmitter signals"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable"> <tbody><tr> <th>Signal name </th> <th>Description </th> <th>Direction </th></tr> <tr> <td>TX_CLK </td> <td>Transmit clock </td> <td>PHY to MAC </td></tr> <tr> <td>TXD0 </td> <td>Transmit data bit 0 (transmitted first) </td> <td>MAC to PHY </td></tr> <tr> <td>TXD1 </td> <td>Transmit data bit 1 </td> <td>MAC to PHY </td></tr> <tr> <td>TXD2 </td> <td>Transmit data bit 2 </td> <td>MAC to PHY </td></tr> <tr> <td>TXD3 </td> <td>Transmit data bit 3 </td> <td>MAC to PHY </td></tr> <tr> <td>TX_EN </td> <td>Transmit enable </td> <td>MAC to PHY </td></tr> <tr> <td>TX_ER </td> <td>Transmit error (optional) </td> <td>MAC to PHY </td></tr></tbody></table> <p>The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for <span class="nowrap">100 Mbit/s</span>, 2.5 MHz for <span class="nowrap">10 Mbit/s</span>). The remaining transmit signals are driven by the MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate without having to be aware of the link speed. The transmit enable signal is held high during frame transmission and low when the transmitter is idle. </p><p>Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort a frame when some problem is detected after transmission has already started. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY. </p><p>More recently, raising transmit error <i>outside</i> frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high) is used to request an <a href="/wiki/Energy-Efficient_Ethernet" title="Energy-Efficient Ethernet">EEE</a>-capable PHY to enter low power mode. </p> <div class="mw-heading mw-heading3"><h3 id="Receiver_signals">Receiver signals</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=3" title="Edit section: Receiver signals"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable"> <tbody><tr> <th>Signal name </th> <th>Description </th> <th>Direction </th></tr> <tr> <td>RX_CLK </td> <td>Receive clock </td> <td>PHY to MAC </td></tr> <tr> <td>RXD0 </td> <td>Receive data bit 0 (received first) </td> <td>PHY to MAC </td></tr> <tr> <td>RXD1 </td> <td>Receive data bit 1 </td> <td>PHY to MAC </td></tr> <tr> <td>RXD2 </td> <td>Receive data bit 2 </td> <td>PHY to MAC </td></tr> <tr> <td>RXD3 </td> <td>Receive data bit 3 </td> <td>PHY to MAC </td></tr> <tr> <td>RX_DV </td> <td>Receive data valid </td> <td>PHY to MAC </td></tr> <tr> <td>RX_ER </td> <td>Receive error </td> <td>PHY to MAC </td></tr> <tr> <td>CRS </td> <td>Carrier sense </td> <td>PHY to MAC </td></tr> <tr> <td>COL </td> <td>Collision detect </td> <td>PHY to MAC </td></tr></tbody></table> <p>The first seven receiver signals are entirely analogous to the transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered (i.e. when the medium is silent), the PHY must present a free-running clock as a substitute. </p><p>The receive data valid signal (RX_DV) is not required to go high immediately when the frame starts, but must do so in time to ensure the "start of frame delimiter" byte is included in the received data. Some of the preamble nibbles may be lost. </p><p>Similar to transmit, raising RX_ER outside a frame is used for special signalling. For receive, two data values are defined: 0b0001 to indicate the link partner is in EEE low power mode, and 0b1110 for a <i>false carrier</i> indication. </p><p>The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists. </p><p>In addition, the MAC may weakly pull-up the COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as indication of an absent/disconnected PHY. </p> <div class="mw-heading mw-heading3"><h3 id="Management_signals">Management signals</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=4" title="Edit section: Management signals"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Management_Data_Input/Output" title="Management Data Input/Output">Management Data Input/Output</a></div> <table class="wikitable"> <tbody><tr> <th>Signal name </th> <th>Description </th> <th>Direction </th></tr> <tr> <td>MDIO </td> <td>Management data </td> <td>Bidirectional </td></tr> <tr> <td>MDC </td> <td>Management data clock </td> <td>MAC to PHY </td></tr></tbody></table> <p>MDC and MDIO constitute a synchronous serial data interface similar to <a href="/wiki/I%C2%B2C" title="I²C">I²C</a>. As with I²C, the interface is a <a href="/wiki/Multidrop_bus" title="Multidrop bus">multidrop bus</a> so MDC and MDIO can be shared among multiple PHYs. </p> <div class="mw-heading mw-heading3"><h3 id="Limitations">Limitations</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=5" title="Edit section: Limitations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals. </p> <div class="mw-heading mw-heading2"><h2 id="Reduced_media-independent_interface"><span class="anchor" id="RMII"></span>Reduced media-independent interface</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=6" title="Edit section: Reduced media-independent interface"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">"RMII" redirects here. Not to be confused with <a href="/wiki/RM2_(disambiguation)" class="mw-redirect mw-disambig" title="RM2 (disambiguation)">RM2</a>.</div> <p>Reduced media-independent interface (RMII) is a standard which was developed to reduce the number of signals required to connect a PHY to a MAC. Reducing pin count reduces cost and complexity for network hardware especially in the context of <a href="/wiki/Microcontroller" title="Microcontroller">microcontrollers</a> with built-in MAC, <a href="/wiki/FPGA" class="mw-redirect" title="FPGA">FPGAs</a>, multiport switches or repeaters, and PC motherboard chipsets. Four things were changed compared to the MII standard to achieve this. These changes mean that RMII uses about half the number of signals compared to MII. </p> <ul><li>The two clocks TXCLK and RXCLK are replaced by a single clock. This clock is an input to the PHY rather than an output, which allows the clock signal to be shared among all PHYs in a multiport device, such as a switch.</li> <li>The clock frequency is doubled from 25 MHz to 50 MHz, while the data paths are narrowed from 4 bits to 2 bits.</li> <li>RXDV and CRS signals are multiplexed into one signal.</li> <li>The COL signal is removed.</li></ul> <table class="wikitable"> <caption>Reduced media-independent interface (RMII) signals </caption> <tbody><tr> <th>Signal name </th> <th>Description </th> <th>Direction </th></tr> <tr> <td>REF_CLK </td> <td>Continuous 50 MHz reference clock </td> <td>Reference clock may be an input on both devices from an external clock source, or may be driven from the MAC to the PHY, or may be driven from the PHY to the MAC </td></tr> <tr> <td>TXD0 </td> <td>Transmit data bit 0 (transmitted first) </td> <td>MAC to PHY </td></tr> <tr> <td>TXD1 </td> <td>Transmit data bit 1 </td> <td>MAC to PHY </td></tr> <tr> <td>TX_EN </td> <td>When high, clock data on TXD0 and TXD1 to the transmitter </td> <td>MAC to PHY </td></tr> <tr> <td>RXD0 </td> <td>Receive data bit 0 (received first) </td> <td>PHY to MAC </td></tr> <tr> <td>RXD1 </td> <td>Receive data bit 1 </td> <td>PHY to MAC </td></tr> <tr> <td>CRS_DV </td> <td>Carrier Sense (CRS) and RX_Data Valid (RX_DV) multiplexed on alternate clock cycles. In <span class="nowrap">10 Mbit/s</span> mode, it alternates every 10 clock cycles. </td> <td>PHY to MAC </td></tr> <tr> <td>RX_ER </td> <td>Receive error (optional on switches) </td> <td>PHY to MAC </td></tr> <tr> <td>MDIO </td> <td>Management data </td> <td>Bidirectional </td></tr> <tr> <td>MDC </td> <td>Management data clock. </td> <td>MAC to PHY </td></tr></tbody></table> <p>MDC and MDIO can be shared among multiple PHYs. </p><p>The receiver signals are referenced to the REF_CLK, same as the transmitter signals. </p><p>This interface requires 9 signals, versus MII's 18. Of those 9, on multiport devices, MDIO, MDC, and REF_CLK may be shared leaving 6 or 7 pins per port. </p><p>RMII requires a <span class="nowrap">50 MHz</span> clock where MII requires a <span class="nowrap">25 MHz</span> clock and data is clocked out two bits at a time vs 4 bits at a time for MII or 1 bit at a time for SNI (<span class="nowrap">10 Mbit/s</span> only). Data is sampled on the rising edge only (i.e. it is <i>not</i> <a href="/wiki/Double-pumped" class="mw-redirect" title="Double-pumped">double-pumped</a>). </p><p>The REF_CLK operates at 50 MHz in both <span class="nowrap">100 Mbit/s</span> mode and <span class="nowrap">10 Mbit/s</span> mode. The transmitting side (PHY or MAC) must keep all signals valid for 10 clock cycles in <span class="nowrap">10 Mbit/s</span> mode. The receiver (PHY or MAC) samples the input signals only every ten cycles in <span class="nowrap">10 Mbit/s</span> mode. </p> <div class="mw-heading mw-heading3"><h3 id="Limitations_2">Limitations</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=7" title="Edit section: Limitations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree. This must instead be communicated over the serial MDIO/MDC interface. There is also no signal which defines whether the interface is in 10 or <span class="nowrap">100 Mbit/s</span> mode, so this must also be handled using the MDIO/MDC interface. Version 1.2 of the RMII Consortium specification states that its MDIO/MDC interface is identical to that specified for MII in IEEE 802.3u. Current revisions of IEEE 802.3 specify a standard MDIO/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex. </p><p>The lack of the RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the <a href="/wiki/Cyclic_redundancy_check" title="Cyclic redundancy check">CRC</a>. The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. This means a slight modification of the definition of CRS: On MII, CRS is asserted for both Rx and Tx frames; on RMII only for Rx frames. This has the consequence that on RMII the two error conditions <i>no carrier</i> and <i>lost carrier</i> cannot be detected, and it is difficult or impossible to support shared media such as <a href="/wiki/10BASE2" title="10BASE2">10BASE2</a> or <a href="/wiki/10BASE5" title="10BASE5">10BASE5</a>. </p><p>Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form a repeater; this is possible, however, with the National DP83848 which supplies the decoded RX_DV as a supplemental signal in RMII mode.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Signal_levels">Signal levels</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=8" title="Edit section: Signal levels"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>TTL <a href="/wiki/Logic_level" title="Logic level">logic levels</a> are used for <span class="nowrap">5 V</span> or <span class="nowrap">3.3 V</span> logic. Input high threshold is <span class="nowrap">2.0 V</span> and low is <span class="nowrap">0.8 V</span>. The specification states that inputs should be <span class="nowrap">5 V</span> tolerant, however, some popular chips with RMII interfaces are not <span class="nowrap">5 V</span> tolerant. Newer devices may support <span class="nowrap">2.5 V</span> and <span class="nowrap">1.8 V</span> logic. </p><p>The RMII signals are treated as <a href="/wiki/Lumped-element_model" title="Lumped-element model">lumped signals</a> rather than <a href="/wiki/Transmission_line" title="Transmission line">transmission lines</a>. However, the IEEE version of the related MII standard specifies <span class="nowrap">68 Ω</span> trace impedance.<sup id="cite_ref-AN-1469_4-0" class="reference"><a href="#cite_note-AN-1469-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> National recommends running <span class="nowrap">50 Ω</span> traces with <span class="nowrap">33 Ω</span> <a href="/wiki/Series_termination" class="mw-redirect" title="Series termination">series termination</a> resistors for either MII or RMII mode to reduce reflections.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (November 2011)">citation needed</span></a></i>]</sup> National also suggests that traces be kept under <span class="nowrap">0.15 m</span> long and matched within <span class="nowrap">0.05 m</span> on length to minimize skew.<sup id="cite_ref-AN-1469_4-1" class="reference"><a href="#cite_note-AN-1469-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 5">: 5 </span></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Gigabit_media-independent_interface"><span class="anchor" id="GMII"></span>Gigabit media-independent interface</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=9" title="Edit section: Gigabit media-independent interface"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The gigabit media-independent interface (GMII) is an interface between the <a href="/wiki/Medium_access_control" title="Medium access control">medium access control</a> (MAC) device and the physical layer (<a href="/wiki/PHY" class="mw-redirect" title="PHY">PHY</a>). The interface operates at speeds up to <span class="nowrap">1000 Mbit/s</span>, implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit, and is backwards compatible with the MII specification and can operate on fall-back speeds of 10 or <span class="nowrap">100 Mbit/s</span>. </p><p>The GMII interface was first defined for 1000BASE-X in IEEE 802.3z-1998 as clause 35, and subsequently incorporated into IEEE 802.3-2000 onwards.<sup id="cite_ref-802.3_2-2" class="reference"><a href="#cite_note-802.3-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Location: Clause 35">: Clause 35 </span></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Transmitter_signals_2">Transmitter signals</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=10" title="Edit section: Transmitter signals"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable"> <tbody><tr> <th>Signal name </th> <th>Description </th></tr> <tr> <td>GTXCLK </td> <td>Clock signal for gigabit TX signals (125 MHz) </td></tr> <tr> <td>TXCLK </td> <td>Clock signal for <span class="nowrap">10/100 Mbit/s</span> signals </td></tr> <tr> <td>TXD[7..0] </td> <td>Data to be transmitted </td></tr> <tr> <td>TXEN </td> <td>Transmitter enable </td></tr> <tr> <td>TXER </td> <td>Transmitter error (used to intentionally corrupt a packet, if necessary) </td></tr></tbody></table> <p>There are two transmitter clocks. The clock used depends on whether the PHY is operating at gigabit or <span class="nowrap">10/100 Mbit/s</span> speeds. For gigabit operation, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. For 10 or <span class="nowrap">100 Mbit/s</span> operation, the TXCLK is supplied by the PHY and is used for synchronizing those signals. This operates at either 25 MHz for <span class="nowrap">100 Mbit/s</span> or 2.5 MHz for <span class="nowrap">10 Mbit/s</span> connections. In contrast, the receiver uses a single clock signal recovered from the incoming data. </p> <div class="mw-heading mw-heading3"><h3 id="Receiver_signals_2">Receiver signals</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=11" title="Edit section: Receiver signals"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable"> <tbody><tr> <th>Signal name </th> <th>Description </th></tr> <tr> <td>RXCLK </td> <td>Received <a href="/wiki/Clock_signal" title="Clock signal">clock signal</a> (recovered from incoming received data) </td></tr> <tr> <td>RXD[7..0] </td> <td>Received data </td></tr> <tr> <td>RXDV </td> <td>Signifies data received is valid </td></tr> <tr> <td>RXER </td> <td>Signifies data received has errors </td></tr> <tr> <td>COL </td> <td>Collision detect (half-duplex connections only) </td></tr> <tr> <td>CS </td> <td>Carrier sense (half-duplex connections only) </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Management_signals_2">Management signals</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=12" title="Edit section: Management signals"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable"> <tbody><tr> <th>Signal name </th> <th>Description </th></tr> <tr> <td>MDC </td> <td>Management interface clock </td></tr> <tr> <td><a href="/wiki/MDIO" class="mw-redirect" title="MDIO">MDIO</a> </td> <td>Management interface I/O bidirectional pin. </td></tr></tbody></table> <p>The management interface controls the behavior of the PHY. It has the same set of registers as the MII, except that register #15 is the Extended Status register.<sup id="cite_ref-802.3_2-3" class="reference"><a href="#cite_note-802.3-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Location: Section 22.2.4 "Management functions"">: Section 22.2.4 "Management functions" </span></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Reduced_gigabit_media-independent_interface"><span class="anchor" id="RGMII"></span>Reduced gigabit media-independent interface</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=13" title="Edit section: Reduced gigabit media-independent interface"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable floatright"> <caption>Supported Ethernet speeds </caption> <tbody><tr> <th>[Mbit/s]</th> <th>[<a href="/wiki/MHz" class="mw-redirect" title="MHz">MHz</a>]</th> <th>Bits/clock cycle </th></tr> <tr> <td align="right">10 </td> <td align="right">2.5 </td> <td align="right">4 </td></tr> <tr> <td align="right">100 </td> <td align="right">25  </td> <td align="right">4 </td></tr> <tr> <td align="right">1000 </td> <td align="right">125  </td> <td align="right">8 </td></tr></tbody></table> <p>The reduced gigabit media-independent interface (RGMII) uses half the number of data pins as are used in the GMII interface. This reduction is achieved by running half as many data lines at double speed, time multiplexing signals and by eliminating non-essential carrier-sense and collision-indication signals. Thus RGMII consists only of 14 pins, as opposed to GMII's 24 to 27. </p><p>Data is clocked on rising and falling edges for <span class="nowrap">1000 Mbit/s</span>, and on rising edges only for <span class="nowrap">10/100 Mbit/s</span>.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER) on the falling edge. The TX_CTL signal likewise carries TXEN on rising edge and (TXEN xor TXER) on the falling edge. This is the case for both <span class="nowrap">1000 Mbit/s</span> and <span class="nowrap">10/100 Mbit/s</span>.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p><p>The transmit clock signal is always provided by the MAC on the TXC line. The receive clock signal is always provided by the PHY on the RXC line.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="Talk:Media-independent interface#Citation request for "The receive clock signal is always provided by the PHY on the RXC line." (August 2020)">citation needed</span></a></i>]</sup> <a href="/wiki/Source-synchronous" title="Source-synchronous">Source-synchronous</a> clocking is used: the clock signal that is output (by either the PHY or the MAC) is synchronous with the data signals. This requires the PCB to be designed to add a 1.5–2 ns delay to the clock signal to meet the setup and hold times on the sink. RGMII v2.0 specifies an optional internal delay, obviating the need for the PCB designer to add delay; this is known as RGMII-ID. </p> <table class="wikitable"> <caption>RGMII signals </caption> <tbody><tr> <th>Signal name </th> <th>Description </th> <th>Direction </th></tr> <tr> <td>TXC </td> <td>Clock signal </td> <td>MAC to PHY </td></tr> <tr> <td>TXD[3..0] </td> <td>Data to be transmitted </td> <td>MAC to PHY </td></tr> <tr> <td>TX_CTL </td> <td>Multiplexing of transmitter enable and transmitter error </td> <td>MAC to PHY </td></tr> <tr> <td>RXC </td> <td>Received <a href="/wiki/Clock_signal" title="Clock signal">clock signal</a> (recovered from incoming received data) </td> <td>PHY to MAC </td></tr> <tr> <td>RXD[3..0] </td> <td>Received data </td> <td>PHY to MAC </td></tr> <tr> <td>RX_CTL </td> <td>Multiplexing of data received is valid and receiver error </td> <td>PHY to MAC </td></tr> <tr> <td>MDC </td> <td>Management interface clock </td> <td>MAC to PHY </td></tr> <tr> <td><a href="/wiki/MDIO" class="mw-redirect" title="MDIO">MDIO</a> </td> <td>Management interface I/O </td> <td>Bidirectional </td></tr></tbody></table> <p>RGMII version 1.3<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> uses 2.5V CMOS,<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> whereas RGMII version 2 uses 1.5V <a href="/wiki/High-speed_transceiver_logic" title="High-speed transceiver logic">HSTL</a>.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Serial_gigabit_media-independent_interface"><span class="anchor" id="SGMII"></span>Serial gigabit media-independent interface</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=14" title="Edit section: Serial gigabit media-independent interface"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The serial gigabit media-independent interface (SGMII) is a variant of MII used for <a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">Gigabit Ethernet</a> but can also carry <span class="nowrap">10/100 Mbit/s</span> Ethernet. </p><p>It uses differential pairs at 625 MHz clock frequency DDR for TX and RX data and TX and RX clocks. It differs from <a href="/wiki/GMII" class="mw-redirect" title="GMII">GMII</a> by its low-power and low pin-count <a href="/wiki/8b/10b" class="mw-redirect" title="8b/10b">8b/10b</a>-coded <a href="/wiki/SerDes" title="SerDes">SerDes</a>. Transmit and receive path each use one differential pair for data and another differential pair for clock. The TX/RX clocks must be generated on device output but are optional on device input (<a href="/wiki/Clock_recovery" title="Clock recovery">clock recovery</a> may be used alternatively). <span class="nowrap">10/100 Mbit/s</span> Ethernet is carried by duplicating data words 100/10 times each, so the clock is always at 625 MHz. </p> <div class="mw-heading mw-heading2"><h2 id="High_serial_gigabit_media_independent_interface"><span class="anchor" id="HSGMII"></span>High serial gigabit media independent interface</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=15" title="Edit section: High serial gigabit media independent interface"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The high serial gigabit media-independent interface (HSGMII) is functionally similar to the SGMII but supports link speeds of up to <span class="nowrap">2.5 Gbit/s</span>. </p> <div class="mw-heading mw-heading2"><h2 id="Quad_serial_gigabit_media-independent_interface"><span class="anchor" id="QSGMII"></span>Quad serial gigabit media-independent interface</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=16" title="Edit section: Quad serial gigabit media-independent interface"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The quad serial gigabit media-independent interface (QSGMII) is a method of combining four SGMII lines into a <span class="nowrap">5 Gbit/s</span> interface. QSGMII, like SGMII, uses <a href="/wiki/Low-voltage_differential_signaling" title="Low-voltage differential signaling">low-voltage differential signaling</a> (LVDS) for the TX and RX data, and a single LVDS clock signal. QSGMII uses significantly fewer signal lines than four separate SGMII connections. </p><p>QSGMII predates <a href="/wiki/NBASE-T" class="mw-redirect" title="NBASE-T">NBASE-T</a> and is used to connect multi-port PHYs to MACs, for example in network routers.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </p><p>The PSGMII (penta serial gigabit media-independent interface) uses the same signal lines as QSGMII, but operates at <span class="nowrap">6.25 Gbit/s</span>, which supports five 1 gigabit/s ports through one MII. </p> <div class="mw-heading mw-heading2"><h2 id="10_gigabit_media-independent_interface"><span class="anchor" id="XGMII"></span>10 gigabit media-independent interface</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=17" title="Edit section: 10 gigabit media-independent interface"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b> with: signal description. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Media-independent_interface&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">July 2023</span>)</i></span></div></td></tr></tbody></table> <p>10 gigabit media-independent interface (XGMII) is a standard defined in <a href="/wiki/IEEE_802.3" title="IEEE 802.3">IEEE 802.3</a> designed for connecting full duplex <a href="/wiki/10_Gigabit_Ethernet" title="10 Gigabit Ethernet">10 Gigabit Ethernet</a> (10GbE) ports to each other and to other electronic devices on a <a href="/wiki/Printed_circuit_board" title="Printed circuit board">printed circuit board</a> (PCB). It is now typically used for on-chip connections. PCB connections are now mostly accomplished with <a href="/wiki/XAUI" title="XAUI">XAUI</a>. XGMII features two 32-bit datapaths (Rx & Tx) and two four-bit control flows (Rxc and Txc), operating at 156.25 MHz <a href="/wiki/Double_data_rate" title="Double data rate">DDR</a> (312.5 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a>).<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=18" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Attachment_Unit_Interface" title="Attachment Unit Interface">Attachment Unit Interface</a> (AUI)</li> <li><a href="/wiki/G.hn" title="G.hn">G.hn</a>, an <a href="/wiki/ITU-T" title="ITU-T">ITU-T</a> recommendation that uses the term MII to refer to the interface between the <a href="/wiki/Data_link_layer" title="Data link layer">data link layer</a> and the <a href="/wiki/Physical_layer" title="Physical layer">physical layer</a>.</li> <li><a href="/wiki/Gigabit_interface_converter" title="Gigabit interface converter">Gigabit interface converter</a> (GBIC)</li> <li><a href="/wiki/List_of_interface_bit_rates" title="List of interface bit rates">List of interface bit rates</a></li> <li><a href="/wiki/Medium-dependent_interface" title="Medium-dependent interface">Medium-dependent interface</a> (MDI)</li> <li><a href="/wiki/Small_form-factor_pluggable_transceiver" class="mw-redirect" title="Small form-factor pluggable transceiver">Small form-factor pluggable transceiver</a> (SFP)</li> <li><a href="/wiki/XAUI" title="XAUI">XAUI</a> – 10 Gigabit Attachment Unit Interface</li> <li><a href="/wiki/XFP_transceiver" title="XFP transceiver">XFP transceiver</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=19" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://ww1.microchip.com/downloads/en/DeviceDoc/KSZ8001L-S-Data-Sheet-DS00003062A.pdf">"KSZ8001L/S 1.8V, 3.3V 10/100BASE-T/TX/FX Physical Layer Transceiver"</a> <span class="cs1-format">(PDF)</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=KSZ8001L%2FS+1.8V%2C+3.3V+10%2F100BASE-T%2FTX%2FFX+Physical+Layer+Transceiver&rft_id=http%3A%2F%2Fww1.microchip.com%2Fdownloads%2Fen%2FDeviceDoc%2FKSZ8001L-S-Data-Sheet-DS00003062A.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMedia-independent+interface" class="Z3988"></span></span> </li> <li id="cite_note-802.3-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-802.3_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-802.3_2-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-802.3_2-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-802.3_2-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><i>IEEE Standard for Ethernet</i>. IEEE 802.3. 31 August 2018. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FIEEESTD.2018.8457469">10.1109/IEEESTD.2018.8457469</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-5044-5090-4" title="Special:BookSources/978-1-5044-5090-4"><bdi>978-1-5044-5090-4</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IEEE+Standard+for+Ethernet&rft.pub=IEEE+802.3&rft.date=2018-08-31&rft_id=info%3Adoi%2F10.1109%2FIEEESTD.2018.8457469&rft.isbn=978-1-5044-5090-4&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMedia-independent+interface" class="Z3988"></span></span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.ti.com/lit/an/snla076a/snla076a.pdf">AN-1405 schematic</a></span> </li> <li id="cite_note-AN-1469-4"><span class="mw-cite-backlink">^ <a href="#cite_ref-AN-1469_4-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-AN-1469_4-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.ti.com/lit/an/snla079d/snla079d.pdf">AN-1469 datasheet</a></span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160303171328/http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf">"Reduced Gigabit Media Independent Interface (RGMII) Version 2.0"</a> <span class="cs1-format">(PDF)</span>. 2002-04-01. Archived from the original on 2016-03-03.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Reduced+Gigabit+Media+Independent+Interface+%28RGMII%29+Version+2.0&rft.date=2002-04-01&rft_id=http%3A%2F%2Fwww.hp.com%2Frnd%2Fpdfs%2FRGMIIv2_0_final_hp.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMedia-independent+interface" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: bot: original URL status unknown (<a href="/wiki/Category:CS1_maint:_bot:_original_URL_status_unknown" title="Category:CS1 maint: bot: original URL status unknown">link</a>)</span></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140413125523/http://www.we-online.de/web/en/index.php/show/media/07_electronic_components/produkte_3/lantiq/Data_Sheet_XWAY_PHY11G_V15_UM_HD_Rev10_VQFN48.pdf">"XWAY PHY11G"</a> <span class="cs1-format">(PDF)</span>. Archived from <a rel="nofollow" class="external text" href="http://www.we-online.de/web/en/index.php/show/media/07_electronic_components/produkte_3/lantiq/Data_Sheet_XWAY_PHY11G_V15_UM_HD_Rev10_VQFN48.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2014-04-13<span class="reference-accessdate">. Retrieved <span class="nowrap">2014-04-11</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=XWAY+PHY11G&rft_id=http%3A%2F%2Fwww.we-online.de%2Fweb%2Fen%2Findex.php%2Fshow%2Fmedia%2F07_electronic_components%2Fprodukte_3%2Flantiq%2FData_Sheet_XWAY_PHY11G_V15_UM_HD_Rev10_VQFN48.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMedia-independent+interface" class="Z3988"></span></span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160303212629/http://www.hp.com/rnd/pdfs/RGMIIv1_3.pdf">"Reduced Gigabit Media Independent Interface (RGMII) Version 1.3"</a> <span class="cs1-format">(PDF)</span>. 2000-12-10. Archived from <a rel="nofollow" class="external text" href="http://www.hp.com/rnd/pdfs/RGMIIv1_3.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2016-03-03.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Reduced+Gigabit+Media+Independent+Interface+%28RGMII%29+Version+1.3&rft.date=2000-12-10&rft_id=http%3A%2F%2Fwww.hp.com%2Frnd%2Fpdfs%2FRGMIIv1_3.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMedia-independent+interface" class="Z3988"></span></span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.jedec.org/sites/default/files/docs/JESD8-5A-01.pdf">"2.5 V ± 0.2 V (Normal Range) and 1.8 V – 2.7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits, JESD8-5A.01"</a> <span class="cs1-format">(PDF)</span>. 2006-06-01.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=2.5+V+%C2%B1+0.2+V+%28Normal+Range%29+and+1.8+V+%E2%80%93+2.7+V+%28Wide+Range%29+Power+Supply+Voltage+and+Interface+Standard+for+Nonterminated+Digital+Integrated+Circuits%2C+JESD8-5A.01&rft.date=2006-06-01&rft_id=http%3A%2F%2Fwww.jedec.org%2Fsites%2Fdefault%2Ffiles%2Fdocs%2FJESD8-5A-01.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMedia-independent+interface" class="Z3988"></span></span> </li> <li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.jedec.org/sites/default/files/docs/jesd8-6.pdf">"High Speed Transceiver Logic (HSTL). A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits, JESD8-6"</a> <span class="cs1-format">(PDF)</span>. 1995-08-01.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=High+Speed+Transceiver+Logic+%28HSTL%29.+A+1.5V+Output+Buffer+Supply+Voltage+Based+Interface+Standard+for+Digital+Integrated+Circuits%2C+JESD8-6&rft.date=1995-08-01&rft_id=http%3A%2F%2Fwww.jedec.org%2Fsites%2Fdefault%2Ffiles%2Fdocs%2Fjesd8-6.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMedia-independent+interface" class="Z3988"></span></span> </li> <li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/powerquicc/3546/1/qsgmii%20specification.pdf">"QSGMII Specification"</a> <span class="cs1-format">(PDF)</span>. Cisco. 2009-08-03<span class="reference-accessdate">. Retrieved <span class="nowrap">2024-10-01</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=QSGMII+Specification&rft.pub=Cisco&rft.date=2009-08-03&rft_id=https%3A%2F%2Fcommunity.nxp.com%2Fpwmxy87654%2Fattachments%2Fpwmxy87654%2Fpowerquicc%2F3546%2F1%2Fqsgmii%2520specification.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMedia-independent+interface" class="Z3988"></span></span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text">IEEE 802.3 clauses 46 & 47</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Media-independent_interface&action=edit&section=20" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://www.ti.com/lit/an/snla076a/snla076a.pdf">Texas Instruments –  AN-1405 DP83848 RMII</a></li> <li><a rel="nofollow" class="external text" href="http://www.ti.com.cn/cn/lit/ds/symlink/dp83848c.pdf">Texas Instruments –  DP83848C PHY Data Sheet</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160303171328/http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf">hp.com –  RGMIIv2_0_final_hp.pdf RGMII 2002-04-01 Version 2.0 </a></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150714164353/http://www.angelfire.com/electronic2/sharads/protocols/MII_Protocols/sgmii.pdf"><i>Serial-GMII Specification Revision 1.7 (ENG-46158)</i></a> <span class="cs1-format">(PDF)</span>, archived from <a rel="nofollow" class="external text" href="http://www.angelfire.com/electronic2/sharads/protocols/MII_Protocols/sgmii.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2015-07-14</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Serial-GMII+Specification+Revision+1.7+%28ENG-46158%29&rft_id=http%3A%2F%2Fwww.angelfire.com%2Felectronic2%2Fsharads%2Fprotocols%2FMII_Protocols%2Fsgmii.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMedia-independent+interface" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20061211171613/http://www.parthus.com/products/platforms/sgmii.php">"CEVA implementation documentation"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.parthus.com/products/platforms/sgmii.php">the original</a> on 2006-12-11.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=CEVA+implementation+documentation&rft_id=http%3A%2F%2Fwww.parthus.com%2Fproducts%2Fplatforms%2Fsgmii.php&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMedia-independent+interface" class="Z3988"></span></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110903061926/http://www.altera.com/support/refdesigns/ip/interface/ref-10gbe.html">Altera 10 Gb Ethernet IP with XGMII and XAUI interfaces </a></li> <li><a rel="nofollow" class="external text" href="http://www.ieee802.org/3/z/public/presentations/nov1996/AIgmitim.pdf">GMII Timing and Electrical Specification </a></li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output 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abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Ethernet" title="Template:Ethernet"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Ethernet" title="Template talk:Ethernet"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Ethernet" title="Special:EditPage/Template:Ethernet"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Ethernet_family_of_local_area_network_technologies" style="font-size:114%;margin:0 4em"><a href="/wiki/Ethernet" title="Ethernet">Ethernet</a> family of <a href="/wiki/Local_area_network" title="Local area network">local area network</a> technologies</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Speeds</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Classic_Ethernet" title="Classic Ethernet">10 Mbit/s</a></li> <li><a href="/wiki/Fast_Ethernet" title="Fast Ethernet">100 Mbit/s</a></li> <li><a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">1 Gbit/s</a></li> <li><a href="/wiki/2.5GBASE-T_and_5GBASE-T" title="2.5GBASE-T and 5GBASE-T">2.5 and 5 Gbit/s</a></li> <li><a href="/wiki/10_Gigabit_Ethernet" title="10 Gigabit Ethernet">10 Gbit/s</a></li> <li><a href="/wiki/25_Gigabit_Ethernet" title="25 Gigabit Ethernet">25 and 50 Gbit/s</a></li> <li><a href="/wiki/100_Gigabit_Ethernet" title="100 Gigabit Ethernet">40 and 100 Gbit/s</a></li> <li><a href="/wiki/Terabit_Ethernet" title="Terabit Ethernet">200, 400, 800 and 1600 Gbit/s</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">General</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Ethernet_physical_layer" title="Ethernet physical layer">Physical layer</a></li> <li><a href="/wiki/Autonegotiation" title="Autonegotiation">Autonegotiation</a></li> <li><a href="/wiki/EtherType" title="EtherType">EtherType</a></li> <li><a href="/wiki/Ethernet_flow_control" title="Ethernet flow control">Flow control</a></li> <li><a href="/wiki/Ethernet_frame" title="Ethernet frame">Frames</a></li> <li><a href="/wiki/Jumbo_frame" title="Jumbo frame">Jumbos</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Organizations</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/IEEE_802.3" title="IEEE 802.3">IEEE 802.3</a></li> <li><a href="/wiki/Ethernet_Alliance" title="Ethernet Alliance">Ethernet Alliance</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Media</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Ethernet_over_fiber" title="Ethernet over fiber">Fiber</a></li> <li><a href="/wiki/Ethernet_over_twisted_pair" title="Ethernet over twisted pair">Twisted pair</a></li> <li><a href="/wiki/Ethernet_over_coax" title="Ethernet over coax">Coaxial</a></li> <li><a href="/wiki/Ethernet_in_the_first_mile" title="Ethernet in the first mile">First mile</a> <ul><li><a href="/wiki/10G-EPON" title="10G-EPON">10G-EPON</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Historic</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Carrier-sense_multiple_access_with_collision_detection" title="Carrier-sense multiple access with collision detection">CSMA/CD</a></li> <li><a href="/wiki/StarLAN" title="StarLAN">StarLAN</a></li> <li><a href="/wiki/10BROAD36" title="10BROAD36">10BROAD36</a></li> <li><a href="/wiki/10BASE-FB" class="mw-redirect" title="10BASE-FB">10BASE-FB</a></li> <li><a href="/wiki/10BASE-FL" class="mw-redirect" title="10BASE-FL">10BASE-FL</a></li> <li><a href="/wiki/10BASE5" title="10BASE5">10BASE5</a></li> <li><a href="/wiki/10BASE2" title="10BASE2">10BASE2</a></li> <li><a href="/wiki/Medium_Attachment_Unit" title="Medium Attachment Unit">MAU</a></li> <li><a href="/wiki/Fiber-optic_inter-repeater_link" class="mw-redirect" title="Fiber-optic inter-repeater link">FOIRL</a></li> <li><a href="/wiki/100BaseVG" title="100BaseVG">100BaseVG</a></li> <li><a href="/wiki/LattisNet" title="LattisNet">LattisNet</a></li> <li><a href="/wiki/Long_Reach_Ethernet" title="Long Reach Ethernet">Long Reach</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Applications</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Audio_over_Ethernet" title="Audio over Ethernet">Audio</a></li> <li><a href="/wiki/Automotive_Ethernet" class="mw-redirect" title="Automotive Ethernet">Automotive</a></li> <li><a href="/wiki/Carrier_Ethernet" title="Carrier Ethernet">Carrier</a></li> <li><a href="/wiki/Data_center_bridging" title="Data center bridging">Data center</a></li> <li><a href="/wiki/Energy-Efficient_Ethernet" title="Energy-Efficient Ethernet">Energy Efficiency</a></li> <li><a href="/wiki/Industrial_Ethernet" title="Industrial Ethernet">Industrial</a></li> <li><a href="/wiki/Metro_Ethernet" title="Metro Ethernet">Metro</a></li> <li><a href="/wiki/Power_over_Ethernet" title="Power over Ethernet">Power</a></li> <li><a href="/wiki/Synchronous_Ethernet" title="Synchronous Ethernet">Synchronous</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Transceiver" title="Transceiver">Transceivers</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Gigabit_interface_converter" title="Gigabit interface converter">GBIC</a></li> <li><a href="/wiki/Small_Form-factor_Pluggable" title="Small Form-factor Pluggable">SFP/SFP+/QSFP/QSFP+/OSFP</a></li> <li><a href="/wiki/XENPAK" title="XENPAK">XENPAK</a>/<a href="/wiki/X2_transceiver" title="X2 transceiver">X2</a></li> <li><a href="/wiki/XFP_transceiver" title="XFP transceiver">XFP</a></li> <li><a href="/wiki/C_form-factor_pluggable" title="C form-factor pluggable">CFP</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Interfaces</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Attachment_Unit_Interface" title="Attachment Unit Interface">AUI</a></li> <li><a href="/wiki/EAD_socket" title="EAD socket">EAD</a></li> <li><a href="/wiki/Medium-dependent_interface" title="Medium-dependent interface">MDI</a></li> <li><a class="mw-selflink selflink">MII</a></li> <li><a href="/wiki/Gigabit_media-independent_interface" class="mw-redirect" title="Gigabit media-independent interface">GMII</a></li> <li><a href="/wiki/10_gigabit_media-independent_interface" class="mw-redirect" title="10 gigabit media-independent interface">XGMII</a></li> <li><a href="/wiki/XAUI" title="XAUI">XAUI</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div> <ul><li><span class="noviewer" typeof="mw:File"><span title="Category"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/16px-Symbol_category_class.svg.png" decoding="async" width="16" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/23px-Symbol_category_class.svg.png 1.5x, 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