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</ul></div></nav><div style="padding-top:10px;text-align:center"> <div id='div-gpt-analog_largeleader'> <script> googletag.cmd.push(function() { googletag.display('div-gpt-analog_largeleader'); }); </script> </div></div><div class="site-inner"><div class="content-sidebar-wrap"><main class="content" id="genesis-content"><article class="post-7764 post type-post status-publish format-standard has-post-thumbnail category-analog-ics category-connectivity category-consumer category-products category-tools tag-agileanalog entry" aria-label="Analog subsystem simplifies integration of multiple analog IPs into ASICs"><header class="entry-header"><h1 class="entry-title">Analog subsystem simplifies integration of multiple analog IPs into ASICs</h1> <p class="entry-meta"><time class="entry-time">April 25, 2023</time> By <span class="entry-author"><a href="https://www.analogictips.com/author/rtraiger/" class="entry-author-link" rel="author"><span class="entry-author-name">Redding Traiger</span></a></span> </p></header><div class="entry-content"><div class="addtoany_share_save_container addtoany_content addtoany_content_top"><div class="a2a_kit a2a_kit_size_16 addtoany_list" data-a2a-url="https://www.analogictips.com/analog-subsystem-simplifies-integration-of-multiple-analog-ips-into-asics/" data-a2a-title="Analog subsystem simplifies integration of multiple analog IPs into ASICs"><a class="a2a_button_facebook" href="https://www.addtoany.com/add_to/facebook?linkurl=https%3A%2F%2Fwww.analogictips.com%2Fanalog-subsystem-simplifies-integration-of-multiple-analog-ips-into-asics%2F&linkname=Analog%20subsystem%20simplifies%20integration%20of%20multiple%20analog%20IPs%20into%20ASICs" title="Facebook" rel="nofollow noopener" target="_blank"></a><a class="a2a_button_x" href="https://www.addtoany.com/add_to/x?linkurl=https%3A%2F%2Fwww.analogictips.com%2Fanalog-subsystem-simplifies-integration-of-multiple-analog-ips-into-asics%2F&linkname=Analog%20subsystem%20simplifies%20integration%20of%20multiple%20analog%20IPs%20into%20ASICs" title="X" rel="nofollow noopener" target="_blank"></a><a class="a2a_button_linkedin" href="https://www.addtoany.com/add_to/linkedin?linkurl=https%3A%2F%2Fwww.analogictips.com%2Fanalog-subsystem-simplifies-integration-of-multiple-analog-ips-into-asics%2F&linkname=Analog%20subsystem%20simplifies%20integration%20of%20multiple%20analog%20IPs%20into%20ASICs" title="LinkedIn" rel="nofollow noopener" target="_blank"></a><a class="a2a_dd addtoany_share_save addtoany_share" href="https://www.addtoany.com/share"></a></div></div><div><img decoding="async" class="alignright wp-image-7765" src="https://www.analogictips.com/wp-content/uploads/2023/04/unnamed-1024x410.png" alt="" width="365" height="146" srcset="https://www.analogictips.com/wp-content/uploads/2023/04/unnamed-1024x410.png 1024w, https://www.analogictips.com/wp-content/uploads/2023/04/unnamed-300x120.png 300w, https://www.analogictips.com/wp-content/uploads/2023/04/unnamed-150x60.png 150w, https://www.analogictips.com/wp-content/uploads/2023/04/unnamed-768x308.png 768w, https://www.analogictips.com/wp-content/uploads/2023/04/unnamed.png 1200w" sizes="(max-width: 365px) 100vw, 365px" />Agile Analog has launched its first range of <a href="https://www.agileanalog.com/">analog subsystems</a>, covering power management, PVT sensing, and sleep management. These innovative, digitally wrapped subsystems significantly reduce the effort required to integrate multiple analog IPs into any ASIC by allowing the IP to be dropped straight into a digital design flow and connected via a standard peripheral bus, such as AMBA APB. The subsystems look just like a normal block of digital IP with the standard interfaces that engineers would expect, making them easy to understand and handle. As a result, time to market, costs, and risk are radically reduced. Initially, the company is introducing three subsystems: agilePMU for power management, agile PVT – PVT sensor, and agileSMU for sleep management.</div> <div></div> <div>The IP blocks within a subsystem are all from Agile Analog’s existing portfolio of customizable analog IPs. This allows each block within the subsystem to be customized to the customer’s exact requirements whilst sitting within the overall digital wrapper. As with all Agile Analog IPs, the digitally wrapped subsystems are process and foundry-agnostic, and each design is optimized for the customer’s specific PDK. Integrating IP within a subsystem further enhances the customer’s design by removing duplicate analog functions, reducing design rule checking (DRC) requirements, and optimizing interconnects. These lead to increased noise immunity, lower power consumption, and smaller area.</div> <div></div> <div>Another key benefit to the customer is that all the verification requirements of the analog to digital, mixed-signal, boundary are performed by Agile Analog. This significantly reduces the customer design and verification time, de-risks the design process, lowers the cost of licensing mixed-signal design tools, and simplifies integration. Customers can now add analog features to provide product differentiation without needing specialist analog and mixed-signal engineers, and the associated costly toolchain.</div> <div></div> <div>Agile Analog’s subsystems are supplied with a full set of supporting collateral, including System Verilog models for easy integration into customers’ existing digital verification flows.</div> <div class="bawmrp"> <h3>You may also like:</h3> <ul> <li style="float:left;width:120px;height:auto;overflow:hidden;list-style:none;border-right: 1px solid #ccc;text-align:center;padding:0px 5px;" class="bawmrp_manual"><a href="https://www.analogictips.com/how-do-comparators-and-op-amps-compare-faq/"><img decoding="async" width="100" height="100" src="https://www.analogictips.com/wp-content/uploads/2023/04/How-do-Comparators-and-Op-Amps-Compare-Figure-2-150x150.jpg" class="attachment-100x100 size-100x100 wp-post-image" alt="" /><br />How do comparators and op amps compare?</a></li> <li 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