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class="vector-toc-link" href="#Microprograms"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4</span> <span>Microprograms</span> </div> </a> <ul id="toc-Microprograms-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Justification" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Justification"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Justification</span> </div> </a> <button aria-controls="toc-Justification-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Justification subsection</span> </button> <ul id="toc-Justification-sublist" class="vector-toc-list"> <li id="toc-Benefits" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Benefits"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Benefits</span> </div> </a> <ul id="toc-Benefits-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-History" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#History"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>History</span> </div> </a> <button aria-controls="toc-History-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle History subsection</span> </button> <ul id="toc-History-sublist" class="vector-toc-list"> <li id="toc-Early_examples" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Early_examples"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Early examples</span> </div> </a> <ul id="toc-Early_examples-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-The_360" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#The_360"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>The 360</span> </div> </a> <ul id="toc-The_360-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Moving_up_the_line" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Moving_up_the_line"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Moving up the line</span> </div> </a> <ul id="toc-Moving_up_the_line-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-RISC_enters" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#RISC_enters"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4</span> <span>RISC enters</span> </div> </a> <ul id="toc-RISC_enters-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Examples" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Examples"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Examples</span> </div> </a> <ul id="toc-Examples-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Implementation" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Implementation"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Implementation</span> </div> </a> <button aria-controls="toc-Implementation-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Implementation subsection</span> </button> <ul id="toc-Implementation-sublist" class="vector-toc-list"> <li id="toc-Horizontal_microcode" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Horizontal_microcode"> <div class="vector-toc-text"> <span class="vector-toc-numb">5.1</span> <span>Horizontal microcode</span> </div> </a> <ul id="toc-Horizontal_microcode-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Vertical_microcode" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Vertical_microcode"> <div class="vector-toc-text"> <span class="vector-toc-numb">5.2</span> <span>Vertical microcode</span> </div> </a> <ul id="toc-Vertical_microcode-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Writable_control_store" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Writable_control_store"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Writable control store</span> </div> </a> <ul id="toc-Writable_control_store-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Comparison_to_VLIW_and_RISC" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Comparison_to_VLIW_and_RISC"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Comparison to VLIW and RISC</span> </div> </a> <ul id="toc-Comparison_to_VLIW_and_RISC-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Micro-operations" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Micro-operations"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Micro-operations</span> </div> </a> <ul id="toc-Micro-operations-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">13</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">Microcode</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 30 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-30" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">30 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%86%D8%B5_%D8%A8%D8%B1%D9%85%D8%AC%D9%8A_%D8%B5%D8%BA%D8%B1%D9%8A" title="نص برمجي صغري – Arabic" lang="ar" hreflang="ar" data-title="نص برمجي صغري" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-az mw-list-item"><a href="https://az.wikipedia.org/wiki/Mikrokod" title="Mikrokod – Azerbaijani" lang="az" hreflang="az" data-title="Mikrokod" data-language-autonym="Azərbaycanca" data-language-local-name="Azerbaijani" class="interlanguage-link-target"><span>Azərbaycanca</span></a></li><li class="interlanguage-link interwiki-bs mw-list-item"><a href="https://bs.wikipedia.org/wiki/Mikroprogram" title="Mikroprogram – Bosnian" lang="bs" hreflang="bs" data-title="Mikroprogram" data-language-autonym="Bosanski" data-language-local-name="Bosnian" class="interlanguage-link-target"><span>Bosanski</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Microcodi" title="Microcodi – Catalan" lang="ca" hreflang="ca" data-title="Microcodi" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-da mw-list-item"><a href="https://da.wikipedia.org/wiki/Mikroprogram" title="Mikroprogram – Danish" lang="da" hreflang="da" data-title="Mikroprogram" data-language-autonym="Dansk" data-language-local-name="Danish" class="interlanguage-link-target"><span>Dansk</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Mikrocode" title="Mikrocode – German" lang="de" hreflang="de" data-title="Mikrocode" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Microc%C3%B3digo" title="Microcódigo – Spanish" lang="es" hreflang="es" data-title="Microcódigo" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eo mw-list-item"><a href="https://eo.wikipedia.org/wiki/Mikrokodo" title="Mikrokodo – Esperanto" lang="eo" hreflang="eo" data-title="Mikrokodo" data-language-autonym="Esperanto" data-language-local-name="Esperanto" class="interlanguage-link-target"><span>Esperanto</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%B1%DB%8C%D8%B2%D8%A8%D8%B1%D9%86%D8%A7%D9%85%D9%87%E2%80%8C%D8%B3%D8%A7%D8%B2%DB%8C" title="ریزبرنامه‌سازی – Persian" lang="fa" hreflang="fa" data-title="ریزبرنامه‌سازی" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Microprogrammation" title="Microprogrammation – French" lang="fr" hreflang="fr" data-title="Microprogrammation" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EB%A7%88%EC%9D%B4%ED%81%AC%EB%A1%9C%EC%BD%94%EB%93%9C" title="마이크로코드 – Korean" lang="ko" hreflang="ko" data-title="마이크로코드" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hy mw-list-item"><a href="https://hy.wikipedia.org/wiki/%D5%84%D5%AB%D5%AF%D6%80%D5%B8%D5%AF%D5%B8%D5%A4" title="Միկրոկոդ – Armenian" lang="hy" hreflang="hy" data-title="Միկրոկոդ" data-language-autonym="Հայերեն" data-language-local-name="Armenian" class="interlanguage-link-target"><span>Հայերեն</span></a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/Mikroprogramiranje" title="Mikroprogramiranje – Croatian" lang="hr" hreflang="hr" data-title="Mikroprogramiranje" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target"><span>Hrvatski</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Microprogrammazione" title="Microprogrammazione – Italian" lang="it" hreflang="it" data-title="Microprogrammazione" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/%D7%9E%D7%99%D7%A7%D7%A8%D7%95%D7%A7%D7%95%D7%93" title="מיקרוקוד – Hebrew" lang="he" hreflang="he" data-title="מיקרוקוד" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-kk mw-list-item"><a href="https://kk.wikipedia.org/wiki/%D0%9A%D3%A9%D0%BB%D0%B4%D0%B5%D0%BD%D0%B5%D2%A3_%D0%BC%D0%B8%D0%BA%D1%80%D0%BE%D0%BA%D0%BE%D0%B4" title="Көлденең микрокод – Kazakh" lang="kk" hreflang="kk" data-title="Көлденең микрокод" data-language-autonym="Қазақша" data-language-local-name="Kazakh" class="interlanguage-link-target"><span>Қазақша</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%AE%E0%B5%88%E0%B4%95%E0%B5%8D%E0%B4%B0%E0%B5%8B%E0%B4%95%E0%B5%8B%E0%B4%A1%E0%B5%8D" title="മൈക്രോകോഡ് – Malayalam" lang="ml" hreflang="ml" data-title="മൈക്രോകോഡ്" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Microcode" title="Microcode – Dutch" lang="nl" hreflang="nl" data-title="Microcode" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/%E3%83%9E%E3%82%A4%E3%82%AF%E3%83%AD%E3%83%97%E3%83%AD%E3%82%B0%E3%83%A9%E3%83%A0%E6%96%B9%E5%BC%8F" title="マイクロプログラム方式 – Japanese" lang="ja" hreflang="ja" data-title="マイクロプログラム方式" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/Mikrokode" title="Mikrokode – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="Mikrokode" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Mikroprogram" title="Mikroprogram – Polish" lang="pl" hreflang="pl" data-title="Mikroprogram" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/%D0%9C%D0%B8%D0%BA%D1%80%D0%BE%D0%BA%D0%BE%D0%B4" title="Микрокод – Russian" lang="ru" hreflang="ru" data-title="Микрокод" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/Microcode" title="Microcode – Simple English" lang="en-simple" hreflang="en-simple" data-title="Microcode" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target"><span>Simple English</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/%D0%9C%D0%B8%D0%BA%D1%80%D0%BE%D0%BF%D1%80%D0%BE%D0%B3%D1%80%D0%B0%D0%BC" title="Микропрограм – Serbian" lang="sr" hreflang="sr" data-title="Микропрограм" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-sh mw-list-item"><a href="https://sh.wikipedia.org/wiki/Mikroprogramiranje" title="Mikroprogramiranje – Serbo-Croatian" lang="sh" hreflang="sh" data-title="Mikroprogramiranje" data-language-autonym="Srpskohrvatski / српскохрватски" data-language-local-name="Serbo-Croatian" class="interlanguage-link-target"><span>Srpskohrvatski / српскохрватски</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/Mikro-ohjelma" title="Mikro-ohjelma – Finnish" lang="fi" hreflang="fi" data-title="Mikro-ohjelma" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/Mikroprogram" title="Mikroprogram – Swedish" lang="sv" hreflang="sv" data-title="Mikroprogram" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/Mikroprogramlama" title="Mikroprogramlama – Turkish" lang="tr" hreflang="tr" data-title="Mikroprogramlama" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/%D0%9C%D1%96%D0%BA%D1%80%D0%BE%D0%BA%D0%BE%D0%B4" title="Мікрокод – Ukrainian" lang="uk" hreflang="uk" data-title="Мікрокод" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/%E5%BE%AE%E7%A8%8B%E5%BA%8F" title="微程序 – Chinese" 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.sidebar-list-title,html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle{background:transparent!important}html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle a{color:var(--color-progressive)!important}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-list-title,html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle{background:transparent!important}html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle a{color:var(--color-progressive)!important}}@media print{body.ns-0 .mw-parser-output .sidebar{display:none!important}}</style><table class="sidebar nomobile nowraplinks" style="margin-top: 0.5em;"><tbody><tr><th class="sidebar-title" style="background-color: rgba(51, 153, 255, 0.15);"><a href="/wiki/Execution_(computing)" title="Execution (computing)">Program execution</a></th></tr><tr><th class="sidebar-heading" style="background-color: rgba(51, 153, 255, 0.15);"> General concepts</th></tr><tr><td class="sidebar-content" style="text-align: left;"> <ul><li><a href="/wiki/Computer_program" title="Computer program">Code</a></li> <li><a href="/wiki/Translator_(computing)" title="Translator (computing)">Translation</a> <ul><li><a href="/wiki/Compiler" title="Compiler">Compiler</a> <ul><li><a href="/wiki/Compile_time" title="Compile time">Compile time</a></li></ul></li> <li><a href="/wiki/Optimizing_compiler" title="Optimizing compiler">Optimizing compiler</a></li></ul></li> <li><a href="/wiki/Intermediate_representation" title="Intermediate representation">Intermediate representation</a> (IR)</li> <li><a href="/wiki/Execution_(computing)" title="Execution (computing)">Execution</a> <ul><li><a href="/wiki/Runtime_system" title="Runtime system">Runtime system</a> <ul><li><a href="/wiki/Execution_(computing)#Runtime" title="Execution (computing)">Runtime</a></li></ul></li> <li><a href="/wiki/Executable" title="Executable">Executable</a></li> <li><a href="/wiki/Interpreter_(computing)" title="Interpreter (computing)">Interpreter</a></li> <li><a href="/wiki/Virtual_machine" title="Virtual machine">Virtual machine</a></li></ul></li></ul></td> </tr><tr><th class="sidebar-heading" style="background-color: rgba(51, 153, 255, 0.15);"> Types of code</th></tr><tr><td class="sidebar-content" style="text-align: left;"> <ul><li><a href="/wiki/Source_code" title="Source code">Source code</a></li> <li><a href="/wiki/Object_code" title="Object code">Object code</a></li> <li><a href="/wiki/Bytecode" title="Bytecode">Bytecode</a></li> <li><a href="/wiki/Machine_code" title="Machine code">Machine code</a></li> <li><a class="mw-selflink selflink">Microcode</a></li></ul></td> </tr><tr><th class="sidebar-heading" style="background-color: rgba(51, 153, 255, 0.15);"> Compilation strategies</th></tr><tr><td class="sidebar-content" style="text-align: left;"> <ul><li><a href="/wiki/Ahead-of-time_compilation" title="Ahead-of-time compilation">Ahead-of-time</a> (AOT)</li> <li><a href="/wiki/Just-in-time_compilation" title="Just-in-time compilation">Just-in-time</a> (JIT) <ul><li><a href="/wiki/Tracing_just-in-time_compilation" title="Tracing just-in-time compilation">Tracing just-in-time</a></li> <li><a href="/wiki/Compile_and_go_system" title="Compile and go system">Compile and go system</a></li></ul></li> <li><a href="/wiki/Precompilation" class="mw-redirect" title="Precompilation">Precompilation</a></li> <li><a href="/wiki/Source-to-source_compiler" title="Source-to-source compiler">Transcompilation</a></li> <li><a href="/wiki/Dynamic_recompilation" title="Dynamic recompilation">Recompilation</a></li></ul></td> </tr><tr><th class="sidebar-heading" style="background-color: rgba(51, 153, 255, 0.15);"> Notable runtimes</th></tr><tr><td class="sidebar-content" style="text-align: left;"> <ul><li><a href="/wiki/Android_Runtime" title="Android Runtime">Android Runtime</a> (ART)</li> <li><a href="/wiki/BEAM_(Erlang_virtual_machine)" title="BEAM (Erlang virtual machine)">BEAM</a> (Erlang)</li> <li><a href="/wiki/Common_Language_Runtime" title="Common Language Runtime">Common Language Runtime</a> (CLR) and <a href="/wiki/Mono_(software)#Code_Execution_Engine" title="Mono (software)">Mono</a></li> <li><a href="/wiki/CPython" title="CPython">CPython</a> and <a href="/wiki/PyPy" title="PyPy">PyPy</a></li> <li><a href="/wiki/Crt0" title="Crt0">crt0</a> (<a href="/wiki/C_(programming_language)" title="C (programming language)">C</a> target-specific initializer)</li> <li><a href="/wiki/Java_virtual_machine" title="Java virtual machine">Java virtual machine</a> (JVM)</li> <li><a href="/wiki/LuaJIT" title="LuaJIT">LuaJIT</a></li> <li><a href="/wiki/Objective-C" title="Objective-C">Objective-C</a> and <a href="/wiki/Swift_(programming_language)" title="Swift (programming language)">Swift</a>'s</li> <li><a href="/wiki/V8_(JavaScript_engine)" title="V8 (JavaScript engine)">V8</a> and <a href="/wiki/Node.js" title="Node.js">Node.js</a></li> <li><a href="/wiki/Zend_Engine" title="Zend Engine">Zend Engine</a> (PHP)</li></ul></td> </tr><tr><th class="sidebar-heading" style="background-color: rgba(51, 153, 255, 0.15);"> Notable compilers & toolchains</th></tr><tr><td class="sidebar-content" style="text-align: left;"> <ul><li><a href="/wiki/GNU_Compiler_Collection" title="GNU Compiler Collection">GNU Compiler Collection</a> (GCC)</li> <li><a href="/wiki/LLVM" title="LLVM">LLVM</a> and <a href="/wiki/Clang" title="Clang">Clang</a></li> <li><a href="/wiki/Microsoft_Visual_C%2B%2B" title="Microsoft Visual C++">MSVC</a></li></ul></td> </tr><tr><td class="sidebar-navbar"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Program_execution" title="Template:Program execution"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Program_execution" title="Template talk:Program execution"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Program_execution" title="Special:EditPage/Template:Program execution"><abbr title="Edit this template">e</abbr></a></li></ul></div></td></tr></tbody></table> <p>In <a href="/wiki/Processor_design" title="Processor design">processor design</a>, <b>microcode</b> serves as an intermediary layer situated between the <a href="/wiki/Central_processing_unit" title="Central processing unit">central processing unit</a> (CPU) hardware and the programmer-visible <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> of a computer, also known as its <a href="/wiki/Machine_code" title="Machine code">machine code</a>.<sup id="cite_ref-Kent2813_1-0" class="reference"><a href="#cite_note-Kent2813-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citing_sources" title="Wikipedia:Citing sources"><span title="This citation requires a reference to the specific page or range of pages in which the material appears. (July 2022)">page needed</span></a></i>]</sup> It consists of a set of hardware-level instructions that implement the higher-level machine code instructions or control internal <a href="/wiki/Finite-state_machine" title="Finite-state machine">finite-state machine</a> sequencing in many <a href="/wiki/Digital_processing" class="mw-redirect" title="Digital processing">digital processing</a> components. While microcode is utilized in <a href="/wiki/Intel" title="Intel">Intel</a> and <a href="/wiki/AMD" title="AMD">AMD</a> general-purpose CPUs in contemporary desktops and laptops, it functions only as a fallback path for scenarios that the faster <a href="/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">hardwired control unit</a> is unable to manage.<sup id="cite_ref-FogMicro_2-0" class="reference"><a href="#cite_note-FogMicro-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p>Housed in special high-speed memory, microcode translates machine instructions, <a href="/wiki/State_machine" class="mw-redirect" title="State machine">state machine</a> data, or other input into sequences of detailed circuit-level operations. It separates the machine instructions from the underlying <a href="/wiki/Electronics" title="Electronics">electronics</a>, thereby enabling greater flexibility in designing and altering instructions. Moreover, it facilitates the construction of complex multi-step instructions, while simultaneously reducing the complexity of computer circuits. The act of writing microcode is often referred to as <i>microprogramming</i>, and the microcode in a specific processor implementation is sometimes termed a <i>microprogram</i>. </p><p>Through extensive microprogramming, <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitectures</a> of smaller scale and simplicity can <a href="/wiki/Emulator" title="Emulator">emulate</a> more robust architectures with wider <a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">word</a> lengths, additional <a href="/wiki/Execution_unit" title="Execution unit">execution units</a>, and so forth. This approach provides a relatively straightforward method of ensuring software compatibility between different products within a processor family. </p><p>Some hardware vendors, notably <a href="/wiki/IBM" title="IBM">IBM</a> and <a href="/wiki/Lenovo" title="Lenovo">Lenovo</a>, use the term <i>microcode</i> interchangeably with <i><a href="/wiki/Firmware" title="Firmware">firmware</a></i>. In this context, all code within a device is termed microcode, whether it is microcode or machine code. For instance, updates to a <a href="/wiki/Hard_disk_drive" title="Hard disk drive">hard disk drive</a>'s microcode often encompass updates to both its microcode and firmware.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=1" title="Edit section: Overview"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Instruction_sets">Instruction sets</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=2" title="Edit section: Instruction sets"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>At the hardware level, processors contain a number of separate areas of circuitry, or "units", that perform different tasks. Commonly found units include the <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">arithmetic logic unit</a> (ALU) which performs instructions such as addition or comparing two numbers, circuits for reading and writing data to external memory, and small areas of onboard memory to store these values while they are being processed. In most designs, additional high-performance memory, the <a href="/wiki/Register_file" title="Register file">register file</a>, is used to store temporary values, not just those needed by the current instruction.<sup id="cite_ref-CPU_4-0" class="reference"><a href="#cite_note-CPU-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p><p>To properly perform an instruction, the various circuits have to be activated in order. For instance, it is not possible to add two numbers if they have not yet been loaded from memory. In <a href="/wiki/RISC" class="mw-redirect" title="RISC">RISC</a> designs, the proper ordering of these instructions is largely up to the programmer, or at least to the <a href="/wiki/Compiler" title="Compiler">compiler</a> of the <a href="/wiki/Programming_language" title="Programming language">programming language</a> they are using. So to add two numbers, for instance, the compiler may output instructions to load one of the values into one register, the second into another, call the addition function in the ALU, and then write the result back out to memory.<sup id="cite_ref-CPU_4-1" class="reference"><a href="#cite_note-CPU-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p><p>As the sequence of instructions needed to complete this higher-level concept, "add these two numbers in memory", may require multiple instructions, this can represent a performance bottleneck if those instructions are stored in <a href="/wiki/Main_memory" class="mw-redirect" title="Main memory">main memory</a>. Reading those instructions one by one is taking up time that could be used to read and write the actual data. For this reason, it is common for non-RISC designs to have many different instructions that differ largely on where they store data. For instance, the <a href="/wiki/MOS_6502" class="mw-redirect" title="MOS 6502">MOS 6502</a> has eight variations of the addition instruction, <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">ADC</code>, which differ only in where they look to find the two operands.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p><p>Using the variation of the instruction, or "<a href="/wiki/Opcode" title="Opcode">opcode</a>", that most closely matches the ultimate operation can reduce the number of instructions to one, saving memory used by the program code and improving performance by leaving the <a href="/wiki/Data_bus" class="mw-redirect" title="Data bus">data bus</a> open for other operations. Internally, however, these instructions are not separate operations, but sequences of the operations the units actually perform. Converting a single instruction read from memory into the sequence of internal actions is the duty of the <a href="/wiki/Control_unit" title="Control unit">control unit</a>, another unit within the processor.<sup id="cite_ref-microcode_6-0" class="reference"><a href="#cite_note-microcode-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Microcode">Microcode</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=3" title="Edit section: Microcode"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The basic idea behind microcode is to replace the custom hardware logic implementing the instruction sequencing with a series of simple instructions run in a "microcode engine" in the processor. Whereas a custom logic system might have a series of diodes and gates that output a series of voltages on various control lines, the microcode engine is connected to these lines instead, and these are turned on and off as the engine reads the microcode instructions in sequence. The microcode instructions are often bit encoded to those lines, for instance, if bit 8 is true, that might mean that the ALU should be paused awaiting data. In this respect microcode is somewhat similar to the paper rolls in a <a href="/wiki/Player_piano" title="Player piano">player piano</a>, where the holes represent which key should be pressed. </p><p>The distinction between custom logic and microcode may seem small, one uses a pattern of diodes and gates to decode the instruction and produce a sequence of signals, whereas the other encodes the signals as microinstructions that are read in sequence to produce the same results. The critical difference is that in a custom logic design, changes to the individual steps require the hardware to be redesigned. Using microcode, all that changes is the code stored in the memory containing the microcode. This makes it much easier to fix problems in a microcode system. It also means that there is no effective limit to the complexity of the instructions, it is only limited by the amount of memory one is willing to use. </p><p>The lowest layer in a computer's software stack is traditionally raw <a href="/wiki/Machine_code" title="Machine code">machine code</a> instructions for the processor. In microcoded processors, fetching and decoding those instructions, and executing them, may be done by microcode. To avoid confusion, each microprogram-related element is differentiated by the <i>micro</i> prefix: microinstruction, microassembler, microprogrammer, etc.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> </p><p>Complex digital processors may also employ more than one (possibly microcode-based) <a href="/wiki/Control_unit" title="Control unit">control unit</a> in order to delegate sub-tasks that must be performed essentially asynchronously in parallel. For example, the <a href="/wiki/VAX_9000" title="VAX 9000">VAX 9000</a> has a hardwired IBox unit to fetch and decode instructions, which it hands to a microcoded EBox unit to be executed,<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> and the <a href="/wiki/VAX_8800" class="mw-redirect" title="VAX 8800">VAX 8800</a> has both a microcoded IBox and a microcoded EBox.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p><p>A high-level programmer, or even an <a href="/wiki/Assembly_language" title="Assembly language">assembly language</a> programmer, does not normally see or change microcode. Unlike machine code, which often retains some <a href="/wiki/Backward_compatibility" title="Backward compatibility">backward compatibility</a> among different processors in a family, microcode only runs on the exact <a href="/wiki/Electronic_circuit" title="Electronic circuit">electronic circuitry</a> for which it is designed, as it constitutes an inherent part of the particular processor design itself. </p> <div class="mw-heading mw-heading3"><h3 id="Design">Design</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=4" title="Edit section: Design"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Engineers normally write the microcode during the design phase of a processor, storing it in a <a href="/wiki/Read-only_memory" title="Read-only memory">read-only memory</a> (ROM) or <a href="/wiki/Programmable_logic_array" title="Programmable logic array">programmable logic array</a> (PLA)<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> structure, or in a combination of both.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> However, machines also exist that have some or all microcode stored in <a href="/wiki/Static_random-access_memory" title="Static random-access memory">static random-access memory</a> (SRAM) or <a href="/wiki/Flash_memory" title="Flash memory">flash memory</a>. This is traditionally denoted as <i>writable <a href="/wiki/Control_store" title="Control store">control store</a></i> in the context of computers, which can be either read-only or <a href="/wiki/Read%E2%80%93write_memory" title="Read–write memory">read–write memory</a>. In the latter case, the CPU initialization process loads microcode into the control store from another storage medium, with the possibility of altering the microcode to correct bugs in the instruction set, or to implement new machine instructions. </p> <div class="mw-heading mw-heading3"><h3 id="Microprograms">Microprograms</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=5" title="Edit section: Microprograms"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Microprograms consist of series of microinstructions, which control the CPU at a very fundamental level of hardware circuitry. For example, a single typical <i>horizontal</i> microinstruction might specify the following operations: </p> <ul><li>Connect register 1 to the <i>A</i> side of the <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">ALU</a></li> <li>Connect register 7 to the <i>B</i> side of the ALU</li> <li>Set the ALU to perform <a href="/wiki/Two%27s_complement" title="Two's complement">two's-complement</a> addition</li> <li>Set the ALU's carry input to zero</li> <li>Store the result value in register 8</li> <li>Update the condition codes from the ALU status flags (<i>negative</i>, <i>zero</i>, <i>overflow</i>, and <i>carry</i>)</li> <li>Microjump to a given <a href="/wiki/Program_counter" title="Program counter">μPC</a> address for the next microinstruction</li></ul> <p>To simultaneously control all processor's features in one cycle, the microinstruction is often wider than 50 bits; e.g., 128 bits on a <a href="/wiki/IBM_System/360_Model_85" title="IBM System/360 Model 85">360/85</a> with an emulator feature. Microprograms are carefully designed and optimized for the fastest possible execution, as a slow microprogram would result in a slow machine instruction and degraded performance for related application programs that use such instructions. </p> <div class="mw-heading mw-heading2"><h2 id="Justification">Justification</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=6" title="Edit section: Justification"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Microcode was originally developed as a simpler method of developing the control logic for a computer. Initially, CPU <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">instruction sets</a> were <a href="/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">hardwired</a>. Each step needed to fetch, decode, and execute the machine instructions (including any operand address calculations, reads, and writes) was controlled directly by <a href="/wiki/Combinational_logic" title="Combinational logic">combinational logic</a> and rather minimal <a href="/wiki/Sequential_circuit" class="mw-redirect" title="Sequential circuit">sequential</a> state machine circuitry. While such hard-wired processors were very efficient, the need for powerful instruction sets with multi-step addressing and complex operations (<i>see below</i>) made them difficult to design and debug; highly encoded and varied-length instructions can contribute to this as well, especially when very irregular encodings are used. </p><p>Microcode simplified the job by allowing much of the processor's behaviour and programming model to be defined via microprogram routines rather than by dedicated circuitry. Even late in the design process, microcode could easily be changed, whereas hard-wired CPU designs were very cumbersome to change. Thus, this greatly facilitated CPU design. </p><p>From the 1940s to the late 1970s, a large portion of programming was done in <a href="/wiki/Assembly_language" title="Assembly language">assembly language</a>; higher-level instructions mean greater programmer productivity, so an important advantage of microcode was the relative ease by which powerful machine instructions can be defined. The ultimate extension of this are "Directly Executable High Level Language" designs, in which each statement of a high-level language such as <a href="/wiki/PL/I" title="PL/I">PL/I</a> is entirely and directly executed by microcode, without compilation. The <a href="/wiki/IBM_Future_Systems_project" title="IBM Future Systems project">IBM Future Systems project</a> and <a href="/wiki/Data_General" title="Data General">Data General</a> Fountainhead Processor are examples of this. During the 1970s, CPU speeds grew more quickly than memory speeds and numerous techniques such as <a href="/wiki/Direct_memory_access" title="Direct memory access">memory block transfer</a>, <a href="/wiki/Prefetching" title="Prefetching">memory pre-fetch</a> and <a href="/wiki/Multi-level_cache" class="mw-redirect" title="Multi-level cache">multi-level caches</a> were used to alleviate this. High-level machine instructions, made possible by microcode, helped further, as fewer more complex machine instructions require less memory bandwidth. For example, an operation on a character string can be done as a single machine instruction, thus avoiding multiple instruction fetches. </p><p>Architectures with instruction sets implemented by complex microprograms included the <a href="/wiki/IBM" title="IBM">IBM</a> <a href="/wiki/System/360" class="mw-redirect" title="System/360">System/360</a> and <a href="/wiki/Digital_Equipment_Corporation" title="Digital Equipment Corporation">Digital Equipment Corporation</a> <a href="/wiki/VAX" title="VAX">VAX</a>. The approach of increasingly complex microcode-implemented instruction sets was later called <a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">complex instruction set computer</a> (CISC). An alternate approach, used in many <a href="/wiki/Microprocessor" title="Microprocessor">microprocessors</a>, is to use one or more <a href="/wiki/Programmable_logic_array" title="Programmable logic array">programmable logic array</a> (PLA) or <a href="/wiki/Read-only_memory" title="Read-only memory">read-only memory</a> (ROM) (instead of combinational logic) mainly for instruction decoding, and let a simple state machine (without much, or any, microcode) do most of the sequencing. The <a href="/wiki/MOS_Technology_6502" title="MOS Technology 6502">MOS Technology 6502</a> is an example of a microprocessor using a PLA for instruction decode and sequencing. The PLA is visible in photomicrographs of the chip,<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> and its operation can be seen in the <a href="/wiki/Transistor" title="Transistor">transistor</a>-level simulation. </p><p>Microprogramming is still used in modern CPU designs. In some cases, after the microcode is debugged in simulation, logic functions are substituted for the control store.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2014)">citation needed</span></a></i>]</sup> Logic functions are often faster and less expensive than the equivalent microprogram memory. </p> <div class="mw-heading mw-heading3"><h3 id="Benefits">Benefits</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=7" title="Edit section: Benefits"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A processor's microprograms operate on a more primitive, totally different, and much more hardware-oriented architecture than the assembly instructions visible to normal programmers. In coordination with the hardware, the microcode implements the programmer-visible architecture. The underlying hardware need not have a fixed relationship to the visible architecture. This makes it easier to implement a given instruction set architecture on a wide variety of underlying hardware micro-architectures. </p><p>The IBM System/360 has a 32-bit architecture with 16 general-purpose registers, but most of the System/360 implementations use hardware that implements a much simpler underlying microarchitecture; for example, the <a href="/wiki/IBM_System/360_Model_30" title="IBM System/360 Model 30">System/360 Model 30</a> has 8-bit data paths to the arithmetic logic unit (ALU) and main memory and implemented the general-purpose registers in a special unit of higher-speed <a href="/wiki/Magnetic-core_memory" title="Magnetic-core memory">core memory</a>, and the <a href="/wiki/IBM_System/360_Model_40" title="IBM System/360 Model 40">System/360 Model 40</a> has 8-bit data paths to the ALU and 16-bit data paths to main memory and also implemented the general-purpose registers in a special unit of higher-speed core memory. The <a href="/wiki/IBM_System/360_Model_50" title="IBM System/360 Model 50">Model 50</a> has full 32-bit data paths and implements the general-purpose registers in a special unit of higher-speed core memory.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> The Model 65 through the Model 195 have larger data paths and implement the general-purpose registers in faster transistor circuits.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (September 2011)">citation needed</span></a></i>]</sup> In this way, microprogramming enabled IBM to design many System/360 models with substantially different hardware and spanning a wide range of cost and performance, while making them all architecturally compatible. This dramatically reduces the number of unique system software programs that must be written for each model. </p><p>A similar approach was used by Digital Equipment Corporation (DEC) in their VAX family of computers. As a result, different VAX processors use different microarchitectures, yet the programmer-visible architecture does not change. </p><p>Microprogramming also reduces the cost of field changes to correct defects (<a href="/wiki/Computer_bug" class="mw-redirect" title="Computer bug">bugs</a>) in the processor; a bug can often be fixed by replacing a portion of the microprogram rather than by changes being made to <a href="/wiki/Hardware_logic" class="mw-redirect" title="Hardware logic">hardware logic</a> and wiring. </p> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=8" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Early_examples">Early examples</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=9" title="Edit section: Early examples"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 1947, the design of the <a href="/wiki/Whirlwind_(computer)" class="mw-redirect" title="Whirlwind (computer)">MIT Whirlwind</a> introduced the concept of a control store as a way to simplify computer design and move beyond <i><a href="/wiki/Ad_hoc" title="Ad hoc">ad hoc</a></i> methods. The control store is a <a href="/wiki/Diode_matrix" title="Diode matrix">diode matrix</a>: a two-dimensional lattice, where one dimension accepts "control time pulses" from the CPU's internal clock, and the other connects to control signals on gates and other circuits. A "pulse distributor" takes the pulses generated by the <a href="/wiki/CPU_clock" class="mw-redirect" title="CPU clock">CPU clock</a> and breaks them up into eight separate time pulses, each of which activates a different row of the lattice. When the row is activated, it activates the control signals connected to it.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> </p><p>In 1951, <a href="/wiki/Maurice_Wilkes" title="Maurice Wilkes">Maurice Wilkes</a><sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> enhanced this concept by adding <i>conditional execution</i>, a concept akin to a <a href="/wiki/Conditional_(programming)" class="mw-redirect" title="Conditional (programming)">conditional</a> in computer software. His initial implementation consisted of a pair of matrices: the first one generated signals in the manner of the Whirlwind control store, while the second matrix selected which row of signals (the microprogram instruction word, so to speak) to invoke on the next cycle. Conditionals were implemented by providing a way that a single line in the control store could choose from alternatives in the second matrix. This made the control signals conditional on the detected internal signal. Wilkes coined the term <i>microprogramming</i> to describe this feature and distinguish it from a simple control store. </p> <div class="mw-heading mw-heading3"><h3 id="The_360">The 360</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=10" title="Edit section: The 360"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/System/360" class="mw-redirect" title="System/360">System/360</a></div> <p>Microcode remained relatively rare in computer design as the cost of the ROM needed to store the code was not significantly different than using a custom control store. This changed through the early 1960s with the introduction of mass-produced <a href="/wiki/Core_memory" class="mw-redirect" title="Core memory">core memory</a> and <a href="/wiki/Core_rope" class="mw-redirect" title="Core rope">core rope</a>, which was far less expensive than dedicated logic based on diode arrays or similar solutions. The first to take real advantage of this was <a href="/wiki/IBM" title="IBM">IBM</a> in their 1964 <a href="/wiki/System/360" class="mw-redirect" title="System/360">System/360</a> series. This allowed the machines to have a very complex instruction set, including operations that matched high-level language constructs like formatting binary values as decimal strings, storing the complex series of instructions needed for this task in low cost memory.<sup id="cite_ref-IBM_16-0" class="reference"><a href="#cite_note-IBM-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </p><p>But the real value in the 360 line was that one could build a series of machines that were completely different internally, yet run the same ISA. For a low-end machine, one might use an 8-bit ALU that requires multiple cycles to complete a single 32-bit addition, while a higher end machine might have a full 32-bit ALU that performs the same addition in a single cycle. These differences could be implemented in control logic, but the cost of implementing a completely different decoder for each machine would be prohibitive. Using microcode meant all that changed was the code in the ROM. For instance, one machine might include a <a href="/wiki/Floating_point_unit" class="mw-redirect" title="Floating point unit">floating point unit</a> and thus its microcode for multiplying two numbers might be only a few lines line, whereas on the same machine without the FPU this would be a program that did the same using multiple additions, and all that changed was the ROM.<sup id="cite_ref-IBM_16-1" class="reference"><a href="#cite_note-IBM-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </p><p>The outcome of this design was that customers could use a low-end model of the family to develop their software, knowing that if more performance was ever needed, they could move to a faster version and nothing else would change. This lowered the barrier to entry and the 360 was a runaway success. By the end of the decade, the use of microcode was <i>de rigueur</i> across the mainframe industry. </p> <div class="mw-heading mw-heading3"><h3 id="Moving_up_the_line">Moving up the line</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=11" title="Edit section: Moving up the line"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Motorola_68000_die.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/fe/Motorola_68000_die.JPG/220px-Motorola_68000_die.JPG" decoding="async" width="220" height="195" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/fe/Motorola_68000_die.JPG/330px-Motorola_68000_die.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/fe/Motorola_68000_die.JPG/440px-Motorola_68000_die.JPG 2x" data-file-width="3651" data-file-height="3228" /></a><figcaption>The microcode (and "nanocode") of the <a href="/wiki/Motorola_68000" title="Motorola 68000">Motorola 68000</a> is stored in the two large square blocks in the upper right and controlled by circuitry to the right of it. It takes up a significant amount of the total chip surface.</figcaption></figure> <p>Early <a href="/wiki/Minicomputer" title="Minicomputer">minicomputers</a> were far too simple to require microcode, and were more similar to earlier mainframes in terms of their instruction sets and the way they were decoded. But it was not long before their designers began using more powerful <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuits</a> that allowed for more complex ISAs. By the mid-1970s, most new minicomputers and <a href="/wiki/Superminicomputer" title="Superminicomputer">superminicomputers</a> were using microcode as well, such as most models of the <a href="/wiki/PDP-11" title="PDP-11">PDP-11</a> and, most notably, most models of the <a href="/wiki/VAX" title="VAX">VAX</a>, which included high-level instruction not unlike those found in the 360.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> </p><p>The same basic evolution occurred with <a href="/wiki/Microprocessor" title="Microprocessor">microprocessors</a> as well. Early designs were extremely simple, and even the more powerful 8-bit designs of the mid-1970s like the <a href="/wiki/Zilog_Z80" title="Zilog Z80">Zilog Z80</a> had instruction sets that were simple enough to be implemented in dedicated logic. By this time, the control logic could be patterned into the same die as the CPU, making the difference in cost between ROM and logic less of an issue. However, it was not long before these companies were also facing the problem of introducing higher-performance designs but still wanting to offer <a href="/wiki/Backward_compatibility" title="Backward compatibility">backward compatibility</a>. Among early examples of microcode in micros was the <a href="/wiki/Intel_8086" title="Intel 8086">Intel 8086</a>.<sup id="cite_ref-microcode_6-1" class="reference"><a href="#cite_note-microcode-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p><p>Among the ultimate implementations of microcode in microprocessors is the <a href="/wiki/Motorola_68000" title="Motorola 68000">Motorola 68000</a>. This offered a highly <a href="/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">orthogonal instruction set</a> with a wide variety of <a href="/wiki/Addressing_mode" title="Addressing mode">addressing modes</a>, all implemented in microcode. This did not come without cost, according to early articles, about 20% of the chip's surface area (and thus cost) is the microcode system.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> and later estimates suggest approximately 23,000 of the systems 68,000 gates were part of the microcode system. </p> <div class="mw-heading mw-heading3"><h3 id="RISC_enters">RISC enters</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=12" title="Edit section: RISC enters"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>While companies continued to compete on the complexity of their instruction sets, and the use of microcode to implement these was unquestioned, in the mid-1970s an internal project in IBM was raising serious questions about the entire concept. As part of a project to develop a high-performance all-digital <a href="/wiki/Telephone_switch" class="mw-redirect" title="Telephone switch">telephone switch</a>, a team led by <a href="/wiki/John_Cocke_(computer_scientist)" title="John Cocke (computer scientist)">John Cocke</a> began examining huge volumes of performance data from their customer's 360 (and <a href="/wiki/System/370" class="mw-redirect" title="System/370">System/370</a>) programs. This led them to notice a curious pattern: when the ISA presented multiple versions of an instruction, the <a href="/wiki/Compiler" title="Compiler">compiler</a> almost always used the simplest one, instead of the one most directly representing the code. They learned that this was because those instructions were always implemented in hardware, and thus run the fastest. Using the other instruction might offer higher performance on some machines, but there was no way to know what machine they were running on. This defeated the purpose of using microcode in the first place, which was to hide these distinctions.<sup id="cite_ref-risc_19-0" class="reference"><a href="#cite_note-risc-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p><p>The team came to a radical conclusion: "Imposing microcode between a computer and its users imposes an expensive overhead in performing the most frequently executed instructions."<sup id="cite_ref-risc_19-1" class="reference"><a href="#cite_note-risc-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p><p>The result of this discovery was what is today known as the <a href="/wiki/RISC" class="mw-redirect" title="RISC">RISC</a> concept. The complex microcode engine and its associated ROM is reduced or eliminated completely, and those circuits instead dedicated to things like additional registers or a wider ALU, which increases the performance of every program. When complex sequences of instructions are needed, this is left to the compiler, which is the entire purpose of using a compiler in the first place. The basic concept was soon picked up by university researchers in California, where simulations suggested such designs would trivially outperform even the fastest conventional designs. It was one such project, at the <a href="/wiki/University_of_California,_Berkeley" title="University of California, Berkeley">University of California, Berkeley</a>, that introduced the term RISC. </p><p>The industry responded to the concept of RISC with both confusion and hostility, including a famous dismissive article by the VAX team at Digital.<sup id="cite_ref-comments_20-0" class="reference"><a href="#cite_note-comments-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> A major point of contention was that implementing the instructions outside of the processor meant it would spend much more time reading those instructions from memory, thereby slowing overall performance no matter how fast the CPU itself ran.<sup id="cite_ref-comments_20-1" class="reference"><a href="#cite_note-comments-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> Proponents pointed out that simulations clearly showed the number of instructions was not much greater, especially when considering compiled code.<sup id="cite_ref-risc_19-2" class="reference"><a href="#cite_note-risc-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p><p>The debate raged until the first commercial RISC designs emerged in the second half of the 1980s, which easily outperformed the most complex designs from other companies. By the late 1980s it was over; even DEC was abandoning microcode for their <a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a> designs, and CISC processors switched to using hardwired circuitry, rather than microcode, to perform many functions. For example, the <a href="/wiki/Intel_80486" class="mw-redirect" title="Intel 80486">Intel 80486</a> uses hardwired circuitry to fetch and decode instructions, using microcode only to execute instructions; register-register move and arithmetic instructions required only one microinstruction, allowing them to be completed in one clock cycle.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> The <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a>'s fetch and decode hardware fetches instructions and decodes them into series of micro-operations that are passed on to the execution unit, which schedules and executes the micro-operations, possibly doing so <a href="/wiki/Out-of-order_execution" title="Out-of-order execution">out-of-order</a>. Complex instructions are implemented by microcode that consists of predefined sequences of micro-operations.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> </p><p>Some processor designs use machine code that runs in a special mode, with special instructions, available only in that mode, that have access to processor-dependent hardware, to implement some low-level features of the instruction set. The DEC Alpha, a pure RISC design, used <a href="/wiki/PALcode" title="PALcode">PALcode</a> to implement features such as <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">translation lookaside buffer</a> (TLB) miss handling and interrupt handling,<sup id="cite_ref-axp-architecture-manual_23-0" class="reference"><a href="#cite_note-axp-architecture-manual-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> as well as providing, for Alpha-based systems running <a href="/wiki/OpenVMS" title="OpenVMS">OpenVMS</a>, instructions requiring interlocked memory access that are similar to instructions provided by the <a href="/wiki/VAX" title="VAX">VAX</a> architecture.<sup id="cite_ref-axp-architecture-manual_23-1" class="reference"><a href="#cite_note-axp-architecture-manual-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> CMOS <a href="/wiki/IBM_System/390" title="IBM System/390">IBM System/390</a> CPUs, starting with the G4 processor, and <a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a> CPUs use <a href="/wiki/Millicode" title="Millicode">millicode</a> to implement some instructions.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Examples">Examples</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=13" title="Edit section: Examples"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>The <a href="/wiki/Analytical_engine" title="Analytical engine">Analytical engine</a> envisioned by <a href="/wiki/Charles_Babbage" title="Charles Babbage">Charles Babbage</a> uses <a href="/wiki/Read-only_memory" title="Read-only memory">pegs inserted into rotating drums</a> to store its internal procedures.</li> <li>The <a href="/wiki/EMIDEC_1100" title="EMIDEC 1100">EMIDEC 1100</a><sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> reputedly uses a hard-wired control store consisting of wires threaded through ferrite cores, known as "the laces".</li> <li>Most models of the IBM System/360 series are microprogrammed: <ul><li>The <a href="/wiki/IBM_System/360_Model_25" title="IBM System/360 Model 25">Model 25</a> is unique among System/360 models in using the top 16 K bytes of core storage to hold the control storage for the microprogram. The 2025 uses a 16-bit microarchitecture with seven control words (or microinstructions). After system maintenance or when changing operating mode, the microcode is loaded from the card reader, tape, or other device.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> The <a href="/wiki/IBM_1410" title="IBM 1410">IBM 1410</a> emulation for this model is loaded this way.</li> <li>The <a href="/wiki/IBM_2030" class="mw-redirect" title="IBM 2030">Model 30</a> uses an 8-bit microarchitecture with only a few hardware registers; everything that the programmer saw is emulated by the microprogram. The microcode for this model is also held on special punched cards, which are stored inside the machine in a dedicated reader per card, called "CROS" units (Capacitor Read-Only Storage).<sup id="cite_ref-360-30-feto_27-0" class="reference"><a href="#cite_note-360-30-feto-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 2–5">: 2–5 </span></sup> Another CROS unit is added for machines ordered with 1401/1440/1460 emulation<sup id="cite_ref-360-30-feto_27-1" class="reference"><a href="#cite_note-360-30-feto-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 4–29">: 4–29 </span></sup> and for machines ordered with 1620 emulation.<sup id="cite_ref-360-30-feto_27-2" class="reference"><a href="#cite_note-360-30-feto-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 4–75">: 4–75 </span></sup></li> <li>The <a href="/wiki/IBM_System/360_Model_40" title="IBM System/360 Model 40">Model 40</a> uses 56-bit control words. The 2040 box implements both the System/360 main processor and the multiplex channel (the I/O processor). This model uses <i>TROS</i> dedicated readers similar to <i>CROS</i> units, but with an inductive pickup (Transformer Read-only Store).</li> <li>The <a href="/wiki/IBM_System/360_Model_50" title="IBM System/360 Model 50">Model 50</a> has two internal datapaths which operated in parallel: a 32-bit datapath used for arithmetic operations, and an 8-bit data path used in some logical operations. The control store uses 90-bit microinstructions.</li> <li>The <a href="/wiki/IBM_System/360_Model_85" title="IBM System/360 Model 85">Model 85</a> has separate instruction fetch (I-unit) and execution (E-unit) to provide high performance. The I-unit is hardware controlled. The E-unit is microprogrammed; the control words are 108 bits wide on a basic 360/85 and wider if an emulator feature is installed.</li></ul></li> <li>The <a href="/wiki/NCR_315" title="NCR 315">NCR 315</a> is microprogrammed with hand wired ferrite cores (a <a href="/wiki/Read-only_memory" title="Read-only memory">ROM</a>) pulsed by a sequencer with conditional execution. Wires routed through the cores are enabled for various data and logic elements in the processor.</li> <li>The Digital Equipment Corporation <a href="/wiki/PDP-9" title="PDP-9">PDP-9</a> processor, KL10 and KS10 <a href="/wiki/PDP-10" title="PDP-10">PDP-10</a> processors, and <a href="/wiki/PDP-11" title="PDP-11">PDP-11</a> processors with the exception of the PDP-11/20, are microprogrammed.<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup></li> <li>Most <a href="/wiki/Data_General_Eclipse" title="Data General Eclipse">Data General Eclipse</a> minicomputers are microprogrammed. The task of writing microcode for the <a href="/wiki/Data_General_Eclipse_MV/8000" title="Data General Eclipse MV/8000">Eclipse MV/8000</a> is detailed in the Pulitzer Prize-winning book titled <i><a href="/wiki/The_Soul_of_a_New_Machine" title="The Soul of a New Machine">The Soul of a New Machine</a></i>.</li> <li>Many systems from <a href="/wiki/Burroughs_Corporation" title="Burroughs Corporation">Burroughs</a> are microprogrammed:</li></ul> <dl><dd><ul><li>The B700 "microprocessor" execute application-level opcodes using sequences of 16-bit microinstructions stored in main memory; each of these is either a register-load operation or mapped to a single 56-bit "nanocode" instruction stored in read-only memory. This allows comparatively simple hardware to act either as a mainframe peripheral controller or to be packaged as a standalone computer.</li> <li>The <a href="/wiki/B1700" class="mw-redirect" title="B1700">B1700</a> is implemented with radically different hardware including bit-addressable main memory but has a similar multi-layer organisation. The operating system preloads the interpreter for whatever language is required. These interpreters present different virtual machines for <a href="/wiki/COBOL" title="COBOL">COBOL</a>, <a href="/wiki/Fortran" title="Fortran">Fortran</a>, etc.</li></ul></dd></dl> <ul><li><a href="/wiki/Microdata_Corporation" title="Microdata Corporation">Microdata</a> produced computers in which the microcode is accessible to the user; this allows the creation of custom assembler level instructions. Microdata's <a href="/wiki/Pick_operating_system" title="Pick operating system">Reality</a> operating system design makes extensive use of this capability.</li> <li>The <a href="/wiki/Xerox_Alto#Architecture" title="Xerox Alto">Xerox Alto</a> workstation used a microcoded design but, unlike many computers, the microcode engine is not hidden from the programmer in a layered design. Applications take advantage of this to accelerate performance.</li> <li>The <a href="/wiki/IBM_System/38" title="IBM System/38">IBM System/38</a> is described as having both <a href="/wiki/IBM_System/38#Microcode" title="IBM System/38">horizontal and vertical microcode</a>.<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> In practice, the processor implements an instruction set architecture named the <i>Internal Microprogrammed Interface</i> (IMPI) using a horizontal microcode format. The so-called vertical microcode layer implements the System/38's hardware-independent <a href="/wiki/IBM_System/38#Machine_Interface" title="IBM System/38">Machine Interface</a> (MI) instruction set by translating MI code to IMPI code and executing it. Prior to the introduction of the <a href="/wiki/IBM_RS64" title="IBM RS64">IBM RS64</a> processor line, early <a href="/wiki/IBM_AS/400" title="IBM AS/400">IBM AS/400</a> systems used the same architecture.<sup id="cite_ref-inside-as400_30-0" class="reference"><a href="#cite_note-inside-as400-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></li> <li>The <a href="/wiki/Nintendo_64" title="Nintendo 64">Nintendo 64</a>'s <a href="/wiki/Reality_Coprocessor" class="mw-redirect" title="Reality Coprocessor">Reality Coprocessor</a> (RCP), which serves as the console's <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">graphics processing unit</a> and audio processor, utilizes microcode; it is possible to implement new effects or tweak the processor to achieve the desired output. Some notable examples of custom RCP microcode include the high-resolution graphics, particle engines, and unlimited draw distances found in <a href="/wiki/Factor_5" title="Factor 5">Factor 5</a>'s <i><a href="/wiki/Indiana_Jones_and_the_Infernal_Machine" title="Indiana Jones and the Infernal Machine">Indiana Jones and the Infernal Machine</a></i>, <i><a href="/wiki/Star_Wars:_Rogue_Squadron" title="Star Wars: Rogue Squadron">Star Wars: Rogue Squadron</a></i>, and <i><a href="/wiki/Star_Wars:_Battle_for_Naboo" class="mw-redirect" title="Star Wars: Battle for Naboo">Star Wars: Battle for Naboo</a></i>;<sup id="cite_ref-Interview:_Battling_the_N64_(Naboo)_31-0" class="reference"><a href="#cite_note-Interview:_Battling_the_N64_(Naboo)-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Indiana_Jones_and_the_Infernal_Machine_32-0" class="reference"><a href="#cite_note-Indiana_Jones_and_the_Infernal_Machine-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> and the <a href="/wiki/Full_motion_video" class="mw-redirect" title="Full motion video">full motion video</a> playback found in <a href="/wiki/Rockstar_San_Diego" title="Rockstar San Diego">Angel Studios</a>' <i><a href="/wiki/Resident_Evil_2" title="Resident Evil 2">Resident Evil 2</a></i>.<sup id="cite_ref-Postmortem_RE2_N64_33-0" class="reference"><a href="#cite_note-Postmortem_RE2_N64-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup></li></ul> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Further information on Nintendo 64 microcode: <a href="/wiki/Nintendo_64_programming_characteristics" class="mw-redirect" title="Nintendo 64 programming characteristics">Nintendo 64 programming characteristics</a> and <a href="/wiki/Nintendo_64_Game_Pak" title="Nintendo 64 Game Pak">Nintendo 64 Game Pak</a></div> <ul><li>The VU0 and VU1 vector units in the <a href="/wiki/Sony" title="Sony">Sony</a> <a href="/wiki/PlayStation_2" title="PlayStation 2">PlayStation 2</a> are microprogrammable; in fact, VU1 is only accessible via microcode for the first several generations of the SDK.</li> <li>The MicroCore Labs <a rel="nofollow" class="external text" href="http://www.microcorelabs.com/mcl86.html">MCL86</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20161103224205/http://www.microcorelabs.com/mcl86.html">Archived</a> 2016-11-03 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> , <a rel="nofollow" class="external text" href="http://www.microcorelabs.com/mcl51.html">MCL51</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170202042033/http://www.microcorelabs.com/mcl51.html">Archived</a> 2017-02-02 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> and <a rel="nofollow" class="external text" href="http://www.microcorelabs.com/mcl65.html">MCL65</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20181221000146/http://www.microcorelabs.com/mcl65.html">Archived</a> 2018-12-21 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> are examples of highly encoded "vertical" microsequencer implementations of the Intel 8086/8088, 8051, and MOS 6502.</li> <li>The <a rel="nofollow" class="external text" href="http://www.bitsavers.org/pdf/digitalScientific/">Digital Scientific Corp.</a> Meta 4 Series 16 computer system was a user-microprogammable system first available in 1970. The microcode had a primarily vertical style with 32-bit microinstructions.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> The instructions were stored on replaceable program boards with a grid of bit positions. One (1) bits were represented by small metal squares that were sensed by amplifiers, zero (0) bits by the absence of the squares.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> The system could be configured with up to 4K 16-bit words of microstore. One of Digital Scientific's products was an emulator for the <a href="/wiki/IBM_1130" title="IBM 1130">IBM 1130</a>.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup></li> <li>The <a href="/wiki/MCP-1600" title="MCP-1600">MCP-1600</a> is a <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a> made by <a href="/wiki/Western_Digital" title="Western Digital">Western Digital</a> from 1975 through the early 1980s. It was used to implement three different computer architectures in microcode: the <a href="/wiki/Pascal_MicroEngine" title="Pascal MicroEngine">Pascal MicroEngine</a>, the <a href="/wiki/WD16" title="WD16">WD16</a>, and the <a href="/wiki/Digital_Equipment_Corporation" title="Digital Equipment Corporation">DEC</a> <a href="/wiki/PDP-11#LSI-11" title="PDP-11">LSI-11</a>, a cost-reduced PDP-11.<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup></li> <li>Earlier <a href="/wiki/X86" title="X86">x86</a> processors are fully microcoded. x86 processors implemented <a href="/wiki/Patchable_microcode" class="mw-redirect" title="Patchable microcode">patchable microcode</a> (patch by <a href="/wiki/BIOS" title="BIOS">BIOS</a> or <a href="/wiki/Operating_system" title="Operating system">operating system</a>) since <a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">Intel P6 microarchitecture</a> and <a href="/wiki/Athlon" title="Athlon">AMD K7 microarchitecture</a>. Such processors implemented microcode ROM and microcode SRAM in their silicon.</li> <li>Many <a href="/wiki/Video_card" class="mw-redirect" title="Video card">video cards</a> and <a href="/wiki/Network_interface_controller" title="Network interface controller">network interface controllers</a> implement patchable microcode (patch by operating system). Such microcode is patched to device's <a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a> or <a href="/wiki/DRAM" class="mw-redirect" title="DRAM">DRAM</a>, for example, <a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR SDRAM</a> of a video card.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Implementation">Implementation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=14" title="Edit section: Implementation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Each microinstruction in a microprogram provides the bits that control the functional elements that internally compose a CPU. The advantage over a hard-wired CPU is that internal CPU control becomes a specialized form of a computer program. Microcode thus transforms a complex electronic design challenge (the control of a CPU) into a less complex programming challenge. To take advantage of this, a CPU is divided into several parts: </p> <ul><li>An <a href="/wiki/I-unit" class="mw-redirect" title="I-unit">I-unit</a> may decode instructions in hardware and determine the microcode address for processing the instruction in parallel with the <a href="/wiki/Execution_unit" title="Execution unit">E-unit</a>.</li> <li>A <a href="/wiki/Microsequencer" title="Microsequencer">microsequencer</a> picks the next word of the control store. A sequencer is mostly a counter, but usually also has some way to jump to a different part of the control store depending on some data, usually data from the <a href="/wiki/Instruction_register" title="Instruction register">instruction register</a> and always some part of the control store. The simplest sequencer is just a register loaded from a few bits of the control store.</li> <li>A <a href="/wiki/Processor_register" title="Processor register">register</a> set is a fast memory containing the data of the central processing unit. It may include registers visible to application programs, such as <a href="/wiki/General-purpose_registers" class="mw-redirect" title="General-purpose registers">general-purpose registers</a> and the <a href="/wiki/Program_counter" title="Program counter">program counter</a>, and may also include other registers that are not easily accessible to the application programmer. Often the register set is a triple-ported <a href="/wiki/Register_file" title="Register file">register file</a>; that is, two registers can be read, and a third written at the same time.</li> <li>An <a href="/wiki/Arithmetic_and_logic_unit" class="mw-redirect" title="Arithmetic and logic unit">arithmetic and logic unit</a> performs calculations, usually addition, logical negation, a right shift, and logical AND. It often performs other functions, as well.</li></ul> <p>There may also be a <a href="/wiki/Memory_address_register" title="Memory address register">memory address register</a> and a <a href="/wiki/Memory_data_register" class="mw-redirect" title="Memory data register">memory data register</a>, used to access the main <a href="/wiki/Computer_storage" class="mw-redirect" title="Computer storage">computer storage</a>. Together, these elements form an "<a href="/wiki/Execution_unit" title="Execution unit">execution unit</a>". Most modern <a href="/wiki/Central_processing_unit" title="Central processing unit">CPUs</a> have several execution units. Even simple computers usually have one unit to read and write memory, and another to execute user code. These elements could often be brought together as a single chip. This chip comes in a fixed width that would form a "slice" through the execution unit. These are known as "<a href="/wiki/Bit_slicing" title="Bit slicing">bit slice</a>" chips. The <a href="/wiki/AMD_Am2900" title="AMD Am2900">AMD Am2900</a> family is one of the best known examples of bit slice elements.<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> The parts of the execution units and the whole execution units are interconnected by a bundle of wires called a <a href="/wiki/Computer_bus" class="mw-redirect" title="Computer bus">bus</a>. </p><p>Programmers develop microprograms, using basic software tools. A <a href="/wiki/Microassembler" title="Microassembler">microassembler</a> allows a programmer to define the table of bits symbolically. Because of its close relationship to the underlying architecture, "microcode has several properties that make it difficult to generate using a compiler."<sup id="cite_ref-Kent2813_1-1" class="reference"><a href="#cite_note-Kent2813-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> A <a href="/wiki/Simulator" class="mw-redirect" title="Simulator">simulator</a> program is intended to execute the bits in the same way as the electronics, and allows much more freedom to debug the microprogram. After the microprogram is finalized, and extensively tested, it is sometimes used as the input to a computer program that constructs logic to produce the same data.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (February 2018)">citation needed</span></a></i>]</sup> This program is similar to those used to optimize a <a href="/wiki/Programmable_logic_device" title="Programmable logic device">programmable logic array</a>. Even without fully optimal logic, heuristically optimized logic can vastly reduce the number of transistors from the number needed for a <a href="/wiki/Read-only_memory" title="Read-only memory">read-only memory</a> (ROM) control store. This reduces the cost to produce, and the electricity used by, a CPU. </p><p>Microcode can be characterized as <i>horizontal</i> or <i>vertical</i>, referring primarily to whether each microinstruction controls CPU elements with little or no decoding (horizontal microcode)<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> or requires extensive decoding by <a href="/wiki/Combinatorial_logic" class="mw-redirect" title="Combinatorial logic">combinatorial logic</a> before doing so (vertical microcode). Consequently, each horizontal microinstruction is wider (contains more bits) and occupies more storage space than a vertical microinstruction. </p> <div class="mw-heading mw-heading3"><h3 id="Horizontal_microcode">Horizontal microcode</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=15" title="Edit section: Horizontal microcode"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>"Horizontal microcode has several discrete micro-operations that are combined in a single microinstruction for simultaneous operation."<sup id="cite_ref-Kent2813_1-2" class="reference"><a href="#cite_note-Kent2813-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> Horizontal microcode is typically contained in a fairly wide control store; it is not uncommon for each word to be 108 bits or more. On each tick of a sequencer clock a microcode word is read, decoded, and used to control the functional elements that make up the CPU. </p><p>In a typical implementation a horizontal microprogram word comprises fairly tightly defined groups of bits. For example, one simple arrangement might be: </p> <table class="wikitable"> <tbody><tr> <td>Register source A</td> <td>Register source B</td> <td>Destination register</td> <td><a href="/wiki/Arithmetic_and_logic_unit" class="mw-redirect" title="Arithmetic and logic unit">Arithmetic and logic unit</a> operation</td> <td>Type of jump</td> <td>Jump address </td></tr></tbody></table> <p>For this type of micromachine to implement a JUMP instruction with the address following the opcode, the microcode might require two clock ticks. The engineer designing it would write microassembler source code looking something like this: </p> <div class="mw-highlight mw-highlight-lang-ucode mw-content-ltr" dir="ltr"><pre><span></span><span class="err"> </span><span class="c"># Any line starting with a number-sign is a comment</span> <span class="err"> </span><span class="c"># This is just a label, the ordinary way assemblers symbolically represent a </span> <span class="err"> </span><span class="c"># memory address.</span> InstructionJUMP<span class="p">:</span> <span class="err"> </span><span class="c"># To prepare for the next instruction, the instruction-decode microcode has already</span> <span class="err"> </span><span class="c"># moved the program counter to the memory address register. This instruction fetches</span> <span class="err"> </span><span class="c"># the target address of the jump instruction from the memory word following the</span> <span class="err"> </span><span class="c"># jump opcode, by copying from the memory data register to the memory address register.</span> <span class="err"> </span><span class="c"># This gives the memory system two clock ticks to fetch the next </span> <span class="err"> </span><span class="c"># instruction to the memory data register for use by the instruction decode.</span> <span class="err"> </span><span class="c"># The sequencer instruction "next" means just add 1 to the control word address.</span> MDR<span class="p">,</span> NONE<span class="p">,</span> MAR<span class="p">,</span> COPY<span class="p">,</span> NEXT<span class="p">,</span> NONE <span class="err"> </span><span class="c"># This places the address of the next instruction into the PC.</span> <span class="err"> </span><span class="c"># This gives the memory system a clock tick to finish the fetch started on the</span> <span class="err"> </span><span class="c"># previous microinstruction.</span> <span class="err"> </span><span class="c"># The sequencer instruction is to jump to the start of the instruction decode.</span> MAR<span class="p">,</span> <span class="mi">1</span><span class="p">,</span> PC<span class="p">,</span> ADD<span class="p">,</span> JMP<span class="p">,</span> InstructionDecode <span class="err"> </span><span class="c"># The instruction decode is not shown, because it is usually a mess, very particular</span> <span class="err"> </span><span class="c"># to the exact processor being emulated. Even this example is simplified.</span> <span class="err"> </span><span class="c"># Many CPUs have several ways to calculate the address, rather than just fetching</span> <span class="err"> </span><span class="c"># it from the word following the op-code. Therefore, rather than just one</span> <span class="err"> </span><span class="c"># jump instruction, those CPUs have a family of related jump instructions.</span> </pre></div> <p>For each tick it is common to find that only some portions of the CPU are used, with the remaining groups of bits in the microinstruction being no-ops. With careful design of hardware and microcode, this property can be exploited to parallelise operations that use different areas of the CPU; for example, in the case above, the ALU is not required during the first tick, so it could potentially be used to complete an earlier arithmetic instruction. </p> <div class="mw-heading mw-heading3"><h3 id="Vertical_microcode">Vertical microcode</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=16" title="Edit section: Vertical microcode"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In vertical microcode, each microinstruction is significantly encoded, that is, the bit fields generally pass through intermediate combinatory logic that, in turn, generates the control and sequencing signals for internal CPU elements (ALU, registers, etc.). This is in contrast with horizontal microcode, in which the bit fields either directly produce the control and sequencing signals or are only minimally encoded. Consequently, vertical microcode requires smaller instruction lengths and less storage, but requires more time to decode, resulting in a slower CPU clock.<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </p><p>Some vertical microcode is just the assembly language of a simple conventional computer that is emulating a more complex computer. Some processors, such as <a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a> processors and the CMOS microprocessors on later IBM mainframes <a href="/wiki/System/390" class="mw-redirect" title="System/390">System/390</a> and <a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a>, use machine code, running in a special mode that gives it access to special instructions, special registers, and other hardware resources unavailable to regular machine code, to implement some instructions and other functions,<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> such as page table walks on Alpha processors.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> This is called <a href="/wiki/PALcode" title="PALcode">PALcode</a> on Alpha processors and <a href="/wiki/Millicode" title="Millicode">millicode</a> on IBM mainframe processors. </p><p>Another form of vertical microcode has two fields: </p> <table class="wikitable"> <tbody><tr> <td>Field select</td> <td>Field value </td></tr></tbody></table> <p>The <i>field select</i> selects which part of the CPU will be controlled by this word of the control store. The <i>field value</i> controls that part of the CPU. With this type of microcode, a designer explicitly chooses to make a slower CPU to save money by reducing the unused bits in the control store; however, the reduced complexity may increase the CPU's clock frequency, which lessens the effect of an increased number of cycles per instruction. </p><p>As transistors grew cheaper, horizontal microcode came to dominate the design of CPUs using microcode, with vertical microcode being used less often. </p><p>When both vertical and horizontal microcode are used, the horizontal microcode may be referred to as <i>nanocode</i> or <i>picocode</i>.<sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Writable_control_store"><span class="anchor" id="IML"></span>Writable control store</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=17" title="Edit section: Writable control store"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Writable_control_store" class="mw-redirect" title="Writable control store">Writable control store</a></div> <p>A few computers were built using <i>writable microcode</i>. In this design, rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a <i>writable control store</i> or <i>WCS</i>. Such a computer is sometimes called a <i>writable instruction set computer</i> (WISC).<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> </p><p>Many experimental prototype computers use <a href="#Writable_control_store">writable control stores</a>; there are also commercial machines that use writable microcode, such as the <a href="/wiki/Burroughs_Small_Systems" class="mw-redirect" title="Burroughs Small Systems">Burroughs Small Systems</a>, early <a href="/wiki/Xerox_PARC" class="mw-redirect" title="Xerox PARC">Xerox</a> workstations, the <a href="/wiki/Digital_Equipment_Corporation" title="Digital Equipment Corporation">DEC</a> <a href="/wiki/VAX" title="VAX">VAX</a> 8800 (<i>Nautilus</i>) family, the <a href="/wiki/Symbolics" title="Symbolics">Symbolics</a> L- and G-machines, a number of IBM System/360 and <a href="/wiki/System/370" class="mw-redirect" title="System/370">System/370</a> implementations, some DEC <a href="/wiki/PDP-10" title="PDP-10">PDP-10</a> machines,<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> and the <a href="/wiki/Data_General_Eclipse_MV/8000" title="Data General Eclipse MV/8000">Data General Eclipse MV/8000</a>.<sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </p><p>The IBM System/370 includes a facility called <i>Initial-Microprogram Load</i> (<i>IML</i> or <i>IMPL</i>)<sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> that can be invoked from the console, as part of <i><a href="/wiki/Power-on_reset#Power-on_reset_on_IBM_mainframes" title="Power-on reset">power-on reset</a></i> (<i>POR</i>) or from another processor in a <a href="/wiki/Tightly_coupled_system" class="mw-redirect" title="Tightly coupled system">tightly coupled</a> <a href="/wiki/Multiprocessor" class="mw-redirect" title="Multiprocessor">multiprocessor</a> complex. </p><p>Some commercial machines, for example IBM 360/85,<sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> have both a read-only storage and a writable control store for microcode. </p><p>WCS offers several advantages including the ease of patching the microprogram and, for certain hardware generations, faster access than ROMs can provide. User-programmable WCS allows the user to optimize the machine for specific purposes. </p><p>Starting with the <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a> in 1995, several <a href="/wiki/X86" title="X86">x86</a> CPUs have writable <a href="/wiki/Intel_Microcode" class="mw-redirect" title="Intel Microcode">Intel Microcode</a>.<sup id="cite_ref-Stiller_1996_52-0" class="reference"><a href="#cite_note-Stiller_1996-52"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup> This, for example, has allowed bugs in the <a href="/wiki/Intel_Core_2" title="Intel Core 2">Intel Core 2</a> and Intel <a href="/wiki/Xeon" title="Xeon">Xeon</a> microcodes to be fixed by patching their microprograms, rather than requiring the entire chips to be replaced. A second prominent example is the set of microcode patches that Intel offered for some of their processor architectures of up to 10 years in age, in a bid to counter the security vulnerabilities discovered in their designs – <a href="/wiki/Spectre_(security_vulnerability)" title="Spectre (security vulnerability)">Spectre</a> and <a href="/wiki/Meltdown_(security_vulnerability)" title="Meltdown (security vulnerability)">Meltdown</a> – which went public at the start of 2018.<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup> A microcode update can be installed by Linux,<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup> <a href="/wiki/FreeBSD" title="FreeBSD">FreeBSD</a>,<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup> Microsoft Windows,<sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup> or the motherboard BIOS.<sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup> </p><p>Some machines offer user-programmable writable control stores as an option, including the <a href="/wiki/HP_2100" title="HP 2100">HP 2100</a>, DEC <a href="/wiki/PDP-11" title="PDP-11">PDP-11/60</a>, <a href="/wiki/TI-990" title="TI-990">TI-990</a>/12,<sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-61" class="reference"><a href="#cite_note-61"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup> and <a href="/wiki/Varian_Data_Machines" title="Varian Data Machines">Varian Data Machines</a> V-70 series <a href="/wiki/Minicomputer" title="Minicomputer">minicomputers</a>. </p> <div class="mw-heading mw-heading2"><h2 id="Comparison_to_VLIW_and_RISC">Comparison to VLIW and RISC</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=18" title="Edit section: Comparison to VLIW and RISC"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output 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class="mbox-text"><div class="mbox-text-span">This section <b>does not <a href="/wiki/Wikipedia:Citing_sources" title="Wikipedia:Citing sources">cite</a> any <a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">sources</a></b>.<span class="hide-when-compact"> Please help <a href="/wiki/Special:EditPage/Microcode" title="Special:EditPage/Microcode">improve this section</a> by <a href="/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a>. Unsourced material may be challenged and <a href="/wiki/Wikipedia:Verifiability#Burden_of_evidence" title="Wikipedia:Verifiability">removed</a>.</span> <span class="date-container"><i>(<span class="date">August 2023</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-Update plainlinks metadata ambox ambox-content ambox-Update" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/42px-Ambox_current_red_Americas.svg.png" decoding="async" width="42" height="34" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/63px-Ambox_current_red_Americas.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/84px-Ambox_current_red_Americas.svg.png 2x" data-file-width="360" data-file-height="290" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">This section needs to be <b>updated</b>. The reason given is: Many CISC processors now do instruction fetch and decode in hardware, and execute most if not all instructions in hardware, and both RISC and CISC processors execute several operations per clock cycle.<span class="hide-when-compact"> Please help update this article to reflect recent events or newly available information.</span> <span class="date-container"><i>(<span class="date">December 2023</span>)</i></span></div></td></tr></tbody></table> <p>The design trend toward heavily microcoded processors with complex instructions began in the early 1960s and continued until roughly the mid-1980s. At that point the <a href="/wiki/RISC" class="mw-redirect" title="RISC">RISC</a> design philosophy started becoming more prominent. </p><p>A CPU that uses microcode generally takes several clock cycles to execute a single instruction, one clock cycle for each step in the microprogram for that instruction. Some <a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a> processors include instructions that can take a very long time to execute. Such variations interfere with both <a href="/wiki/Interrupt_latency" title="Interrupt latency">interrupt latency</a> and, what is far more important in modern systems, <a href="/wiki/Instruction_pipelining" title="Instruction pipelining">pipelining</a>. </p><p>When designing a new processor, a <a href="/wiki/Hardwired_control" class="mw-redirect" title="Hardwired control">hardwired control</a> RISC has the following advantages over microcoded CISC: </p> <ul><li>Programming has largely moved away from assembly level, so it's no longer worthwhile to provide complex instructions for productivity reasons.</li> <li>Simpler instruction sets allow direct execution by hardware, avoiding the performance penalty of microcoded execution.</li> <li>Analysis shows complex instructions are rarely used, hence the machine resources devoted to them are largely wasted.</li> <li>The machine resources devoted to rarely used complex instructions are better used for expediting performance of simpler, commonly used instructions.</li> <li>Complex microcoded instructions may require many clock cycles that vary, and are difficult to <a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">pipeline</a> for increased performance.</li></ul> <p>There are counterpoints as well: </p> <ul><li>The complex instructions in heavily microcoded implementations may not take much extra machine resources, except for microcode space. For example, the same ALU is often used to calculate an effective address and to compute the result from the operands, e.g., the original <a href="/wiki/Z80" class="mw-redirect" title="Z80">Z80</a>, <a href="/wiki/8086" class="mw-redirect" title="8086">8086</a>, and others.</li> <li>The simpler non-RISC instructions (i.e., involving direct memory <a href="/wiki/Operand" title="Operand">operands</a>) are frequently used by modern compilers. Even immediate to stack (i.e., memory result) arithmetic operations are commonly employed. Although such memory operations, often with varying length encodings, are more difficult to pipeline, it is still fully feasible to do so - clearly exemplified by the <a href="/wiki/I486" title="I486">i486</a>, <a href="/wiki/AMD_K5" title="AMD K5">AMD K5</a>, <a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">Cyrix 6x86</a>, <a href="/wiki/Motorola_68040" title="Motorola 68040">Motorola 68040</a>, etc.</li> <li>Non-RISC instructions inherently perform more work per instruction (on average), and are also normally highly encoded, so they enable smaller overall size of the same program, and thus better use of limited cache memories.</li></ul> <p>Many RISC and <a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> processors are designed to execute every instruction (as long as it is in the cache) in a single cycle. This is very similar to the way CPUs with microcode execute one microinstruction per cycle. VLIW processors have instructions that behave similarly to very wide horizontal microcode, although typically without such fine-grained control over the hardware as provided by microcode. RISC instructions are sometimes similar to the narrow vertical microcode. </p><p>Microcode has been popular in application-specific processors such as <a href="/wiki/Network_processor" title="Network processor">network processors</a>, <a href="/wiki/Digital_signal_processor" title="Digital signal processor">digital signal processors</a>, <a href="/wiki/Channel_I/O" title="Channel I/O">channel controllers</a>, <a href="/wiki/Disk_controller" title="Disk controller">disk controllers</a>, <a href="/wiki/Network_interface_controller" title="Network interface controller">network interface controllers</a>, <a href="/wiki/Flash_memory_controller" title="Flash memory controller">flash memory controllers</a>, <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">graphics processing units</a>, and in other hardware. </p> <div class="mw-heading mw-heading2"><h2 id="Micro-operations">Micro-operations</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=19" title="Edit section: Micro-operations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Modern CISC implementations, such as the <a href="/wiki/X86" title="X86">x86</a> family starting with the <a href="/wiki/NexGen" title="NexGen">NexGen</a> Nx586, Intel <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a>, and <a href="/wiki/AMD_K5" title="AMD K5">AMD K5</a>. decode instructions into dynamically buffered <a href="/wiki/Micro-operation" title="Micro-operation">micro-operations</a> with an instruction encoding similar to RISC or traditional microcode. A hardwired instruction decode unit directly emits microoperations for common x86 instructions, but falls back to a more traditional microcode ROM containing microoperations for more complex or rarely used instructions.<sup id="cite_ref-FogMicro_2-1" class="reference"><a href="#cite_note-FogMicro-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p>For example, an x86 might look up microoperations from microcode to handle complex multistep operations such as loop or string instructions, <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> <a href="/wiki/Transcendental_function" title="Transcendental function">transcendental functions</a> or unusual values such as <a href="/wiki/Denormal_number" class="mw-redirect" title="Denormal number">denormal numbers</a>, and special-purpose instructions such as <a href="/wiki/CPUID" title="CPUID">CPUID</a>. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=20" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239009302">.mw-parser-output .portalbox{padding:0;margin:0.5em 0;display:table;box-sizing:border-box;max-width:175px;list-style:none}.mw-parser-output .portalborder{border:1px solid var(--border-color-base,#a2a9b1);padding:0.1em;background:var(--background-color-neutral-subtle,#f8f9fa)}.mw-parser-output .portalbox-entry{display:table-row;font-size:85%;line-height:110%;height:1.9em;font-style:italic;font-weight:bold}.mw-parser-output .portalbox-image{display:table-cell;padding:0.2em;vertical-align:middle;text-align:center}.mw-parser-output .portalbox-link{display:table-cell;padding:0.2em 0.2em 0.2em 0.3em;vertical-align:middle}@media(min-width:720px){.mw-parser-output .portalleft{clear:left;float:left;margin:0.5em 1em 0.5em 0}.mw-parser-output .portalright{clear:right;float:right;margin:0.5em 0 0.5em 1em}}</style><ul role="navigation" aria-label="Portals" class="noprint portalbox portalborder portalright"> <li class="portalbox-entry"><span class="portalbox-image"><span class="noviewer" typeof="mw:File"><a href="/wiki/File:Nuvola_apps_ksim.png" class="mw-file-description"><img alt="icon" src="//upload.wikimedia.org/wikipedia/commons/thumb/8/8d/Nuvola_apps_ksim.png/28px-Nuvola_apps_ksim.png" decoding="async" width="28" height="28" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/8d/Nuvola_apps_ksim.png/42px-Nuvola_apps_ksim.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/8d/Nuvola_apps_ksim.png/56px-Nuvola_apps_ksim.png 2x" data-file-width="128" data-file-height="128" /></a></span></span><span class="portalbox-link"><a href="/wiki/Portal:Electronics" title="Portal:Electronics">Electronics portal</a></span></li></ul> <style data-mw-deduplicate="TemplateStyles:r1184024115">.mw-parser-output .div-col{margin-top:0.3em;column-width:30em}.mw-parser-output .div-col-small{font-size:90%}.mw-parser-output .div-col-rules{column-rule:1px solid #aaa}.mw-parser-output .div-col dl,.mw-parser-output .div-col ol,.mw-parser-output .div-col ul{margin-top:0}.mw-parser-output .div-col li,.mw-parser-output .div-col dd{page-break-inside:avoid;break-inside:avoid-column}</style><div class="div-col" style="column-width: 20em;"> <ul><li><a href="/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li> <li><a href="/wiki/CPU_design" class="mw-redirect" title="CPU design">CPU design</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> (FSM)</li> <li><a href="/wiki/Firmware" title="Firmware">Firmware</a></li> <li><a href="/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li> <li><a href="/wiki/Pentium_FDIV_bug" title="Pentium FDIV bug">Pentium FDIV bug</a></li> <li><a href="/wiki/Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">Instruction pipeline</a></li> <li><a href="/wiki/Microsequencer" title="Microsequencer">Microsequencer</a></li> <li><a href="/wiki/MikroSim" title="MikroSim">MikroSim</a></li> <li><a href="/wiki/Millicode" title="Millicode">Millicode</a></li> <li><a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">Superscalar</a></li></ul> </div> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=21" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-40"><span class="mw-cite-backlink"><b><a href="#cite_ref-40">^</a></b></span> <span class="reference-text">IBM horizontally microcoded processors had multiple micro-orders and register select fields that required decoding.</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=22" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-Kent2813-1"><span class="mw-cite-backlink">^ <a href="#cite_ref-Kent2813_1-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Kent2813_1-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Kent2813_1-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFKentWilliams1993" class="citation book cs1">Kent, Allen; Williams, James G. (April 5, 1993). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=EjWV8J8CQEYC"><i>Encyclopedia of Computer Science and Technology: Volume 28 - Supplement 13</i></a>. New York: Marcel Dekker, Inc. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-8247-2281-7" title="Special:BookSources/0-8247-2281-7"><bdi>0-8247-2281-7</bdi></a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20161120161636/https://books.google.com/books?id=EjWV8J8CQEYC">Archived</a> from the original on November 20, 2016<span class="reference-accessdate">. Retrieved <span class="nowrap">Jan 17,</span> 2016</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Encyclopedia+of+Computer+Science+and+Technology%3A+Volume+28+-+Supplement+13&rft.place=New+York&rft.pub=Marcel+Dekker%2C+Inc&rft.date=1993-04-05&rft.isbn=0-8247-2281-7&rft.aulast=Kent&rft.aufirst=Allen&rft.au=Williams%2C+James+G.&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DEjWV8J8CQEYC&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-FogMicro-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-FogMicro_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-FogMicro_2-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFFog2017" class="citation report cs1">Fog, Agner (2017-05-02). <a rel="nofollow" class="external text" href="https://www.agner.org/optimize/microarchitecture.pdf">The microarchitecture of Intel, AMD and VIA CPUs</a> <span class="cs1-format">(PDF)</span> (Report). Technical University of Denmark. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170328065929/https://agner.org/optimize/microarchitecture.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2017-03-28<span class="reference-accessdate">. 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Duke Press. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1882419661" title="Special:BookSources/978-1882419661"><bdi>978-1882419661</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Inside+the+AS%2F400%2C+Second+Edition&rft.pub=Duke+Press&rft.date=1997&rft.isbn=978-1882419661&rft.au=Frank+G.+Soltis&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3D5DoPAAAACAAJ&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-Interview:_Battling_the_N64_(Naboo)-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-Interview:_Battling_the_N64_(Naboo)_31-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://ign64.ign.com/articles/087/087646p1.html">"Interview: Battling the N64 (Naboo)"</a>. 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December 12, 2000. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130927083807/http://www.ign.com/articles/2000/12/13/indiana-jones-and-the-infernal-machine-2">Archived</a> from the original on September 27, 2013<span class="reference-accessdate">. Retrieved <span class="nowrap">September 24,</span> 2013</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=IGN&rft.atitle=Indiana+Jones+and+the+Infernal+Machine&rft.date=2000-12-12&rft_id=http%3A%2F%2Fwww.ign.com%2Farticles%2F2000%2F12%2F13%2Findiana-jones-and-the-infernal-machine-2&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-Postmortem_RE2_N64-33"><span class="mw-cite-backlink"><b><a href="#cite_ref-Postmortem_RE2_N64_33-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMeynink2000" class="citation news cs1">Meynink, Todd (July 28, 2000). <a rel="nofollow" class="external text" href="http://www.gamasutra.com/view/feature/3148/postmortem_angel_studios_.php">"Postmortem: Angel Studios' Resident Evil 2 (N64 Version)"</a>. <i><a href="/wiki/Gamasutra" class="mw-redirect" title="Gamasutra">Gamasutra</a></i>. <a href="/wiki/United_Business_Media" class="mw-redirect" title="United Business Media">United Business Media LLC</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20121021070818/http://www.gamasutra.com/view/feature/3148/postmortem_angel_studios_.php">Archived</a> from the original on October 21, 2012<span class="reference-accessdate">. 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Digital Scientific Corporation. May 1971. 7032MO. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200114014526/http://www.bitsavers.org/pdf/digitalScientific/7032MO_Meta4Series16RefMan.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2020-01-14<span class="reference-accessdate">. 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Digital Scientific Corporation. March 1970. 7024MO. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190923061816/http://bitsavers.org/pdf/digitalScientific/7024MO_ROMmanual_Mar70.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2019-09-23<span class="reference-accessdate">. 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Digital Scientific Corporation. June 1970. 7006MO. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190923061755/http://bitsavers.org/pdf/digitalScientific/7006MO_Meta16_SysMan_Jun70.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2019-09-23<span class="reference-accessdate">. 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McGraw-Hill. p. 300. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-07-027363-4" title="Special:BookSources/0-07-027363-4"><bdi>0-07-027363-4</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Computer+Architecture+and+Organization&rft.pages=300&rft.pub=McGraw-Hill&rft.date=1978&rft.isbn=0-07-027363-4&rft.aulast=Hayes&rft.aufirst=John+P.&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-41"><span class="mw-cite-backlink"><b><a href="#cite_ref-41">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFNeal_HarmanAndy_Gimblett2009" class="citation web cs1">Neal Harman; Andy Gimblett (2009-10-12). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150419164703/http://euler.mat.uson.mx/~havillam/ca/CS323/0708.cs-323003.html">"CS-323: High Performance Microprocessors – Chapter 1. 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May 1996. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110815022514/http://download.majix.org/dec/palcode_dsgn_gde.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on August 15, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">November 7,</span> 2013</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PALcode+for+Alpha+Microprocessors+System+Design+Guide&rft.pub=Digital+Equipment+Corporation&rft.date=1996-05&rft_id=http%3A%2F%2Fdownload.majix.org%2Fdec%2Fpalcode_dsgn_gde.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-45"><span class="mw-cite-backlink"><b><a href="#cite_ref-45">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSpruth2012" class="citation book cs1">Spruth, Wilhelm (December 2012). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=0YmqCAAAQBAJ"><i>The Design of a Microprocessor</i></a>. Springer Science & Business Media. p. 31. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-3-642-74916-2" title="Special:BookSources/978-3-642-74916-2"><bdi>978-3-642-74916-2</bdi></a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20161120195023/https://books.google.com/books?id=0YmqCAAAQBAJ">Archived</a> from the original on November 20, 2016<span class="reference-accessdate">. Retrieved <span class="nowrap">Jan 18,</span> 2015</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=The+Design+of+a+Microprocessor&rft.pages=31&rft.pub=Springer+Science+%26+Business+Media&rft.date=2012-12&rft.isbn=978-3-642-74916-2&rft.aulast=Spruth&rft.aufirst=Wilhelm&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3D0YmqCAAAQBAJ&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-46"><span class="mw-cite-backlink"><b><a href="#cite_ref-46">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKoopman1987" class="citation journal cs1">Koopman, Philip Jr. (1987). <a rel="nofollow" class="external text" href="http://www.ece.cmu.edu/~koopman/forth/rochester_87.pdf">"Writable instruction set, stack oriented computers: The WISC Concept"</a> <span class="cs1-format">(PDF)</span>. <i>The Journal of Forth Application and Research</i>: 49–71. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20080511192958/http://www.ece.cmu.edu/~koopman/forth/rochester_87.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2008-05-11.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=The+Journal+of+Forth+Application+and+Research&rft.atitle=Writable+instruction+set%2C+stack+oriented+computers%3A+The+WISC+Concept&rft.pages=49-71&rft.date=1987&rft.aulast=Koopman&rft.aufirst=Philip+Jr.&rft_id=http%3A%2F%2Fwww.ece.cmu.edu%2F~koopman%2Fforth%2Frochester_87.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-47"><span class="mw-cite-backlink"><b><a href="#cite_ref-47">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSmith2002" class="citation newsgroup cs1">Smith, Eric (3 September 2002). <a rel="nofollow" class="external text" href="http://pdp10.nocrew.org/cpu/kl10-ucode.txt">"Re: What was the size of Microcode in various machines"</a>. <a href="/wiki/Usenet_newsgroup" title="Usenet newsgroup">Newsgroup</a>: <a rel="nofollow" class="external text" href="news:alt.folklore.computers">alt.folklore.computers</a>. <a href="/wiki/Usenet_(identifier)" class="mw-redirect" title="Usenet (identifier)">Usenet:</a> <a rel="nofollow" class="external text" href="news:qhn0qyveyu.fsf@ruckus.brouhaha.com">qhn0qyveyu.fsf@ruckus.brouhaha.com</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090126231132/http://pdp10.nocrew.org/cpu/kl10-ucode.txt">Archived</a> from the original on 26 January 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">18 December</span> 2008</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Re%3A+What+was+the+size+of+Microcode+in+various+machines&rft.pub=alt.folklore.computers&rft.date=2002-09-03&rft_id=news%3Aqhn0qyveyu.fsf%40ruckus.brouhaha.com%23id-name%3DUsenet%3A&rft.aulast=Smith&rft.aufirst=Eric&rft_id=http%3A%2F%2Fpdp10.nocrew.org%2Fcpu%2Fkl10-ucode.txt&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-48"><span class="mw-cite-backlink"><b><a href="#cite_ref-48">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSmotherman" class="citation web cs1">Smotherman, Mark. <a rel="nofollow" class="external text" href="https://people.computing.clemson.edu/~mark/330/eagle.html">"CPSC 3300 / The Soul of a New Machine"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">2023-10-27</span></span>. <q>4096 x 75-bit SRAM writable control store: 74-bit microinstruction with 1 parity bit (18 fields)</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=CPSC+3300+%2F+The+Soul+of+a+New+Machine&rft.aulast=Smotherman&rft.aufirst=Mark&rft_id=https%3A%2F%2Fpeople.computing.clemson.edu%2F~mark%2F330%2Feagle.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-49"><span class="mw-cite-backlink"><b><a href="#cite_ref-49">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="http://www.bitsavers.org/pdf/ibm/370/princOps/GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf"><i>IBM System/370 Principles of Operation</i></a> <span class="cs1-format">(PDF)</span>. Fourth Edition. IBM. September 1974. pp. 98, 245. GA22-7000-4. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120229195635/http://bitsavers.org/pdf/ibm/370/princOps/GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2012-02-29<span class="reference-accessdate">. Retrieved <span class="nowrap">2012-08-27</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=IBM+System%2F370+Principles+of+Operation&rft.series=Fourth+Edition&rft.pages=98%2C+245&rft.pub=IBM&rft.date=1974-09&rft_id=http%3A%2F%2Fwww.bitsavers.org%2Fpdf%2Fibm%2F370%2FprincOps%2FGA22-7000-4_370_Principles_Of_Operation_Sep75.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-50"><span class="mw-cite-backlink"><b><a href="#cite_ref-50">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="http://www.bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6916-1_360-85_funcChar_Jun68.pdf"><i>IBM System/360 Model 85 Functional Characteristics</i></a> <span class="cs1-format">(PDF)</span>. SECOND EDITION. IBM. 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Trends & News (in German). <a href="/wiki/Heise_Verlag" class="mw-redirect" title="Heise Verlag">Heise Verlag</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170828172141/https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html">Archived</a> from the original on 2017-08-28<span class="reference-accessdate">. Retrieved <span class="nowrap">2017-08-28</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=c%27t+%E2%80%93+magazin+f%C3%BCr+computertechnik&rft.atitle=Prozessorgefl%C3%BCster&rft.date=1996-05-12&rft.aulast=Stiller&rft.aufirst=Andreas&rft.au=Paul%2C+Matthias+R.&rft_id=https%3A%2F%2Fwww.heise.de%2Fct%2Fartikel%2FProzessorgefluester-284546.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-53"><span class="mw-cite-backlink"><b><a href="#cite_ref-53">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1">"9.11: Microcode update facilities". <a rel="nofollow" class="external text" href="http://www.intel.com/Assets/PDF/manual/253668.pdf"><i>Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide, Part 1</i></a> <span class="cs1-format">(PDF)</span>. <a href="/wiki/Intel" title="Intel">Intel</a>. September 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=9.11%3A+Microcode+update+facilities&rft.btitle=Intel+64+and+IA-32+Architectures+Software+Developer%27s+Manual%2C+Volume+3A%3A+System+Programming+Guide%2C+Part+1&rft.pub=Intel&rft.date=2016-09&rft_id=http%3A%2F%2Fwww.intel.com%2FAssets%2FPDF%2Fmanual%2F253668.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-54"><span class="mw-cite-backlink"><b><a href="#cite_ref-54">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.tomshardware.com/news/intel-meltdown-spectre-patch-silicon,36672.html">Intel Patches All Recent CPUs, Promises Hardware Fixes For Upcoming 8th Gen Chips</a> by Paul Alcorn on March 15, 2018</span> </li> <li id="cite_note-55"><span class="mw-cite-backlink"><b><a href="#cite_ref-55">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20180319202103/https://downloadcenter.intel.com/download/27591/Linux-Processor-Microcode-Data-File">"Download Linux* Processor Microcode Data File"</a>. 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Retrieved <span class="nowrap">2018-03-21</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Download+Linux%2A+Processor+Microcode+Data+File&rft_id=https%3A%2F%2Fdownloadcenter.intel.com%2Fdownload%2F27591%2FLinux-Processor-Microcode-Data-File&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-56"><span class="mw-cite-backlink"><b><a href="#cite_ref-56">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120226174302/http://urbanmyth.org/microcode/">"Intel Microcode Update Utility for Linux"</a>. Archived from <a rel="nofollow" class="external text" href="http://urbanmyth.org/microcode/">the original</a> on 2012-02-26.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Microcode+Update+Utility+for+Linux&rft_id=http%3A%2F%2Furbanmyth.org%2Fmicrocode%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-57"><span class="mw-cite-backlink"><b><a href="#cite_ref-57">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://svnweb.freebsd.org/ports/head/sysutils/cpupdate/">"[ports] Index of /head/sysutils/cpupdate"</a>. Freebsd.org. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200401215701/https://svnweb.freebsd.org/ports/head/sysutils/cpupdate/">Archived</a> from the original on 2020-04-01<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-01-16</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=%5Bports%5D+Index+of+%2Fhead%2Fsysutils%2Fcpupdate&rft.pub=Freebsd.org&rft_id=https%3A%2F%2Fsvnweb.freebsd.org%2Fports%2Fhead%2Fsysutils%2Fcpupdate%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-58"><span class="mw-cite-backlink"><b><a href="#cite_ref-58">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="http://support.microsoft.com/kb/936357">"A microcode reliability update is available that improves the reliability of systems that use Intel processors"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20080223074207/http://support.microsoft.com/kb/936357">Archived</a> from the original on 2008-02-23<span class="reference-accessdate">. Retrieved <span class="nowrap">2008-02-25</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=A+microcode+reliability+update+is+available+that+improves+the+reliability+of+systems+that+use+Intel+processors&rft_id=http%3A%2F%2Fsupport.microsoft.com%2Fkb%2F936357&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-59"><span class="mw-cite-backlink"><b><a href="#cite_ref-59">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140901063251/http://www.intel.com/support/motherboards/server/sb/cs-021619.htm">"Server Products - BIOS Update required when Missing Microcode message is seen during POST"</a>. <i>Intel</i>. January 24, 2013. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/support/motherboards/server/sb/cs-021619.htm">the original</a> on September 1, 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=Server+Products+-+BIOS+Update+required+when+Missing+Microcode+message+is+seen+during+POST&rft.date=2013-01-24&rft_id=http%3A%2F%2Fwww.intel.com%2Fsupport%2Fmotherboards%2Fserver%2Fsb%2Fcs-021619.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-60"><span class="mw-cite-backlink"><b><a href="#cite_ref-60">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.bitsavers.org/pdf/ti/990/990-12/2268241_990-12CPU_DepoRepair_Feb83.pdf">"Model 990/12 LR Computer Depot Maintenance and Repair Manual"</a> <span class="cs1-format">(PDF)</span>. <i>Bitsavers.org</i>. Texas Instruments<span class="reference-accessdate">. Retrieved <span class="nowrap">15 February</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Bitsavers.org&rft.atitle=Model+990%2F12+LR+Computer+Depot+Maintenance+and+Repair+Manual&rft_id=http%3A%2F%2Fwww.bitsavers.org%2Fpdf%2Fti%2F990%2F990-12%2F2268241_990-12CPU_DepoRepair_Feb83.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></span> </li> <li id="cite_note-61"><span class="mw-cite-backlink"><b><a href="#cite_ref-61">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><i>Texas Instruments Model 990 Computer MDS-990 Microcode Development System Programmer's Guide</i> (15 August 1979 ed.). Texas Instruments Archives, RG-20 accession 94-08, Box 10, 45C. DeGolyer Library, Southern Methodist University, Dallas, TX USA.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Texas+Instruments+Model+990+Computer+MDS-990+Microcode+Development+System+Programmer%27s+Guide&rft.place=Texas+Instruments+Archives%2C+RG-20+accession+94-08%2C+Box+10%2C+45C.+DeGolyer+Library%2C+Southern+Methodist+University%2C+Dallas%2C+TX+USA&rft.edition=15+August+1979&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_book" title="Template:Cite book">cite book</a>}}</code>: CS1 maint: location (<a href="/wiki/Category:CS1_maint:_location" title="Category:CS1 maint: location">link</a>)</span></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=23" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSmith1988" class="citation journal cs1">Smith, Richard E. (1988). <a rel="nofollow" class="external text" href="http://doi.ieeecomputersociety.org/10.1109/MAHC.1988.10039">"A Historical Overview of Computer Architecture"</a>. <i><a href="/wiki/Annals_of_the_History_of_Computing" class="mw-redirect" title="Annals of the History of Computing">Annals of the History of Computing</a></i>. <b>10</b> (4): 277–303. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FMAHC.1988.10039">10.1109/MAHC.1988.10039</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:16405547">16405547</a><span class="reference-accessdate">. Retrieved <span class="nowrap">June 21,</span> 2006</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Annals+of+the+History+of+Computing&rft.atitle=A+Historical+Overview+of+Computer+Architecture&rft.volume=10&rft.issue=4&rft.pages=277-303&rft.date=1988&rft_id=info%3Adoi%2F10.1109%2FMAHC.1988.10039&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A16405547%23id-name%3DS2CID&rft.aulast=Smith&rft.aufirst=Richard+E.&rft_id=http%3A%2F%2Fdoi.ieeecomputersociety.org%2F10.1109%2FMAHC.1988.10039&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSmotherman,_Mark2022" class="citation web cs1">Smotherman, Mark (October 2022). <a rel="nofollow" class="external text" href="https://people.computing.clemson.edu/~mark/uprog.html">"A Brief History of Microprogramming"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">October 27,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=A+Brief+History+of+Microprogramming&rft.date=2022-10&rft.au=Smotherman%2C+Mark&rft_id=https%3A%2F%2Fpeople.computing.clemson.edu%2F~mark%2Fuprog.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWilkes1986" class="citation journal cs1"><a href="/wiki/Maurice_Wilkes" title="Maurice Wilkes">Wilkes, M. V.</a> (1986). <a rel="nofollow" class="external text" href="http://doi.ieeecomputersociety.org/10.1109/MAHC.1986.10035">"The Genesis of Microprogramming"</a>. <i>Annals of the History of Computing</i>. <b>8</b> (2): 116–126. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FMAHC.1986.10035">10.1109/MAHC.1986.10035</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:1978847">1978847</a><span class="reference-accessdate">. Retrieved <span class="nowrap">August 7,</span> 2006</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Annals+of+the+History+of+Computing&rft.atitle=The+Genesis+of+Microprogramming&rft.volume=8&rft.issue=2&rft.pages=116-126&rft.date=1986&rft_id=info%3Adoi%2F10.1109%2FMAHC.1986.10035&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A1978847%23id-name%3DS2CID&rft.aulast=Wilkes&rft.aufirst=M.+V.&rft_id=http%3A%2F%2Fdoi.ieeecomputersociety.org%2F10.1109%2FMAHC.1986.10035&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWilkesStringer1953" class="citation journal cs1"><a href="/wiki/Maurice_Wilkes" title="Maurice Wilkes">Wilkes, M. V.</a>; <a href="/wiki/John_Bentley_Stringer" title="John Bentley Stringer">Stringer, J. B.</a> (April 1953). <a rel="nofollow" class="external text" href="http://research.microsoft.com/~gbell/Computer_Structures_Principles_and_Examples/csp0174.htm">"Microprogramming and the Design of the Control Circuits in an Electronic Digital Computer"</a>. <i><a href="/wiki/Proceedings_of_the_Cambridge_Philosophical_Society" class="mw-redirect" title="Proceedings of the Cambridge Philosophical Society">Proceedings of the Cambridge Philosophical Society</a></i>. <b>49</b> (pt. 2): 230–238. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/1953PCPS...49..230W">1953PCPS...49..230W</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1017%2FS0305004100028322">10.1017/S0305004100028322</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:62230627">62230627</a><span class="reference-accessdate">. Retrieved <span class="nowrap">August 23,</span> 2006</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Proceedings+of+the+Cambridge+Philosophical+Society&rft.atitle=Microprogramming+and+the+Design+of+the+Control+Circuits+in+an+Electronic+Digital+Computer&rft.volume=49&rft.issue=pt.+2&rft.pages=230-238&rft.date=1953-04&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A62230627%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1017%2FS0305004100028322&rft_id=info%3Abibcode%2F1953PCPS...49..230W&rft.aulast=Wilkes&rft.aufirst=M.+V.&rft.au=Stringer%2C+J.+B.&rft_id=http%3A%2F%2Fresearch.microsoft.com%2F~gbell%2FComputer_Structures_Principles_and_Examples%2Fcsp0174.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHusson1970" class="citation book cs1">Husson, S.S. (1970). <span class="id-lock-registration" title="Free registration required"><a rel="nofollow" class="external text" href="https://archive.org/details/microprogramming00huss"><i>Microprogramming Principles and Practices</i></a></span>. Prentice-Hall. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-13-581454-5" title="Special:BookSources/0-13-581454-5"><bdi>0-13-581454-5</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Microprogramming+Principles+and+Practices&rft.pub=Prentice-Hall&rft.date=1970&rft.isbn=0-13-581454-5&rft.aulast=Husson&rft.aufirst=S.S.&rft_id=https%3A%2F%2Farchive.org%2Fdetails%2Fmicroprogramming00huss&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFTucker1967" class="citation journal cs1">Tucker, S.G. (1967). <a rel="nofollow" class="external text" href="http://domino.research.ibm.com/tchjr/journalindex.nsf/a3807c5b4823c53f85256561006324be/758c1e6a8a3e5d0285256bfa00685a2f?OpenDocument">"Microprogram control for SYSTEM/360"</a>. <i><a href="/wiki/IBM_Systems_Journal" class="mw-redirect" title="IBM Systems Journal">IBM Systems Journal</a></i>. <b>6</b> (4): 222–241. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1147%2Fsj.64.0222">10.1147/sj.64.0222</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IBM+Systems+Journal&rft.atitle=Microprogram+control+for+SYSTEM%2F360&rft.volume=6&rft.issue=4&rft.pages=222-241&rft.date=1967&rft_id=info%3Adoi%2F10.1147%2Fsj.64.0222&rft.aulast=Tucker&rft.aufirst=S.G.&rft_id=http%3A%2F%2Fdomino.research.ibm.com%2Ftchjr%2Fjournalindex.nsf%2Fa3807c5b4823c53f85256561006324be%2F758c1e6a8a3e5d0285256bfa00685a2f%3FOpenDocument&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShirriff2022" class="citation web cs1">Shirriff, Ken (December 2022). <a rel="nofollow" class="external text" href="https://www.righto.com/2022/11/how-8086-processors-microcode-engine.html">"How the 8086 processor's microcode engine works"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=How+the+8086+processor%27s+microcode+engine+works&rft.date=2022-12&rft.aulast=Shirriff&rft.aufirst=Ken&rft_id=https%3A%2F%2Fwww.righto.com%2F2022%2F11%2Fhow-8086-processors-microcode-engine.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMicrocode" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Microcode&action=edit&section=24" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1235681985">.mw-parser-output .side-box{margin:4px 0;box-sizing:border-box;border:1px solid #aaa;font-size:88%;line-height:1.25em;background-color:var(--background-color-interactive-subtle,#f8f9fa);display:flow-root}.mw-parser-output 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title="wiktionary:Special:Search/microcode">microcode</a></b></i> in Wiktionary, the free dictionary.</div></div> </div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-External_links plainlinks metadata ambox ambox-style ambox-external_links" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/f/f2/Edit-clear.svg/40px-Edit-clear.svg.png" decoding="async" width="40" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/f/f2/Edit-clear.svg/60px-Edit-clear.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/f/f2/Edit-clear.svg/80px-Edit-clear.svg.png 2x" data-file-width="48" data-file-height="48" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">This article's <b>use of <a href="/wiki/Wikipedia:External_links" title="Wikipedia:External links">external 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<ul><li><a rel="nofollow" class="external text" href="http://c2.com/cgi/wiki?WritableInstructionSetComputer">Writable Instruction Set Computer</a></li> <li><a rel="nofollow" class="external text" href="http://www.research.ibm.com/journal/rd/102/ibmrd1002F.pdf">Capacitor Read-only Store</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20050124004424/http://www-03.ibm.com/ibm/history/exhibits/attic3/attic3_016.html">Transformer Read-only Store</a></li> <li><a rel="nofollow" class="external text" href="http://people.cs.clemson.edu/~mark/uprog.html">A Brief History of Microprogramming</a></li> <li><a rel="nofollow" class="external text" href="https://lists.debian.org/debian-user/2013/09/msg00126.html">Intel processor microcode security update</a> (fixes the issues when running 32-bit virtual machines in PAE mode)</li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150907195925/http://inertiawar.com/microcode/hawkes_intel_microcode.pdf">Notes on Intel Microcode Updates</a>, March 2013, by Ben Hawkes, archived from the original on September 7, 2015</li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20030309102752/http://www.eetimes.com/news/97/963news/hole.html">Hole seen in Intel's bug-busting feature</a>, <i><a href="/wiki/EE_Times" title="EE Times">EE Times</a></i>, 2002, by Alexander Wolfe, archived from the original on March 9, 2003</li> <li><a rel="nofollow" class="external text" href="http://www.securiteam.com/securityreviews/5FP0M1PDFO.html">Opteron Exposed: Reverse Engineering AMD K8 Microcode Updates</a>, July 26, 2004</li> <li><a rel="nofollow" class="external text" href="https://ieeexplore.ieee.org/document/8662722">WepSIM: An Online Interactive Educational Simulator Integrating Microdesign, Microprogramming, and Assembly Language Programming</a>, July 26, 2022</li></ul> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1236075235">.mw-parser-output .navbox{box-sizing:border-box;border:1px solid #a2a9b1;width:100%;clear:both;font-size:88%;text-align:center;padding:1px;margin:1em auto 0}.mw-parser-output .navbox .navbox{margin-top:0}.mw-parser-output .navbox+.navbox,.mw-parser-output .navbox+.navbox-styles+.navbox{margin-top:-1px}.mw-parser-output .navbox-inner,.mw-parser-output .navbox-subgroup{width:100%}.mw-parser-output .navbox-group,.mw-parser-output .navbox-title,.mw-parser-output .navbox-abovebelow{padding:0.25em 1em;line-height:1.5em;text-align:center}.mw-parser-output .navbox-group{white-space:nowrap;text-align:right}.mw-parser-output .navbox,.mw-parser-output .navbox-subgroup{background-color:#fdfdfd}.mw-parser-output .navbox-list{line-height:1.5em;border-color:#fdfdfd}.mw-parser-output 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href="/wiki/Template_talk:Processor_technologies" title="Template talk:Processor technologies"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Processor_technologies" title="Special:EditPage/Template:Processor technologies"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Processor_technologies" style="font-size:114%;margin:0 4em"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Abstract_machine" title="Abstract machine">Abstract machine</a></li> <li><a href="/wiki/Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li> <li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li> <li><a href="/wiki/Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li> <li><a href="/wiki/Queue_automaton" title="Queue automaton">Queue automaton</a></li> <li><a href="/wiki/Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li> <li><a href="/wiki/Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li> <li><a href="/wiki/Turing_machine" title="Turing machine">Turing machine</a> <ul><li><a href="/wiki/Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li> <li><a href="/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal</a></li> <li><a href="/wiki/Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li> <li><a href="/wiki/Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li> <li><a href="/wiki/Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li> <li><a href="/wiki/Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li> <li><a href="/wiki/Hypercomputation" title="Hypercomputation">Hypercomputation</a></li> <li><a href="/wiki/Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li> <li><a href="/wiki/History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li> <li><a href="/wiki/Stack_machine" title="Stack machine">Stack machine</a></li> <li><a href="/wiki/Register_machine" title="Register machine">Register machines</a> <ul><li><a href="/wiki/Counter_machine" title="Counter machine">Counter</a></li> <li><a href="/wiki/Pointer_machine" title="Pointer machine">Pointer</a></li> <li><a href="/wiki/Random-access_machine" title="Random-access machine">Random-access</a></li> <li><a href="/wiki/Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></li> <li><a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li> <li><a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard</a> <ul><li><a href="/wiki/Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li> <li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li> <li><a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li> <li><a href="/wiki/Cellular_architecture" title="Cellular architecture">Cellular</a></li> <li><a href="/wiki/Endianness" title="Endianness">Endianness</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Memory access</a> <ul><li><a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li> <li><a href="/wiki/Uniform_memory_access" title="Uniform memory access">HUMA</a></li> <li><a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li> <li><a href="/wiki/Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li> <li><a href="/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a> <ul><li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li> <li><a href="/wiki/Fabric_computing" title="Fabric computing">Fabric</a></li> <li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li> <li><a href="/wiki/Cognitive_computing" title="Cognitive computing">Cognitive</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set<br />architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li> <li><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></li> <li><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li> <li><a href="/wiki/Explicit_data_graph_execution" title="Explicit data graph execution">EDGE</a> <ul><li><a href="/wiki/TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li> <li><a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> <ul><li><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></li></ul></li> <li><a href="/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">MISC</a></li> <li><a href="/wiki/One-instruction_set_computer" title="One-instruction set computer">OISC</a></li> <li><a href="/wiki/No_instruction_set_computing" title="No instruction set computing">NISC</a></li> <li><a href="/wiki/Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">ZISC</a></li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Quantum_computing" title="Quantum computing">Quantum computing</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a> <ul><li><a href="/wiki/Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br />sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li> <li><a href="/wiki/VAX" title="VAX">VAX</a></li> <li><a href="/wiki/PDP-11_architecture" title="PDP-11 architecture">PDP-11</a></li> <li><a href="/wiki/X86" title="X86">x86</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li>Power <ul><li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li></ul></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a href="/wiki/SuperH" title="SuperH">SuperH</a></li> <li><a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li> <li><a href="/wiki/ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/IA-64" title="IA-64">Itanium</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/Little_man_computer" title="Little man computer">LMC</a></li> <li>System/3x0 <ul><li><a href="/wiki/IBM_System/360_architecture" title="IBM System/360 architecture">S/360</a></li> <li><a href="/wiki/IBM_System/370" title="IBM System/370">S/370</a></li> <li><a href="/wiki/IBM_System/390" title="IBM System/390">S/390</a></li> <li><a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li> <li>Tilera ISA</li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Adapteva#Products" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li> <li><a href="/wiki/Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li> <li><a href="/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Data_dependency" title="Data dependency">Data dependency</a></li> <li><a href="/wiki/Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li> <li><a href="/wiki/Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li> <li><a href="/wiki/False_sharing" title="False sharing">False sharing</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Scoreboarding" title="Scoreboarding">Scoreboarding</a></li> <li><a href="/wiki/Tomasulo%27s_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a> <ul><li><a href="/wiki/Reservation_station" title="Reservation station">Reservation station</a></li> <li><a href="/wiki/Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li> <li><a href="/wiki/Register_renaming" title="Register renaming">Register renaming</a></li> <li><a href="/wiki/Wide-issue" title="Wide-issue">Wide-issue</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch prediction</a></li> <li><a href="/wiki/Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit-level_parallelism" title="Bit-level parallelism">Bit</a> <ul><li><a href="/wiki/Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li> <li><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word</a></li></ul></li> <li><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li> <li><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Pipelining</a> <ul><li><a href="/wiki/Scalar_processor" title="Scalar processor">Scalar</a></li> <li><a href="/wiki/Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li> <li><a href="/wiki/Task_parallelism" title="Task parallelism">Task</a> <ul><li><a href="/wiki/Thread_(computing)" title="Thread (computing)">Thread</a></li> <li><a href="/wiki/Process_(computing)" title="Process (computing)">Process</a></li></ul></li> <li><a href="/wiki/Data_parallelism" title="Data parallelism">Data</a> <ul><li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li></ul></li> <li><a href="/wiki/Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li> <li><a href="/wiki/Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Temporal_multithreading" title="Temporal multithreading">Temporal</a></li> <li><a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> <ul><li><a href="/wiki/Hyper-threading" title="Hyper-threading">Hyperthreading</a></li> <li><a href="/wiki/Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li> <li><a href="/wiki/Speculative_multithreading" title="Speculative multithreading">Speculative</a></li> <li><a href="/wiki/Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li> <li><a href="/wiki/Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single_instruction,_single_data" title="Single instruction, single data">SISD</a></li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> <ul><li><a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li> <li><a href="/wiki/SWAR" title="SWAR">SWAR</a></li></ul></li> <li><a href="/wiki/Multiple_instruction,_single_data" title="Multiple instruction, single data">MISD</a></li> <li><a href="/wiki/Multiple_instruction,_multiple_data" title="Multiple instruction, multiple data">MIMD</a> <ul><li><a href="/wiki/Single_program,_multiple_data" title="Single program, multiple data">SPMD</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_performance" title="Computer performance">Processor<br />performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a></li> <li><a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC) <ul><li><a href="/wiki/Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li> <li><a href="/wiki/Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li> <li><a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li> <li><a href="/wiki/Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li> <li><a href="/wiki/SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li> <li><a href="/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li> <li><a href="/wiki/Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU) <ul><li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li> <li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li> <li><a href="/wiki/Barrel_processor" title="Barrel processor">Barrel</a></li> <li><a href="/wiki/Stream_processing" title="Stream processing">Stream</a></li> <li><a href="/wiki/Tile_processor" title="Tile processor">Tile processor</a></li> <li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">FPOA</a></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li> <li><a href="/wiki/System_in_a_package" title="System in a package">System in a package</a> (SiP)</li> <li><a href="/wiki/Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li> <li><a href="/wiki/Microcontroller" title="Microcontroller">Microcontroller</a></li> <li><a href="/wiki/Mobile_processor" title="Mobile processor">Mobile</a></li> <li><a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">ASIP</a></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br />on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li> <li><a href="/wiki/Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware<br />accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/AI_accelerator" title="AI accelerator">AI accelerator</a></li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li> <li><a href="/wiki/Image_processor" title="Image processor">Image processor</a></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li> <li><a href="/wiki/Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li> <li><a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li> <li><a href="/wiki/Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li> <li><a href="/wiki/Network_processor" title="Network processor">Network processor</a></li> <li><a href="/wiki/Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/1-bit_computing" title="1-bit computing">1-bit</a></li> <li><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></li> <li><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></li> <li><a href="/wiki/12-bit_computing" title="12-bit computing">12-bit</a></li> <li><a href="/wiki/Apollo_Guidance_Computer" title="Apollo Guidance Computer">15-bit</a></li> <li><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></li> <li><a href="/wiki/24-bit_computing" title="24-bit computing">24-bit</a></li> <li><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></li> <li><a href="/wiki/48-bit_computing" title="48-bit computing">48-bit</a></li> <li><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></li> <li><a href="/wiki/128-bit_computing" title="128-bit computing">128-bit</a></li> <li><a href="/wiki/256-bit_computing" title="256-bit computing">256-bit</a></li> <li><a href="/wiki/512-bit_computing" title="512-bit computing">512-bit</a></li> <li><a href="/wiki/Bit_slicing" title="Bit slicing">bit slicing</a></li> <li><a href="/wiki/Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a> <ul><li><a href="/wiki/Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-core" title="Single-core">Single-core</a></li> <li><a href="/wiki/Multi-core_processor" title="Multi-core processor">Multi-core</a></li> <li><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Core</a></li> <li><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li> <li><a href="/wiki/Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li> <li><a href="/wiki/Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li> <li><a href="/wiki/Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">coherence</a></li></ul></li> <li><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus</a></li> <li><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></li> <li><a href="/wiki/Clock_signal" title="Clock signal">Clock signal</a></li> <li><a href="/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a></li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Execution_unit" title="Execution unit">Functional<br />units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li> <li><a href="/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li> <li><a href="/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li> <li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU) <ul><li><a href="/wiki/Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li> <li><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li> <li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch predictor</a></li> <li><a href="/wiki/Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li> <li><a href="/wiki/Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC) <ul><li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li> <li><a href="/wiki/Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential</a></li> <li><a href="/wiki/Glue_logic" title="Glue logic">Glue</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a> <ul><li><a href="/wiki/Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li> <li><a href="/wiki/Gate_array" title="Gate array">Array</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Processor_register" title="Processor register">Processor register</a></li> <li><a href="/wiki/Status_register" title="Status register">Status register</a></li> <li><a href="/wiki/Stack_register" title="Stack register">Stack register</a></li> <li><a href="/wiki/Register_file" title="Register file">Register file</a></li> <li><a href="/wiki/Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li> <li><a href="/wiki/Memory_address_register" title="Memory address register">Memory address register</a></li> <li><a href="/wiki/Program_counter" title="Program counter">Program counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li> <li><a href="/wiki/Instruction_unit" title="Instruction unit">Instruction unit</a></li> <li><a href="/wiki/Data_buffer" title="Data buffer">Data buffer</a></li> <li><a href="/wiki/Write_buffer" title="Write buffer">Write buffer</a></li> <li><a class="mw-selflink selflink">Microcode</a> <a href="/wiki/ROM_image" title="ROM image">ROM</a></li> <li><a href="/wiki/Counter_(digital)" title="Counter (digital)">Counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multiplexer" title="Multiplexer">Multiplexer</a></li> <li><a href="/wiki/Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li> <li><a href="/wiki/Adder_(electronics)" title="Adder (electronics)">Adder</a></li> <li><a href="/wiki/Binary_multiplier" title="Binary multiplier">Multiplier</a> <ul><li><a href="/wiki/CPU_multiplier" title="CPU multiplier">CPU</a></li></ul></li> <li><a href="/wiki/Binary_decoder" title="Binary decoder">Binary decoder</a> <ul><li><a href="/wiki/Address_decoder" title="Address decoder">Address decoder</a></li> <li><a href="/wiki/Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li> <li><a href="/wiki/Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> <ul><li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D</a></li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li> <li><a href="/wiki/Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean</a></li> <li><a href="/wiki/Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li> <li><a href="/wiki/Analogue_electronics" title="Analogue electronics">Analog</a></li> <li><a href="/wiki/Quantum_circuit" title="Quantum circuit">Quantum</a></li> <li><a href="/wiki/Switch#Electronic_switches" title="Switch">Switch</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Power_management" title="Power management">Power<br />management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Power_Management_Unit" title="Power Management Unit">PMU</a></li> <li><a href="/wiki/Advanced_Power_Management" title="Advanced Power Management">APM</a></li> <li><a href="/wiki/ACPI" title="ACPI">ACPI</a></li> <li><a href="/wiki/Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li> <li><a href="/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li> <li><a href="/wiki/Clock_gating" title="Clock gating">Clock gating</a></li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li> <li><a href="/wiki/Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li> <li><a href="/wiki/Processor_design" title="Processor design">Processor design</a></li> <li><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li> <li><a href="/wiki/Hardware_security_module" title="Hardware security module">Hardware security module</a></li> <li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li> <li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Pin_grid_array" title="Pin grid array">Pin grid array</a></li> <li><a href="/wiki/Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" 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