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<li id="toc-Availability" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Availability"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>Availability</span> </div> </a> <ul id="toc-Availability-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Features" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Features"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Features</span> </div> </a> <ul id="toc-Features-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Connectors" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Connectors"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Connectors</span> </div> </a> <ul id="toc-Connectors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Compatibility" 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div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="/wiki/ESATA" class="mw-redirect" title="ESATA">eSATA</a>.</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">"SRIS" redirects here. For the singular of the plural, see <a href="/wiki/SRI_(disambiguation)" class="mw-redirect mw-disambig" title="SRI (disambiguation)">SRI (disambiguation)</a>.</div> <p class="mw-empty-elt"> </p> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">SATA Express</caption><tbody><tr><td colspan="2" class="infobox-image"><span typeof="mw:File"><a href="/wiki/File:SATA_Express_logo.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/0f/SATA_Express_logo.svg/120px-SATA_Express_logo.svg.png" decoding="async" width="120" height="117" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/0f/SATA_Express_logo.svg/180px-SATA_Express_logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/0f/SATA_Express_logo.svg/240px-SATA_Express_logo.svg.png 2x" data-file-width="183" data-file-height="178" /></a></span><div class="infobox-caption">Revision 3.2 of the Serial ATA specification standardizes SATA Express<sup id="cite_ref-sata-3.2_1-0" class="reference"><a href="#cite_note-sata-3.2-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup></div></td></tr><tr><th scope="row" class="infobox-label">Year created</th><td class="infobox-data">2013</td></tr><tr><th scope="row" class="infobox-label">Speed</th><td class="infobox-data">Up to 16 <a href="/wiki/Gbit/s" class="mw-redirect" title="Gbit/s">Gbit/s</a></td></tr><tr><th scope="row" class="infobox-label">Style</th><td class="infobox-data"><a href="/wiki/Serial_communication" title="Serial communication">Serial</a></td></tr><tr><th scope="row" class="infobox-label">Hotplugging interface</th><td class="infobox-data">Yes<sup id="cite_ref-sata-3.2_1-1" class="reference"><a href="#cite_note-sata-3.2-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label">Website</th><td class="infobox-data"><span class="url"><a rel="nofollow" class="external text" href="https://www.sata-io.org/">www<wbr />.sata-io<wbr />.org</a></span></td></tr></tbody></table> <p><b>SATA Express</b> (sometimes unofficially shortened to <b>SATAe</b>) is a <a href="/wiki/Computer_bus" class="mw-redirect" title="Computer bus">computer bus</a> <a href="/wiki/Interface_(computing)" title="Interface (computing)">interface</a> that supports both <a href="/wiki/Serial_ATA" class="mw-redirect" title="Serial ATA">Serial ATA</a> (SATA) and <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> (PCIe) storage devices, initially standardized in the <a href="/wiki/SATA_3.2" class="mw-redirect" title="SATA 3.2">SATA 3.2</a> specification.<sup id="cite_ref-sata-3.2_1-2" class="reference"><a href="#cite_note-sata-3.2-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> The SATA Express connector used on the host side is <a href="/wiki/Backward_compatible" class="mw-redirect" title="Backward compatible">backward compatible</a> with the standard <a href="/wiki/Serial_ATA#DATACONN" class="mw-redirect" title="Serial ATA">SATA data connector</a>,<sup id="cite_ref-connectors_2-0" class="reference"><a href="#cite_note-connectors-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> while it also provides two <a href="/wiki/PCI_Express_lane" class="mw-redirect" title="PCI Express lane">PCI Express lanes</a> as a pure PCI Express connection to the storage device.<sup id="cite_ref-sata-3.2-announcement_3-0" class="reference"><a href="#cite_note-sata-3.2-announcement-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p><p>Instead of continuing with the SATA interface's usual approach of doubling its native speed with each major version, SATA 3.2 specification included the PCI Express <a href="/wiki/Computer_bus" class="mw-redirect" title="Computer bus">bus</a> for achieving data transfer speeds greater than the <a href="/wiki/SATA_3.0" class="mw-redirect" title="SATA 3.0">SATA 3.0</a> speed limit of 6 <a href="/wiki/Gbit/s" class="mw-redirect" title="Gbit/s">Gbit/s</a>. Designers of the SATA interface concluded that doubling the native SATA speed would take too much time to catch up with the advancements in <a href="/wiki/Solid-state_drive" title="Solid-state drive">solid-state drive</a> (SSD) technology,<sup id="cite_ref-storagesearch_4-0" class="reference"><a href="#cite_note-storagesearch-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> would require too many changes to the SATA standard, and would result in a much greater power consumption compared with the existing PCI Express bus.<sup id="cite_ref-anandtech-7843_5-0" class="reference"><a href="#cite_note-anandtech-7843-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-pcie-storage_6-0" class="reference"><a href="#cite_note-pcie-storage-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> As a widely adopted computer bus, PCI Express provides sufficient <a href="/wiki/Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a> while allowing easy scaling up by using faster or additional <a href="/wiki/PCI_Express_lane" class="mw-redirect" title="PCI Express lane">lanes</a>.<sup id="cite_ref-pcie-3.0-faq_7-0" class="reference"><a href="#cite_note-pcie-3.0-faq-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> </p><p>In addition to supporting legacy <a href="/wiki/Advanced_Host_Controller_Interface" title="Advanced Host Controller Interface">Advanced Host Controller Interface</a> (AHCI) at the logical interface level, SATA Express also supports <a href="/wiki/NVM_Express" title="NVM Express">NVM Express</a> (NVMe) as the logical device interface for attached PCI Express storage devices. While the support for AHCI ensures software-level backward compatibility with legacy SATA devices and legacy <a href="/wiki/Operating_system" title="Operating system">operating systems</a>, NVM Express is designed to fully utilize high-speed PCI Express storage devices by leveraging their capability of executing many <a href="/wiki/I/O" class="mw-redirect" title="I/O">I/O</a> operations <a href="/wiki/Parallelism_(computing)" class="mw-redirect" title="Parallelism (computing)">in parallel</a>.<sup id="cite_ref-ahci-nvme_8-0" class="reference"><a href="#cite_note-ahci-nvme-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SATA_Express&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:SATA_Express_connectors_on_a_computer_motherboard.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/f3/SATA_Express_connectors_on_a_computer_motherboard.jpg/330px-SATA_Express_connectors_on_a_computer_motherboard.jpg" decoding="async" width="330" height="174" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/f3/SATA_Express_connectors_on_a_computer_motherboard.jpg/495px-SATA_Express_connectors_on_a_computer_motherboard.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/f3/SATA_Express_connectors_on_a_computer_motherboard.jpg/660px-SATA_Express_connectors_on_a_computer_motherboard.jpg 2x" data-file-width="1024" data-file-height="539" /></a><figcaption>Two SATA Express connectors (light gray) on a <a href="/wiki/Computer_motherboard" class="mw-redirect" title="Computer motherboard">computer motherboard</a>; to the right of them are common SATA connectors (dark gray)</figcaption></figure> <p>The Serial ATA (<a href="/wiki/Serial_ATA" class="mw-redirect" title="Serial ATA">SATA</a>) interface was designed primarily for interfacing with <a href="/wiki/Hard_disk_drive" title="Hard disk drive">hard disk drives</a> (HDDs), doubling its native speed with each major revision: maximum SATA transfer speeds went from 1.5 Gbit/s in <a href="/wiki/SATA_1.0" class="mw-redirect" title="SATA 1.0">SATA 1.0</a> (standardized in 2003), through 3 Gbit/s in <a href="/wiki/SATA_2.0" class="mw-redirect" title="SATA 2.0">SATA 2.0</a> (standardized in 2004), to 6 Gbit/s as provided by <a href="/wiki/SATA_3.0" class="mw-redirect" title="SATA 3.0">SATA 3.0</a> (standardized in 2009).<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> SATA has also been selected as the interface for gradually more adopted solid-state drives (<a href="/wiki/Solid-state_drive" title="Solid-state drive">SSDs</a>), but the need for a faster interface became apparent as the speed of SSDs and <a href="/wiki/Hybrid_drive" title="Hybrid drive">hybrid drives</a> increased over time.<sup id="cite_ref-anandtech-7843_5-1" class="reference"><a href="#cite_note-anandtech-7843-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> As an example, some SSDs available in early 2009 were already well over the capabilities of SATA 1.0 and close to the SATA 2.0 maximum transfer speed,<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> while in the second half of 2013 high-end consumer SSDs had already reached the SATA 3.0 speed limit, requiring an even faster interface.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </p><p>While evaluating different approaches to the required speed increase, designers of the SATA interface concluded that extending the SATA interface so it doubles its native speed to 12 Gbit/s would require more than two years, making that approach unsuitable for catching up with advancements in SSD technology.<sup id="cite_ref-storagesearch_4-1" class="reference"><a href="#cite_note-storagesearch-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> At the same time, increasing the native SATA speed to 12 Gbit/s would require too many changes to the SATA standard, ending up in a more costly and less <a href="/wiki/Power_efficiency" class="mw-redirect" title="Power efficiency">power efficient</a> solution compared with the already available and widely adopted PCI Express bus. Thus, PCI Express was selected by the designers of SATA interface, as part of the <a href="/wiki/SATA_3.2" class="mw-redirect" title="SATA 3.2">SATA 3.2</a> revision that was standardized in 2013; extending the SATA specification to also provide a PCI Express interface within the same backward-compatible connector allowed much faster speeds by reusing already existing technology.<sup id="cite_ref-pcie-storage_6-1" class="reference"><a href="#cite_note-pcie-storage-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-sata-io-sata-express_13-0" class="reference"><a href="#cite_note-sata-io-sata-express-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p><p>Some vendors also use proprietary logical interfaces for their flash-based <a href="/wiki/Data_storage" title="Data storage">storage products</a>, connected through the PCI Express bus. Such storage products can use a multi-lane PCI Express link, while interfacing with the operating system through <a href="/wiki/Proprietary_software" title="Proprietary software">proprietary</a> drivers and host interfaces.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> Moreover, as of June 2014<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=SATA_Express&action=edit">[update]</a></sup> there are similar storage products using NVM Express as the non-proprietary logical interface for a PCI Express add-on card.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Availability"><span class="anchor" id="SRIS"></span>Availability</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SATA_Express&action=edit&section=2" title="Edit section: Availability"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Support for SATA Express was initially announced for the Intel 9 Series chipsets, <a href="/wiki/Z97" class="mw-redirect" title="Z97">Z97</a> and <a href="/wiki/H97" class="mw-redirect" title="H97">H97</a> <a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">Platform Controller Hubs</a> (PCHs), with both of them supporting Intel <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> and <a href="/wiki/Haswell_Refresh" class="mw-redirect" title="Haswell Refresh">Haswell Refresh</a> processors; availability of these two chipsets was planned for 2014.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-arstechnica-201405_18-0" class="reference"><a href="#cite_note-arstechnica-201405-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> In December 2013, <a href="/wiki/Asus" title="Asus">Asus</a> unveiled a prototype "<a href="/wiki/Z87" class="mw-redirect" title="Z87">Z87</a>-Deluxe/SATA Express" <a href="/wiki/Motherboard" title="Motherboard">motherboard</a> based on the Intel Z87 chipset, supporting Haswell processors and using additional ASMedia controller to provide SATA Express connectivity; this motherboard was also showcased at <a href="/wiki/Consumer_Electronics_Show" title="Consumer Electronics Show">CES</a> 2014 although no launch date was announced.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> </p><p>In April 2014, Asus also demonstrated support for the so-called <i>separate reference clock with independent <a href="/wiki/Spread_spectrum" title="Spread spectrum">spread spectrum</a> clocking</i> (SRIS) with some of its pre-production SATA Express hardware. SRIS eliminates the need for complex and costly shielding on SATA Express cables required for transmitting PCI Express synchronization signals, by providing a separate <a href="/wiki/Clock_generator" title="Clock generator">clock generator</a> on the storage device with additional support from the motherboard <a href="/wiki/Firmware" title="Firmware">firmware</a>.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> </p><p>In May 2014, Intel Z97 and H97 chipsets became available, bringing support for both SATA Express and <a href="/wiki/M.2" title="M.2">M.2</a>, which is a specification for flash-based storage devices in form of internally mounted computer <a href="/wiki/Expansion_cards" class="mw-redirect" title="Expansion cards">expansion cards</a>. Z97 and H97 chipsets use two <a href="/wiki/PCI_Express_2.0" class="mw-redirect" title="PCI Express 2.0">PCI Express 2.0</a> lanes for each of their SATA Express ports, providing 1 <a href="/wiki/GB/s" class="mw-redirect" title="GB/s">GB/s</a> of bandwidth to PCI Express storage devices.<sup id="cite_ref-arstechnica-201405_18-1" class="reference"><a href="#cite_note-arstechnica-201405-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> The release of these two new chipsets, intended primarily for high-end desktops, was soon followed by the availability of Z97- and H97-based motherboards.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> </p><p>In late August 2014, <a href="/wiki/Intel_X99" title="Intel X99">Intel X99</a> chipset became available, bringing support for both SATA Express and M.2 to the Intel's enthusiast platform. Each of the X99's SATA Express ports requires two PCI Express 2.0 lanes provided by the chipset, while the M.2 slots can use either two 2.0 lanes from the chipset itself, or up to four 3.0 lanes taken directly from the <a href="/wiki/LGA_2011-v3" class="mw-redirect" title="LGA 2011-v3">LGA 2011-v3</a> <a href="/wiki/CPU" class="mw-redirect" title="CPU">CPU</a>. As a result, the X99 provides bandwidths of up to 3.94 GB/s for connected PCI Express storage devices. Following the release of X99 chipset, numerous X99-based motherboards became available.<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> </p><p>In early March 2017, <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a> became available, bringing native support for SATA Express to the AMD <a href="/wiki/Socket_AM4" title="Socket AM4">Socket AM4</a> platform, through use of its accompanying X370, X300, B350, A320 and A300 chipsets. Ryzen also supports M.2 and other forms of PCI Express storage devices, using up to the total of eight PCI Express 3.0 lanes provided by the chipset and the AM4 CPU.<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> As a result, Ryzen provides bandwidths of up to 7.88 GB/s for connected PCI Express storage devices. </p><p>As a form factor, SATA Express is considered a failed standard<sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Manual_of_Style/Words_to_watch#Unsupported_attributions" title="Wikipedia:Manual of Style/Words to watch"><span title="The material near this tag may use weasel words or too-vague attribution. (March 2021)">by whom?</span></a></i>]</sup>, because when SATA Express was introduced, the <a href="/wiki/M.2" title="M.2">M.2</a> form factor and <a href="/wiki/NVM_Express" title="NVM Express">NVMe</a> standards were also launched, gaining much larger popularity than Serial ATA and SATA Express. Not many storage devices utilizing the SATA Express interface were released for consumers, and SATA Express ports quickly disappeared from new motherboards. </p> <div class="mw-heading mw-heading2"><h2 id="Features">Features</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SATA_Express&action=edit&section=3" title="Edit section: Features"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:SATA_Express_interface.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/68/SATA_Express_interface.svg/420px-SATA_Express_interface.svg.png" decoding="async" width="420" height="447" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/68/SATA_Express_interface.svg/630px-SATA_Express_interface.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/68/SATA_Express_interface.svg/840px-SATA_Express_interface.svg.png 2x" data-file-width="583" data-file-height="620" /></a><figcaption>A high-level overview of the SATA Express software architecture, which supports both legacy SATA and PCI Express storage devices, with <a href="/wiki/AHCI" class="mw-redirect" title="AHCI">AHCI</a> and <a href="/wiki/NVMe" class="mw-redirect" title="NVMe">NVMe</a> as the logical device interfaces<sup id="cite_ref-ahci-nvme_8-1" class="reference"><a href="#cite_note-ahci-nvme-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 4">: 4 </span></sup></figcaption></figure> <p>SATA Express interface supports both PCI Express and SATA storage devices by exposing two PCI Express 2.0 or 3.0 lanes and two SATA 3.0 (6 Gbit/s) ports through the same host-side SATA Express connector (but not both at the same time). Exposed PCI Express lanes provide a pure PCI Express connection between the host and storage device, with no additional layers of <a href="/wiki/Bus_(computing)" title="Bus (computing)">bus</a> abstraction.<sup id="cite_ref-sata-3.2-announcement_3-1" class="reference"><a href="#cite_note-sata-3.2-announcement-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-pcie-storage_6-2" class="reference"><a href="#cite_note-pcie-storage-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> The <a href="/wiki/SATA_3.2" class="mw-redirect" title="SATA 3.2">SATA revision 3.2</a> specification, in its gold revision as of August 2013<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=SATA_Express&action=edit">[update]</a></sup>, standardizes the SATA Express and specifies its hardware layout and electrical parameters.<sup id="cite_ref-sata-3.2_1-3" class="reference"><a href="#cite_note-sata-3.2-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> </p><p>The choice of PCI Express also enables scaling up the performance of SATA Express interface by using multiple lanes and different versions of PCI Express. In more detail, using two PCI Express 2.0 lanes provides a total bandwidth of 1000 MB/s (2 × 5 <a href="/wiki/Gigatransfers" class="mw-redirect" title="Gigatransfers">GT</a>/s raw data rate and <a href="/wiki/8b/10b_encoding" title="8b/10b encoding">8b/10b encoding</a>), while using two <a href="/wiki/PCI_Express_3.0" class="mw-redirect" title="PCI Express 3.0">PCI Express 3.0</a> lanes provides 1969 MB/s (2 × 8 GT/s raw data rate and <a href="/wiki/128b/130b_encoding" class="mw-redirect" title="128b/130b encoding">128b/130b encoding</a>).<sup id="cite_ref-sata-3.2-announcement_3-2" class="reference"><a href="#cite_note-sata-3.2-announcement-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-pcie-3.0-faq_7-1" class="reference"><a href="#cite_note-pcie-3.0-faq-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> In comparison, the 6 Gbit/s raw bandwidth of SATA 3.0 equates effectively to 600 MB/s (6 GT/s raw data rate and 8b/10b encoding). </p><p>There are three options available for the logical device <a href="/wiki/Interface_(computing)" title="Interface (computing)">interfaces</a> and command sets used for interfacing with storage devices connected to a SATA Express controller:<sup id="cite_ref-pcie-storage_6-3" class="reference"><a href="#cite_note-pcie-storage-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ahci-nvme_8-2" class="reference"><a href="#cite_note-ahci-nvme-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p> <dl><dt>Legacy SATA</dt> <dd>Used for <a href="/wiki/Backward_compatibility" title="Backward compatibility">backward compatibility</a> with legacy SATA devices, and interfaced through the AHCI driver and legacy SATA 3.0 (6 Gbit/s) ports provided by a SATA Express controller.</dd></dl> <dl><dt>PCI Express using AHCI</dt> <dd>Used for PCI Express SSDs and interfaced through the <a href="/wiki/AHCI" class="mw-redirect" title="AHCI">AHCI</a> driver and provided PCI Express lanes, providing backward compatibility with widespread SATA support in operating systems at the cost of not delivering optimal performance by using AHCI for accessing PCI Express SSDs. AHCI was developed back at the time when the purpose of a <a href="/wiki/Host_bus_adapter" class="mw-redirect" title="Host bus adapter">host bus adapter</a> (HBA) in a system was to connect the CPU/memory subsystem with a much slower storage subsystem based on rotating <a href="/wiki/Magnetic_storage" title="Magnetic storage">magnetic media</a>; as a result, AHCI has some inherent <a href="/wiki/NVMe_vs_AHCI" class="mw-redirect" title="NVMe vs AHCI">inefficiencies</a> when applied to SSD devices, which behave much more like <a href="/wiki/DRAM" class="mw-redirect" title="DRAM">DRAM</a> than like spinning media.</dd></dl> <dl><dt>PCI Express using NVMe</dt> <dd>Used for PCI Express SSDs and interfaced through the <a href="/wiki/NVMe" class="mw-redirect" title="NVMe">NVMe</a> driver and provided PCI Express lanes, as a high-performance and scalable host controller interface designed and optimized especially for interfacing with PCI Express SSDs. NVMe has been designed from the ground up, capitalizing on the low latency and <a href="/wiki/Parallelism_(computing)" class="mw-redirect" title="Parallelism (computing)">parallelism</a> of PCI Express SSDs, and complementing the parallelism of contemporary CPUs, platforms and applications. At a high level, primary <a href="/wiki/NVMe_vs_AHCI" class="mw-redirect" title="NVMe vs AHCI">advantages of NVMe over AHCI</a> relate to NVMe's ability to exploit parallelism in host hardware and software, based on its design advantages that include data transfers with fewer stages, greater depth of <a href="/wiki/Command_queue" title="Command queue">command queues</a>, and more efficient <a href="/wiki/Interrupt" title="Interrupt">interrupt</a> processing.</dd></dl> <div class="mw-heading mw-heading2"><h2 id="Connectors"><span class="anchor" id="SFF-8639"></span><span class="anchor" id="U.2"></span><span class="anchor" id="CONNECTORS"></span>Connectors</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SATA_Express&action=edit&section=4" title="Edit section: Connectors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/M.2" title="M.2">M.2 (NGFF)</a>, <a href="/wiki/Serial_ATA#CONNECTORS" class="mw-redirect" title="Serial ATA">Serial ATA connectors</a>, and <a href="/wiki/U.2" title="U.2">U.2</a></div> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:SATA_Express_motherboard_connection.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/02/SATA_Express_motherboard_connection.svg/370px-SATA_Express_motherboard_connection.svg.png" decoding="async" width="370" height="217" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/02/SATA_Express_motherboard_connection.svg/555px-SATA_Express_motherboard_connection.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/02/SATA_Express_motherboard_connection.svg/740px-SATA_Express_motherboard_connection.svg.png 2x" data-file-width="600" data-file-height="352" /></a><figcaption>SATA Express host-side connector, formally known as the "host plug", accepts both SATA Express and legacy standard SATA data cables.<sup id="cite_ref-sata-io-sata-express_13-1" class="reference"><a href="#cite_note-sata-io-sata-express-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></figcaption></figure> <p>Connectors used for SATA Express were selected specifically to ensure backward compatibility with legacy SATA devices where possible, without the need for additional adapters or converters.<sup id="cite_ref-connectors_2-1" class="reference"><a href="#cite_note-connectors-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> The connector on the host side accepts either one PCI Express SSD or up to two legacy SATA devices, by providing either PCI Express lanes or SATA 3.0 ports depending on the type of connected storage device.<sup id="cite_ref-sata-io-sata-express_13-2" class="reference"><a href="#cite_note-sata-io-sata-express-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p><p>There are five types of SATA Express connectors, differing by their position and purpose:<sup id="cite_ref-connectors_2-2" class="reference"><a href="#cite_note-connectors-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p> <ul><li><i>Host plug</i> is used on motherboards and add-on controllers. This connector is <a href="/wiki/Backward_compatible" class="mw-redirect" title="Backward compatible">backward compatible</a> by accepting legacy standard SATA data cables, resulting in the host plug providing connectivity for up to two SATA devices.</li> <li><i>Host cable receptacle</i> is the host-side connector on SATA Express cables. This connector is not backward compatible.</li> <li><i>Device cable receptacle</i> is the device-side connector on SATA Express cables, backward compatible by accepting one SATA device.</li> <li><i>Device plug</i> is used on SATA Express devices. This connector is partially backward compatible by allowing SATA Express devices to be plugged into <a href="/wiki/U.2" title="U.2">U.2</a> <a href="/wiki/Storage_backplane" class="mw-redirect" title="Storage backplane">backplanes</a><sup id="cite_ref-intel-server-ssds_32-0" class="reference"><a href="#cite_note-intel-server-ssds-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-u.2-sff-8639_34-0" class="reference"><a href="#cite_note-u.2-sff-8639-34"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> or <a href="/wiki/MultiLink_SAS" class="mw-redirect" title="MultiLink SAS">MultiLink SAS</a> receptacles;<sup id="cite_ref-ml-sas-sff-8630_36-0" class="reference"><a href="#cite_note-ml-sas-sff-8630-36"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup> however, a SATA Express device connected that way will be functional only if the host supports PCI Express devices.</li> <li><i>Host receptacle</i> is used on backplanes for mating directly with SATA Express devices, resulting in cableless connections. This connector is backward compatible by accepting one SATA device.</li></ul> <p>The above listed SATA Express connectors provide only two PCI Express lanes, as the result of overall design focusing on a rapid low-cost platform transition. That choice allowed easier backward compatibility with legacy SATA devices, together with making it possible to use cheaper unshielded cables. As of March 2015<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=SATA_Express&action=edit">[update]</a></sup>, some NVM Express devices in form of 2.5-inch drives use the <i>U.2</i> connector (originally known as <i>SFF-8639</i>, with the renaming taking place in June 2015<sup id="cite_ref-tomshardware-u.2_33-1" class="reference"><a href="#cite_note-tomshardware-u.2-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup>),<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> which is expected to gain broader acceptance. The U.2 connector is mechanically identical to the SATA Express device plug, but provides four PCI Express lanes through a different usage of available pins.<sup id="cite_ref-intel-server-ssds_32-1" class="reference"><a href="#cite_note-intel-server-ssds-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> </p><p>The table below summarizes the compatibility of involved connectors. </p> <table class="wikitable" style="margin-left: auto; margin-right: auto; min-width: 60em;"> <caption>Connector mating matrix<sup id="cite_ref-connectors_2-3" class="reference"><a href="#cite_note-connectors-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 1">: 1 </span></sup> </caption> <tbody><tr> <th style="min-width: 9em;">  </th> <th style="min-width: 8.5em;">SATA Express<br />host cable<br />receptacle </th> <th style="min-width: 8.5em;">SATA Express<br />device cable<br />receptacle </th> <th style="min-width: 8.5em;">SATA Express<br />host receptacle </th> <th style="min-width: 8.5em;">SATA cable<br />receptacle </th> <th style="min-width: 8.5em;">U.2 backplane<br />receptacle<sup id="cite_ref-u.2-sff-8639_34-1" class="reference"><a href="#cite_note-u.2-sff-8639-34"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> </th> <th style="min-width: 8.5em;"><a href="/wiki/SAS_MultiLink" class="mw-redirect" title="SAS MultiLink">SAS MultiLink</a><br />receptacle<sup id="cite_ref-ml-sas-sff-8630_36-1" class="reference"><a href="#cite_note-ml-sas-sff-8630-36"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup> </th></tr> <tr> <th>SATA Express<br />host plug </th> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th>SATA Express<br />device plug </th> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<sup id="cite_ref-device-plug-1_42-0" class="reference"><a href="#cite_note-device-plug-1-42"><span class="cite-bracket">[</span>c<span class="cite-bracket">]</span></a></sup> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<sup id="cite_ref-device-plug-1_42-1" class="reference"><a href="#cite_note-device-plug-1-42"><span class="cite-bracket">[</span>c<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th>SATA<br />device plug </th> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<sup id="cite_ref-device-plug-2_43-0" class="reference"><a href="#cite_note-device-plug-2-43"><span class="cite-bracket">[</span>d<span class="cite-bracket">]</span></a></sup> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<sup id="cite_ref-device-plug-2_43-1" class="reference"><a href="#cite_note-device-plug-2-43"><span class="cite-bracket">[</span>d<span class="cite-bracket">]</span></a></sup> </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Compatibility">Compatibility</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SATA_Express&action=edit&section=5" title="Edit section: Compatibility"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Device-level <a href="/wiki/Backward_compatibility" title="Backward compatibility">backward compatibility</a> for SATA Express is ensured by fully supporting legacy SATA 3.0 (6 Gbit/s) storage devices, both on the electrical level and through the required <a href="/wiki/Operating_system" title="Operating system">operating system</a> support. Mechanically, connectors on the host side retain their backward compatibility in a way similar to how <a href="/wiki/USB_3.0" title="USB 3.0">USB 3.0</a> does it –  the new host-side SATA Express connector is made by "stacking" an additional connector on top of two legacy standard SATA data connectors, which are regular SATA 3.0 (6 Gbit/s) ports that can accept legacy SATA devices.<sup id="cite_ref-connectors_2-4" class="reference"><a href="#cite_note-connectors-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-sata-io-sata-express_13-3" class="reference"><a href="#cite_note-sata-io-sata-express-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> This backward compatibility of the host-side SATA Express connector, which is formally known as the host plug, ensures the possibility for attaching legacy SATA devices to hosts equipped with SATA Express controllers. </p><p>Backward compatibility on the software level, provided for legacy operating systems and associated <a href="/wiki/Device_driver" title="Device driver">device drivers</a> that can access only SATA storage devices, is achieved by retaining support for the AHCI <a href="/wiki/Host_adapter" title="Host adapter">controller interface</a> as a legacy logical device interface, as visible from the operating system perspective. Access to storage devices using AHCI as a logical device interface is possible for both SATA SSDs and PCI Express SSDs, so operating systems that do not provide support for NVMe can optionally be configured to interact with PCI Express storage devices as if they were legacy AHCI devices.<sup id="cite_ref-ahci-nvme_8-3" class="reference"><a href="#cite_note-ahci-nvme-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> However, because <a href="/wiki/NVMe_vs_AHCI" class="mw-redirect" title="NVMe vs AHCI">NVMe is far more efficient than AHCI</a> when used with PCI Express SSDs, SATA Express interface is unable to deliver its maximum performance when AHCI is used to access PCI Express storage devices; see <a href="#Features">above</a> for more details. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SATA_Express&action=edit&section=6" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239009302">.mw-parser-output .portalbox{padding:0;margin:0.5em 0;display:table;box-sizing:border-box;max-width:175px;list-style:none}.mw-parser-output .portalborder{border:1px solid var(--border-color-base,#a2a9b1);padding:0.1em;background:var(--background-color-neutral-subtle,#f8f9fa)}.mw-parser-output .portalbox-entry{display:table-row;font-size:85%;line-height:110%;height:1.9em;font-style:italic;font-weight:bold}.mw-parser-output .portalbox-image{display:table-cell;padding:0.2em;vertical-align:middle;text-align:center}.mw-parser-output .portalbox-link{display:table-cell;padding:0.2em 0.2em 0.2em 0.3em;vertical-align:middle}@media(min-width:720px){.mw-parser-output .portalleft{clear:left;float:left;margin:0.5em 1em 0.5em 0}.mw-parser-output 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title="List of device bandwidths">List of device bandwidths</a></li> <li><a href="/wiki/M.2" title="M.2">M.2</a> (formerly known as the Next Generation Form Factor)</li> <li><a href="/wiki/Serial_attached_SCSI" class="mw-redirect" title="Serial attached SCSI">Serial attached SCSI</a> (SAS)</li></ul> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SATA_Express&action=edit&section=7" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-u.2-sff-8639-34"><span class="mw-cite-backlink">^ <a href="#cite_ref-u.2-sff-8639_34-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-u.2-sff-8639_34-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">The U.2 connector was originally known as SFF-8639, with the renaming taking place in June 2015.<sup id="cite_ref-tomshardware-u.2_33-0" class="reference"><a href="#cite_note-tomshardware-u.2-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup></span> </li> <li id="cite_note-ml-sas-sff-8630-36"><span class="mw-cite-backlink">^ <a href="#cite_ref-ml-sas-sff-8630_36-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-ml-sas-sff-8630_36-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">MultiLink SAS receptacle is also known as the SFF-8630 connector.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup></span> </li> <li id="cite_note-device-plug-1-42"><span class="mw-cite-backlink">^ <a href="#cite_ref-device-plug-1_42-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-device-plug-1_42-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">SATA Express device plug mates with the U.2 (SFF-8639) and SAS MultiLink (SFF-8630) connectors, but will be functional only if the host supports PCI Express devices.</span> </li> <li id="cite_note-device-plug-2-43"><span class="mw-cite-backlink">^ <a href="#cite_ref-device-plug-2_43-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-device-plug-2_43-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">SATA device plug mates with the U.2 (SFF-8639) and SAS MultiLink (SFF-8630) connectors, but will be functional only if the host supports SATA devices.</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SATA_Express&action=edit&section=8" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-sata-3.2-1"><span class="mw-cite-backlink">^ <a href="#cite_ref-sata-3.2_1-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-sata-3.2_1-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-sata-3.2_1-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-sata-3.2_1-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output 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title="AnandTech">AnandTech</a>, March 13, 2014, by Kristian Vatto</li> <li><a rel="nofollow" class="external text" href="http://www.tomshardware.com/reviews/intel-ssd-dc-p3700-nvme,3858-2.html">Intel SSD DC P3700 Review: Understanding NVM Express</a>, <a href="/wiki/Tom%27s_Hardware" title="Tom's Hardware">Tom's Hardware</a>, August 13, 2014, by Drew Riley</li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140202110152/http://www.snia.org/sites/default/files/SNIASSSIPCIe101WhitePaper1.12013.pdf">PCIe SSD 101: An Overview of Standards, Markets and Performance</a>, <a href="/wiki/Storage_Networking_Industry_Association" title="Storage Networking Industry Association">SNIA</a>, August 2013, archived from the original on February 2, 2014</li> <li><span><a rel="nofollow" class="external text" href="https://patents.google.com/patent/US20130294023">Interface card mount</a></span> –  US patent 20130294023, November 7, 2013, assigned to Raphael Gay</li> <li><a rel="nofollow" class="external text" href="http://scsita.org/library/multilink-sas/">MultiLink SAS presentations, press releases and roadmaps</a>, <a href="/wiki/SCSI_Trade_Association" title="SCSI Trade Association">SCSI Trade Association</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190101025346/http://www.scsita.org/library/multilink-sas/">Archived</a> January 1, 2019, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a></li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl 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.navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="Technical_and_de_facto_standards_for_wired_computer_buses" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Computer_bus" title="Template:Computer bus"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Computer_bus" title="Template talk:Computer bus"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Computer_bus" title="Special:EditPage/Template:Computer bus"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Technical_and_de_facto_standards_for_wired_computer_buses" style="font-size:114%;margin:0 4em"><a href="/wiki/Technical_standard" title="Technical standard">Technical</a> and <a href="/wiki/De_facto_standard" title="De facto standard"><i>de facto</i> standards</a> for <a href="/wiki/Wired_communication" title="Wired communication">wired</a> <a href="/wiki/Bus_(computing)" title="Bus (computing)">computer buses</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">General</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_bus" title="System bus">System bus</a></li> <li><a href="/wiki/Front-side_bus" title="Front-side bus">Front-side bus</a></li> <li><a href="/wiki/Back-side_bus" title="Back-side bus">Back-side bus</a></li> <li><a href="/wiki/Daisy_chain_(electrical_engineering)" title="Daisy chain (electrical engineering)">Daisy chain</a></li> <li><a href="/wiki/Control_bus" title="Control bus">Control bus</a></li> <li><a href="/wiki/Address_bus" class="mw-redirect" title="Address bus">Address bus</a></li> <li><a href="/wiki/Bus_contention" title="Bus contention">Bus contention</a></li> <li><a href="/wiki/Bus_mastering" title="Bus mastering">Bus mastering</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a></li> <li><a href="/wiki/Plug_and_play" title="Plug and play">Plug and play</a></li> <li><a href="/wiki/List_of_interface_bit_rates#Computer_buses" title="List of interface bit rates">List of bus bandwidths</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Standards</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/SS-50_bus" title="SS-50 bus">SS-50 bus</a></li> <li><a href="/wiki/S-100_bus" title="S-100 bus">S-100 bus</a></li> <li><a href="/wiki/Multibus" title="Multibus">Multibus</a></li> <li><a href="/wiki/Unibus" title="Unibus">Unibus</a></li> <li><a href="/wiki/VAXBI_bus" title="VAXBI bus">VAXBI</a></li> <li><a href="/wiki/MBus_(SPARC)" title="MBus (SPARC)">MBus</a></li> <li><a href="/wiki/STD_Bus" title="STD Bus">STD Bus</a></li> <li><a href="/wiki/System_Management_Bus" title="System Management Bus">SMBus</a></li> <li><a href="/wiki/Q-Bus" title="Q-Bus">Q-Bus</a></li> <li><a href="/wiki/Europe_Card_Bus" title="Europe Card Bus">Europe Card Bus</a></li> <li><a href="/wiki/Industry_Standard_Architecture" title="Industry Standard Architecture">ISA</a></li> <li><a href="/wiki/STEbus" title="STEbus">STEbus</a></li> <li><a href="/wiki/Amiga_Zorro_II" title="Amiga Zorro II">Zorro II</a></li> <li><a href="/wiki/Amiga_Zorro_III" title="Amiga Zorro III">Zorro III</a></li> <li><a href="/wiki/Computer_Automated_Measurement_and_Control" title="Computer Automated Measurement and Control">CAMAC</a></li> <li><a href="/wiki/FASTBUS" title="FASTBUS">FASTBUS</a></li> <li><a href="/wiki/Low_Pin_Count" title="Low Pin Count">LPC</a></li> <li><a href="/wiki/HP_Precision_Bus" title="HP Precision Bus">HP Precision Bus</a></li> <li><a href="/wiki/Extended_Industry_Standard_Architecture" title="Extended Industry Standard Architecture">EISA</a></li> <li><a href="/wiki/VMEbus" title="VMEbus">VME</a></li> <li><a href="/wiki/VME_eXtensions_for_Instrumentation" title="VME eXtensions for Instrumentation">VXI</a></li> <li><a href="/wiki/VXS" title="VXS">VXS</a></li> <li><a href="/wiki/VPX" title="VPX">VPX</a></li> <li><a href="/wiki/NuBus" title="NuBus">NuBus</a></li> <li><a href="/wiki/TURBOchannel" title="TURBOchannel">TURBOchannel</a></li> <li><a href="/wiki/Micro_Channel_architecture" title="Micro Channel architecture">MCA</a></li> <li><a href="/wiki/SBus" title="SBus">SBus</a></li> <li><a href="/wiki/VESA_Local_Bus" title="VESA Local Bus">VLB</a></li> <li><a href="/wiki/GSC_bus" title="GSC bus">HP GSC bus</a></li> <li><a href="/wiki/InfiniBand" title="InfiniBand">InfiniBand</a></li> <li><a href="/wiki/Ethernet" title="Ethernet">Ethernet</a></li> <li><a href="/wiki/Ultra_Port_Architecture" title="Ultra Port Architecture">UPA</a></li> <li><a href="/wiki/Peripheral_Component_Interconnect" title="Peripheral Component Interconnect">PCI</a></li> <li><a href="/wiki/PCI-X" title="PCI-X">PCI Extended (PCI-X)</a></li> <li><a href="/wiki/PCI_eXtensions_for_Instrumentation" title="PCI eXtensions for Instrumentation">PXI</a></li> <li><a href="/wiki/PCI_Express" title="PCI Express">PCI Express (PCIe)</a></li> <li><a href="/wiki/Accelerated_Graphics_Port" title="Accelerated Graphics Port">AGP</a></li> <li><a href="/wiki/Compute_Express_Link" title="Compute Express Link">Compute Express Link (CXL)</a></li> <li><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface (DMI)</a></li> <li><a href="/wiki/RapidIO" title="RapidIO">RapidIO</a></li> <li><a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">Intel QuickPath Interconnect</a></li> <li><a href="/wiki/NVLink" title="NVLink">NVLink</a></li> <li><a href="/wiki/HyperTransport" title="HyperTransport">HyperTransport</a> <ul><li><a href="/wiki/Infinity_Fabric" class="mw-redirect" title="Infinity Fabric">Infinity Fabric</a></li></ul></li> <li><a href="/wiki/Intel_Ultra_Path_Interconnect" title="Intel Ultra Path Interconnect">Intel Ultra Path Interconnect</a></li> <li><a href="/wiki/Coherent_Accelerator_Processor_Interface" title="Coherent Accelerator Processor Interface">Coherent Accelerator Processor Interface (CAPI)</a></li> <li><a href="/wiki/SpaceWire" title="SpaceWire">SpaceWire</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Storage</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ST-506/ST-412" title="ST-506/ST-412">ST-506</a></li> <li><a href="/wiki/Enhanced_Small_Disk_Interface" title="Enhanced Small Disk Interface">ESDI</a></li> <li><a href="/wiki/Intelligent_Peripheral_Interface" title="Intelligent Peripheral Interface">IPI</a></li> <li><a href="/wiki/Storage_Module_Device" title="Storage Module Device">SMD</a></li> <li><a href="/wiki/Parallel_ATA" title="Parallel ATA">Parallel ATA (PATA)</a></li> <li><a href="/wiki/Bus_and_Tag" title="Bus and Tag">Bus and Tag</a></li> <li><a href="/wiki/Digital_Storage_Systems_Interconnect" title="Digital Storage Systems Interconnect">DSSI</a></li> <li><a href="/wiki/HIPPI" title="HIPPI">HIPPI</a></li> <li><a href="/wiki/SATA" title="SATA">Serial ATA (SATA)</a></li> <li><a href="/wiki/SCSI" title="SCSI">SCSI</a> <ul><li><a href="/wiki/Parallel_SCSI" title="Parallel SCSI">Parallel</a></li> <li><a href="/wiki/Serial_Attached_SCSI" title="Serial Attached SCSI">SAS</a></li></ul></li> <li><a href="/wiki/ESCON" title="ESCON">ESCON</a></li> <li><a href="/wiki/Fibre_Channel" title="Fibre Channel">Fibre Channel</a></li> <li><a href="/wiki/Serial_Storage_Architecture" title="Serial Storage Architecture">SSA</a></li> <li><a class="mw-selflink selflink">SATAe</a></li> <li>PCI Express (via <a href="/wiki/Advanced_Host_Controller_Interface" title="Advanced Host Controller Interface">AHCI</a> or <a href="/wiki/NVM_Express" title="NVM Express">NVMe</a> logical device interface)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Peripheral</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Apple_Desktop_Bus" title="Apple Desktop Bus">Apple Desktop Bus</a></li> <li><a href="/wiki/Atari_SIO" title="Atari SIO">Atari SIO</a></li> <li><a href="/wiki/Digital_Control_Bus" title="Digital Control Bus">DCB</a></li> <li><a href="/wiki/Commodore_bus" title="Commodore bus">Commodore bus</a></li> <li><a href="/wiki/HP-IL" title="HP-IL">HP-IL</a></li> <li><a href="/wiki/HIL_bus" title="HIL bus">HIL</a></li> <li><a href="/wiki/MIDI" title="MIDI">MIDI</a></li> <li><a href="/wiki/RS-232" title="RS-232">RS-232</a></li> <li><a href="/wiki/RS-422" title="RS-422">RS-422</a></li> <li><a href="/wiki/RS-423" title="RS-423">RS-423</a></li> <li><a href="/wiki/RS-485" title="RS-485">RS-485</a></li> <li><a href="/wiki/Lightning_(connector)" title="Lightning (connector)">Lightning</a></li> <li><a href="/wiki/DMX512#DMX512-A" title="DMX512">DMX512-A</a></li> <li><a href="/wiki/IEEE-488" class="mw-redirect" title="IEEE-488">IEEE-488 (GPIB)</a></li> <li><a href="/wiki/IEEE_1284" title="IEEE 1284">IEEE-1284 (parallel port)</a></li> <li><a href="/wiki/IEEE_1394" title="IEEE 1394">IEEE-1394 (FireWire)</a></li> <li><a href="/wiki/UNI/O" title="UNI/O">UNI/O</a></li> <li><a href="/wiki/1-Wire" title="1-Wire">1-Wire</a></li> <li><a href="/wiki/I%C2%B2C" title="I²C">I²C</a> (<a href="/wiki/ACCESS.bus" title="ACCESS.bus">ACCESS.bus</a>, <a href="/wiki/Power_Management_Bus" title="Power Management Bus">PMBus</a>, <a href="/wiki/System_Management_Bus" title="System Management Bus">SMBus</a>)</li> <li><a href="/wiki/I3C_(bus)" title="I3C (bus)">I3C</a></li> <li><a href="/wiki/Serial_Peripheral_Interface" title="Serial Peripheral Interface">SPI</a></li> <li><a href="/wiki/IEC_61030" title="IEC 61030">D²B</a></li> <li><a href="/wiki/Parallel_SCSI" title="Parallel SCSI">Parallel SCSI</a></li> <li><a href="/wiki/Profibus" title="Profibus">Profibus</a></li> <li><a href="/wiki/USB" title="USB">USB</a></li> <li><a href="/wiki/Camera_Link" title="Camera Link">Camera Link</a></li> <li><a href="/wiki/PCI_Express#PCI_Express_External_Cabling" title="PCI Express">External PCIe</a></li> <li><a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Audio</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ADAT_Lightpipe" title="ADAT Lightpipe">ADAT Lightpipe</a></li> <li><a href="/wiki/AES3" title="AES3">AES3</a></li> <li><a href="/wiki/Intel_High_Definition_Audio" title="Intel High Definition Audio">Intel HD Audio</a></li> <li><a href="/wiki/I%C2%B2S" title="I²S">I²S</a></li> <li><a href="/wiki/MADI" title="MADI">MADI</a></li> <li><a href="/wiki/McASP" title="McASP">McASP</a></li> <li><a href="/wiki/S/PDIF" title="S/PDIF">S/PDIF</a></li> <li><a href="/wiki/TOSLINK" title="TOSLINK">TOSLINK</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Portable</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/PC_Card" title="PC Card">PC Card</a></li> <li><a href="/wiki/ExpressCard" title="ExpressCard">ExpressCard</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Embedded</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multidrop_bus" title="Multidrop bus">Multidrop bus</a></li> <li><a href="/wiki/CoreConnect" title="CoreConnect">CoreConnect</a></li> <li><a href="/wiki/Advanced_Microcontroller_Bus_Architecture" title="Advanced Microcontroller Bus Architecture">AMBA</a> (<a href="/wiki/Advanced_eXtensible_Interface" title="Advanced eXtensible Interface">AXI</a>)</li> <li><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a></li> <li><a href="/wiki/SLIMbus" title="SLIMbus">SLIMbus</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div><small>Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.</small><br /><span class="noviewer" typeof="mw:File"><span title="Category"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/16px-Symbol_category_class.svg.png" decoding="async" width="16" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/23px-Symbol_category_class.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/31px-Symbol_category_class.svg.png 2x" data-file-width="180" data-file-height="185" /></span></span> <a href="/wiki/Category:Computer_buses" title="Category:Computer buses">Category</a></div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Solid-state_drives" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Solid-state_drive" title="Template:Solid-state drive"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Solid-state_drive" title="Template talk:Solid-state drive"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Solid-state_drive" title="Special:EditPage/Template:Solid-state drive"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Solid-state_drives" style="font-size:114%;margin:0 4em"><a href="/wiki/Solid-state_drive" title="Solid-state drive">Solid-state drives</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Key terminology</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Encryption" title="Encryption">Encryption</a></li> <li><a href="/wiki/Error_detection_and_correction" title="Error detection and correction">ECC</a></li> <li><a href="/wiki/Flash_file_system" title="Flash file system">Flash file system</a></li> <li><a href="/wiki/Flash_memory" title="Flash memory">Flash memory</a></li> <li><a href="/wiki/Multi-level_cell" title="Multi-level cell">SLC/MLC</a></li> <li><a href="/wiki/Flash_memory_controller" title="Flash memory controller">Flash memory controller</a></li> <li><a href="/wiki/Garbage_collection_(SSD)" class="mw-redirect" title="Garbage collection (SSD)">Garbage collection</a></li> <li><a href="/wiki/IOPS" title="IOPS">IOPS</a></li> <li><a href="/wiki/Bit_rate" title="Bit rate">MB/s</a></li> <li><a href="/wiki/Flash_memory#Memory_wear" title="Flash memory">Memory wear</a></li> <li><a href="/wiki/Open-channel_SSD" title="Open-channel SSD">Open-channel SSD</a></li> <li><a href="/wiki/Write_amplification#Over-provisioning" title="Write amplification">Over-provisioning</a></li> <li><a href="/wiki/Flash_memory#Read_disturb" title="Flash memory">Read disturb</a></li> <li><a href="/wiki/Write_amplification#Secure_erase" title="Write amplification">Secure erase</a></li> <li><a href="/wiki/Solid-state_storage" title="Solid-state storage">Solid-state storage</a></li> <li><a href="/wiki/Trim_(computing)" title="Trim (computing)">Trim command</a></li> <li><a href="/wiki/Wear_leveling" title="Wear leveling">Wear leveling</a></li> <li><a href="/wiki/Write_amplification" title="Write amplification">Write amplification</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Flash manufacturers</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Micron_Technology" title="Micron Technology">Micron</a></li> <li><a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a></li> <li><a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a> <ul><li>Bought <a href="/wiki/Intel" title="Intel">Intel</a>'s NAND flash SSD business and renamed it Solidigm</li></ul></li> <li>Flash Forward (joint venture between <a href="/wiki/Western_Digital" title="Western Digital">Western Digital</a> and <a href="/wiki/Kioxia" title="Kioxia">Kioxia</a>)</li> <li><a href="/wiki/Yangtze_Memory_Technologies" title="Yangtze Memory Technologies">YMTC</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_flash_memory_controller_manufacturers" title="List of flash memory controller manufacturers">Controllers</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Captive</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Western_Digital" title="Western Digital">Western Digital</a> <ul><li><a href="/wiki/SanDisk" title="SanDisk">SanDisk</a></li> <li><a href="/wiki/Fusion-io" title="Fusion-io">Fusion-io</a></li> <li><a href="/wiki/HGST" title="HGST">HGST</a></li> <li><a href="/wiki/STec" title="STec">sTec</a></li></ul></li> <li><a href="/wiki/Kioxia" title="Kioxia">Kioxia</a> <ul><li><a href="/wiki/OCZ" title="OCZ">OCZ</a> (bankrupt, assets sold to Toshiba, which later spun off its SSD and flash business to Kioxia)</li> <li><a href="/wiki/Indilinx" title="Indilinx">Indilinx</a> (bought by OCZ)</li></ul></li> <li><a href="/wiki/Micron_Technology" title="Micron Technology">Micron</a></li> <li><a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a></li> <li><a href="/wiki/Seagate_Technology" title="Seagate Technology">Seagate</a> <ul><li><a href="/wiki/SandForce" title="SandForce">SandForce</a></li></ul></li> <li><a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a> <ul><li>Bought <a href="/wiki/Intel" title="Intel">Intel</a>'s NAND flash SSD business including controllers and renamed it Solidigm</li></ul></li> <li><a href="/w/index.php?title=FADU&action=edit&redlink=1" class="new" title="FADU (page does not exist)">FADU</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Independent</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Greenliant_Systems" title="Greenliant Systems">Greenliant Systems</a></li> <li><a href="/w/index.php?title=Goke_Microelectronics&action=edit&redlink=1" class="new" title="Goke Microelectronics (page does not exist)">Goke</a></li> <li><a href="/wiki/JMicron" title="JMicron">Maxiotek</a></li> <li><a href="/wiki/Marvell_Technology_Group" class="mw-redirect" title="Marvell Technology Group">Marvell</a></li> <li><a href="/wiki/Phison" title="Phison">Phison</a></li> <li><a href="/wiki/PMC-Sierra" title="PMC-Sierra">PMC-Sierra</a></li> <li><a href="/wiki/Silicon_Motion" title="Silicon Motion">SMI</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">SSD manufacturers</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_solid-state_drive_manufacturers" title="List of solid-state drive manufacturers">List of solid-state drive manufacturers</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Interfaces</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Advanced_Host_Controller_Interface" title="Advanced Host Controller Interface">Advanced Host Controller Interface</a> (AHCI)</li> <li><a href="/wiki/Fibre_Channel" title="Fibre Channel">Fibre Channel</a> (FC)</li> <li><a href="/wiki/NVM_Express" title="NVM Express">NVM Express</a> (NVMe)</li> <li><a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> (PCIe)</li> <li><a class="mw-selflink selflink">SATA Express</a></li> <li><a href="/wiki/Serial_ATA" class="mw-redirect" title="Serial ATA">Serial ATA</a> (SATA)</li> <li><a href="/wiki/Serial_attached_SCSI" class="mw-redirect" title="Serial attached SCSI">Serial attached SCSI</a> (SAS)</li> <li><a href="/wiki/USB" title="USB">Universal Serial Bus</a> (USB)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Configurations</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Hard_disk_drive#Form_factors" title="Hard disk drive">HDD form factors</a></li> <li><a href="/wiki/MSATA" class="mw-redirect" title="MSATA">mSATA</a></li> <li><a href="/wiki/M.2" title="M.2">M.2</a></li> <li><a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> <a href="/wiki/Expansion_card" title="Expansion card">expansion card</a></li> <li><a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a> <ul><li><a href="/wiki/USB-C" title="USB-C">USB Type-C</a></li></ul></li> <li><a href="/wiki/U.2" title="U.2">U.2</a></li> <li><a href="/wiki/U.3" class="mw-redirect" title="U.3">U.3</a></li> <li><a href="/wiki/EDSFF" class="mw-redirect" title="EDSFF">EDSFF</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related organizations</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/International_Committee_for_Information_Technology_Standards" title="International Committee for Information Technology Standards">INCITS</a></li> <li><a href="/wiki/JEDEC" title="JEDEC">JEDEC / JC-42, JC-64.8</a></li> <li><a href="/wiki/Open_NAND_Flash_Interface_Working_Group" title="Open NAND Flash Interface Working Group">ONFI</a></li> <li><a href="/wiki/NVM_Express#History" title="NVM Express">NVMHCI Work Group</a></li> <li><a href="/wiki/USB_Implementers_Forum" title="USB Implementers Forum">USB-IF</a></li> <li><a href="/wiki/Serial_ATA_International_Organization" title="Serial ATA International Organization">SATA-IO</a></li> <li><a href="/wiki/Small_Form_Factor_Committee" title="Small Form Factor Committee">SFF Committee</a></li> <li><a href="/wiki/Storage_Networking_Industry_Association" title="Storage Networking Industry Association">SNIA</a></li> <li><a href="/wiki/Solid_state_storage_initiative" class="mw-redirect" title="Solid state storage initiative">SSSI</a></li> <li><a href="/wiki/SCSI" title="SCSI">T10/SCSI</a></li> <li><a href="/wiki/Fibre_Channel" title="Fibre Channel">T11/FC</a></li> <li><a href="/wiki/Parallel_ATA" title="Parallel ATA">T13/ATA</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div> <ul><li><span class="noviewer" typeof="mw:File"><span title="Category"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/16px-Symbol_category_class.svg.png" decoding="async" width="16" height="16" class="mw-file-element" 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