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Neutral atoms trapped in a far-off resonance optical lattice satisfy... <a class="more_link u-tcGrayDark u-linkUnstyled" data-container=".work_68790699" data-show=".complete" data-hide=".summarized" data-more-link-behavior="true" href="#">more</a></div><div class="complete hidden">Quantum logic gates require qubits that can interact strongly with each other and with external fields while minimizing unwanted coupling to the decohering environment. Neutral atoms trapped in a far-off resonance optical lattice satisfy these criteria. The adjustable parameters of the lattice (e.g., laser polarization, frequency, intensity) allow one to design interactions for which atoms interact strongly via dipole-dipole interactions</div></div></div><ul class="InlineList u-ph0x u-fs13"><li class="InlineList-item logged_in_only"><div class="share_on_academia_work_button"><a class="academia_share Button Button--inverseBlue Button--sm js-bookmark-button" data-academia-share="Work/68790699" data-share-source="work_strip" data-spinner="small_white_hide_contents"><i class="fa fa-plus"></i><span class="work-strip-link-text u-ml1x" data-content="button_text">Bookmark</span></a></div></li><li class="InlineList-item"><ul class="InlineList InlineList--bordered u-ph0x"><li class="InlineList-item InlineList-item--bordered"><span class="InlineList-item-text">by <span itemscope="itemscope" itemprop="author" itemtype="https://schema.org/Person"><a class="u-tcGrayDark u-fw700" data-has-card-for-user="48434445" href="https://mq.academia.edu/GavinBrennen">Gavin Brennen</a><script data-card-contents-for-user="48434445" type="text/json">{"id":48434445,"first_name":"Gavin","last_name":"Brennen","domain_name":"mq","page_name":"GavinBrennen","display_name":"Gavin Brennen","profile_url":"https://mq.academia.edu/GavinBrennen?f_ri=628286","photo":"https://0.academia-photos.com/48434445/12765263/14194797/s65_gavin.brennen.jpg"}</script></span></span></li><li class="js-paper-rank-work_68790699 InlineList-item InlineList-item--bordered hidden"><span class="js-paper-rank-view hidden u-tcGrayDark" data-paper-rank-work-id="68790699"><i class="u-m1x fa fa-bar-chart"></i><strong class="js-paper-rank"></strong></span><script>$(function() { new Works.PaperRankView({ workId: 68790699, container: ".js-paper-rank-work_68790699", }); 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Nanotube","url":"https://www.academia.edu/Documents/in/Carbon_Nanotube?f_ri=628286","nofollow":false},{"id":34019,"name":"Monte Carlo Methods","url":"https://www.academia.edu/Documents/in/Monte_Carlo_Methods?f_ri=628286","nofollow":false},{"id":69841,"name":"Standard Deviation","url":"https://www.academia.edu/Documents/in/Standard_Deviation?f_ri=628286"},{"id":382725,"name":"Delays","url":"https://www.academia.edu/Documents/in/Delays?f_ri=628286"},{"id":628286,"name":"Logic Gates","url":"https://www.academia.edu/Documents/in/Logic_Gates?f_ri=628286"},{"id":808173,"name":"Logic Gate","url":"https://www.academia.edu/Documents/in/Logic_Gate?f_ri=628286"}]}, }) } })();</script></ul></li></ul></div></div><div class="u-borderBottom1 u-borderColorGrayLighter"><div class="clearfix u-pv7x u-mb0x js-work-card work_2195516" data-work_id="2195516" itemscope="itemscope" itemtype="https://schema.org/ScholarlyArticle"><div class="header"><div class="title u-fontSerif u-fs22 u-lineHeight1_3"><a class="u-tcGrayDarkest js-work-link" href="https://www.academia.edu/2195516/FPGA_based_ASIC_power_factor_control_for_three_phase_inverter">FPGA based ASIC power-factor control for three-phase inverter</a></div></div><div class="u-pb4x u-mt3x"><div class="summary u-fs14 u-fw300 u-lineHeight1_5 u-tcGrayDarkest"><div class="summarized">In this paper, a new three-phase inverter power-factor correction PFC scheme is proposed using Field Programmable Gate Array (FPGA) technology all the functions can be implemented in a single chip. The implementation tool fit the entered... <a class="more_link u-tcGrayDark u-linkUnstyled" data-container=".work_2195516" data-show=".complete" data-hide=".summarized" data-more-link-behavior="true" href="#">more</a></div><div class="complete hidden">In this paper, a new three-phase inverter power-factor correction PFC scheme is proposed using Field Programmable Gate Array (FPGA) technology all the functions can be implemented in a single chip. The implementation tool fit the entered design into the target device (XC4008E). Design verification includes functional simulator, in circuit testing and timing simulation the main function is to verify the proper operation of the designed circuit. It will compile a design file into a configuration file that is optimized in terms of use of logic gates and interconnections for the target device. Power factor measures how effective electrical power is being used. A high power factor means that electrical power is being utilized effectively, while a low power factor indicates poor utilization of electrical power. The simplest way to improve power factor is to add power factor correction capacitors to your plant distribution system. In this paper a new technique is proposed to improve the power factor, experimental results are presented to show the effectiveness of the proposed technique. <br /> <br /><a href="http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1223503" rel="nofollow">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1223503</a></div></div></div><ul class="InlineList u-ph0x u-fs13"><li class="InlineList-item logged_in_only"><div class="share_on_academia_work_button"><a class="academia_share Button Button--inverseBlue Button--sm js-bookmark-button" data-academia-share="Work/2195516" data-share-source="work_strip" data-spinner="small_white_hide_contents"><i class="fa fa-plus"></i><span class="work-strip-link-text u-ml1x" data-content="button_text">Bookmark</span></a></div></li><li class="InlineList-item"><div class="download"><a id="c7003ef36a9f8e3f6a45abb460e94fb0" rel="nofollow" data-download="{"attachment_id":30246954,"asset_id":2195516,"asset_type":"Work","always_allow_download":false,"track":null,"button_location":"work_strip","source":null,"hide_modal":null}" class="Button Button--sm Button--inverseGreen js-download-button prompt_button doc_download" href="https://www.academia.edu/attachments/30246954/download_file?st=MTczMjY4OTUxOCw4LjIyMi4yMDguMTQ2&s=work_strip"><i class="fa fa-arrow-circle-o-down fa-lg"></i><span class="u-textUppercase u-ml1x" data-content="button_text">Download</span></a></div></li><li class="InlineList-item"><ul class="InlineList InlineList--bordered u-ph0x"><li class="InlineList-item InlineList-item--bordered"><span class="InlineList-item-text">by <span itemscope="itemscope" itemprop="author" itemtype="https://schema.org/Person"><a class="u-tcGrayDark u-fw700" data-has-card-for-user="460680" href="https://malaya.academia.edu/SaadMekhilef">Prof. Dr. Saad Mekhilef</a><script data-card-contents-for-user="460680" type="text/json">{"id":460680,"first_name":"Prof. Dr. Saad","last_name":"Mekhilef","domain_name":"malaya","page_name":"SaadMekhilef","display_name":"Prof. Dr. Saad Mekhilef","profile_url":"https://malaya.academia.edu/SaadMekhilef?f_ri=628286","photo":"https://0.academia-photos.com/460680/910656/1138162/s65_saad.mekhilef.jpg"}</script></span></span></li><li class="js-paper-rank-work_2195516 InlineList-item InlineList-item--bordered hidden"><span class="js-paper-rank-view hidden u-tcGrayDark" data-paper-rank-work-id="2195516"><i class="u-m1x fa fa-bar-chart"></i><strong class="js-paper-rank"></strong></span><script>$(function() { new Works.PaperRankView({ workId: 2195516, container: ".js-paper-rank-work_2195516", }); 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$(".js-view-count[data-work-id=2195516]").text(description); $(".js-view-count-work_2195516").attr('title', description).tooltip(); }); });</script></span><script>$(function() { $(".js-view-count-work_2195516").removeClass('hidden') })</script></div></li><li class="InlineList-item u-positionRelative" style="max-width: 250px"><div class="u-positionAbsolute" data-has-card-for-ri-list="2195516"><i class="fa fa-tag InlineList-item-icon u-positionRelative"></i>  <a class="InlineList-item-text u-positionRelative">8</a>  </div><span class="InlineList-item-text u-textTruncate u-pl9x"><a class="InlineList-item-text" data-has-card-for-ri="5697" href="https://www.academia.edu/Documents/in/FPGA">FPGA</a>, <script data-card-contents-for-ri="5697" type="text/json">{"id":5697,"name":"FPGA","url":"https://www.academia.edu/Documents/in/FPGA?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="17194" href="https://www.academia.edu/Documents/in/Field-Programmable_Gate_Arrays">Field-Programmable Gate Arrays</a>, <script data-card-contents-for-ri="17194" type="text/json">{"id":17194,"name":"Field-Programmable Gate Arrays","url":"https://www.academia.edu/Documents/in/Field-Programmable_Gate_Arrays?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="21892" href="https://www.academia.edu/Documents/in/DIGITAL_LOGIC_DESIGN">DIGITAL LOGIC DESIGN</a>, <script data-card-contents-for-ri="21892" type="text/json">{"id":21892,"name":"DIGITAL LOGIC DESIGN","url":"https://www.academia.edu/Documents/in/DIGITAL_LOGIC_DESIGN?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="125075" href="https://www.academia.edu/Documents/in/grid_connected_PV_inverters">grid connected PV inverters</a><script data-card-contents-for-ri="125075" type="text/json">{"id":125075,"name":"grid connected PV inverters","url":"https://www.academia.edu/Documents/in/grid_connected_PV_inverters?f_ri=628286","nofollow":false}</script></span></li><script>(function(){ if (true) { new Aedu.ResearchInterestListCard({ el: $('*[data-has-card-for-ri-list=2195516]'), work: {"id":2195516,"title":"FPGA based ASIC power-factor control for three-phase inverter","created_at":"2012-11-25T17:01:17.561-08:00","url":"https://www.academia.edu/2195516/FPGA_based_ASIC_power_factor_control_for_three_phase_inverter?f_ri=628286","dom_id":"work_2195516","summary":"In this paper, a new three-phase inverter power-factor correction PFC scheme is proposed using Field Programmable Gate Array (FPGA) technology all the functions can be implemented in a single chip. The implementation tool fit the entered design into the target device (XC4008E). Design verification includes functional simulator, in circuit testing and timing simulation the main function is to verify the proper operation of the designed circuit. It will compile a design file into a configuration file that is optimized in terms of use of logic gates and interconnections for the target device. Power factor measures how effective electrical power is being used. A high power factor means that electrical power is being utilized effectively, while a low power factor indicates poor utilization of electrical power. The simplest way to improve power factor is to add power factor correction capacitors to your plant distribution system. In this paper a new technique is proposed to improve the power factor, experimental results are presented to show the effectiveness of the proposed technique.\r\n\r\nhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1223503 ","downloadable_attachments":[{"id":30246954,"asset_id":2195516,"asset_type":"Work","always_allow_download":false}],"ordered_authors":[{"id":460680,"first_name":"Prof. Dr. Saad","last_name":"Mekhilef","domain_name":"malaya","page_name":"SaadMekhilef","display_name":"Prof. Dr. Saad Mekhilef","profile_url":"https://malaya.academia.edu/SaadMekhilef?f_ri=628286","photo":"https://0.academia-photos.com/460680/910656/1138162/s65_saad.mekhilef.jpg"}],"research_interests":[{"id":5697,"name":"FPGA","url":"https://www.academia.edu/Documents/in/FPGA?f_ri=628286","nofollow":false},{"id":17194,"name":"Field-Programmable Gate Arrays","url":"https://www.academia.edu/Documents/in/Field-Programmable_Gate_Arrays?f_ri=628286","nofollow":false},{"id":21892,"name":"DIGITAL LOGIC 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$(".js-view-count-work_71339718").removeClass('hidden') })</script></div></li><li class="InlineList-item u-positionRelative" style="max-width: 250px"><div class="u-positionAbsolute" data-has-card-for-ri-list="71339718"><i class="fa fa-tag InlineList-item-icon u-positionRelative"></i>  <a class="InlineList-item-text u-positionRelative">8</a>  </div><span class="InlineList-item-text u-textTruncate u-pl9x"><a class="InlineList-item-text" data-has-card-for-ri="12022" href="https://www.academia.edu/Documents/in/Numerical_Analysis">Numerical Analysis</a>, <script data-card-contents-for-ri="12022" type="text/json">{"id":12022,"name":"Numerical Analysis","url":"https://www.academia.edu/Documents/in/Numerical_Analysis?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="117555" href="https://www.academia.edu/Documents/in/Plasma">Plasma</a>, <script data-card-contents-for-ri="117555" type="text/json">{"id":117555,"name":"Plasma","url":"https://www.academia.edu/Documents/in/Plasma?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="229042" href="https://www.academia.edu/Documents/in/High_Electron_Mobility_Transistors">High Electron Mobility Transistors</a>, <script data-card-contents-for-ri="229042" type="text/json">{"id":229042,"name":"High Electron Mobility Transistors","url":"https://www.academia.edu/Documents/in/High_Electron_Mobility_Transistors?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="250448" href="https://www.academia.edu/Documents/in/Impedance">Impedance</a><script data-card-contents-for-ri="250448" type="text/json">{"id":250448,"name":"Impedance","url":"https://www.academia.edu/Documents/in/Impedance?f_ri=628286","nofollow":false}</script></span></li><script>(function(){ if (true) { new Aedu.ResearchInterestListCard({ el: $('*[data-has-card-for-ri-list=71339718]'), work: {"id":71339718,"title":"Power Amplification at THz via Plasma Wave Excitation in RTD-Gated HEMTs","created_at":"2022-02-13T05:55:55.369-08:00","url":"https://www.academia.edu/71339718/Power_Amplification_at_THz_via_Plasma_Wave_Excitation_in_RTD_Gated_HEMTs?f_ri=628286","dom_id":"work_71339718","summary":null,"downloadable_attachments":[{"id":80725220,"asset_id":71339718,"asset_type":"Work","always_allow_download":false}],"ordered_authors":[{"id":5286030,"first_name":"Grace","last_name":"Xing","domain_name":"independent","page_name":"GraceXing","display_name":"Grace Xing","profile_url":"https://independent.academia.edu/GraceXing?f_ri=628286","photo":"/images/s65_no_pic.png"}],"research_interests":[{"id":12022,"name":"Numerical Analysis","url":"https://www.academia.edu/Documents/in/Numerical_Analysis?f_ri=628286","nofollow":false},{"id":117555,"name":"Plasma","url":"https://www.academia.edu/Documents/in/Plasma?f_ri=628286","nofollow":false},{"id":229042,"name":"High Electron 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data-has-card-for-ri="440" href="https://www.academia.edu/Documents/in/Distributed_Computing">Distributed Computing</a>, <script data-card-contents-for-ri="440" type="text/json">{"id":440,"name":"Distributed Computing","url":"https://www.academia.edu/Documents/in/Distributed_Computing?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="2141" href="https://www.academia.edu/Documents/in/Signal_Processing">Signal Processing</a>, <script data-card-contents-for-ri="2141" type="text/json">{"id":2141,"name":"Signal Processing","url":"https://www.academia.edu/Documents/in/Signal_Processing?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="3974" href="https://www.academia.edu/Documents/in/Telecommunications">Telecommunications</a>, <script data-card-contents-for-ri="3974" type="text/json">{"id":3974,"name":"Telecommunications","url":"https://www.academia.edu/Documents/in/Telecommunications?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="56023" href="https://www.academia.edu/Documents/in/Satellite_Communication">Satellite Communication</a><script data-card-contents-for-ri="56023" type="text/json">{"id":56023,"name":"Satellite Communication","url":"https://www.academia.edu/Documents/in/Satellite_Communication?f_ri=628286","nofollow":false}</script></span></li><script>(function(){ if (true) { new Aedu.ResearchInterestListCard({ el: $('*[data-has-card-for-ri-list=33790737]'), work: {"id":33790737,"title":"Gateway Switching in Q/V Band Satellite Feeder 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Computing","url":"https://www.academia.edu/Documents/in/Distributed_Computing?f_ri=628286","nofollow":false},{"id":2141,"name":"Signal Processing","url":"https://www.academia.edu/Documents/in/Signal_Processing?f_ri=628286","nofollow":false},{"id":3974,"name":"Telecommunications","url":"https://www.academia.edu/Documents/in/Telecommunications?f_ri=628286","nofollow":false},{"id":56023,"name":"Satellite Communication","url":"https://www.academia.edu/Documents/in/Satellite_Communication?f_ri=628286","nofollow":false},{"id":628286,"name":"Logic Gates","url":"https://www.academia.edu/Documents/in/Logic_Gates?f_ri=628286"},{"id":951108,"name":"Attenuation","url":"https://www.academia.edu/Documents/in/Attenuation?f_ri=628286"},{"id":991311,"name":"Signal to Noise Ratio","url":"https://www.academia.edu/Documents/in/Signal_to_Noise_Ratio?f_ri=628286"},{"id":1237788,"name":"Electrical And Electronic Engineering","url":"https://www.academia.edu/Documents/in/Electrical_And_Electronic_Engineering?f_ri=628286"},{"id":1259267,"name":"Switches","url":"https://www.academia.edu/Documents/in/Switches?f_ri=628286"}]}, }) } })();</script></ul></li></ul></div></div><div class="u-borderBottom1 u-borderColorGrayLighter"><div class="clearfix u-pv7x u-mb0x js-work-card work_9668134" data-work_id="9668134" itemscope="itemscope" itemtype="https://schema.org/ScholarlyArticle"><div class="header"><div class="title u-fontSerif u-fs22 u-lineHeight1_3"><a class="u-tcGrayDarkest js-work-link" href="https://www.academia.edu/9668134/Concurrent_Error_Detection_Adder_Based_on_Two_Paths_Output_Computation">Concurrent Error Detection Adder Based on Two Paths Output Computation</a></div></div><div class="u-pb4x u-mt3x"><div class="summary u-fs14 u-fw300 u-lineHeight1_5 u-tcGrayDarkest"><div class="summarized">This paper presents a concurrent error detection(CED) technique for a bit-slice of a full-adder. The proposed method involves computing the sum and carry bits in two alternative ways so that transient faults will be detected by comparing... <a class="more_link u-tcGrayDark u-linkUnstyled" data-container=".work_9668134" data-show=".complete" data-hide=".summarized" data-more-link-behavior="true" href="#">more</a></div><div class="complete hidden">This paper presents a concurrent error detection(CED) technique for a bit-slice of a full-adder. The proposed method involves computing the sum and carry bits in two alternative ways so that transient faults will be detected by comparing the results (Sum and Carry out) obtained from the two computing paths. This technique attempts to reduce the amount of extra hardware and cost of the circuit. In order to avoid the problem of extra time we will propagate the result when the first computation is finished so that dependent computation can commence execution as soon as possible. To prove the efficiency of the proposed method, the circuit is simulated in standard CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. The proposed design involves 12.12% saving in transistor count compared to DMR (Dual Modular Redundancy) style design.</div></div></div><ul class="InlineList u-ph0x u-fs13"><li class="InlineList-item logged_in_only"><div class="share_on_academia_work_button"><a class="academia_share Button Button--inverseBlue Button--sm js-bookmark-button" data-academia-share="Work/9668134" data-share-source="work_strip" data-spinner="small_white_hide_contents"><i class="fa fa-plus"></i><span class="work-strip-link-text u-ml1x" data-content="button_text">Bookmark</span></a></div></li><li class="InlineList-item"><div class="download"><a id="36077866df868902a301866de4c8ec41" rel="nofollow" data-download="{"attachment_id":47682676,"asset_id":9668134,"asset_type":"Work","always_allow_download":false,"track":null,"button_location":"work_strip","source":null,"hide_modal":null}" class="Button Button--sm Button--inverseGreen js-download-button prompt_button doc_download" href="https://www.academia.edu/attachments/47682676/download_file?st=MTczMjY4OTUxOSw4LjIyMi4yMDguMTQ2&s=work_strip"><i class="fa fa-arrow-circle-o-down fa-lg"></i><span class="u-textUppercase u-ml1x" data-content="button_text">Download</span></a></div></li><li class="InlineList-item"><ul class="InlineList InlineList--bordered u-ph0x"><li class="InlineList-item InlineList-item--bordered"><span class="InlineList-item-text">by <span itemscope="itemscope" itemprop="author" itemtype="https://schema.org/Person"><a class="u-tcGrayDark u-fw700" data-has-card-for-user="23103903" href="https://independent.academia.edu/KaLokMan">Ka Lok Man</a><script data-card-contents-for-user="23103903" type="text/json">{"id":23103903,"first_name":"Ka Lok","last_name":"Man","domain_name":"independent","page_name":"KaLokMan","display_name":"Ka Lok Man","profile_url":"https://independent.academia.edu/KaLokMan?f_ri=628286","photo":"/images/s65_no_pic.png"}</script></span></span></li><li class="js-paper-rank-work_9668134 InlineList-item InlineList-item--bordered hidden"><span class="js-paper-rank-view hidden u-tcGrayDark" data-paper-rank-work-id="9668134"><i class="u-m1x fa fa-bar-chart"></i><strong class="js-paper-rank"></strong></span><script>$(function() { new Works.PaperRankView({ workId: 9668134, container: ".js-paper-rank-work_9668134", }); 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$(".js-view-count[data-work-id=9668134]").text(description); $(".js-view-count-work_9668134").attr('title', description).tooltip(); }); });</script></span><script>$(function() { $(".js-view-count-work_9668134").removeClass('hidden') })</script></div></li><li class="InlineList-item u-positionRelative" style="max-width: 250px"><div class="u-positionAbsolute" data-has-card-for-ri-list="9668134"><i class="fa fa-tag InlineList-item-icon u-positionRelative"></i>  <a class="InlineList-item-text u-positionRelative">11</a>  </div><span class="InlineList-item-text u-textTruncate u-pl10x"><a class="InlineList-item-text" data-has-card-for-ri="80870" href="https://www.academia.edu/Documents/in/Parallel_and_Distributed_Computing">Parallel & Distributed Computing</a>, <script data-card-contents-for-ri="80870" type="text/json">{"id":80870,"name":"Parallel \u0026 Distributed Computing","url":"https://www.academia.edu/Documents/in/Parallel_and_Distributed_Computing?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="91936" href="https://www.academia.edu/Documents/in/Hardware">Hardware</a>, <script data-card-contents-for-ri="91936" type="text/json">{"id":91936,"name":"Hardware","url":"https://www.academia.edu/Documents/in/Hardware?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="130129" href="https://www.academia.edu/Documents/in/Transient_analysis">Transient analysis</a>, <script data-card-contents-for-ri="130129" type="text/json">{"id":130129,"name":"Transient analysis","url":"https://www.academia.edu/Documents/in/Transient_analysis?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="168144" href="https://www.academia.edu/Documents/in/Redundancy">Redundancy</a><script data-card-contents-for-ri="168144" type="text/json">{"id":168144,"name":"Redundancy","url":"https://www.academia.edu/Documents/in/Redundancy?f_ri=628286","nofollow":false}</script></span></li><script>(function(){ if (true) { new Aedu.ResearchInterestListCard({ el: $('*[data-has-card-for-ri-list=9668134]'), work: {"id":9668134,"title":"Concurrent Error Detection Adder Based on Two Paths Output Computation","created_at":"2014-12-07T22:41:55.387-08:00","url":"https://www.academia.edu/9668134/Concurrent_Error_Detection_Adder_Based_on_Two_Paths_Output_Computation?f_ri=628286","dom_id":"work_9668134","summary":"This paper presents a concurrent error detection(CED) technique for a bit-slice of a full-adder. The proposed method involves computing the sum and carry bits in two alternative ways so that transient faults will be detected by comparing the results (Sum and Carry out) obtained from the two computing paths. This technique attempts to reduce the amount of extra hardware and cost of the circuit. In order to avoid the problem of extra time we will propagate the result when the first computation is finished so that dependent computation can commence execution as soon as possible. To prove the efficiency of the proposed method, the circuit is simulated in standard CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. The proposed design involves 12.12% saving in transistor count compared to DMR (Dual Modular Redundancy) style design.","downloadable_attachments":[{"id":47682676,"asset_id":9668134,"asset_type":"Work","always_allow_download":false}],"ordered_authors":[{"id":23103903,"first_name":"Ka Lok","last_name":"Man","domain_name":"independent","page_name":"KaLokMan","display_name":"Ka Lok Man","profile_url":"https://independent.academia.edu/KaLokMan?f_ri=628286","photo":"/images/s65_no_pic.png"}],"research_interests":[{"id":80870,"name":"Parallel \u0026 Distributed Computing","url":"https://www.academia.edu/Documents/in/Parallel_and_Distributed_Computing?f_ri=628286","nofollow":false},{"id":91936,"name":"Hardware","url":"https://www.academia.edu/Documents/in/Hardware?f_ri=628286","nofollow":false},{"id":130129,"name":"Transient analysis","url":"https://www.academia.edu/Documents/in/Transient_analysis?f_ri=628286","nofollow":false},{"id":168144,"name":"Redundancy","url":"https://www.academia.edu/Documents/in/Redundancy?f_ri=628286","nofollow":false},{"id":628286,"name":"Logic Gates","url":"https://www.academia.edu/Documents/in/Logic_Gates?f_ri=628286"},{"id":632671,"name":"Full Adder","url":"https://www.academia.edu/Documents/in/Full_Adder?f_ri=628286"},{"id":808173,"name":"Logic Gate","url":"https://www.academia.edu/Documents/in/Logic_Gate?f_ri=628286"},{"id":1111094,"name":"Adders","url":"https://www.academia.edu/Documents/in/Adders?f_ri=628286"},{"id":1183716,"name":"Adder","url":"https://www.academia.edu/Documents/in/Adder?f_ri=628286"},{"id":1983545,"name":"TRANSISTOR COUNT","url":"https://www.academia.edu/Documents/in/TRANSISTOR_COUNT?f_ri=628286"},{"id":2150075,"name":"Error Detection","url":"https://www.academia.edu/Documents/in/Error_Detection?f_ri=628286"}]}, }) } })();</script></ul></li></ul></div></div><div class="u-borderBottom1 u-borderColorGrayLighter"><div class="clearfix u-pv7x u-mb0x js-work-card work_66035202" data-work_id="66035202" itemscope="itemscope" itemtype="https://schema.org/ScholarlyArticle"><div class="header"><div class="title u-fontSerif u-fs22 u-lineHeight1_3"><a class="u-tcGrayDarkest js-work-link" href="https://www.academia.edu/66035202/Wireless_sensors_networks_for_Internet_of_Things">Wireless sensors networks for Internet of Things</a></div></div><div class="u-pb4x u-mt3x"></div><ul class="InlineList u-ph0x u-fs13"><li class="InlineList-item logged_in_only"><div class="share_on_academia_work_button"><a class="academia_share Button Button--inverseBlue Button--sm js-bookmark-button" data-academia-share="Work/66035202" data-share-source="work_strip" data-spinner="small_white_hide_contents"><i class="fa fa-plus"></i><span class="work-strip-link-text u-ml1x" data-content="button_text">Bookmark</span></a></div></li><li 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href="https://independent.academia.edu/MUHAMMADADNANABID">MUHAMMAD ADNAN ABID</a><script data-card-contents-for-user="117725419" type="text/json">{"id":117725419,"first_name":"MUHAMMAD ADNAN","last_name":"ABID","domain_name":"independent","page_name":"MUHAMMADADNANABID","display_name":"MUHAMMAD ADNAN ABID","profile_url":"https://independent.academia.edu/MUHAMMADADNANABID?f_ri=628286","photo":"/images/s65_no_pic.png"}</script></span></span></li><li class="js-paper-rank-work_66035202 InlineList-item InlineList-item--bordered hidden"><span class="js-paper-rank-view hidden u-tcGrayDark" data-paper-rank-work-id="66035202"><i class="u-m1x fa fa-bar-chart"></i><strong class="js-paper-rank"></strong></span><script>$(function() { new Works.PaperRankView({ workId: 66035202, container: ".js-paper-rank-work_66035202", }); });</script></li><li class="js-percentile-work_66035202 InlineList-item InlineList-item--bordered hidden u-tcGrayDark"><span class="percentile-widget hidden"><span class="u-mr2x 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data-card-contents-for-ri="2851" type="text/json">{"id":2851,"name":"RFID","url":"https://www.academia.edu/Documents/in/RFID?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="9136" href="https://www.academia.edu/Documents/in/Wireless_Sensor_Networks">Wireless Sensor Networks</a>, <script data-card-contents-for-ri="9136" type="text/json">{"id":9136,"name":"Wireless Sensor Networks","url":"https://www.academia.edu/Documents/in/Wireless_Sensor_Networks?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="14725" href="https://www.academia.edu/Documents/in/Internet_of_Things">Internet of Things</a><script data-card-contents-for-ri="14725" type="text/json">{"id":14725,"name":"Internet of Things","url":"https://www.academia.edu/Documents/in/Internet_of_Things?f_ri=628286","nofollow":false}</script></span></li><script>(function(){ if (true) { new Aedu.ResearchInterestListCard({ el: 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type="text/json">{"id":2738,"name":"Renewable Energy","url":"https://www.academia.edu/Documents/in/Renewable_Energy?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="15118" href="https://www.academia.edu/Documents/in/Topology">Topology</a>, <script data-card-contents-for-ri="15118" type="text/json">{"id":15118,"name":"Topology","url":"https://www.academia.edu/Documents/in/Topology?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="18186" href="https://www.academia.edu/Documents/in/Renewable_energy_resources">Renewable energy resources</a><script data-card-contents-for-ri="18186" type="text/json">{"id":18186,"name":"Renewable energy resources","url":"https://www.academia.edu/Documents/in/Renewable_energy_resources?f_ri=628286","nofollow":false}</script></span></li><script>(function(){ if (true) { new Aedu.ResearchInterestListCard({ el: $('*[data-has-card-for-ri-list=74142639]'), work: {"id":74142639,"title":"Dual input hybrid buck LC converter","created_at":"2022-03-20T09:10:00.026-07:00","url":"https://www.academia.edu/74142639/Dual_input_hybrid_buck_LC_converter?f_ri=628286","dom_id":"work_74142639","summary":null,"downloadable_attachments":[{"id":83638377,"asset_id":74142639,"asset_type":"Work","always_allow_download":false}],"ordered_authors":[{"id":33591375,"first_name":"Nicolae","last_name":"Muntean","domain_name":"independent","page_name":"MunteanN","display_name":"Nicolae Muntean","profile_url":"https://independent.academia.edu/MunteanN?f_ri=628286","photo":"https://0.academia-photos.com/33591375/12030480/18665478/s65_nicolae.muntean.jpg"}],"research_interests":[{"id":2696,"name":"Power Electronics","url":"https://www.academia.edu/Documents/in/Power_Electronics?f_ri=628286","nofollow":false},{"id":2738,"name":"Renewable Energy","url":"https://www.academia.edu/Documents/in/Renewable_Energy?f_ri=628286","nofollow":false},{"id":15118,"name":"Topology","url":"https://www.academia.edu/Documents/in/Topology?f_ri=628286","nofollow":false},{"id":18186,"name":"Renewable energy resources","url":"https://www.academia.edu/Documents/in/Renewable_energy_resources?f_ri=628286","nofollow":false},{"id":628286,"name":"Logic Gates","url":"https://www.academia.edu/Documents/in/Logic_Gates?f_ri=628286"},{"id":1084703,"name":"Optical Switches","url":"https://www.academia.edu/Documents/in/Optical_Switches?f_ri=628286"}]}, }) } })();</script></ul></li></ul></div></div><div class="u-borderBottom1 u-borderColorGrayLighter"><div class="clearfix u-pv7x u-mb0x js-work-card work_44305200" data-work_id="44305200" itemscope="itemscope" itemtype="https://schema.org/ScholarlyArticle"><div class="header"><div class="title u-fontSerif u-fs22 u-lineHeight1_3"><a class="u-tcGrayDarkest js-work-link" href="https://www.academia.edu/44305200/ANN_Based_1_bit_Full_Adder_SubtractorCircuit_using_Analog_Inputs">ANN Based 1-bit Full Adder-SubtractorCircuit using Analog Inputs</a></div></div><div class="u-pb4x u-mt3x"><div class="summary u-fs14 u-fw300 u-lineHeight1_5 u-tcGrayDarkest"><div class="summarized">In this paper, we have designed the detailed logical circuits of 1-bit full adder- subtractor working on analog inputs while manipulating it through half-adder, NAND, AND and OR gates integrating with ANN and Machine Learning algorithm... <a class="more_link u-tcGrayDark u-linkUnstyled" data-container=".work_44305200" data-show=".complete" data-hide=".summarized" data-more-link-behavior="true" href="#">more</a></div><div class="complete hidden">In this paper, we have designed the detailed logical circuits of 1-bit full adder- subtractor<br />working on analog inputs while manipulating it through half-adder, NAND, AND and OR gates integrating with ANN and Machine Learning algorithm where fixed bias is also applied with each of the designed logical gate combinations. Because hardware implementation is far better than the software manipulation so combination of designed circuit can be used to further design ANN based 4-bit or 8-bit full Adder Subtractor. Creating the new hardware device following the same circuits and techniques can reflect the best performance of Adder Subtractor over analog inputs. Resultant waveform of designed ANN based 1-bit full Adder-Subtractor and its subcircuits are completely in favor of its new hardware implementation.</div></div></div><ul class="InlineList u-ph0x u-fs13"><li class="InlineList-item logged_in_only"><div class="share_on_academia_work_button"><a class="academia_share Button Button--inverseBlue Button--sm js-bookmark-button" data-academia-share="Work/44305200" data-share-source="work_strip" data-spinner="small_white_hide_contents"><i class="fa fa-plus"></i><span class="work-strip-link-text u-ml1x" data-content="button_text">Bookmark</span></a></div></li><li class="InlineList-item"><div class="download"><a id="26bd383ce10bcde65a20a5130289c747" rel="nofollow" data-download="{"attachment_id":64690473,"asset_id":44305200,"asset_type":"Work","always_allow_download":false,"track":null,"button_location":"work_strip","source":null,"hide_modal":null}" class="Button Button--sm Button--inverseGreen js-download-button prompt_button doc_download" href="https://www.academia.edu/attachments/64690473/download_file?st=MTczMjY4OTUxOSw4LjIyMi4yMDguMTQ2&s=work_strip"><i class="fa fa-arrow-circle-o-down fa-lg"></i><span class="u-textUppercase u-ml1x" data-content="button_text">Download</span></a></div></li><li class="InlineList-item"><ul class="InlineList InlineList--bordered u-ph0x"><li class="InlineList-item InlineList-item--bordered"><span class="InlineList-item-text">by <span itemscope="itemscope" itemprop="author" itemtype="https://schema.org/Person"><a class="u-tcGrayDark u-fw700" data-has-card-for-user="174638752" href="https://szabistdubai.academia.edu/HassanMushtaq">Hassan Mushtaq</a><script data-card-contents-for-user="174638752" type="text/json">{"id":174638752,"first_name":"Hassan","last_name":"Mushtaq","domain_name":"szabistdubai","page_name":"HassanMushtaq","display_name":"Hassan Mushtaq","profile_url":"https://szabistdubai.academia.edu/HassanMushtaq?f_ri=628286","photo":"/images/s65_no_pic.png"}</script></span></span></li><li class="js-paper-rank-work_44305200 InlineList-item InlineList-item--bordered hidden"><span class="js-paper-rank-view hidden u-tcGrayDark" data-paper-rank-work-id="44305200"><i class="u-m1x fa fa-bar-chart"></i><strong class="js-paper-rank"></strong></span><script>$(function() { new Works.PaperRankView({ workId: 44305200, container: ".js-paper-rank-work_44305200", }); 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$(".js-view-count[data-work-id=44305200]").text(description); $(".js-view-count-work_44305200").attr('title', description).tooltip(); }); });</script></span><script>$(function() { $(".js-view-count-work_44305200").removeClass('hidden') })</script></div></li><li class="InlineList-item u-positionRelative" style="max-width: 250px"><div class="u-positionAbsolute" data-has-card-for-ri-list="44305200"><i class="fa fa-tag InlineList-item-icon u-positionRelative"></i>  <a class="InlineList-item-text u-positionRelative">16</a>  </div><span class="InlineList-item-text u-textTruncate u-pl10x"><a class="InlineList-item-text" data-has-card-for-ri="465" href="https://www.academia.edu/Documents/in/Artificial_Intelligence">Artificial Intelligence</a>, <script data-card-contents-for-ri="465" type="text/json">{"id":465,"name":"Artificial Intelligence","url":"https://www.academia.edu/Documents/in/Artificial_Intelligence?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="2008" href="https://www.academia.edu/Documents/in/Machine_Learning">Machine Learning</a>, <script data-card-contents-for-ri="2008" type="text/json">{"id":2008,"name":"Machine Learning","url":"https://www.academia.edu/Documents/in/Machine_Learning?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="4758" href="https://www.academia.edu/Documents/in/Electronics">Electronics</a>, <script data-card-contents-for-ri="4758" type="text/json">{"id":4758,"name":"Electronics","url":"https://www.academia.edu/Documents/in/Electronics?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="10628" href="https://www.academia.edu/Documents/in/Analog_Circuit_Design">Analog Circuit Design</a><script data-card-contents-for-ri="10628" type="text/json">{"id":10628,"name":"Analog Circuit Design","url":"https://www.academia.edu/Documents/in/Analog_Circuit_Design?f_ri=628286","nofollow":false}</script></span></li><script>(function(){ if (true) { new Aedu.ResearchInterestListCard({ el: $('*[data-has-card-for-ri-list=44305200]'), work: {"id":44305200,"title":"ANN Based 1-bit Full Adder-SubtractorCircuit using Analog Inputs","created_at":"2020-10-15T13:02:46.281-07:00","url":"https://www.academia.edu/44305200/ANN_Based_1_bit_Full_Adder_SubtractorCircuit_using_Analog_Inputs?f_ri=628286","dom_id":"work_44305200","summary":"In this paper, we have designed the detailed logical circuits of 1-bit full adder- subtractor\nworking on analog inputs while manipulating it through half-adder, NAND, AND and OR gates integrating with ANN and Machine Learning algorithm where fixed bias is also applied with each of the designed logical gate combinations. Because hardware implementation is far better than the software manipulation so combination of designed circuit can be used to further design ANN based 4-bit or 8-bit full Adder Subtractor. Creating the new hardware device following the same circuits and techniques can reflect the best performance of Adder Subtractor over analog inputs. Resultant waveform of designed ANN based 1-bit full Adder-Subtractor and its subcircuits are completely in favor of its new hardware implementation.","downloadable_attachments":[{"id":64690473,"asset_id":44305200,"asset_type":"Work","always_allow_download":false}],"ordered_authors":[{"id":174638752,"first_name":"Hassan","last_name":"Mushtaq","domain_name":"szabistdubai","page_name":"HassanMushtaq","display_name":"Hassan Mushtaq","profile_url":"https://szabistdubai.academia.edu/HassanMushtaq?f_ri=628286","photo":"/images/s65_no_pic.png"}],"research_interests":[{"id":465,"name":"Artificial Intelligence","url":"https://www.academia.edu/Documents/in/Artificial_Intelligence?f_ri=628286","nofollow":false},{"id":2008,"name":"Machine Learning","url":"https://www.academia.edu/Documents/in/Machine_Learning?f_ri=628286","nofollow":false},{"id":4758,"name":"Electronics","url":"https://www.academia.edu/Documents/in/Electronics?f_ri=628286","nofollow":false},{"id":10628,"name":"Analog Circuit Design","url":"https://www.academia.edu/Documents/in/Analog_Circuit_Design?f_ri=628286","nofollow":false},{"id":15097,"name":"Integrated Circuits","url":"https://www.academia.edu/Documents/in/Integrated_Circuits?f_ri=628286"},{"id":17160,"name":"Digital Circuits","url":"https://www.academia.edu/Documents/in/Digital_Circuits?f_ri=628286"},{"id":21892,"name":"DIGITAL LOGIC DESIGN","url":"https://www.academia.edu/Documents/in/DIGITAL_LOGIC_DESIGN?f_ri=628286"},{"id":54123,"name":"Artificial Neural Networks","url":"https://www.academia.edu/Documents/in/Artificial_Neural_Networks?f_ri=628286"},{"id":60834,"name":"Electronic Circuits","url":"https://www.academia.edu/Documents/in/Electronic_Circuits?f_ri=628286"},{"id":195186,"name":"BCD and Binary Adder/Subtractor","url":"https://www.academia.edu/Documents/in/BCD_and_Binary_Adder_Subtractor?f_ri=628286"},{"id":302922,"name":"Electrical Circuit Analysis","url":"https://www.academia.edu/Documents/in/Electrical_Circuit_Analysis?f_ri=628286"},{"id":628286,"name":"Logic Gates","url":"https://www.academia.edu/Documents/in/Logic_Gates?f_ri=628286"},{"id":632671,"name":"Full Adder","url":"https://www.academia.edu/Documents/in/Full_Adder?f_ri=628286"},{"id":1010004,"name":"Analog and Digital Integrated Circuits","url":"https://www.academia.edu/Documents/in/Analog_and_Digital_Integrated_Circuits?f_ri=628286"},{"id":1183716,"name":"Adder","url":"https://www.academia.edu/Documents/in/Adder?f_ri=628286"},{"id":2150121,"name":"Half Adder","url":"https://www.academia.edu/Documents/in/Half_Adder?f_ri=628286"}]}, }) } })();</script></ul></li></ul></div></div><div class="u-borderBottom1 u-borderColorGrayLighter"><div class="clearfix u-pv7x u-mb0x js-work-card work_11721264" data-work_id="11721264" itemscope="itemscope" itemtype="https://schema.org/ScholarlyArticle"><div class="header"><div class="title u-fontSerif u-fs22 u-lineHeight1_3"><a class="u-tcGrayDarkest js-work-link" href="https://www.academia.edu/11721264/An_ultra_low_voltage_rail_to_rail_DTMOS_voltage_follower">An ultra low voltage rail-to-rail DTMOS voltage follower</a></div></div><div class="u-pb4x u-mt3x"></div><ul class="InlineList u-ph0x u-fs13"><li class="InlineList-item logged_in_only"><div class="share_on_academia_work_button"><a class="academia_share Button Button--inverseBlue Button--sm js-bookmark-button" data-academia-share="Work/11721264" data-share-source="work_strip" data-spinner="small_white_hide_contents"><i class="fa fa-plus"></i><span class="work-strip-link-text u-ml1x" data-content="button_text">Bookmark</span></a></div></li><li class="InlineList-item"><div class="download"><a id="46a8fa46ed14bff4a35d573ac61afccc" rel="nofollow" data-download="{"attachment_id":46558888,"asset_id":11721264,"asset_type":"Work","always_allow_download":false,"track":null,"button_location":"work_strip","source":null,"hide_modal":null}" class="Button Button--sm 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data-has-card-for-ri="628286" href="https://www.academia.edu/Documents/in/Logic_Gates">Logic Gates</a>, <script data-card-contents-for-ri="628286" type="text/json">{"id":628286,"name":"Logic Gates","url":"https://www.academia.edu/Documents/in/Logic_Gates?f_ri=628286","nofollow":false}</script><a class="InlineList-item-text" data-has-card-for-ri="808173" href="https://www.academia.edu/Documents/in/Logic_Gate">Logic Gate</a><script data-card-contents-for-ri="808173" type="text/json">{"id":808173,"name":"Logic Gate","url":"https://www.academia.edu/Documents/in/Logic_Gate?f_ri=628286","nofollow":false}</script></span></li><script>(function(){ if (true) { new Aedu.ResearchInterestListCard({ el: $('*[data-has-card-for-ri-list=11721264]'), work: {"id":11721264,"title":"An ultra low voltage rail-to-rail DTMOS voltage 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class="header"><div class="title u-fontSerif u-fs22 u-lineHeight1_3"><a class="u-tcGrayDarkest js-work-link" href="https://www.academia.edu/21602307/Design_and_implementation_of_a_low_cost_embedded_Linux_gateway_for_smart_home_health_monitoring">Design and implementation of a low-cost embedded Linux gateway for smart home health monitoring</a></div></div><div class="u-pb4x u-mt3x"></div><ul class="InlineList u-ph0x u-fs13"><li class="InlineList-item logged_in_only"><div class="share_on_academia_work_button"><a class="academia_share Button Button--inverseBlue Button--sm js-bookmark-button" data-academia-share="Work/21602307" data-share-source="work_strip" data-spinner="small_white_hide_contents"><i class="fa fa-plus"></i><span class="work-strip-link-text u-ml1x" data-content="button_text">Bookmark</span></a></div></li><li class="InlineList-item"><div class="download"><a id="cedcc8028e2e79a2cb6c93985a84be4b" rel="nofollow" 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The clock gating components are inserted in clock tree during VLSI design flow... <a class="more_link u-tcGrayDark u-linkUnstyled" data-container=".work_5086626" data-show=".complete" data-hide=".summarized" data-more-link-behavior="true" href="#">more</a></div><div class="complete hidden">In this paper, a new clock tree distribution design flow and algorithm of clock gates splitting to improve the clock tree power dissipation had been presented. The clock gating components are inserted in clock tree during VLSI design flow to reduce clock tree dynamic power consumption. The effective splitting and physical placement of the clock gates are vital to ensure the clock gating efficiency. The paper presents an approach that is able to achieve optimum power saving on clock tree during full operation mode and shut off mode.</div></div></div><ul class="InlineList u-ph0x u-fs13"><li class="InlineList-item logged_in_only"><div class="share_on_academia_work_button"><a class="academia_share Button Button--inverseBlue Button--sm js-bookmark-button" data-academia-share="Work/5086626" data-share-source="work_strip" data-spinner="small_white_hide_contents"><i class="fa fa-plus"></i><span class="work-strip-link-text u-ml1x" data-content="button_text">Bookmark</span></a></div></li><li class="InlineList-item"><div class="download"><a id="507c6503c00b4662b50bcb9e0ca8c9a3" rel="nofollow" data-download="{"attachment_id":49454715,"asset_id":5086626,"asset_type":"Work","always_allow_download":false,"track":null,"button_location":"work_strip","source":null,"hide_modal":null}" class="Button Button--sm Button--inverseGreen js-download-button prompt_button doc_download" href="https://www.academia.edu/attachments/49454715/download_file?st=MTczMjY4OTUxOSw4LjIyMi4yMDguMTQ2&s=work_strip"><i class="fa fa-arrow-circle-o-down fa-lg"></i><span class="u-textUppercase u-ml1x" data-content="button_text">Download</span></a></div></li><li class="InlineList-item"><ul class="InlineList InlineList--bordered u-ph0x"><li class="InlineList-item InlineList-item--bordered"><span class="InlineList-item-text">by <span itemscope="itemscope" itemprop="author" itemtype="https://schema.org/Person"><a class="u-tcGrayDark u-fw700" data-has-card-for-user="6813355" href="https://independent.academia.edu/priyankarajput3">priyanka rajput</a><script data-card-contents-for-user="6813355" type="text/json">{"id":6813355,"first_name":"priyanka","last_name":"rajput","domain_name":"independent","page_name":"priyankarajput3","display_name":"priyanka rajput","profile_url":"https://independent.academia.edu/priyankarajput3?f_ri=628286","photo":"/images/s65_no_pic.png"}</script></span></span></li><li class="js-paper-rank-work_5086626 InlineList-item InlineList-item--bordered hidden"><span class="js-paper-rank-view hidden u-tcGrayDark" data-paper-rank-work-id="5086626"><i class="u-m1x fa fa-bar-chart"></i><strong class="js-paper-rank"></strong></span><script>$(function() { new Works.PaperRankView({ workId: 5086626, container: ".js-paper-rank-work_5086626", }); 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The clock gating components are inserted in clock tree during VLSI design flow to reduce clock tree dynamic power consumption. The effective splitting and physical placement of the clock gates are vital to ensure the clock gating efficiency. The paper presents an approach that is able to achieve optimum power saving on clock tree during full operation mode and shut off mode.","downloadable_attachments":[{"id":49454715,"asset_id":5086626,"asset_type":"Work","always_allow_download":false}],"ordered_authors":[{"id":6813355,"first_name":"priyanka","last_name":"rajput","domain_name":"independent","page_name":"priyankarajput3","display_name":"priyanka rajput","profile_url":"https://independent.academia.edu/priyankarajput3?f_ri=628286","photo":"/images/s65_no_pic.png"}],"research_interests":[{"id":434,"name":"Vlsi Design","url":"https://www.academia.edu/Documents/in/Vlsi_Design?f_ri=628286","nofollow":false},{"id":9832,"name":"VLSI","url":"https://www.academia.edu/Documents/in/VLSI?f_ri=628286","nofollow":false},{"id":609191,"name":"Logic Design","url":"https://www.academia.edu/Documents/in/Logic_Design?f_ri=628286","nofollow":false},{"id":628286,"name":"Logic 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u-mt3x"><div class="summary u-fs14 u-fw300 u-lineHeight1_5 u-tcGrayDarkest">For reference.<br />Class 12 <br />CBSE</div></div><ul class="InlineList u-ph0x u-fs13"><li class="InlineList-item logged_in_only"><div class="share_on_academia_work_button"><a class="academia_share Button Button--inverseBlue Button--sm js-bookmark-button" data-academia-share="Work/29809628" data-share-source="work_strip" data-spinner="small_white_hide_contents"><i class="fa fa-plus"></i><span class="work-strip-link-text u-ml1x" data-content="button_text">Bookmark</span></a></div></li><li class="InlineList-item"><div class="download"><a id="614f7eaa34cfcd588f84a5f200b50e87" rel="nofollow" data-download="{"attachment_id":50272249,"asset_id":29809628,"asset_type":"Work","always_allow_download":false,"track":null,"button_location":"work_strip","source":null,"hide_modal":null}" class="Button Button--sm Button--inverseGreen js-download-button prompt_button doc_download" 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u-lineHeight1_3"><a class="u-tcGrayDarkest js-work-link" href="https://www.academia.edu/75765840/Smart_gateway_based_communication_for_cloud_of_things">Smart gateway based communication for cloud of things</a></div></div><div class="u-pb4x u-mt3x"><div class="summary u-fs14 u-fw300 u-lineHeight1_5 u-tcGrayDarkest"><div class="summarized">ABSTRACT Integration of Internet of Things with Cloud Computing is gaining importance, with the way the trend is going on in ubiquitous computing world. Literally, everything is going to be connected to the Internet and its data will be... <a class="more_link u-tcGrayDark u-linkUnstyled" data-container=".work_75765840" data-show=".complete" data-hide=".summarized" data-more-link-behavior="true" href="#">more</a></div><div class="complete hidden">ABSTRACT Integration of Internet of Things with Cloud Computing is gaining importance, with the way the trend is going on in ubiquitous computing world. Literally, everything is going to be connected to the Internet and its data will be used for various progressive purposes, creating not only information from it, but also, knowledge and even wisdom. Internet of Things (IoT) becoming so pervasive that it is becoming important to integrate it with cloud computing because of the amount of data IoT&amp;#39;s could generate and their requirement to have the privilege of virtual resource utilization and storage capacity, but also, to make it possible to create more usefulness from the data generated by IoT&amp;#39;s and develop smart applications for the users. Integration of IoT with Cloud Computing, referred here as Cloud of Things, requires smart gateway to perform the rich tasks and preprocessing, which sensors and light IoTs are not capable of doing. This paper focuses on some of the key challenges involved in CoT and the proposal of smart gateway based communication.</div></div></div><ul class="InlineList u-ph0x u-fs13"><li class="InlineList-item logged_in_only"><div class="share_on_academia_work_button"><a class="academia_share Button Button--inverseBlue Button--sm js-bookmark-button" data-academia-share="Work/75765840" data-share-source="work_strip" data-spinner="small_white_hide_contents"><i class="fa fa-plus"></i><span class="work-strip-link-text u-ml1x" data-content="button_text">Bookmark</span></a></div></li><li class="InlineList-item"><ul class="InlineList InlineList--bordered u-ph0x"><li class="InlineList-item InlineList-item--bordered"><span class="InlineList-item-text">by <span itemscope="itemscope" itemprop="author" itemtype="https://schema.org/Person"><a class="u-tcGrayDark u-fw700" data-has-card-for-user="35301767" href="https://independent.academia.edu/EuinamHuh">Eui-nam Huh</a><script data-card-contents-for-user="35301767" type="text/json">{"id":35301767,"first_name":"Eui-nam","last_name":"Huh","domain_name":"independent","page_name":"EuinamHuh","display_name":"Eui-nam Huh","profile_url":"https://independent.academia.edu/EuinamHuh?f_ri=628286","photo":"https://0.academia-photos.com/35301767/80511479/69092036/s65_eui-nam.huh.png"}</script></span></span></li><li class="js-paper-rank-work_75765840 InlineList-item InlineList-item--bordered hidden"><span class="js-paper-rank-view hidden u-tcGrayDark" data-paper-rank-work-id="75765840"><i class="u-m1x fa fa-bar-chart"></i><strong class="js-paper-rank"></strong></span><script>$(function() { new Works.PaperRankView({ workId: 75765840, container: ".js-paper-rank-work_75765840", }); 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This paper focuses on some of the key challenges involved in CoT and the proposal of smart gateway based communication.","downloadable_attachments":[],"ordered_authors":[{"id":35301767,"first_name":"Eui-nam","last_name":"Huh","domain_name":"independent","page_name":"EuinamHuh","display_name":"Eui-nam Huh","profile_url":"https://independent.academia.edu/EuinamHuh?f_ri=628286","photo":"https://0.academia-photos.com/35301767/80511479/69092036/s65_eui-nam.huh.png"}],"research_interests":[{"id":422,"name":"Computer Science","url":"https://www.academia.edu/Documents/in/Computer_Science?f_ri=628286","nofollow":false},{"id":433,"name":"Computer Architecture","url":"https://www.academia.edu/Documents/in/Computer_Architecture?f_ri=628286","nofollow":false},{"id":2879,"name":"Ubiquitous Computing","url":"https://www.academia.edu/Documents/in/Ubiquitous_Computing?f_ri=628286","nofollow":false},{"id":14725,"name":"Internet of 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voltage adjustable CMOS Schmitt trigger using dynamic threshold MOS (DTMOS). Cross-coupled inverter with body control is employed to speed up the switching process, and control the intensity of the feedback. The... <a class="more_link u-tcGrayDark u-linkUnstyled" data-container=".work_7724376" data-show=".complete" data-hide=".summarized" data-more-link-behavior="true" href="#">more</a></div><div class="complete hidden">This paper presents a low voltage adjustable CMOS Schmitt trigger using dynamic threshold MOS (DTMOS). Cross-coupled inverter with body control is employed to speed up the switching process, and control the intensity of the feedback. The proposed Schmitt trigger has been designed using 0.18 μm 0.4 V CMOS technology and analyzed using PSPICE with BSIM3V3 device models. The simulation results show rail-to-rail operation and independently adjustable switching voltages for both low-to-high (VT(LH)) and high-to-low (VT(HL)) as high as 15% of the supply voltage. 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Cross-coupled inverter with body control is employed to speed up the switching process, and control the intensity of the feedback. The proposed Schmitt trigger has been designed using 0.18 μm 0.4 V CMOS technology and analyzed using PSPICE with BSIM3V3 device models. The simulation results show rail-to-rail operation and independently adjustable switching voltages for both low-to-high (VT(LH)) and high-to-low (VT(HL)) as high as 15% of the supply voltage. The power dissipation is 0.13 μW.","downloadable_attachments":[{"id":48360170,"asset_id":7724376,"asset_type":"Work","always_allow_download":false}],"ordered_authors":[{"id":14032744,"first_name":"Apirak","last_name":"Suadet","domain_name":"kmilt","page_name":"ApirakSuadet","display_name":"Apirak Suadet","profile_url":"https://kmilt.academia.edu/ApirakSuadet?f_ri=628286","photo":"https://0.academia-photos.com/14032744/8155091/9126256/s65_apirak.suadet.jpg"}],"research_interests":[{"id":43005,"name":"Hysteresis","url":"https://www.academia.edu/Documents/in/Hysteresis?f_ri=628286","nofollow":false},{"id":229258,"name":"Low Power Electronics","url":"https://www.academia.edu/Documents/in/Low_Power_Electronics?f_ri=628286","nofollow":false},{"id":628286,"name":"Logic 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