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VHDL - Wikipedia

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</a> </li> <li id="toc-Caratteristiche_distintive" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Caratteristiche_distintive"> <div class="vector-toc-text"> <span class="vector-toc-numb">1</span> <span>Caratteristiche distintive</span> </div> </a> <ul id="toc-Caratteristiche_distintive-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Utilizzo_nella_progettazione_elettronica" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Utilizzo_nella_progettazione_elettronica"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Utilizzo nella progettazione elettronica</span> </div> </a> <ul id="toc-Utilizzo_nella_progettazione_elettronica-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Concetti_fondamentali" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Concetti_fondamentali"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Concetti fondamentali</span> </div> </a> <ul id="toc-Concetti_fondamentali-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Esempio_finale" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Esempio_finale"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Esempio finale</span> </div> </a> <ul id="toc-Esempio_finale-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Altri_progetti" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Altri_progetti"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Altri progetti</span> </div> </a> <ul id="toc-Altri_progetti-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Collegamenti_esterni" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Collegamenti_esterni"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Collegamenti esterni</span> </div> </a> <ul id="toc-Collegamenti_esterni-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Indice" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Mostra/Nascondi l&#039;indice" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Mostra/Nascondi l&#039;indice</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">VHDL</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Vai a una voce in un&#039;altra lingua. Disponibile in 36 lingue" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-36" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">36 lingue</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-am mw-list-item"><a href="https://am.wikipedia.org/wiki/%E1%89%AA_%E1%8A%A4%E1%89%BD_%E1%8B%B2_%E1%8A%A4%E1%88%8D" title="ቪ ኤች ዲ ኤል - amarico" lang="am" hreflang="am" data-title="ቪ ኤች ዲ ኤል" data-language-autonym="አማርኛ" data-language-local-name="amarico" class="interlanguage-link-target"><span>አማርኛ</span></a></li><li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%81%D9%8A_%D8%A5%D8%AA%D8%B4_%D8%AF%D9%8A_%D8%A5%D9%84" title="في إتش دي إل - arabo" lang="ar" hreflang="ar" data-title="في إتش دي إل" data-language-autonym="العربية" data-language-local-name="arabo" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-bn mw-list-item"><a href="https://bn.wikipedia.org/wiki/%E0%A6%AD%E0%A6%BF_%E0%A6%8F%E0%A6%87%E0%A6%9A_%E0%A6%A1%E0%A6%BF_%E0%A6%8F%E0%A6%B2" title="ভি এইচ ডি এল - bengalese" lang="bn" hreflang="bn" data-title="ভি এইচ ডি এল" data-language-autonym="বাংলা" data-language-local-name="bengalese" class="interlanguage-link-target"><span>বাংলা</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/VHDL" title="VHDL - catalano" lang="ca" hreflang="ca" data-title="VHDL" data-language-autonym="Català" data-language-local-name="catalano" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/VHDL" title="VHDL - ceco" lang="cs" hreflang="cs" data-title="VHDL" data-language-autonym="Čeština" data-language-local-name="ceco" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-da mw-list-item"><a href="https://da.wikipedia.org/wiki/VHDL" title="VHDL - danese" lang="da" hreflang="da" data-title="VHDL" data-language-autonym="Dansk" data-language-local-name="danese" class="interlanguage-link-target"><span>Dansk</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Very_High_Speed_Integrated_Circuit_Hardware_Description_Language" title="Very High Speed Integrated Circuit Hardware Description Language - tedesco" lang="de" hreflang="de" data-title="Very High Speed Integrated Circuit Hardware Description Language" data-language-autonym="Deutsch" data-language-local-name="tedesco" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-el mw-list-item"><a href="https://el.wikipedia.org/wiki/VHDL" title="VHDL - greco" lang="el" hreflang="el" data-title="VHDL" data-language-autonym="Ελληνικά" data-language-local-name="greco" class="interlanguage-link-target"><span>Ελληνικά</span></a></li><li class="interlanguage-link interwiki-en mw-list-item"><a href="https://en.wikipedia.org/wiki/VHDL" title="VHDL - inglese" lang="en" hreflang="en" data-title="VHDL" data-language-autonym="English" data-language-local-name="inglese" class="interlanguage-link-target"><span>English</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/VHDL" title="VHDL - spagnolo" lang="es" hreflang="es" data-title="VHDL" data-language-autonym="Español" data-language-local-name="spagnolo" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/VHDL" title="VHDL - estone" lang="et" hreflang="et" data-title="VHDL" data-language-autonym="Eesti" data-language-local-name="estone" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-eu mw-list-item"><a href="https://eu.wikipedia.org/wiki/VHDL" title="VHDL - basco" lang="eu" hreflang="eu" data-title="VHDL" data-language-autonym="Euskara" data-language-local-name="basco" class="interlanguage-link-target"><span>Euskara</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%88%DB%8C%E2%80%8C%D8%A7%DA%86%E2%80%8C%D8%AF%DB%8C%E2%80%8C%D8%A7%D9%84" title="وی‌اچ‌دی‌ال - persiano" lang="fa" hreflang="fa" data-title="وی‌اچ‌دی‌ال" data-language-autonym="فارسی" data-language-local-name="persiano" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/VHDL" title="VHDL - finlandese" lang="fi" hreflang="fi" data-title="VHDL" data-language-autonym="Suomi" data-language-local-name="finlandese" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/VHDL" title="VHDL - francese" lang="fr" hreflang="fr" data-title="VHDL" data-language-autonym="Français" data-language-local-name="francese" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/VHDL" title="VHDL - ebraico" lang="he" hreflang="he" data-title="VHDL" data-language-autonym="עברית" data-language-local-name="ebraico" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/VHDL" title="VHDL - ungherese" lang="hu" hreflang="hu" data-title="VHDL" data-language-autonym="Magyar" data-language-local-name="ungherese" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/VHDL" title="VHDL - indonesiano" lang="id" hreflang="id" data-title="VHDL" data-language-autonym="Bahasa Indonesia" data-language-local-name="indonesiano" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-is mw-list-item"><a href="https://is.wikipedia.org/wiki/VHDL" title="VHDL - islandese" lang="is" hreflang="is" data-title="VHDL" data-language-autonym="Íslenska" data-language-local-name="islandese" class="interlanguage-link-target"><span>Íslenska</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/VHDL" title="VHDL - giapponese" lang="ja" hreflang="ja" data-title="VHDL" data-language-autonym="日本語" data-language-local-name="giapponese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/VHDL" title="VHDL - coreano" lang="ko" hreflang="ko" data-title="VHDL" data-language-autonym="한국어" data-language-local-name="coreano" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-mn mw-list-item"><a href="https://mn.wikipedia.org/wiki/VHDL" title="VHDL - mongolo" lang="mn" hreflang="mn" data-title="VHDL" data-language-autonym="Монгол" data-language-local-name="mongolo" class="interlanguage-link-target"><span>Монгол</span></a></li><li class="interlanguage-link interwiki-ms mw-list-item"><a href="https://ms.wikipedia.org/wiki/VHDL" title="VHDL - malese" lang="ms" hreflang="ms" data-title="VHDL" data-language-autonym="Bahasa Melayu" data-language-local-name="malese" class="interlanguage-link-target"><span>Bahasa Melayu</span></a></li><li class="interlanguage-link interwiki-my mw-list-item"><a href="https://my.wikipedia.org/wiki/%E1%80%97%E1%80%BD%E1%80%AE%E1%80%A1%E1%80%AD%E1%80%90%E1%80%BA%E1%80%81%E1%80%BB%E1%80%BA%E1%80%92%E1%80%AE%E1%80%A1%E1%80%9A%E1%80%BA%E1%80%9C%E1%80%BA" title="ဗွီအိတ်ချ်ဒီအယ်လ် - birmano" lang="my" hreflang="my" data-title="ဗွီအိတ်ချ်ဒီအယ်လ်" data-language-autonym="မြန်မာဘာသာ" data-language-local-name="birmano" class="interlanguage-link-target"><span>မြန်မာဘာသာ</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/VHDL" title="VHDL - olandese" lang="nl" hreflang="nl" data-title="VHDL" data-language-autonym="Nederlands" data-language-local-name="olandese" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/VHDL" title="VHDL - norvegese bokmål" lang="nb" hreflang="nb" data-title="VHDL" data-language-autonym="Norsk bokmål" data-language-local-name="norvegese bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/VHDL" title="VHDL - polacco" lang="pl" hreflang="pl" data-title="VHDL" data-language-autonym="Polski" data-language-local-name="polacco" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/VHDL" title="VHDL - portoghese" lang="pt" hreflang="pt" data-title="VHDL" data-language-autonym="Português" data-language-local-name="portoghese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/VHDL" title="VHDL - rumeno" lang="ro" hreflang="ro" data-title="VHDL" data-language-autonym="Română" data-language-local-name="rumeno" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/VHDL" title="VHDL - russo" lang="ru" hreflang="ru" data-title="VHDL" data-language-autonym="Русский" data-language-local-name="russo" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/VHDL" title="VHDL - serbo" lang="sr" hreflang="sr" data-title="VHDL" data-language-autonym="Српски / srpski" data-language-local-name="serbo" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/VHDL" title="VHDL - svedese" lang="sv" hreflang="sv" data-title="VHDL" data-language-autonym="Svenska" data-language-local-name="svedese" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/VHDL" title="VHDL - turco" lang="tr" hreflang="tr" data-title="VHDL" data-language-autonym="Türkçe" data-language-local-name="turco" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/VHDL" title="VHDL - ucraino" lang="uk" hreflang="uk" data-title="VHDL" data-language-autonym="Українська" data-language-local-name="ucraino" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/VHDL" title="VHDL - vietnamita" lang="vi" hreflang="vi" data-title="VHDL" data-language-autonym="Tiếng Việt" data-language-local-name="vietnamita" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/VHDL" title="VHDL - cinese" lang="zh" hreflang="zh" data-title="VHDL" data-language-autonym="中文" data-language-local-name="cinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q209455#sitelinks-wikipedia" title="Modifica collegamenti interlinguistici" class="wbc-editpage">Modifica collegamenti</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> <nav aria-label="Namespace"> <div id="p-associated-pages" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-associated-pages" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-nstab-main" class="selected vector-tab-noicon mw-list-item"><a href="/wiki/VHDL" title="Vedi la voce [c]" accesskey="c"><span>Voce</span></a></li><li id="ca-talk" class="vector-tab-noicon mw-list-item"><a href="/wiki/Discussione:VHDL" rel="discussion" title="Vedi le discussioni relative a questa pagina [t]" accesskey="t"><span>Discussione</span></a></li> </ul> </div> </div> <div id="vector-variants-dropdown" class="vector-dropdown emptyPortlet" > <input type="checkbox" id="vector-variants-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-variants-dropdown" class="vector-dropdown-checkbox " aria-label="Cambia versione linguistica" > <label id="vector-variants-dropdown-label" for="vector-variants-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet" aria-hidden="true" ><span class="vector-dropdown-label-text">italiano</span> </label> <div class="vector-dropdown-content"> <div id="p-variants" class="vector-menu mw-portlet mw-portlet-variants emptyPortlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> </ul> </div> </div> </div> </div> </nav> </div> <div id="right-navigation" class="vector-collapsible"> <nav aria-label="Visite"> <div id="p-views" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-views" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-view" class="selected vector-tab-noicon mw-list-item"><a href="/wiki/VHDL"><span>Leggi</span></a></li><li id="ca-ve-edit" class="vector-tab-noicon mw-list-item"><a href="/w/index.php?title=VHDL&amp;veaction=edit" title="Modifica questa pagina [v]" accesskey="v"><span>Modifica</span></a></li><li id="ca-edit" class="collapsible vector-tab-noicon mw-list-item"><a href="/w/index.php?title=VHDL&amp;action=edit" title="Modifica il wikitesto di questa pagina [e]" accesskey="e"><span>Modifica wikitesto</span></a></li><li id="ca-history" class="vector-tab-noicon mw-list-item"><a href="/w/index.php?title=VHDL&amp;action=history" title="Versioni precedenti di questa pagina [h]" accesskey="h"><span>Cronologia</span></a></li> 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class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/83/Vhdl_signed_adder_source.svg/310px-Vhdl_signed_adder_source.svg.png" decoding="async" width="310" height="332" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/83/Vhdl_signed_adder_source.svg/465px-Vhdl_signed_adder_source.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/83/Vhdl_signed_adder_source.svg/620px-Vhdl_signed_adder_source.svg.png 2x" data-file-width="486" data-file-height="521" /></a><figcaption>Esempio di codice VHDL</figcaption></figure> <p>Il <b>VHDL</b> (acronimo di <i>VHSIC Hardware Description Language</i>, dove "VHSIC" è la sigla di <i>Very High Speed Integrated Circuits</i>), in <a href="/wiki/Informatica" title="Informatica">informatica</a> ed <a href="/wiki/Elettronica" title="Elettronica">elettronica</a>, è un <a href="/wiki/Linguaggio_di_descrizione_dell%27hardware" class="mw-redirect" title="Linguaggio di descrizione dell&#39;hardware">linguaggio di descrizione dell'hardware</a> nato da un progetto del <a href="/wiki/Defense_Advanced_Research_Projects_Agency" title="Defense Advanced Research Projects Agency">Dipartimento della difesa</a> statunitense. Il VHDL nasce nel <a href="/wiki/1987" title="1987">1987</a> quando diventa lo standard <a href="/wiki/IEEE" class="mw-redirect" title="IEEE">IEEE</a> 1076 e nel <a href="/wiki/1993" title="1993">1993</a> ne esce una versione aggiornata. </p><p>È, insieme al <a href="/wiki/Verilog" title="Verilog">Verilog</a>, il linguaggio più usato per la progettazione di <a href="/wiki/Elettronica_digitale" title="Elettronica digitale">sistemi elettronici digitali</a>. È lo strumento fondamentale per la progettazione dei moderni <a href="/wiki/Circuito_integrato" title="Circuito integrato">circuiti integrati</a> digitali e le sue applicazioni spaziano dai <a href="/wiki/Microprocessore" title="Microprocessore">microprocessori</a> (<a href="/wiki/Digital_Signal_Processor" class="mw-redirect" title="Digital Signal Processor">DSP</a>, acceleratori grafici), comunicazioni (<a href="/wiki/Telefono_cellulare" title="Telefono cellulare">cellulari</a>, <a href="/wiki/TV_satellitare" class="mw-redirect" title="TV satellitare">TV satellitare</a>), automobili (<a href="/wiki/Navigatore_satellitare" title="Navigatore satellitare">navigatori</a>, <a href="/wiki/Controllo_di_stabilit%C3%A0" class="mw-redirect" title="Controllo di stabilità">controllo di stabilità</a>) a molte altre. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Caratteristiche_distintive">Caratteristiche distintive</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=VHDL&amp;veaction=edit&amp;section=1" title="Modifica la sezione Caratteristiche distintive" class="mw-editsection-visualeditor"><span>modifica</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=VHDL&amp;action=edit&amp;section=1" title="Edit section&#039;s source code: Caratteristiche distintive"><span>modifica wikitesto</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Il VHDL si presenta per molti versi simile a un vero e proprio <a href="/wiki/Linguaggio_di_programmazione" title="Linguaggio di programmazione">linguaggio di programmazione</a>: in particolare ne usa i tipici <a href="/wiki/Struttura_di_controllo" title="Struttura di controllo">costrutti</a> quali <i>if...then...else</i>. Tuttavia, essendo un linguaggio che descrive il funzionamento e la struttura di componenti <a href="/wiki/Hardware" title="Hardware">hardware</a>, ha alcune caratteristiche distintive rispetto ai linguaggi <i>software</i>. La principale è la concorrenzialità; con questo termine si indica il fatto che diverse parti di un codice scritto in VHDL, una volta tradotte in un circuito elettronico, funzionano contemporaneamente, in quanto dispongono di <i>hardware</i> dedicato; al contrario, in un linguaggio <i>software</i>, le funzioni descritte dal codice sono generalmente eseguite sequenzialmente, riga dopo riga, in quanto dispongono di un unico processore fisico. </p><p>Il VHDL permette di modellare facilmente l'interazione tra i vari blocchi funzionali che compongono un sistema. Queste interazioni sono essenzialmente lo scambio di segnali di controllo e di dati tra i vari oggetti che costituiscono il sistema. In un sistema hardware infatti ogni oggetto da modellare, sia esso una semplice porta logica o un complesso microprocessore, reagisce istantaneamente ai cambiamenti di stato dei propri ingressi producendo dei cambiamenti sulle proprie uscite. Ogni blocco funzionale, a sua volta, è descritto nella relazione ingressi-uscite, usando i classici costrutti del linguaggi di programmazione (if, for, while). </p> <div class="mw-heading mw-heading2"><h2 id="Utilizzo_nella_progettazione_elettronica">Utilizzo nella progettazione elettronica</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=VHDL&amp;veaction=edit&amp;section=2" title="Modifica la sezione Utilizzo nella progettazione elettronica" class="mw-editsection-visualeditor"><span>modifica</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=VHDL&amp;action=edit&amp;section=2" title="Edit section&#039;s source code: Utilizzo nella progettazione elettronica"><span>modifica wikitesto</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Le principali fasi di progettazione sono due: </p> <ul><li>nella prima l'oggetto viene descritto come <code>ENTITY</code>, ovvero come il componente viene visto dall'esterno: questa sezione comprende generalmente le porte di comunicazione, i tempi di ritardo, la larghezza dei <a href="/wiki/Bus_(informatica)" title="Bus (informatica)">bus</a> e i parametri di configurazione;</li> <li>nella seconda si progetta la <code>ARCHITECTURE</code>, ovvero l'architettura interna in cui si descrive come il dispositivo funziona; è questa la parte più importante perché ne costituisce la descrizione funzionale vera e propria.</li></ul> <p>Anche se ognuno può scrivere questa seconda parte come vuole, di solito vengono usati due stili: <i>behavioural</i> o <i>structural</i>. Con il primo, <i>behavioural</i>, si descrive la relazione funzionale ingressi-uscita tramite una funzione o un algoritmo; se invece si usa lo stile <i>structural</i> si rappresenta la struttura interna del dispositivo formata da componenti di più basso livello ed i loro collegamenti (RTL: <i><a href="/wiki/Register_transfer_level" title="Register transfer level">Register transfer level</a></i>), ovvero si decide già con quali oggetti realizzare la funzionalità e li si connette tra di loro. </p><p>Nella progettazione di un nuovo dispositivo, di solito, si parte da una descrizione <i>behavioural</i> di alto livello, per passare poi ad una descrizione RTL ovvero costituito dai componenti fondamentali digitali come i <a href="/wiki/Registro_(informatica)" title="Registro (informatica)">registri</a>, l'<a href="/wiki/Unit%C3%A0_aritmetica_e_logica" title="Unità aritmetica e logica">ALU</a>, i <a href="/wiki/Bus_(informatica)" title="Bus (informatica)">bus</a> e le <a href="/wiki/Macchina_a_stati_finiti" class="mw-redirect" title="Macchina a stati finiti">macchine a stati</a>. </p><p>L'ultimo passo di traduzione del modello RTL in una <i>netlist</i> è eseguito in maniera automatica da un programma software che si chiama "sintetizzatore". Esempi di sintetizzatori commerciali sono ad esempio Synopsys Design Compiler per gli <a href="/wiki/Application_specific_integrated_circuit" title="Application specific integrated circuit">ASIC</a> e ISE <a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> o Quartus <a href="/wiki/Altera" class="mw-redirect" title="Altera">Altera</a> per le <a href="/wiki/Field_programmable_gate_array" class="mw-redirect" title="Field programmable gate array">FPGA</a>. Il sintetizzatore produce una <i>netlist</i> ovvero un file vhdl o verilog di istanze di celle della tecnologia su cui viene "mappato" il circuito digitale. La tecnologia è di solito quella delle FPGA o dei circuiti integrati CMOS. Esistono anche sintetizzatori liberi, quali ad esempio Alliance VHDL o MVSIS. </p><p>Durante l'esecuzione di tutto il flusso di progettazione si effettuano delle simulazioni per verificare che sia mantenuta la congruenza tra i vari modelli <i>behavioural</i>, RTL e <i>netlist</i>. Per effettuare queste simulazioni si usa un <i>test bench</i>, scritto anch'esso in VHDL, che ha la funzione di generare gli stimoli sugli ingressi del circuito e di verificare la correttezza delle uscite. </p> <div class="mw-heading mw-heading2"><h2 id="Concetti_fondamentali">Concetti fondamentali</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=VHDL&amp;veaction=edit&amp;section=3" title="Modifica la sezione Concetti fondamentali" class="mw-editsection-visualeditor"><span>modifica</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=VHDL&amp;action=edit&amp;section=3" title="Edit section&#039;s source code: Concetti fondamentali"><span>modifica wikitesto</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>I costrutti del VHDL si possono dividere in due classi: i costrutti paralleli e i costrutti sequenziali. </p><p>I <b>costrutti paralleli</b> sono eseguiti ogni volta che almeno uno degli ingressi cambia stato; l'esempio più semplice è la descrizione di una porta <a href="/wiki/Algebra_di_Boole" title="Algebra di Boole">AND</a>: </p> <div class="mw-highlight mw-highlight-lang-vhdl mw-content-ltr" dir="ltr"><pre><span></span><span class="n">Z</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="n">A</span><span class="w"> </span><span class="k">and</span><span class="w"> </span><span class="n">B</span><span class="p">;</span><span class="w"> </span> <span class="c1">-- se A o B cambiano valore, Z assume il nuovo valore dopo un intervallo infinitesimo delta (questo per differenziare il tipo di dato signal dal tipo di dato variabile). Se Z fosse una variabile, cambierebbe istantaneamente</span> </pre></div> <p>Per descrivere funzioni più complesse si usano i processi; per esempio per descrivere un <a href="/wiki/Flip-flop" title="Flip-flop">flip-flop</a> si scrive: </p> <div class="mw-highlight mw-highlight-lang-vhdl mw-content-ltr" dir="ltr"><pre><span></span><span class="n">FLIPFLOP</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="k">process</span><span class="w"> </span><span class="p">(</span><span class="n">clock</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">)</span><span class="w"> </span><span class="c1">-- Il processo viene eseguito se almeno uno tra i segnali clock e reset cambia valore </span> <span class="k">begin</span> <span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">reset</span><span class="o">=</span><span class="sc">&#39;1&#39;</span><span class="p">)</span><span class="w"> </span><span class="k">then</span> <span class="w"> </span><span class="n">Q</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="sc">&#39;0&#39;</span><span class="p">;</span> <span class="k">elsif</span><span class="w"> </span><span class="p">(</span><span class="n">clock</span><span class="na">&#39;event</span><span class="w"> </span><span class="k">and</span><span class="w"> </span><span class="n">clock</span><span class="o">=</span><span class="sc">&#39;1&#39;</span><span class="p">)</span><span class="w"> </span><span class="k">then</span> <span class="w"> </span><span class="n">Q</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="n">D</span><span class="p">;</span> <span class="k">end</span><span class="w"> </span><span class="k">if</span><span class="p">;</span> <span class="k">end</span><span class="w"> </span><span class="k">process</span><span class="p">;</span> </pre></div> <p>Tutti i processi presenti in un codice VHDL agiscono come se fossero in funzione contemporaneamente. Ad esempio, supponendo di avere molti processi che descrivono ciascuno un flip-flop come quello precedente, con uguale <i><a href="/wiki/Clock" title="Clock">clock</a></i> di comando per tutti, quando si ha il fronte di salita del <i>clock</i> si deve immaginare che tutti i processi siano eseguiti contemporaneamente, in modo "concorrenziale". Nel caso di un simulatore software, poiché un computer esegue un numero limitato di operazioni contemporanee, quando non una sola alla volta, si tiene traccia dello stato iniziale e si simulano i processi in sequenza calcolando l'effetto che avrebbero avuto se fossero stati paralleli. </p><p>I <b>costrutti sequenziali</b> sono eseguiti riga dopo riga come nei linguaggi per il software. Ad esempio tutti i costrutti all'interno di un processo sono eseguiti sequenzialmente (vedi esempio sopra). Fanno parte dei comandi sequenziali il <i>if...then...else</i>, il <i>case</i>, il <i>for...loop</i> e altri. </p> <div class="mw-heading mw-heading2"><h2 id="Esempio_finale">Esempio finale</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=VHDL&amp;veaction=edit&amp;section=4" title="Modifica la sezione Esempio finale" class="mw-editsection-visualeditor"><span>modifica</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=VHDL&amp;action=edit&amp;section=4" title="Edit section&#039;s source code: Esempio finale"><span>modifica wikitesto</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Un esempio di programma in VHDL: il <a href="/wiki/Flip-flop" title="Flip-flop">flip-flop</a> tipo JK sincrono </p> <div class="mw-highlight mw-highlight-lang-vhdl mw-content-ltr" dir="ltr"><pre><span></span><span class="k">library</span><span class="w"> </span><span class="nn">ieee</span><span class="p">;</span> <span class="k">use</span><span class="w"> </span><span class="nn">ieee.std_logic_1164.</span><span class="k">all</span><span class="p">;</span> <span class="k">entity</span><span class="w"> </span><span class="nc">jk_ff</span><span class="w"> </span><span class="k">is</span> <span class="w"> </span><span class="k">generic</span><span class="w"> </span><span class="p">(</span><span class="n">prop_delay</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="kt">Time</span><span class="w"> </span><span class="o">:=</span><span class="w"> </span><span class="mi">10</span><span class="w"> </span><span class="n">ns</span><span class="p">);</span><span class="w"> </span><span class="c1">-- tempo di propagazione</span> <span class="w"> </span><span class="k">port</span><span class="w"> </span><span class="p">(</span><span class="n">clk</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="k">in</span><span class="w"> </span><span class="kt">std_logic</span><span class="p">;</span><span class="w"> </span><span class="c1">-- segnale di clock</span> <span class="w"> </span><span class="n">j</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="k">in</span><span class="w"> </span><span class="kt">std_logic</span><span class="p">;</span> <span class="w"> </span><span class="n">k</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="k">in</span><span class="w"> </span><span class="kt">std_logic</span><span class="p">;</span> <span class="w"> </span><span class="n">q</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="k">out</span><span class="w"> </span><span class="kt">std_logic</span><span class="p">;</span><span class="w"> </span><span class="c1">-- l&#39;uscita</span> <span class="w"> </span><span class="n">q_n</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="k">out</span><span class="w"> </span><span class="kt">std_logic</span><span class="p">);</span><span class="w"> </span><span class="c1">-- l&#39;uscita negata</span> <span class="k">end</span><span class="w"> </span><span class="nc">jk_ff</span><span class="p">;</span> <span class="k">architecture</span><span class="w"> </span><span class="nc">behavioural</span><span class="w"> </span><span class="k">of</span><span class="w"> </span><span class="nc">jk_ff</span><span class="w"> </span><span class="k">is</span> <span class="w"> </span><span class="k">signal</span><span class="w"> </span><span class="n">outp</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="kt">std_logic</span><span class="p">;</span> <span class="k">begin</span> <span class="w"> </span><span class="n">ff</span><span class="o">:</span><span class="k">process</span><span class="p">(</span><span class="n">clk</span><span class="p">)</span> <span class="w"> </span><span class="k">begin</span> <span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">clk</span><span class="na">&#39;event</span><span class="w"> </span><span class="k">and</span><span class="w"> </span><span class="n">clk</span><span class="o">=</span><span class="sc">&#39;1&#39;</span><span class="p">)</span><span class="w"> </span><span class="k">then</span> <span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">j</span><span class="o">=</span><span class="sc">&#39;1&#39;</span><span class="w"> </span><span class="k">and</span><span class="w"> </span><span class="n">k</span><span class="o">=</span><span class="sc">&#39;0&#39;</span><span class="p">)</span><span class="w"> </span><span class="k">then</span> <span class="w"> </span><span class="n">outp</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="sc">&#39;1&#39;</span><span class="p">;</span> <span class="w"> </span><span class="k">elsif</span><span class="w"> </span><span class="p">(</span><span class="n">j</span><span class="o">=</span><span class="sc">&#39;0&#39;</span><span class="w"> </span><span class="k">and</span><span class="w"> </span><span class="n">k</span><span class="o">=</span><span class="sc">&#39;1&#39;</span><span class="p">)</span><span class="w"> </span><span class="k">then</span> <span class="w"> </span><span class="n">outp</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="sc">&#39;0&#39;</span><span class="p">;</span> <span class="w"> </span><span class="k">elsif</span><span class="w"> </span><span class="p">(</span><span class="n">j</span><span class="o">=</span><span class="sc">&#39;0&#39;</span><span class="w"> </span><span class="k">and</span><span class="w"> </span><span class="n">k</span><span class="o">=</span><span class="sc">&#39;0&#39;</span><span class="p">)</span><span class="w"> </span><span class="k">then</span> <span class="w"> </span><span class="k">null</span><span class="p">;</span> <span class="w"> </span><span class="k">elsif</span><span class="w"> </span><span class="p">(</span><span class="n">j</span><span class="o">=</span><span class="sc">&#39;1&#39;</span><span class="w"> </span><span class="k">and</span><span class="w"> </span><span class="n">k</span><span class="o">=</span><span class="sc">&#39;1&#39;</span><span class="p">)</span><span class="w"> </span><span class="k">then</span> <span class="w"> </span><span class="n">outp</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="k">not</span><span class="w"> </span><span class="n">outp</span><span class="p">;</span> <span class="w"> </span><span class="k">end</span><span class="w"> </span><span class="k">if</span><span class="p">;</span> <span class="w"> </span><span class="k">end</span><span class="w"> </span><span class="k">if</span><span class="p">;</span> <span class="w"> </span><span class="k">end</span><span class="w"> </span><span class="k">process</span><span class="w"> </span><span class="nc">ff</span><span class="p">;</span> <span class="w"> </span><span class="n">q</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="n">outp</span><span class="w"> </span><span class="k">after</span><span class="w"> </span><span class="n">prop_delay</span><span class="p">;</span> <span class="w"> </span><span class="n">q_n</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="k">not</span><span class="w"> </span><span class="n">q</span><span class="w"> </span><span class="k">after</span><span class="w"> </span><span class="n">prop_delay</span><span class="p">;</span> <span class="k">end</span><span class="w"> </span><span class="nc">behavioural</span><span class="p">;</span> <span class="k">architecture</span><span class="w"> </span><span class="nc">structural</span><span class="w"> </span><span class="k">of</span><span class="w"> </span><span class="nc">jk_ff</span><span class="w"> </span><span class="k">is</span> <span class="w"> </span><span class="k">component</span><span class="w"> </span><span class="nc">nand3</span><span class="w"> </span><span class="c1">-- si richiamano delle porte logiche NAND</span> <span class="w"> </span><span class="k">port</span><span class="w"> </span><span class="p">(</span><span class="n">a</span><span class="p">,</span><span class="w"> </span><span class="n">b</span><span class="p">,</span><span class="w"> </span><span class="n">c</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="k">in</span><span class="w"> </span><span class="kt">std_logic</span><span class="p">;</span><span class="w"> </span><span class="c1">-- con 3 ingressi (nand3)</span> <span class="w"> </span><span class="n">q</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="k">out</span><span class="w"> </span><span class="kt">std_logic</span><span class="p">);</span> <span class="w"> </span><span class="k">end</span><span class="w"> </span><span class="k">component</span><span class="p">;</span> <span class="w"> </span><span class="k">component</span><span class="w"> </span><span class="nc">nand2</span> <span class="w"> </span><span class="k">port</span><span class="w"> </span><span class="p">(</span><span class="n">a</span><span class="p">,</span><span class="w"> </span><span class="n">b</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="k">in</span><span class="w"> </span><span class="kt">std_logic</span><span class="p">;</span><span class="w"> </span><span class="c1">-- o 2 ingressi (nand2)</span> <span class="w"> </span><span class="n">q</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="k">out</span><span class="w"> </span><span class="kt">std_logic</span><span class="p">);</span> <span class="w"> </span><span class="k">end</span><span class="w"> </span><span class="k">component</span><span class="p">;</span> <span class="w"> </span><span class="k">signal</span><span class="w"> </span><span class="n">sgn_1</span><span class="p">,</span><span class="w"> </span><span class="n">sgn_2</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="kt">std_logic</span><span class="p">;</span><span class="w"> </span><span class="c1">-- si definiscono i segnali interni</span> <span class="k">begin</span><span class="w"> </span><span class="c1">-- si descrivono le connessioni</span> <span class="w"> </span><span class="n">nand3_a</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="n">nand3</span><span class="w"> </span><span class="k">port</span><span class="w"> </span><span class="k">map</span><span class="w"> </span><span class="p">(</span><span class="n">a</span><span class="o">=&gt;</span><span class="n">j</span><span class="p">,</span><span class="w"> </span><span class="n">b</span><span class="o">=&gt;</span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">c</span><span class="o">=&gt;</span><span class="n">q_n</span><span class="p">,</span><span class="w"> </span><span class="n">q</span><span class="o">=&gt;</span><span class="n">sgn_1</span><span class="p">);</span> <span class="w"> </span><span class="n">nand3_b</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="n">nand3</span><span class="w"> </span><span class="k">port</span><span class="w"> </span><span class="k">map</span><span class="w"> </span><span class="p">(</span><span class="n">a</span><span class="o">=&gt;</span><span class="n">k</span><span class="p">,</span><span class="w"> </span><span class="n">b</span><span class="o">=&gt;</span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">c</span><span class="o">=&gt;</span><span class="n">q</span><span class="p">,</span><span class="w"> </span><span class="n">q</span><span class="o">=&gt;</span><span class="n">sgn_2</span><span class="p">);</span> <span class="w"> </span><span class="n">nand2_a</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="n">nand2</span><span class="w"> </span><span class="k">port</span><span class="w"> </span><span class="k">map</span><span class="w"> </span><span class="p">(</span><span class="n">a</span><span class="o">=&gt;</span><span class="n">sgn_1</span><span class="p">,</span><span class="w"> </span><span class="n">b</span><span class="o">=&gt;</span><span class="n">q_n</span><span class="p">,</span><span class="w"> </span><span class="n">q</span><span class="o">=&gt;</span><span class="n">q</span><span class="p">);</span> <span class="w"> </span><span class="n">nand2_b</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="n">nand2</span><span class="w"> </span><span class="k">port</span><span class="w"> </span><span class="k">map</span><span class="w"> </span><span class="p">(</span><span class="n">a</span><span class="o">=&gt;</span><span class="n">sgn_2</span><span class="p">,</span><span class="w"> </span><span class="n">b</span><span class="o">=&gt;</span><span class="n">q</span><span class="p">,</span><span class="w"> </span><span class="n">q</span><span class="o">=&gt;</span><span class="n">q_n</span><span class="p">);</span> <span class="k">end</span><span class="w"> </span><span class="nc">structural</span><span class="p">;</span> </pre></div> <div class="mw-heading mw-heading2"><h2 id="Altri_progetti">Altri progetti</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=VHDL&amp;veaction=edit&amp;section=5" title="Modifica la sezione Altri progetti" class="mw-editsection-visualeditor"><span>modifica</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=VHDL&amp;action=edit&amp;section=5" title="Edit section&#039;s source code: Altri progetti"><span>modifica wikitesto</span></a><span class="mw-editsection-bracket">]</span></span></div> <div id="interProject" class="toccolours" style="display: none; clear: both; margin-top: 2em"><p id="sisterProjects" style="background-color: #efefef; color: black; font-weight: bold; margin: 0"><span>Altri progetti</span></p><ul title="Collegamenti verso gli altri progetti Wikimedia"> <li class="" title=""><span class="plainlinks" title="commons:Category:VHDL"><a class="external text" href="https://commons.wikimedia.org/wiki/Category:VHDL?uselang=it">Wikimedia Commons</a></span></li></ul></div> <ul><li><span typeof="mw:File"><a href="https://commons.wikimedia.org/wiki/?uselang=it" title="Collabora a Wikimedia Commons"><img alt="Collabora a Wikimedia Commons" src="//upload.wikimedia.org/wikipedia/commons/thumb/4/4a/Commons-logo.svg/18px-Commons-logo.svg.png" decoding="async" width="18" height="24" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/4a/Commons-logo.svg/27px-Commons-logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/4a/Commons-logo.svg/36px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></a></span> <span class="plainlinks"><a class="external text" href="https://commons.wikimedia.org/wiki/?uselang=it">Wikimedia Commons</a></span> contiene immagini o altri file su <b><span class="plainlinks"><a class="external text" href="https://commons.wikimedia.org/wiki/Category:VHDL?uselang=it">VHDL</a></span></b></li></ul> <div class="mw-heading mw-heading2"><h2 id="Collegamenti_esterni">Collegamenti esterni</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=VHDL&amp;veaction=edit&amp;section=6" title="Modifica la sezione Collegamenti esterni" class="mw-editsection-visualeditor"><span>modifica</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=VHDL&amp;action=edit&amp;section=6" title="Edit section&#039;s source code: Collegamenti esterni"><span>modifica wikitesto</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>(<span style="font-weight:bolder; font-size:80%"><abbr title="inglese">EN</abbr></span>) <a rel="nofollow" class="external text" href="http://ghdl.free.fr/">GHDL</a>: simulatore VHDL con licenza GPL</li> <li>(<span style="font-weight:bolder; font-size:80%"><abbr title="inglese">EN</abbr></span>) <a rel="nofollow" class="external text" href="http://www.model.com">Compilatore Modelsim</a></li> <li>(<span style="font-weight:bolder; font-size:80%"><abbr title="inglese">EN</abbr></span>) <a rel="nofollow" class="external text" href="http://www.symphonyeda.com">Compilatore SymphonyEDA</a></li> <li><cite class="citation libro" style="font-style:normal">(<span style="font-weight:bolder; font-size:80%"><abbr title="inglese">EN</abbr></span>) Peter Ashenden, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170212090951/https://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf"><span style="font-style:italic;">VHDL Cookbook</span></a> (<span style="font-weight: bolder; font-size:80%"><abbr title="documento in formato PDF">PDF</abbr></span>), 1ª&#160;ed., 1990. <small>URL consultato l'11 febbraio 2017</small> <small>(archiviato dall'<abbr title="https&#58;//tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf">url originale</abbr> il 12 febbraio 2017)</small>.</cite></li> <li><cite class="citation libro" style="font-style:normal">(<span style="font-weight:bolder; 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esiste)">854</a><b>&#160;·</b> <a href="/w/index.php?title=Software_configuration_management&amp;action=edit&amp;redlink=1" class="new" title="Software configuration management (la pagina non esiste)">828</a><b>&#160;·</b> <a href="/w/index.php?title=Software_test_documentation&amp;action=edit&amp;redlink=1" class="new" title="Software test documentation (la pagina non esiste)">829</a><b>&#160;·</b> <a href="/w/index.php?title=Futurebus&amp;action=edit&amp;redlink=1" class="new" title="Futurebus (la pagina non esiste)">896</a><b>&#160;·</b> <a href="/wiki/Single_UNIX_Specification" title="Single UNIX Specification">1003</a><b>&#160;·</b> <a href="/wiki/VMEbus" title="VMEbus">1014</a><b>&#160;·</b> <a href="/wiki/Software_Design_Description" title="Software Design Description">1016</a><b>&#160;·</b> <a class="mw-selflink selflink">1076</a><b>&#160;·</b> <a href="/wiki/JTAG" title="JTAG">1149.1</a><b>&#160;·</b> <a href="/w/index.php?title=PILOT&amp;action=edit&amp;redlink=1" class="new" title="PILOT (la pagina non esiste)">1154</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1164&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1164 (la pagina non esiste)">1164</a><b>&#160;·</b> <a href="/wiki/Open_Firmware" title="Open Firmware">1275</a><b>&#160;·</b> <a href="/w/index.php?title=Distributed_Interactive_Simulation&amp;action=edit&amp;redlink=1" class="new" title="Distributed Interactive Simulation (la pagina non esiste)">1278</a><b>&#160;·</b> <a href="/wiki/IEEE_1284" title="IEEE 1284">1284</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1355&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1355 (la pagina non esiste)">1355</a><b>&#160;·</b> <a href="/wiki/IEEE_1394" title="IEEE 1394">1394</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1451&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1451 (la pagina non esiste)">1451</a><b>&#160;·</b> <a href="/w/index.php?title=Standard_Delay_Format&amp;action=edit&amp;redlink=1" class="new" title="Standard Delay Format (la pagina non esiste)">1497</a><b>&#160;·</b> <a href="/w/index.php?title=High-level_architecture&amp;action=edit&amp;redlink=1" class="new" title="High-level architecture (la pagina non esiste)">1516</a><b>&#160;·</b> <a href="/wiki/IEEE_1541" title="IEEE 1541">1541</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1547&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1547 (la pagina non esiste)">1547</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1584&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1584 (la pagina non esiste)">1584</a><b>&#160;·</b> <a href="/wiki/Precision_Time_Protocol" title="Precision Time Protocol">1588</a><b>&#160;·</b> <a href="/w/index.php?title=Scalable_Coherent_Interface&amp;action=edit&amp;redlink=1" class="new" title="Scalable Coherent Interface (la pagina non esiste)">1596</a><b>&#160;·</b> <a href="/w/index.php?title=Advanced_Library_Format&amp;action=edit&amp;redlink=1" class="new" title="Advanced Library Format (la pagina non esiste)">1603</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1613&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1613 (la pagina non esiste)">1613</a><b>&#160;·</b> <a href="/wiki/SystemC" title="SystemC">1666</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1667&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1667 (la pagina non esiste)">1667</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1675-2008&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1675-2008 (la pagina non esiste)">1675</a><b>&#160;·</b> <a href="/w/index.php?title=IP-XACT&amp;action=edit&amp;redlink=1" class="new" title="IP-XACT (la pagina non esiste)">1685</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1722&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1722 (la pagina non esiste)">1722</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1733&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1733 (la pagina non esiste)">1733</a><b>&#160;·</b> <a href="/wiki/SystemVerilog" title="SystemVerilog">1800</a><b>&#160;·</b> <a href="/w/index.php?title=Unified_Power_Format&amp;action=edit&amp;redlink=1" class="new" title="Unified Power Format (la pagina non esiste)">1801</a><b>&#160;·</b> <a href="/wiki/DNP3" title="DNP3">1815</a><b>&#160;·</b> <a href="/w/index.php?title=Property_Specification_Language&amp;action=edit&amp;redlink=1" class="new" title="Property Specification Language (la pagina non esiste)">1850</a><b>&#160;·</b> <a href="/w/index.php?title=DySPAN&amp;action=edit&amp;redlink=1" class="new" title="DySPAN (la pagina non esiste)">1900</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1901&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1901 (la pagina non esiste)">1901</a><b>&#160;·</b> <a href="/w/index.php?title=RuBee&amp;action=edit&amp;redlink=1" class="new" title="RuBee (la pagina non esiste)">1902</a><b>&#160;·</b> <a href="/w/index.php?title=Service_Interoperability_in_Ethernet_Passive_Optical_Networks&amp;action=edit&amp;redlink=1" class="new" title="Service Interoperability in Ethernet Passive Optical Networks (la pagina non esiste)">1904</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1905&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1905 (la pagina non esiste)">1905</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_2030&amp;action=edit&amp;redlink=1" class="new" title="IEEE 2030 (la pagina non esiste)">2030</a><b>&#160;·</b> <a href="/w/index.php?title=Micro_T-Kernel&amp;action=edit&amp;redlink=1" class="new" title="Micro T-Kernel (la pagina non esiste)">2050</a><b>&#160;·</b> <a href="/w/index.php?title=ISO/IEEE_11073&amp;action=edit&amp;redlink=1" class="new" title="ISO/IEEE 11073 (la pagina non esiste)">11073</a><b>&#160;·</b> <a href="/wiki/ISO/IEC_12207" title="ISO/IEC 12207">12207</a><b>&#160;·</b> <a href="/w/index.php?title=Software_maintenance&amp;action=edit&amp;redlink=1" class="new" title="Software maintenance (la pagina non esiste)">14764</a><b>&#160;·</b> <a href="/wiki/Risk_management" class="mw-redirect" title="Risk management">16085</a><b>&#160;·</b> <a href="/wiki/Project_management" title="Project management">16326</a><b>&#160;·</b> <a href="/w/index.php?title=Requirements_engineering&amp;action=edit&amp;redlink=1" class="new" title="Requirements engineering (la pagina non esiste)">29148</a><b>&#160;·</b> <a href="/w/index.php?title=ISO/IEC_42010&amp;action=edit&amp;redlink=1" class="new" title="ISO/IEC 42010 (la pagina non esiste)">42010</a></td></tr><tr><th colspan="1" class="navbox_group"><a href="/wiki/IEEE_802" title="IEEE 802">802 series</a></th><td colspan="1" class="navbox_list navbox_even"><table class="subnavbox"><tbody><tr><th class="subnavbox_group"><a href="/wiki/IEEE_802.1" title="IEEE 802.1">802.1</a></th><td colspan="1"><a href="/wiki/IEEE_802.1D" title="IEEE 802.1D">D</a><b>&#160;·</b> <a href="/wiki/IEEE_802.1p" title="IEEE 802.1p">p</a><b>&#160;·</b> <a href="/wiki/IEEE_802.1Q" title="IEEE 802.1Q">Q</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.1Qav&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.1Qav (la pagina non esiste)">Qav</a><b>&#160;·</b> <a href="/w/index.php?title=Stream_Reservation_Protocol&amp;action=edit&amp;redlink=1" class="new" title="Stream Reservation Protocol (la pagina non esiste)">Qat</a><b>&#160;·</b> <a href="/w/index.php?title=Provider_Backbone_Bridge_Traffic_Engineering&amp;action=edit&amp;redlink=1" class="new" title="Provider Backbone Bridge Traffic Engineering (la pagina non esiste)">Qay</a><b>&#160;·</b> <a href="/wiki/Spanning_tree_(networking)" title="Spanning tree (networking)">w</a><b>&#160;·</b> <a href="/wiki/IEEE_802.1x" title="IEEE 802.1x">X</a><b>&#160;·</b> <a href="/w/index.php?title=Link_Layer_Discovery_Protocol&amp;action=edit&amp;redlink=1" class="new" title="Link Layer Discovery Protocol (la pagina non esiste)">ab</a><b>&#160;·</b> <a href="/wiki/IEEE_802.1ad" title="IEEE 802.1ad">ad</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.1AE&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.1AE (la pagina non esiste)">AE</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.1ag&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.1ag (la pagina non esiste)">ag</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.1ah-2008&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.1ah-2008 (la pagina non esiste)">ah</a><b>&#160;·</b> <a href="/wiki/Multiple_Registration_Protocol" title="Multiple Registration Protocol">ak</a><b>&#160;·</b> <a href="/wiki/IEEE_802.1aq" title="IEEE 802.1aq">aq</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.1AS&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.1AS (la pagina non esiste)">AS</a><b>&#160;·</b> <a href="/wiki/Link_aggregation" title="Link aggregation">ax</a><b>&#160;·</b> <a href="/w/index.php?title=Data_center_bridging&amp;action=edit&amp;redlink=1" class="new" title="Data center bridging (la pagina non esiste)">az</a><b>&#160;·</b> <a href="/w/index.php?title=Audio_Video_Bridging&amp;action=edit&amp;redlink=1" class="new" title="Audio Video Bridging (la pagina non esiste)">BA</a></td></tr><tr><th class="subnavbox_group"><a href="/wiki/IEEE_802.3" title="IEEE 802.3">802.3</a></th><td colspan="1"><a href="/w/index.php?title=10BASE5&amp;action=edit&amp;redlink=1" class="new" title="10BASE5 (la pagina non esiste)">-1983</a><b>&#160;·</b> <a href="/w/index.php?title=802.3a&amp;action=edit&amp;redlink=1" class="new" title="802.3a (la pagina non esiste)">a</a><b>&#160;·</b> <a href="/w/index.php?title=802.3b&amp;action=edit&amp;redlink=1" class="new" title="802.3b (la pagina non esiste)">b</a><b>&#160;·</b> <a href="/w/index.php?title=802.3d&amp;action=edit&amp;redlink=1" class="new" title="802.3d (la pagina non esiste)">d</a><b>&#160;·</b> <a href="/w/index.php?title=802.3e&amp;action=edit&amp;redlink=1" class="new" title="802.3e (la pagina non esiste)">e</a><b>&#160;·</b> <a href="/w/index.php?title=802.3i&amp;action=edit&amp;redlink=1" class="new" title="802.3i (la pagina non esiste)">i</a><b>&#160;·</b> <a href="/w/index.php?title=802.3j&amp;action=edit&amp;redlink=1" class="new" title="802.3j (la pagina non esiste)">j</a><b>&#160;·</b> <a href="/w/index.php?title=802.3u&amp;action=edit&amp;redlink=1" class="new" title="802.3u (la pagina non esiste)">u</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.3x&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.3x (la pagina non esiste)">x</a><b>&#160;·</b> <a href="/w/index.php?title=802.3y&amp;action=edit&amp;redlink=1" class="new" title="802.3y (la pagina non esiste)">y</a><b>&#160;·</b> <a href="/w/index.php?title=802.3z&amp;action=edit&amp;redlink=1" class="new" title="802.3z (la pagina non esiste)">z</a><b>&#160;·</b> <a href="/w/index.php?title=802.3ab&amp;action=edit&amp;redlink=1" class="new" title="802.3ab (la pagina non esiste)">ab</a><b>&#160;·</b> <a href="/w/index.php?title=802.3ac&amp;action=edit&amp;redlink=1" class="new" title="802.3ac (la pagina non esiste)">ac</a><b>&#160;·</b> <a href="/wiki/Link_aggregation" title="Link aggregation">ad</a><b>&#160;·</b> <a href="/w/index.php?title=802.3ae&amp;action=edit&amp;redlink=1" class="new" title="802.3ae (la pagina non esiste)">ae</a><b>&#160;·</b> <a href="/wiki/Power_over_Ethernet" title="Power over Ethernet">af</a><b>&#160;·</b> <a href="/w/index.php?title=802.3ah&amp;action=edit&amp;redlink=1" class="new" title="802.3ah (la pagina non esiste)">ah</a><b>&#160;·</b> <a href="/w/index.php?title=802.3ak&amp;action=edit&amp;redlink=1" class="new" title="802.3ak (la pagina non esiste)">ak</a><b>&#160;·</b> <a href="/w/index.php?title=802.3an&amp;action=edit&amp;redlink=1" class="new" title="802.3an (la pagina non esiste)">an</a><b>&#160;·</b> <a href="/w/index.php?title=802.3aq&amp;action=edit&amp;redlink=1" class="new" title="802.3aq (la pagina non esiste)">aq</a><b>&#160;·</b> <a href="/wiki/Power_over_Ethernet" title="Power over Ethernet">at</a><b>&#160;·</b> <a href="/w/index.php?title=802.3av&amp;action=edit&amp;redlink=1" class="new" title="802.3av (la pagina non esiste)">av</a><b>&#160;·</b> <a href="/w/index.php?title=802.3az&amp;action=edit&amp;redlink=1" class="new" title="802.3az (la pagina non esiste)">az</a><b>&#160;·</b> <a href="/wiki/IEEE_802.3ba" title="IEEE 802.3ba">ba</a><b>&#160;·</b> <a href="/w/index.php?title=802.3bt&amp;action=edit&amp;redlink=1" class="new" title="802.3bt (la pagina non esiste)">bt</a><b>&#160;·</b> <a href="/w/index.php?title=802.3by&amp;action=edit&amp;redlink=1" class="new" title="802.3by (la pagina non esiste)">by</a><b>&#160;·</b> <a href="/w/index.php?title=802.3bz&amp;action=edit&amp;redlink=1" class="new" title="802.3bz (la pagina non esiste)">bz</a><b>&#160;·</b> <a href="/w/index.php?title=802.3cg&amp;action=edit&amp;redlink=1" class="new" title="802.3cg (la pagina non esiste)">cg</a></td></tr><tr><th class="subnavbox_group"><a href="/wiki/IEEE_802.11" title="IEEE 802.11">802.11</a></th><td colspan="1"><a href="/w/index.php?title=IEEE_802.11_(legacy_mode)&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11 (legacy mode) (la pagina non esiste)">legacy mode</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11a-1999&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11a-1999 (la pagina non esiste)">a</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11b-1999&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11b-1999 (la pagina non esiste)">b</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11c&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11c (la pagina non esiste)">c</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11d-2001&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11d-2001 (la pagina non esiste)">d</a><b>&#160;·</b> <a href="/wiki/IEEE_802.11e" title="IEEE 802.11e">e</a><b>&#160;·</b> <a href="/w/index.php?title=Inter-Access_Point_Protocol&amp;action=edit&amp;redlink=1" class="new" title="Inter-Access Point Protocol (la pagina non esiste)">f</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11g-2003&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11g-2003 (la pagina non esiste)">g</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11h-2003&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11h-2003 (la pagina non esiste)">h</a><b>&#160;·</b> <a href="/wiki/IEEE_802.11i" title="IEEE 802.11i">i</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11j-2004&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11j-2004 (la pagina non esiste)">j</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11k-2008&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11k-2008 (la pagina non esiste)">k</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11n-2009&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11n-2009 (la pagina non esiste)">n</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11p&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11p (la pagina non esiste)">p</a><b>&#160;·</b> <a href="/wiki/IEEE_802.11r" title="IEEE 802.11r">r</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11s&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11s (la pagina non esiste)">s</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11u&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11u (la pagina non esiste)">u</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11v&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11v (la pagina non esiste)">v</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11w-2009&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11w-2009 (la pagina non esiste)">w</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11y-2008&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11y-2008 (la pagina non esiste)">y</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11ac&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11ac (la pagina non esiste)">ac</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11ad&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11ad (la pagina non esiste)">ad</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11af&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11af (la pagina non esiste)">af</a><b>&#160;·</b> <a href="/wiki/IEEE_802.11ah" title="IEEE 802.11ah">ah</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11ai&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11ai (la pagina non esiste)">ai</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11ax&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11ax (la pagina non esiste)">ax</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11ay&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11ay (la pagina non esiste)">ay</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.11be&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.11be (la pagina non esiste)">be</a></td></tr></tbody></table> <a href="/wiki/IEEE_802.2" title="IEEE 802.2">.2</a><b>&#160;·</b> <a href="/wiki/Token_bus" title="Token bus">.4</a><b>&#160;·</b> <a href="/wiki/Token_ring" title="Token ring">.5</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.6&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.6 (la pagina non esiste)">.6</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.7&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.7 (la pagina non esiste)">.7</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.8&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.8 (la pagina non esiste)">.8</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.9&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.9 (la pagina non esiste)">.9</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.10&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.10 (la pagina non esiste)">.10</a><b>&#160;·</b> <a href="/w/index.php?title=100BaseVG&amp;action=edit&amp;redlink=1" class="new" title="100BaseVG (la pagina non esiste)">.12</a><b>&#160;·</b> <a href="/w/index.php?title=Cable_modem&amp;action=edit&amp;redlink=1" class="new" title="Cable modem (la pagina non esiste)">.14</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.15&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.15 (la pagina non esiste)">.15</a> (<a href="/wiki/Bluetooth" title="Bluetooth">.1</a><b>&#160;·</b> <a href="/wiki/IEEE_802.15.4" title="IEEE 802.15.4">.4</a><b>&#160;·</b> <a href="/wiki/IEEE_802.15.4a" class="mw-redirect" title="IEEE 802.15.4a">.4a</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.15.6&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.15.6 (la pagina non esiste)">.6</a>)<b>&#160;·</b> <a href="/wiki/IEEE_802.16" class="mw-redirect" title="IEEE 802.16">.16</a> (<a href="/wiki/WiMAX" title="WiMAX">Original · d · e</a>)<b>&#160;·</b> <a href="/w/index.php?title=Resilient_Packet_Ring&amp;action=edit&amp;redlink=1" class="new" title="Resilient Packet Ring (la pagina non esiste)">.17</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.18&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.18 (la pagina non esiste)">.18</a><b>&#160;·</b> <a href="/wiki/IEEE_802.20" title="IEEE 802.20">.20</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_802.21&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.21 (la pagina non esiste)">.21</a><b>&#160;·</b> *<a href="/w/index.php?title=IEEE_802.22&amp;action=edit&amp;redlink=1" class="new" title="IEEE 802.22 (la pagina non esiste)">.22</a></td></tr><tr><th colspan="1" class="navbox_group">Proposte</th><td colspan="1" class="navbox_list navbox_odd"><a href="/w/index.php?title=IEEE_P1363&amp;action=edit&amp;redlink=1" class="new" title="IEEE P1363 (la pagina non esiste)">P1363</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_P1619&amp;action=edit&amp;redlink=1" class="new" title="IEEE P1619 (la pagina non esiste)">P1619</a><b>&#160;·</b> <a href="/w/index.php?title=Rosetta-lang&amp;action=edit&amp;redlink=1" class="new" title="Rosetta-lang (la pagina non esiste)">P1699</a><b>&#160;·</b> <a href="/w/index.php?title=Universal_Power_Adapter_for_Mobile_Devices&amp;action=edit&amp;redlink=1" class="new" title="Universal Power Adapter for Mobile Devices (la pagina non esiste)">P1823</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_P1906.1&amp;action=edit&amp;redlink=1" class="new" title="IEEE P1906.1 (la pagina non esiste)">P1906.1</a></td></tr><tr><th colspan="1" class="navbox_group">Sostituite</th><td colspan="1" class="navbox_list navbox_even"><a href="/w/index.php?title=IEEE_754-1985&amp;action=edit&amp;redlink=1" class="new" title="IEEE 754-1985 (la pagina non esiste)">754-1985</a><b>&#160;·</b> <a href="/w/index.php?title=Software_requirements_specification&amp;action=edit&amp;redlink=1" class="new" title="Software requirements specification (la pagina non esiste)">830</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1219&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1219 (la pagina non esiste)">1219</a><b>&#160;·</b> <a href="/w/index.php?title=Software_requirements_specification&amp;action=edit&amp;redlink=1" class="new" title="Software requirements specification (la pagina non esiste)">1233</a><b>&#160;·</b> <a href="/w/index.php?title=Concept_of_operations&amp;action=edit&amp;redlink=1" class="new" title="Concept of operations (la pagina non esiste)">1362</a><b>&#160;·</b> <a href="/wiki/Verilog" title="Verilog">1364</a><b>&#160;·</b> <a href="/w/index.php?title=IEEE_1471&amp;action=edit&amp;redlink=1" class="new" title="IEEE 1471 (la pagina non esiste)">1471</a></td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r141815314"><table class="navbox mw-collapsible mw-collapsed noprint metadata" id="navbox-Logica_programmabile"><tbody><tr><th colspan="2"><div class="navbox_navbar"><div class="noprint plainlinks" style="background-color:transparent; padding:0; font-size:xx-small; color:var(--color-base, #000000); white-space:nowrap;"><a href="/wiki/Template:Logica_programmabile" title="Template:Logica programmabile"><span title="Vai alla pagina del template">V</span></a>&#160;·&#160;<a href="/w/index.php?title=Discussioni_template:Logica_programmabile&amp;action=edit&amp;redlink=1" class="new" title="Discussioni template:Logica programmabile (la pagina non esiste)"><span title="Discuti del template">D</span></a>&#160;·&#160;<a class="external text" href="https://it.wikipedia.org/w/index.php?title=Template:Logica_programmabile&amp;action=edit"><span title="Modifica il template. Usa l&#39;anteprima prima di salvare">M</span></a></div></div><span class="navbox_title"><a href="/wiki/Controllore_logico_programmabile" title="Controllore logico programmabile">Logica programmabile</a></span></th></tr><tr><th colspan="1" class="navbox_group">Concetti</th><td colspan="1" class="navbox_list navbox_odd"><a href="/wiki/ASIC" class="mw-redirect" title="ASIC">ASIC</a><b>&#160;·</b> <a href="/wiki/System-on-a-chip" title="System-on-a-chip">SoC</a><b>&#160;·</b> <a href="/wiki/Field_Programmable_Gate_Array" title="Field Programmable Gate Array">FPGA</a> (<a href="/w/index.php?title=Configurable_Logic_Block&amp;action=edit&amp;redlink=1" class="new" title="Configurable Logic Block (la pagina non esiste)">CLB</a>)<b>&#160;·</b> <a href="/wiki/Complex_Programmable_Logic_Device" title="Complex Programmable Logic Device">CPLD</a><b>&#160;·</b> <a href="/w/index.php?title=Erasable_Programmable_Logic_Device&amp;action=edit&amp;redlink=1" class="new" title="Erasable Programmable Logic Device (la pagina non esiste)">EPLD</a><b>&#160;·</b> <a href="/wiki/Programmable_Logic_Array" title="Programmable Logic Array">PLA</a><b>&#160;·</b> <a href="/wiki/Programmable_Array_Logic" class="mw-redirect" title="Programmable Array Logic">PAL</a><b>&#160;·</b> <a href="/wiki/Generic_Array_Logic" title="Generic Array Logic">GAL</a><b>&#160;·</b> <a href="/wiki/PSoC" title="PSoC">PSoC</a><b>&#160;·</b> <a href="/w/index.php?title=Reconfigurable_Computing&amp;action=edit&amp;redlink=1" class="new" title="Reconfigurable Computing (la pagina non esiste)">Reconfigurable Computing</a> (<a href="/w/index.php?title=Xputer&amp;action=edit&amp;redlink=1" class="new" title="Xputer (la pagina non esiste)">Xputer</a>)<b>&#160;·</b> <a href="/w/index.php?title=Soft_microprocessor&amp;action=edit&amp;redlink=1" class="new" title="Soft microprocessor (la pagina non esiste)">Soft microprocessor</a><b>&#160;·</b> <a href="/w/index.php?title=Circuit_underutilization&amp;action=edit&amp;redlink=1" class="new" title="Circuit underutilization (la pagina non esiste)">Circuit underutilization</a><b>&#160;·</b> <a href="/w/index.php?title=High-level_synthesis&amp;action=edit&amp;redlink=1" class="new" title="High-level synthesis (la pagina non esiste)">High-level synthesis</a><b>&#160;·</b> <a href="/wiki/Acceleratore_(informatica)" title="Acceleratore (informatica)">Acceleratore</a></td></tr><tr><th colspan="1" class="navbox_group">Tecniche di programmazione</th><td colspan="1" class="navbox_list navbox_even"><a href="/wiki/Gate_array" title="Gate array">Gate array</a><b>&#160;·</b> <a href="/wiki/Antifusibile" title="Antifusibile">Antifusibile</a><b>&#160;·</b> <a href="/wiki/Erasable_Programmable_Read_Only_Memory" class="mw-redirect" title="Erasable Programmable Read Only Memory">EPROM</a><b>&#160;·</b> <a href="/wiki/Electrically_Erasable_Programmable_Read-Only_Memory" class="mw-redirect" title="Electrically Erasable Programmable Read-Only Memory">E²PROM</a><b>&#160;·</b> <a href="/wiki/Memoria_Flash" class="mw-redirect" title="Memoria Flash">Flash</a><b>&#160;·</b> <a href="/wiki/Static_Random_Access_Memory" class="mw-redirect" title="Static Random Access Memory">SRAM</a></td></tr><tr><th colspan="1" class="navbox_group">Linguaggi</th><td colspan="1" class="navbox_list navbox_odd"><a href="/wiki/Verilog" title="Verilog">Verilog</a> (<a href="/w/index.php?title=Verilog-A&amp;action=edit&amp;redlink=1" class="new" title="Verilog-A (la pagina non esiste)">A</a>, <a href="/w/index.php?title=Verilog-AMS&amp;action=edit&amp;redlink=1" class="new" title="Verilog-AMS (la pagina non esiste)">AMS</a>)<b>&#160;·</b> <a class="mw-selflink selflink">VHDL</a> (<a href="/w/index.php?title=VHDL-AMS&amp;action=edit&amp;redlink=1" class="new" title="VHDL-AMS (la pagina non esiste)">AMS</a>, <a href="/w/index.php?title=VHDL-VITAL&amp;action=edit&amp;redlink=1" class="new" title="VHDL-VITAL (la pagina non esiste)">VITAL</a>)<b>&#160;·</b> <a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a> (<a href="/w/index.php?title=SystemVerilog_DPI&amp;action=edit&amp;redlink=1" class="new" title="SystemVerilog DPI (la pagina non esiste)">DPI</a>)<b>&#160;·</b> <a href="/wiki/SystemC" title="SystemC">SystemC</a><b>&#160;·</b> <a href="/w/index.php?title=Altera_Hardware_Description_Language&amp;action=edit&amp;redlink=1" class="new" title="Altera Hardware Description Language (la pagina non esiste)">AHDL</a><b>&#160;·</b> <a href="/wiki/Handel-C" title="Handel-C">Handel-C</a><b>&#160;·</b> <a href="/w/index.php?title=Property_Specification_Language&amp;action=edit&amp;redlink=1" class="new" title="Property Specification Language (la pagina non esiste)">PSL</a><b>&#160;·</b> <a href="/w/index.php?title=Unified_Power_Format&amp;action=edit&amp;redlink=1" class="new" title="Unified Power Format (la pagina non esiste)">UPF</a><b>&#160;·</b> <a href="/w/index.php?title=PALASM&amp;action=edit&amp;redlink=1" class="new" title="PALASM (la pagina non esiste)">PALASM</a><b>&#160;·</b> <a href="/w/index.php?title=Advanced_Boolean_Expression_Language&amp;action=edit&amp;redlink=1" class="new" title="Advanced Boolean Expression Language (la pagina non esiste)">ABEL</a><b>&#160;·</b> <a href="/w/index.php?title=Cornell_University_Programming_Language&amp;action=edit&amp;redlink=1" class="new" title="Cornell University Programming Language (la pagina non esiste)">CUPL</a><b>&#160;·</b> <a href="/w/index.php?title=OpenVera&amp;action=edit&amp;redlink=1" class="new" title="OpenVera (la pagina non esiste)">OpenVera</a><b>&#160;·</b> <a href="/w/index.php?title=C_to_HDL&amp;action=edit&amp;redlink=1" class="new" title="C to HDL (la pagina non esiste)">C to HDL</a><b>&#160;·</b> <a href="/w/index.php?title=Flow_to_HDL&amp;action=edit&amp;redlink=1" class="new" title="Flow to HDL (la pagina non esiste)">Flow to HDL</a><b>&#160;·</b> <a href="/wiki/MyHDL" title="MyHDL">MyHDL</a><b>&#160;·</b> <a href="/w/index.php?title=ELLA_(programming_language)&amp;action=edit&amp;redlink=1" class="new" title="ELLA (programming language) (la pagina non esiste)">ELLA</a><b>&#160;·</b> <a href="/wiki/Chisel" title="Chisel">Chisel</a></td></tr><tr><th colspan="1" class="navbox_group">Costruttori</th><td colspan="1" class="navbox_list navbox_even"><a href="/w/index.php?title=Accellera&amp;action=edit&amp;redlink=1" class="new" title="Accellera (la pagina non esiste)">Accellera</a><b>&#160;·</b> <a href="/w/index.php?title=Achronix&amp;action=edit&amp;redlink=1" class="new" title="Achronix (la pagina non esiste)">Achronix</a><b>&#160;·</b> <a href="/wiki/AMD" class="mw-redirect" title="AMD">AMD</a> (<a href="/wiki/Xilinx" title="Xilinx">Xilinx</a>)<b>&#160;·</b> <a href="/w/index.php?title=Aldec&amp;action=edit&amp;redlink=1" class="new" title="Aldec (la pagina non esiste)">Aldec</a><b>&#160;·</b> <a href="/wiki/ARM_Holdings" title="ARM Holdings">Arm</a><b>&#160;·</b> <a href="/w/index.php?title=Cadence_Design_Systems&amp;action=edit&amp;redlink=1" class="new" title="Cadence Design Systems (la pagina non esiste)">Cadence</a><b>&#160;·</b> <a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a><b>&#160;·</b> <a href="/wiki/Intel" title="Intel">Intel</a><b>&#160;·</b> <a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a><b>&#160;·</b> <a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a><b>&#160;·</b> <a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a><b>&#160;·</b> <a href="/wiki/Siemens_(azienda)" title="Siemens (azienda)">Siemens</a> (<a href="/wiki/Mentor_Graphics" title="Mentor Graphics">Mentor Graphics</a>)<b>&#160;·</b> <a href="/w/index.php?title=Synopsys&amp;action=edit&amp;redlink=1" class="new" title="Synopsys (la pagina non esiste)">Synopsys</a><b>&#160;·</b> <a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a></td></tr><tr><th colspan="1" class="navbox_group">Prodotti</th><td colspan="1" class="navbox_list navbox_odd"><table class="subnavbox"><tbody><tr><th class="subnavbox_group">Hardware</th><td colspan="1"><a href="/w/index.php?title=ICE_(FPGA)&amp;action=edit&amp;redlink=1" class="new" title="ICE (FPGA) (la pagina non esiste)">iCE</a><b>&#160;·</b> <a href="/w/index.php?title=Stratix&amp;action=edit&amp;redlink=1" class="new" title="Stratix (la pagina non esiste)">Stratix</a><b>&#160;·</b> <a href="/w/index.php?title=Virtex_(FPGA)&amp;action=edit&amp;redlink=1" class="new" title="Virtex (FPGA) (la pagina non esiste)">Virtex</a></td></tr><tr><th class="subnavbox_group">Software</th><td colspan="1"><a href="/w/index.php?title=Intel_Quartus_Prime&amp;action=edit&amp;redlink=1" class="new" title="Intel Quartus Prime (la pagina non esiste)">Intel Quartus Prime</a><b>&#160;·</b> <a href="/w/index.php?title=Xilinx_ISE&amp;action=edit&amp;redlink=1" class="new" title="Xilinx ISE (la pagina non esiste)">Xilinx ISE</a><b>&#160;·</b> <a href="/w/index.php?title=Xilinx_Vivado&amp;action=edit&amp;redlink=1" class="new" title="Xilinx Vivado (la pagina non esiste)">Xilinx Vivado</a><b>&#160;·</b> <a href="/w/index.php?title=ModelSim&amp;action=edit&amp;redlink=1" class="new" title="ModelSim (la pagina non esiste)">ModelSim</a><b>&#160;·</b> <a href="/w/index.php?title=Verilog-to-Routing&amp;action=edit&amp;redlink=1" class="new" title="Verilog-to-Routing (la pagina non esiste)">VTR</a></td></tr><tr><th class="subnavbox_group">IP</th><td colspan="1"><table class="subnavbox"><tbody><tr><th class="subnavbox_group">Proprietario</th><td colspan="1"><a href="/w/index.php?title=Argonaut_RISC_Core&amp;action=edit&amp;redlink=1" class="new" title="Argonaut RISC Core (la pagina non esiste)">ARC</a><b>&#160;·</b> <a href="/w/index.php?title=ARM_Cortex-M&amp;action=edit&amp;redlink=1" class="new" title="ARM Cortex-M (la pagina non esiste)">ARM Cortex-M</a><b>&#160;·</b> <a href="/wiki/LEON" title="LEON">LEON</a><b>&#160;·</b> <a href="/w/index.php?title=LatticeMico8&amp;action=edit&amp;redlink=1" class="new" title="LatticeMico8 (la pagina non esiste)">LatticeMico8</a><b>&#160;·</b> <a href="/w/index.php?title=MicroBlaze&amp;action=edit&amp;redlink=1" class="new" title="MicroBlaze (la pagina non esiste)">MicroBlaze</a><b>&#160;·</b> <a href="/w/index.php?title=PicoBlaze&amp;action=edit&amp;redlink=1" class="new" title="PicoBlaze (la pagina non esiste)">PicoBlaze</a><b>&#160;·</b> <a href="/w/index.php?title=Altera_Nios&amp;action=edit&amp;redlink=1" class="new" title="Altera Nios (la pagina non esiste)">Nios</a><b>&#160;·</b> <a href="/w/index.php?title=Nios_II&amp;action=edit&amp;redlink=1" class="new" title="Nios II (la pagina non esiste)">Nios II</a></td></tr><tr><th class="subnavbox_group">Open-Source</th><td colspan="1"><a href="/w/index.php?title=Java_Optimized_Processor&amp;action=edit&amp;redlink=1" class="new" title="Java Optimized Processor (la pagina non esiste)">JOP</a><b>&#160;·</b> <a href="/w/index.php?title=LatticeMico32&amp;action=edit&amp;redlink=1" class="new" title="LatticeMico32 (la pagina non esiste)">LatticeMico32</a><b>&#160;·</b> <a href="/wiki/OpenCores" title="OpenCores">OpenCores</a><b>&#160;·</b> <a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a><b>&#160;·</b> <a href="/w/index.php?title=Power_ISA&amp;action=edit&amp;redlink=1" class="new" title="Power ISA (la pagina non esiste)">Power ISA</a> (<a href="/w/index.php?title=Libre-SOC&amp;action=edit&amp;redlink=1" class="new" title="Libre-SOC (la pagina non esiste)">Libre-SOC</a>, <a href="/w/index.php?title=OpenPOWER_Microwatt&amp;action=edit&amp;redlink=1" class="new" title="OpenPOWER Microwatt (la pagina non esiste)">Microwatt</a>)<b>&#160;·</b> <a href="/wiki/RISC-V" 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