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verification</title> <meta name="description" content="Search results for: run-time verification"> <meta name="keywords" content="run-time verification"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> <button class="d-block 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action="https://publications.waset.org/abstracts/search"> <div id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="run-time verification"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 593</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: run-time verification</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">593</span> Novel Formal Verification Based Coverage Augmentation Technique</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Surinder%20Sood">Surinder Sood</a>, <a href="https://publications.waset.org/abstracts/search?q=Debajyoti%20Mukherjee"> Debajyoti Mukherjee</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Formal verification techniques have become widely popular in pre-silicon verification as an alternate to constrain random simulation based techniques. This paper proposed a novel formal verification-based coverage augmentation technique in verifying complex RTL functional verification faster. The proposed approach relies on augmenting coverage analysis coming from simulation and formal verification. Besides this, the functional qualification framework not only helps in improving the coverage at a faster pace but also aids in maturing and qualifying the formal verification infrastructure. The proposed technique has helped to achieve faster verification sign-off, resulting in faster time-to-market. The design picked had a complex control and data path and had many configurable options to meet multiple specification needs. The flow is generic, and tool independent, thereby leveraging across the projects and design will be much easier <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=COI%20%28cone%20of%20influence%29" title="COI (cone of influence)">COI (cone of influence)</a>, <a href="https://publications.waset.org/abstracts/search?q=coverage" title=" coverage"> coverage</a>, <a href="https://publications.waset.org/abstracts/search?q=formal%20verification" title=" formal verification"> formal verification</a>, <a href="https://publications.waset.org/abstracts/search?q=fault%20injection" title=" fault injection"> fault injection</a> </p> <a href="https://publications.waset.org/abstracts/159250/novel-formal-verification-based-coverage-augmentation-technique" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/159250.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">124</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">592</span> Implementation of a Baseline RISC for the Realization of a Dynamically Reconfigurable Processor</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hajer%20Najjar">Hajer Najjar</a>, <a href="https://publications.waset.org/abstracts/search?q=Riad%20Bourguiba"> Riad Bourguiba</a>, <a href="https://publications.waset.org/abstracts/search?q=Jaouhar%20Mouine"> Jaouhar Mouine</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Reduced instruction set computer (RISC) processors are widely used because of their multiple advantages. In fact, they are based on a simple instruction set so that they increase the speed of the processor and reduce its energy consumption. In this paper, we will present a basic RISC architecture processor that will be developed later to converge to a new architecture with runtime reconfiguration. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=processor" title="processor">processor</a>, <a href="https://publications.waset.org/abstracts/search?q=RISC" title=" RISC"> RISC</a>, <a href="https://publications.waset.org/abstracts/search?q=DLX" title=" DLX"> DLX</a>, <a href="https://publications.waset.org/abstracts/search?q=pipeline" title=" pipeline"> pipeline</a>, <a href="https://publications.waset.org/abstracts/search?q=runtime%20reconfiguration" title=" runtime reconfiguration"> runtime reconfiguration</a> </p> <a href="https://publications.waset.org/abstracts/16176/implementation-of-a-baseline-risc-for-the-realization-of-a-dynamically-reconfigurable-processor" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/16176.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">405</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">591</span> Effect of Clinical Depression on Automatic Speaker Verification</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Sheeraz%20Memon">Sheeraz Memon</a>, <a href="https://publications.waset.org/abstracts/search?q=Namunu%20C.%20Maddage"> Namunu C. Maddage</a>, <a href="https://publications.waset.org/abstracts/search?q=Margaret%20Lech"> Margaret Lech</a>, <a href="https://publications.waset.org/abstracts/search?q=Nicholas%20Allen"> Nicholas Allen</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The effect of a clinical environment on the accuracy of the speaker verification was tested. The speaker verification tests were performed within homogeneous environments containing clinically depressed speakers only, and non-depresses speakers only, as well as within mixed environments containing different mixtures of both climatically depressed and non-depressed speakers. The speaker verification framework included the MFCCs features and the GMM modeling and classification method. The speaker verification experiments within homogeneous environments showed 5.1% increase of the EER within the clinically depressed environment when compared to the non-depressed environment. It indicated that the clinical depression increases the intra-speaker variability and makes the speaker verification task more challenging. Experiments with mixed environments indicated that the increase of the percentage of the depressed individuals within a mixed environment increases the speaker verification equal error rates. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=speaker%20verification" title="speaker verification">speaker verification</a>, <a href="https://publications.waset.org/abstracts/search?q=GMM" title=" GMM"> GMM</a>, <a href="https://publications.waset.org/abstracts/search?q=EM" title=" EM"> EM</a>, <a href="https://publications.waset.org/abstracts/search?q=clinical%20environment" title=" clinical environment"> clinical environment</a>, <a href="https://publications.waset.org/abstracts/search?q=clinical%20depression" title=" clinical depression"> clinical depression</a> </p> <a href="https://publications.waset.org/abstracts/39436/effect-of-clinical-depression-on-automatic-speaker-verification" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/39436.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">375</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">590</span> Runtime Monitoring Using Policy-Based Approach to Control Information Flow for Mobile Apps</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mohamed%20Sarrab">Mohamed Sarrab</a>, <a href="https://publications.waset.org/abstracts/search?q=Hadj%20Bourdoucen"> Hadj Bourdoucen</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Mobile applications are verified to check the correctness or evaluated to check the performance with respect to specific security properties such as availability, integrity, and confidentiality. Where they are made available to the end users of the mobile application is achievable only to a limited degree using software engineering static verification techniques. The more sensitive the information, such as credit card data, personal medical information or personal emails being processed by mobile application, the more important it is to ensure the confidentiality of this information. Monitoring non-trusted mobile application during execution in an environment where sensitive information is present is difficult and unnerving. The paper addresses the issue of monitoring and controlling the flow of confidential information during non-trusted mobile application execution. The approach concentrates on providing a dynamic and usable information security solution by interacting with the mobile users during the run-time of mobile application in response to information flow events. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=mobile%20application" title="mobile application">mobile application</a>, <a href="https://publications.waset.org/abstracts/search?q=run-time%20verification" title=" run-time verification"> run-time verification</a>, <a href="https://publications.waset.org/abstracts/search?q=usable%20security" title=" usable security"> usable security</a>, <a href="https://publications.waset.org/abstracts/search?q=direct%20information%20flow" title=" direct information flow"> direct information flow</a> </p> <a href="https://publications.waset.org/abstracts/2363/runtime-monitoring-using-policy-based-approach-to-control-information-flow-for-mobile-apps" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/2363.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">381</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">589</span> Formal Verification of Cache System Using a Novel Cache Memory Model</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Guowei%20Hou">Guowei Hou</a>, <a href="https://publications.waset.org/abstracts/search?q=Lixin%20Yu"> Lixin Yu</a>, <a href="https://publications.waset.org/abstracts/search?q=Wei%20Zhuang"> Wei Zhuang</a>, <a href="https://publications.waset.org/abstracts/search?q=Hui%20Qin"> Hui Qin</a>, <a href="https://publications.waset.org/abstracts/search?q=Xue%20Yang"> Xue Yang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Formal verification is proposed to ensure the correctness of the design and make functional verification more efficient. As cache plays a vital role in the design of System on Chip (SoC), and cache with Memory Management Unit (MMU) and cache memory unit makes the state space too large for simulation to verify, then a formal verification is presented for such system design. In the paper, a formal model checking verification flow is suggested and a new cache memory model which is called “exhaustive search model” is proposed. Instead of using large size ram to denote the whole cache memory, exhaustive search model employs just two cache blocks. For cache system contains data cache (Dcache) and instruction cache (Icache), Dcache memory model and Icache memory model are established separately using the same mechanism. At last, the novel model is employed to the verification of a cache which is module of a custom-built SoC system that has been applied in practical, and the result shows that the cache system is verified correctly using the exhaustive search model, and it makes the verification much more manageable and flexible. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cache%20system" title="cache system">cache system</a>, <a href="https://publications.waset.org/abstracts/search?q=formal%20verification" title=" formal verification"> formal verification</a>, <a href="https://publications.waset.org/abstracts/search?q=novel%20model" title=" novel model"> novel model</a>, <a href="https://publications.waset.org/abstracts/search?q=system%20on%20chip%20%28SoC%29" title=" system on chip (SoC)"> system on chip (SoC)</a> </p> <a href="https://publications.waset.org/abstracts/26581/formal-verification-of-cache-system-using-a-novel-cache-memory-model" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/26581.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">496</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">588</span> Functional and Stimuli Implementation and Verification of Programmable Peripheral Interface (PPI) Protocol</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=N.%20N.%20Joshi">N. N. Joshi</a>, <a href="https://publications.waset.org/abstracts/search?q=G.%20K.%20Singh"> G. K. Singh</a> </p> <p class="card-text"><strong>Abstract:</strong></p> We present the stimuli implementation and verification of a Programmable Peripheral Interface (PPI) 8255. It involves a designing and verification of configurable intellectual property (IP) module of PPI protocol using Verilog HDL for implementation part and System Verilog for verification. The overview of the PPI-8255 presented then the design specification implemented for the work following the functional description and pin configuration of PPI-8255. The coverage report of design shows that our design and verification environment covered 100% functionality in accordance with the design specification generated by the Questa Sim 10.0b. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Programmable%20Peripheral%20Interface%20%28PPI%29" title="Programmable Peripheral Interface (PPI)">Programmable Peripheral Interface (PPI)</a>, <a href="https://publications.waset.org/abstracts/search?q=verilog%20HDL" title=" verilog HDL"> verilog HDL</a>, <a href="https://publications.waset.org/abstracts/search?q=system%20verilog" title=" system verilog"> system verilog</a>, <a href="https://publications.waset.org/abstracts/search?q=questa%20sim" title=" questa sim "> questa sim </a> </p> <a href="https://publications.waset.org/abstracts/21194/functional-and-stimuli-implementation-and-verification-of-programmable-peripheral-interface-ppi-protocol" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/21194.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">522</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">587</span> Embedded Hw-Sw Reconfigurable Techniques For Wireless Sensor Network Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=B.%20Kirubakaran">B. Kirubakaran</a>, <a href="https://publications.waset.org/abstracts/search?q=C.%20Rajasekaran"> C. Rajasekaran </a> </p> <p class="card-text"><strong>Abstract:</strong></p> Reconfigurable techniques are used in many engineering and industrial applications for the efficient data transmissions through the wireless sensor networks. Nowadays most of the industrial applications are work for try to minimize the size and cost. During runtime the reconfigurable technique avoid the unwanted hang and delay in the system performance. In recent world Field Programmable Gate Array (FPGA) as one of the most efficient reconfigurable device and widely used for most of the hardware and software reconfiguration applications. In this paper, the work deals with whatever going to make changes in the hardware and software during runtime it’s should not affect the current running process that’s the main objective of the paper our changes be done in a parallel manner at the same time concentrating the cost and power transmission problems during data trans-receiving. Analog sensor (Temperature) as an input for the controller (PIC) through that control the FPGA digital sensors in generalized manner. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=field%20programmable%20gate%20array" title="field programmable gate array">field programmable gate array</a>, <a href="https://publications.waset.org/abstracts/search?q=peripheral%20interrupt%20controller" title=" peripheral interrupt controller"> peripheral interrupt controller</a>, <a href="https://publications.waset.org/abstracts/search?q=runtime%20reconfigurable%20techniques" title=" runtime reconfigurable techniques"> runtime reconfigurable techniques</a>, <a href="https://publications.waset.org/abstracts/search?q=wireless%20sensor%20networks" title=" wireless sensor networks"> wireless sensor networks</a> </p> <a href="https://publications.waset.org/abstracts/5897/embedded-hw-sw-reconfigurable-techniques-for-wireless-sensor-network-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/5897.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">407</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">586</span> Signature Verification System for a Banking Business Process Management</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=A.%20Rahaf">A. Rahaf</a>, <a href="https://publications.waset.org/abstracts/search?q=S.%20Liyakathunsia"> S. Liyakathunsia</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In today’s world, unprecedented operational pressure is faced by banks that test the efficiency, effectiveness, and agility of their business processes. In a typical banking process, a person’s authorization is usually based on his signature on most all of the transactions. Signature verification is considered as one of the highly significant information needed for any bank document processing. Banks usually use Signature Verification to authenticate the identity of individuals. In this paper, a business process model has been proposed in order to increase the quality of the verification process and to reduce time and needed resources. In order to understand the current process, a survey has been conducted and distributed among bank employees. After analyzing the survey, a process model has been created using Bizagi modeler which helps in simulating the process after assigning time and cost of it. The outcomes show that the automation of signature verification process is highly recommended for a banking business process. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=business%20process%20management" title="business process management">business process management</a>, <a href="https://publications.waset.org/abstracts/search?q=process%20modeling" title=" process modeling"> process modeling</a>, <a href="https://publications.waset.org/abstracts/search?q=quality" title=" quality"> quality</a>, <a href="https://publications.waset.org/abstracts/search?q=Signature%20Verification" title=" Signature Verification"> Signature Verification</a> </p> <a href="https://publications.waset.org/abstracts/67664/signature-verification-system-for-a-banking-business-process-management" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/67664.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">425</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">585</span> An Encapsulation of a Navigable Tree Position: Theory, Specification, and Verification</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nicodemus%20M.%20J.%20Mbwambo">Nicodemus M. J. Mbwambo</a>, <a href="https://publications.waset.org/abstracts/search?q=Yu-Shan%20Sun"> Yu-Shan Sun</a>, <a href="https://publications.waset.org/abstracts/search?q=Murali%20Sitaraman"> Murali Sitaraman</a>, <a href="https://publications.waset.org/abstracts/search?q=Joan%20Krone"> Joan Krone</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a generic data abstraction that captures a navigable tree position. The mathematical modeling of the abstraction encapsulates the current tree position, which can be used to navigate and modify the tree. The encapsulation of the tree position in the data abstraction specification avoids the use of explicit references and aliasing, thereby simplifying verification of (imperative) client code that uses the data abstraction. To ease the tasks of such specification and verification, a general tree theory, rich with mathematical notations and results, has been developed. The paper contains an example to illustrate automated verification ramifications. With sufficient tree theory development, automated proving seems plausible even in the absence of a special-purpose tree solver. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=automation" title="automation">automation</a>, <a href="https://publications.waset.org/abstracts/search?q=data%20abstraction" title=" data abstraction"> data abstraction</a>, <a href="https://publications.waset.org/abstracts/search?q=maps" title=" maps"> maps</a>, <a href="https://publications.waset.org/abstracts/search?q=specification" title=" specification"> specification</a>, <a href="https://publications.waset.org/abstracts/search?q=tree" title=" tree"> tree</a>, <a href="https://publications.waset.org/abstracts/search?q=verification" title=" verification"> verification</a> </p> <a href="https://publications.waset.org/abstracts/131080/an-encapsulation-of-a-navigable-tree-position-theory-specification-and-verification" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/131080.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">166</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">584</span> Pyramid Binary Pattern for Age Invariant Face Verification</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Saroj%20Bijarnia">Saroj Bijarnia</a>, <a href="https://publications.waset.org/abstracts/search?q=Preety%20Singh"> Preety Singh</a> </p> <p class="card-text"><strong>Abstract:</strong></p> We propose a simple and effective biometrics system based on face verification across aging using a new variant of texture feature, Pyramid Binary Pattern. This employs Local Binary Pattern along with its hierarchical information. Dimension reduction of generated texture feature vector is done using Principal Component Analysis. Support Vector Machine is used for classification. Our proposed method achieves an accuracy of 92:24% and can be used in an automated age-invariant face verification system. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=biometrics" title="biometrics">biometrics</a>, <a href="https://publications.waset.org/abstracts/search?q=age%20invariant" title=" age invariant"> age invariant</a>, <a href="https://publications.waset.org/abstracts/search?q=verification" title=" verification"> verification</a>, <a href="https://publications.waset.org/abstracts/search?q=support%20vector%20machine" title=" support vector machine"> support vector machine</a> </p> <a href="https://publications.waset.org/abstracts/64435/pyramid-binary-pattern-for-age-invariant-face-verification" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/64435.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">352</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">583</span> Physical Verification Flow on Multiple Foundries</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Rohaya%20Abdul%20Wahab">Rohaya Abdul Wahab</a>, <a href="https://publications.waset.org/abstracts/search?q=Raja%20Mohd%20Fuad%20Tengku%20Aziz"> Raja Mohd Fuad Tengku Aziz</a>, <a href="https://publications.waset.org/abstracts/search?q=Nazaliza%20Othman"> Nazaliza Othman</a>, <a href="https://publications.waset.org/abstracts/search?q=Sharifah%20Saleh"> Sharifah Saleh</a>, <a href="https://publications.waset.org/abstracts/search?q=Nabihah%20Razali"> Nabihah Razali</a>, <a href="https://publications.waset.org/abstracts/search?q=Muhammad%20Al%20Baqir%20Zinal%20Abidin"> Muhammad Al Baqir Zinal Abidin</a>, <a href="https://publications.waset.org/abstracts/search?q=Md%20Hanif%20Md%20Nasir"> Md Hanif Md Nasir </a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper will discuss how we optimize our physical verification flow in our IC Design Department having various rule decks from multiple foundries. Our ultimate goal is to achieve faster time to tape-out and avoid schedule delay. Currently the physical verification runtimes and memory usage have drastically increased with the increasing number of design rules, design complexity and the size of the chips to be verified. To manage design violations, we use a number of solutions to reduce the amount of violations needed to be checked by physical verification engineers. The most important functions in physical verifications are DRC (design rule check), LVS (layout vs. schematic) and XRC (extraction). Since we have a multiple number of foundries for our design tape-outs, we need a flow that improve the overall turnaround time and ease of use of the physical verification process. The demand for fast turnaround time is even more critical since the physical design is the last stage before sending the layout to the foundries. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=physical%20verification" title="physical verification">physical verification</a>, <a href="https://publications.waset.org/abstracts/search?q=DRC" title=" DRC"> DRC</a>, <a href="https://publications.waset.org/abstracts/search?q=LVS" title=" LVS"> LVS</a>, <a href="https://publications.waset.org/abstracts/search?q=XRC" title=" XRC"> XRC</a>, <a href="https://publications.waset.org/abstracts/search?q=flow" title=" flow"> flow</a>, <a href="https://publications.waset.org/abstracts/search?q=foundry" title=" foundry"> foundry</a>, <a href="https://publications.waset.org/abstracts/search?q=runset" title=" runset"> runset</a> </p> <a href="https://publications.waset.org/abstracts/29033/physical-verification-flow-on-multiple-foundries" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/29033.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">654</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">582</span> Dynamic Software Product Lines for Customer Centric Context Aware Business Process Management</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Bochra%20Khiari">Bochra Khiari</a>, <a href="https://publications.waset.org/abstracts/search?q=Lamia%20Labed"> Lamia Labed</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In the new digital marketplace, organizations are striving for a proactive position by leveraging the great potential of disruptive technologies to seize the full opportunity of the digital revolution in order to reshape their customer value propositions. New technologies such as big data analytics, which provide prediction of future events based on real-time information, are being integrated into BPM which urges the need for additional core values like capabilities for dynamic adaptation, autonomic behavior, runtime reconfiguration and post-deployment activities to manage unforeseen scenarios at runtime in a situated and changeable context. Dynamic Software Product Lines (DSPL) is an emerging paradigm that supports these runtime variability mechanisms. However, few works exploiting DSPLs principles and techniques in the BPM domain have been proposed so far. In this paper, we propose a conceptual approach DynPL4CBPM, which integrates DSPLs concepts along with the entire related dynamic properties, to the whole BPM lifecycle in order to dynamically adapt business processes according to different context conditions in an individual environment. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=adaptive%20processes" title="adaptive processes">adaptive processes</a>, <a href="https://publications.waset.org/abstracts/search?q=context%20aware%20business%20process%20management" title=" context aware business process management"> context aware business process management</a>, <a href="https://publications.waset.org/abstracts/search?q=customer%20centric%20business%20process%20management" title=" customer centric business process management"> customer centric business process management</a>, <a href="https://publications.waset.org/abstracts/search?q=dynamic%20software%20product%20lines" title=" dynamic software product lines"> dynamic software product lines</a> </p> <a href="https://publications.waset.org/abstracts/81537/dynamic-software-product-lines-for-customer-centric-context-aware-business-process-management" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/81537.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">161</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">581</span> A Reduced Distributed Sate Space for Modular Petri Nets</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Sawsen%20Khlifa">Sawsen Khlifa</a>, <a href="https://publications.waset.org/abstracts/search?q=Chiheb%20AMeur%20Abid"> Chiheb AMeur Abid</a>, <a href="https://publications.waset.org/abstracts/search?q=Belhassan%20Zouari"> Belhassan Zouari</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Modular verification approaches have been widely attempted to cope with the well known state explosion problem. This paper deals with the modular verification of modular Petri nets. We propose a reduced version for the modular state space of a given modular Petri net. The new structure allows the creation of smaller modular graphs. Each one draws the behavior of the corresponding module and outlines some global information. Hence, this version helps to overcome the explosion problem and to use less memory space. In this condensed structure, the verification of some generic properties concerning one module is limited to the exploration of its associated graph. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=distributed%20systems" title="distributed systems">distributed systems</a>, <a href="https://publications.waset.org/abstracts/search?q=modular%20verification" title=" modular verification"> modular verification</a>, <a href="https://publications.waset.org/abstracts/search?q=petri%20nets" title=" petri nets"> petri nets</a>, <a href="https://publications.waset.org/abstracts/search?q=state%20space%20explosition" title=" state space explosition"> state space explosition</a> </p> <a href="https://publications.waset.org/abstracts/148880/a-reduced-distributed-sate-space-for-modular-petri-nets" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/148880.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">115</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">580</span> Automatic Verification Technology of Virtual Machine Software Patch on IaaS Cloud</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yoji%20Yamato">Yoji Yamato</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, we propose an automatic verification technology of software patches for user virtual environments on IaaS Cloud to decrease verification costs of patches. In these days, IaaS services have been spread and many users can customize virtual machines on IaaS Cloud like their own private servers. Regarding to software patches of OS or middleware installed on virtual machines, users need to adopt and verify these patches by themselves. This task increases operation costs of users. Our proposed method replicates user virtual environments, extracts verification test cases for user virtual environments from test case DB, distributes patches to virtual machines on replicated environments and conducts those test cases automatically on replicated environments. We have implemented the proposed method on OpenStack using Jenkins and confirmed the feasibility. Using the implementation, we confirmed the effectiveness of test case creation efforts by our proposed idea of 2-tier abstraction of software functions and test cases. We also evaluated the automatic verification performance of environment replications, test cases extractions and test cases conductions. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=OpenStack" title="OpenStack">OpenStack</a>, <a href="https://publications.waset.org/abstracts/search?q=cloud%20computing" title=" cloud computing"> cloud computing</a>, <a href="https://publications.waset.org/abstracts/search?q=automatic%20verification" title=" automatic verification"> automatic verification</a>, <a href="https://publications.waset.org/abstracts/search?q=jenkins" title=" jenkins"> jenkins</a> </p> <a href="https://publications.waset.org/abstracts/17257/automatic-verification-technology-of-virtual-machine-software-patch-on-iaas-cloud" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/17257.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">488</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">579</span> Formal Verification for Ethereum Smart Contract Using Coq</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Xia%20Yang">Xia Yang</a>, <a href="https://publications.waset.org/abstracts/search?q=Zheng%20Yang"> Zheng Yang</a>, <a href="https://publications.waset.org/abstracts/search?q=Haiyong%20Sun"> Haiyong Sun</a>, <a href="https://publications.waset.org/abstracts/search?q=Yan%20Fang"> Yan Fang</a>, <a href="https://publications.waset.org/abstracts/search?q=Jingyu%20Liu"> Jingyu Liu</a>, <a href="https://publications.waset.org/abstracts/search?q=Jia%20Song"> Jia Song</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The smart contract in Ethereum is a unique program deployed on the Ethereum Virtual Machine (EVM) to help manage cryptocurrency. The security of this smart contract is critical to Ethereum’s operation and highly sensitive. In this paper, we present a formal model for smart contract, using the separated term-obligation (STO) strategy to formalize and verify the smart contract. We use the IBM smart sponsor contract (SSC) as an example to elaborate the detail of the formalizing process. We also propose a formal smart sponsor contract model (FSSCM) and verify SSC’s security properties with an interactive theorem prover Coq. We found the 'Unchecked-Send' vulnerability in the SSC, using our formal model and verification method. Finally, we demonstrate how we can formalize and verify other smart contracts with this approach, and our work indicates that this formal verification can effectively verify the correctness and security of smart contracts. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=smart%20contract" title="smart contract">smart contract</a>, <a href="https://publications.waset.org/abstracts/search?q=formal%20verification" title=" formal verification"> formal verification</a>, <a href="https://publications.waset.org/abstracts/search?q=Ethereum" title=" Ethereum"> Ethereum</a>, <a href="https://publications.waset.org/abstracts/search?q=Coq" title=" Coq"> Coq</a> </p> <a href="https://publications.waset.org/abstracts/85595/formal-verification-for-ethereum-smart-contract-using-coq" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/85595.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">691</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">578</span> Identity Verification Using k-NN Classifiers and Autistic Genetic Data</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Fuad%20M.%20Alkoot">Fuad M. Alkoot</a> </p> <p class="card-text"><strong>Abstract:</strong></p> DNA data have been used in forensics for decades. However, current research looks at using the DNA as a biometric identity verification modality. The goal is to improve the speed of identification. We aim at using gene data that was initially used for autism detection to find if and how accurate is this data for identification applications. Mainly our goal is to find if our data preprocessing technique yields data useful as a biometric identification tool. We experiment with using the nearest neighbor classifier to identify subjects. Results show that optimal classification rate is achieved when the test set is corrupted by normally distributed noise with zero mean and standard deviation of 1. The classification rate is close to optimal at higher noise standard deviation reaching 3. This shows that the data can be used for identity verification with high accuracy using a simple classifier such as the k-nearest neighbor (k-NN).  <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=biometrics" title="biometrics">biometrics</a>, <a href="https://publications.waset.org/abstracts/search?q=genetic%20data" title=" genetic data"> genetic data</a>, <a href="https://publications.waset.org/abstracts/search?q=identity%20verification" title=" identity verification"> identity verification</a>, <a href="https://publications.waset.org/abstracts/search?q=k%20nearest%20neighbor" title=" k nearest neighbor"> k nearest neighbor</a> </p> <a href="https://publications.waset.org/abstracts/75552/identity-verification-using-k-nn-classifiers-and-autistic-genetic-data" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/75552.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">258</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">577</span> Failure Analysis and Verification Using an Integrated Method for Automotive Electric/Electronic Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Lei%20Chen">Lei Chen</a>, <a href="https://publications.waset.org/abstracts/search?q=Jian%20Jiao"> Jian Jiao</a>, <a href="https://publications.waset.org/abstracts/search?q=Tingdi%20Zhao"> Tingdi Zhao</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Failures of automotive electric/electronic systems, which are universally considered to be safety-critical and software-intensive, may cause catastrophic accidents. Analysis and verification of failures in these kinds of systems is a big challenge with increasing system complexity. Model-checking is often employed to allow formal verification by ensuring that the system model conforms to specified safety properties. The system-level effects of failures are established, and the effects on system behavior are observed through the formal verification. A hazard analysis technique, called Systems-Theoretic Process Analysis, is capable of identifying design flaws which may cause potential failure hazardous, including software and system design errors and unsafe interactions among multiple system components. This paper provides a concept on how to use model-checking integrated with Systems-Theoretic Process Analysis to perform failure analysis and verification of automotive electric/electronic systems. As a result, safety requirements are optimized, and failure propagation paths are found. Finally, an automotive electric/electronic system case study is used to verify the effectiveness and practicability of the method. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=failure%20analysis%20and%20verification" title="failure analysis and verification">failure analysis and verification</a>, <a href="https://publications.waset.org/abstracts/search?q=model%20checking" title=" model checking"> model checking</a>, <a href="https://publications.waset.org/abstracts/search?q=system-theoretic%20process%20analysis" title=" system-theoretic process analysis"> system-theoretic process analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=automotive%20electric%2Felectronic%20system" title=" automotive electric/electronic system"> automotive electric/electronic system</a> </p> <a href="https://publications.waset.org/abstracts/112321/failure-analysis-and-verification-using-an-integrated-method-for-automotive-electricelectronic-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/112321.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">120</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">576</span> Online Authenticity Verification of a Biometric Signature Using Dynamic Time Warping Method and Neural Networks</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ga%C5%82ka%20Aleksandra">Gałka Aleksandra</a>, <a href="https://publications.waset.org/abstracts/search?q=Jeli%C5%84ska%20Justyna"> Jelińska Justyna</a>, <a href="https://publications.waset.org/abstracts/search?q=Masiak%20Albert"> Masiak Albert</a>, <a href="https://publications.waset.org/abstracts/search?q=Walentukiewicz%20Krzysztof"> Walentukiewicz Krzysztof</a> </p> <p class="card-text"><strong>Abstract:</strong></p> An offline signature is well-known however not the safest way to verify identity. Nowadays, to ensure proper authentication, i.e. in banking systems, multimodal verification is more widely used. In this paper the online signature analysis based on dynamic time warping (DTW) coupled with machine learning approaches has been presented. In our research signatures made with biometric pens were gathered. Signature features as well as their forgeries have been described. For verification of authenticity various methods were used including convolutional neural networks using DTW matrix and multilayer perceptron using sums of DTW matrix paths. System efficiency has been evaluated on signatures and signature forgeries collected on the same day. Results are presented and discussed in this paper. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=dynamic%20time%20warping" title="dynamic time warping">dynamic time warping</a>, <a href="https://publications.waset.org/abstracts/search?q=handwritten%20signature%20verification" title=" handwritten signature verification"> handwritten signature verification</a>, <a href="https://publications.waset.org/abstracts/search?q=feature-based%20recognition" title=" feature-based recognition"> feature-based recognition</a>, <a href="https://publications.waset.org/abstracts/search?q=online%20signature" title=" online signature"> online signature</a> </p> <a href="https://publications.waset.org/abstracts/153364/online-authenticity-verification-of-a-biometric-signature-using-dynamic-time-warping-method-and-neural-networks" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/153364.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">175</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">575</span> Satellite Technology Usage for Greenhouse Gas Emissions Monitoring and Verification: Policy Considerations for an International System</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Timiebi%20Aganaba-Jeanty">Timiebi Aganaba-Jeanty</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Accurate and transparent monitoring, reporting and verification of Greenhouse Gas (GHG) emissions and removals is a requirement of the United Nations Framework Convention on Climate Change (UNFCCC). Several countries are obligated to prepare and submit an annual national greenhouse gas inventory covering anthropogenic emissions by sources and removals by sinks, subject to a review conducted by an international team of experts. However, the process is not without flaws. The self-reporting varies enormously in thoroughness, frequency and accuracy including inconsistency in the way such reporting occurs. The world’s space agencies are calling for a new generation of satellites that would be precise enough to map greenhouse gas emissions from individual nations. The plan is delicate politically because the global system could verify or cast doubt on emission reports from the member states of the UNFCCC. A level playing field is required and an idea that an international system should be perceived as an instrument to facilitate fairness and equality rather than to spy on or punish. This change of perspective is required to get buy in for an international verification system. The research proposes the viability of a satellite system that provides independent access to data regarding greenhouse gas emissions and the policy and governance implications of its potential use as a monitoring and verification system for the Paris Agreement. It assesses the foundations of the reporting monitoring and verification system as proposed in Paris and analyzes this in light of a proposed satellite system. The use of remote sensing technology has been debated for verification purposes and as evidence in courts but this is not without controversy. Lessons can be learned from its use in this context. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=greenhouse%20gas%20emissions" title="greenhouse gas emissions">greenhouse gas emissions</a>, <a href="https://publications.waset.org/abstracts/search?q=reporting" title=" reporting"> reporting</a>, <a href="https://publications.waset.org/abstracts/search?q=monitoring%20and%20verification" title=" monitoring and verification"> monitoring and verification</a>, <a href="https://publications.waset.org/abstracts/search?q=satellite" title=" satellite"> satellite</a>, <a href="https://publications.waset.org/abstracts/search?q=UNFCCC" title=" UNFCCC"> UNFCCC</a> </p> <a href="https://publications.waset.org/abstracts/57507/satellite-technology-usage-for-greenhouse-gas-emissions-monitoring-and-verification-policy-considerations-for-an-international-system" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/57507.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">286</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">574</span> The Co-Simulation Interface SystemC/Matlab Applied in JPEG and SDR Application</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Walid%20Hassairi">Walid Hassairi</a>, <a href="https://publications.waset.org/abstracts/search?q=Moncef%20Bousselmi"> Moncef Bousselmi</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohamed%20Abid"> Mohamed Abid</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Functional verification is a major part of today’s system design task. Several approaches are available for verification on a high abstraction level, where designs are often modeled using MATLAB/Simulink. However, different approaches are a barrier to a unified verification flow. In this paper, we propose a co-simulation interface between SystemC and MATLAB and Simulink to enable functional verification of multi-abstraction levels designs. The resulting verification flow is tested on JPEG compression algorithm. The required synchronization of both simulation environments, as well as data type conversion is solved using the proposed co-simulation flow. We divided into two encoder jpeg parts. First implemented in SystemC which is the DCT is representing the HW part. Second, consisted of quantization and entropy encoding which is implemented in Matlab is the SW part. For communication and synchronization between these two parts we use S-Function and engine in Simulink matlab. With this research premise, this study introduces a new implementation of a Hardware SystemC of DCT. We compare the result of our simulation compared to SW / SW. We observe a reduction in simulation time you have 88.15% in JPEG and the design efficiency of the supply design is 90% in SDR. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=hardware%2Fsoftware" title="hardware/software">hardware/software</a>, <a href="https://publications.waset.org/abstracts/search?q=co-design" title=" co-design"> co-design</a>, <a href="https://publications.waset.org/abstracts/search?q=co-simulation" title=" co-simulation"> co-simulation</a>, <a href="https://publications.waset.org/abstracts/search?q=systemc" title=" systemc"> systemc</a>, <a href="https://publications.waset.org/abstracts/search?q=matlab" title=" matlab"> matlab</a>, <a href="https://publications.waset.org/abstracts/search?q=s-function" title=" s-function"> s-function</a>, <a href="https://publications.waset.org/abstracts/search?q=communication" title=" communication"> communication</a>, <a href="https://publications.waset.org/abstracts/search?q=synchronization" title=" synchronization"> synchronization</a> </p> <a href="https://publications.waset.org/abstracts/39414/the-co-simulation-interface-systemcmatlab-applied-in-jpeg-and-sdr-application" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/39414.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">405</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">573</span> A Proposal for Systematic Mapping Study of Software Security Testing, Verification and Validation</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Adriano%20Bessa%20Albuquerque">Adriano Bessa Albuquerque</a>, <a href="https://publications.waset.org/abstracts/search?q=Francisco%20Jose%20Barreto%20Nunes"> Francisco Jose Barreto Nunes</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Software vulnerabilities are increasing and not only impact services and processes availability as well as information confidentiality, integrity and privacy, but also cause changes that interfere in the development process. Security test could be a solution to reduce vulnerabilities. However, the variety of test techniques with the lack of real case studies of applying tests focusing on software development life cycle compromise its effective use. This paper offers an overview of how a Systematic Mapping Study (MS) about security verification, validation and test (VVT) was performed, besides presenting general results about this study. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=software%20test" title="software test">software test</a>, <a href="https://publications.waset.org/abstracts/search?q=software%20security%20verification%20validation%20and%20test" title=" software security verification validation and test"> software security verification validation and test</a>, <a href="https://publications.waset.org/abstracts/search?q=security%20test%20institutionalization" title=" security test institutionalization"> security test institutionalization</a>, <a href="https://publications.waset.org/abstracts/search?q=systematic%20mapping%20study" title=" systematic mapping study"> systematic mapping study</a> </p> <a href="https://publications.waset.org/abstracts/43751/a-proposal-for-systematic-mapping-study-of-software-security-testing-verification-and-validation" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/43751.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">409</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">572</span> Biometric Identification with Latitude and Longitude Fingerprint Verification for Attendance</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Muhammad%20Fezan%20Afzal">Muhammad Fezan Afzal</a>, <a href="https://publications.waset.org/abstracts/search?q=Imran%20Khan"> Imran Khan</a>, <a href="https://publications.waset.org/abstracts/search?q=Salma%20Imtiaz"> Salma Imtiaz</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The need for human verification and identification requires from centuries for authentication. Since it is being used in big institutes like financial, government and crime departments, a continued struggle is important to make this system more efficient to prevent security breaches. Therefore, multiple devices are used to authenticate the biometric for each individual. A large number of devices are required to cover a large number of users. As the number of devices increases, cost will automatically increase. Furthermore, it is time-consuming for biometrics due to the devices being insufficient and are not available at every door. In this paper, we propose the framework and algorithm where the mobile of each individual can also perform the biometric authentication of attendance and security. Every mobile has a biometric authentication system that is used in different mobile applications for security purposes. Therefore, each individual can use the biometric system mobile without moving from one place to another. Moreover, by using the biometrics mobile, the cost of biometric systems can be removed that are mostly deployed in different organizations for the attendance of students, employees and for other security purposes. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=fingerprint" title="fingerprint">fingerprint</a>, <a href="https://publications.waset.org/abstracts/search?q=fingerprint%20authentication" title=" fingerprint authentication"> fingerprint authentication</a>, <a href="https://publications.waset.org/abstracts/search?q=mobile%20verification" title=" mobile verification"> mobile verification</a>, <a href="https://publications.waset.org/abstracts/search?q=mobile%20biometric%20verification" title=" mobile biometric verification"> mobile biometric verification</a>, <a href="https://publications.waset.org/abstracts/search?q=mobile%20fingerprint%20sensor" title=" mobile fingerprint sensor"> mobile fingerprint sensor</a> </p> <a href="https://publications.waset.org/abstracts/171752/biometric-identification-with-latitude-and-longitude-fingerprint-verification-for-attendance" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/171752.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">69</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">571</span> Automation Test Method and HILS Environment Configuration for Hydrogen Storage System Management Unit Verification</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jaejeogn%20Kim">Jaejeogn Kim</a>, <a href="https://publications.waset.org/abstracts/search?q=Jeongmin%20Hong"> Jeongmin Hong</a>, <a href="https://publications.waset.org/abstracts/search?q=Jungin%20Lee"> Jungin Lee</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The Hydrogen Storage System Management Unit (HMU) is a controller that manages hydrogen charging and storage. It detects hydrogen leaks and tank pressure and temperature, calculates the charging concentration and remaining amount, and controls the opening and closing of the hydrogen tank valve. Since this role is an important part of the vehicle behavior and stability of Fuel Cell Electric Vehicles (FCEV), verifying the HMU controller is an essential part. To perform verification under various conditions, it is necessary to increase time efficiency based on an automated verification environment and increase the reliability of the controller by applying numerous test cases. To this end, we introduce the HMU controller automation verification method by applying the HILS environment and an automation test program with the ASAM XIL standard. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=HILS" title="HILS">HILS</a>, <a href="https://publications.waset.org/abstracts/search?q=ASAM" title=" ASAM"> ASAM</a>, <a href="https://publications.waset.org/abstracts/search?q=fuel%20cell%20electric%20vehicle" title=" fuel cell electric vehicle"> fuel cell electric vehicle</a>, <a href="https://publications.waset.org/abstracts/search?q=automation%20test" title=" automation test"> automation test</a>, <a href="https://publications.waset.org/abstracts/search?q=hydrogen%20storage%20system" title=" hydrogen storage system"> hydrogen storage system</a> </p> <a href="https://publications.waset.org/abstracts/184315/automation-test-method-and-hils-environment-configuration-for-hydrogen-storage-system-management-unit-verification" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/184315.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">70</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">570</span> Leveraging Hyperledger Iroha for the Issuance and Verification of Higher-Education Certificates</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Vasiliki%20Vlachou">Vasiliki Vlachou</a>, <a href="https://publications.waset.org/abstracts/search?q=Christos%20Kontzinos"> Christos Kontzinos</a>, <a href="https://publications.waset.org/abstracts/search?q=Ourania%20Markaki"> Ourania Markaki</a>, <a href="https://publications.waset.org/abstracts/search?q=Panagiotis%20Kokkinakos"> Panagiotis Kokkinakos</a>, <a href="https://publications.waset.org/abstracts/search?q=Vagelis%20Karakolis"> Vagelis Karakolis</a>, <a href="https://publications.waset.org/abstracts/search?q=John%20Psarras"> John Psarras</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Higher Education is resisting the pull of technology, especially as this concerns the issuance and verification of degrees and certificates. It is widely known that education certificates are largely produced in paper form making them vulnerable to damage while holders of such certificates are dependent on the universities and other issuing organisations. QualiChain is an EU Horizon 2020 (H2020) research project aiming to transform and revolutionise the domain of public education and its ties with the job market by leveraging blockchain, analytics and decision support to develop a platform for the verification and sharing of education certificates. Blockchain plays an integral part in the QualiChain solution in providing a trustworthy environment to store, share and manage such accreditations. Under the context of this paper, three prominent blockchain platforms (Ethereum, Hyperledger Fabric, Hyperledger Iroha) were considered as a means of experimentation for creating a system with the basic functionalities that will be needed for trustworthy degree verification. The methodology and respective system developed and presented in this paper used Hyperledger Iroha and proved that this specific platform can be used to easily develop decentralize applications. Future papers will attempt to further experiment with other blockchain platforms and assess which has the best potential. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=blockchain" title="blockchain">blockchain</a>, <a href="https://publications.waset.org/abstracts/search?q=degree%20verification" title=" degree verification"> degree verification</a>, <a href="https://publications.waset.org/abstracts/search?q=higher%20education%20certificates" title=" higher education certificates"> higher education certificates</a>, <a href="https://publications.waset.org/abstracts/search?q=Hyperledger%20Iroha" title=" Hyperledger Iroha"> Hyperledger Iroha</a> </p> <a href="https://publications.waset.org/abstracts/127503/leveraging-hyperledger-iroha-for-the-issuance-and-verification-of-higher-education-certificates" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/127503.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">141</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">569</span> Verification and Validation of Simulated Process Models of KALBR-SIM Training Simulator</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=T.%20Jayanthi">T. Jayanthi</a>, <a href="https://publications.waset.org/abstracts/search?q=K.%20Velusamy"> K. Velusamy</a>, <a href="https://publications.waset.org/abstracts/search?q=H.%20Seetha"> H. Seetha</a>, <a href="https://publications.waset.org/abstracts/search?q=S.%20A.%20V.%20Satya%20Murty"> S. A. V. Satya Murty</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Verification and Validation of Simulated Process Model is the most important phase of the simulator life cycle. Evaluation of simulated process models based on Verification and Validation techniques checks the closeness of each component model (in a simulated network) with the real system/process with respect to dynamic behaviour under steady state and transient conditions. The process of Verification and validation helps in qualifying the process simulator for the intended purpose whether it is for providing comprehensive training or design verification. In general, model verification is carried out by comparison of simulated component characteristics with the original requirement to ensure that each step in the model development process completely incorporates all the design requirements. Validation testing is performed by comparing the simulated process parameters to the actual plant process parameters either in standalone mode or integrated mode. A Full Scope Replica Operator Training Simulator for PFBR - Prototype Fast Breeder Reactor has been developed at IGCAR, Kalpakkam, INDIA named KALBR-SIM (Kalpakkam Breeder Reactor Simulator) wherein the main participants are engineers/experts belonging to Modeling Team, Process Design and Instrumentation and Control design team. This paper discusses the Verification and Validation process in general, the evaluation procedure adopted for PFBR operator training Simulator, the methodology followed for verifying the models, the reference documents and standards used etc. It details out the importance of internal validation by design experts, subsequent validation by external agency consisting of experts from various fields, model improvement by tuning based on expert’s comments, final qualification of the simulator for the intended purpose and the difficulties faced while co-coordinating various activities. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Verification%20and%20Validation%20%28V%26V%29" title="Verification and Validation (V&V)">Verification and Validation (V&V)</a>, <a href="https://publications.waset.org/abstracts/search?q=Prototype%20Fast%20Breeder%20Reactor%20%28PFBR%29" title=" Prototype Fast Breeder Reactor (PFBR)"> Prototype Fast Breeder Reactor (PFBR)</a>, <a href="https://publications.waset.org/abstracts/search?q=Kalpakkam%20Breeder%20Reactor%20Simulator%20%28KALBR-SIM%29" title=" Kalpakkam Breeder Reactor Simulator (KALBR-SIM)"> Kalpakkam Breeder Reactor Simulator (KALBR-SIM)</a>, <a href="https://publications.waset.org/abstracts/search?q=steady%20state" title=" steady state"> steady state</a>, <a href="https://publications.waset.org/abstracts/search?q=transient%20state" title=" transient state"> transient state</a> </p> <a href="https://publications.waset.org/abstracts/16092/verification-and-validation-of-simulated-process-models-of-kalbr-sim-training-simulator" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/16092.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">266</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">568</span> Urban Rail Transit CBTC Computer Interlocking Subsystem Relying on Multi-Template Pen Point Tracking Algorithm</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Xinli%20Chen">Xinli Chen</a>, <a href="https://publications.waset.org/abstracts/search?q=Xue%20Su"> Xue Su</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In the urban rail transit CBTC system, interlocking is considered one of the most basic sys-tems, which has the characteristics of logical complexity and high-security requirements. The development and verification of traditional interlocking subsystems are entirely manual pro-cesses and rely too much on the designer, which often hides many uncertain factors. In order to solve this problem, this article is based on the multi-template nib tracking algorithm for model construction and verification, achieving the main safety attributes and using SCADE for formal verification. Experimental results show that this method helps to improve the quality and efficiency of interlocking software. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=computer%20interlocking%20subsystem" title="computer interlocking subsystem">computer interlocking subsystem</a>, <a href="https://publications.waset.org/abstracts/search?q=penpoint%20tracking" title=" penpoint tracking"> penpoint tracking</a>, <a href="https://publications.waset.org/abstracts/search?q=communication-based%20train%20control%20system" title=" communication-based train control system"> communication-based train control system</a>, <a href="https://publications.waset.org/abstracts/search?q=multi-template%20tip%20tracking" title=" multi-template tip tracking"> multi-template tip tracking</a> </p> <a href="https://publications.waset.org/abstracts/140081/urban-rail-transit-cbtc-computer-interlocking-subsystem-relying-on-multi-template-pen-point-tracking-algorithm" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/140081.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">160</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">567</span> Developed Text-Independent Speaker Verification System</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mohammed%20Arif">Mohammed Arif</a>, <a href="https://publications.waset.org/abstracts/search?q=Abdessalam%20Kifouche"> Abdessalam Kifouche</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Speech is a very convenient way of communication between people and machines. It conveys information about the identity of the talker. Since speaker recognition technology is increasingly securing our everyday lives, the objective of this paper is to develop two automatic text-independent speaker verification systems (TI SV) using low-level spectral features and machine learning methods. (i) The first system is based on a support vector machine (SVM), which was widely used in voice signal processing with the aim of speaker recognition involving verifying the identity of the speaker based on its voice characteristics, and (ii) the second is based on Gaussian Mixture Model (GMM) and Universal Background Model (UBM) to combine different functions from different resources to implement the SVM based. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=speaker%20verification" title="speaker verification">speaker verification</a>, <a href="https://publications.waset.org/abstracts/search?q=text-independent" title=" text-independent"> text-independent</a>, <a href="https://publications.waset.org/abstracts/search?q=support%20vector%20machine" title=" support vector machine"> support vector machine</a>, <a href="https://publications.waset.org/abstracts/search?q=Gaussian%20mixture%20model" title=" Gaussian mixture model"> Gaussian mixture model</a>, <a href="https://publications.waset.org/abstracts/search?q=cepstral%20analysis" title=" cepstral analysis"> cepstral analysis</a> </p> <a href="https://publications.waset.org/abstracts/183493/developed-text-independent-speaker-verification-system" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/183493.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">58</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">566</span> End to End Monitoring in Oracle Fusion Middleware for Data Verification</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Syed%20Kashif%20Ali">Syed Kashif Ali</a>, <a href="https://publications.waset.org/abstracts/search?q=Usman%20Javaid"> Usman Javaid</a>, <a href="https://publications.waset.org/abstracts/search?q=Abdullah%20Chohan"> Abdullah Chohan</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In large enterprises multiple departments use different sort of information systems and databases according to their needs. These systems are independent and heterogeneous in nature and sharing information/data between these systems is not an easy task. The usage of middleware technologies have made data sharing between systems very easy. However, monitoring the exchange of data/information for verification purposes between target and source systems is often complex or impossible for maintenance department due to security/access privileges on target and source systems. In this paper, we are intended to present our experience of an end to end data monitoring approach at middle ware level implemented in Oracle BPEL for data verification without any help of monitoring tool. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=service%20level%20agreement" title="service level agreement">service level agreement</a>, <a href="https://publications.waset.org/abstracts/search?q=SOA" title=" SOA"> SOA</a>, <a href="https://publications.waset.org/abstracts/search?q=BPEL" title=" BPEL"> BPEL</a>, <a href="https://publications.waset.org/abstracts/search?q=oracle%20fusion%20middleware" title=" oracle fusion middleware"> oracle fusion middleware</a>, <a href="https://publications.waset.org/abstracts/search?q=web%20service%20monitoring" title=" web service monitoring"> web service monitoring</a> </p> <a href="https://publications.waset.org/abstracts/18853/end-to-end-monitoring-in-oracle-fusion-middleware-for-data-verification" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/18853.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">480</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">565</span> Bias-Corrected Estimation Methods for Receiver Operating Characteristic Surface</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Khanh%20To%20Duc">Khanh To Duc</a>, <a href="https://publications.waset.org/abstracts/search?q=Monica%20Chiogna"> Monica Chiogna</a>, <a href="https://publications.waset.org/abstracts/search?q=Gianfranco%20Adimari"> Gianfranco Adimari</a> </p> <p class="card-text"><strong>Abstract:</strong></p> With three diagnostic categories, assessment of the performance of diagnostic tests is achieved by the analysis of the receiver operating characteristic (ROC) surface, which generalizes the ROC curve for binary diagnostic outcomes. The volume under the ROC surface (VUS) is a summary index usually employed for measuring the overall diagnostic accuracy. When the true disease status can be exactly assessed by means of a gold standard (GS) test, unbiased nonparametric estimators of the ROC surface and VUS are easily obtained. In practice, unfortunately, disease status verification via the GS test could be unavailable for all study subjects, due to the expensiveness or invasiveness of the GS test. Thus, often only a subset of patients undergoes disease verification. Statistical evaluations of diagnostic accuracy based only on data from subjects with verified disease status are typically biased. This bias is known as verification bias. Here, we consider the problem of correcting for verification bias when continuous diagnostic tests for three-class disease status are considered. We assume that selection for disease verification does not depend on disease status, given test results and other observed covariates, i.e., we assume that the true disease status, when missing, is missing at random. Under this assumption, we discuss several solutions for ROC surface analysis based on imputation and re-weighting methods. In particular, verification bias-corrected estimators of the ROC surface and of VUS are proposed, namely, full imputation, mean score imputation, inverse probability weighting and semiparametric efficient estimators. Consistency and asymptotic normality of the proposed estimators are established, and their finite sample behavior is investigated by means of Monte Carlo simulation studies. Two illustrations using real datasets are also given. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=imputation" title="imputation">imputation</a>, <a href="https://publications.waset.org/abstracts/search?q=missing%20at%20random" title=" missing at random"> missing at random</a>, <a href="https://publications.waset.org/abstracts/search?q=inverse%20probability%20weighting" title=" inverse probability weighting"> inverse probability weighting</a>, <a href="https://publications.waset.org/abstracts/search?q=ROC%20surface%20analysis" title=" ROC surface analysis"> ROC surface analysis</a> </p> <a href="https://publications.waset.org/abstracts/51883/bias-corrected-estimation-methods-for-receiver-operating-characteristic-surface" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/51883.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">416</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">564</span> A Formal Verification Approach for Linux Kernel Designing</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Zi%20Wang">Zi Wang</a>, <a href="https://publications.waset.org/abstracts/search?q=Xinlei%20He"> Xinlei He</a>, <a href="https://publications.waset.org/abstracts/search?q=Jianghua%20Lv"> Jianghua Lv</a>, <a href="https://publications.waset.org/abstracts/search?q=Yuqing%20Lan"> Yuqing Lan</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Kernel though widely used, is complicated. Errors caused by some bugs are often costly. Statically, more than half of the mistakes occur in the design phase. Thus, we introduce a modeling method, KMVM (Linux Kernel Modeling and verification Method), based on type theory for proper designation and correct exploitation of the Kernel. In the model, the Kernel is separated into six levels: subsystem, dentry, file, struct, func, and base. Each level is treated as a type. The types are specified in the structure and relationship. At the same time, we use a demanding path to express the function to be implemented. The correctness of the design is verified by recursively checking the type relationship and type existence. The method has been applied to verify the OPEN business of VFS (virtual file system) in Linux Kernel. Also, we have designed and developed a set of security communication mechanisms in the Kernel with verification. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=formal%20approach" title="formal approach">formal approach</a>, <a href="https://publications.waset.org/abstracts/search?q=type%20theory" title=" type theory"> type theory</a>, <a href="https://publications.waset.org/abstracts/search?q=Linux%20Kernel" title=" Linux Kernel"> Linux Kernel</a>, <a href="https://publications.waset.org/abstracts/search?q=software%20program" title=" software program"> software program</a> </p> <a href="https://publications.waset.org/abstracts/155062/a-formal-verification-approach-for-linux-kernel-designing" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/155062.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads 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