<?xml version="1.0" encoding="UTF-8"?> <article key="pdf/15954" mdate="2009-03-20 00:00:00"> <author>Ashwani K. Rana and Narottam Chand and Vinod Kapoor</author> <title>Trap Assisted Tunneling Model for Gate Current in Nano Scale MOSFET with HighK Gate Dielectrics</title> <pages>546 - 553</pages> <year>2009</year> <volume>3</volume> <number>3</number> <journal>International Journal of Electronics and Communication Engineering</journal> <ee>https://publications.waset.org/pdf/15954</ee> <url>https://publications.waset.org/vol/27</url> <publisher>World Academy of Science, Engineering and Technology</publisher> <abstract>This paper presents a new compact analytical model of the gate leakage current in highk based nano scale MOSFET by assuming a twostep inelastic trapassisted tunneling (ITAT) process as the conduction mechanism. This model is based on an inelastic trapassisted tunneling (ITAT) mechanism combined with a semiempirical gate leakage current formulation in the BSIM 4 model. The gate tunneling currents have been calculated as a function of gate voltage for different gate dielectrics structures such as HfO2, Al2O3 and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The proposed model is compared and contrasted with santaurus simulation results to verify the accuracy of the model and excellent agreement is found between the analytical and simulated data. It is observed that proposed analytical model is suitable for different highk gate dielectrics simply by adjusting two fitting parameters. It was also shown that gate leakages reduced with the introduction of highk gate dielectric in place of SiO2.</abstract> <index>Open Science Index 27, 2009</index> </article>