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class="vector-toc-list"> <li id="toc-Links_and_rates" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Links_and_rates"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>Links and rates</span> </div> </a> <ul id="toc-Links_and_rates-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Packet-oriented" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Packet-oriented"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2</span> <span>Packet-oriented</span> </div> </a> <ul id="toc-Packet-oriented-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Power-managed" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Power-managed"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.3</span> <span>Power-managed</span> </div> </a> <ul id="toc-Power-managed-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Applications" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Applications"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Applications</span> </div> </a> <button aria-controls="toc-Applications-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Applications subsection</span> </button> <ul id="toc-Applications-sublist" class="vector-toc-list"> <li id="toc-Front-side_bus_replacement" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Front-side_bus_replacement"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Front-side bus replacement</span> </div> </a> <ul id="toc-Front-side_bus_replacement-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Multiprocessor_interconnect" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Multiprocessor_interconnect"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>Multiprocessor interconnect</span> </div> </a> <ul id="toc-Multiprocessor_interconnect-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Router_or_switch_bus_replacement" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Router_or_switch_bus_replacement"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Router or switch bus replacement</span> </div> </a> <ul id="toc-Router_or_switch_bus_replacement-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Co-processor_interconnect" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Co-processor_interconnect"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>Co-processor interconnect</span> </div> </a> <ul id="toc-Co-processor_interconnect-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Add-on_card_connector_(HTX_and_HTX3)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Add-on_card_connector_(HTX_and_HTX3)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.5</span> <span>Add-on card connector (HTX and HTX3)</span> </div> </a> <ul id="toc-Add-on_card_connector_(HTX_and_HTX3)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Testing" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Testing"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.6</span> <span>Testing</span> </div> </a> <ul id="toc-Testing-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Implementations" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Implementations"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Implementations</span> </div> </a> <ul id="toc-Implementations-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Frequency_specifications" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Frequency_specifications"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Frequency specifications</span> </div> </a> <ul id="toc-Frequency_specifications-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Name" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Name"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Name</span> </div> </a> <ul id="toc-Name-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Infinity_Fabric" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Infinity_Fabric"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Infinity Fabric</span> </div> </a> <ul id="toc-Infinity_Fabric-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">HyperTransport</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 22 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-22" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">22 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%AA%D9%82%D9%86%D9%8A%D8%A9_%D8%A7%D9%84%D8%B1%D8%A8%D8%B7_%D8%A7%D9%84%D9%81%D8%A7%D8%A6%D9%82" title="تقنية الربط الفائق – Arabic" lang="ar" hreflang="ar" data-title="تقنية الربط الفائق" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Catalan" lang="ca" hreflang="ca" data-title="HyperTransport" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/HyperTransport" title="HyperTransport – German" lang="de" hreflang="de" data-title="HyperTransport" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Estonian" lang="et" hreflang="et" data-title="HyperTransport" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Spanish" lang="es" hreflang="es" data-title="HyperTransport" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eo mw-list-item"><a href="https://eo.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Esperanto" lang="eo" hreflang="eo" data-title="HyperTransport" data-language-autonym="Esperanto" data-language-local-name="Esperanto" class="interlanguage-link-target"><span>Esperanto</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%81%D8%B1%D8%A7%D8%AA%D8%B1%D8%A7%D8%A8%D8%B1%DB%8C" title="فراترابری – Persian" lang="fa" hreflang="fa" data-title="فراترابری" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/HyperTransport" title="HyperTransport – French" lang="fr" hreflang="fr" data-title="HyperTransport" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-gl mw-list-item"><a href="https://gl.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Galician" lang="gl" hreflang="gl" data-title="HyperTransport" data-language-autonym="Galego" data-language-local-name="Galician" class="interlanguage-link-target"><span>Galego</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%ED%95%98%EC%9D%B4%ED%8D%BC%ED%8A%B8%EB%9E%9C%EC%8A%A4%ED%8F%AC%ED%8A%B8" title="하이퍼트랜스포트 – Korean" lang="ko" hreflang="ko" data-title="하이퍼트랜스포트" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-ha mw-list-item"><a href="https://ha.wikipedia.org/wiki/HyperTransportation" title="HyperTransportation – Hausa" lang="ha" hreflang="ha" data-title="HyperTransportation" data-language-autonym="Hausa" data-language-local-name="Hausa" class="interlanguage-link-target"><span>Hausa</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Indonesian" lang="id" hreflang="id" data-title="HyperTransport" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Italian" lang="it" hreflang="it" data-title="HyperTransport" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%B9%E0%B5%88%E0%B4%AA%E0%B5%8D%E0%B4%AA%E0%B5%BC%E0%B4%9F%E0%B5%8D%E0%B4%B0%E0%B4%BE%E0%B5%BB%E0%B4%B8%E0%B5%8D%E0%B4%AA%E0%B5%8B%E0%B5%BC%E0%B4%9F%E0%B5%8D%E0%B4%9F%E0%B5%8D" title="ഹൈപ്പർട്രാൻസ്പോർട്ട് – Malayalam" lang="ml" hreflang="ml" data-title="ഹൈപ്പർട്രാൻസ്പോർട്ട്" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Japanese" lang="ja" hreflang="ja" data-title="HyperTransport" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Polish" lang="pl" hreflang="pl" data-title="HyperTransport" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Portuguese" lang="pt" hreflang="pt" data-title="HyperTransport" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Russian" lang="ru" hreflang="ru" data-title="HyperTransport" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Finnish" lang="fi" hreflang="fi" data-title="HyperTransport" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Turkish" lang="tr" hreflang="tr" data-title="HyperTransport" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Ukrainian" lang="uk" hreflang="uk" data-title="HyperTransport" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/HyperTransport" title="HyperTransport – Chinese" lang="zh" hreflang="zh" data-title="HyperTransport" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q863778#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> <nav aria-label="Namespaces"> <div id="p-associated-pages" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-associated-pages" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-nstab-main" class="selected vector-tab-noicon mw-list-item"><a href="/wiki/HyperTransport" title="View the content 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.hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="/wiki/Hyper-Threading" class="mw-redirect" title="Hyper-Threading">Hyper-Threading</a>, which is also sometimes abbreviated "HT".</div> <p class="mw-empty-elt"> </p> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:HyperTransport_Consortium_logo.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e6/HyperTransport_Consortium_logo.svg/220px-HyperTransport_Consortium_logo.svg.png" decoding="async" width="220" height="33" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e6/HyperTransport_Consortium_logo.svg/330px-HyperTransport_Consortium_logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e6/HyperTransport_Consortium_logo.svg/440px-HyperTransport_Consortium_logo.svg.png 2x" data-file-width="2200" data-file-height="334" /></a><figcaption>Logo of the HyperTransport Consortium</figcaption></figure> <p><b>HyperTransport</b> (<b>HT</b>), formerly known as <b>Lightning Data Transport</b>, is a technology for interconnection of computer <a href="/wiki/Processor_(computing)" title="Processor (computing)">processors</a>. It is a bidirectional <a href="/wiki/Serial_communication" title="Serial communication">serial</a>/<a href="/wiki/Parallel_communication" title="Parallel communication">parallel</a> high-<a href="/wiki/Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a>, low-<a href="/wiki/Memory_latency" title="Memory latency">latency</a> <a href="/wiki/Point-to-point_link" class="mw-redirect" title="Point-to-point link">point-to-point link</a> that was introduced on April 2, 2001.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> The <a href="/wiki/HyperTransport_Consortium" title="HyperTransport Consortium">HyperTransport Consortium</a> is in charge of promoting and developing HyperTransport technology. </p><p>HyperTransport is best known as the <a href="/wiki/System_bus" title="System bus">system bus</a> architecture of <a href="/wiki/AMD" title="AMD">AMD</a> <a href="/wiki/Central_processing_unit" title="Central processing unit">central processing units</a> (CPUs) from <a href="/wiki/Athlon_64" title="Athlon 64">Athlon 64</a> through <a href="/wiki/AMD_FX" title="AMD FX">AMD FX</a> and the associated <a href="/wiki/Motherboard" title="Motherboard">motherboard</a> chipsets. HyperTransport has also been used by <a href="/wiki/IBM" title="IBM">IBM</a> and <a href="/wiki/Apple_Inc." title="Apple Inc.">Apple</a> for the <a href="/wiki/Power_Mac_G5" title="Power Mac G5">Power Mac G5</a> machines, as well as a number of modern <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> systems. </p><p>The current specification HTX 3.1 remained competitive for 2014 high-speed (2666 and 3200 <a href="/wiki/Megatransfer" class="mw-redirect" title="Megatransfer">MT</a>/s or about 10.4 GB/s and 12.8 GB/s) <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a> RAM and slower (around 1 GB/s <a rel="nofollow" class="external autonumber" href="http://www.extremetech.com/computing/175283-sandisk-announces-ulltra-dimms-terabytes-of-low-latency-flash-storage-directly-off-the-ram-channel">[1]</a> similar to high end <a href="/wiki/Solid-state_drive#Standard_card_form_factors" title="Solid-state drive">PCIe SSDs</a> <a href="/wiki/ULLtraDIMM" title="ULLtraDIMM">ULLtraDIMM</a> flash RAM) technology<sup class="noprint Inline-Template" style="margin-left:0.1em; white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify"><span title="The text near this tag may need clarification or removal of jargon. (June 2015)">clarification needed</span></a></i>]</sup>—a wider range of RAM speeds on a common CPU bus than any Intel <a href="/wiki/Front-side_bus" title="Front-side bus">front-side bus</a>. Intel technologies require each speed range of RAM to have its own interface, resulting in a more complex motherboard layout but with fewer bottlenecks. HTX 3.1 at 26 GB/s can serve as a unified bus for as many as four DDR4 sticks running at the fastest proposed speeds. Beyond that DDR4 RAM may require two or more HTX 3.1 buses diminishing its value as unified transport. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=1" title="Edit section: Overview"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Links_and_rates">Links and rates</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=2" title="Edit section: Links and rates"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>HyperTransport comes in four versions—1.x, 2.0, 3.0, and 3.1—which run from 200<span class="nowrap"> </span><a href="/wiki/MHz" class="mw-redirect" title="MHz">MHz</a> to 3.2 GHz. It is also a DDR or "<a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a>" connection, meaning it sends data on both the rising and falling edges of the <a href="/wiki/Clock_signal" title="Clock signal">clock signal</a>. This allows for a maximum data rate of 6400 MT/s when running at 3.2 GHz. The operating frequency is autonegotiated with the motherboard chipset (North Bridge) in current computing. </p><p>HyperTransport supports an autonegotiated bit width, ranging from 2 to 32 bits per link; there are two unidirectional links per HyperTransport bus. With the advent of version 3.1, using full <a href="/wiki/32-bit" class="mw-redirect" title="32-bit">32-bit</a> links and utilizing the full HyperTransport 3.1 specification's operating frequency, the theoretical transfer rate is 25.6 <a href="/wiki/Gigabyte" title="Gigabyte">GB</a>/s (3.2 GHz × 2 transfers per clock cycle × 32 bits per link) per direction, or 51.2 GB/s aggregated throughput, making it faster than most existing bus standard for PC workstations and servers as well as making it faster than most bus standards for high-performance computing and networking. </p><p>Links of various widths can be mixed together in a single system configuration as in one <a href="/wiki/16-bit" class="mw-redirect" title="16-bit">16-bit</a> link to another CPU and one <a href="/wiki/8-bit" class="mw-redirect" title="8-bit">8-bit</a> link to a peripheral device, which allows for a wider interconnect between <a href="/wiki/CPU" class="mw-redirect" title="CPU">CPUs</a>, and a lower bandwidth interconnect to <a href="/wiki/Peripheral" title="Peripheral">peripherals</a> as appropriate. It also supports link splitting, where a single 16-bit link can be divided into two 8-bit links. The technology also typically has lower latency than other solutions due to its lower overhead. </p><p>Electrically, HyperTransport is similar to <a href="/wiki/Low-voltage_differential_signaling" title="Low-voltage differential signaling">low-voltage differential signaling</a> (LVDS) operating at 1.2 V.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> HyperTransport 2.0 added post-cursor transmitter <a href="/wiki/Deemphasis" class="mw-redirect" title="Deemphasis">deemphasis</a>. HyperTransport 3.0 added scrambling and receiver phase alignment as well as optional transmitter precursor deemphasis. </p> <div class="mw-heading mw-heading3"><h3 id="Packet-oriented">Packet-oriented</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=3" title="Edit section: Packet-oriented"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>HyperTransport is <a href="/wiki/Packet_(information_technology)" class="mw-redirect" title="Packet (information technology)">packet</a>-based, where each packet consists of a set of <a href="/wiki/32-bit" class="mw-redirect" title="32-bit">32-bit</a> words, regardless of the physical width of the link. The first word in a packet always contains a command field. Many packets contain a 40-bit address. An additional 32-bit control packet is prepended when 64-bit addressing is required. The data payload is sent after the control packet. Transfers are always padded to a multiple of 32 bits, regardless of their actual length. </p><p>HyperTransport packets enter the interconnect in segments known as bit times. The number of bit times required depends on the link width. HyperTransport also supports system management messaging, signaling interrupts, issuing probes to adjacent devices or processors, <a href="/wiki/I/O" class="mw-redirect" title="I/O">I/O</a> transactions, and general data transactions. There are two kinds of write commands supported: posted and non-posted. Posted writes do not require a response from the target. This is usually used for high bandwidth devices such as <a href="/wiki/Uniform_memory_access" title="Uniform memory access">uniform memory access</a> traffic or <a href="/wiki/Direct_memory_access" title="Direct memory access">direct memory access</a> transfers. Non-posted writes require a response from the receiver in the form of a "target done" response. Reads also require a response, containing the read data. HyperTransport supports the PCI consumer/producer ordering model. </p> <div class="mw-heading mw-heading3"><h3 id="Power-managed">Power-managed</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=4" title="Edit section: Power-managed"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>HyperTransport also facilitates <a href="/wiki/Power_management" title="Power management">power management</a> as it is compliant with the <a href="/wiki/Advanced_Configuration_and_Power_Interface" class="mw-redirect" title="Advanced Configuration and Power Interface">Advanced Configuration and Power Interface</a> specification. This means that changes in processor sleep states (C states) can signal changes in device states (D states), e.g. powering off disks when the CPU goes to sleep. HyperTransport 3.0 added further capabilities to allow a centralized power management controller to implement power management policies. </p> <div class="mw-heading mw-heading2"><h2 id="Applications">Applications</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=5" title="Edit section: Applications"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Front-side_bus_replacement">Front-side bus replacement</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=6" title="Edit section: Front-side bus replacement"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The primary use for HyperTransport is to replace the Intel-defined <a href="/wiki/Front-side_bus" title="Front-side bus">front-side bus</a>, which is different for every type of Intel processor. For instance, a <a href="/wiki/Pentium_compatible_processor" class="mw-redirect" title="Pentium compatible processor">Pentium</a> cannot be plugged into a <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> bus directly, but must first go through an adapter to expand the system. The proprietary front-side bus must connect through adapters for the various standard buses, like <a href="/wiki/Accelerated_Graphics_Port" title="Accelerated Graphics Port">AGP</a> or PCI Express. These are typically included in the respective controller functions, namely the <i><a href="/wiki/Northbridge_(computing)" title="Northbridge (computing)">northbridge</a></i> and <i><a href="/wiki/Southbridge_(computing)" title="Southbridge (computing)">southbridge</a></i>. </p><p>In contrast, HyperTransport is an open specification, published by a multi-company consortium. A single HyperTransport adapter chip will work with a wide spectrum of HyperTransport enabled microprocessors. </p><p><a href="/wiki/AMD" title="AMD">AMD</a> used HyperTransport to replace the <a href="/wiki/Front-side_bus" title="Front-side bus">front-side bus</a> in their <a href="/wiki/Opteron" title="Opteron">Opteron</a>, <a href="/wiki/Athlon_64" title="Athlon 64">Athlon 64</a>, <a href="/wiki/Athlon_II" title="Athlon II">Athlon II</a>, <a href="/wiki/Sempron_64" class="mw-redirect" title="Sempron 64">Sempron 64</a>, <a href="/wiki/Turion_64" class="mw-redirect" title="Turion 64">Turion 64</a>, <a href="/wiki/Phenom_(processor)" class="mw-redirect" title="Phenom (processor)">Phenom</a>, <a href="/wiki/Phenom_II" title="Phenom II">Phenom II</a> and <a href="/wiki/Bulldozer_(microarchitecture)" title="Bulldozer (microarchitecture)">FX</a> families of microprocessors. </p> <div class="mw-heading mw-heading3"><h3 id="Multiprocessor_interconnect">Multiprocessor interconnect</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=7" title="Edit section: Multiprocessor interconnect"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Another use for HyperTransport is as an interconnect for <a href="/wiki/Non-Uniform_Memory_Access" class="mw-redirect" title="Non-Uniform Memory Access">NUMA</a> <a href="/wiki/Multiprocessor" class="mw-redirect" title="Multiprocessor">multiprocessor</a> computers. AMD used HyperTransport with a proprietary <a href="/wiki/Cache_coherency" class="mw-redirect" title="Cache coherency">cache coherency</a> extension as part of their Direct Connect Architecture in their <a href="/wiki/Opteron" title="Opteron">Opteron</a> and <a href="/wiki/Athlon_64_FX" class="mw-redirect" title="Athlon 64 FX">Athlon 64 FX</a> (<a href="/wiki/AMD_Quad_FX_platform" title="AMD Quad FX platform">Dual Socket Direct Connect (DSDC) Architecture</a>) line of processors. <a href="#Infinity_Fabric">Infinity Fabric</a> used with the <a href="/wiki/EPYC" class="mw-redirect" title="EPYC">EPYC</a> server CPUs is a superset of HyperTransport. The <a href="/wiki/HORUS_interconnect" class="mw-redirect" title="HORUS interconnect">HORUS interconnect</a> from <a href="/wiki/Newisys" title="Newisys">Newisys</a> extends this concept to larger clusters. The Aqua device from 3Leaf Systems virtualizes and interconnects CPUs, memory, and I/O. </p> <div class="mw-heading mw-heading3"><h3 id="Router_or_switch_bus_replacement">Router or switch bus replacement</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=8" title="Edit section: Router or switch bus replacement"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>HyperTransport can also be used as a bus in <a href="/wiki/Router_(computing)" title="Router (computing)">routers</a> and <a href="/wiki/Network_switch" title="Network switch">switches</a>. Routers and switches have multiple network interfaces, and must forward data between these ports as fast as possible. For example, a four-port, 1000 <a href="/wiki/Mbit" class="mw-redirect" title="Mbit">Mbit</a>/s <a href="/wiki/Ethernet" title="Ethernet">Ethernet</a> router needs a maximum 8000 Mbit/s of internal bandwidth (1000 Mbit/s × 4 ports × 2 directions)—HyperTransport greatly exceeds the bandwidth this application requires. However a 4 + 1 port 10 Gb router would require 100 Gbit/s of internal bandwidth. Add to that 802.11ac 8 antennas and the WiGig 60 GHz standard (802.11ad) and HyperTransport becomes more feasible (with anywhere between 20 and 24 lanes used for the needed bandwidth). </p> <div class="mw-heading mw-heading3"><h3 id="Co-processor_interconnect">Co-processor interconnect</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=9" title="Edit section: Co-processor interconnect"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The issue of latency and bandwidth between CPUs and co-processors has usually been the major stumbling block to their practical implementation. Co-processors such as <a href="/wiki/FPGAs" class="mw-redirect" title="FPGAs">FPGAs</a> have appeared that can access the HyperTransport bus and become integrated on the motherboard. Current generation FPGAs from both main manufacturers (<a href="/wiki/Altera" title="Altera">Altera</a> and <a href="/wiki/Xilinx" title="Xilinx">Xilinx</a>) directly support the HyperTransport interface, and have <a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">IP Cores</a> available. Companies such as XtremeData, Inc. and DRC take these FPGAs (Xilinx in DRC's case) and create a module that allows FPGAs to plug directly into the Opteron socket. </p><p>AMD started an initiative named <a href="/wiki/Torrenza" title="Torrenza">Torrenza</a> on September 21, 2006, to further promote the usage of HyperTransport for plug-in cards and <a href="/wiki/Coprocessors" class="mw-redirect" title="Coprocessors">coprocessors</a>. This initiative opened their "Socket F" to plug-in boards such as those from XtremeData and DRC. </p> <div class="mw-heading mw-heading3"><h3 id="Add-on_card_connector_(HTX_and_HTX3)"><span id="Add-on_card_connector_.28HTX_and_HTX3.29"></span>Add-on card connector (HTX and HTX3)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=10" title="Edit section: Add-on card connector (HTX and HTX3)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:HyperTransport16_pcie8riser_pcie16.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1e/HyperTransport16_pcie8riser_pcie16.jpg/220px-HyperTransport16_pcie8riser_pcie16.jpg" decoding="async" width="220" height="69" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1e/HyperTransport16_pcie8riser_pcie16.jpg/330px-HyperTransport16_pcie8riser_pcie16.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1e/HyperTransport16_pcie8riser_pcie16.jpg/440px-HyperTransport16_pcie8riser_pcie16.jpg 2x" data-file-width="1024" data-file-height="321" /></a><figcaption>Connectors from top to bottom: HTX, PCI-Express for riser card, PCI-Express</figcaption></figure> <p>A connector specification that allows a slot-based peripheral to have direct connection to a microprocessor using a HyperTransport interface was released by the HyperTransport Consortium. It is known as <b>H</b>yper<b>T</b>ransport e<b>X</b>pansion (<b>HTX</b>). Using a reversed instance of the same mechanical connector as a 16-lane <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> slot (plus an x1 connector for power pins), HTX allows development of plug-in cards that support direct access to a CPU and <a href="/wiki/Direct_memory_access" title="Direct memory access">DMA</a> to the system <a href="/wiki/RAM" class="mw-redirect" title="RAM">RAM</a>. The initial card for this slot was the <a href="/wiki/QLogic" title="QLogic">QLogic</a> InfiniPath InfiniBand HCA. IBM and <a href="/wiki/Hewlett-Packard" title="Hewlett-Packard">HP</a>, among others, have released HTX compliant systems. </p><p>The original HTX standard is limited to 16<span class="nowrap"> </span>bits and 800<span class="nowrap"> </span>MHz.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p><p>In August 2008, the HyperTransport Consortium released HTX3, which extends the clock rate of HTX to 2.6 GHz (5.2 GT/s, 10.7 GTi, 5.2 real GHz data rate, 3 MT/s edit rate) and retains backwards compatibility.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Testing">Testing</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=11" title="Edit section: Testing"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The "DUT" test connector<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> is defined to enable standardized functional test system interconnection. </p> <div class="mw-heading mw-heading2"><h2 id="Implementations">Implementations</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=12" title="Edit section: Implementations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/AMD" title="AMD">AMD</a> <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a> and Direct Connect Architecture based CPUs</li> <li><a href="/wiki/AMD" title="AMD">AMD</a> chipsets <ul><li>AMD-8000 series</li> <li><a href="/wiki/AMD_580_chipset_series" title="AMD 580 chipset series">AMD 480 series</a></li> <li><a href="/wiki/AMD_580_chipset_series" title="AMD 580 chipset series">AMD 580 series</a></li> <li><a href="/wiki/AMD_690_chipset_series" title="AMD 690 chipset series">AMD 690 series</a></li> <li><a href="/wiki/AMD_700_chipset_series" title="AMD 700 chipset series">AMD 700 series</a></li> <li><a href="/wiki/AMD_800_chipset_series" title="AMD 800 chipset series">AMD 800 series</a></li> <li><a href="/wiki/AMD_900_chipset_series" title="AMD 900 chipset series">AMD 900 series</a></li></ul></li> <li><a href="/wiki/ATI_Technologies" title="ATI Technologies">ATI</a> chipsets <ul><li>ATI <a href="/wiki/Xpress_200" title="Xpress 200">Radeon Xpress 200</a> for AMD processor</li> <li>ATI <a href="/wiki/Xpress_3200" title="Xpress 3200">Radeon Xpress 3200</a> for AMD processor</li></ul></li> <li><a href="/wiki/Broadcom" title="Broadcom">Broadcom</a> (then <a href="/wiki/ServerWorks" title="ServerWorks">ServerWorks</a>) HyperTransport SystemI/O controllers <ul><li>HT-2000</li> <li>HT-2100</li></ul></li> <li><a href="/wiki/Cisco" title="Cisco">Cisco</a> QuantumFlow Processors</li> <li>ht_tunnel from <a href="/wiki/OpenCores" title="OpenCores">OpenCores</a> project (MPL licence)</li> <li><a href="/wiki/IBM" title="IBM">IBM</a> CPC925 and CPC945 (<a href="/wiki/PowerPC_G5#Northbridges" class="mw-redirect" title="PowerPC G5">PowerPC 970 northbridges</a>) chipsets</li> <li><a href="/wiki/Loongson" title="Loongson">Loongson</a>-3 <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> processor</li> <li><a href="/wiki/Nvidia" title="Nvidia">Nvidia</a> nForce chipsets <ul><li><a href="/wiki/NForce" title="NForce">nForce</a> and <a href="/wiki/NForce2" title="NForce2">nForce2</a> series (link between North and South Bridges)</li> <li>nForce Professional MCPs (Media and Communication Processor)</li> <li><a href="/wiki/NForce_3" class="mw-redirect" title="NForce 3">nForce 3</a> series</li> <li><a href="/wiki/NForce_4" class="mw-redirect" title="NForce 4">nForce 4</a> series</li> <li><a href="/wiki/NForce_500" title="NForce 500">nForce 500 series</a></li> <li><a href="/wiki/NForce_600" title="NForce 600">nForce 600 series</a></li> <li><a href="/wiki/NForce_700" title="NForce 700">nForce 700 series</a></li> <li><a href="/wiki/NForce_900" class="mw-redirect" title="NForce 900">nForce 900 series</a></li></ul></li> <li><a href="/wiki/PMC-Sierra" title="PMC-Sierra">PMC-Sierra</a> RM9000X2 <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> CPU</li> <li><a href="/wiki/Power_Mac_G5" title="Power Mac G5">Power Mac G5</a><sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Raza_Microelectronics_Inc" class="mw-redirect" title="Raza Microelectronics Inc">Raza</a> Thread Processors</li> <li>SiByte <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> CPUs from <a href="/wiki/Broadcom" title="Broadcom">Broadcom</a></li> <li><a href="/wiki/Transmeta" title="Transmeta">Transmeta</a> TM8000 Efficeon CPUs</li> <li><a href="/wiki/VIA_Technologies" title="VIA Technologies">VIA</a> chipsets K8 series</li></ul> <div class="mw-heading mw-heading2"><h2 id="Frequency_specifications">Frequency specifications</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=13" title="Edit section: Frequency specifications"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable" style="text-align:center; vetical-align:center;"> <tbody><tr> <th rowspan="2">HyperTransport<br />version </th> <th rowspan="2">Year </th> <th rowspan="2">Max. HT frequency </th> <th rowspan="2">Max. link width </th> <th colspan="3">Max. aggregate bandwidth (GB/s) </th></tr> <tr> <th>bi-directional </th> <th>16-bit unidirectional </th> <th>32-bit unidirectional* </th></tr> <tr> <th>1.0 </th> <td>2001 </td> <td>800 MHz </td> <td>32-bit </td> <td>12.8 </td> <td>3.2 </td> <td>6.4 </td></tr> <tr> <th>1.1 </th> <td>2002 </td> <td>800 MHz </td> <td>32-bit </td> <td>12.8 </td> <td>3.2 </td> <td>6.4 </td></tr> <tr> <th>2.0 </th> <td>2004 </td> <td>1.4 GHz </td> <td>32-bit </td> <td>22.4 </td> <td>5.6 </td> <td>11.2 </td></tr> <tr> <th>3.0 </th> <td>2006 </td> <td>2.6 GHz </td> <td>32-bit </td> <td>41.6 </td> <td>10.4 </td> <td>20.8 </td></tr> <tr> <th>3.1 </th> <td>2008 </td> <td>3.2 GHz </td> <td>32-bit </td> <td>51.2 </td> <td>12.8 </td> <td>25.6 </td></tr></tbody></table> <p>* AMD <a href="/wiki/Athlon_64" title="Athlon 64">Athlon 64</a>, Athlon 64 FX, <a href="/wiki/Athlon_64_X2" title="Athlon 64 X2">Athlon 64 X2</a>, Athlon X2, <a href="/wiki/Athlon_II" title="Athlon II">Athlon II</a>, Phenom, <a href="/wiki/Phenom_II" title="Phenom II">Phenom II</a>, <a href="/wiki/Sempron" title="Sempron">Sempron</a>, <a href="/wiki/AMD_Turion" title="AMD Turion">Turion</a> series and later use one 16-bit HyperTransport link. AMD Athlon 64 FX (<a href="/wiki/Socket_F" title="Socket F">1207</a>), <a href="/wiki/Opteron" title="Opteron">Opteron</a> use up to three 16-bit HyperTransport links. Common clock rates for these processor links are 800 MHz to 1 GHz (older single and multi socket systems on 754/939/940 links) and 1.6 GHz to 2.0 GHz (newer single socket systems on AM2+/AM3 links—most newer CPUs using 2.0<span class="nowrap"> </span>GHz). While HyperTransport itself is capable of 32-bit width links, that width is not currently utilized by any AMD processors. Some chipsets though do not even utilize the 16-bit width used by the processors. Those include the Nvidia <a href="/wiki/NForce3" title="NForce3">nForce3</a> 150, nForce3 Pro 150, and the <a href="/wiki/ULi" class="mw-redirect" title="ULi">ULi</a> M1689—which use a 16-bit HyperTransport downstream link but limit the HyperTransport upstream link to 8 bits. </p> <div class="mw-heading mw-heading2"><h2 id="Name">Name</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=14" title="Edit section: Name"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>There has been some marketing confusion<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (August 2023)">citation needed</span></a></i>]</sup> between the use of <b>HT</b> referring to <b>H</b>yper<b>T</b>ransport and the later use of <b>HT</b> to refer to <a href="/wiki/Intel" title="Intel">Intel</a>'s <a href="/wiki/Hyper-Threading" class="mw-redirect" title="Hyper-Threading">Hyper-Threading</a> feature on some <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a>-based and the newer Nehalem and Westmere-based <a href="/wiki/Intel_Core" title="Intel Core">Intel Core</a> microprocessors. Hyper-Threading is officially known as <b>H</b>yper-<b>T</b>hreading <b>T</b>echnology (<b>HTT</b>) or <b>HT Technology</b>. Because of this potential for confusion, the HyperTransport Consortium always uses the written-out form: "HyperTransport." </p> <div class="mw-heading mw-heading2"><h2 id="Infinity_Fabric">Infinity Fabric</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=15" title="Edit section: Infinity Fabric"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><b>Infinity Fabric</b> (<b>IF</b>) is a superset of HyperTransport announced by AMD in 2016 as an interconnect for its GPUs and CPUs. It is also usable as interchip interconnect for communication between CPUs and GPUs (for <a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous System Architecture</a>), an arrangement known as <b>Infinity Architecture</b>.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> The company said the Infinity Fabric would scale from 30<span class="nowrap"> </span>GB/s to 512<span class="nowrap"> </span>GB/s, and be used in the <a href="/wiki/Zen_(microarchitecture)" title="Zen (microarchitecture)">Zen</a>-based CPUs and <a href="/wiki/Graphics_Core_Next#Graphics_Core_Next_5" title="Graphics Core Next">Vega</a> GPUs which were subsequently released in 2017. </p><p>On Zen and <a href="/wiki/Zen%2B" title="Zen+">Zen+</a> CPUs, the "SDF" data interconnects are run at the same frequency as the DRAM memory clock (MEMCLK), a decision made to remove the latency caused by different clock speeds. As a result, using a faster RAM module makes the entire bus faster. The links are 32-bit wide, as in HT, but 8 transfers are done per cycle (128-bit packets) compared to the original 2. Electrical changes are made for higher power efficiency.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> On <a href="/wiki/Zen_2" title="Zen 2">Zen 2</a> and <a href="/wiki/Zen_3" title="Zen 3">Zen 3</a> CPUs, the IF bus is on a separate clock, either in a 1:1 or a 2:1 ratio to the DRAM clock. This avoids a limitation on desktop platforms where maximum DRAM speeds were in practice limited by the IF speed. The bus width has also been doubled.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> On <a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> and later CPUs, the IF bus is able to run at an asynchronous clock to the DRAM, to allow the higher clock speeds that DDR5 is capable of.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/UALink" title="UALink">UALink</a> will utilize Infinity Fabric as the primary shared memory protocol. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=16" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Elastic_interface_bus" class="mw-redirect" title="Elastic interface bus">Elastic interface bus</a></li> <li><a href="/wiki/Fibre_Channel" title="Fibre Channel">Fibre Channel</a></li> <li><a href="/wiki/Front-side_bus" title="Front-side bus">Front-side bus</a></li> <li><a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">Intel QuickPath Interconnect</a></li> <li><a href="/wiki/List_of_interface_bit_rates" title="List of interface bit rates">List of interface bit rates</a></li> <li><a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a></li> <li><a href="/wiki/RapidIO" title="RapidIO">RapidIO</a></li> <li><a href="/wiki/AGESA" title="AGESA">AGESA</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=HyperTransport&action=edit&section=17" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 32em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20061010070210/http://www.hypertransport.org/consortium/cons_pressrelease.cfm?RecordID=62">"API NetWorks Accelerates Use of HyperTransport Technology With Launch of Industry's First HyperTransport Technology-to-PCI Bridge Chip"</a>. <i>HyperTransport Consortium</i> (Press release). April 2, 2001. Archived from <a rel="nofollow" class="external text" href="http://www.hypertransport.org/consortium/cons_pressrelease.cfm?RecordID=62">the original</a> on October 10, 2006.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=API+NetWorks+Accelerates+Use+of+HyperTransport+Technology+With+Launch+of+Industry%27s+First+HyperTransport+Technology-to-PCI+Bridge+Chip&rft.date=2001-04-02&rft_id=http%3A%2F%2Fwww.hypertransport.org%2Fconsortium%2Fcons_pressrelease.cfm%3FRecordID%3D62&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHyperTransport" class="Z3988"></span></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110716171022/http://www.hypertransport.org/docs/wp/HT_Overview.pdf">"Overview"</a> <span class="cs1-format">(PDF)</span>. <i>HyperTransport Consortium</i>. Archived from <a rel="nofollow" class="external text" href="http://www.hypertransport.org/docs/wp/HT_Overview.pdf">the original</a> <span class="cs1-format">(PDF)</span> on July 16, 2011.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=HyperTransport+Consortium&rft.atitle=Overview&rft_id=http%3A%2F%2Fwww.hypertransport.org%2Fdocs%2Fwp%2FHT_Overview.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHyperTransport" class="Z3988"></span></span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFEmbersonHolden2007" class="citation web cs1">Emberson, David; Holden, Brian (December 12, 2007). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120308085021/http://www.hypertransport.org/docs/uploads/HTX_Specifications.pdf">"HTX specification"</a> <span class="cs1-format">(PDF)</span>. <i>HyperTransport Consortium</i>. p. 4. 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Retrieved <span class="nowrap">January 30,</span> 2008</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=HyperTransport+Consortium&rft.atitle=HTX+specification&rft.pages=4&rft.date=2007-12-12&rft.aulast=Emberson&rft.aufirst=David&rft.au=Holden%2C+Brian&rft_id=http%3A%2F%2Fwww.hypertransport.org%2Fdocs%2Fuploads%2FHTX_Specifications.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHyperTransport" class="Z3988"></span></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFEmberson2008" class="citation web cs1">Emberson, David (June 25, 2008). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120308085016/http://www.hypertransport.org/docs/uploads/HTX3_Specifications.pdf">"HTX3 specification"</a> <span class="cs1-format">(PDF)</span>. <i>HyperTransport Consortium</i>. p. 4. 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class="external text" href="https://web.archive.org/web/20080822010544/http://www.hypertransport.org/default.cfm?page=HyperTransportSpecifications"><i>HyperTransport Consortium</i></a> (home), archived from <a rel="nofollow" class="external text" href="http://www.hypertransport.org/">the original</a> on August 22, 2008<span class="reference-accessdate">, retrieved <span class="nowrap">November 2,</span> 2002</span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=HyperTransport+Consortium&rft_id=http%3A%2F%2Fwww.hypertransport.org%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHyperTransport" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="http://www.hypertransport.org/default.cfm?page=TechnologyHyperTransportOverview">"Technology"</a>, <i>HyperTransport</i></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=HyperTransport&rft.atitle=Technology&rft_id=http%3A%2F%2Fwww.hypertransport.org%2Fdefault.cfm%3Fpage%3DTechnologyHyperTransportOverview&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHyperTransport" class="Z3988"></span><sup class="noprint Inline-Template"><span style="white-space: nowrap;">[<i><a href="/wiki/Wikipedia:Link_rot" title="Wikipedia:Link rot"><span title=" Dead link tagged April 2017">permanent dead link</span></a></i><span style="visibility:hidden; color:transparent; padding-left:2px">‍</span>]</span></sup>.</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20080822010544/http://www.hypertransport.org/default.cfm?page=HyperTransportSpecifications">"Technical Specifications"</a>, <i>HyperTransport</i>, archived from <a rel="nofollow" class="external text" href="http://www.hypertransport.org/default.cfm?page=HyperTransportSpecifications">the original</a> on August 22, 2008</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=HyperTransport&rft.atitle=Technical+Specifications&rft_id=http%3A%2F%2Fwww.hypertransport.org%2Fdefault.cfm%3Fpage%3DHyperTransportSpecifications&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHyperTransport" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2 cs1-prop-foreign-lang-source"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20081029020858/http://www.htce.uni-hd.de/"><i>Center of Excellence for HyperTransport</i></a> (in German), Uni HD, archived from <a rel="nofollow" class="external text" href="http://htce.uni-hd.de/">the original</a> on October 29, 2008<span class="reference-accessdate">, retrieved <span class="nowrap">September 4,</span> 2008</span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Center+of+Excellence+for+HyperTransport&rft.pub=Uni+HD&rft_id=http%3A%2F%2Fhtce.uni-hd.de%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHyperTransport" class="Z3988"></span></li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output .hlist dt::after{content:": "}.mw-parser-output .hlist dd::after,.mw-parser-output .hlist li::after{content:" · ";font-weight:bold}.mw-parser-output .hlist dd:last-child::after,.mw-parser-output .hlist dt:last-child::after,.mw-parser-output .hlist li:last-child::after{content:none}.mw-parser-output .hlist dd dd:first-child::before,.mw-parser-output .hlist dd dt:first-child::before,.mw-parser-output .hlist dd li:first-child::before,.mw-parser-output .hlist dt dd:first-child::before,.mw-parser-output .hlist dt dt:first-child::before,.mw-parser-output .hlist dt li:first-child::before,.mw-parser-output .hlist li dd:first-child::before,.mw-parser-output .hlist li dt:first-child::before,.mw-parser-output .hlist li li:first-child::before{content:" (";font-weight:normal}.mw-parser-output .hlist dd dd:last-child::after,.mw-parser-output .hlist dd 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.navbox-abovebelow,.mw-parser-output .navbox-group,.mw-parser-output .navbox-subgroup .navbox-title{background-color:#ddf}.mw-parser-output .navbox-subgroup .navbox-group,.mw-parser-output .navbox-subgroup .navbox-abovebelow{background-color:#e6e6ff}.mw-parser-output .navbox-even{background-color:#f7f7f7}.mw-parser-output .navbox-odd{background-color:transparent}.mw-parser-output .navbox .hlist td dl,.mw-parser-output .navbox .hlist td ol,.mw-parser-output .navbox .hlist td ul,.mw-parser-output .navbox td.hlist dl,.mw-parser-output .navbox td.hlist ol,.mw-parser-output .navbox td.hlist ul{padding:0.125em 0}.mw-parser-output .navbox .navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="Technical_and_de_facto_standards_for_wired_computer_buses" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar 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title="Special:EditPage/Template:Computer bus"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Technical_and_de_facto_standards_for_wired_computer_buses" style="font-size:114%;margin:0 4em"><a href="/wiki/Technical_standard" title="Technical standard">Technical</a> and <a href="/wiki/De_facto_standard" title="De facto standard"><i>de facto</i> standards</a> for <a href="/wiki/Wired_communication" title="Wired communication">wired</a> <a href="/wiki/Bus_(computing)" title="Bus (computing)">computer buses</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">General</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_bus" title="System bus">System bus</a></li> <li><a href="/wiki/Front-side_bus" title="Front-side bus">Front-side bus</a></li> <li><a href="/wiki/Back-side_bus" title="Back-side bus">Back-side bus</a></li> <li><a href="/wiki/Daisy_chain_(electrical_engineering)" title="Daisy chain (electrical engineering)">Daisy chain</a></li> <li><a href="/wiki/Control_bus" title="Control bus">Control bus</a></li> <li><a href="/wiki/Address_bus" class="mw-redirect" title="Address bus">Address bus</a></li> <li><a href="/wiki/Bus_contention" title="Bus contention">Bus contention</a></li> <li><a href="/wiki/Bus_mastering" title="Bus mastering">Bus mastering</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a></li> <li><a href="/wiki/Plug_and_play" title="Plug and play">Plug and play</a></li> <li><a href="/wiki/List_of_interface_bit_rates#Computer_buses" title="List of interface bit rates">List of bus bandwidths</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Standards</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/SS-50_bus" title="SS-50 bus">SS-50 bus</a></li> <li><a href="/wiki/S-100_bus" title="S-100 bus">S-100 bus</a></li> <li><a href="/wiki/Multibus" title="Multibus">Multibus</a></li> <li><a href="/wiki/Unibus" title="Unibus">Unibus</a></li> <li><a href="/wiki/VAXBI_bus" title="VAXBI bus">VAXBI</a></li> <li><a href="/wiki/MBus_(SPARC)" title="MBus (SPARC)">MBus</a></li> <li><a href="/wiki/STD_Bus" title="STD Bus">STD Bus</a></li> <li><a href="/wiki/System_Management_Bus" title="System Management Bus">SMBus</a></li> <li><a href="/wiki/Q-Bus" title="Q-Bus">Q-Bus</a></li> <li><a href="/wiki/Europe_Card_Bus" title="Europe Card Bus">Europe Card Bus</a></li> <li><a href="/wiki/Industry_Standard_Architecture" title="Industry Standard Architecture">ISA</a></li> <li><a href="/wiki/STEbus" title="STEbus">STEbus</a></li> <li><a href="/wiki/Amiga_Zorro_II" title="Amiga Zorro II">Zorro II</a></li> <li><a href="/wiki/Amiga_Zorro_III" title="Amiga Zorro III">Zorro III</a></li> <li><a href="/wiki/Computer_Automated_Measurement_and_Control" title="Computer Automated Measurement and Control">CAMAC</a></li> <li><a href="/wiki/FASTBUS" title="FASTBUS">FASTBUS</a></li> <li><a href="/wiki/Low_Pin_Count" title="Low Pin Count">LPC</a></li> <li><a href="/wiki/HP_Precision_Bus" title="HP Precision Bus">HP Precision Bus</a></li> <li><a href="/wiki/Extended_Industry_Standard_Architecture" title="Extended Industry Standard Architecture">EISA</a></li> <li><a href="/wiki/VMEbus" title="VMEbus">VME</a></li> <li><a href="/wiki/VME_eXtensions_for_Instrumentation" title="VME eXtensions for Instrumentation">VXI</a></li> <li><a href="/wiki/VXS" title="VXS">VXS</a></li> <li><a href="/wiki/VPX" title="VPX">VPX</a></li> <li><a href="/wiki/NuBus" title="NuBus">NuBus</a></li> <li><a href="/wiki/TURBOchannel" title="TURBOchannel">TURBOchannel</a></li> <li><a href="/wiki/Micro_Channel_architecture" title="Micro Channel architecture">MCA</a></li> <li><a href="/wiki/SBus" title="SBus">SBus</a></li> <li><a href="/wiki/VESA_Local_Bus" title="VESA Local Bus">VLB</a></li> <li><a href="/wiki/GSC_bus" title="GSC bus">HP GSC bus</a></li> <li><a href="/wiki/InfiniBand" title="InfiniBand">InfiniBand</a></li> <li><a href="/wiki/Ethernet" title="Ethernet">Ethernet</a></li> <li><a href="/wiki/Ultra_Port_Architecture" title="Ultra Port Architecture">UPA</a></li> <li><a href="/wiki/Peripheral_Component_Interconnect" title="Peripheral Component Interconnect">PCI</a></li> <li><a href="/wiki/PCI-X" title="PCI-X">PCI Extended (PCI-X)</a></li> <li><a href="/wiki/PCI_eXtensions_for_Instrumentation" title="PCI eXtensions for Instrumentation">PXI</a></li> <li><a href="/wiki/PCI_Express" title="PCI Express">PCI Express (PCIe)</a></li> <li><a href="/wiki/Accelerated_Graphics_Port" title="Accelerated Graphics Port">AGP</a></li> <li><a href="/wiki/Compute_Express_Link" title="Compute Express Link">Compute Express Link (CXL)</a></li> <li><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface (DMI)</a></li> <li><a href="/wiki/RapidIO" title="RapidIO">RapidIO</a></li> <li><a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">Intel QuickPath Interconnect</a></li> <li><a href="/wiki/NVLink" title="NVLink">NVLink</a></li> <li><a class="mw-selflink selflink">HyperTransport</a> <ul><li><a href="/wiki/Infinity_Fabric" class="mw-redirect" title="Infinity Fabric">Infinity Fabric</a></li></ul></li> <li><a href="/wiki/Intel_Ultra_Path_Interconnect" title="Intel Ultra Path Interconnect">Intel Ultra Path Interconnect</a></li> <li><a href="/wiki/Coherent_Accelerator_Processor_Interface" title="Coherent Accelerator Processor Interface">Coherent Accelerator Processor Interface (CAPI)</a></li> <li><a href="/wiki/SpaceWire" title="SpaceWire">SpaceWire</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Storage</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ST-506/ST-412" title="ST-506/ST-412">ST-506</a></li> <li><a href="/wiki/Enhanced_Small_Disk_Interface" title="Enhanced Small Disk Interface">ESDI</a></li> <li><a href="/wiki/Intelligent_Peripheral_Interface" title="Intelligent Peripheral Interface">IPI</a></li> <li><a href="/wiki/Storage_Module_Device" title="Storage Module Device">SMD</a></li> <li><a href="/wiki/Parallel_ATA" title="Parallel ATA">Parallel ATA (PATA)</a></li> <li><a href="/wiki/Bus_and_Tag" title="Bus and Tag">Bus and Tag</a></li> <li><a href="/wiki/Digital_Storage_Systems_Interconnect" title="Digital Storage Systems Interconnect">DSSI</a></li> <li><a href="/wiki/HIPPI" title="HIPPI">HIPPI</a></li> <li><a href="/wiki/SATA" title="SATA">Serial ATA (SATA)</a></li> <li><a href="/wiki/SCSI" title="SCSI">SCSI</a> <ul><li><a href="/wiki/Parallel_SCSI" title="Parallel SCSI">Parallel</a></li> <li><a href="/wiki/Serial_Attached_SCSI" title="Serial Attached SCSI">SAS</a></li></ul></li> <li><a href="/wiki/ESCON" title="ESCON">ESCON</a></li> <li><a href="/wiki/Fibre_Channel" title="Fibre Channel">Fibre Channel</a></li> <li><a href="/wiki/Serial_Storage_Architecture" title="Serial Storage Architecture">SSA</a></li> <li><a href="/wiki/SATA_Express" title="SATA Express">SATAe</a></li> <li>PCI Express (via <a href="/wiki/Advanced_Host_Controller_Interface" title="Advanced Host Controller Interface">AHCI</a> or <a href="/wiki/NVM_Express" title="NVM Express">NVMe</a> logical device interface)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Peripheral</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Apple_Desktop_Bus" title="Apple Desktop Bus">Apple Desktop Bus</a></li> <li><a href="/wiki/Atari_SIO" title="Atari SIO">Atari SIO</a></li> <li><a href="/wiki/Digital_Control_Bus" title="Digital Control Bus">DCB</a></li> <li><a href="/wiki/Commodore_bus" title="Commodore bus">Commodore bus</a></li> <li><a href="/wiki/HP-IL" title="HP-IL">HP-IL</a></li> <li><a href="/wiki/HIL_bus" title="HIL bus">HIL</a></li> <li><a href="/wiki/MIDI" title="MIDI">MIDI</a></li> <li><a href="/wiki/RS-232" title="RS-232">RS-232</a></li> <li><a href="/wiki/RS-422" title="RS-422">RS-422</a></li> <li><a href="/wiki/RS-423" title="RS-423">RS-423</a></li> <li><a href="/wiki/RS-485" title="RS-485">RS-485</a></li> <li><a href="/wiki/Lightning_(connector)" title="Lightning (connector)">Lightning</a></li> <li><a href="/wiki/DMX512#DMX512-A" title="DMX512">DMX512-A</a></li> <li><a href="/wiki/IEEE-488" class="mw-redirect" title="IEEE-488">IEEE-488 (GPIB)</a></li> <li><a href="/wiki/IEEE_1284" title="IEEE 1284">IEEE-1284 (parallel port)</a></li> <li><a href="/wiki/IEEE_1394" title="IEEE 1394">IEEE-1394 (FireWire)</a></li> <li><a href="/wiki/UNI/O" title="UNI/O">UNI/O</a></li> <li><a href="/wiki/1-Wire" title="1-Wire">1-Wire</a></li> <li><a href="/wiki/I%C2%B2C" title="I²C">I²C</a> (<a href="/wiki/ACCESS.bus" title="ACCESS.bus">ACCESS.bus</a>, <a href="/wiki/Power_Management_Bus" title="Power Management Bus">PMBus</a>, <a href="/wiki/System_Management_Bus" title="System Management Bus">SMBus</a>)</li> <li><a href="/wiki/I3C_(bus)" title="I3C (bus)">I3C</a></li> <li><a href="/wiki/Serial_Peripheral_Interface" title="Serial Peripheral Interface">SPI</a></li> <li><a href="/wiki/IEC_61030" title="IEC 61030">D²B</a></li> <li><a href="/wiki/Parallel_SCSI" title="Parallel SCSI">Parallel SCSI</a></li> <li><a href="/wiki/Profibus" title="Profibus">Profibus</a></li> <li><a href="/wiki/USB" title="USB">USB</a></li> <li><a href="/wiki/Camera_Link" title="Camera Link">Camera Link</a></li> <li><a href="/wiki/PCI_Express#PCI_Express_External_Cabling" title="PCI Express">External PCIe</a></li> <li><a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Audio</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ADAT_Lightpipe" title="ADAT Lightpipe">ADAT Lightpipe</a></li> <li><a href="/wiki/AES3" title="AES3">AES3</a></li> <li><a href="/wiki/Intel_High_Definition_Audio" title="Intel High Definition Audio">Intel HD Audio</a></li> <li><a href="/wiki/I%C2%B2S" title="I²S">I²S</a></li> <li><a href="/wiki/MADI" title="MADI">MADI</a></li> <li><a href="/wiki/McASP" title="McASP">McASP</a></li> <li><a href="/wiki/S/PDIF" title="S/PDIF">S/PDIF</a></li> <li><a href="/wiki/TOSLINK" title="TOSLINK">TOSLINK</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Portable</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/PC_Card" title="PC Card">PC Card</a></li> <li><a href="/wiki/ExpressCard" title="ExpressCard">ExpressCard</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Embedded</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multidrop_bus" title="Multidrop bus">Multidrop bus</a></li> <li><a href="/wiki/CoreConnect" title="CoreConnect">CoreConnect</a></li> <li><a href="/wiki/Advanced_Microcontroller_Bus_Architecture" title="Advanced Microcontroller Bus Architecture">AMBA</a> (<a href="/wiki/Advanced_eXtensible_Interface" title="Advanced eXtensible Interface">AXI</a>)</li> <li><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a></li> <li><a href="/wiki/SLIMbus" title="SLIMbus">SLIMbus</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div><small>Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.</small><br /><span class="noviewer" typeof="mw:File"><span title="Category"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/16px-Symbol_category_class.svg.png" decoding="async" width="16" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/23px-Symbol_category_class.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/31px-Symbol_category_class.svg.png 2x" data-file-width="180" data-file-height="185" /></span></span> <a href="/wiki/Category:Computer_buses" title="Category:Computer buses">Category</a></div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" 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