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subsection</span> </button> <ul id="toc-AArch64_Execution_state-sublist" class="vector-toc-list"> <li id="toc-Naming_conventions" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Naming_conventions"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>Naming conventions</span> </div> </a> <ul id="toc-Naming_conventions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-AArch64_features" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#AArch64_features"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2</span> <span>AArch64 features</span> </div> </a> <ul id="toc-AArch64_features-sublist" class="vector-toc-list"> <li id="toc-Instruction_formats" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Instruction_formats"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2.1</span> <span>Instruction formats</span> </div> </a> <ul id="toc-Instruction_formats-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-ARM-A_(application_architecture)" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#ARM-A_(application_architecture)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>ARM-A (application architecture)</span> </div> </a> <button aria-controls="toc-ARM-A_(application_architecture)-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle ARM-A (application architecture) subsection</span> </button> <ul id="toc-ARM-A_(application_architecture)-sublist" class="vector-toc-list"> <li id="toc-ARMv8.1-A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ARMv8.1-A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>ARMv8.1-A</span> </div> </a> <ul id="toc-ARMv8.1-A-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-ARMv8.2-A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ARMv8.2-A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>ARMv8.2-A</span> </div> </a> <ul id="toc-ARMv8.2-A-sublist" class="vector-toc-list"> <li id="toc-Scalable_Vector_Extension_(SVE)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Scalable_Vector_Extension_(SVE)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.1</span> <span>Scalable Vector Extension (SVE)</span> </div> </a> <ul id="toc-Scalable_Vector_Extension_(SVE)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-ARMv8.3-A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ARMv8.3-A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>ARMv8.3-A</span> </div> </a> <ul id="toc-ARMv8.3-A-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-ARMv8.4-A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ARMv8.4-A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>ARMv8.4-A</span> </div> </a> <ul id="toc-ARMv8.4-A-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-ARMv8.5-A_and_ARMv9.0-A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ARMv8.5-A_and_ARMv9.0-A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.5</span> <span>ARMv8.5-A and ARMv9.0-A</span> </div> </a> <ul id="toc-ARMv8.5-A_and_ARMv9.0-A-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-ARMv8.6-A_and_ARMv9.1-A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ARMv8.6-A_and_ARMv9.1-A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.6</span> <span>ARMv8.6-A and ARMv9.1-A</span> </div> </a> <ul id="toc-ARMv8.6-A_and_ARMv9.1-A-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-ARMv8.7-A_and_ARMv9.2-A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ARMv8.7-A_and_ARMv9.2-A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.7</span> <span>ARMv8.7-A and ARMv9.2-A</span> </div> </a> <ul id="toc-ARMv8.7-A_and_ARMv9.2-A-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-ARMv8.8-A_and_ARMv9.3-A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ARMv8.8-A_and_ARMv9.3-A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.8</span> <span>ARMv8.8-A and ARMv9.3-A</span> </div> </a> <ul id="toc-ARMv8.8-A_and_ARMv9.3-A-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-ARMv8.9-A_and_ARMv9.4-A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ARMv8.9-A_and_ARMv9.4-A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.9</span> <span>ARMv8.9-A and ARMv9.4-A</span> </div> </a> <ul id="toc-ARMv8.9-A_and_ARMv9.4-A-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-ARMv9.5-A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ARMv9.5-A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.10</span> <span>ARMv9.5-A</span> </div> </a> <ul id="toc-ARMv9.5-A-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-ARMv9.6-A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ARMv9.6-A"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.11</span> <span>ARMv9.6-A</span> </div> </a> <ul id="toc-ARMv9.6-A-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-ARM-R_(real-time_architecture)" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#ARM-R_(real-time_architecture)"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>ARM-R (real-time architecture)</span> </div> </a> <button aria-controls="toc-ARM-R_(real-time_architecture)-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle ARM-R (real-time architecture) subsection</span> </button> <ul id="toc-ARM-R_(real-time_architecture)-sublist" class="vector-toc-list"> <li id="toc-Key_Features_of_Armv8-R_with_AArch64_Support" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Key_Features_of_Armv8-R_with_AArch64_Support"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Key Features of Armv8-R with AArch64 Support</span> </div> </a> <ul id="toc-Key_Features_of_Armv8-R_with_AArch64_Support-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" 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nomobile noexcerpt noprint searchaux" style="display:none">64-bit extension of the ARM architecture</div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Technical plainlinks metadata ambox ambox-style ambox-technical" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/f/f2/Edit-clear.svg/40px-Edit-clear.svg.png" decoding="async" width="40" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/f/f2/Edit-clear.svg/60px-Edit-clear.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/f/f2/Edit-clear.svg/80px-Edit-clear.svg.png 2x" data-file-width="48" data-file-height="48" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">This article <b>may be too technical for most readers to understand</b>.<span class="hide-when-compact"> Please <a class="external text" href="https://en.wikipedia.org/w/index.php?title=AArch64&action=edit">help improve it</a> to <a href="/wiki/Wikipedia:Make_technical_articles_understandable" title="Wikipedia:Make technical articles understandable">make it understandable to non-experts</a>, without removing the technical details.</span> <span class="date-container"><i>(<span class="date">June 2020</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:ARMCortexA57A53.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/2b/ARMCortexA57A53.jpg/220px-ARMCortexA57A53.jpg" decoding="async" width="220" height="146" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/2b/ARMCortexA57A53.jpg/330px-ARMCortexA57A53.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/2b/ARMCortexA57A53.jpg/440px-ARMCortexA57A53.jpg 2x" data-file-width="4928" data-file-height="3264" /></a><figcaption>Armv8-A platform with <a href="/wiki/ARM_Cortex-A57" title="ARM Cortex-A57">Cortex-A57</a>/<a href="/wiki/ARM_Cortex-A53" title="ARM Cortex-A53">A53</a> MPCore <a href="/wiki/ARM_big.LITTLE" title="ARM big.LITTLE">big.LITTLE</a> CPU chip</figcaption></figure> <p><b>AArch64</b> or <b>ARM64</b> is the <a href="/wiki/64-bit" class="mw-redirect" title="64-bit">64-bit</a> Execution state of the <a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM architecture family</a>. It was first introduced with the <a href="/wiki/Armv8-A" class="mw-redirect" title="Armv8-A">Armv8-A</a> architecture, and has had many extension updates.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="AArch64_Execution_state">AArch64 Execution state</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=1" title="Edit section: AArch64 Execution state"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Naming_conventions">Naming conventions</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=2" title="Edit section: Naming conventions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>64-bit: <ul><li>Execution state: AArch64.</li> <li>Instruction sets: A64.</li></ul></li> <li>32-bit: <ul><li>Execution state: AArch32.</li> <li>Instruction sets: A32 + T32.</li> <li>Example: ARMv8-R, Cortex-A32.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup></li></ul></li></ul> <div class="mw-heading mw-heading3"><h3 id="AArch64_features">AArch64 features</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=3" title="Edit section: AArch64 features"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>New instruction set, A64: <ul><li>Has 31 general-purpose 64-bit registers.</li> <li>Has dedicated zero or stack pointer (SP) register (depending on instruction).</li> <li>The program counter (PC) is no longer directly accessible as a register.</li> <li>Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped). <ul><li>Has paired loads/stores (in place of LDM/STM).</li> <li>No <a href="/wiki/Branch_predication" class="mw-redirect" title="Branch predication">predication</a> for most instructions (except branches).</li></ul></li> <li>Most instructions can take 32-bit or 64-bit arguments.</li> <li>Addresses assumed to be 64-bit.</li></ul></li> <li>Advanced <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a><span class="anchor" id="SIMD"></span> (Neon) enhanced: <ul><li>Has 32 × 128-bit registers (up from 16), also accessible via VFPv4.</li> <li>Supports <a href="/wiki/Double-precision_floating-point_format" title="Double-precision floating-point format">double-precision floating-point format</a>.</li> <li>Fully <a href="/wiki/IEEE_754" title="IEEE 754">IEEE 754</a> compliant.</li> <li>AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers.</li></ul></li> <li>A new exception system: <ul><li>Fewer banked registers and modes.</li></ul></li> <li>Memory translation from 48-bit virtual addresses based on the existing Large Physical Address Extension (LPAE), which was designed to be easily extended to 64-bit.</li></ul> <p>Extension: Data gathering hint (ARMv8.0-DGH). </p><p>AArch64 was introduced in ARMv8-A and is included in subsequent versions of ARMv8-A. It was also introduced in ARMv8-R as an option, after its introduction in ARMv8-A; it is not included in ARMv8-M. </p> <div class="mw-heading mw-heading4"><h4 id="Instruction_formats">Instruction formats</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=4" title="Edit section: Instruction formats"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The main opcode for selecting which group an A64 instruction belongs to is at bits 25–28. </p> <table class="wikitable mw-collapsible mw-collapsed" style="text-align:center;"> <caption><span class="nowrap">A64 instruction formats</span> </caption> <tbody><tr> <th rowspan="2">Type </th> <th colspan="32">Bit </th></tr> <tr> <th>31</th> <th>30</th> <th>29</th> <th>28</th> <th>27</th> <th>26</th> <th>25</th> <th>24</th> <th>23</th> <th>22</th> <th>21</th> <th>20</th> <th>19</th> <th>18</th> <th>17</th> <th>16</th> <th>15</th> <th>14</th> <th>13</th> <th>12</th> <th>11</th> <th>10</th> <th>9</th> <th>8</th> <th>7</th> <th>6</th> <th>5</th> <th>4</th> <th>3</th> <th>2</th> <th>1</th> <th>0 </th></tr> <tr> <td>Reserved </td> <td>0 </td> <td colspan="2">op<sub>0</sub> </td> <td>0</td> <td>0</td> <td>0</td> <td>0 </td> <td colspan="9">op<sub>1</sub> </td> <td colspan="16"> </td></tr> <tr> <td><abbr title="Scalable Matrix Extensions">SME</abbr> </td> <td>1 </td> <td colspan="2">op<sub>0</sub> </td> <td>0</td> <td>0</td> <td>0</td> <td>0 </td> <td colspan="25">Varies </td></tr> <tr> <td>Unallocated </td> <td colspan="3"> </td> <td>0</td> <td>0</td> <td>0</td> <td>1 </td> <td colspan="25"> </td></tr> <tr> <td><abbr title="Scalable Vector Extensions">SVE</abbr> </td> <td colspan="3"> </td> <td>0</td> <td>0</td> <td>1</td> <td>0 </td> <td colspan="25">Varies </td></tr> <tr> <td>Unallocated </td> <td colspan="3"> </td> <td>0</td> <td>0</td> <td>1</td> <td>1 </td> <td colspan="25"> </td></tr> <tr> <td>Data Processing — Immediate PC-rel. </td> <td>op</td> <td colspan="2">imm<sub>lo</sub></td> <td>1</td> <td>0</td> <td>0</td> <td>0</td> <td>0</td> <td colspan="19">imm<sub>hi</sub></td> <td colspan="5">Rd </td></tr> <tr> <td>Data Processing — Immediate Others </td> <td>sf</td> <td colspan="2"></td> <td>1</td> <td>0</td> <td>0</td> <td colspan="2">01–11</td> <td colspan="19"></td> <td colspan="5">Rd </td></tr> <tr> <td>Branches + System Instructions </td> <td colspan="3">op0</td> <td>1</td> <td>0</td> <td>1</td> <td colspan="14">op1</td> <td colspan="7"></td> <td colspan="5">op2 </td></tr> <tr> <td>Load and Store Instructions </td> <td colspan="4">op0</td> <td>1</td> <td>op1</td> <td>0</td> <td colspan="2">op2</td> <td></td> <td colspan="6">op3</td> <td colspan="4"></td> <td colspan="2">op4</td> <td colspan="10"> </td></tr> <tr> <td>Data Processing — Register </td> <td>sf</td> <td>op0</td> <td></td> <td>op1</td> <td>1</td> <td>0</td> <td>1</td> <td colspan="4">op2</td> <td colspan="5"></td> <td colspan="6">op3</td> <td colspan="10"> </td></tr> <tr> <td>Data Processing — Floating Point and SIMD </td> <td colspan="4">op0</td> <td>1</td> <td>1</td> <td>1</td> <td colspan="2">op1</td> <td colspan="4">op2</td> <td colspan="9">op3</td> <td colspan="10"> </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="ARM-A_(application_architecture)"><span id="ARM-A_.28application_architecture.29"></span><span class="anchor" id="ARM8-A"></span>ARM-A (application architecture)</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=5" title="Edit section: ARM-A (application architecture)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Comparison_of_ARMv8-A_processors" class="mw-redirect" title="Comparison of ARMv8-A processors">Comparison of ARMv8-A processors</a></div> <p>Announced in October 2011,<sup id="cite_ref-armv8-a-announcement_3-0" class="reference"><a href="#cite_note-armv8-a-announcement-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> <b>ARMv8-A</b> represents a fundamental change to the ARM architecture. It adds an optional 64-bit Execution state, named "AArch64", and the associated new "A64" instruction set, in addition to a 32-bit Execution state, "AArch32", supporting the 32-bit "A32" (original 32-bit Arm) and "T32" (Thumb/Thumb-2) instruction sets. The latter instruction sets provide <a href="/wiki/User_space" class="mw-redirect" title="User space">user-space</a> compatibility with the existing 32-bit ARMv7-A architecture. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit <a href="/wiki/Hypervisor" title="Hypervisor">hypervisor</a>.<sup id="cite_ref-v8arch_4-0" class="reference"><a href="#cite_note-v8arch-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> ARM announced their <a href="/wiki/ARM_Cortex-A53" title="ARM Cortex-A53">Cortex-A53</a> and <a href="/wiki/ARM_Cortex-A57" title="ARM Cortex-A57">Cortex-A57</a> cores on 30 October 2012.<sup id="cite_ref-cortex-a50_announce_5-0" class="reference"><a href="#cite_note-cortex-a50_announce-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Apple_Inc." title="Apple Inc.">Apple</a> was the first to release an ARMv8-A compatible core (<a href="/wiki/Apple_A7" title="Apple A7">Cyclone</a>) in a consumer product (<a href="/wiki/IPhone_5S" class="mw-redirect" title="IPhone 5S">iPhone 5S</a>). <a href="/wiki/AppliedMicro" class="mw-redirect" title="AppliedMicro">AppliedMicro</a>, using an <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a>, was the first to demo ARMv8-A.<sup id="cite_ref-AppliedMicro-First_64-bit_ARM_v8_Core_6-0" class="reference"><a href="#cite_note-AppliedMicro-First_64-bit_ARM_v8_Core-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> The first ARMv8-A <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a> from <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a> is the Exynos 5433 used in the <a href="/wiki/Samsung_Galaxy_Note_4" title="Samsung Galaxy Note 4">Galaxy Note 4</a>, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a <a href="/wiki/ARM_big.LITTLE" title="ARM big.LITTLE">big.LITTLE</a> configuration; but it will run only in AArch32 mode.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> </p><p>ARMv8-A includes the VFPv3/v4 and advanced SIMD (Neon) as standard features in both AArch32 and AArch64. It also adds cryptography instructions supporting <a href="/wiki/Advanced_Encryption_Standard" title="Advanced Encryption Standard">AES</a>, <a href="/wiki/SHA-1" title="SHA-1">SHA-1</a>/<a href="/wiki/SHA-256" class="mw-redirect" title="SHA-256">SHA-256</a> and <a href="/wiki/Finite_field_arithmetic" title="Finite field arithmetic">finite field arithmetic</a>.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p><p>An ARMv8-A processor can support one or both of AArch32 and AArch64; it may support AArch32 and AArch64 at lower Exception levels and only AArch64 at higher Exception levels.<sup id="cite_ref-Execution-state-and-Exception-levels_9-0" class="reference"><a href="#cite_note-Execution-state-and-Exception-levels-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> For example, the ARM Cortex-A32 supports only AArch32,<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> the <a href="/wiki/ARM_Cortex-A34" title="ARM Cortex-A34">ARM Cortex-A34</a> supports only AArch64,<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> and the <a href="/wiki/ARM_Cortex-A72" title="ARM Cortex-A72">ARM Cortex-A72</a> supports both AArch64 and AArch32.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> An ARMv9-A processor must support AArch64 at all Exception levels, and may support AArch32 at EL0.<sup id="cite_ref-Execution-state-and-Exception-levels_9-1" class="reference"><a href="#cite_note-Execution-state-and-Exception-levels-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="ARMv8.1-A">ARMv8.1-A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=6" title="Edit section: ARMv8.1-A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In December 2014, ARMv8.1-A,<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation. </p><p>Instruction set enhancements included the following: </p> <ul><li>A set of AArch64 atomic read-write instructions.</li> <li>Additions to the Advanced SIMD instruction set for both AArch32 and AArch64 to enable opportunities for some library optimizations: <ul><li>Signed Saturating Rounding Doubling Multiply Accumulate, Returning High Half.</li> <li>Signed Saturating Rounding Doubling Multiply Subtract, Returning High Half.</li> <li>The instructions are added in vector and scalar forms.</li></ul></li> <li>A set of AArch64 load and store instructions that can provide memory access order that is limited to configurable address regions.</li> <li>The optional CRC instructions in v8.0 become a requirement in ARMv8.1.</li></ul> <p>Enhancements for the exception model and memory translation system included the following: </p> <ul><li>A new Privileged Access Never (PAN) state bit provides control that prevents privileged access to user data unless explicitly enabled.</li> <li>An increased VMID range for virtualization; supports a larger number of virtual machines.</li> <li>Optional support for hardware update of the page table access flag, and the standardization of an optional, hardware updated, dirty bit mechanism.</li> <li>The Virtualization Host Extensions (VHE). These enhancements improve the performance of Type 2 hypervisors by reducing the software overhead associated when transitioning between the Host and Guest operating systems. The extensions allow the Host OS to execute at EL2, as opposed to EL1, without substantial modification.</li> <li>A mechanism to free up some translation table bits for operating system use, where the hardware support is not needed by the OS.</li> <li><a href="/w/index.php?title=Top_byte_ignore&action=edit&redlink=1" class="new" title="Top byte ignore (page does not exist)">Top byte ignore</a> for <a href="/w/index.php?title=Memory_tagging&action=edit&redlink=1" class="new" title="Memory tagging (page does not exist)">memory tagging</a>.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading3"><h3 id="ARMv8.2-A">ARMv8.2-A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=7" title="Edit section: ARMv8.2-A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In January 2016, ARMv8.2-A was announced.<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> Its enhancements fell into four categories: </p> <ul><li>Optional <a href="/wiki/Half-precision_floating-point_format" title="Half-precision floating-point format">half-precision floating-point</a> data processing (half-precision was already supported, but not for processing, just as a storage format.)</li> <li>Memory model enhancements.</li> <li>Introduction of <a href="/wiki/Reliability,_availability_and_serviceability" title="Reliability, availability and serviceability">Reliability, Availability and Serviceability Extension</a> (RAS Extension).</li> <li>Introduction of statistical profiling.</li></ul> <p><span class="anchor" id="ARMv8-A_SVE"></span> </p> <div class="mw-heading mw-heading4"><h4 id="Scalable_Vector_Extension_(SVE)"><span id="Scalable_Vector_Extension_.28SVE.29"></span>Scalable Vector Extension (SVE) <span class="anchor" id="Scalable_vector_extension"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=8" title="Edit section: Scalable Vector Extension (SVE)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Scalable Vector Extension (SVE) is "an optional extension to the ARMv8.2-A architecture and newer" developed specifically for vectorization of <a href="/wiki/High-performance_computing" title="High-performance computing">high-performance computing</a> scientific workloads.<sup id="cite_ref-2016-08-22-arm-blog_16-0" class="reference"><a href="#cite_note-2016-08-22-arm-blog-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-gcc8changelog_17-0" class="reference"><a href="#cite_note-gcc8changelog-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> The specification allows for variable vector lengths to be implemented from 128 to 2048 bits. The extension is complementary to, and does not replace, the <a href="/wiki/ARM_architecture#Advanced_SIMD_(Neon)" class="mw-redirect" title="ARM architecture">NEON</a> extensions. </p><p>A 512-bit SVE variant has already been implemented on the <a href="/wiki/Fugaku_(supercomputer)" title="Fugaku (supercomputer)">Fugaku supercomputer</a> using the <a href="/wiki/Fujitsu_A64FX" title="Fujitsu A64FX">Fujitsu A64FX</a> ARM processor; this computer<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> was the fastest supercomputer in the world for two years, from June 2020<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> to May 2022.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> A more flexible version, 2x256 SVE, was implemented by the <a href="/wiki/AWS_Graviton" title="AWS Graviton">AWS Graviton3</a> ARM processor. </p><p>SVE is supported by the <a href="/wiki/GNU_Compiler_Collection" title="GNU Compiler Collection">GCC</a> compiler, with GCC 8 supporting automatic vectorization<sup id="cite_ref-gcc8changelog_17-1" class="reference"><a href="#cite_note-gcc8changelog-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> and GCC 10 supporting C intrinsics. As of July 2020<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=AArch64&action=edit">[update]</a></sup>, <a href="/wiki/LLVM" title="LLVM">LLVM</a> and <a href="/wiki/Clang" title="Clang">clang</a> support C and IR intrinsics. ARM's own fork of LLVM supports auto-vectorization.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="ARMv8.3-A">ARMv8.3-A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=9" title="Edit section: ARMv8.3-A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In October 2016, ARMv8.3-A was announced. Its enhancements fell into six categories:<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> </p> <ul><li>Pointer authentication<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> (AArch64 only); mandatory extension (based on a new block cipher, <a href="/wiki/QARMA" title="QARMA">QARMA</a><sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup>) to the architecture (compilers need to exploit the security feature, but as the instructions are in NOP space, they are backwards compatible albeit providing no extra security on older chips).</li> <li>Nested virtualization (AArch64 only).</li> <li>Advanced SIMD <a href="/wiki/Complex_number" title="Complex number">complex number</a> support (AArch64 and AArch32); e.g. rotations by multiples of 90 degrees.</li> <li>New FJCVTZS (Floating-point <a href="/wiki/JavaScript" title="JavaScript">JavaScript</a> Convert to Signed fixed-point, rounding toward Zero) instruction.<sup id="cite_ref-:0_25-0" class="reference"><a href="#cite_note-:0-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup></li> <li>A change to the memory consistency model (AArch64 only); to support the (non-default) weaker RCpc (Release Consistent processor consistent) model of <a href="/wiki/C%2B%2B11" title="C++11">C++11</a>/<a href="/wiki/C11_(C_standard_revision)" title="C11 (C standard revision)">C11</a> (the default C++11/C11 consistency model was already supported in previous ARMv8).</li> <li>ID mechanism support for larger system-visible caches (AArch64 and AArch32).</li></ul> <p>ARMv8.3-A architecture is now supported by (at least) the <a href="/wiki/GNU_Compiler_Collection" title="GNU Compiler Collection">GCC</a> 7 compiler.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="ARMv8.4-A">ARMv8.4-A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=10" title="Edit section: ARMv8.4-A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In November 2017, ARMv8.4-A was announced. Its enhancements fell into these categories:<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> </p> <ul><li>"SHA3 / SHA512 / SM3 / <a href="/wiki/SM4_algorithm" class="mw-redirect" title="SM4 algorithm">SM4</a> crypto extensions." I.e. optional instructions.</li> <li>Improved virtualization support.</li> <li>Memory Partitioning and Monitoring (MPAM) capabilities.</li> <li>A new Secure EL2 state and Activity Monitors.</li> <li>Signed and unsigned integer <a href="/wiki/Dot_product" title="Dot product">dot product</a> (SDOT and UDOT) instructions.</li></ul> <div class="mw-heading mw-heading3"><h3 id="ARMv8.5-A_and_ARMv9.0-A">ARMv8.5-A and ARMv9.0-A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=11" title="Edit section: ARMv8.5-A and ARMv9.0-A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><span class="anchor" id="ARMv8.5-A"></span><span class="anchor" id="ARMv9.0-A"></span> In September 2018, ARMv8.5-A was announced. Its enhancements fell into these categories:<sup id="cite_ref-armv8-x-and-armv9-x-extensions-and-features_30-0" class="reference"><a href="#cite_note-armv8-x-and-armv9-x-extensions-and-features-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> </p> <ul><li>Memory Tagging Extension (MTE) (AArch64).<sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup></li> <li>Branch Target Indicators (BTI) (AArch64) to reduce "the ability of an attacker to execute arbitrary code". Like pointer authentication, the relevant instructions are no-ops on earlier versions of ARMv8-A.</li> <li>Random Number Generator instructions – "providing Deterministic and True Random Numbers conforming to various National and International Standards".</li></ul> <p>On 2 August 2019, <a href="/wiki/Google" title="Google">Google</a> announced <a href="/wiki/Android_(operating_system)" title="Android (operating system)">Android</a> would adopt Memory Tagging Extension (MTE).<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> </p><p><span class="anchor" id="ARMv9-A"></span> In March 2021, ARMv9-A was announced. ARMv9-A's baseline is all the features from ARMv8.5.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> ARMv9-A also adds: </p> <ul><li>Scalable Vector Extension 2 (SVE2). SVE2 builds on SVE's scalable vectorization for increased fine-grain <a href="/wiki/Data-level_parallelism" class="mw-redirect" title="Data-level parallelism">Data Level Parallelism (DLP)</a>, to allow more work done per instruction. SVE2 aims to bring these benefits to a wider range of software including DSP and multimedia SIMD code that currently use <a href="#SIMD">Neon</a>.<sup id="cite_ref-sve2-tme_38-0" class="reference"><a href="#cite_note-sve2-tme-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> The <a href="/wiki/LLVM" title="LLVM">LLVM</a>/<a href="/wiki/Clang" title="Clang">Clang</a> 9.0 and <a href="/wiki/GNU_Compiler_Collection" title="GNU Compiler Collection">GCC</a> 10.0 development codes were updated to support SVE2.<sup id="cite_ref-sve2-tme_38-1" class="reference"><a href="#cite_note-sve2-tme-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:1_39-0" class="reference"><a href="#cite_note-:1-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup></li> <li>Transactional Memory Extension (TME). Following <a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">the x86 extensions</a>, TME brings support for <a href="/wiki/Transactional_memory" title="Transactional memory">Hardware Transactional Memory (HTM)</a> and Transactional Lock Elision (TLE). TME aims to bring scalable concurrency to increase coarse-grained <a href="/wiki/Thread-level_parallelism" class="mw-redirect" title="Thread-level parallelism">Thread Level Parallelism (TLP)</a>, to allow more work done per thread.<sup id="cite_ref-sve2-tme_38-2" class="reference"><a href="#cite_note-sve2-tme-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> The <a href="/wiki/LLVM" title="LLVM">LLVM</a>/<a href="/wiki/Clang" title="Clang">Clang</a> 9.0 and <a href="/wiki/GNU_Compiler_Collection" title="GNU Compiler Collection">GCC</a> 10.0 development codes were updated to support TME.<sup id="cite_ref-:1_39-1" class="reference"><a href="#cite_note-:1-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup></li> <li>Confidential Compute Architecture (CCA).<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading3"><h3 id="ARMv8.6-A_and_ARMv9.1-A">ARMv8.6-A and ARMv9.1-A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=12" title="Edit section: ARMv8.6-A and ARMv9.1-A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><span class="anchor" id="ARMv8.6-A"></span><span class="anchor" id="ARMv9.1-A"></span> In September 2019, ARMv8.6-A was announced. Its enhancements fell into these categories:<sup id="cite_ref-armv8-x-and-armv9-x-extensions-and-features_30-1" class="reference"><a href="#cite_note-armv8-x-and-armv9-x-extensions-and-features-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> </p> <ul><li>General Matrix Multiply (GEMM).</li> <li><a href="/wiki/Bfloat16_floating-point_format" title="Bfloat16 floating-point format">Bfloat16 format</a> support.</li> <li>SIMD matrix manipulation instructions, BFDOT, BFMMLA, BFMLAL and BFCVT.</li> <li>Enhancements for virtualization, system management and security.</li> <li>And the following extensions (that <a href="/wiki/LLVM" title="LLVM">LLVM</a> 11 already added support for<sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup>): <ul><li>Enhanced Counter Virtualization (ARMv8.6-ECV).</li> <li>Fine-Grained Traps (ARMv8.6-FGT).</li> <li>Activity Monitors virtualization (ARMv8.6-AMU).</li></ul></li></ul> <p>For example, fine-grained traps, Wait-for-Event (WFE) instructions, EnhancedPAC2 and FPAC. The bfloat16 extensions for SVE and Neon are mainly for deep learning use.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="ARMv8.7-A_and_ARMv9.2-A">ARMv8.7-A and ARMv9.2-A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=13" title="Edit section: ARMv8.7-A and ARMv9.2-A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><span class="anchor" id="ARMv8.7-A"></span><span class="anchor" id="ARMv9.2-A"></span> In September 2020, ARMv8.7-A was announced. Its enhancements fell into these categories:<sup id="cite_ref-armv8-x-and-armv9-x-extensions-and-features_30-2" class="reference"><a href="#cite_note-armv8-x-and-armv9-x-extensions-and-features-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> </p> <ul><li>Scalable Matrix Extension (SME)(ARMv9.2 only).<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> SME adds new features to process matrices efficiently, such as: <ul><li>Matrix tile storage.</li> <li>On-the-fly matrix transposition.</li> <li>Load/store/insert/extract tile vectors.</li> <li>Matrix outer product of SVE vectors.</li> <li>"Streaming mode" SVE.</li></ul></li> <li>Enhanced support for PCIe hot plug (AArch64).</li> <li>Atomic 64-byte load and stores to accelerators (AArch64).</li> <li>Wait For Instruction (WFI) and Wait For Event (WFE) with timeout (AArch64).</li> <li>Branch-Record recording (ARMv9.2 only).</li> <li>Call Stack Recorder</li></ul> <div class="mw-heading mw-heading3"><h3 id="ARMv8.8-A_and_ARMv9.3-A">ARMv8.8-A and ARMv9.3-A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=14" title="Edit section: ARMv8.8-A and ARMv9.3-A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><span class="anchor" id="ARMv8.8-A"></span><span class="anchor" id="ARMv9.3-A"></span> In September 2021, ARMv8.8-A and ARMv9.3-A were announced. Their enhancements fell into these categories:<sup id="cite_ref-armv8-x-and-armv9-x-extensions-and-features_30-3" class="reference"><a href="#cite_note-armv8-x-and-armv9-x-extensions-and-features-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </p> <ul><li>Non-maskable interrupts (AArch64).</li> <li>Instructions to optimize memcpy() and memset() style operations (AArch64).</li> <li>Enhancements to PAC (AArch64).</li> <li>Hinted conditional branches (AArch64).</li></ul> <p><a href="/wiki/LLVM" title="LLVM">LLVM</a> 15 supports ARMv8.8-A and ARMv9.3-A.<sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="ARMv8.9-A_and_ARMv9.4-A">ARMv8.9-A and ARMv9.4-A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=15" title="Edit section: ARMv8.9-A and ARMv9.4-A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><span class="anchor" id="ARMv8.9-A"></span><span class="anchor" id="ARMv9.4-A"></span> In September 2022, ARMv8.9-A and ARMv9.4-A were announced, including:<sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> </p> <ul><li>Virtual Memory System Architecture (VMSA) enhancements. <ul><li>Permission indirection and overlays.</li> <li>Translation hardening.</li> <li>128-bit translation tables (ARMv9 only).</li></ul></li> <li>Scalable Matrix Extension 2 (SME2) (ARMv9 only). <ul><li>Multi-vector instructions.</li> <li>Multi-vector predicates.</li> <li>2b/4b weight compression.</li> <li>1b binary networks.</li> <li>Range Prefetch.</li></ul></li> <li>Guarded Control Stack (GCS) (ARMv9 only).</li> <li>Confidential Computing. <ul><li>Memory Encryption Contexts.</li> <li>Device Assignment.</li></ul></li></ul> <div class="mw-heading mw-heading3"><h3 id="ARMv9.5-A">ARMv9.5-A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=16" title="Edit section: ARMv9.5-A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><span class="anchor" id="ARMv9.5-A"></span> In October 2023, ARMv9.5-A was announced, including:<sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> </p> <ul><li>FP8 support (E5M2 and E4M3 formats) added to: <ul><li>SME2</li> <li>SVE2</li> <li>Advanced SIMD (Neon)</li></ul></li> <li>Live migration of Virtual Machines using Hardware Dirty state tracking structures (FEAT_HDBSS)</li> <li>Checked Point Arithmetic</li> <li>Support for using a combination of the PC and SP as the modifier when generating or checking Pointer Authentication codes.</li> <li>Support for Realm Management Extension (RME) enabled designs, support for non-secure only in the Granule Protection Tables and the ability to disable certain Physical Address Spaces (PAS).</li> <li>EL3 configuration write-traps.</li> <li>Breakpoint support for address range and mismatch triggering without the need for linking.</li> <li>Support for efficiently delegating SErrors from EL3 to EL2 or EL1.</li></ul> <div class="mw-heading mw-heading3"><h3 id="ARMv9.6-A">ARMv9.6-A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=17" title="Edit section: ARMv9.6-A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><span class="anchor" id="ARMv9.6-A"></span> In October 2024, ARMv9.6-A was announced, including:<sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </p> <ul><li>Improved SME efficiency with structured sparsity and quarter tile operations</li> <li>MPAM Domains to better support shared-memory computer systems on multi-chiplet and multi-chip systems</li> <li>Hypervisor memory control for Trace and Statistical Profiling on virtual machines</li> <li>Improved Caching and Data Placement</li> <li>Granular Data Isolation for Confidential Compute</li> <li>Bitwise locking of EL1 system registers</li> <li>Improved scaling of Granular Protection Tables (GPT) for large memory systems</li> <li>New SVE instructions for expand/compact and finding first/last active element</li> <li>Additional unprivileged load and store instructions to enable OS to interact with application memory</li> <li>New compare and branch instruction</li> <li>Injection of Undefined-Instruction exceptions from EL3</li></ul> <div class="mw-heading mw-heading2"><h2 id="ARM-R_(real-time_architecture)"><span id="ARM-R_.28real-time_architecture.29"></span><span class="anchor" id="ARM8-R"></span>ARM-R (real-time architecture)</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=18" title="Edit section: ARM-R (real-time architecture)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-Expand_section plainlinks metadata ambox ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/44px-Wiki_letter_w_cropped.svg.png" decoding="async" width="44" height="31" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/66px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/88px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></div></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b> with: examples and additional citations. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=AArch64&action=edit&section=1">adding to it</a>.<span class="hide-when-compact"> Relevant discussion may be found on <a href="/wiki/Talk:AArch64" title="Talk:AArch64">Talk:AArch64</a>.</span> <span class="date-container"><i>(<span class="date">May 2021</span>)</i></span></div></td></tr></tbody></table> <p>The <i><b>ARM-R</b></i> architecture, specifically the Armv8-R profile, is designed to address the needs of real-time applications, where predictable and deterministic behavior is essential. This profile focuses on delivering high performance, reliability, and efficiency in embedded systems where real-time constraints are critical. </p><p>With the introduction of optional AArch64 support in the Armv8-R profile, the real-time capabilities have been further enhanced. The Cortex-R82<sup id="cite_ref-:2_52-0" class="reference"><a href="#cite_note-:2-52"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup> is the first processor to implement this extended support, bringing several new features and improvements to the real-time domain.<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Key_Features_of_Armv8-R_with_AArch64_Support">Key Features of Armv8-R with AArch64 Support</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=19" title="Edit section: Key Features of Armv8-R with AArch64 Support"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ol><li><b>AArch64 Instruction Set (A64)</b>: <ul><li>The A64 instruction<sup id="cite_ref-:0_25-1" class="reference"><a href="#cite_note-:0-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> set in the Cortex-R82 provides 64-bit data handling and operations, which improves performance for certain computational tasks and enhances overall system efficiency.<sup id="cite_ref-:2_52-1" class="reference"><a href="#cite_note-:2-52"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup></li> <li><b>Example Instruction</b>: <code>ADD X0, X1, X2</code> adds the values in 64-bit registers X1 and X2 and stores the result in X0. This 64-bit operation allows for larger and more complex calculations compared to the 32-bit operations of the previous A32 instruction set.</li></ul></li> <li><b>Enhanced Memory Management</b>: <ul><li><b>Memory Barrier Instructions</b>: The Cortex-R82 introduces improved memory barrier instructions to ensure proper ordering of memory operations, which is critical in real-time systems where the timing of memory operations must be strictly controlled.<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup> <ul><li><b>Data Synchronization Barrier (DSB)</b>: Ensures that all data accesses before the barrier are completed before continuing with subsequent operations.</li> <li><b>Data Memory Barrier (DMB)</b>: Guarantees that all memory accesses before the barrier are completed before any memory accesses after the barrier can proceed.</li></ul></li> <li><b>Example</b>: In a real-time automotive control system, DSB might be used to ensure that sensor data is fully written to memory before the system proceeds with processing or decision-making, preventing data corruption or inconsistencies.</li></ul></li> <li><b>Improved Address Space</b>: <ul><li><b>64-bit Addressing</b>: AArch64 allows the Cortex-R82 to address a much larger memory space compared to its 32-bit predecessors, making it suitable for applications requiring extensive memory.</li> <li><b>Example</b>: A complex industrial automation system can utilize the expanded address space to manage large data sets and buffers more efficiently, improving system performance and capability.</li></ul></li> <li><b>Real-Time Performance Enhancements</b>: <ul><li><b>Interrupt Handling</b>: With AArch64 support, the Cortex-R82 can handle interrupts with lower latency and improved predictability, crucial for real-time operations.</li> <li><b>Example</b>: In a robotics application, the Cortex-R82's enhanced interrupt handling can ensure timely responses to external stimuli, such as changes in sensor data or control commands.</li></ul></li></ol> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AArch64&action=edit&section=20" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" 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