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<article id="post-43446" class="post-43446 post type-post status-publish format-standard hentry category-volume-11-issue-05-may-2022"> <div class="article-inner "> <header class="entry-header"> <div class="entry-header-text entry-header-text-top text-center"> <h6 class="entry-category is-xsmall"><a href="https://www.ijert.org/category/volume-11-issue-05-may-2022" rel="category tag">Volume 11, Issue 05 (May 2022)</a></h6><h1 class="entry-title">Design and Implementation of 32-bit Wallace Multiplier using Compressors and Various Adders</h1><div class="entry-divider is-divider small"></div> </div> </header> <div class="entry-content single-page"> <div style='padding:16px 0px 0px 0px;'><img src='wp-content/uploads/doi-ijert-logo.png' /><strong> DOI : </strong><strong>10.17577/IJERTV11IS050369</strong></div><p> <div id="gap-1361285989" class="gap-element clearfix" style="display:block; height:auto;"> <style> #gap-1361285989 { padding-top: 10px; } </style> </div> <a href="https://www.ijert.org/research/design-and-implementation-of-32-bit-wallace-multiplier-using-compressors-and-various-adders-IJERTV11IS050369.pdf" target="_blank" class="button primary is-primary is-medium" rel="noopener" > <span>Download Full-Text PDF</span> </a> <a href="#cite" class="button primary" > <span>Cite this Publication</span> </a> <div id="cite" class="lightbox-by-id lightbox-content mfp-hide lightbox-white " style="max-width:600px ;padding:20px"> Prathima Gamini , K. Pradeep Kumar , K. Ramya Sri , J. Samhitha, M. Sandeep Kumar, 2022, Design and Implementation of 32-bit Wallace Multiplier using Compressors and Various Adders, INTERNATIONAL JOURNAL OF ENGINEERING RESEARCH & TECHNOLOGY (IJERT) Volume 11, Issue 05 (May 2022), </div> <img decoding="async" src="https://www.ijert.org/author-photo/V11IS5/IJERTV11IS050369.jpg" /> </p> <ul> <li><strong>Open Access </strong> <img decoding="async" src="../images/open-access-logo.png" /> </li> <li> <div class="post-views content-post post-43446 entry-meta load-static"> <span class="post-views-icon dashicons dashicons-chart-bar"></span> <span class="post-views-label">Article Download / Views:</span> <span class="post-views-count">681</span> </div> </li> <li> <strong>Authors :</strong> Prathima Gamini , K. Pradeep Kumar , K. Ramya Sri , J. Samhitha, M. Sandeep Kumar </li> <li> <strong>Paper ID :</strong> IJERTV11IS050369 </li> <li> <strong> Volume & Issue : </strong> <a href="https://www.ijert.org/volume-11-issue-05-may-2022" target=_blank style="color:blue;">Volume 11, Issue 05 (May 2022) </a></li> <li> <strong> Published (First Online): </strong> 07-06-2022 </li> <li> <strong>ISSN (Online) :</strong> 2278-0181 </li> <li> <strong>Publisher Name :</strong> IJERT </li> <li> <strong>License: </strong><a href="http://creativecommons.org/licenses/by/4.0/" rel="license"><img decoding="async" style="border-width: 0;" src="https://i.creativecommons.org/l/by/4.0/80x15.png" alt="Creative Commons License" /></a> This work is licensed under a <a href="http://creativecommons.org/licenses/by/4.0/" rel="license">Creative Commons Attribution 4.0 International License</a> </li> </ul> <p> <div id="gap-1864124241" class="gap-element clearfix" style="display:block; height:auto;"> <style> #gap-1864124241 { padding-top: 15px; } </style> </div> <div class="accordion"> <div id="accordion-896871443" class="accordion-item"> <a id="accordion-896871443-label" class="accordion-title plain" href="#accordion-item-pdf-version" aria-expanded="false" aria-controls="accordion-896871443-content" > <button class="toggle" aria-label="Toggle"><i class="icon-angle-down"></i></button> <span>PDF Version</span> </a> <div id="accordion-896871443-content" class="accordion-inner" aria-labelledby="accordion-896871443-label" > <a class="fancybox-pdf" href="https://www.ijert.org/research/design-and-implementation-of-32-bit-wallace-multiplier-using-compressors-and-various-adders-IJERTV11IS050369.pdf"> View </a> </div> </div> <div id="accordion-1451152294" class="accordion-item"> <a id="accordion-1451152294-label" class="accordion-title plain active" href="#accordion-item-text-only-version" aria-expanded="true" aria-controls="accordion-1451152294-content" > <button class="toggle" aria-label="Toggle"><i class="icon-angle-down"></i></button> <span>Text Only Version</span> </a> <div id="accordion-1451152294-content" class="accordion-inner" style="display: block;" aria-labelledby="accordion-1451152294-label" > </p> <div style="text-align: justify;text-justify: inter-word;"> <div itemProp="mainEntity" itemScope="itemscope" itemType="http://schema.org/ScholarlyArticle" > <meta itemProp="datePublished" name="datePublished" content="07-06-2022"/> <meta itemProp="image" name="image" content="https://www.ijert.org/images/default_publication_preview_large.png"/> </p> <h4 itemProp="headline">Design and Implementation of 32-bit Wallace Multiplier using Compressors and Various Adders</h4> [1] Prathima Gamini, [2] K. Pradeep Kumar, [3] K.Ramya Sri, [4] J.Samhitha, [5] M.Sandeep Kumar</p> [1] Assistant Professor,</p> [2] [3] [4] [5] B.Tech Students</p> <p>Department of ECE, Sagi Rama Krishnam Raju Engineering College Students, Department of ECE, SRKREC, Bhimavaram ,Andhra Pradesh ,India.</p> <p>Abstract – This project deals with the implementation of 32-bit Multiplier with the help of Compressors and various adders by using Wallace Tree Approach. Multipliers involve the generation and addition of partial products. By employing compressors , the partial products count will be reduced, which helps in minimization of hardware requirements and on-chip space.</p> <h4>Usage of compressors in partial products reduction is so popular and their summing takes place by making use of different adders involving Carry Look-ahead Adder (CLA), Carry Select Adder (CSLA), Kogge-Stone Adder (KSA) and Brent-Kung Adder (BKA).Then the delay, power consumption, Bonded IOB , LUTs and Slice of 8-bit , 16-bit and 32-bit multipliers for various adders are compared. These multipliers are coded in Verilog HDL and synthesized using XILINX Vivado software v2017.2.</h4> <p>Key Words: Compressors, Wallace Tree Approach, Adders, Multiplier.</p> <p>1.INTRODUCTION</p> <p>As long as power consumption and computation speed are constrained, multipliers are important components dictating overall circuit performance. The reduction of partial products in the multiplication process contributes to overall delay , power and area. A compressor is a processing element that can handle more inputs than half and full adders. Compressors are the basic building blocks for accumulating partial products. Higher order compressors provide better results in terms of power and speed because they can reduce both the vertical critical part and stage operations at the same time. As a result, compressors are used to improve the performance of circuit structures optimized for high-speed applications. To perform the partial product addition in high- speed applications, a large number of compressors are used in multiplication. Typically, partial product addition has beem accomplished using various types of compressors such as 3-2, 4-2, 5-2 and so on.</p> <p>Wallace Tree Approach has been used in this paper. The Wallace Tree is a long multiplication variant. It is a hardware implementation of a binary multiplier, which is a digital circuit for multiplying two integers.</p> <p>Section 2 of this paper provides a brief overview of compressor architectures and concepts. Section 3 discusses basic parallel adders and parallel prefix adders that are used. Section 4 goes over Wallace Multiplier. Section 5 provides a comparison of results based on different parameters using different adders.</p> <p>2.COMPRESSORS</p> <p>A Compressor is a device that is used to accumulate partial products and reduce operands while adding partial product terms in multipliers. Compressors are used in the multiplication process to reduce the latency of the partial product reduction part. High speed multipliers use 3-2, 4-2, 5- 2 and 7-2 compressors.</p> <p>2.1 DESIGN OF 3-2 COMPRESSOR</p> <p>A 3-2 Compressor (Full Adder) performs an addition operation on three binary digits. It produces Sum and Carry. The Boolean Equations are:</p> <p>SUM= A XOR B XOR Cin.</p> <p>Carryout=(A AND B) OR (B AND Cin) OR (Cin AND A).</p> <p>This can also implemented by only 9 NAND or 9 NOR gates.These can used in many arithmetic and logical operations .This is the basic building block of Ripple carry adder.</p> <p>Figure 2.1: 3-2 compressor</p> <ol> <ol> <li> <p>DESIGN OF 4-2 COMPRESSOR</p> <p>A 4-2 Compressor is made up of two full adders that are serially connected. The 4-2 Compressor takes five inputs (x1, x2, x3, x4 and Cin) and produces three outputs (sum, carry and Cout). Cin is the output of the preceding lower significant stage as well as the output. Cout is the input to a compressor in the successive higher significant stage.</p> <p>Fig 2.2 . 4-2 compressor</p> </li> <li> <p>DESIGN OF 5-2 COMPRESSOR</p> <p>It has seven inputs, five of which are direct and two of which</p> <p>are carry- in bits from a previous stage. Similarly, there are four outputs, two of which are carry-out bits to the next stage and other two are sum and carry bits.</p> <p>Fig 2.3. 5-2 Compressor</p> </li> <li> <p>DESIGN OF 7-2 COMPRESSOR</p> </li> </ol> </ol> <p>A 7-2 Compressor used for high-density multiplexing. It is implemented by using 3-2 Compressors (FA). It has seven primary inputs x1, x2, x3, x4, x5, x6 and x7.Sum and Carry are the outputs of the Compressor. Here Cin1, Cin2, Cin3 and Cin4 are Carry inputs from the previous compressor and Cout1, Cout2, Cout3 and Cout4 are Carry outputs to the next compressor.</p> <p>Fig 2.4. 7-2 Compressor</p> <p>3.ADDERS</p> <ol> <ol> <li> <p>PARALLEL ADDERS</p> <p>Parallel adders are made up of cascading n full adders. The parallel adder is used to find the sum of two binary numbers that are greater than one bit when all full adders are linked in a chain. The carry output is connected to the carry input of the following full adder. The time required for addition is independent of the number of bits. The main advantage of using a parallel adder is the speed with which it processes data.</p> <p>Fig 3.1. Parallel Adder</p> <ol> <li> <p>CARRY LOOK-AHEAD ADDER (CLA)</p> <p>A Carry look-ahead adder is a fast adder, a type of electronics adder used in digital logic. It is primarily used to reduce the amount of time required to determine the carry bits. It calculates one or more carry bits before the sum, which reduces the time it takes to calculate the result of the adders larger value bits. As the number of bits increases, so does the complexity. The output carry at any stage is solely determined by the first or beginning stages initial carry bit. This adder isthe fastest in terms of Computation.</p> <p>Fig 3.1.1. Architecture of 4-Bit Carry Look-Ahead Adder</p> </li> <li> <p>CARRY SELECT ADDER (CSLA)</p> <p>CSLA is used in many data processing processors to perform fast arithmetic functions. Area,power and dealy can be reduced by gate level modification of CSLA architecture. The carry-select adder consists of ripple-carry adders and a multiplexers. It generates the output for possible two values of Cin ( 0 and 1). But the correct sum and correct carry-out are selected with the help of multiplexer once the correct carry-in is known.</p> <p>Fig 3.1.2. Architecture of 4-bit Carry Select Adder</p> </li> </ol> </li> <li> <p>PARALLEL PREFIX ADDERS</p> </li> </ol> </ol> <p>These are fast adders with high performance.The addition in this adder is accomplished through the use of the prefix operation. The tree structure is used to boost speed.These are equivalent to CLA. Implementation of Carry generation block is the main difference between them. These are fastest adders which are used for high performance arithmetic circuits in industries.</p> <p>This procedure can be carried out in three stages:</p> <ol> <li> <p>Pre-processing Stage</p> </li> <li> <p>Carry generation Stage</p> </li> <li> <p>Post processing Stage</p> </li> </ol> <p>Simply in these stages it gets the inputs and produces the generate and propagate signals.Then, it takes up two pairs of generate and propagate signals and continues the computation and finally it finds the carry using which results the sum output.</p> <p>Pre-Processing Stage:</p> <p>In this stage,A and B are the inputs, and we compute the generate and propagate signals to generate the carry input of each adder.</p> <p>Pi=Ai XOR Bi Gi=Ai AND Bi</p> <p>Carry Generation Stage:</p> <p>At this stage, we generate cerry by using intermediae signals such as propagated and generate bits.Carry operations that correspond to each other are carried out in parallel,resulting in carries that are computed into smaller bits.</p> <p>G[i:j] = G[i:k] OR P[i:k] AND G[k-1:j] <p>P[i:j] =P[i:k] AND P[k-1:j] <p>Post-Processing Stage:</p> <p>At this stage the calculation of final sum and carry are done.</p> <p>Si=Pi XOR Ci-1</p> <p>Ci = G[i:0] OR (Cin AND P[i:0])</p> <p>Fig 3.2. Basic block for Parallel Prefix Adder</p> <ol> <ol> <ol> <li> <p>KOGGESTONE ADDER(KSA)</p> <p>The Koggestone adder architecture is commonly used in logical circuits for high performance.A parallel prefix adder derived from a carry look-ahead adder is the Koggestone.It could be considered the fastest design. The most significant advantage of using Koggestone is the minimal fanout or logic depth.As a result, the Kogge stone becomes fast and takes up a large amount of space.</p> <p>The entire function of the Kogeestone is divided into three stages:</p> <ol> <li> <p>Pre-processing Stage:This step entails calculating propagate and generate bits (Pi,Gi) for inputs A and B.</p> <p>Pi=Ai XOR Bi Gi=Ai AND Bi</p> </li> <li> <p>Carry Generation Stage :It is the most important stage,in which carries corresponding to each bit are computed and a group of generated and propagated bits is used.</p> <p>P[i:j] = P[i:k+1] AND P[k:j] <p>G[i:j] = G[i:k+1] OR (P[i:k+1 AND G[k:j])</p> </li> <li> <p>Post processing Stage : This is the final common step for all adders of the same kind.</p> </li> </ol> <p>Si = Pi XOR Ci-1</p> <p>Ci = Gi</p> <p>Fig 3.2.1. Functioning of 4-bit Koggestone Adder</p> </li> <li> <p>BRENT-KUNG ADDER</p> </li> </ol> </ol> </ol> <p>Brent-Kung is a parallel prefix adder created with carry-look ahead adder.It is designed to reduce chip area and ease of manufacturing. The Brent-Kung adder isa good balance between area, power and cost.It takes less area to implement</p> <p>than the Koggestone adder,since the adder uses a limited number of propagate and generaate cells than the KSA.The cost and wiring complexity is less in Brent-Kung adders.It is the most widely used Parallel prefix adder.It is significantly faster than ripple-carry adders.</p> <p>Brent-Kung adders complete function is divided into three stages:</p> <ol> <li> <p>Pre-processing Stage : It generates Pi and Gi at this stage.</p> <p>Pi=Ai XOR Bi Gi=Ai AND Bi</p> </li> <li> <p>Prefix Carry Stage : The received signal from the first stage is passed on to the next stage ,yielding all carry bit signals.</p> <p>There are three types of cells present at this stage: black cells, grey cells and buffer cells.</p> <p>G[i:j] = G[i:k] OR P[i:k] AND G[k-1:j] <p>P[i:j] =P[i:k] AND P[k-1:j] </li> <li> <p>Post-processing Stage : This is the final stage here,the exclusive or is performed between Pi and Ci-1.</p> <p>Si = Pi XOR Ci-1</p> <p>Ci = Gi OR Pi AND Ci-1 (or) Ci = Gi</p> <p>Fig 3.2.2. Functioning of 4-bit Brent-Kung Adder</p> <p>4.MULTIPLIER</p> <p>A Binary Multiplier is an electronic circuit usd in digital electronis that is used to multiply two binary numbers.A digital Multiplier is used to implement various arthimetic techniques.So in order to implement the proposed multiplier Wallace Tree Approach is used. Generally, the method we use for multiplication is based on calculating partial products, shifting them to the left, and then adding them together.The most diffcult part is obtaining partial products, which requires multiplying a large number by one.</p> <p>4.1 WALLACE TREE APPROACH</p> <p>For multiplication, we used the wallace tree approach in this paper.Simply put, the Wallace tree mutliplier is a hardware implementation of a binary multiplier that can multiply two integers. A high-speed multiplier is the Wallace tree multiplier.It is typically used in low-power applications.Parallel multipliers are the high speed multipliers.Therefore, the enhaced speed of the multiplication operation is achieved using different methods and Wallace tree is one of the methods.</p> <p>The multiplier architecture is divided into three parts: 1.Generation of partial product</p> <ol> <li> <p>Partial production addition</p> </li> <li> <p>Final addition</p> </li> </ol> </li> </ol> <p>In the first stage of multiplication process after the generation of partial products.Half adders, Full adder(3-2),4-2,5-2 and 7:2 Compressors are used to reduce the partial products for fast multiplication. The sum anfd carry signals from the HA , FA and compressors are passed to the next stage.The resulting sum and carry out of the last stage is added using adder at final stage.</p> <p>6. COMPARISION OF RESULTS BY ADDERS BASED ON DIFFERENT PARAMETERS</p> <p>The multiplication is performed by adders KOGGESTONE ADDER, BRENT-KUNG ADDER, CARRY LOOK-AHEAD</p> <p>ADDER, CARRY SELECT ADDER the results are obtained and the final results are comparedd based on different parameters such as delay, power, IOB(Input Output Buffer), LUTs and Slices.The obtained results for different bits of adders are given below</p> <p>CARRY LOOK-AHEAD ADDER</p> <p>CARRY SELECT ADDER</p> <p>KOGGESTONE ADDER</p> <p>BRUNT-KUNG ADDER</p> <p>COMPARISON OF PARAMETERS 7.CONCLUSION</p> <p>The partial products generated from the mulplication of two 32-bit numbers are added with different adders by employing compressors and several characteristics of all adders are compared.It is observed that Brent-Kung Adder is the best for adding these partial products.Its delay,total power consumption,Bounded IOB,LUTs and Slice are relatively less when compared to other adders.</p> <p>8.REFERENCES</p> [1] K.Gopi Krishna, B.Santhosh, V.Sridhar,International Journal of Engineering Sciences & Research Technology(september 2013),Design Of Wallace Tree Using Compressors.</p> [2] Jinimol P George and Ramesh P Department of ECE, Wallace Tree Multiplier using Compressor, Cochin University for Science and Technology, Kerala, India.International Journal of Current Enginnering and Technology, Vol.5, No.3 (June 2015).</p> [3] Prathima Gamini, Mullangi Pavan Kumar, Bala Manikanta Pulleti, Pachigilla Phani Sai Pradeep, Signed Booth Multiplier using various types of adders, 2019, Journal of Adv Research in Dynamical and ControlSystems Volume 11.</p> [4] G.Challa Ram, D.Sudha Rani, R.Nalasaikesava, K.Bala Sindhuri, Design of Delay Efficient Modified 16 bit Wallace Multiplier, IEEE International Conference on Recent Trends In Electronics Information Communication Technology, 2016, India.</p> [5] Vinoth, C.VS Kanchana Bhaaskaran,B.Brindha,S. Sakthikumaran, V. Kavinilavu, B.Bhaskar, M. Kanagasabapathy, and B. Sharath.A Novel Low Power and High-Speed Wallace Tree Multiplier for RISC Processor, IEEE,2011.</p> [6] Bhavani Koyada, N.Meghana, Md.Omair Jaleel and Praneet Raj Jeripotula.A Comparative Study on Adders,MGIT,JNTUH,Hyderabad.IEEE WiSPNET 2017 conference.</p> [7] Harish Kumar, Hemanth Kumar A R ,Design and Implementation of Vedic Multiplier using Compressors, International Journal of Engineering Research & Technology (IJERT), Bangalore Institute of Technology, India,2015.</p> [8] Sarnala Butchibabu, Sannikanti Kishore Babu, Design and Implementation of Efficient Parallel Prefix Adders on FPGA, International Journal of Engineering & Technology (IJERT), 2014.</p> [9] Anku Bala, Rajesh Mehra, Area Efficient Design Analysis of Carry Look Ahead Adder, International Journal of Computer Applications,June 2015.</p> [10] A. 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