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</div> <div class='descriptionwrapper'> <p class='description'><span>Computer history, restoring vintage computers, IC reverse engineering, and whatever</span></p> </div> </div> </div></div> </div> </div> <div class='header-cap-bottom cap-bottom'> <div class='cap-left'></div> <div class='cap-right'></div> </div> </div> </header> <div class='tabs-outer'> <div class='tabs-cap-top cap-top'> <div class='cap-left'></div> <div class='cap-right'></div> </div> <div class='fauxborder-left tabs-fauxborder-left'> <div class='fauxborder-right tabs-fauxborder-right'></div> <div class='region-inner tabs-inner'> <div class='tabs no-items section' id='crosscol'></div> <div class='tabs no-items section' id='crosscol-overflow'></div> </div> </div> <div class='tabs-cap-bottom cap-bottom'> <div class='cap-left'></div> <div class='cap-right'></div> </div> </div> <div class='main-outer'> <div class='main-cap-top cap-top'> <div class='cap-left'></div> <div class='cap-right'></div> </div> <div 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class='cap-right'></div> </div> <div class='fauxborder-left'> <div class='fauxborder-right'></div> <div class='fauxcolumn-inner'> </div> </div> <div class='cap-bottom'> <div class='cap-left'></div> <div class='cap-right'></div> </div> </div>  <div class='columns-inner'> <div class='column-center-outer'> <div class='column-center-inner'> <div class='main section' id='main'><div class='widget Blog' data-version='1' id='Blog1'> <div class='blog-posts hfeed'> <div class="date-outer"> <div class="date-posts"> <div class='post-outer'> <div class='post hentry' itemprop='blogPost' itemscope='itemscope' itemtype='http://schema.org/BlogPosting'> <meta content='https://static.righto.com/images/8086-length/die-labeled-w600.jpg' itemprop='image_url'/> <meta content='6264947694886887540' itemprop='blogId'/> <meta content='5529658376547613898' itemprop='postId'/> <a name='5529658376547613898'></a> <h3 class='post-title entry-title' itemprop='name'> <a href='http://www.righto.com/2023/02/how-8086-processor-determines-length-of.html'>How the 8086 processor determines the length of an instruction</a> </h3> <div class='post-header'> <div class='post-header-line-1'></div> </div> <div class='post-body entry-content' id='post-body-5529658376547613898' itemprop='description articleBody'> <style> .hilite {cursor:zoom-in} a:link img.hilite, a:visited img.hilite {color: #fff;} a:hover img.hilite {color: #f66;} </style> <style> pre.microcode {font-family: courier, fixed; padding: 10px; background-color: #f5f5f5; display:inline-block;border:none;} pre.microcode span {color: green; font-style:italic; font-family: sans-serif; font-size: 90%;} </style> <p>The Intel 8086 processor (1978) has a complicated instruction set with instructions ranging from one to six bytes long. This raises the question of how the processor knows the length of an instruction.<span id="fnref:stackoverflow"><a class="ref" href="#fn:stackoverflow">1</a></span> The answer is that the 8086 uses an interesting combination of lookup ROMs and microcode to determine how many bytes to use for an instruction. In brief, the ROMs perform enough decoding to figure out if it needs one byte or two. After that, the microcode simply consumes instruction bytes as it needs them. Thus, nothing in the chip explicitly "knows" the length of an instruction. This blog post describes this process in more detail.</p> <p>The die photo below shows the chip under a microscope. I've labeled the key functional blocks; the ones that are important to this post are darker. Architecturally, the chip is partitioned into a Bus Interface Unit (BIU) at the top and an Execution Unit (EU) below. The BIU handles bus and memory activity as well as instruction prefetching, while the Execution Unit (EU) executes the instructions.</p> <p><a href="https://static.righto.com/images/8086-length/die-labeled.jpg"><img alt="The 8086 die under a microscope, with main functional blocks labeled. This photo shows the chip with the metal and polysilicon removed, revealing the silicon underneath. Click on this image (or any other) for a larger version." class="hilite" height="627" src="https://static.righto.com/images/8086-length/die-labeled-w600.jpg" title="The 8086 die under a microscope, with main functional blocks labeled. This photo shows the chip with the metal and polysilicon removed, revealing the silicon underneath. Click on this image (or any other) for a larger version." width="600" /></a><div class="cite">The 8086 die under a microscope, with main functional blocks labeled. This photo shows the chip with the metal and polysilicon removed, revealing the silicon underneath. Click on this image (or any other) for a larger version.</div></p> <h2>The prefetch queue, the loader, and the microcode</h2> <p>The 8086 uses a 6-byte instruction prefetch queue to hold instructions, and this queue will play an important role in this discussion.<span id="fnref:8088"><a class="ref" href="#fn:8088">3</a></span> Earlier microprocessors read instructions from memory as they were needed, which could cause the CPU to wait on memory. The 8086, instead, read instructions from memory before they were needed, storing them in the instruction prefetch queue. (You can think of this as a primitive instruction cache.) To execute an instruction, the 8086 took bytes out of the queue one at a time. If the queue ran empty, the processor waited until more instruction bytes were fetched from memory into the queue.</p> <p>A circuit called the loader handles the interaction between the prefetch queue and instruction execution. The loader is a small state machine that provides control signals to the rest of the execution circuitry. The loader gets the first byte of an instruction from the prefetch queue and issues a signal FC (First Clock) that starts execution of the instruction.</p> <p>At this point, the Group Decode ROM performs the first stage of instruction decoding, classifying the instruction into various categories based on the opcode byte. Most of the 8086's instructions are implemented in microcode. However, a few instructions are so simple that they are implemented with logic circuits. For example, the <code>CLC</code> (Clear Carry) instruction clears the carry flag directly. The Group Decode ROM categorizes these instructions as 1BL (one-byte, implemented in logic). The loader responds by issuing an SC (Second Clock) signal to wrap up execution and start the next instruction. Thus, these simple instructions take two clock cycles.</p> <p>The 8086 has various prefix bytes that can be put in front of an instruction to change its behavior. For instance, a segment prefix changes the memory segment that the instruction uses. A <code>LOCK</code> prefix locks the bus during the next instruction. The Group Decode ROM detects a prefix and outputs a prefix signal. This causes the prefix to be handled in logic, rather than microcode, similar to the 1BL instructions. Thus, a prefix also takes one byte and two clock cycles.</p> <p>The remaining instructions are handled by microcode.<span id="fnref:microcode"><a class="ref" href="#fn:microcode">2</a></span> Let's start with a one-byte instruction such as <code>INC AX</code>, which increments the <code>AX</code> register. As before, the loader gets the instruction byte from the prefix queue. The Group Decode ROM determines that this instruction is implemented in microcode and can start after one byte, so the microcode engine starts running. The microcode below handles the increment and decrement instructions. It moves the appropriate register, indicated by <code>M</code> to the ALU's temporary B register. It puts the incremented or decremented result (危) back into the register (<code>M</code>). <code>RNI</code> tells the loader to run the next instruction. With two micro-instruction, this instruction takes two clock cycles.</p> <pre class="microcode"> M → tmpB XI tmpB, NX <span><b>INC/DEC</b>: get value from M, set up ALU</span> 危 → M WB,RNI F <span>put result in M, run next instruction</span> </pre> <p>But what happens with an instruction that is more than one byte long, such as adding an immediate value to a register? Let's look at <code>ADD AX,1234</code>, which adds 1234 to the AX register. As before, the loader reads one byte and then the microcode engine starts running. At this point, the 8086 doesn't "realize" that this is a 3-byte instruction. The first line of the microcode below gets one byte of the immediate operand: <code>Q→tmpBL</code> loads a byte from the instruction prefetch queue into the low byte of the temporary B register. Similarly, the second line loads the second byte. The next line puts the register value (<code>M</code>) in <code>tmpA</code>. The last line puts the sum back into the register and runs the next instruction. Since this instruction takes two bytes from the prefetch queue, it is three bytes long in total. But nothing explicitly indicates this instruction is three bytes long.</p> <pre class="microcode"> Q → tmpBL JMPS L8 2 <span><b>alu A,i</b>: get byte from queue</span> Q → tmpBH <span>get byte from queue</span> M → tmpA XI tmpA, NX <span>get value from M, set up ALU</span> 危 → M WB,RNI F <span>put result in M, run next instruction</span> </pre> <p>You can also add a one-byte immediate value to a register, such as <code>ADD AL,12</code>. This uses the same microcode above. However, in the first line, <code>JMPS L8</code> is a conditional jump that skips the second micro-instruction if the data length is 8 bits. Thus, the microcode only consumes one byte from the prefetch queue, making the instruction two bytes long. In other words, what makes this instruction two bytes instead of three is the bit in the opcode which triggers the conditional jump in the microcode.</p> <p>The 8086 has another class of instructions, those with a ModR/M byte following the opcode. The Group Decode ROM classifies these instructions as 2BR (two-byte ROM) indicating that the second byte must be fetched before processing by the microcode ROM. For these instructions, the loader fetches the second byte from the prefetch queue before triggering the SC (Second Clock signal) to start microcode execution.</p> <p>The ModR/M byte indicates the addressing mode that the instruction should use, such as register-to-register or memory-to-register. The ModR/M can change the instruction length by specifying an address displacement of one or two bytes. A second ROM called the Translation ROM selects the appropriate microcode for the addressing mode (<a href="http://www.righto.com/2023/02/8086-modrm-addressing.html">details</a>). For example, if the addressing mode includes an address displacement, the microcode below is used:</p> <pre class="microcode"> Q → tmpBL JMPS MOD1 12 <span><b>[i]</b>: get byte(s)</span> Q → tmpBH 危 → tmpA BX EAFINISH <span><b>12</b>: add displacement</span> </pre> <p>This microcode fetches two displacement bytes from the prefetch queue (<code>Q</code>). However, if the ModR/M byte specifies a one-byte displacement, the <code>MOD1</code> condition causes the microcode to jump over the second fetch. Thus, this microcode uses one or two additional instruction bytes depending on the value of the <code>ModR/M</code> byte.</p> <p>To summarize, nothing in the 8086 "knows" how long an instruction is. The Group Decode ROM makes part of the decision, classifying instructions as a prefix, 1-byte logic, 2-byte ROM, or otherwise, causing the loader to fetch one or two bytes. The microcode then consumes instruction bytes as needed. In the end, the length of an 8086 instruction is determined by how many bytes are taken from the prefetch queue by the time it ends.</p> <h2>Some other systems</h2> <p>It's interesting to see how other processors deal with instruction length. For example, RISC processors (Reduced Instruction Set Computers) typically have fixed-length instructions. For instance, the ARM-1 processor used 32-bit instructions, making instruction decoding very simple.</p> <p>Early microprocessors such as the MOS Technology 6502 (1975) didn't use microcode, but were controlled by state machines. The CPU fetches instruction bytes from memory as needed, as it moves through various execution states. Thus, as with the 8086, the length of an instruction wasn't explicit, but was how many bytes it used.</p> <p>The IBM 1401 computer (1959) took a completely different approach with its variable-length words. Each character in memory had an associated "word mark" bit, which you can think of as a metadata bit. Each machine instruction consisted of a variable number of characters with a word mark on the first one. Thus, the processor could read instruction characters until it hit a word mark, which indicated the start of the next instruction. The word mark explicitly indicated to the processor how long each instruction was.</p> <p>Perhaps the worst approach for variable-length instructions was the Intel iAPX 432 processor (1981), which had instructions with variable <em>bit</em> lengths, from 6 to 321 bits long. As a result, instructions weren't aligned on byte boundaries, making instruction decoding even more inconvenient. This was just one of the reasons that the iAPX 432 ended up overly complicated, years behind schedule, and a commercial failure.</p>  <p>The 8086's variable-length instructions led to the x86 architecture, with instructions from 1 to 15 bytes long. This is particularly inconvenient with modern superscalar processors that run multiple instructions in parallel. The problem is that the processor must break the instruction stream into individual instructions before they execute. The Intel P6 microarchitecture used in the Pentium Pro (1995) has instruction decoders to decode the instruction stream into micro-operations.<span id="fnref:p6"><a class="ref" href="#fn:p6">4</a></span> It starts with an "instruction length block" that analyzes the first bytes of the instruction to determine how long it is. (This is not a straightforward task to perform rapidly on multiple instructions in parallel.) The "instruction steering block" uses this information to break the byte stream into instructions and steer instructions to the decoders.</p> <p>The AMD K6 3D processor (1999) had predecode logic that associated 5 predecode bits with each instruction byte: three pointed to the start of the next instruction, one indicated the length depended on a D bit, and one indicated the presence of a ModR/M byte. This logic examined up to three bytes to make its decisions. Instructions were split apart and assigned to decoders based on the predecode bits. In some cases, the predecode logic gave up and flagged the instruction as "unsuccessfully predecoded", for instance an instruction longer than 7 bytes. These instructions were handled by a slower path.</p> <h2>Conclusions</h2> <p>The 8086 processor has instructions with a variety of lengths, but nothing in the processor explicitly determines the length. Instead, an instruction uses as many bytes as it needs. (That sounds sort of tautological, but I'm not sure how else to put it.) The Group Decode ROM makes an initial classification, the Translation ROM determines the addressing mode, and the microcode consumes bytes as needed.</p> <p>While this approach gave the 8086 a flexible instruction set, it created a problem in the long run for the x86 architecture, requiring complicated logic to determine instruction length. One benefit of RISC-based processors such as the Apple M1 is that they have (mostly) constant instruction lengths, making instruction decoding faster and simpler.</p> <p>I've written multiple <a href="https://www.righto.com/search/label/8086">posts on the 8086</a> so far and plan to continue reverse-engineering the 8086 die so follow me on Twitter <a href="https://twitter.com/kenshirriff">@kenshirriff</a> or <a href="http://www.righto.com/feeds/posts/default">RSS</a> for updates. I've also started experimenting with Mastodon recently as <a href="https://oldbytes.space/@kenshirriff">@oldbytes.space@kenshirriff</a>.</p> <h2>Notes and references</h2> <div class="footnote"> <ol> <li id="fn:stackoverflow"> <p>I was inspired to investigate instruction length based on a <a href="https://stackoverflow.com/questions/25101978/how-does-the-cpu-assembler-know-the-size-of-the-next-instruction">Stack Overflow question</a>. <a class="footnote-backref" href="#fnref:stackoverflow" title="Jump back to footnote 1 in the text">↩</a></p> </li> <li id="fn:microcode"> <p>I'll just give a brief overview of microcode here. Each micro-instruction is 21 bits long, as shown below. A micro-instruction specifies a move between a source register and destination register. It also has an action that depends on the micro-instruction type. For more details, see my post on the <a href="https://www.righto.com/2023/01/the-8086-processors-microcode-pipeline.html">8086 microcode pipeline</a>.</p> <p><a href="https://static.righto.com/images/8086-length/microcode-format.jpg"><img alt="The encoding of a micro-instruction into 21 bits. Based on NEC v. Intel: Will Hardware Be Drawn into the Black Hole of Copyright?" class="hilite" height="203" src="https://static.righto.com/images/8086-length/microcode-format-w700.jpg" title="The encoding of a micro-instruction into 21 bits. Based on NEC v. Intel: Will Hardware Be Drawn into the Black Hole of Copyright?" width="700" /></a><div class="cite">The encoding of a micro-instruction into 21 bits. Based on <a href="https://digitalcommons.law.scu.edu/cgi/viewcontent.cgi?referer=&httpsredir=1&article=1031&context=chtlj">NEC v. Intel: Will Hardware Be Drawn into the Black Hole of Copyright?</a></div></p> <p> <a class="footnote-backref" href="#fnref:microcode" title="Jump back to footnote 2 in the text">↩</a></p> </li> <li id="fn:8088"> <p>The 8088 processor, used in the original IBM PC, has a smaller 4-byte prefetch queue. The 8088 is almost the same as the 8086, except it has an 8-bit external bus instead of a 16-bit external bus. This makes memory accesses (including prefetches) slower, so a smaller prefetch queue works better. <a class="footnote-backref" href="#fnref:8088" title="Jump back to footnote 3 in the text">↩</a></p> </li> <li id="fn:p6"> <p>The book <a href="https://amzn.to/3Z6UYE6">Modern Processor Design</a> discusses the P6 microarchitecture in detail. The book <a href="https://amzn.to/3KE94sr">The Anatomy of a High-Performance Microprocessor</a> discusses the AMD K5 3D processor in even more detail; see chapter 2. <a class="footnote-backref" href="#fnref:p6" title="Jump back to footnote 4 in the text">↩</a></p> </li> </ol> </div> <div style='clear: both;'></div> </div> <div class='post-footer'> <div class='post-footer-line post-footer-line-1'><span class='post-comment-link'> <a class='comment-link' href='https://www.blogger.com/comment/fullpage/post/6264947694886887540/5529658376547613898' onclick=''> 5 comments: </a> </span> <span class='post-icons'> <span class='item-action'> <a href='https://www.blogger.com/email-post/6264947694886887540/5529658376547613898' title='Email Post'> <img alt='' class='icon-action' height='13' src='http://img1.blogblog.com/img/icon18_email.gif' width='18'/> </a> </span> <span class='item-control blog-admin pid-1138732533'> <a href='https://www.blogger.com/post-edit.g?blogID=6264947694886887540&postID=5529658376547613898&from=pencil' title='Edit Post'> <img alt='' class='icon-action' height='18' src='https://resources.blogblog.com/img/icon18_edit_allbkg.gif' width='18'/> </a> </span> </span> <span class='post-backlinks post-comment-link'> </span> <div class='post-share-buttons goog-inline-block'> <a class='goog-inline-block share-button sb-email' href='https://www.blogger.com/share-post.g?blogID=6264947694886887540&postID=5529658376547613898&target=email' target='_blank' title='Email This'><span class='share-button-link-text'>Email This</span></a><a class='goog-inline-block share-button sb-blog' href='https://www.blogger.com/share-post.g?blogID=6264947694886887540&postID=5529658376547613898&target=blog' onclick='window.open(this.href, "_blank", "height=270,width=475"); return false;' target='_blank' title='BlogThis!'><span class='share-button-link-text'>BlogThis!</span></a><a class='goog-inline-block share-button sb-twitter' href='https://www.blogger.com/share-post.g?blogID=6264947694886887540&postID=5529658376547613898&target=twitter' target='_blank' title='Share to X'><span class='share-button-link-text'>Share to X</span></a><a class='goog-inline-block share-button sb-facebook' href='https://www.blogger.com/share-post.g?blogID=6264947694886887540&postID=5529658376547613898&target=facebook' onclick='window.open(this.href, "_blank", "height=430,width=640"); return false;' target='_blank' title='Share to Facebook'><span class='share-button-link-text'>Share to Facebook</span></a><a class='goog-inline-block share-button sb-pinterest' href='https://www.blogger.com/share-post.g?blogID=6264947694886887540&postID=5529658376547613898&target=pinterest' target='_blank' title='Share to Pinterest'><span class='share-button-link-text'>Share to Pinterest</span></a> </div> </div> <div class='post-footer-line post-footer-line-2'><span class='post-labels'> Labels: <a href='http://www.righto.com/search/label/8086' rel='tag'>8086</a>, <a href='http://www.righto.com/search/label/chips' rel='tag'>chips</a>, <a href='http://www.righto.com/search/label/microcode' rel='tag'>microcode</a>, <a href='http://www.righto.com/search/label/reverse-engineering' rel='tag'>reverse-engineering</a> </span> </div> <div class='post-footer-line post-footer-line-3'></div> </div> </div> </div> </div></div> <div class="date-outer"> <div class="date-posts"> <div class='post-outer'> <div class='post hentry' itemprop='blogPost' itemscope='itemscope' itemtype='http://schema.org/BlogPosting'> <meta content='https://static.righto.com/images/8086-addressing/die-labeled-w600.jpg' itemprop='image_url'/> <meta content='6264947694886887540' itemprop='blogId'/> <meta content='8745122849902587790' itemprop='postId'/> <a name='8745122849902587790'></a> <h3 class='post-title entry-title' itemprop='name'> <a href='http://www.righto.com/2023/02/8086-modrm-addressing.html'>Reverse-engineering the ModR/M addressing microcode in the Intel 8086 processor</a> </h3> <div class='post-header'> <div class='post-header-line-1'></div> </div> <div class='post-body entry-content' id='post-body-8745122849902587790' itemprop='description articleBody'> <style> .hilite {cursor:zoom-in} a:link img.hilite, a:visited img.hilite {color: #fff;} a:hover img.hilite {color: #f66;} </style> <style> pre.microcode {font-family: courier, fixed; padding: 10px; background-color: #f5f5f5; display:inline-block;} pre.microcode span {color: green; font-style:italic; font-family: sans-serif; font-size: 90%;} </style> <p>One interesting aspect of a computer's instruction set is its addressing modes, how the computer determines the address for a memory access. The Intel 8086 (1978) used the <a href="https://en.wikipedia.org/wiki/ModR/M">ModR/M</a> byte, a special byte following the opcode, to select the addressing mode.<span id="fnref:immediate"><a class="ref" href="#fn:immediate">1</a></span> The ModR/M byte has persisted into the modern x86 architecture, so it's interesting to look at its roots and original implementation.</p> <p>In this post, I look at the hardware and microcode in the 8086 that implements ModR/M<span id="fnref:modes"><a class="ref" href="#fn:modes">2</a></span> and how the 8086 designers fit multiple addressing modes into the 8086's limited microcode ROM. One technique was a hybrid approach that combined generic microcode with hardware logic that filled in the details for a particular instruction. A second technique was modular microcode, with subroutines for various parts of the task.</p> <p>I've been reverse-engineering the 8086 starting with the silicon die. The die photo below shows the chip under a microscope. The metal layer on top of the chip is visible, with the silicon and polysilicon mostly hidden underneath. Around the edges of the die, bond wires connect pads to the chip's 40 external pins. I've labeled the key functional blocks; the ones that are important to this discussion are darker and will be discussed in detail below. Architecturally, the chip is partitioned into a Bus Interface Unit (BIU) at the top and an Execution Unit (EU) below. The BIU handles bus and memory activity as well as instruction prefetching, while the Execution Unit (EU) executes instructions and microcode. Both units play important roles in memory addressing.</p> <p><a href="https://static.righto.com/images/8086-addressing/die-labeled.jpg"><img alt="The 8086 die under a microscope, with main functional blocks labeled. This photo shows the chip's single metal layer; the polysilicon and silicon are underneath. Click on this image (or any other) for a larger version." class="hilite" height="622" src="https://static.righto.com/images/8086-addressing/die-labeled-w600.jpg" title="The 8086 die under a microscope, with main functional blocks labeled. This photo shows the chip's single metal layer; the polysilicon and silicon are underneath. Click on this image (or any other) for a larger version." width="600" /></a><div class="cite">The 8086 die under a microscope, with main functional blocks labeled. This photo shows the chip's single metal layer; the polysilicon and silicon are underneath. Click on this image (or any other) for a larger version.</div></p> <h2>8086 addressing modes</h2> <p>Let's start with an addition instruction, <code>ADD</code> <em>dst</em>,<em>src</em>, which adds a source value to a destination value and stores the result in the destination.<span id="fnref:assembly"><a class="ref" href="#fn:assembly">3</a></span> What are the source and destination? Memory? Registers? The addressing mode answers this question.</p> <p>You can use a register as the source and another register as the destination. The instruction below uses the <code>AX</code> register as the destination and the <code>BX</code> register as the source. Thus, it adds <code>BX</code> to <code>AX</code> and puts the result in <code>AX</code>.</p> <pre class="microcode"> ADD AX, BX <span>Add the contents of the BX register to the AX register</span> </pre> <p>A memory access is indicated with square brackets around the "effective address"<span id="fnref:effective-address"><a class="ref" href="#fn:effective-address">4</a></span> to access. For instance, <code>[1234]</code> means the memory location with address 1234, while <code>[BP]</code> means the memory location that the <code>BP</code> register points to. For a more complicated addressing mode, <code>[BP+SI+1234]</code> means the memory location is determined by adding the BP and SI registers to the constant 1234 (known as the displacement). On the 8086, you can use memory for the source or the destination, but not both. Here are some examples of using memory as a source:</p> <pre class="microcode"> ADD AX, [1234] <span>Add the contents of memory location 1234 to AX register</span> ADD CX, [BP] <span>Add memory pointed to by BP register to CX register</span> ADD DX, [BX+SI+1234] <span>Source memory address is BX + SI + constant 1234</span> </pre> <p>Here are examples with memory as the destination:</p> <pre class="microcode"> ADD [1234], AX <span>Add AX to the contents of memory location 1234</span> ADD [BP], CX <span>Add CX to memory pointed to by BP register</span> ADD [BX+SI+1234], DX <span>Destination memory address is BX + SI + constant 1234</span> </pre> <p>You can also operate on bytes instead of words, using a byte register and accessing a memory byte:</p> <pre class="microcode"> ADD AL, [SI+1234] <span>Add to the low byte of AX register</span> ADD AH, [BP+DI+1234] <span>Add to the high byte of AX register</span> </pre> <p>As you can see, the 8086 supports many different addressing schemes. To understand how they are implemented, we must first look at how instructions encode the addressing schemes in the ModR/M byte.</p> <h2>The ModR/M byte</h2> <p>The ModR/M byte follows many opcodes to specify the addressing mode. This byte is fairly complicated but I'll try to explain it in this section. The diagram below shows how the byte is split into three fields:<span id="fnref:octal"><a class="ref" href="#fn:octal">5</a></span> <code>mod</code> selects the overall mode, <code>reg</code> selects a register, and <code>r/m</code> selects either a register or memory mode.</p> <style type="text/css"> table.modrm {border-collapse:collapse; border: 2px solid #999; padding: 5px;} table.modrm th {border: 2px solid #999;} table.modrm th,td {padding: 2px 9px;} table.modrm td {border-left: 2px solid #999;} table.modrm .bl {border-left: 3px solid #999;} table.modrm .c {text-align: center;} table.modrm .r {color: red;} table.modrm .g {color: green;} table.modrm .b {color: blue;} </style> <table class="modrm"> <tr><th class="r" colspan=2>mod</th><th class="g" colspan=3>reg</th><th class="b" colspan=3>r/m</th><tr> <tr><td class="r">7</td><td class="r">6</td><td class="g">5</td><td class="g">4</td><td class="g">3</td><td class="b">2</td><td class="b">1</td><td class="b">0</td></tr> </table> <p>I'll start with the register-register mode, where the <code>mod</code> bits are <span style="color:red">11</span> and the <code>reg</code> and <code>r/m</code> fields each select one of eight registers, as shown below. The instruction <code>ADD AX,BX</code> would use <code>reg</code>=<span style="color:green">011</span> to select <code>BX</code> and <code>r/m</code>=<span style="color:blue">000</span> to select <code>AX</code>, so the ModR/M byte would be <span style="color:red">11</span/g><span style="color:green">011</span/g><span style="color:blue">000</span/g>. (The register assignment depends on whether the instruction operates on words, bytes, or segment registers. For instance, in a word instruction, <code>001</code> selects the <code>CX</code> register, while in a byte instruction, <code>001</code> selects the <code>CL</code> register, the low byte of <code>CX</code>.)</p> <p><a href="https://static.righto.com/images/8086-addressing/reg-assignments.jpg"><img alt="The register assignments, from MCS-86 Assembly Language Reference Guide." class="hilite" height="189" src="https://static.righto.com/images/8086-addressing/reg-assignments-w400.jpg" title="The register assignments, from MCS-86 Assembly Language Reference Guide." width="400" /></a><div class="cite">The register assignments, from <a href="http://bitsavers.org/components/intel/8086/9800749-1_MCS-86_Assembly_Language_Reference_Guide_Oct78.pdf">MCS-86 Assembly Language Reference Guide</a>.</div></p> <p>The next addressing mode specifies a memory argument and a register argument. In this case, the <code>mod</code> bits are <span style="color:red">00</span>, the <code>reg</code> field specifies a register as described above, and the <code>r/m</code> field specifies a memory address according to the table below. For example, the instruction <code>ADD [SI],CX</code> would use <code>reg</code>=<span style="color:green">001</span> to select <code>CX</code> and <code>r/m</code>=<span style="color:blue">100</span> to select <code>[SI]</code>, so the ModR/M byte would be <span style="color:red">00</span/g><span style="color:green">001</span/g><span style="color:blue">100</span/g>.</p> <style type="text/css"> table.rm td:first-child {color:blue} table.rm td:nth-child(2) {padding-left: 2em;} </style> <table class="modrm rm"> <tr><th>r/m</th><th>Operand Address</th></tr> <tr><td>000</td><td>[BX+SI]</td></tr> <tr><td>001</td><td>[BX+DI]</td></tr> <tr><td>010</td><td>[BP+SI]</td></tr> <tr><td>011</td><td>[BP+DI]</td></tr> <tr><td>100</td><td>[SI]</td></tr> <tr><td>101</td><td>[DI]</td></tr> <tr><td>110</td><td>[BP]</td></tr> <tr><td>111</td><td>[BX]</td></tr> </table> <p>The next mode, <span style="color:red">01</span>, adds an 8-bit signed displacement to the address. This displacement consists of one byte following the ModR/M byte. This supports addressing modes such as <code>[BP+5]</code>. The mode <span style="color:red">10</span> is similar except the displacement is two bytes long, for addressing modes such as <code>[BP+DI+0x1234]</code>.</p>  <p>The table below shows the meaning of all 256 values for the ModR/M byte. The <code>mod</code> bits are colored red, the <code>reg</code> bits green, and the <code>r/m</code> bits blue. Note the special case "disp16" to support a 16-bit fixed address.</p> <p><a href="https://static.righto.com/images/8086-addressing/modrm.png"><img alt="The ModR/M values. Note that this table would be trivial if it used octal rather than hexadecimal. Based on Table 6-13 in the ASM386 Assembly Language Reference." class="hilite" height="619" src="https://static.righto.com/images/8086-addressing/modrm-w600.png" title="The ModR/M values. Note that this table would be trivial if it used octal rather than hexadecimal. Based on Table 6-13 in the ASM386 Assembly Language Reference." width="600" /></a><div class="cite">The ModR/M values. Note that this table would be trivial if it used octal rather than hexadecimal. Based on Table 6-13 in the <a href="http://bitsavers.org/pdf/intel/iRMX/iRMX_III/iRMX_III_V2.2/469165-003_ASM386_Assembly_Language_Reference_1995.pdf">ASM386 Assembly Language Reference</a>.</div></p> <p>The register combinations for memory accesses may seem random but they were designed to support the needs of high-level languages, such as arrays and data structures. The idea is to add a base register, an index register, and/or a fixed displacement to determine the address.<span id="fnref:system360"><a class="ref" href="#fn:system360">6</a></span> The base register can indicate the start of an array, the index register holds the offset in the array, and the displacement provides the offset of a field in the array entry. The base register is <code>BX</code> for data or <code>BP</code> for information on the stack. The index registers are <code>SI</code> (Source Index) and <code>DI</code> (Destination Index).<span id="fnref:modrm"><a class="ref" href="#fn:modrm">7</a></span></p> <p>Some addressing features are handled by the opcode, not the ModR/M byte. For instance, the ModR/M byte doesn't distinguish between <code>ADD AX,[SI]</code> and <code>ADD [SI],AX</code>. Instead, the two variants are distinguished by bit 1 of the instruction, the <code>D</code> or "direction" bit.<span id="fnref:destination"><a class="ref" href="#fn:destination">8</a></span> Moreover, many instructions have one opcode that operates on words and another that operates on bytes, distinguished by bit 0 of the opcode, the <code>W</code> or word bit.</p> <p>The <code>D</code> and <code>W</code> bits are an example of orthogonality in the 8086 instruction set, allowing features to be combined in various combinations. For instance, the addressing modes combine 8 types of offset computation with three sizes of displacements and 8 target registers. Arithmetic instructions combine these addressing modes with eight ALU operations, each of which can act on a byte or a word, with two possible memory directions. All of these combinations are implemented with one block of microcode, implementing a large instruction set with a small amount of microcode. (The orthogonality of the 8086 shouldn't be overstated, though; it has many special cases and things that don't quite fit.)</p> <h2>An overview of 8086 microcode</h2> <p>Most people think of machine instructions as the basic steps that a computer performs. However, many processors (including the 8086) have another layer of software underneath: microcode. With microcode, instead of building the control circuitry from complex logic gates, the control logic is largely replaced with code. To execute a machine instruction, the computer internally executes several simpler micro-instructions, specified by the microcode.</p> <p>The 8086 uses a hybrid approach: although it uses microcode, much of the instruction functionality is implemented with gate logic. This approach removed duplication from the microcode and kept the microcode small enough for 1978 technology. In a sense, the microcode is parameterized. For instance, the microcode can specify a generic Arithmetic/Logic Unit (ALU) operation and a generic register. The gate logic examines the instruction to determine which specific operation to perform and the appropriate register.</p> <p>A micro-instruction in the 8086 is encoded into 21 bits as shown below. Every micro-instruction has a move from a source register to a destination register, each specified with 5 bits. The meaning of the remaining bits depends on the type field. A "short jump" is a conditional jump within the current block of 16 micro-instructions. An ALU operation sets up the arithmetic-logic unit to perform an operation. Bookkeeping operations are anything from flushing the prefetch queue to ending the current instruction. A memory operation triggers a bus cycle to read or write memory. A "long jump" is a conditional jump to any of 16 fixed microcode locations (specified in an external table called the Translation ROM). Finally, a "long call" is a conditional subroutine call to one of 16 locations. For more about 8086 microcode, see my <a href="https://www.righto.com/2022/11/how-8086-processors-microcode-engine.html">microcode blog post</a>.</p> <p><a href="https://static.righto.com/images/8086-addressing/microcode-format.jpg"><img alt="The encoding of a micro-instruction into 21 bits. Based on NEC v. Intel: Will Hardware Be Drawn into the Black Hole of Copyright?" class="hilite" height="203" src="https://static.righto.com/images/8086-addressing/microcode-format-w700.jpg" title="The encoding of a micro-instruction into 21 bits. Based on NEC v. Intel: Will Hardware Be Drawn into the Black Hole of Copyright?" width="700" /></a><div class="cite">The encoding of a micro-instruction into 21 bits. Based on <a href="https://digitalcommons.law.scu.edu/cgi/viewcontent.cgi?referer=&httpsredir=1&article=1031&context=chtlj">NEC v. Intel: Will Hardware Be Drawn into the Black Hole of Copyright?</a></div></p> <h2>Some examples of microcode for addressing</h2> <p>In this section, I'll take a close look at a few addressing modes and how they are implemented in microcode. In the next section, I'll summarize all the microcode for addressing modes.</p> <h3>A register-register operation</h3> <p>Let's start by looking at a register-to-register instruction, before we get into the complications of memory accesses: <code>ADD BX,AX</code> which adds <code>AX</code> to <code>BX</code>, storing the result in <code>BX</code>. This instruction has the opcode value 01 and ModR/M value C3 (hex). </p> <p>Before the microcode starts, the hardware performs some decoding of the opcode. The Group Decode ROM (below) classifies an instruction into multiple categories: this instruction contains a D bit, a W bit, and an ALU operation, and has a ModR/M byte. Fields from the opcode and ModR/M bytes are extracted and stored in various internal registers. The ALU operation type (<code>ADD</code>) is stored in the <code>ALU opr</code> register. From the ModR/M byte, the <code>reg</code> register code (<code>AX</code>) is stored in the <code>N</code> register, and the <code>r/m</code> register code (<code>BX</code>) is stored in the <code>M</code> register. (The <code>M</code> and <code>N</code> registers are internal registers that are invisible to the programmer; each holds a 5-bit register code that specifies a register.<span id="fnref:mn"><a class="ref" href="#fn:mn">9</a></span>)</p> <p><a href="https://static.righto.com/images/8086-addressing/group-decode-rom.jpg"><img alt="This diagram shows the Group Decode ROM. The Group Decode ROM is more of a PLA (programmable logic array) with two layers of NOR gates. Its input lines are at the lower left and its outputs are at the upper right." class="hilite" height="482" src="https://static.righto.com/images/8086-addressing/group-decode-rom-w500.jpg" title="This diagram shows the Group Decode ROM. The Group Decode ROM is more of a PLA (programmable logic array) with two layers of NOR gates. Its input lines are at the lower left and its outputs are at the upper right." width="500" /></a><div class="cite">This diagram shows the Group Decode ROM. The Group Decode ROM is more of a PLA (programmable logic array) with two layers of NOR gates. Its input lines are at the lower left and its outputs are at the upper right.</div></p> <p>Once the preliminary decoding is done, the microcode below for this ALU instruction is executed.<span id="fnref:microcode"><a class="ref" href="#fn:microcode">10</a></span> (There are three micro-instructions, so the instruction takes three clock cycles.) Each micro-instruction contains a move and an action. First, the register specified by <code>M</code> (i.e. <code>BX</code>) is moved to the ALU's temporary A register (<code>tmpA</code>). Meanwhile, the ALU is configured to perform the appropriate operation on <code>tmpA</code>; <code>XI</code> indicates that the ALU operation is specified by the instruction bits, i.e. <code>ADD</code>).</p> <p>The second instruction moves the register specified by <code>N</code> (i.e. <code>AX</code>) to the ALU's <code>tmpB</code> register. The action <code>NX</code> indicates that this is the next-to-last micro-instruction so the microcode engine can start processing the next machine instruction. The last micro-instruction stores the ALU's result (<code>危</code>) in the register indicated by <code>M</code> (i.e. <code>BX</code>). The status flags are updated because of the <code>F</code>. <code>WB,RNI</code> (Run Next Instruction) indicates that this is the end and the microcode engine can process the next machine instruction. The <code>WB</code> prefix would skip the actions if a memory writeback were pending (which is not the case).</p> <pre class="microcode"> move action M → tmpA XI tmpA <span><b>ALU rm↔r</b>: BX to tmpA</span> N → tmpB WB,NX <span>AX to tmpB</span> 危 → M WB,RNI F <span>result to BX, run next instruction.</span> </pre> <p>This microcode packs a lot into three micro-instructions. Note that it is very generic: the microcode doesn't know what ALU operation is being performed or which registers are being used. Instead, the microcode deals with abstract registers and operations, while the hardware fills in the details using bits from the instructions. The same microcode is used for eight different ALU operations. And as we'll see, it supports multiple addressing modes.</p> <h3>Using memory as the destination</h3> <p>Memory operations on the 8086 involve both microcode and hardware. A memory operation uses two internal registers: <code>IND</code> (Indirect) holds the memory address, while <code>OPR</code> (Operand) holds the word that is read or written. A typical memory micro-instruction is <code>R DS,P0</code>, which starts a read from the Data Segment with a "Plus 0" on the <code>IND</code> register afterward. The Bus Interface Unit carries out this operation by adding the segment register to compute the physical address, and then running the memory bus cycles.</p> <p>With that background, let's look at the instruction <code>ADD [SI],AX</code>, which adds <code>AX</code> to the memory location indexed by <code>SI</code>. As before, the hardware performs some analysis of the instruction (hex 01 04). In the ModR/M byte, mod=00 (memory, no displacement), reg=000 (AX), and R/M=100 ([SI]). The <code>N</code> register is loaded with the code for <code>AX</code> as before. The <code>M</code> register, however, is loaded with <code>OPR</code> (the memory data register) since the Group Decode ROM determines that the instruction has a memory addressing mode.</p> <p>The microcode below starts in an effective address microcode subroutine for the <code>[SI]</code> mode. The first line of the microcode subroutine computes the effective address simply by loading the <code>tmpA</code> register with <code>SI</code>. It jumps to the micro-routine <code>EAOFFSET</code> which ends up at <code>EALOAD</code> (for reasons that will be described below), which loads the value from memory. Specifically, <code>EALOAD</code> puts the address in <code>IND</code>, reads the value from memory, puts the value into <code>tmpB</code>, and returns from the subroutine.</p> <pre class="microcode"> SI → tmpA JMP EAOFFSET <span><b>[SI]</b>: put SI in tmpA</span> tmpA → IND R DS,P0 <span><b>EALOAD</b>: read memory</b></span> OPR → tmpB RTN M → tmpA XI tmpA <span><b>ALU rm↔r</b>: OPR to tmpA</span> N → tmpB WB,NX <span>AX to tmpB</span> 危 → M WB,RNI F <span>result to BX, run next instruction.</span> W DS,P0 RNI <span>writes result to memory</span> </pre> <p>Microcode execution continues with the <code>ALU rm↔r</code> routine described above, but with a few differences. The <code>M</code> register indicates <code>OPR</code>, so the value read from memory is put into <code>tmpA</code>. As before, the <code>N</code> register specifies <code>AX</code>, so that register is put into <code>tmpB</code>. In this case, the <code>WB,NX</code> determines that the result will be written back to memory so it skips the <code>NXT</code> operation. The ALU's result (<code>危</code>) is stored in <code>OPR</code> as directed by <code>M</code>. The <code>WB,RNI</code> is skipped so microcode execution continues. The <code>W DS,P0</code> micro-instruction writes the result (in <code>OPR</code>) to the memory address in <code>IND</code>. At this point, <code>RNI</code> terminates the microcode sequence.</p> <p>A lot is going on here to add two numbers! The main point is that the same microcode runs as in the register case, but the results are different due to the <code>M</code> register and the conditional <code>WB</code> code. By running different subroutines, different effective address computations can be performed.</p>  <h3>Using memory as the source</h3> <p>Now let's look at how the microcode uses memory as a source, as in the instruction <code>ADD AX,[SI]</code>. This instruction (hex 03 04) has the same ModR/M byte as before, so the <code>N</code> register holds <code>AX</code> and the <code>M</code> register holds <code>OPR</code>. However, because the opcode has the D bit set, the <code>M</code> and <code>N</code> registers are swapped when accessed. Thus, when the microcode uses <code>M</code>, it gets the value <code>AX</code> from <code>N</code>, and vice versa. (Yes, this is confusing.)</p> <p>The microcode starts the same as the previous example, reading <code>[SI]</code> into <code>tmpB</code> and returning to the ALU code. However, since the meaning of <code>M</code> and <code>N</code> are reversed, the AX value goes into <code>tmpA</code> while the memory value goes into <code>tmpB</code>. (This switch doesn't matter for addition, but would matter for subtraction.) An important difference is that there is no writeback to memory, so <code>WB,NX</code> starts processing the next machine instruction. In the last micro-instruction, the result is written to <code>M</code>, indicating the <code>AX</code> register. Finally, <code>WB,RNI</code> runs the next machine instruction.</p> <pre class="microcode"> SI → tmpA JMP EAOFFSET <span><b>[SI]</b>: put SI in tmpA</span> tmpA → IND R DS,P0 <span><b>EALOAD: read memory</b></span> OPR → tmpB RTN M → tmpA XI tmpA <span><b>ALU rm↔r</b>: AX to tmpA</span> N → tmpB WB,NX <span>OPR to tmpB</span> 危 → M WB,RNI F <span>result to AX, run next instruction.</span> </pre> <p>The main point is that the same microcode handles memory as a source and a destination, simply by setting the <code>D</code> bit. First, the <code>D</code> bit reverses the operands by swapping <code>M</code> and <code>N</code>. Second, the <code>WB</code> conditionals prevent the writeback to memory that happened in the previous case.</p>   <h3>Using a displacement</h3> <p>The memory addressing modes optionally support a signed displacement of one or two bytes. Let's look at the instruction <code>ADD AX,[SI+0x1234]</code>. In hex, this instruction is 03 84 34 12, where the last two bytes are the displacement, reversed because the 8086 uses little-endian numbers. The mod bits are 10, indicating a 16-bit displacement, but the other bits are the same as in the previous example.</p> <p>Microcode execution again starts with the <code>[SI]</code> subroutine. However, the jump to <code>EAOFFSET</code> goes to <code>[i]</code> this time, to handle the displacement offset. (I'll explain how, shortly.) This code loads the offset as two bytes from the instruction prefetch queue (<code>Q</code>) into the <code>tmpB</code> register. It adds the offset to the previous address in <code>tmpA</code> and puts the sum 危 in <code>tmpA</code>, computing the effective address. Then it jumps to <code>EAFINISH</code> (<code>EALOAD</code>). From there, the code continues as earlier, reading an argument from memory and computing the sum.</p> <pre class="microcode"> SI → tmpA JMP EAOFFSET <span><b>[SI]</b>: put SI in tmpA</span> Q → tmpBL JMPS MOD1 12 <span><b>[i]</b>: load from queue, conditional jump</span> Q → tmpBH 危 → tmpA JMP EAFINISH <span><b>12</b>:</span> tmpA → IND R DS,P0 <span><b>EALOAD: read memory</b></span> OPR → tmpB RTN M → tmpA XI tmpA <span><b>ALU rm↔r</b>: AX to tmpA</span> N → tmpB WB,NX <span>OPR to tmpB</span> 危 → M WB,RNI F <span>result to AX, run next instruction.</span> </pre> <p>For the one-byte displacement case, the conditional <code>MOD1</code> will jump over the fetch of the second displacement byte. When the first byte is loaded into the low byte of <code>tmpB</code>, it was sign-extended into the high byte.<span id="fnref:sign"><a class="ref" href="#fn:sign">14</a></span> Thus, the one-byte displacement case uses the same microcode but ends up with a sign-extended 1-byte displacement in <code>tmpB</code>.</p> <h2>The Translation ROM</h2> <p>Now let's take a closer look at the jumps to <code>EAOFFSET</code>, <code>EAFINISH</code>, and the effective address subroutines, which use something called the Translation ROM. The Translation ROM converts the 5-bit jump tag in a micro-instruction into a 13-bit microcode address. It also provides the addresses of the effective address subroutines. As will be seen below, there are some complications.<span id="fnref:translation-pla"><a class="ref" href="#fn:translation-pla">11</a></span></p> <p><a href="https://static.righto.com/images/8086-addressing/translation-rom.jpg"><img alt="The Translation ROM as it appears on the die. The metal layer has been removed to expose the silicon and polysilicon underneath. The left half decodes the inputs to select a row. The right half outputs the corresponding microcode address." class="hilite" height="636" src="https://static.righto.com/images/8086-addressing/translation-rom-w350.jpg" title="The Translation ROM as it appears on the die. The metal layer has been removed to expose the silicon and polysilicon underneath. The left half decodes the inputs to select a row. The right half outputs the corresponding microcode address." width="350" /></a><div class="cite">The Translation ROM as it appears on the die. The metal layer has been removed to expose the silicon and polysilicon underneath. The left half decodes the inputs to select a row. The right half outputs the corresponding microcode address.</div></p> <h2>The effective address micro-routines</h2> <h3>Register calculations</h3> <p>The Translation ROM has an entry for the addressing mode calculations such as <code>[SI]</code> and <code>[BP+DI]</code>, generally indicated by the <code>r/m</code> bits, the three low bits of the ModR/M byte. Each routine computes the effective address and puts it into the ALU's temporary A register and jumps to <code>EAOFFSET</code>, which adds any displacement offset. The microcode below shows the four simplest effective address calculations, which just load the appropriate register into <code>tmpA</code>.</p> <pre class="microcode"> SI → tmpA JMP EAOFFSET <span><b>[SI]</b>: load SI into tmpA</span> DI → tmpA JMP EAOFFSET <span><b>[DI]</b>: load SI into tmpA</span> BP → tmpA JMP EAOFFSET <span><b>[BP]</b>: load BP into tmpA</span> BX → tmpA JMP EAOFFSET <span><b>[BX]</b>: load BX into tmpA</span> </pre> <p>For the cases below, an addition is required, so the registers are loaded into the ALU's temporary A and temporary B registers. The effective address is the sum (indicated by 危), which is moved to temporary A.<span id="fnref:alu-default"><a class="ref" href="#fn:alu-default">12</a></span> These routines are carefully arranged in memory so <code>[BX+DI]</code> and <code>[BP+SI]</code> each execute one micro-instruction and then jump into the middle of the other routines, saving code.<span id="fnref:timing"><a class="ref" href="#fn:timing">13</a></span></p> <pre class="microcode"> BX → tmpA <span><b>[BX+SI]</b>: get regs</span> SI → tmpB <span><b>1</b>:</span> 危 → tmpA JMP EAOFFSET BP → tmpA <span><b>[BP+DI]</b>: get regs</span> DI → tmpB <span><b>4</b>:</span> 危 → tmpA JMP EAOFFSET BX → tmpA JMPS 4 <span><b>[BX+DI]</b>: short jump to 4</span> BP → tmpA JMPS 1 <span><b>[BP+SI]</b>: short jump to 1</span> </pre> <h3>The <code>EAOFFSET</code> and <code>EAFINISH</code> targets</h3> <p>After computing the register portion of the effective address, the routines above jump to <code>EAOFFSET</code>, but this is not a fixed target. Instead, the Translation ROM selects one of three target microcode addresses based on the instruction and the ModR/M byte: <br/>If there's a displacement, the microcode jumps to <code>[i]</code> to add the displacement value. <br/>If there is no displacement but a memory read, the microcode otherwise jumps to <code>EALOAD</code> to load the memory contents. <br/>If there is no displacement and no memory read should take place, the microcode jumps to <code>EADONE</code>. <br/>In other words, the microcode jump is a three-way branch that is implemented by the Translation ROM and is transparent to the microcode.</p> <p>For a displacement, the <code>[i]</code> immediate code below loads a 1-byte or 2-byte displacement into the <code>tmpB</code> register and adds it to the <code>tmpA</code> register, as described earlier. At the end of a displacement calculation, the microcode jumps to the <code>EAFINISH</code> tag, which is another branching target. Based on the instruction, the Translation ROM selects one of two microcode targets: <code>EALOAD</code> to load from memory, or <code>EADONE</code> to skip the load.</p> <pre class="microcode"> Q → tmpBL JMPS MOD1 12 <span><b>[i]</b>: get byte(s)</span> Q → tmpBH 危 → tmpA JMP EAFINISH <span><b>12</b>: add displacement</span> </pre> <p>The <code>EALOAD</code> microcode below reads the value from memory, using the effective address in <code>tmpA</code>. It puts the result in <code>tmpB</code>. The <code>RTN</code> micro-instruction returns to the microcode that implements the original machine instruction.</p> <pre class="microcode"> tmpA → IND R DS,P0 <span><b>EALOAD</b>: read from tmpA address</span> OPR → tmpB RTN <span>store result in tmpB, return</span> </pre> <p>The <code>EADONE</code> routine puts the effective address in <code>IND</code>, but it doesn't read from the memory location. This supports machine instructions such as <code>MOV</code> (some moves) and <code>LEA</code> (Load Effective Address) that don't read from memory</p> <pre class="microcode"> tmpA → IND RTN <span><b>EADONE</b>: store effective address in IND</span> </pre> <p>To summarize, the microcode runs different subroutines and different paths, depending on the addressing mode, executing the appropriate code. The Translation ROM selects the appropriate control flow path.</p> <h2>Special cases</h2> <p>There are a couple of special cases in addressing that I will discuss in this section.</p> <h3>Supporting a fixed address</h3> <p>It is common to access a fixed memory address, but the standard addressing modes use a base or index register. The 8086 replaces the mode of <code>[BP]</code> with no displacement with 16-bit fixed addressing. In other words, a ModR/M byte with the pattern <code>00xxx110</code> is treated specially. (This special case is the orange <code>disp16</code> line in the ModR/M table earlier.) This is implemented in the Translation ROM which has additional rows to detect this pattern and execute the immediate word <code>[iw]</code> microcode below instead. This microcode fetches a word from the instruction prefetch queue (<code>Q</code>) into the <code>tmpA</code> register, a byte at a time. It jumps to <code>EAFINISH</code> instead of <code>EAOFFSET</code> because it doesn't make sense to add another displacement.</p> <pre class="microcode"> Q → tmpAL <span><b>[iw]</b>: get bytes</span> Q → tmpAH JMP EAFINISH </pre> <h3>Selecting the segment</h3> <p>Memory accesses in the 8086 are relative to one of the 64-kilobyte segments: Data Segment, Code Segment, Stack Segment, or Extra Segment. Most addressing modes use the Data Segment by default. However, addressing modes that use the <code>BP</code> register use the Stack Segment by default. This is a sensible choice since the <code>BP</code> (Base Pointer) register is intended for accessing values on the stack. </p> <p>This special case is implemented in the Translation ROM. It has an extra output bit that indicates that the addressing mode should use the Stack Segment. Since the Translation ROM is already decoding the addressing mode to select the right microcode routine, adding one more output bit is straightforward. This bit goes to the segment register selection circuitry, changing the default segment. This circuitry also handles prefixes that change the segment. Thus, segment register selection is handled in hardware without any action by the microcode.</p> <h2>Conclusions</h2> <p>I hope you have enjoyed this tour through the depths of 8086 microcode. The effective address calculation in the 8086 uses a combination of microcode and logic circuitry to implement a variety of addressing methods. Special cases make the addressing modes more useful, but make the circuitry more complicated. This shows the CISC (Complex Instruction Set Computer) philosophy of x86, making the instructions complicated but highly functional. In contrast, the RISC (Reduced Instruction Set Computer) philosophy takes the opposite approach, making the instructions simpler but allowing the processor to run faster. RISC vs. CISC was a big debate of the 1980s, but isn't as relevant nowadays.</p> <p>People often ask if microcode could be updated on the 8086. Microcode was hardcoded into the ROM, so it could not be changed. This became a big problem for Intel with the famous Pentium <a href="https://en.wikipedia.org/wiki/Pentium_FDIV_bug">floating-point division bug</a>. The Pentium chip turned out to have a bug that resulted in rare but serious errors when dividing. Intel recalled the defective processors in 1994 and replaced them at a cost of $475 million. Starting with the Pentium Pro (1995), microcode could be patched at boot time, a useful feature that persists in modern CPUs.</p> <p>I've written multiple <a href="https://www.righto.com/search/label/8086">posts on the 8086</a> so far and plan to continue reverse-engineering the 8086 die so follow me on Twitter <a href="https://twitter.com/kenshirriff">@kenshirriff</a> or <a href="http://www.righto.com/feeds/posts/default">RSS</a> for updates. I've also started experimenting with Mastodon recently as <a href="https://oldbytes.space/@kenshirriff">@oldbytes.space@kenshirriff</a>.</p> <h2>Notes and references</h2> <div class="footnote"> <ol> <li id="fn:immediate"> <p>There are additional addressing modes that don't use a ModR/M byte. For instance, immediate instructions use a constant in the instruction. For instance <code>ADD AX,42</code> adds 42 to the AX register. Other instructions implicitly define the addressing mode. I'm ignoring these instructions for now. <a class="footnote-backref" href="#fnref:immediate" title="Jump back to footnote 1 in the text">↩</a></p> </li> <li id="fn:modes"> <p>The 8086 supports more addressing modes than the ModR/M byte provides, by using separate opcodes. For instance, arithmetic instructions can take an "immediate" value, an 8- or 16-bit value specified as part of the instruction. Other instructions operate on specific registers rather than memory or access memory through the stack. For this blog post, I'm focusing on the ModR/M modes and ignoring the other instructions. Also, although I'm discussing the 8086, this blog post applies to the Intel 8088 processor as well. The 8088 has an 8-bit bus, a smaller prefetch queue, and some minor internal changes, but for this post you can consider them to be the same. <a class="footnote-backref" href="#fnref:modes" title="Jump back to footnote 2 in the text">↩</a></p> </li> <li id="fn:assembly"> <p>My assembly code examples are based on Intel <a href="http://www.bitsavers.org/pdf/intel/ISIS_II/121703-003_ASM86_Language_Reference_Manual_Nov83.pdf">ASM86 assembly</a> syntax. There's a completely different format of x86 assembly language known as <a href="https://www.cs.mcgill.ca/~cs573/winter2001/AttLinux_syntax.htm">AT&T syntax</a>. Confusingly, it reverses the source and destination. For example, in AT&T syntax, <code>addw %bx, %cx%</code> stores the result in CX. AT&T syntax is widely used, for instance in Linux code. The AT&T syntax is based on earlier <a href="https://stackoverflow.com/a/42250270/3073190">PDP-11 assembly code</a>. <a class="footnote-backref" href="#fnref:assembly" title="Jump back to footnote 3 in the text">↩</a></p> </li> <li id="fn:effective-address"> <p>The term "effective address" dates back to the 1950s, when computers moved beyond fixed memory addresses and started using index registers. The earliest uses that I could find are from 1955 for the <a href="http://www.bitsavers.org/pdf/ibm/650/22-6258-0_FeaturesIdxAccum.pdf">IBM 650</a> data processing machine and the <a href="http://bitsavers.org/pdf/ibm/704/24-6661-2_704_Manual_1955.pdf">IBM 704</a> mainframe. The "Load Effective Address" instruction, which provides the effective address as a value instead of performing the memory access, was perhaps introduced in the IBM System/360 (1964) under the name "Load Address". It has been a part of many subsequent processors including the 8086. <a class="footnote-backref" href="#fnref:effective-address" title="Jump back to footnote 4 in the text">↩</a></p> </li> <li id="fn:octal"> <p>Note that the ModR/M byte has the bits grouped in threes (as do many instructions). This is due to the octal heritage of the 8086, dating back through the 8080 and the 8008 to the Datapoint 2200 (which used TTL chips to decode groups of three bits). Although the 8086 instruction set is invariably described in hexadecimal, it makes much more sense when viewed in octal. See <a href="https://gist.github.com/seanjensengrey/f971c20d05d4d0efc0781f2f3c0353da">x86 is an octal machine</a> for details. <a class="footnote-backref" href="#fnref:octal" title="Jump back to footnote 5 in the text">↩</a></p> </li> <li id="fn:system360"> <p>The 8086's addressing schemes are reminiscent of the IBM System/360 (1964). In particular, System/360 had a "RX" instruction format that accessed memory through a base register plus an index register plus a displacement, using another register for the other argument. This is very similar to the 8086's base + index + displacement method. The System/360's "RR" (register-register) instruction format accessed two registers, much like the register mode of the ModR/M byte. The details are very different, though, between the two systems. See the <a href="http://bitsavers.trailing-edge.com/pdf/ibm/360/princOps/A22-6821-0_360PrincOps.pdf">IBM System/360 Principles of Operation</a> for more details. <a class="footnote-backref" href="#fnref:system360" title="Jump back to footnote 6 in the text">↩</a></p> </li> <li id="fn:modrm"> <p>The motivation behind the ModR/M options is discussed in <a href="https://amzn.to/3m6VCmI">The 8086/8088 Primer</a> by 8086 designer Steve Morse, pages 23-33. <a class="footnote-backref" href="#fnref:modrm" title="Jump back to footnote 7 in the text">↩</a></p> </li> <li id="fn:destination"> <p>The D bit is usually called the register direction bit, but the designer of the 8086 instruction set calls it the destination field; see <a href="https://amzn.to/3m6VCmI">The 8086/8088 Primer</a>, Steve Morse, page 28. To summarize: <br/>If the bit is 0, the result is stored into the location indicated by the <code>mod</code> and <code>r/m</code> fields while the register specified by <code>reg</code> is the source. <br/>If the bit is 1, the result is stored into the register indicated by the <code>reg</code> field.</p> <p>For the <code>W</code> word bit, 0 indicates a byte operation and 1 indicates a word operation.</p> <p>One curious side-effect of the D bit is that an instruction like <code>ADD AX,BX</code> can be implemented in two ways since both arguments are registers. The <code>reg</code> field can specify <code>AX</code> while the <code>r/m</code> field specifies <code>BX</code> or vice versa, depending on the D bit. Different 8086 assemblers can be "fingerprinted" based on their decisions in these ambiguous cases. <a class="footnote-backref" href="#fnref:destination" title="Jump back to footnote 8 in the text">↩</a></p> </li> <li id="fn:mn"> <p>The M and N registers hold a 5-bit code. This code indicates a 16-bit register (e.g. <code>AX</code> or <code>IND</code>), an 8-bit register (e.g. <code>AL</code>), or a special value (e.g. <code>危</code>, the ALU result; <code>ZEROS</code>, all zero bits; or <code>F</code>, the flags). The 3-bit register specification is mapped onto the 5-bit code depending on whether the W bit is set (byte or word register), or if the operation is specifying a segment register. <a class="footnote-backref" href="#fnref:mn" title="Jump back to footnote 9 in the text">↩</a></p> </li> <li id="fn:microcode"> <p>The microcode listings are based on Andrew Jenner's <a href="https://www.reenigne.org/blog/8086-microcode-disassembled/">disassembly</a>. I have made some modifications to (hopefully) make it easier to understand. <a class="footnote-backref" href="#fnref:microcode" title="Jump back to footnote 10 in the text">↩</a></p> </li> <li id="fn:translation-pla"> <p>You can also view the Translation ROM as a PLA (Programmable Logic Array) constructed from two layers of NOR gates. The conditional entries make it seem more like a PLA than a ROM. Technically, it can be considered a ROM since a single row is active at a time. I'm using the name "Translation ROM" because that's what Intel calls it in the patents. <a class="footnote-backref" href="#fnref:translation-pla" title="Jump back to footnote 11 in the text">↩</a></p> </li> <li id="fn:alu-default"> <p>Normally, an ALU operation requires a micro-instruction to specify the desired ALU operation and temporary register. For the address addition, the ALU operation is not explicitly specified because it uses the ALU's default, of adding <code>tmpA</code> and <code>tmpB</code>. The ALU is reset to this default at the beginning of each machine instruction. <a class="footnote-backref" href="#fnref:alu-default" title="Jump back to footnote 12 in the text">↩</a></p> </li> <li id="fn:timing"> <p>A microcode jump takes an extra clock cycle for the microcode address register to get updated. This is why, for instance, <code>[BP+DI]</code> takes 7 clock cycles but <code>[BX+DI]</code> takes 8 clock cycles. Thus, the 8086 implementers took the tradeoff of slowing down some addressing modes by a clock cycle in order to save a few micro-instructions in the small microcode ROM.</p> <p><a href="https://static.righto.com/images/8086-addressing/ea-timing.jpg"><img alt="This table shows the clock cycles required for effective address calculations. From MCS-86 Assembly Language Reference Guide." class="hilite" height="162" src="https://static.righto.com/images/8086-addressing/ea-timing-w400.jpg" title="This table shows the clock cycles required for effective address calculations. From MCS-86 Assembly Language Reference Guide." width="400" /></a><div class="cite">This table shows the clock cycles required for effective address calculations. From <a href="http://bitsavers.org/components/intel/8086/9800749-1_MCS-86_Assembly_Language_Reference_Guide_Oct78.pdf">MCS-86 Assembly Language Reference Guide</a>.</div></p> <p> <a class="footnote-backref" href="#fnref:timing" title="Jump back to footnote 13 in the text">↩</a></p> </li> <li id="fn:sign"> <p>A one-byte signed number can be sign-extended into a two-byte signed number. This is done by copying the top bit (the sign) from the low byte and filling the top byte with that bit. For example, 0x64 is sign-extended to 0x0064 (+100), while 0x9c is sign-extended to 0xff9c (-100). <a class="footnote-backref" href="#fnref:sign" title="Jump back to footnote 14 in the text">↩</a></p> </li> </ol> </div> <div style='clear: both;'></div> </div> <div class='post-footer'> <div class='post-footer-line post-footer-line-1'><span class='post-comment-link'> <a class='comment-link' href='https://www.blogger.com/comment/fullpage/post/6264947694886887540/8745122849902587790' onclick=''> 7 comments: </a> </span> <span class='post-icons'> <span class='item-action'> <a href='https://www.blogger.com/email-post/6264947694886887540/8745122849902587790' title='Email Post'> <img alt='' class='icon-action' height='13' src='http://img1.blogblog.com/img/icon18_email.gif' width='18'/> </a> </span> <span class='item-control blog-admin pid-1138732533'> <a href='https://www.blogger.com/post-edit.g?blogID=6264947694886887540&postID=8745122849902587790&from=pencil' title='Edit Post'> <img alt='' class='icon-action' height='18' src='https://resources.blogblog.com/img/icon18_edit_allbkg.gif' width='18'/> </a> </span> </span> <span class='post-backlinks post-comment-link'> </span> <div class='post-share-buttons goog-inline-block'> <a class='goog-inline-block share-button sb-email' href='https://www.blogger.com/share-post.g?blogID=6264947694886887540&postID=8745122849902587790&target=email' target='_blank' title='Email This'><span class='share-button-link-text'>Email This</span></a><a class='goog-inline-block share-button sb-blog' href='https://www.blogger.com/share-post.g?blogID=6264947694886887540&postID=8745122849902587790&target=blog' onclick='window.open(this.href, "_blank", "height=270,width=475"); return false;' target='_blank' title='BlogThis!'><span class='share-button-link-text'>BlogThis!</span></a><a class='goog-inline-block share-button sb-twitter' href='https://www.blogger.com/share-post.g?blogID=6264947694886887540&postID=8745122849902587790&target=twitter' target='_blank' title='Share to X'><span class='share-button-link-text'>Share to X</span></a><a class='goog-inline-block share-button sb-facebook' href='https://www.blogger.com/share-post.g?blogID=6264947694886887540&postID=8745122849902587790&target=facebook' onclick='window.open(this.href, "_blank", "height=430,width=640"); return false;' target='_blank' title='Share to Facebook'><span class='share-button-link-text'>Share to Facebook</span></a><a class='goog-inline-block share-button sb-pinterest' href='https://www.blogger.com/share-post.g?blogID=6264947694886887540&postID=8745122849902587790&target=pinterest' target='_blank' title='Share to Pinterest'><span class='share-button-link-text'>Share to Pinterest</span></a> </div> </div> <div class='post-footer-line post-footer-line-2'><span class='post-labels'> Labels: <a href='http://www.righto.com/search/label/8086' rel='tag'>8086</a>, <a href='http://www.righto.com/search/label/microcode' rel='tag'>microcode</a>, <a href='http://www.righto.com/search/label/reverse-engineering' rel='tag'>reverse-engineering</a> </span> </div> <div class='post-footer-line post-footer-line-3'></div> </div> </div> </div> </div></div> <div class="date-outer"> <div class="date-posts"> <div class='post-outer'> <div class='post hentry' itemprop='blogPost' itemscope='itemscope' itemtype='http://schema.org/BlogPosting'> <meta content='https://static.righto.com/images/8086-interrupts/die-labeled-w600.jpg' itemprop='image_url'/> <meta content='6264947694886887540' itemprop='blogId'/> <meta content='6015138995640807347' itemprop='postId'/> <a name='6015138995640807347'></a> <h3 class='post-title entry-title' itemprop='name'> <a href='http://www.righto.com/2023/02/8086-interrupt.html'>Reverse-engineering the interrupt circuitry in the Intel 8086 processor</a> </h3> <div class='post-header'> <div class='post-header-line-1'></div> </div> <div class='post-body entry-content' id='post-body-6015138995640807347' itemprop='description articleBody'> <style> .hilite {cursor:zoom-in} a:link img.hilite, a:visited img.hilite {color: #fff;} a:hover img.hilite {color: #f66;} </style> <p>Interrupts have been an important part of computers since the mid-1950s,<span id="fnref:history"><a class="ref" href="#fn:history">1</a></span> providing a mechanism to interrupt a program's execution. Interrupts allows the computer to handle time-critical tasks such as I/O device operations. In this blog post, I look at the interrupt features in the Intel 8086 (1978) and how they are implemented in silicon, a combination of interesting circuitry and microcode.</p> <p>I've been reverse-engineering the 8086 starting with the silicon die. The die photo below shows the chip under a microscope. The metal layer on top of the chip is visible, with the silicon and polysilicon mostly hidden underneath. Around the edges of the die, bond wires connect pads to the chip's 40 external pins; relevant pins are marked in yellow. I've labeled the key functional blocks; the ones that are important to this discussion are darker and will be discussed in detail below. Architecturally, the chip is partitioned into a Bus Interface Unit (BIU) at the top and an Execution Unit (EU) below. The BIU handles bus activity, while the Execution Unit (EU) executes instructions and microcode. Both parts are extensively involved in interrupt handling.</p> <p><a href="https://static.righto.com/images/8086-interrupts/die-labeled.jpg"><img alt="The 8086 die under a microscope, with main functional blocks labeled. This photo shows the chip's single metal layer; the polysilicon and silicon are underneath. Click on this image (or any other) for a larger version." class="hilite" height="624" src="https://static.righto.com/images/8086-interrupts/die-labeled-w600.jpg" title="The 8086 die under a microscope, with main functional blocks labeled. This photo shows the chip's single metal layer; the polysilicon and silicon are underneath. Click on this image (or any other) for a larger version." width="600" /></a><div class="cite">The 8086 die under a microscope, with main functional blocks labeled. This photo shows the chip's single metal layer; the polysilicon and silicon are underneath. Click on this image (or any other) for a larger version.</div></p> <h2>Interrupts in the 8086</h2> <p>The idea behind an interrupt is to stop the current flow of execution, run an interrupt handler to perform a task, and then continue execution where it left off. An interrupt is like a subroutine call in some ways; it pushes the current segment register and program counter on the stack and continues at a new address. However, there are a few important differences. First, the address of the interrupt handler is obtained indirectly, through an interrupt vector table. Interrupts are numbered 0 through 255, and each interrupt has an entry in the vector table that gives the address of the code to handle the interrupt. Second, an interrupt pushes the processor flags to the stack, so they can be restored after the interrupt. Finally, an interrupt clears the interrupt and trap flags, blocking more interrupts while handling the interrupt.</p> <p>The 8086 provides several types of interrupts, some generated by hardware and some generated by software. For hardware interrupts, the INTR pin on the chip generates a maskable interrupt when activated, while the NMI pin on the chip generates a higher-priority non-maskable interrupt.<span id="fnref:maskable"><a class="ref" href="#fn:maskable">2</a></span> Typically, most interrupts use the INTR pin, signaling things such as a timer, keyboard request, real-time clock, or a disk needing service. The NMI interrupt is designed for things such as parity error or an impending power failure, which are so critical they can't be delayed. The 8086 also has a RESET pin that resets the CPU. Although not technically an interrupt, the RESET action has many features in common with interrupts, so I'll discuss it here.</p> <p>On the software side, the 8086 has multiple types of interrupts generated by different instructions. The <code>INT n</code> instruction creates an interrupt of the specified type (0 to 255). These software interrupts were used in the IBM PC to execute a function in the BIOS, the layer underneath the operating system. These functions could be everything from a floppy disk operation to accessing the printer. The one-byte <code>INT 3</code> instruction creates a breakpoint interrupt for debugging. The divide instructions generate an interrupt if a divide-by-zero or overflow occurs. The <code>INTO</code> instruction (Interrupt if Overflow) generates an interrupt if the overflow flag is set. To support single-step mode in debuggers, the Trap flag generate an interrupt on every instruction.</p> <p>The diagram below shows how the vector table is implemented. Each of the 256 interrupt types has an entry holding the address of the interrupt handler (the code segment value and the instruction pointer (program counter) value). In the next section, I'll show below how the microcode loads the vector from the table and switches execution to that interrupt handler.</p> <p><a href="https://static.righto.com/images/8086-interrupts/vector-table.jpg"><img alt="This diagram shows where the interrupt vectors are stored in memory. From iAPX 86/88 User's Manual, Figure 4-18." class="hilite" height="653" src="https://static.righto.com/images/8086-interrupts/vector-table-w450.jpg" title="This diagram shows where the interrupt vectors are stored in memory. From iAPX 86/88 User's Manual, Figure 4-18." width="450" /></a><div class="cite">This diagram shows where the interrupt vectors are stored in memory. From <a href="http://www.bitsavers.org/components/intel/8086/1981_iAPX_86_88_Users_Manual.pdf">iAPX 86/88 User's Manual</a>, Figure 4-18.</div></p> <h2>Microcode</h2> <p>Most of the operations in the 8086 are implemented in microcode, a low-level layer of code that sits between the machine code instructions and the chip's hardware. I'll explain a few features of the 8086's microcode that are important for the interrupt code. Each micro-instruction is 21 bits long, as shown below. The first part of the micro-instruction specifies a move between a source register and a destination register; these may be special-purpose internal registers, not just the registers visible to the programmer. The meaning of the remaining bits depends on the type of micro-instruction, but includes jumps within the microcode, ALU (Arithmetic/Logic Unit) operations, and memory operations.</p> <p><a href="https://static.righto.com/images/8086-interrupts/microcode-format.jpg"><img alt="The encoding of a micro-instruction into 21 bits. Based on NEC v. Intel: Will Hardware Be Drawn into the Black Hole of Copyright?" class="hilite" height="203" src="https://static.righto.com/images/8086-interrupts/microcode-format-w700.jpg" title="The encoding of a micro-instruction into 21 bits. Based on NEC v. Intel: Will Hardware Be Drawn into the Black Hole of Copyright?" width="700" /></a><div class="cite">The encoding of a micro-instruction into 21 bits. Based on <a href="https://digitalcommons.law.scu.edu/cgi/viewcontent.cgi?referer=&httpsredir=1&article=1031&context=chtlj">NEC v. Intel: Will Hardware Be Drawn into the Black Hole of Copyright?</a></div></p> <p>For a memory access, microcode issues a memory read or write micro-instruction. Memory accesses use two internal registers: the <code>IND</code> (Indirect) register holds the address in the segment, while the <code>OPR</code> (Operand) register holds the word that is read or written. A micro-instruction such as <code>W SS,P2</code> writes the <code>OPR</code> register to the memory address specified by the <code>IND</code> register and the segment register (<code>SS</code> indicates the stack segment). The <code>IND</code> register can also be incremented or decremented (<code>P2</code> indicates "Plus 2").</p> <p>The 8086's Bus Interface Unit (BIU) handles the memory request in hardware, while the microcode waits. The BIU has an adder to combine the segment address and the offset to obtain the "absolute" address. It also has a constant ROM to increment or decrement the <code>IND</code> register. Memory accesses are complicated in the 8086 and take at least four clock cycles,<span id="fnref:cycles"><a class="ref" href="#fn:cycles">3</a></span> called T1, T2, T3, and T4. An interrupt acknowledge is almost the same as a memory read, except the <code>IAK</code> bit is set in the microcode, causing some behavior changes.</p> <p>The interaction between microcode and the ALU (Arithmetic/Logic Unit) will also be important. The ALU has three temporary registers that hold the arguments for operations, called temporary A, B, and C. These registers are invisible to the programmer. The first argument for, say, an addition can come from any of the three registers, while the second argument is always from the temporary B register. Performing an ALU operation takes at least two micro-instructions. First, the ALU is configured to perform an operation, for example, ADD or DEC2 (decrement by 2). The result is then read from the ALU, denoted as the <code>危</code> register.</p> <h2>Software interrupts</h2> <p>The main microcode for interrupt handling is shown below.<span id="fnref:jenner"><a class="ref" href="#fn:jenner">4</a></span> Each line specifies a move operation and an action, with my comments in green. On entry to <code>INTR</code> interrupt handler, the <code>OPR</code> operand register holds the interrupt type. This chunk of microcode looks up the interrupt handler in the vector table, pushes the status flags onto the stack, and then branches to a routine <code>FARCALL2</code> to perform a subroutine call the interrupt handler.</p> <style> pre.microcode {font-family: courier, fixed; padding: 10px; background-color: #f5f5f5; display:inline-block;} pre.microcode span {color: green; font-style:italic; font-family: sans-serif; font-size: 90%;} </style> <pre class="microcode"> move action 19d OPR → tmpBL SUSP <span>INTR: OPR to tmpB(low), suspend prefetch</span> 19e 0 → tmpbH ADD tmpB <span>0 to tmpB(high), add tmpB to tmpB</span> 19f 危 → tmpB <span>ALU sum to tmpB, add tmpB to tmpB</span> 1a0 危 → IND R S0,P2 <span>ALU sum to IND, read from memory, IND+=2</span> 1a1 OPR → tmpB DEC2 tmpC <span>memory to tmpB, set up decrement tmpC</span> 1a2 SP → tmpC R S0,P0 <span>SP to tmpC, read from memory</span> 1a3 OPR → tmpA <span>memory to tmpA</span> 1a4 F → OPR CITF <span>Flags to OPR, clear interrupt and trap flags</span> 1a5 危 → IND W SS,P0 <span>ALU dec to IND, Write to memory</span> 1a6 IND → tmpC JMP FARCALL2 <span>IND to tmpC, branch to FARCALL2</span> </pre> <p>In more detail, the microcode routine starts at 19d by moving the interrupt number from the <code>OPR</code> register to the low byte of the ALU's temporary B register. The <code>SUSP</code> action suspends instruction prefetching since we'll start executing instructions from a new location. Next, line 19e zeros out the top byte of the temporary B register and tells the ALU to add temporary B to itself. The next micro-instruction puts the ALU result (indicated by 危) into temporary B, doubling the value.</p> <p>Line 1a0 calculates another sum (doubling) from the ALU and stores it in the <code>IND</code> register. In other words, the interrupt number has been multiplied by 4, yielding an address into the vector table. The interrupt handle address is read from the vector table: <code>R S0,P2</code> operation reads from memory, segment 0, and performs a "Plus 2" on the <code>IND</code> register. Line 1a1 puts the result (<code>OPR</code>) into the temporary B register.</p> <p>Line 1a2 stores the current stack pointer register into temporary C. It also performs a second read to get the handler code segment from the vector table. Line 1a3 stores this in the temporary A register. Line 1a4 puts the flags (<code>F</code>) into the <code>OPR</code> register. It also clears the interrupt and trap flags (<code>CITF</code>), blocking further interrupts.</p> <p>Line 1a5 puts the ALU result (the decremented stack pointer) into the <code>IND</code> register. (This ALU operation was set up back in line 1a1.) To push the flags on the stack, <code>W SS,P0</code> writes <code>OPR</code> to the Stack segment and does a "Plus 0" on the <code>IND</code> register. Finally, line 1a6 stores the <code>IND</code> register (the new top-of-stack) into the temporary C register and jumps to the <code>FARCALL2</code> micro-routine.<span id="fnref:jump"><a class="ref" href="#fn:jump">5</a></span></p> <p>Understanding microcode can be tricky, since it is even more low-level than machine instructions, but hopefully this discussion gives you a feel for it. Everything is broken down into very small steps, even more basic than machine instructions. Microcode is a bit like a jigsaw puzzle, carefully fit together to ensure everything is at the right place at the right time, as efficiently as possible.</p> <h3>Subroutine call microcode: FARCALL2</h3> <p>Next, I'll describe the <code>FARCALL2</code> microcode. Because of its segment registers, the 8086 has two types of calls (and jumps): a near call is a subroutine call within the same code segment, while a far call is a subroutine call to a different code segment. A far call target is specified with two words: the new code segment register and the new program counter.</p> <p>The <code>FARCALL2</code> micro-routine performs a subroutine call to a particular segment and offset. At entry to <code>FARCALL2</code>, the target code segment in temporary A, the offset is in temporary B, and the decremented stack pointer will be provided by the ALU. The microcode below pushes the code segment register to the stack, updates the code segment register with the new value, and then jumps to <code>NEARCALL</code> to finish the subroutine call.</p> <pre class="microcode"> 06c 危 → IND CORR <span>FARCALL2: ALU (IND-2) to IND, correct PC</span> 06d CS → OPR W SS,M2 <span>CS to OPR, write to memory, IND-=2</span> 06e tmpA → CS PASS tmpC <span>tmpA to CS, ALU passthrough</span> 06f PC → OPR JMP NEARCALL <span>PC to OPR, branch to NEARCALL</span> </pre> <p>For a subroutine call, the program counter is saved so execution can resume where it left off. But because of prefetching, the program counter in the 8086 points to the next instruction to <em>fetch</em>, not the next instruction to <em>execute</em>. To fix this, the <code>CORR</code> (Correction) micro-instruction corrects the program counter value by subtracting the length of the prefetch queue. Line 06c also puts the decremented stack location into <code>IND</code> using the ALU decrement operation set up way back at line 1a1.</p> <p>Line 06d puts the code segment value (<code>CS</code>) into the <code>OPR</code> register and then writes it to the stack segment, performing a "Minus 2" on <code>IND</code>. In other words, the CS register is pushed onto the stack. Line 06e stores the new value (from temporary A) into the CS register. It also sets up the ALU to pass the value of the temporary C register as its result. Finally, line 06f puts the (corrected) program counter into the <code>OPR</code> register and jumps to the <code>NEARCALL</code> routine.</p> <h3>Subroutine call microcode: NEARCALL</h3> <p>The <code>NEARCALL</code> micro-routine does a near subroutine call, updating the program counter but not the segment register. At entry, the target address is in temporary B, the <code>IND</code> register indicates the top of the stack, and <code>OPR</code> holds the program counter.</p> <pre class="microcode"> 077 tmpB → PC FLUSH <span>NEARCALL: tmpB to PC, restart prefetch</span> 078 IND → tmpC <span>IND to tmpC</span> 079 危 → IND <span>ALU to IND</span> 07a 危 → SP W SS,P0 RNI <span>ALU to SP, write PC to memory, run next instruction</span> </pre> <p>Line 077 puts temporary B into the program counter. The <code>FLUSH</code> operation flushes the stale instructions from the prefetch queue and starts prefetching from the new PC address. Line 078 puts <code>IND</code> (i.e. the new stack pointer value) into temporary C. Line 079 puts this value into the <code>IND</code> register and line 07a puts this value into the <code>SP</code> register. (The ALU was configured at line 06e to pass the temporary C value unmodified.)</p> <p>Line 07a pushes the PC to the stack by writing <code>OPR</code> (the old program counter) to the stack segment. Finally, <code>RNI</code> (Run Next Instruction) ends this microcode sequence and causes the 8086 to run the next machine instruction, the first instruction of the interrupt handler.</p> <h3>Starting an interrupt</h3> <p>The above microcode handles a generic interrupt. But there's one more piece: setting up the interrupt type for the instruction. For instance, the <code>INT ib</code> machine instruction has the interrupt type in the second byte of the opcode. This machine instruction has the two micro-instructions below. The microcode loads the type from the instruction prefetch queue (<code>Q</code>) and puts it into temporary B and then <code>OPR</code>. Then it jumps to the <code>INTR</code> microcode discussed earlier.</p> <pre class="microcode"> 1a8 Q → tmpB <span>INT ib: load a byte from the queue</span> 1a9 tmpB → OPR JMP INTR <span>Put the byte in OPR and jump to INTR</span> </pre> <p>Several instructions require specific interrupt numbers, and the microcode uses a tricky technique to obtain these numbers. The numbers are obtained from a special pseudo-register called <code>CR</code>, which is all zeros except the three low bits come from the microcode address.<span id="fnref:zero"><a class="ref" href="#fn:zero">6</a></span> The microcode is carefully arranged in memory so the micro-instruction is at the right address to generate the necessary value. For instance, in the microcode below, entry point <code>INT1</code> will load the number 1 into <code>OPR</code>, entry point <code>INT2</code> will load the number 2 into <code>OPR</code>, and <code>INT0</code> will load 0 into <code>OPR</code>. Each line then jumps to the main <code>INTR</code> interrupt microcode.</p>  <pre class="microcode"> 198 CR → OPR JMP INTR <span>INT1: num to OPR, branch to INTR</span> 199 CR → OPR JMP INTR <span>INT2: num to OPR, branch to INTR</span> ... 1a7 CR → OPR JMP INTR <span>INT0: num to OPR, branch to INTR</span> </pre> <p>The microcode for the <code>INT 3</code> and <code>INTO</code> (not to be confused with <code>INT0</code>) machine instructions has some wasted micro-instructions to ensure that the <code>CR → OPR</code> is at the right address. This wastes a couple of cycles and a couple of micro-instructions.<span id="fnref:int3"><a class="ref" href="#fn:int3">7</a></span></p>  <h3>Return from interrupt</h3> <p>The <code>IRET</code> interrupt is used to return from interrupts. It pops the program counter, code segment register, and flags from the stack, so execution can continue at the point where the interrupt happened. It calls the microcode subroutine <code>FARRET</code> to pop the code segment register and the PC from the stack. (I won't go into <code>FARRET</code> in this post.) Then it pops the flags from the stack, updates the Stack Pointer, and runs the next instruction.</p> <pre class="microcode"> 0c8 CALL FARRET <span>IRET: call Far Return</span> 0c9 R SS,P2 <span>read from stack, IND+=2</span> 0ca OPR → F <span>mem to Flags</span> 0cb IND → SP RNI <span>IND to stack pointer, run next instruction</span> </pre> <h2>External hardware interrupts</h2> <p>As well as software interrupts, the 8086 has hardware interrupts. The 8086 chip has pins for INTR and NMI; pulling the pin high causes a hardware interrupt. This section discusses the hardware circuitry and the microcode that handles these interrupts.</p> <h3>The interrupt pin circuit</h3> <p>The schematic below shows the input circuitry for the INTR pin; the NMI, RESET, and TEST pins use the same circuit. The function of this circuit is to clean up the input and ensure that it is synchronized with the clock. The chip's INTR pin is connected to a protection diode to drain a negative voltage to ground. Next, the signal goes through three inverters, probably to force a marginal voltage to either 0 or 1. Finally, the signal goes through an edge-triggered flip-flop to synchronize it with the clock. The flip-flop is constructed from two set-reset latches, the first gated by clk' and the second gated by clk. At the output of each stage is a "superbuffer", two transistors that produce a higher-current output than a regular inverter. This flip-flop circuit is unusual for the 8086; most flip-flops and latches are constructed from dynamic logic with pass transistors, which is much more compact. The more complicated circuitry on the INTR input probably protects against metastability and other problems that could occur with poor-quality input signals.</p> <p><a href="https://static.righto.com/images/8086-interrupts/pin-input.jpg"><img alt="Schematic of the input circuitry for the INTR pin." class="hilite" height="209" src="https://static.righto.com/images/8086-interrupts/pin-input-w700.jpg" title="Schematic of the input circuitry for the INTR pin." width="700" /></a><div class="cite">Schematic of the input circuitry for the INTR pin.</div></p> <h3>The interrupt logic circuitry</h3> <p>The chip has a block of interrupt logic to receive interrupts, handle interrupt priorities, and execute an interrupt at the appropriate time. This circuitry is in the top right part of the chip, on the opposite side of the chip from the interrupt pins. The schematic below shows this circuitry.</p> <p><a href="https://static.righto.com/images/8086-interrupts/interrupt-logic.jpg"><img alt="The interrupt logic circuitry activates the microcode interrupt code at the appropriate time." class="hilite" height="422" src="https://static.righto.com/images/8086-interrupts/interrupt-logic-w600.jpg" title="The interrupt logic circuitry activates the microcode interrupt code at the appropriate time." width="600" /></a><div class="cite">The interrupt logic circuitry activates the microcode interrupt code at the appropriate time.</div></p> <p>The top chunk of logic latches an NMI (non-maskable interrupt) until it runs or it is cleared by a reset.<span id="fnref:nmi"><a class="ref" href="#fn:nmi">8</a></span> The first flip-flop helps convert an NMI input into a one-clock pulse. The second flip-flop holds the NMI until it runs.</p> <p>The middle chunk of logic handles traps. If the trap flag is high, the latch will hold the trap request until it can take place. The latch is loaded on First Clock (FC), which indicates the start of a new instruction. The NOR gate blocks the trap if there is an interrupt or NMI, which has higher priority.<span id="fnref:simultaneous"><a class="ref" href="#fn:simultaneous">9</a></span></p> <p>The third chunk of logic schedules the interrupt. Three things can delay an interrupt: an interrupt delay micro-instruction, an instruction that modifies a segment register, or an instruction prefix.<span id="fnref:delay"><a class="ref" href="#fn:delay">10</a></span> If not delayed, the interrupt (NMI, trap, or INTR pin) will run at the start of the next instruction (i.e. <code>FC</code>).<span id="fnref:fc"><a class="ref" href="#fn:fc">11</a></span> The microcode interrupt code is run for these cases as well as a reset. Note that the reset is not gated by First Clock, but can run at any time.</p> <p>The interrupt signal from this circuitry loads a hardcoded interrupt address into the microcode address latches, depending on the type of interrupt.<span id="fnref:mc-addr"><a class="ref" href="#fn:mc-addr">12</a></span> This happens for an interrupt at First Clock, while a reset can happen any time in the instruction cycle. A trap goes to the <code>INT1</code> microcode routine described earlier, while an NMI interrupt goes to <code>INT2</code> microcode routine. The microcode for the <code>INTR</code> interrupt will be discussed in the next section.</p> <p>The interrupt signal also goes to the Group Decode ROM (via the instruction register), where it blocks regular instruction decoding. Finally, the interrupt signal goes to a circuit called the loader, where it prevents fetching of the next instruction from the prefetch queue.</p> <h2>The external INTR interrupt</h2> <p>The INTR interrupt has some special behavior to communicate with the device that triggered the interrupt: the 8086 performs two bus cycles to acknowledge the interrupt and to obtain the interrupt number from the device. This is implemented with a combination of microcode and the bus interface logic. The bus cycles are similar to memory read cycles, but with some behavior specific to interrupts.</p> <p>The INTR interrupt has its own microcode, shown below. The first micro-instruction zeros the <code>IND</code> memory address register and then performs a special <code>IAK</code> bus cycle.<span id="fnref:iak"><a class="ref" href="#fn:iak">13</a></span> This is similar to a memory read but asserts the <code>INTA</code> interrupt acknowledge line so the device knows that its interrupt has been received. Next, prefetching is suspended. The third line performs a second <code>IAK</code> bus cycle and the external device puts the interrupt number onto the bus. The interrupt number is read into the <code>ORD</code> register, just like a memory read. At this point, the code falls through into the interrupt microcode described previously.</p> <pre class="microcode"> 19a 0 → IND IAK S0,P0 <span>IRQ: 0 to IND, run interrupt bus cycle</span> 19b SUSP <span>suspend prefetch</span> 19c IAK S0,P0 <span>run interrupt bus cycle</span> 19d ... <span>The INTR routine discussed earlier</span> </pre> <h3>The bus cycle</h3> <p>The diagram below provides timing details of the two interrupt acknowledge bus cycles. Each cycle is similar to a memory read bus cycle, going through the T1 through T4 states, starting with an <code>ALE</code> (Address Latch Enable) signal. The main difference is the interrupt acknowledge bus cycle also raises the <code>INTA</code> (Interrupt Acknowledge) to let the requesting device know that its interrupt has been acknowledged.<span id="fnref:minimum"><a class="ref" href="#fn:minimum">14</a></span> On the second cycle, the device provides an 8-bit type vector that provides the interrupt number. The 8086 also issues a <code>LOCK</code> signal to lock the bus from other uses during this sequence. The point of this is that the 8086 goes through a fairly complex bus sequence when handling a hardware interrupt. The microcode triggers these two bus cycles with the <code>IAK</code> micro-operation, but the bus interface circuitry goes through the various states of the bus cycle in hardware, without involving the microcode.</p> <p><a href="https://static.righto.com/images/8086-interrupts/int-ack.jpg"><img alt="This diagram shows the interrupt acknowledge sequence. From Intel 8086 datasheet." class="hilite" height="308" src="https://static.righto.com/images/8086-interrupts/int-ack-w600.jpg" title="This diagram shows the interrupt acknowledge sequence. From Intel 8086 datasheet." width="600" /></a><div class="cite">This diagram shows the interrupt acknowledge sequence. From <a href="https://www.electro-tech-online.com/datasheets/8086_intel.pdf">Intel 8086 datasheet</a>.</div></p> <p>The circuitry to control the bus cycle is complicated with many flip-flops and logic gates; the diagram below shows the flip-flops. I plan to write about the bus cycle circuitry in detail later, but for now, I'll give an extremely simplified description. Internally, there is a T0 state before T1 to provide a cycle to set up the bus operation. The bus timing states are controlled by a chain of flip-flops configured like a shift register with additional logic: the output from the T0 flip-flop is connected to the input of the T1 flip-flop and likewise with T2 and T3, forming a chain. A bus cycle is started by putting a 1 into the input of the T0 flip-flop. When the CPU's clock transitions, the flip-flop latches this signal, indicating the (internal) T0 bus state. On the next clock cycle, this 1 signal goes from the T0 flip-flop to the T1 flip-flop, creating the externally-visible T1 state. Likewise, the signal passes to the T2 and T3 flip-flops in sequence, creating the bus cycle. Some special-case logic changes the behavior for an interrupt versus a read.<span id="fnref:bus-logic"><a class="ref" href="#fn:bus-logic">15</a></span></p> <p><a href="https://static.righto.com/images/8086-interrupts/mem-ctrl.jpg"><img alt="The read/write control circuitry on the die with the flip-flops labeled. Metal and polysilicon were removed to show the underlying silicon." class="hilite" height="509" src="https://static.righto.com/images/8086-interrupts/mem-ctrl-w600.jpg" title="The read/write control circuitry on the die with the flip-flops labeled. Metal and polysilicon were removed to show the underlying silicon." width="600" /></a><div class="cite">The read/write control circuitry on the die with the flip-flops labeled. Metal and polysilicon were removed to show the underlying silicon.</div></p> <h2>Reset</h2> <p>The reset pin resets the CPU to an initial state. This isn't an interrupt, but much of the circuitry is the same, so I'll describe it for completeness. The reset microcode below initializes the segment registers, program counter, and flags to 0, except the code segment is initialized to 0xffff. Thus, after a reset, instruction execution will start at absolute address 0xffff0. The reset line is also connected to numerous flip-flops and circuits in the 8086 to ensure that they are initialized to the proper state. These initializations happen outside of the microcode.</p> <pre class="microcode"> 1e4 0 → DS SUSP <span>RESET: 0 to DS, suspend prefetch</span> 1e5 ONES → CS <span>FFFF to CS</span> 1e6 0 → PC FLUSH <span>0 to PC, start prefetch</span> 1e7 0 → F <span>0 to Flags</span> 1e8 0 → ES <span>0 to ES</span> 1e9 0 → SS RNI <span>0 to SS, run next instruction</span> </pre> <h2>A bit of history</h2> <p>The 8086's interrupt system inherits a lot from the Intel 8008 processor. Interrupts were a bit of an afterthought on the 8008 so the interrupt handling was primitive and designed to simplify implementation.<span id="fnref:8008"><a class="ref" href="#fn:8008">17</a></span> In particular, an interrupt response acts like an instruction fetch except the interrupting device "jams" an instruction on the bus. To support this, the 8008 provided one-byte <code>RST</code> (Restart) instructions that would call a fixed location. The Intel 8080 improved the 8008, but kept this model of performing an instruction fetch cycle that received a "jammed" instruction for an interrupt. With more pins available, the 8080 added the <code>INTA</code> Interrupt Acknowledge pin.</p> <p>The approach of "jamming" an instruction onto the bus for an interrupt is rather unusual. Other contemporary microprocessors such as the 6800, 6502, or Intel 8048 used an interrupt vector approach, which is much more standard: an interrupt vector table held pointers to the interrupt service routines.</p> <p>The 8086 switched to an interrupt vector table, but retained some 8080 interrupt characteristics for backward compatibility. In particular, the 8086 performs a memory cycle very much like an instruction fetch, but instead of an instruction, it receives an interrupt number. The 8086 performs two interrupt ack bus cycles but ignores the first one, which lets the same hardware work with the 8080 and 8086.<span id="fnref:8259A"><a class="ref" href="#fn:8259A">16</a></span></p> <h2>Conclusions</h2> <p>This is another blog post that I expected would be quick and easy, but there's a lot going on in the 8086's interrupt system, both in hardware and microcode. The 8086 has some strange characteristics, such as acknowledging interrupts twice, but these features make more sense when looking at the 8086's history and what it inherited from the 8008 and 8080.</p> <p>I've written multiple <a href="https://www.righto.com/search/label/8086">posts on the 8086</a> so far and plan to continue reverse-engineering the 8086 die so follow me on Twitter <a href="https://twitter.com/kenshirriff">@kenshirriff</a> or <a href="http://www.righto.com/feeds/posts/default">RSS</a> for updates. I've also started experimenting with Mastodon recently as <a href="https://oldbytes.space/@kenshirriff">@oldbytes.space@kenshirriff</a>. Thanks to <a href="https://news.ycombinator.com/item?id=34495797">pwg</a> on HN for suggesting interrupts as a topic.</p> <h2>Notes and references</h2> <div class="footnote"> <ol> <li id="fn:history"> <p>The first computer to provide interrupts was probably the UNIVAC 1103A (1956). The book "Computer Architecture" by Blaauw and Brooks discusses different approaches to interrupts in great detail, pages 418-434. A history of interrupts is in <a href="http://www.cap-lore.com/Hardware/int.html">this article</a>. <a class="footnote-backref" href="#fnref:history" title="Jump back to footnote 1 in the text">↩</a></p> </li> <li id="fn:maskable"> <p>The maskable interrupt can be blocked in software, while the non-maskable interrupt cannot be blocked. <a class="footnote-backref" href="#fnref:maskable" title="Jump back to footnote 2 in the text">↩</a></p> </li> <li id="fn:cycles"> <p>A typical memory access takes four clock cycles. However, slow memory can add wait states, adding as many clock cycles as necessary. Moreover, accessing a word from an unaligned (odd) address results in two complete bus cycles to access the two bytes, since the bus can only read an aligned word at a time. Thus, memory accesses can take much more than four cycles. <a class="footnote-backref" href="#fnref:cycles" title="Jump back to footnote 3 in the text">↩</a></p> </li> <li id="fn:jenner"> <p>The 8086's microcode was disassembled by Andrew Jenner (<a href="https://www.reenigne.org/blog/8086-microcode-disassembled/">link</a>) from my die photos, so the microcode listings are based on his disassembly. <a class="footnote-backref" href="#fnref:jenner" title="Jump back to footnote 4 in the text">↩</a></p> </li> <li id="fn:jump"> <p>The microcode jumps use a level of indirection because there isn't room in the micro-instruction for the full micro-address. Instead, the micro-instruction has a four-bit tag specifying the desired routine. The Translation ROM holds the corresponding micro-address for the routine, which is loaded into the microcode address register. <a class="footnote-backref" href="#fnref:jump" title="Jump back to footnote 5 in the text">↩</a></p> </li> <li id="fn:zero"> <p>The <code>CR</code> transfer source loads the low three bits of the microcode address. Its implementation is almost the same as the <code>ZERO</code> source, which loads zero. A signal zeroes bits 15-3 for both sources. The bottom 3 bits are pulled low for the ZERO source or if the corresponding microcode bit is 0. By the time this load happens, the microcode counter has incremented, so the value is one more than the address with the micro-instruction. Also note that it uses the raw 13-bit microcode address which is 9 bits plus four counter bits. The address decoder converts this to the 9-bit "physical" microcode address that I'm showing. The point is that the 3 lower bits from my microcode listing won't give the right value. <a class="footnote-backref" href="#fnref:zero" title="Jump back to footnote 6 in the text">↩</a></p> </li> <li id="fn:int3"> <p>The jump in the microcode is why the one-byte <code>INT 3</code> instruction takes 52 clocks while the two-byte <code>INT nn</code> instruction takes 51 clocks. You'd expect <code>INT nn</code> to be slower because it has an extra byte to execute, but the microcode layout for <code>INT 3</code> makes it slower. <a class="footnote-backref" href="#fnref:int3" title="Jump back to footnote 7 in the text">↩</a></p> </li> <li id="fn:nmi"> <p>There's a subtle difference between the NMI and the INTR interrupts. Once the NMI pin goes high, the interrupt is scheduled, even if the pin goes low. For a regular interrupt, the INTR pin must be high at the start of an instruction. Thus, NMI is latched but INTR is not. <a class="footnote-backref" href="#fnref:nmi" title="Jump back to footnote 8 in the text">↩</a></p> </li> <li id="fn:simultaneous"> <p>Since the 8086 has multiple interrupt sources, you might wonder how multiple interrupts are handled at the same time. The chip makes sure the interrupts are handled correctly, according to their priorities. The diagram below shows what happens if trapping (single-step) is enabled, a divide causes a divide-by-0 exception, and an external interrupt arrives.</p> <p><a href="https://static.righto.com/images/8086-interrupts/simultaneous-interrupts.jpg"><img alt="Processing simultaneous interrupts. From iAPX 86/88 User's Manual, Figure 2-31." class="hilite" height="798" src="https://static.righto.com/images/8086-interrupts/simultaneous-interrupts-w400.jpg" title="Processing simultaneous interrupts. From iAPX 86/88 User's Manual, Figure 2-31." width="400" /></a><div class="cite">Processing simultaneous interrupts. From <a href="http://www.bitsavers.org/components/intel/8086/1981_iAPX_86_88_Users_Manual.pdf">iAPX 86/88 User's Manual</a>, Figure 2-31.</div></p> <p> <a class="footnote-backref" href="#fnref:simultaneous" title="Jump back to footnote 9 in the text">↩</a></p> </li> <li id="fn:delay"> <p>The interrupt delay micro-instruction is used for the <code>WAIT</code> machine instruction. I think that a long string of prefix instructions will delay an interrupt (even an NMI) for an arbitrarily long time. <a class="footnote-backref" href="#fnref:delay" title="Jump back to footnote 10 in the text">↩</a></p> </li> <li id="fn:fc"> <p>Interrupts usually happen after the end of a machine instruction, rather than interrupting an instruction during execution. There are a couple of exceptions, however, for instructions that can take a very long time to complete (block copies) or could take forever (<code>WAIT</code>). The solution is that the microcode for these instructions checks to see if an interrupt is pending, so the instruction can explicitly stop and the interrupt can be handled. <a class="footnote-backref" href="#fnref:fc" title="Jump back to footnote 11 in the text">↩</a></p> </li> <li id="fn:mc-addr"> <p>The microcode address is 13 bits long: a special bit, 8 instruction bits, and four counter bits. For an interrupt, it is set to <code>1r0000000.00ab</code>, where <code>r</code> indicates a reset and <code>ab</code> indicate an interrupt of various types: <br/> Trap: goes to vector 1, INT1 addr 198 10000000.00 <br/> NMI: goes to vector 2, INT2 addr 199 100000000.01 (Bit <code>b</code> is NMI) <br/> INTR: goes to IRQ addr 19a 100000000.10, vector specified by device. Bit <code>a</code> is intr-enable', blocked by NMI. <br/> This logic takes into account the relative priorities of the different interrupts. This address is initialized through a special multiplexer path for interrupts that loads bits directly into the microcode address latch. <a class="footnote-backref" href="#fnref:mc-addr" title="Jump back to footnote 12 in the text">↩</a></p> </li> <li id="fn:iak"> <p>The <code>IAK</code> micro-instruction is the same as a read micro-instruction except the <code>IAK</code> (Interrupt Acknowledge) bit is set. This bit controls the differences between a read micro-instruction and an interrupt acknowledge micro-instruction.</p> <p>The logic that makes the bus cycle an interrupt acknowledge rather than a read is a bit strange. A signal indicates that the cycle is an I/O operation or an interrupt acknowledge. This is determined by the instruction decoder (for I/O) or bit <code>P</code> of the microcode (for an interrupt acknowledge). This signal is used for the S2 status pin. Later, this signal is ANDed with the read/write signal to determine that it is an interrupt acknowledge and not an I/O. This probably optimized signal generation, but it seems inconvenient to merge two signals together and then split them out later. <a class="footnote-backref" href="#fnref:iak" title="Jump back to footnote 13 in the text">↩</a></p> </li> <li id="fn:minimum"> <p>The 8086 has two different modes, giving its pins different meanings in the different modes. In "Minimum" mode, the control pins have simple functions. In particular, the interrupt is acknowledged using the INTA pin. In "Maximum" mode, the control pins are encoded to provide more state information to a bus controller. In this mode, the interrupt acknowledge state is encoded and signaled over the S2, S1, and S0 state pins. I'm discussing minimum mode; the sequence is the same in maximum mode but uses different pins. <a class="footnote-backref" href="#fnref:minimum" title="Jump back to footnote 14 in the text">↩</a></p> </li> <li id="fn:bus-logic"> <p>To prevent another device from grabbing the bus during interrupt acknowledgement, the LOCK pin is activated. The hardware for this LOCK signal toggles the internal lock latch on each of the interrupt ALE signals, so the lock is enabled on the first one and disabled on the second. The interrupt ack signal also prevents the address lines from being enabled during the interrupt ack. <a class="footnote-backref" href="#fnref:bus-logic" title="Jump back to footnote 15 in the text">↩</a></p> </li> <li id="fn:8259A"> <p>An 8086/8088 system will typically use an external chip, the <a href="https://pdos.csail.mit.edu/6.828/2017/readings/hardware/8259A.pdf">8259A</a> Programmable Interrupt Controller. This chip extends the interrupt functionality of the 8086 by providing 8 priority-based hardware interrupts.</p> <p>The Intel 8259A Programmable Interrupt Controller chip was designed to receive interrupt requests from multiple devices, prioritize interrupts, and direct the 8080 or 8086 processor accordingly. When used with the 8080, the interrupt controller chip will issue a <code>CALL</code> instruction to execute the specified interrupt handler. In particular, when the 8080 responds to an interrupt with <code>INTA</code> pulses, the interrupt controller chip will first put a <code>CALL</code> instruction on the bus, and then will respond to the next two <code>INTA</code> pulses with the address. For the 8086, the interrupt controller ignores the first <code>INTA</code> pulse and responds to the second <code>INTA</code> pulse with the 8-bit pointer. The point of this is that for both processors, the interrupt controller freezes its state on the first <code>INTA</code> and sends the interrupt-specific byte on the second <code>INTA</code>. Thus, even though the interrupt controller responds to the 8080 with an instruction and responds to the 8086 with an interrupt code, the underlying timing and logic are mostly the same. <a class="footnote-backref" href="#fnref:8259A" title="Jump back to footnote 16 in the text">↩</a></p> </li> <li id="fn:8008"> <p>The article <a href="https://stevemorse.org/8086history/8086history.pdf">Intel Microprocessors: 8008 to 8086</a> provides some history on interrupts in the 8008. Also see <a href="https://archive.computerhistory.org/resources/access/text/2012/07/102657982-05-01-acc.pdf">Intel 8008 Microprocessor Oral History Panel</a>, pages 5-6. Most of the 8008's features were inherited from the Datapoint 2200 desktop computer, but the interrupts were not part of the Datapoint 2200. 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class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2023/01/'> January </a> <span class='post-count' dir='ltr'>(8)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2022/'> 2022 </a> <span class='post-count' dir='ltr'>(18)</span> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2022/11/'> November </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2022/08/'> August </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2022/07/'> July </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2022/06/'> June </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2022/05/'> May </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a 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class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2021/05/'> May </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2021/04/'> April </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2021/03/'> March </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2021/02/'> February </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2021/01/'> January </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2020/'> 2020 </a> <span class='post-count' dir='ltr'>(33)</span> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2020/12/'> December </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2020/11/'> November </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2020/10/'> October </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2020/09/'> September </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2020/08/'> August </a> <span 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</span> </a> <a class='post-count-link' href='http://www.righto.com/2020/04/'> April </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2020/03/'> March </a> <span class='post-count' dir='ltr'>(5)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2020/01/'> January </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2019/'> 2019 </a> <span class='post-count' dir='ltr'>(18)</span> <ul class='hierarchy'> <li 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href='http://www.righto.com/2019/08/'> August </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2019/07/'> July </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2019/04/'> April </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2019/02/'> February </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2019/01/'> January </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2018/'> 2018 </a> <span class='post-count' dir='ltr'>(17)</span> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2018/12/'> December </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2018/09/'> September </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2018/08/'> August </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2018/06/'> June </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2018/05/'> May </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2018/04/'> April </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2018/03/'> March </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2018/02/'> February </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2018/01/'> January </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2017/'> 2017 </a> <span class='post-count' dir='ltr'>(21)</span> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2017/12/'> December </a> <span class='post-count' dir='ltr'>(5)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2017/11/'> November </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2017/10/'> October </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2017/08/'> August </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2017/07/'> July </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2017/06/'> June </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2017/04/'> April </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2017/03/'> March </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2017/02/'> February </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2017/01/'> January </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/'> 2016 </a> <span class='post-count' dir='ltr'>(34)</span> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/12/'> December </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/10/'> October </a> <span class='post-count' dir='ltr'>(5)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/09/'> September </a> <span class='post-count' dir='ltr'>(8)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/08/'> August </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/07/'> July </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/06/'> June </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/05/'> May </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/04/'> April </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/03/'> March </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/02/'> February </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2016/01/'> January </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2015/'> 2015 </a> <span class='post-count' dir='ltr'>(12)</span> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2015/12/'> December </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2015/11/'> November </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2015/10/'> October </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2015/08/'> August </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2015/05/'> May </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2015/03/'> March </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2015/02/'> February </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2014/'> 2014 </a> <span class='post-count' dir='ltr'>(13)</span> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2014/12/'> December </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2014/10/'> October </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2014/09/'> September </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2014/05/'> May </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2014/03/'> March </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2014/02/'> February </a> <span class='post-count' dir='ltr'>(5)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2013/'> 2013 </a> <span class='post-count' dir='ltr'>(24)</span> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2013/11/'> November </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2013/09/'> September </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2013/08/'> August </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2013/07/'> July </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2013/06/'> June </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2013/04/'> April </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2013/03/'> March </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2013/02/'> February </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2013/01/'> January </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2012/'> 2012 </a> <span class='post-count' dir='ltr'>(10)</span> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2012/12/'> December </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2012/11/'> November </a> <span class='post-count' dir='ltr'>(5)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2012/10/'> October </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2012/05/'> May </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2012/03/'> March </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2012/02/'> February </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2011/'> 2011 </a> <span class='post-count' dir='ltr'>(11)</span> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2011/12/'> December </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2011/07/'> July </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2011/05/'> May </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2011/04/'> April </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2011/03/'> March </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2011/02/'> February </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2010/'> 2010 </a> <span class='post-count' dir='ltr'>(22)</span> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2010/12/'> December </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2010/11/'> November </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2010/10/'> October </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2010/08/'> August </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2010/06/'> June </a> <span class='post-count' dir='ltr'>(1)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2010/05/'> May </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2010/04/'> April </a> <span class='post-count' dir='ltr'>(3)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2010/03/'> March </a> <span class='post-count' dir='ltr'>(4)</span> </li> </ul> <ul class='hierarchy'> <li class='archivedate collapsed'> <a class='toggle' href='javascript:void(0)'> <span class='zippy'> ►  </span> </a> <a class='post-count-link' href='http://www.righto.com/2010/01/'> January </a> <span class='post-count' dir='ltr'>(2)</span> </li> </ul> </li> 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