CINXE.COM

<!DOCTYPE html> <html class="client-nojs vector-feature-language-in-header-enabled vector-feature-language-in-main-page-header-disabled vector-feature-page-tools-pinned-disabled vector-feature-toc-pinned-clientpref-1 vector-feature-main-menu-pinned-disabled vector-feature-limited-width-clientpref-1 vector-feature-limited-width-content-enabled vector-feature-custom-font-size-clientpref-1 vector-feature-appearance-pinned-clientpref-1 vector-feature-night-mode-enabled skin-theme-clientpref-day vector-sticky-header-enabled vector-toc-available" lang="en" dir="ltr"> <head> <meta charset="UTF-8"> <title>DDR4 SDRAM - Wikipedia</title> <script>(function(){var className="client-js vector-feature-language-in-header-enabled vector-feature-language-in-main-page-header-disabled vector-feature-page-tools-pinned-disabled vector-feature-toc-pinned-clientpref-1 vector-feature-main-menu-pinned-disabled vector-feature-limited-width-clientpref-1 vector-feature-limited-width-content-enabled vector-feature-custom-font-size-clientpref-1 vector-feature-appearance-pinned-clientpref-1 vector-feature-night-mode-enabled skin-theme-clientpref-day vector-sticky-header-enabled vector-toc-available";var cookie=document.cookie.match(/(?:^|; )enwikimwclientpreferences=([^;]+)/);if(cookie){cookie[1].split('%2C').forEach(function(pref){className=className.replace(new RegExp('(^| )'+pref.replace(/-clientpref-\w+$|[^\w-]+/g,'')+'-clientpref-\\w+( |$)'),'$1'+pref+'$2');});}document.documentElement.className=className;}());RLCONF={"wgBreakFrames":false,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"df61638f-8c28-4101-a896-6af9407aea6b","wgCanonicalNamespace":"","wgCanonicalSpecialPageName":false,"wgNamespaceNumber":0,"wgPageName":"DDR4_SDRAM","wgTitle":"DDR4 SDRAM","wgCurRevisionId":1278891957,"wgRevisionId":1278891957,"wgArticleId":19126521,"wgIsArticle":true,"wgIsRedirect":false,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":["CS1: unfit URL","CS1 German-language sources (de)","CS1 Japanese-language sources (ja)","Articles with short description","Short description is different from Wikidata","All articles with failed verification","Articles with failed verification from September 2019","Wikipedia articles in need of updating from January 2014","All Wikipedia articles in need of updating","SDRAM"],"wgPageViewLanguage":"en","wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"DDR4_SDRAM","wgRelevantArticleId":19126521,"wgIsProbablyEditable":true,"wgRelevantPageIsProbablyEditable":true,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgRedirectedFrom":"DDR4","wgNoticeProject":"wikipedia","wgCiteReferencePreviewsActive":false,"wgFlaggedRevsParams":{"tags":{"status":{"levels":1}}},"wgMediaViewerOnClick":true,"wgMediaViewerEnabledByDefault":true,"wgPopupsFlags":0,"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr","pageVariantFallbacks":"en"},"wgMFDisplayWikibaseDescriptions":{"search":true,"watchlist":true,"tagline":false,"nearby":true},"wgWMESchemaEditAttemptStepOversample":false,"wgWMEPageLength":50000,"wgInternalRedirectTargetUrl":"/wiki/DDR4_SDRAM","wgEditSubmitButtonLabelPublish":true,"wgULSPosition":"interlanguage","wgULSisCompactLinksEnabled":false,"wgVector2022LanguageInHeader":true,"wgULSisLanguageSelectorEmpty":false,"wgWikibaseItemId":"Q1189682","wgCheckUserClientHintsHeadersJsApi":["brands","architecture","bitness","fullVersionList","mobile","model","platform","platformVersion"],"GEHomepageSuggestedEditsEnableTopics":true,"wgGETopicsMatchModeEnabled":false,"wgGELevelingUpEnabledForUser":false}; RLSTATE={"ext.globalCssJs.user.styles":"ready","site.styles":"ready","user.styles":"ready","ext.globalCssJs.user":"ready","user":"ready","user.options":"loading","ext.cite.styles":"ready","skins.vector.search.codex.styles":"ready","skins.vector.styles":"ready","skins.vector.icons":"ready","jquery.makeCollapsible.styles":"ready","ext.wikimediamessages.styles":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready","ext.uls.interlanguage":"ready","wikibase.client.init":"ready"};RLPAGEMODULES=["mediawiki.action.view.redirect","ext.cite.ux-enhancements","mediawiki.page.media","site","mediawiki.page.ready","jquery.makeCollapsible","mediawiki.toc","skins.vector.js","ext.centralNotice.geoIP","ext.centralNotice.startUp","ext.gadget.ReferenceTooltips","ext.gadget.switcher","ext.urlShortener.toolbar","ext.centralauth.centralautologin","mmv.bootstrap","ext.popups","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader","ext.echo.centralauth","ext.eventLogging","ext.wikimediaEvents","ext.navigationTiming","ext.uls.interface","ext.cx.eventlogging.campaigns","ext.cx.uls.quick.actions","wikibase.client.vector-2022","ext.checkUser.clientHints","ext.quicksurveys.init","ext.growthExperiments.SuggestedEditSession"];</script> <script>(RLQ=window.RLQ||[]).push(function(){mw.loader.impl(function(){return["user.options@12s5i",function($,jQuery,require,module){mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); }];});});</script> <link rel="stylesheet" href="/w/load.php?lang=en&modules=ext.cite.styles%7Cext.uls.interlanguage%7Cext.visualEditor.desktopArticleTarget.noscript%7Cext.wikimediamessages.styles%7Cjquery.makeCollapsible.styles%7Cskins.vector.icons%2Cstyles%7Cskins.vector.search.codex.styles%7Cwikibase.client.init&only=styles&skin=vector-2022"> <script async="" src="/w/load.php?lang=en&modules=startup&only=scripts&raw=1&skin=vector-2022"></script> <meta name="ResourceLoaderDynamicStyles" content=""> <link rel="stylesheet" href="/w/load.php?lang=en&modules=site.styles&only=styles&skin=vector-2022"> <meta name="generator" content="MediaWiki 1.44.0-wmf.23"> <meta name="referrer" content="origin"> <meta name="referrer" content="origin-when-cross-origin"> <meta name="robots" content="max-image-preview:standard"> <meta name="format-detection" content="telephone=no"> <meta name="viewport" content="width=1120"> <meta property="og:title" content="DDR4 SDRAM - Wikipedia"> <meta property="og:type" content="website"> <link rel="preconnect" href="//upload.wikimedia.org"> <link rel="alternate" media="only screen and (max-width: 640px)" href="//en.m.wikipedia.org/wiki/DDR4_SDRAM"> <link rel="alternate" type="application/x-wiki" title="Edit this page" href="/w/index.php?title=DDR4_SDRAM&action=edit"> <link rel="apple-touch-icon" href="/static/apple-touch/wikipedia.png"> <link rel="icon" href="/static/favicon/wikipedia.ico"> <link rel="search" type="application/opensearchdescription+xml" href="/w/rest.php/v1/search" title="Wikipedia (en)"> <link rel="EditURI" type="application/rsd+xml" href="//en.wikipedia.org/w/api.php?action=rsd"> <link rel="canonical" href="https://en.wikipedia.org/wiki/DDR4_SDRAM"> <link rel="license" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en"> <link rel="alternate" type="application/atom+xml" title="Wikipedia Atom feed" href="/w/index.php?title=Special:RecentChanges&feed=atom"> <link rel="dns-prefetch" href="//meta.wikimedia.org" /> <link rel="dns-prefetch" href="auth.wikimedia.org"> </head> <body class="skin--responsive skin-vector skin-vector-search-vue mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject mw-editable page-DDR4_SDRAM rootpage-DDR4_SDRAM skin-vector-2022 action-view"><a class="mw-jump-link" href="#bodyContent">Jump to content</a> <div class="vector-header-container"> <header class="vector-header mw-header"> <div class="vector-header-start"> <nav class="vector-main-menu-landmark" aria-label="Site"> <div id="vector-main-menu-dropdown" class="vector-dropdown vector-main-menu-dropdown vector-button-flush-left vector-button-flush-right" title="Main menu" > <input type="checkbox" id="vector-main-menu-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-main-menu-dropdown" class="vector-dropdown-checkbox " aria-label="Main menu" > <label id="vector-main-menu-dropdown-label" for="vector-main-menu-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-menu mw-ui-icon-wikimedia-menu"></span> <span class="vector-dropdown-label-text">Main menu</span> </label> <div class="vector-dropdown-content"> <div id="vector-main-menu-unpinned-container" class="vector-unpinned-container"> <div id="vector-main-menu" class="vector-main-menu vector-pinnable-element"> <div class="vector-pinnable-header vector-main-menu-pinnable-header vector-pinnable-header-unpinned" data-feature-name="main-menu-pinned" data-pinnable-element-id="vector-main-menu" data-pinned-container-id="vector-main-menu-pinned-container" data-unpinned-container-id="vector-main-menu-unpinned-container" > <div class="vector-pinnable-header-label">Main menu</div> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-main-menu.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-main-menu.unpin">hide</button> </div> <div id="p-navigation" class="vector-menu mw-portlet mw-portlet-navigation" > <div class="vector-menu-heading"> Navigation </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="n-mainpage-description" class="mw-list-item"><a href="/wiki/Main_Page" title="Visit the main page [z]" accesskey="z"><span>Main page</span></a></li><li id="n-contents" class="mw-list-item"><a href="/wiki/Wikipedia:Contents" title="Guides to browsing Wikipedia"><span>Contents</span></a></li><li id="n-currentevents" class="mw-list-item"><a href="/wiki/Portal:Current_events" title="Articles related to current events"><span>Current events</span></a></li><li id="n-randompage" class="mw-list-item"><a href="/wiki/Special:Random" title="Visit a randomly selected article [x]" accesskey="x"><span>Random article</span></a></li><li id="n-aboutsite" class="mw-list-item"><a href="/wiki/Wikipedia:About" title="Learn about Wikipedia and how it works"><span>About Wikipedia</span></a></li><li id="n-contactpage" class="mw-list-item"><a href="//en.wikipedia.org/wiki/Wikipedia:Contact_us" title="How to contact Wikipedia"><span>Contact us</span></a></li> </ul> </div> </div> <div id="p-interaction" class="vector-menu mw-portlet mw-portlet-interaction" > <div class="vector-menu-heading"> Contribute </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="n-help" class="mw-list-item"><a href="/wiki/Help:Contents" title="Guidance on how to use and edit Wikipedia"><span>Help</span></a></li><li id="n-introduction" class="mw-list-item"><a href="/wiki/Help:Introduction" title="Learn how to edit Wikipedia"><span>Learn to edit</span></a></li><li id="n-portal" class="mw-list-item"><a href="/wiki/Wikipedia:Community_portal" title="The hub for editors"><span>Community portal</span></a></li><li id="n-recentchanges" class="mw-list-item"><a href="/wiki/Special:RecentChanges" title="A list of recent changes to Wikipedia [r]" accesskey="r"><span>Recent changes</span></a></li><li id="n-upload" class="mw-list-item"><a href="/wiki/Wikipedia:File_upload_wizard" title="Add images or other media for use on Wikipedia"><span>Upload file</span></a></li><li id="n-specialpages" class="mw-list-item"><a href="/wiki/Special:SpecialPages"><span>Special pages</span></a></li> </ul> </div> </div> </div> </div> </div> </div> </nav> <a href="/wiki/Main_Page" class="mw-logo"> <img class="mw-logo-icon" src="/static/images/icons/wikipedia.png" alt="" aria-hidden="true" height="50" width="50"> <span class="mw-logo-container skin-invert"> <img class="mw-logo-wordmark" alt="Wikipedia" src="/static/images/mobile/copyright/wikipedia-wordmark-en.svg" style="width: 7.5em; height: 1.125em;"> <img class="mw-logo-tagline" alt="The Free Encyclopedia" src="/static/images/mobile/copyright/wikipedia-tagline-en.svg" width="117" height="13" style="width: 7.3125em; height: 0.8125em;"> </span> </a> </div> <div class="vector-header-end"> <div id="p-search" role="search" class="vector-search-box-vue vector-search-box-collapses vector-search-box-show-thumbnail vector-search-box-auto-expand-width vector-search-box"> <a href="/wiki/Special:Search" class="cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only search-toggle" title="Search Wikipedia [f]" accesskey="f"><span class="vector-icon mw-ui-icon-search mw-ui-icon-wikimedia-search"></span> <span>Search</span> </a> <div class="vector-typeahead-search-container"> <div class="cdx-typeahead-search cdx-typeahead-search--show-thumbnail cdx-typeahead-search--auto-expand-width"> <form action="/w/index.php" id="searchform" class="cdx-search-input cdx-search-input--has-end-button"> <div id="simpleSearch" class="cdx-search-input__input-wrapper" data-search-loc="header-moved"> <div class="cdx-text-input cdx-text-input--has-start-icon"> <input class="cdx-text-input__input" type="search" name="search" placeholder="Search Wikipedia" aria-label="Search Wikipedia" autocapitalize="sentences" title="Search Wikipedia [f]" accesskey="f" id="searchInput" > <span class="cdx-text-input__icon cdx-text-input__start-icon"></span> </div> <input type="hidden" name="title" value="Special:Search"> </div> <button class="cdx-button cdx-search-input__end-button">Search</button> </form> </div> </div> </div> <nav class="vector-user-links vector-user-links-wide" aria-label="Personal tools"> <div class="vector-user-links-main"> <div id="p-vector-user-menu-preferences" class="vector-menu mw-portlet emptyPortlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> </ul> </div> </div> <div id="p-vector-user-menu-userpage" class="vector-menu mw-portlet emptyPortlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> </ul> </div> </div> <nav class="vector-appearance-landmark" aria-label="Appearance"> <div id="vector-appearance-dropdown" class="vector-dropdown " title="Change the appearance of the page's font size, width, and color" > <input type="checkbox" id="vector-appearance-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-appearance-dropdown" class="vector-dropdown-checkbox " aria-label="Appearance" > <label id="vector-appearance-dropdown-label" for="vector-appearance-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-appearance mw-ui-icon-wikimedia-appearance"></span> <span class="vector-dropdown-label-text">Appearance</span> </label> <div class="vector-dropdown-content"> <div id="vector-appearance-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <div id="p-vector-user-menu-notifications" class="vector-menu mw-portlet emptyPortlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> </ul> </div> </div> <div id="p-vector-user-menu-overflow" class="vector-menu mw-portlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="pt-sitesupport-2" class="user-links-collapsible-item mw-list-item user-links-collapsible-item"><a data-mw="interface" href="https://donate.wikimedia.org/?wmf_source=donate&wmf_medium=sidebar&wmf_campaign=en.wikipedia.org&uselang=en" class=""><span>Donate</span></a> </li> <li id="pt-createaccount-2" class="user-links-collapsible-item mw-list-item user-links-collapsible-item"><a data-mw="interface" href="/w/index.php?title=Special:CreateAccount&returnto=DDR4+SDRAM" title="You are encouraged to create an account and log in; however, it is not mandatory" class=""><span>Create account</span></a> </li> <li id="pt-login-2" class="user-links-collapsible-item mw-list-item user-links-collapsible-item"><a data-mw="interface" href="/w/index.php?title=Special:UserLogin&returnto=DDR4+SDRAM" title="You're encouraged to log in; however, it's not mandatory. [o]" accesskey="o" class=""><span>Log in</span></a> </li> </ul> </div> </div> </div> <div id="vector-user-links-dropdown" class="vector-dropdown vector-user-menu vector-button-flush-right vector-user-menu-logged-out" title="Log in and more options" > <input type="checkbox" id="vector-user-links-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-user-links-dropdown" class="vector-dropdown-checkbox " aria-label="Personal tools" > <label id="vector-user-links-dropdown-label" for="vector-user-links-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-ellipsis mw-ui-icon-wikimedia-ellipsis"></span> <span class="vector-dropdown-label-text">Personal tools</span> </label> <div class="vector-dropdown-content"> <div id="p-personal" class="vector-menu mw-portlet mw-portlet-personal user-links-collapsible-item" title="User menu" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="pt-sitesupport" class="user-links-collapsible-item mw-list-item"><a href="https://donate.wikimedia.org/?wmf_source=donate&wmf_medium=sidebar&wmf_campaign=en.wikipedia.org&uselang=en"><span>Donate</span></a></li><li id="pt-createaccount" class="user-links-collapsible-item mw-list-item"><a href="/w/index.php?title=Special:CreateAccount&returnto=DDR4+SDRAM" title="You are encouraged to create an account and log in; however, it is not mandatory"><span class="vector-icon mw-ui-icon-userAdd mw-ui-icon-wikimedia-userAdd"></span> <span>Create account</span></a></li><li id="pt-login" class="user-links-collapsible-item mw-list-item"><a href="/w/index.php?title=Special:UserLogin&returnto=DDR4+SDRAM" title="You're encouraged to log in; however, it's not mandatory. [o]" accesskey="o"><span class="vector-icon mw-ui-icon-logIn mw-ui-icon-wikimedia-logIn"></span> <span>Log in</span></a></li> </ul> </div> </div> <div id="p-user-menu-anon-editor" class="vector-menu mw-portlet mw-portlet-user-menu-anon-editor" > <div class="vector-menu-heading"> Pages for logged out editors <a href="/wiki/Help:Introduction" aria-label="Learn more about editing"><span>learn more</span></a> </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="pt-anoncontribs" class="mw-list-item"><a href="/wiki/Special:MyContributions" title="A list of edits made from this IP address [y]" accesskey="y"><span>Contributions</span></a></li><li id="pt-anontalk" class="mw-list-item"><a href="/wiki/Special:MyTalk" title="Discussion about edits from this IP address [n]" accesskey="n"><span>Talk</span></a></li> </ul> </div> </div> </div> </div> </nav> </div> </header> </div> <div class="mw-page-container"> <div class="mw-page-container-inner"> <div class="vector-sitenotice-container"> <div id="siteNotice"></div> </div> <div class="vector-column-start"> <div class="vector-main-menu-container"> <div id="mw-navigation"> <nav id="mw-panel" class="vector-main-menu-landmark" aria-label="Site"> <div id="vector-main-menu-pinned-container" class="vector-pinned-container"> </div> </nav> </div> </div> <div class="vector-sticky-pinned-container"> <nav id="mw-panel-toc" aria-label="Contents" data-event-name="ui.sidebar-toc" class="mw-table-of-contents-container vector-toc-landmark"> <div id="vector-toc-pinned-container" class="vector-pinned-container"> <div id="vector-toc" class="vector-toc vector-pinnable-element"> <div class="vector-pinnable-header vector-toc-pinnable-header vector-pinnable-header-pinned" data-feature-name="toc-pinned" data-pinnable-element-id="vector-toc" > <h2 class="vector-pinnable-header-label">Contents</h2> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-toc.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-toc.unpin">hide</button> </div> <ul class="vector-toc-contents" id="mw-panel-toc-list"> <li id="toc-mw-content-text" class="vector-toc-list-item vector-toc-level-1"> <a href="#" class="vector-toc-link"> <div class="vector-toc-text">(Top)</div> </a> </li> <li id="toc-Features" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Features"> <div class="vector-toc-text"> <span class="vector-toc-numb">1</span> <span>Features</span> </div> </a> <ul id="toc-Features-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Timeline" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Timeline"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Timeline</span> </div> </a> <button aria-controls="toc-Timeline-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Timeline subsection</span> </button> <ul id="toc-Timeline-sublist" class="vector-toc-list"> <li id="toc-Market_perception_and_adoption" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Market_perception_and_adoption"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Market perception and adoption</span> </div> </a> <ul id="toc-Market_perception_and_adoption-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Operation" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Operation"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Operation</span> </div> </a> <button aria-controls="toc-Operation-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Operation subsection</span> </button> <ul id="toc-Operation-sublist" class="vector-toc-list"> <li id="toc-Command_encoding" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Command_encoding"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Command encoding</span> </div> </a> <ul id="toc-Command_encoding-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Design_considerations" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Design_considerations"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Design considerations</span> </div> </a> <ul id="toc-Design_considerations-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Modules" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Modules"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Modules</span> </div> </a> <button aria-controls="toc-Modules-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Modules subsection</span> </button> <ul id="toc-Modules-sublist" class="vector-toc-list"> <li id="toc-Module_packaging" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Module_packaging"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1</span> <span>Module packaging</span> </div> </a> <ul id="toc-Module_packaging-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-JEDEC_standard_DDR4_module" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#JEDEC_standard_DDR4_module"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.2</span> <span>JEDEC standard DDR4 module</span> </div> </a> <ul id="toc-JEDEC_standard_DDR4_module-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Successor" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Successor"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Successor</span> </div> </a> <ul id="toc-Successor-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" title="Table of Contents" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">DDR4 SDRAM</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 22 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-22" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">22 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%AF%D9%8A_%D8%AF%D9%8A_%D8%A2%D8%B1_4_%D8%A5%D8%B3_%D8%AF%D9%8A_%D8%B1%D8%A7%D9%85" title="دي دي آر 4 إس دي رام – Arabic" lang="ar" hreflang="ar" data-title="دي دي آر 4 إس دي رام" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Catalan" lang="ca" hreflang="ca" data-title="DDR4 SDRAM" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Czech" lang="cs" hreflang="cs" data-title="DDR4 SDRAM" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/DDR-SDRAM#DDR4-SDRAM" title="DDR-SDRAM – German" lang="de" hreflang="de" data-title="DDR-SDRAM" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Estonian" lang="et" hreflang="et" data-title="DDR4 SDRAM" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Spanish" lang="es" hreflang="es" data-title="DDR4 SDRAM" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – French" lang="fr" hreflang="fr" data-title="DDR4 SDRAM" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Korean" lang="ko" hreflang="ko" data-title="DDR4 SDRAM" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/DDR4" title="DDR4 – Italian" lang="it" hreflang="it" data-title="DDR4" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-lt mw-list-item"><a href="https://lt.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Lithuanian" lang="lt" hreflang="lt" data-title="DDR4 SDRAM" data-language-autonym="Lietuvių" data-language-local-name="Lithuanian" class="interlanguage-link-target"><span>Lietuvių</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%A1%E0%B4%BF%E0%B4%A1%E0%B4%BF%E0%B4%86%E0%B5%BC_4_%E0%B4%8E%E0%B4%B8%E0%B5%8D%E0%B4%A1%E0%B4%BF%E0%B4%B1%E0%B4%BE%E0%B4%82" title="ഡിഡിആർ 4 എസ്ഡിറാം – Malayalam" lang="ml" hreflang="ml" data-title="ഡിഡിആർ 4 എസ്ഡിറാം" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Japanese" lang="ja" hreflang="ja" data-title="DDR4 SDRAM" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="DDR4 SDRAM" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-uz mw-list-item"><a href="https://uz.wikipedia.org/wiki/DDR4" title="DDR4 – Uzbek" lang="uz" hreflang="uz" data-title="DDR4" data-language-autonym="Oʻzbekcha / ўзбекча" data-language-local-name="Uzbek" class="interlanguage-link-target"><span>Oʻzbekcha / ўзбекча</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/DDR4" title="DDR4 – Polish" lang="pl" hreflang="pl" data-title="DDR4" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Portuguese" lang="pt" hreflang="pt" data-title="DDR4 SDRAM" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Russian" lang="ru" hreflang="ru" data-title="DDR4 SDRAM" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Slovak" lang="sk" hreflang="sk" data-title="DDR4 SDRAM" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Serbian" lang="sr" hreflang="sr" data-title="DDR4 SDRAM" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Swedish" lang="sv" hreflang="sv" data-title="DDR4 SDRAM" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Ukrainian" lang="uk" hreflang="uk" data-title="DDR4 SDRAM" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/DDR4_SDRAM" title="DDR4 SDRAM – Chinese" lang="zh" hreflang="zh" data-title="DDR4 SDRAM" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q1189682#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> <nav aria-label="Namespaces"> <div id="p-associated-pages" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-associated-pages" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-nstab-main" class="selected vector-tab-noicon mw-list-item"><a href="/wiki/DDR4_SDRAM" title="View the content page [c]" accesskey="c"><span>Article</span></a></li><li id="ca-talk" class="vector-tab-noicon mw-list-item"><a href="/wiki/Talk:DDR4_SDRAM" rel="discussion" title="Discuss improvements to the content page [t]" accesskey="t"><span>Talk</span></a></li> </ul> </div> </div> <div id="vector-variants-dropdown" class="vector-dropdown emptyPortlet" > <input type="checkbox" id="vector-variants-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-variants-dropdown" class="vector-dropdown-checkbox " aria-label="Change language variant" > <label id="vector-variants-dropdown-label" for="vector-variants-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet" aria-hidden="true" ><span class="vector-dropdown-label-text">English</span> </label> <div class="vector-dropdown-content"> <div id="p-variants" class="vector-menu mw-portlet mw-portlet-variants emptyPortlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> </ul> </div> </div> </div> </div> </nav> </div> <div id="right-navigation" class="vector-collapsible"> <nav aria-label="Views"> <div id="p-views" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-views" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-view" class="selected vector-tab-noicon mw-list-item"><a href="/wiki/DDR4_SDRAM"><span>Read</span></a></li><li id="ca-edit" class="vector-tab-noicon mw-list-item"><a href="/w/index.php?title=DDR4_SDRAM&action=edit" title="Edit this page [e]" accesskey="e"><span>Edit</span></a></li><li id="ca-history" class="vector-tab-noicon mw-list-item"><a href="/w/index.php?title=DDR4_SDRAM&action=history" title="Past revisions of this page [h]" accesskey="h"><span>View history</span></a></li> </ul> </div> </div> </nav> <nav class="vector-page-tools-landmark" aria-label="Page tools"> <div id="vector-page-tools-dropdown" class="vector-dropdown vector-page-tools-dropdown" > <input type="checkbox" id="vector-page-tools-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-tools-dropdown" class="vector-dropdown-checkbox " aria-label="Tools" > <label id="vector-page-tools-dropdown-label" for="vector-page-tools-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet" aria-hidden="true" ><span class="vector-dropdown-label-text">Tools</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-tools-unpinned-container" class="vector-unpinned-container"> <div id="vector-page-tools" class="vector-page-tools vector-pinnable-element"> <div class="vector-pinnable-header vector-page-tools-pinnable-header vector-pinnable-header-unpinned" data-feature-name="page-tools-pinned" data-pinnable-element-id="vector-page-tools" data-pinned-container-id="vector-page-tools-pinned-container" data-unpinned-container-id="vector-page-tools-unpinned-container" > <div class="vector-pinnable-header-label">Tools</div> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-page-tools.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-page-tools.unpin">hide</button> </div> <div id="p-cactions" class="vector-menu mw-portlet mw-portlet-cactions emptyPortlet vector-has-collapsible-items" title="More options" > <div class="vector-menu-heading"> Actions </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-more-view" class="selected vector-more-collapsible-item mw-list-item"><a href="/wiki/DDR4_SDRAM"><span>Read</span></a></li><li id="ca-more-edit" class="vector-more-collapsible-item mw-list-item"><a href="/w/index.php?title=DDR4_SDRAM&action=edit" title="Edit this page [e]" accesskey="e"><span>Edit</span></a></li><li id="ca-more-history" class="vector-more-collapsible-item mw-list-item"><a href="/w/index.php?title=DDR4_SDRAM&action=history"><span>View history</span></a></li> </ul> </div> </div> <div id="p-tb" class="vector-menu mw-portlet mw-portlet-tb" > <div class="vector-menu-heading"> General </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="t-whatlinkshere" class="mw-list-item"><a href="/wiki/Special:WhatLinksHere/DDR4_SDRAM" title="List of all English Wikipedia pages containing links to this page [j]" accesskey="j"><span>What links here</span></a></li><li id="t-recentchangeslinked" class="mw-list-item"><a href="/wiki/Special:RecentChangesLinked/DDR4_SDRAM" rel="nofollow" title="Recent changes in pages linked from this page [k]" accesskey="k"><span>Related changes</span></a></li><li id="t-upload" class="mw-list-item"><a href="//en.wikipedia.org/wiki/Wikipedia:File_Upload_Wizard" title="Upload files [u]" accesskey="u"><span>Upload file</span></a></li><li id="t-permalink" class="mw-list-item"><a href="/w/index.php?title=DDR4_SDRAM&oldid=1278891957" title="Permanent link to this revision of this page"><span>Permanent link</span></a></li><li id="t-info" class="mw-list-item"><a href="/w/index.php?title=DDR4_SDRAM&action=info" title="More information about this page"><span>Page information</span></a></li><li id="t-cite" class="mw-list-item"><a href="/w/index.php?title=Special:CiteThisPage&page=DDR4_SDRAM&id=1278891957&wpFormIdentifier=titleform" title="Information on how to cite this page"><span>Cite this page</span></a></li><li id="t-urlshortener" class="mw-list-item"><a href="/w/index.php?title=Special:UrlShortener&url=https%3A%2F%2Fen.wikipedia.org%2Fwiki%2FDDR4_SDRAM"><span>Get shortened URL</span></a></li><li id="t-urlshortener-qrcode" class="mw-list-item"><a href="/w/index.php?title=Special:QrCode&url=https%3A%2F%2Fen.wikipedia.org%2Fwiki%2FDDR4_SDRAM"><span>Download QR code</span></a></li> </ul> </div> </div> <div id="p-coll-print_export" class="vector-menu mw-portlet mw-portlet-coll-print_export" > <div class="vector-menu-heading"> Print/export </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="coll-download-as-rl" class="mw-list-item"><a href="/w/index.php?title=Special:DownloadAsPdf&page=DDR4_SDRAM&action=show-download-screen" title="Download this page as a PDF file"><span>Download as PDF</span></a></li><li id="t-print" class="mw-list-item"><a href="/w/index.php?title=DDR4_SDRAM&printable=yes" title="Printable version of this page [p]" accesskey="p"><span>Printable version</span></a></li> </ul> </div> </div> <div id="p-wikibase-otherprojects" class="vector-menu mw-portlet mw-portlet-wikibase-otherprojects" > <div class="vector-menu-heading"> In other projects </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="wb-otherproject-link wb-otherproject-commons mw-list-item"><a href="https://commons.wikimedia.org/wiki/Category:DDR4_RAM" hreflang="en"><span>Wikimedia Commons</span></a></li><li id="t-wikibase" class="wb-otherproject-link wb-otherproject-wikibase-dataitem mw-list-item"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q1189682" title="Structured data on this page hosted by Wikidata [g]" accesskey="g"><span>Wikidata item</span></a></li> </ul> </div> </div> </div> </div> </div> </div> </nav> </div> </div> </div> <div class="vector-column-end"> <div class="vector-sticky-pinned-container"> <nav class="vector-page-tools-landmark" aria-label="Page tools"> <div id="vector-page-tools-pinned-container" class="vector-pinned-container"> </div> </nav> <nav class="vector-appearance-landmark" aria-label="Appearance"> <div id="vector-appearance-pinned-container" class="vector-pinned-container"> <div id="vector-appearance" class="vector-appearance vector-pinnable-element"> <div class="vector-pinnable-header vector-appearance-pinnable-header vector-pinnable-header-pinned" data-feature-name="appearance-pinned" data-pinnable-element-id="vector-appearance" data-pinned-container-id="vector-appearance-pinned-container" data-unpinned-container-id="vector-appearance-unpinned-container" > <div class="vector-pinnable-header-label">Appearance</div> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-appearance.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-appearance.unpin">hide</button> </div> </div> </div> </nav> </div> </div> <div id="bodyContent" class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"><span class="mw-redirectedfrom">(Redirected from <a href="/w/index.php?title=DDR4&redirect=no" class="mw-redirect" title="DDR4">DDR4</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Type of computer memory introduced 2014</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">This article is about DDR4 SDRAM. For graphics DDR4, see <a href="/wiki/GDDR4_SDRAM" title="GDDR4 SDRAM">GDDR4 SDRAM</a>. For the video game, see <a href="/wiki/Dance_Dance_Revolution_4thMix" title="Dance Dance Revolution 4thMix">Dance Dance Revolution 4thMix</a>.</div> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">DDR4 SDRAM<br /><span style="font-size: 85%;">Double Data Rate 4 Synchronous Dynamic Random-Access Memory</span></caption><tbody><tr><td colspan="2" class="infobox-subheader">Type of <a href="/wiki/RAM" class="mw-redirect" title="RAM">RAM</a></td></tr><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:16_GiB-DDR4-RAM-Riegel_RAM019FIX_Small_Crop_90_PCNT.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/85/16_GiB-DDR4-RAM-Riegel_RAM019FIX_Small_Crop_90_PCNT.png/250px-16_GiB-DDR4-RAM-Riegel_RAM019FIX_Small_Crop_90_PCNT.png" decoding="async" width="220" height="53" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/85/16_GiB-DDR4-RAM-Riegel_RAM019FIX_Small_Crop_90_PCNT.png/330px-16_GiB-DDR4-RAM-Riegel_RAM019FIX_Small_Crop_90_PCNT.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/85/16_GiB-DDR4-RAM-Riegel_RAM019FIX_Small_Crop_90_PCNT.png/500px-16_GiB-DDR4-RAM-Riegel_RAM019FIX_Small_Crop_90_PCNT.png 2x" data-file-width="23294" data-file-height="5661" /></a></span><div class="infobox-caption">16 <a href="/wiki/Gigabyte" title="Gigabyte">GB</a><sup id="cite_ref-binpre_1-0" class="reference"><a href="#cite_note-binpre-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> DDR4-2666 1.2 V <a href="/wiki/UDIMM" class="mw-redirect" title="UDIMM">UDIMM</a></div></td></tr><tr><th scope="row" class="infobox-label">Developer</th><td class="infobox-data"><a href="/wiki/JEDEC" title="JEDEC">JEDEC</a></td></tr><tr><th scope="row" class="infobox-label">Type</th><td class="infobox-data"><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous dynamic random-access memory</a> (SDRAM)</td></tr><tr><th scope="row" class="infobox-label">Generation</th><td class="infobox-data">4th generation</td></tr><tr><th scope="row" class="infobox-label">Release date</th><td class="infobox-data">2014<span class="noprint">; 11 years ago</span><span style="display:none"> (<span class="bday dtstart published updated">2014</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Standards</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li>DDR4-1600 (PC4-12800)</li><li>DDR4-1866 (PC4-14900)</li><li>DDR4-2133 (PC4-17000)</li><li>DDR4-2400 (PC4-19200)</li><li>DDR4-2666 (PC4-21300)</li><li>DDR4-2933 (PC4-23466)</li><li>DDR4-3200 (PC4-25600)</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></th><td class="infobox-data"><span class="nowrap">800–1600 MHz</span></td></tr><tr><th scope="row" class="infobox-label">Cycle time</th><td class="infobox-data">0.625 ns to 1.25 ns</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Prefetch_buffer" class="mw-redirect" title="Prefetch buffer">Prefetch buffer</a></th><td class="infobox-data">8n-prefetch architecture</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus</a> clock rate</th><td class="infobox-data">1600 MT/s to 3200 MT/s.</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Transfer_(computing)" class="mw-redirect" title="Transfer (computing)">Transfer rate</a></th><td class="infobox-data">12.8 GB/s to 25.6 GB/s</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Voltage" title="Voltage">Voltage</a></th><td class="infobox-data"><span class="nowrap"> Reference 1.2 V</span></td></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a> (2007)</td></tr><tr><th scope="row" class="infobox-label">Successor</th><td class="infobox-data"><a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5 SDRAM</a> (2020)</td></tr></tbody></table> <p><b>Double Data Rate 4 Synchronous Dynamic Random-Access Memory</b> (<b>DDR4 SDRAM</b>) is a type of <a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">synchronous dynamic random-access memory</a> with a high <a href="/wiki/Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a> ("<a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a>") interface. </p><p>Released to the market in 2014,<sup id="cite_ref-hynix_April_2011_2-0" class="reference"><a href="#cite_note-hynix_April_2011-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-micron_May_2012_3-0" class="reference"><a href="#cite_note-micron_May_2012-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> it is a variant of <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">dynamic random-access memory</a> (DRAM), some of which have been in use since the early 1970s,<sup id="cite_ref-dram_story_5-0" class="reference"><a href="#cite_note-dram_story-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> and a higher-speed successor to the <a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> and <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a> technologies. </p><p>DDR4 is not compatible with any earlier type of random-access memory (RAM) due to different signaling voltage and physical interface, besides other factors. </p><p>DDR4 <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">SDRAM</a> was released to the public market in Q2 2014, focusing on <a href="/wiki/ECC_memory" title="ECC memory">ECC memory</a>,<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> while the non-ECC DDR4 modules became available in Q3 2014, accompanying the launch of <a href="/wiki/Haswell-E" class="mw-redirect" title="Haswell-E">Haswell-E</a> processors that require DDR4 memory.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Features">Features</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=1" title="Edit section: Features"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The primary advantages of DDR4 over its predecessor, DDR3, include higher module density and lower voltage requirements, coupled with higher <a href="/wiki/Bit_rate#Goodput_(data_transfer_rate)" title="Bit rate">data rate transfer</a> speeds. The DDR4 standard allows for <a href="/wiki/DIMM" title="DIMM">DIMMs</a> of up to 64 <a href="/wiki/Gigabyte" title="Gigabyte">GB</a> in capacity, compared to DDR3's maximum of 16 GB per DIMM.<sup id="cite_ref-binpre_1-1" class="reference"><a href="#cite_note-binpre-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup><sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability"><span title="The material near this tag failed verification of its source citation(s). (September 2019)">failed verification</span></a></i>]</sup> </p><p>Unlike previous generations of DDR memory, <a href="/wiki/Prefetch_buffer" class="mw-redirect" title="Prefetch buffer">prefetch</a> has <i>not</i> been increased above the 8n used in DDR3;<sup id="cite_ref-SamsungIDF_9-0" class="reference"><a href="#cite_note-SamsungIDF-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 16">: 16 </span></sup> the basic burst size is eight 64-bit words, and higher bandwidths are achieved by sending more read/write commands per second. To allow this, the standard divides the DRAM banks into two or four selectable bank groups,<sup id="cite_ref-JEDEC_10-0" class="reference"><a href="#cite_note-JEDEC-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> where transfers to different bank groups may be done more rapidly. </p><p>Because power consumption increases with speed, the reduced voltage allows higher speed operation without unreasonable power and cooling requirements. </p><p><b>DDR4 RAM</b> operates at a voltage of <b>1.2 V</b> and supports frequencies between <b>800 and 1600 MHz</b> (DDR4-1600 through DDR4-3200). Compared to DDR3, which operates at <b>1.5 V</b> with <a href="/wiki/Frequency" title="Frequency">frequencies</a> from <b>400 to 1067 MHz</b> (DDR3-800 through DDR3-2133), DDR4 offers better performance and <a href="/wiki/Efficient_energy_use" title="Efficient energy use">energy efficiency</a>. DDR4 speeds are advertised as double the base clock rate due to its Double Data Rate (DDR) nature, with common speeds including DDR4-2400 and DDR4-3200, and higher speeds like DDR4-4266 and DDR4-5000 available at a premium. Unlike DDR3, DDR4 does not have a low voltage variant; it consistently operates at <b>1.2 V</b>. Additionally, DDR4 improves on DDR3 with a longer burst length of 16 and supports larger memory capacities, enhancing both performance and system flexibility.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Timeline">Timeline</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=2" title="Edit section: Timeline"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure typeof="mw:File/Thumb"><a href="/wiki/File:Samsung_displays_first_DDR4_module.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/en/thumb/d/d3/Samsung_displays_first_DDR4_module.jpg/330px-Samsung_displays_first_DDR4_module.jpg" decoding="async" width="330" height="78" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/d/d3/Samsung_displays_first_DDR4_module.jpg 1.5x" data-file-width="484" data-file-height="114" /></a><figcaption>The first DDR4 memory module prototype was manufactured by <a href="/wiki/Samsung" title="Samsung">Samsung</a> and announced in January 2011.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup></figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Desktop_DDR_Memory_Comparison.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1b/Desktop_DDR_Memory_Comparison.svg/250px-Desktop_DDR_Memory_Comparison.svg.png" decoding="async" width="220" height="331" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1b/Desktop_DDR_Memory_Comparison.svg/330px-Desktop_DDR_Memory_Comparison.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1b/Desktop_DDR_Memory_Comparison.svg/500px-Desktop_DDR_Memory_Comparison.svg.png 2x" data-file-width="575" data-file-height="865" /></a><figcaption>Physical comparison of <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR</a>, <a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a>, <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a>, and DDR4 SDRAM</figcaption></figure> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:2*8Go_DDR4_Corsair_-_2018-05-08.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/94/2%2A8Go_DDR4_Corsair_-_2018-05-08.jpg/250px-2%2A8Go_DDR4_Corsair_-_2018-05-08.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/94/2%2A8Go_DDR4_Corsair_-_2018-05-08.jpg/330px-2%2A8Go_DDR4_Corsair_-_2018-05-08.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/94/2%2A8Go_DDR4_Corsair_-_2018-05-08.jpg/500px-2%2A8Go_DDR4_Corsair_-_2018-05-08.jpg 2x" data-file-width="4032" data-file-height="3024" /></a><figcaption>Front and back of 8 GB<sup id="cite_ref-binpre_1-2" class="reference"><a href="#cite_note-binpre-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> DDR4 memory modules</figcaption></figure> <ul><li><b>2005:</b> Standards body <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a> began working on a successor to DDR3 around 2005,<sup id="cite_ref-digitimes_2005_15-0" class="reference"><a href="#cite_note-digitimes_2005-15"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> about 2 years before the launch of DDR3 in 2007.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> The high-level architecture of DDR4 was planned for completion in 2008.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup></li> <li><b>2007:</b> Some advance information was published in 2007,<sup id="cite_ref-The_H_19-0" class="reference"><a href="#cite_note-The_H-19"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> and a guest speaker from <a href="/wiki/Qimonda" title="Qimonda">Qimonda</a> provided further public details in a presentation at the August 2008 <a href="/wiki/San_Francisco" title="San Francisco">San Francisco</a> <a href="/wiki/Intel_Developer_Forum" title="Intel Developer Forum">Intel Developer Forum</a> (IDF).<sup id="cite_ref-The_H_19-1" class="reference"><a href="#cite_note-The_H-19"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-pc_pro_2008_20-0" class="reference"><a href="#cite_note-pc_pro_2008-20"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-computerbase_2008_21-0" class="reference"><a href="#cite_note-computerbase_2008-21"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-inquirer_2008_22-0" class="reference"><a href="#cite_note-inquirer_2008-22"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> DDR4 was described as involving a 30 nm process at 1.2 volts, with <a href="/wiki/Bus_(computing)" title="Bus (computing)">bus</a> frequencies of 2133 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.<sup id="cite_ref-pc_pro_2008_20-1" class="reference"><a href="#cite_note-pc_pro_2008-20"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-inquirer_2008_22-1" class="reference"><a href="#cite_note-inquirer_2008-22"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup></li> <li><b>2009:</b> In February, <a href="/wiki/Samsung" title="Samsung">Samsung</a> validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> since in 2009, DRAM chips were only beginning to migrate to a 50 nm process.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup></li> <li><b>2010:</b> Subsequently, further details were revealed at MemCon 2010, <a href="/wiki/Tokyo" title="Tokyo">Tokyo</a> (a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4"<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> or definitely<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> delayed until 2015. However, DDR4 <a href="/wiki/Engineering_sample" title="Engineering sample">test samples</a> were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.<sup id="cite_ref-hynix_April_2011_2-1" class="reference"><a href="#cite_note-hynix_April_2011-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup></li> <li><b>2011:</b> In January, <a href="/wiki/Samsung" title="Samsung">Samsung</a> announced the completion and release for testing of a 2 GB<sup id="cite_ref-binpre_1-3" class="reference"><a href="#cite_note-binpre-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR4</a> DRAM module based on a process between 30 and 39 <a href="/wiki/Nanometer" class="mw-redirect" title="Nanometer">nm</a>.<sup id="cite_ref-samsung_1_29-0" class="reference"><a href="#cite_note-samsung_1-29"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> It has a maximum data transfer rate of 2133 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> at 1.2 V, uses <a href="/wiki/Open_drain" class="mw-redirect" title="Open drain">pseudo open drain</a> technology (adapted from <a href="/wiki/GDDR" class="mw-redirect" title="GDDR">graphics DDR</a> memory<sup id="cite_ref-techgage_30-0" class="reference"><a href="#cite_note-techgage-30"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup>) and draws 40% less power than an equivalent DDR3 module.<sup id="cite_ref-samsung_1_29-1" class="reference"><a href="#cite_note-samsung_1-29"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><br />In April, <a href="/wiki/Hynix" class="mw-redirect" title="Hynix">Hynix</a> announced the production of 2 GB<sup id="cite_ref-binpre_1-4" class="reference"><a href="#cite_note-binpre-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified),<sup id="cite_ref-hynix_April_2011_2-2" class="reference"><a href="#cite_note-hynix_April_2011-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> adding that it anticipated commencing high volume production in the second half of 2012.<sup id="cite_ref-hynix_April_2011_2-3" class="reference"><a href="#cite_note-hynix_April_2011-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> Semiconductor processes for DDR4 were expected to transition to sub-30 nm at some point between late 2012 and 2014.<sup id="cite_ref-PC_Watch_32-0" class="reference"><a href="#cite_note-PC_Watch-32"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-PC_Watch_(diagram_1)_33-0" class="reference"><a href="#cite_note-PC_Watch_(diagram_1)-33"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup></li> <li><b>2012:</b> In May, <a href="/wiki/Micron_Technology" title="Micron Technology">Micron</a> announced<sup id="cite_ref-micron_May_2012_3-1" class="reference"><a href="#cite_note-micron_May_2012-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> it was aiming at starting production in late 2012 of 30 nm modules. In July, Samsung announced that it would begin sampling the industry's first 16 GB<sup id="cite_ref-binpre_1-5" class="reference"><a href="#cite_note-binpre-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> registered dual inline memory modules (RDIMMs) using DDR4 SDRAM for enterprise server systems.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> In September, JEDEC released the final specification of DDR4.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup></li> <li><b>2013:</b> DDR4 was expected to represent 5% of the DRAM market in 2013,<sup id="cite_ref-hynix_April_2011_2-4" class="reference"><a href="#cite_note-hynix_April_2011-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> and to reach <a href="/wiki/Mass_market" title="Mass market">mass market</a> adoption and 50% <a href="/wiki/Market_penetration" title="Market penetration">market penetration</a> around 2015;<sup id="cite_ref-hynix_April_2011_2-5" class="reference"><a href="#cite_note-hynix_April_2011-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> as of 2013, however, adoption of DDR4 had been delayed and it was no longer expected to reach a majority of the market until 2016 or later.<sup id="cite_ref-TechHive_April_2013_37-0" class="reference"><a href="#cite_note-TechHive_April_2013-37"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> The transition from DDR3 to DDR4 is thus taking longer than the approximately five years taken for DDR3 to achieve mass market transition over DDR2.<sup id="cite_ref-PC_Watch_32-1" class="reference"><a href="#cite_note-PC_Watch-32"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> In part, this is because changes required to other components would affect all other parts of computer systems, which would need to be updated to work with DDR4.<sup id="cite_ref-xbit_38-0" class="reference"><a href="#cite_note-xbit-38"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup></li> <li><b>2014:</b> In April, Hynix announced that it had developed the world's first highest-density 128 GB module based on 8 <a href="/wiki/Gigabit" class="mw-redirect" title="Gigabit">Gbit</a> DDR4 using 20 nm technology. The module works at 2133 MHz, with a 64-bit I/O, and processes up to 17 GB of data per second.</li> <li><b>2016:</b> In April, Samsung announced that they had begun to mass-produce DRAM on a "10 nm-class" process, by which they mean the 1x nm node regime of 16 nm to 19 nm, which supports a 30% faster data transfer rate of 3,200 Mbit/s.<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> Previously, a size of 20 nm was used.<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup></li> <li><b>2020:</b> DDR5 RAM was formally introduced by the <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a> Solid State Technology Association in July 2020 as the successor to DDR4. JEDEC, a global leader in developing open standards for the <a href="/wiki/Microelectronics" title="Microelectronics">microelectronics</a> industry, spearheaded the development of DDR5 to address the growing demands for higher performance and efficiency in modern computing. The <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a> standard builds on the advancements of DDR4 with notable improvements in bandwidth, efficiency, and capacity, offering a base data rate of 4800 MT/s and supporting higher speeds as the technology matures. DDR5 also features enhanced power management, increased burst length, and improved prefetch capabilities, making it suitable for a wide range of applications from high-performance gaming to data-intensive computing tasks.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Market_perception_and_adoption">Market perception and adoption</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=3" title="Edit section: Market perception and adoption"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In April 2013, a news writer at <a href="/wiki/International_Data_Group" title="International Data Group">International Data Group</a> (IDG) – an American technology research business originally part of <a href="/wiki/International_Data_Corporation" class="mw-redirect" title="International Data Corporation">IDC</a> – produced an analysis of their perceptions related to DDR4 SDRAM.<sup id="cite_ref-IDG_2013_42-0" class="reference"><a href="#cite_note-IDG_2013-42"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> The conclusions were that the increasing popularity of <a href="/wiki/Mobile_computing" title="Mobile computing">mobile computing</a> and other devices using slower but low-powered memory, the slowing of growth in the traditional <a href="/wiki/Desktop_computing" class="mw-redirect" title="Desktop computing">desktop computing</a> sector, and the <a href="/wiki/Consolidation_(economics)" class="mw-redirect" title="Consolidation (economics)">consolidation</a> of the memory manufacturing marketplace, meant that margins on RAM were tight. </p><p>As a result, the desired <a href="/wiki/Premium_pricing" title="Premium pricing">premium pricing</a> for the new technology was harder to achieve, and capacity had shifted to other sectors. SDRAM manufacturers and chipset creators were, to an extent, "stuck between a rock and a hard place" where "nobody wants to pay a premium for DDR4 products, and manufacturers don't want to make the memory if they are not going to get a premium", according to Mike Howard from iSuppli.<sup id="cite_ref-IDG_2013_42-1" class="reference"><a href="#cite_note-IDG_2013-42"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> A switch in <a href="/wiki/Consumer_sentiment" class="mw-redirect" title="Consumer sentiment">consumer sentiment</a> toward desktop computing and release of processors having DDR4 support by <a href="/wiki/Intel" title="Intel">Intel</a> and <a href="/wiki/AMD" title="AMD">AMD</a> could therefore potentially lead to "aggressive" growth.<sup id="cite_ref-IDG_2013_42-2" class="reference"><a href="#cite_note-IDG_2013-42"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> </p><p>Intel's 2014 <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> roadmap, revealed the company's first use of DDR4 SDRAM in <a href="/wiki/Haswell-EP" class="mw-redirect" title="Haswell-EP">Haswell-EP</a> processors.<sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> </p><p>AMD's <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a> processors, revealed in 2016 and shipped in 2017, use DDR4 SDRAM.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Operation">Operation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=4" title="Edit section: Operation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Update plainlinks metadata ambox ambox-content ambox-Update" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/b/bd/Ambox_current_red_Asia_Australia.svg/60px-Ambox_current_red_Asia_Australia.svg.png" decoding="async" width="42" height="34" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/bd/Ambox_current_red_Asia_Australia.svg/120px-Ambox_current_red_Asia_Australia.svg.png 1.5x" data-file-width="360" data-file-height="290" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">This section needs to be <b>updated</b>.<span class="hide-when-compact"> Please help update this article to reflect recent events or newly available information.</span> <span class="date-container"><i>(<span class="date">January 2014</span>)</i></span></div></td></tr></tbody></table> <p><b>DDR4 RAM</b> operates with a primary supply voltage of <b>1.2 V</b> and an auxiliary <b>2.5 V</b> supply for wordline boosting (<a rel="nofollow" class="external text" href="https://patents.google.com/patent/EP1528571A2/en">VPP</a>). This contrasts with <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a>, which runs at <b>1.5 V</b> and had lower voltage variants at <b>1.35 V</b> introduced in 2013. DDR4 was introduced with a minimum transfer rate of <b>2133 MT/s</b>, influenced by DDR3's nearing limit at similar speeds, and is expected to reach up to <b>4266 MT/s</b>. Notable improvements in DDR4 include increased data transfer rates and enhanced efficiency. Early DDR4 samples, such as those from <a href="/wiki/Samsung" title="Samsung">Samsung</a> in January 2011, showed a CAS latency of <b>13 <a href="/wiki/Clock_signal" title="Clock signal">clock cycles</a></b>, comparable to the DDR2 to DDR3 transition. Additionally, DDR4 features a longer burst length of 16, higher capacity support, and improved <a href="/wiki/Signal_integrity" title="Signal integrity">signal integrity</a> with tighter pin spacing (0.85 mm vs. 1.0 mm), slightly increased height (31.25 mm vs. 30.35 mm), and increased thickness (1.2 mm vs. 1.0 mm) for better signal routing and performance. </p><p>Internal banks are increased to 16 (4 bank select bits), with up to 8 ranks per DIMM.<sup id="cite_ref-SamsungIDF_9-1" class="reference"><a href="#cite_note-SamsungIDF-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 16">: 16 </span></sup> </p><p>Protocol changes include:<sup id="cite_ref-SamsungIDF_9-2" class="reference"><a href="#cite_note-SamsungIDF-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 20">: 20 </span></sup> </p> <ul><li>Parity on the command/address bus</li> <li>Data bus inversion (like <a href="/wiki/GDDR4" class="mw-redirect" title="GDDR4">GDDR4</a>)</li> <li><a href="/wiki/Cyclic_redundancy_check" title="Cyclic redundancy check">CRC</a> on the data bus</li> <li>Independent programming of individual DRAMs on a DIMM, to allow better control of <a href="/wiki/On-die_termination" title="On-die termination">on-die termination</a>.</li></ul> <p>Increased memory density is anticipated, possibly using TSV ("<a href="/wiki/Through-silicon_via" title="Through-silicon via">through-silicon via</a>") or other <a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D stacking processes</a>.<sup id="cite_ref-PC_Watch_32-2" class="reference"><a href="#cite_note-PC_Watch-32"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-xbit_38-1" class="reference"><a href="#cite_note-xbit-38"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-bit-tech_45-0" class="reference"><a href="#cite_note-bit-tech-45"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-jedec_1_46-0" class="reference"><a href="#cite_note-jedec_1-46"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> The DDR4 specification will include standardized <a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D stacking</a> "from the start" according to JEDEC,<sup id="cite_ref-jedec_1_46-1" class="reference"><a href="#cite_note-jedec_1-46"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> with provision for up to <span class="nowrap">8 stacked</span> dies.<sup id="cite_ref-SamsungIDF_9-3" class="reference"><a href="#cite_note-SamsungIDF-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 12">: 12 </span></sup> X-bit Labs predicted that "as a result DDR4 memory chips with very high density will become relatively inexpensive".<sup id="cite_ref-xbit_38-2" class="reference"><a href="#cite_note-xbit-38"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> </p><p>Switched memory banks are also an anticipated option for servers.<sup id="cite_ref-PC_Watch_32-3" class="reference"><a href="#cite_note-PC_Watch-32"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-bit-tech_45-1" class="reference"><a href="#cite_note-bit-tech-45"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </p><p>In 2008, the book <i>Wafer Level 3-D ICs Process Technology</i> highlighted concerns about the increasing die area consumption due to non-scaling analog elements like <a href="/wiki/Charge_pump" title="Charge pump">charge pumps</a>, <a href="/wiki/Voltage_regulator" title="Voltage regulator">voltage regulators</a>, and additional circuitry. These components, including <a href="/wiki/Cyclic_redundancy_check" title="Cyclic redundancy check">CRC</a> error-detection, <a href="/wiki/On-die_termination" title="On-die termination">on-die termination</a>, burst hardware, programmable pipelines, low impedance, and a greater need for <a href="/wiki/Sense_amplifier" title="Sense amplifier">sense amplifiers</a> (driven by reduced bits per bitline due to lower voltage), have significantly increased bandwidth but at the cost of occupying more die area. Consequently, the proportion of die allocated to the memory array itself has decreased over time: from <b>70–78%</b> for SDRAM and DDR1 to <b>47%</b> for DDR2, <b>38%</b> for DDR3, and potentially less than <b>30%</b> for DDR4.<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> </p><p>The specification defined standards for ×4, ×8 and ×16 memory devices with capacities of 2, 4, 8 and 16 Gbit.<sup id="cite_ref-binpre_1-6" class="reference"><a href="#cite_note-binpre-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </p><p>In addition to bandwidth and capacity variants, DDR4 modules can optionally implement: </p> <ul><li><b>ECC</b>, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC4-19200 ECC or PC4-19200E is a PC4-19200 module with ECC.<sup id="cite_ref-:0_49-0" class="reference"><a href="#cite_note-:0-49"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup></li> <li><b>Registered (or buffered) RAM</b> enhances signal integrity, which can improve clock rates and allow for higher physical slot capacity, by buffering signals electrically. This comes at the cost of an additional clock cycle of latency. These modules are identified by an "R" in their designation, such as <b>PC4-19200R</b>. Typically, modules with this designation are also ECC (<a href="/wiki/Error_correction_code" title="Error correction code">Error-Correcting Code</a>) Registered, though the 'E' for ECC may not always be included in the designation. Conversely, non-registered RAM, also known as unbuffered RAM, is identified by a "U" in the designation. e.g. PC4-19200U.<sup id="cite_ref-:0_49-1" class="reference"><a href="#cite_note-:0-49"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup></li> <li><b>Be Load reduced modules</b>, which are designated by LR and are similar to registered/buffered memory, in a way that <a href="/wiki/LRDIMM" class="mw-redirect" title="LRDIMM">LRDIMM</a> modules buffer both control and data lines while retaining the parallel nature of all signals. As such, LRDIMM memory provides larger overall maximum memory capacities, while addressing some of the performance and power consumption issues of FB memory induced by the required conversion between serial and parallel signal forms.<sup id="cite_ref-:0_49-2" class="reference"><a href="#cite_note-:0-49"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading3"><h3 id="Command_encoding">Command encoding</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=5" title="Edit section: Command encoding"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable plainrowheaders" style="text-align: center; font-size: 95%;"> <caption>DDR4 command encoding<sup id="cite_ref-ddr4_50-0" class="reference"><a href="#cite_note-ddr4-50"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> </caption> <tbody><tr> <th>Command </th> <th><span style="text-decoration:overline;">CS</span><br /> </th> <th>BG1–0,<br />BA1–0</th> <th><span style="text-decoration:overline;">ACT</span><br /> </th> <th>A17<br /> </th> <th>A16<br /><span style="text-decoration:overline;">RAS</span></th> <th>A15<br /><span style="text-decoration:overline;">CAS</span></th> <th>A14<br /><span style="text-decoration:overline;">WE</span></th> <th>A13<br /> </th> <th>A12<br />BC</th> <th>A11<br /> </th> <th>A10<br />AP</th> <th>A9–0<br />  </th></tr> <tr> <td style="text-align:left;">Deselect (no operation) </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="11" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">X </td></tr> <tr> <td style="text-align:left;">Active (activate): open a row </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td>Bank</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="9">Row address </td></tr> <tr> <td style="text-align:left;">No operation </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">ZQ calibration </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td>Long</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Read (BC, burst chop) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td>Bank</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td>BC</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td>AP</td> <td>Column </td></tr> <tr> <td style="text-align:left;">Write (AP, auto-precharge) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td>Bank</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td>BC</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td>AP</td> <td>Column </td></tr> <tr> <td style="text-align:left; background: #ececec; color: #2C2C2C;">Unassigned, reserved </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">v</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Precharge all banks </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Precharge one bank </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td>Bank</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Refresh </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Mode register set (MR0–MR6) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td>Register</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">L</td> <td colspan="4">Data </td></tr> <tr> <td colspan="14" style="background-color:#FFF;"><small><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output .hlist dt::after{content:": "}.mw-parser-output .hlist dd::after,.mw-parser-output .hlist li::after{content:" · ";font-weight:bold}.mw-parser-output .hlist dd:last-child::after,.mw-parser-output .hlist dt:last-child::after,.mw-parser-output .hlist li:last-child::after{content:none}.mw-parser-output .hlist dd dd:first-child::before,.mw-parser-output .hlist dd dt:first-child::before,.mw-parser-output .hlist dd li:first-child::before,.mw-parser-output .hlist dt dd:first-child::before,.mw-parser-output .hlist dt dt:first-child::before,.mw-parser-output .hlist dt li:first-child::before,.mw-parser-output .hlist li dd:first-child::before,.mw-parser-output .hlist li dt:first-child::before,.mw-parser-output .hlist li li:first-child::before{content:" (";font-weight:normal}.mw-parser-output .hlist dd dd:last-child::after,.mw-parser-output .hlist dd dt:last-child::after,.mw-parser-output .hlist dd li:last-child::after,.mw-parser-output .hlist dt dd:last-child::after,.mw-parser-output .hlist dt dt:last-child::after,.mw-parser-output .hlist dt li:last-child::after,.mw-parser-output .hlist li dd:last-child::after,.mw-parser-output .hlist li dt:last-child::after,.mw-parser-output .hlist li li:last-child::after{content:")";font-weight:normal}.mw-parser-output .hlist ol{counter-reset:listitem}.mw-parser-output .hlist ol>li{counter-increment:listitem}.mw-parser-output .hlist ol>li::before{content:" "counter(listitem)"\a0 "}.mw-parser-output .hlist dd ol>li:first-child::before,.mw-parser-output .hlist dt ol>li:first-child::before,.mw-parser-output .hlist li ol>li:first-child::before{content:" ("counter(listitem)"\a0 "}</style><div class="hlist"> <ul><li>Signal level <ul><li>H, high</li> <li>L, low</li> <li>V, either low or high, a valid signal</li> <li>X, irrelevant</li></ul></li> <li>Logic level <ul><li><style data-mw-deduplicate="TemplateStyles:r981673959">.mw-parser-output .legend{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .legend-color{display:inline-block;min-width:1.25em;height:1.25em;line-height:1.25;margin:1px 0;text-align:center;border:1px solid black;background-color:transparent;color:black}.mw-parser-output .legend-text{}</style><span class="legend-color mw-no-invert" style="background-color:#9f9; color:black;"> </span> Active</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r981673959" /><span class="legend-color mw-no-invert" style="background-color:#f99; color:black;"> </span> Inactive</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r981673959" /><span class="legend-color mw-no-invert" style="background-color:#ececec; color:black;"> </span> Not interpreted</li></ul></li></ul> </div></small> </td></tr></tbody></table> <p>Although it still operates in fundamentally the same way, DDR4 makes one major change to the <a href="/wiki/SDRAM#Commands" class="mw-redirect" title="SDRAM">command formats used by previous SDRAM generations</a>. A new command signal, <span style="text-decoration:overline;">ACT</span>, is low to indicate the activate (open row) command. </p><p>The activate command requires more address bits than any other (18 row address bits in a 16 Gbit part), so the standard <span style="text-decoration:overline;">RAS</span>, <span style="text-decoration:overline;">CAS</span>, and <span style="text-decoration:overline;">WE</span> <a href="/wiki/Active_low" class="mw-redirect" title="Active low">active low</a> signals are shared with high-order address bits that are not used when <span style="text-decoration:overline;">ACT</span> is high. The combination of <span style="text-decoration:overline;">RAS</span>=L and <span style="text-decoration:overline;">CAS</span>=<span style="text-decoration:overline;">WE</span>=H that previously encoded an activate command is unused. </p><p>As in previous SDRAM encodings, A10 is used to select command variants: auto-precharge on read and write commands, and one bank vs. all banks for the precharge command. It also selects two variants of the ZQ calibration command. </p><p>As in DDR3, A12 is used to request <i>burst chop</i>: truncation of an 8-transfer burst after four transfers. Although the bank is still busy and unavailable for other commands until eight transfer times have elapsed, a different bank can be accessed. </p><p>Also, the number of bank addresses has been increased greatly. There are four bank select bits to select up to 16 banks within each DRAM: two bank address bits (BA0, BA1), and two bank group bits (BG0, BG1). There are additional timing restrictions when accessing banks within the same bank group; it is faster to access a bank in a different bank group. </p><p>In addition, there are three chip select signals (C0, C1, C2), allowing up to eight <a href="/wiki/Multi-Chip_Module#Chip_stack_MCMs" class="mw-redirect" title="Multi-Chip Module">stacked chips</a> to be placed inside a single DRAM package. These effectively act as three more bank select bits, bringing the total to seven (128 possible banks). </p><p>Standard transfer rates are 1600, 1866, 2133, 2400, 2666, 2933, and 3200 MT/s<sup id="cite_ref-ddr4_50-1" class="reference"><a href="#cite_note-ddr4-50"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ddr4b_51-0" class="reference"><a href="#cite_note-ddr4b-51"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> (<style data-mw-deduplicate="TemplateStyles:r1154941027">.mw-parser-output .frac{white-space:nowrap}.mw-parser-output .frac .num,.mw-parser-output .frac .den{font-size:80%;line-height:0;vertical-align:super}.mw-parser-output .frac .den{vertical-align:sub}.mw-parser-output .sr-only{border:0;clip:rect(0,0,0,0);clip-path:polygon(0px 0px,0px 0px,0px 0px);height:1px;margin:-1px;overflow:hidden;padding:0;position:absolute;width:1px}</style><span class="frac"><span class="num">12</span>⁄<span class="den">15</span></span>, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1154941027" /><span class="frac"><span class="num">14</span>⁄<span class="den">15</span></span>, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1154941027" /><span class="frac"><span class="num">16</span>⁄<span class="den">15</span></span>, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1154941027" /><span class="frac"><span class="num">18</span>⁄<span class="den">15</span></span>, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1154941027" /><span class="frac"><span class="num">20</span>⁄<span class="den">15</span></span>, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1154941027" /><span class="frac"><span class="num">22</span>⁄<span class="den">15</span></span>, and <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1154941027" /><span class="frac"><span class="num">24</span>⁄<span class="den">15</span></span> GHz clock frequencies, double data rate), with speeds up to DDR4-4800 (2400 MHz clock) commercially available.<sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Design_considerations">Design considerations</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=6" title="Edit section: Design considerations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The DDR4 team at <a href="/wiki/Micron_Technology" title="Micron Technology">Micron Technology</a> identified some key points for IC and PCB design:<sup id="cite_ref-Denali_53-0" class="reference"><a href="#cite_note-Denali-53"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup> </p><p>IC design:<sup id="cite_ref-Denali_53-1" class="reference"><a href="#cite_note-Denali-53"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup> </p> <ul><li>VrefDQ calibration (DDR4 "requires that VrefDQ calibration be performed by the controller");</li> <li>New addressing schemes ("bank grouping", <span style="text-decoration:overline;">ACT</span> to replace <span style="text-decoration:overline;">RAS</span>, <span style="text-decoration:overline;">CAS</span>, and <span style="text-decoration:overline;">WE</span> commands, PAR and <span style="text-decoration:overline;">Alert</span> for error checking and <span style="text-decoration:overline;">DBI</span> for data bus inversion);</li> <li>New power saving features (low-power auto self-refresh, temperature-controlled refresh, fine-granularity refresh, data-bus inversion, and CMD/ADDR latency).</li></ul> <p>Circuit board design:<sup id="cite_ref-Denali_53-2" class="reference"><a href="#cite_note-Denali-53"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup> </p> <ul><li>New power supplies (VDD/VDDQ at 1.2 V and wordline boost, known as VPP, at 2.5 V);</li> <li>VrefDQ must be supplied internal to the DRAM while VrefCA is supplied externally from the board;</li> <li>DQ pins terminate high using pseudo-open-drain I/O (this differs from the CA pins in DDR3 which are center-tapped to VTT).<sup id="cite_ref-Denali_53-3" class="reference"><a href="#cite_note-Denali-53"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup></li></ul> <p><a href="/wiki/Rowhammer" class="mw-redirect" title="Rowhammer">Rowhammer</a> mitigation techniques include larger storage capacitors, modifying the address lines to use <a href="/wiki/Address_space_layout_randomization" title="Address space layout randomization">address space layout randomization</a> and dual-voltage I/O lines that further isolate potential boundary conditions that might result in instability at high write/read speeds. </p> <div class="mw-heading mw-heading2"><h2 id="Modules">Modules</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=7" title="Edit section: Modules"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Module_packaging">Module packaging</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=8" title="Edit section: Module packaging"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:DDR_4_RAM_SO-DIMM_16GB_by_Micron-top_back_PNr%C2%B00841.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a2/DDR_4_RAM_SO-DIMM_16GB_by_Micron-top_back_PNr%C2%B00841.jpg/250px-DDR_4_RAM_SO-DIMM_16GB_by_Micron-top_back_PNr%C2%B00841.jpg" decoding="async" width="220" height="109" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a2/DDR_4_RAM_SO-DIMM_16GB_by_Micron-top_back_PNr%C2%B00841.jpg/330px-DDR_4_RAM_SO-DIMM_16GB_by_Micron-top_back_PNr%C2%B00841.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a2/DDR_4_RAM_SO-DIMM_16GB_by_Micron-top_back_PNr%C2%B00841.jpg/500px-DDR_4_RAM_SO-DIMM_16GB_by_Micron-top_back_PNr%C2%B00841.jpg 2x" data-file-width="3574" data-file-height="1773" /></a><figcaption>A 16GB<sup id="cite_ref-binpre_1-7" class="reference"><a href="#cite_note-binpre-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> DDR4 SO-DIMM module by <a href="/wiki/Micron_Technology" title="Micron Technology">Micron</a></figcaption></figure> <p>DDR4 memory is supplied in 288-pin <a href="/wiki/Dual_in-line_memory_module" class="mw-redirect" title="Dual in-line memory module">dual in-line memory modules</a> (DIMMs), similar in size to 240-pin DDR3 DIMMs. <b>DDR4 RAM</b> modules feature pins that are spaced more closely at <b>0.85 mm</b> compared to the <b>1.0 mm</b> spacing in DDR3, allowing for a higher pin density within the same standard <a href="/wiki/DIMM" title="DIMM">DIMM</a> length of <b>133.35 mm</b> (5¼ inches). The height of DDR4 modules is slightly increased to <b>31.25 mm</b> (1.23 inches) from <b>30.35 mm</b> (1.2 inches) to facilitate easier signal routing. Additionally, the thickness of DDR4 modules has been increased to <b>1.2 mm</b> from <b>1.0 mm</b> to support more signal layers, enhancing overall performance and reliability.<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup> DDR4 DIMM modules have a slightly curved <a href="/wiki/Edge_connector" title="Edge connector">edge connector</a> so not all of the pins are engaged at the same time during module insertion, lowering the insertion force.<sup id="cite_ref-molex-ddr4_13-1" class="reference"><a href="#cite_note-molex-ddr4-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p><p>DDR4 <a href="/wiki/SO-DIMM" class="mw-redirect" title="SO-DIMM">SO-DIMMs</a> have 260 pins instead of the 204 pins of DDR3 SO-DIMMs, spaced at 0.5 rather than 0.6 mm, and are 2.0 mm wider (69.6 versus 67.6 mm), but remain the same 30 mm in height.<sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup> </p><p>For its <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake microarchitecture</a>, Intel designed a SO-DIMM package named <a href="/wiki/UniDIMM" title="UniDIMM">UniDIMM</a>, which can be populated with either DDR3 or DDR4 chips. At the same time, the <a href="/wiki/Integrated_memory_controller" class="mw-redirect" title="Integrated memory controller">integrated memory controller</a> (IMC) of Skylake CPUs is announced to be capable of working with either type of memory. The purpose of UniDIMMs is to help in the market transition from DDR3 to DDR4, where pricing and availability may make it undesirable to switch the RAM type. UniDIMMs have the same dimensions and number of pins as regular DDR4 SO-DIMMs, but the edge connector's notch is placed differently to avoid accidental use in incompatible DDR4 SO-DIMM sockets.<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="JEDEC_standard_DDR4_module">JEDEC standard DDR4 module</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=9" title="Edit section: JEDEC standard DDR4 module"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable floatright" style="text-align:center; font-size:90%;"> <tbody><tr> <th scope="col">Standard <br />name </th> <th scope="col">Memory<br />clock<br /><small>(MHz)</small> </th> <th scope="col">I/O bus<br />clock<br /><small>(MHz)</small> </th> <th scope="col">Data<br />rate<br /><small>(<a href="/wiki/Transfer_(computing)" class="mw-redirect" title="Transfer (computing)">MT/s</a>)<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup></small> </th> <th scope="col">Module<br />name </th> <th scope="col">Peak trans-<br />fer rate<br /><small>(GB/s)<sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">[</span>c<span class="cite-bracket">]</span></a></sup></small> </th> <th scope="col">Timings<br /><small>CL-tRCD-tRP</small> </th> <th scope="col">CAS<br />latency<br /><small>(ns)</small> </th></tr> <tr> <td>DDR4-1600J*<br />DDR4-1600K <br />DDR4-1600L</td> <td>200</td> <td>800</td> <td>1600</td> <td>PC4-12800</td> <td>12.8</td> <td>10-10-10<br />11-11-11<br />12-12-12</td> <td>12.5<br />13.75 <br />15 </td></tr> <tr> <td>DDR4-1866L*<br />DDR4-1866M<br />DDR4-1866N</td> <td>233.33</td> <td>933.33</td> <td>1866.67</td> <td>PC4-14900</td> <td>14.9333</td> <td>12-12-12<br />13-13-13<br />14-14-14</td> <td>12.857<br />13.929<br />15 </td></tr> <tr> <td>DDR4-2133N*<br />DDR4-2133P<br />DDR4-2133R</td> <td>266.67</td> <td>1066.67</td> <td>2133.33</td> <td>PC4-17000</td> <td>17.06667</td> <td>14-14-14<br />15-15-15<br />16-16-16</td> <td>13.125<br />14.063<br />15 </td></tr> <tr> <td>DDR4-2400P*<br />DDR4-2400R<br />DDR4-2400T<br />DDR4-2400U</td> <td>300</td> <td>1200</td> <td>2400</td> <td>PC4-19200</td> <td>19.2</td> <td>15-15-15<br />16-16-16<br />17-17-17<br />18-18-18</td> <td>12.5 <br />13.32 <br />14.16 <br />15 </td></tr> <tr> <td>DDR4-2666T<br />DDR4-2666U<br />DDR4-2666V<br />DDR4-2666W</td> <td>333.33</td> <td>1333.33</td> <td>2666.67</td> <td>PC4-21300</td> <td>21.3333</td> <td>17-17-17<br />18-18-18<br />19-19-19<br />20-20-20</td> <td>12.75 <br />13.50 <br />14.25 <br />15 </td></tr> <tr> <td>DDR4-2933V<br />DDR4-2933W<br />DDR4-2933Y<br />DDR4-2933AA</td> <td>366.67</td> <td>1466.67</td> <td>2933.33</td> <td>PC4-23466</td> <td>23.46667</td> <td>19-19-19<br />20-20-20<br />21-21-21<br />22-22-22</td> <td>12.96 <br />13.64 <br />14.32 <br />15 </td></tr> <tr> <td>DDR4-3200W<br />DDR4-3200AA<br />DDR4-3200AC</td> <td>400</td> <td>1600</td> <td>3200</td> <td>PC4-25600</td> <td>25.6</td> <td>20-20-20<br />22-22-22<br />24-24-24</td> <td>12.5 <br />13.75 <br />15 </td></tr></tbody></table> <dl><dt><a href="/wiki/CAS_latency" title="CAS latency">CAS latency</a> (CL)</dt> <dd><a href="/wiki/Clock_signal" title="Clock signal">Clock cycles</a> between sending a column address to the memory and the beginning of the data in response</dd> <dt>tRCD</dt> <dd>Clock cycles between row activate and reads/writes</dd> <dt>tRP</dt> <dd>Clock cycles between row precharge and activate</dd></dl> <p>DDR4-xxxx denotes per-bit data transfer rate, and is normally used to describe DDR chips. PC4-xxxxx denotes overall transfer rate, in megabytes per second, and applies only to modules (assembled DIMMs). Because DDR4 memory modules transfer data on a bus that is 8 bytes (64 data bits) wide, module peak transfer rate is calculated by taking transfers per second and multiplying by eight.<sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Successor"><span class="anchor" id="DDR5"></span>Successor</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=10" title="Edit section: Successor"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>At the 2016 <a href="/wiki/Intel_Developer_Forum" title="Intel Developer Forum">Intel Developer Forum</a>, the future of <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5 SDRAM</a> was discussed. The specifications were finalized at the end of 2016 –  but no modules will be available before 2020.<sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup> Other memory technologies –  namely <a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a> in version 3 and 4<sup id="cite_ref-61" class="reference"><a href="#cite_note-61"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup> –  aiming to replace DDR4 have also been proposed. </p><p>In 2011, JEDEC introduced the <b><a rel="nofollow" class="external text" href="https://www.jedec.org/standards-documents/docs/jesd229-2">Wide I/O 2</a></b> standard, which features stacked memory dies placed directly on top of the CPU within the same package. This configuration provides higher bandwidth and improved power efficiency compared to DDR4 SDRAM, thanks to its wide interface and short signal lengths. Wide I/O 2 aims to replace various mobile <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDRX SDRAM</a> standards used in high-performance embedded and mobile devices like smartphones. </p><p>In parallel, Hynix developed <b><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a> (HBM)</b>, standardized as JEDEC JESD235. Both Wide I/O 2 and HBM utilize a very wide parallel memory interface—up to 512 bits for Wide I/O 2 compared to 64 bits for DDR4—although they operate at lower frequencies than DDR4. Wide I/O 2 is designed for high-performance, compact devices, often integrated into processors or system on a chip (SoC) packages. In contrast, HBM targets graphics memory and general computing, while <b><a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a> (HMC)</b> is aimed at high-end servers and enterprise applications.<sup id="cite_ref-extreme_62-0" class="reference"><a href="#cite_note-extreme-62"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Micron_Technology" title="Micron Technology">Micron Technology</a>'s <a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a> (HMC) stacked memory uses a serial interface. Many other computer buses have migrated towards replacing parallel buses with serial buses, for example by the evolution of <a href="/wiki/Serial_ATA" class="mw-redirect" title="Serial ATA">Serial ATA</a> replacing <a href="/wiki/Parallel_ATA" title="Parallel ATA">Parallel ATA</a>, <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> replacing <a href="/wiki/Conventional_PCI" class="mw-redirect" title="Conventional PCI">PCI</a>, and serial ports replacing parallel ports. In general, serial buses are easier to scale up and have fewer wires/traces, making circuit boards using them easier to design.<sup id="cite_ref-63" class="reference"><a href="#cite_note-63"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-64" class="reference"><a href="#cite_note-64"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-65" class="reference"><a href="#cite_note-65"><span class="cite-bracket">[</span>62<span class="cite-bracket">]</span></a></sup> </p><p>In the longer term, experts speculate that non-volatile RAM types like PCM (<a href="/wiki/Phase-change_memory" title="Phase-change memory">phase-change memory</a>), RRAM (<a href="/wiki/Resistive_random-access_memory" title="Resistive random-access memory">resistive random-access memory</a>), or MRAM (<a href="/wiki/Magnetoresistive_random-access_memory" class="mw-redirect" title="Magnetoresistive random-access memory">magnetoresistive random-access memory</a>) could replace DDR4 SDRAM and its successors.<sup id="cite_ref-66" class="reference"><a href="#cite_note-66"><span class="cite-bracket">[</span>63<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/GDDR5" class="mw-redirect" title="GDDR5">GDDR5</a> SGRAM is a graphics type of <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a> <a href="/wiki/Synchronous_graphics_RAM" class="mw-redirect" title="Synchronous graphics RAM">synchronous graphics RAM</a>, which was introduced before DDR4, and is not a successor to DDR4. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=11" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1266661725">.mw-parser-output .portalbox{padding:0;margin:0.5em 0;display:table;box-sizing:border-box;max-width:175px;list-style:none}.mw-parser-output .portalborder{border:1px solid var(--border-color-base,#a2a9b1);padding:0.1em;background:var(--background-color-neutral-subtle,#f8f9fa)}.mw-parser-output .portalbox-entry{display:table-row;font-size:85%;line-height:110%;height:1.9em;font-style:italic;font-weight:bold}.mw-parser-output .portalbox-image{display:table-cell;padding:0.2em;vertical-align:middle;text-align:center}.mw-parser-output .portalbox-link{display:table-cell;padding:0.2em 0.2em 0.2em 0.3em;vertical-align:middle}@media(min-width:720px){.mw-parser-output .portalleft{margin:0.5em 1em 0.5em 0}.mw-parser-output .portalright{clear:right;float:right;margin:0.5em 0 0.5em 1em}}</style><ul role="navigation" aria-label="Portals" class="noprint portalbox portalborder portalright"> <li class="portalbox-entry"><span class="portalbox-image"><span class="noviewer" typeof="mw:File"><a href="/wiki/File:Noun-technology.svg" class="mw-file-description"><img alt="icon" src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Noun-technology.svg/29px-Noun-technology.svg.png" decoding="async" width="29" height="28" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Noun-technology.svg/43px-Noun-technology.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Noun-technology.svg/57px-Noun-technology.svg.png 2x" data-file-width="90" data-file-height="88" /></a></span></span><span class="portalbox-link"><a href="/wiki/Portal:Technology" title="Portal:Technology">Technology portal</a></span></li></ul> <ul><li><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous dynamic random-access memory</a> –  main article for DDR memory types</li> <li><a href="/wiki/List_of_interface_bit_rates" title="List of interface bit rates">List of interface bit rates</a></li> <li><a href="/wiki/Memory_timings" title="Memory timings">Memory timings</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=12" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-14">^</a></b></span> <span class="reference-text">As a prototype, this DDR4 memory module has a flat <a href="/wiki/Edge_connector" title="Edge connector">edge connector</a> at the bottom, while production DDR4 DIMM modules have a slightly curved edge connector so not all of the pins are engaged at a time during module insertion, lowering the insertion force.<sup id="cite_ref-molex-ddr4_13-0" class="reference"><a href="#cite_note-molex-ddr4-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup></span> </li> <li id="cite_note-57"><span class="mw-cite-backlink"><b><a href="#cite_ref-57">^</a></b></span> <span class="reference-text">1 MT = one million transfers</span> </li> <li id="cite_note-58"><span class="mw-cite-backlink"><b><a href="#cite_ref-58">^</a></b></span> <span class="reference-text">1 GB = one billion bytes</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=13" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626" /><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-binpre-1"><span class="mw-cite-backlink">^ <a href="#cite_ref-binpre_1-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-binpre_1-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-binpre_1-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-binpre_1-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-binpre_1-4"><sup><i><b>e</b></i></sup></a> <a href="#cite_ref-binpre_1-5"><sup><i><b>f</b></i></sup></a> <a href="#cite_ref-binpre_1-6"><sup><i><b>g</b></i></sup></a> <a href="#cite_ref-binpre_1-7"><sup><i><b>h</b></i></sup></a></span> <span class="reference-text">Here, <i>K</i>, <i>M</i>, <i>G</i>, or <i>T</i> refer to the <a href="/wiki/Binary_prefix" title="Binary prefix">binary prefixes</a> based on powers of 1024.</span> </li> <li id="cite_note-hynix_April_2011-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-hynix_April_2011_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-hynix_April_2011_2-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-hynix_April_2011_2-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-hynix_April_2011_2-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-hynix_April_2011_2-4"><sup><i><b>e</b></i></sup></a> <a href="#cite_ref-hynix_April_2011_2-5"><sup><i><b>f</b></i></sup></a></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFMarc2011" class="citation web cs1">Marc (2011-04-05). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120415182459/http://www.behardware.com/news/11425/hynix-produces-its-first-ddr4-modules.html">"Hynix produces its first DDR4 modules"</a>. <i>Be hardware</i>. Archived from <a rel="nofollow" class="external text" href="http://www.behardware.com/news/11425/hynix-produces-its-first-ddr4-modules.html">the original</a> on 2012-04-15<span class="reference-accessdate">. Retrieved <span class="nowrap">2012-04-14</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Be+hardware&rft.atitle=Hynix+produces+its+first+DDR4+modules&rft.date=2011-04-05&rft.au=Marc&rft_id=http%3A%2F%2Fwww.behardware.com%2Fnews%2F11425%2Fhynix-produces-its-first-ddr4-modules.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-micron_May_2012-3"><span class="mw-cite-backlink">^ <a href="#cite_ref-micron_May_2012_3-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-micron_May_2012_3-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://www.engadget.com/2012/05/08/micron-teases-working-ddr4-ram-module"><i>Micron teases working DDR4 RAM</i></a>, Engadget, 2012-05-08<span class="reference-accessdate">, retrieved <span class="nowrap">2012-05-08</span></span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Micron+teases+working+DDR4+RAM&rft.pub=Engadget&rft.date=2012-05-08&rft_id=https%3A%2F%2Fwww.engadget.com%2F2012%2F05%2F08%2Fmicron-teases-working-ddr4-ram-module&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://arstechnica.com/gadgets/2013/08/samsung-mass-produces-ddr4-which-still-has-nowhere-to-go/">"Samsung mass-produces DDR4"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">2013-08-31</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Samsung+mass-produces+DDR4&rft_id=https%3A%2F%2Farstechnica.com%2Fgadgets%2F2013%2F08%2Fsamsung-mass-produces-ddr4-which-still-has-nowhere-to-go%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-dram_story-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-dram_story_5-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110604145404/http://www.ieee.org/portal/cms_docs_societies/sscs/PrintEditions/200801.pdf"><i>The DRAM Story</i></a> <span class="cs1-format">(PDF)</span>, IEEE, 2008, p. 10, archived from <a rel="nofollow" class="external text" href="http://www.ieee.org/portal/cms_docs_societies/sscs/PrintEditions/200801.pdf">the original</a> <span class="cs1-format">(PDF)</span> on June 4, 2011<span class="reference-accessdate">, retrieved <span class="nowrap">2012-01-23</span></span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=The+DRAM+Story&rft.pages=10&rft.pub=IEEE&rft.date=2008&rft_id=http%3A%2F%2Fwww.ieee.org%2Fportal%2Fcms_docs_societies%2Fsscs%2FPrintEditions%2F200801.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://globenewswire.com/news-release/2014/06/02/641205/10083787/en/Crucial-DDR4-Server-Memory-Now-Available.html">"Crucial DDR4 Server Memory Now Available"</a>. <i>Globe newswire</i>. 2 June 2014<span class="reference-accessdate">. Retrieved <span class="nowrap">12 December</span> 2014</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Globe+newswire&rft.atitle=Crucial+DDR4+Server+Memory+Now+Available&rft.date=2014-06-02&rft_id=http%3A%2F%2Fglobenewswire.com%2Fnews-release%2F2014%2F06%2F02%2F641205%2F10083787%2Fen%2FCrucial-DDR4-Server-Memory-Now-Available.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFbtarunr2014" class="citation web cs1">btarunr (14 September 2014). <a rel="nofollow" class="external text" href="https://www.techpowerup.com/205231/how-intel-plans-to-transition-between-ddr3-and-ddr4-for-the-mainstream.html">"How Intel Plans to Transition Between DDR3 and DDR4 for the Mainstream"</a>. <i>TechPowerUp</i><span class="reference-accessdate">. Retrieved <span class="nowrap">28 April</span> 2015</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TechPowerUp&rft.atitle=How+Intel+Plans+to+Transition+Between+DDR3+and+DDR4+for+the+Mainstream&rft.date=2014-09-14&rft.au=btarunr&rft_id=https%3A%2F%2Fwww.techpowerup.com%2F205231%2Fhow-intel-plans-to-transition-between-ddr3-and-ddr4-for-the-mainstream.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFWang2013" class="citation web cs1">Wang, David (12 March 2013). <a rel="nofollow" class="external text" href="https://www.eetimes.com/document.asp?doc_id=1280577">"Why migrate to DDR4?"</a>. Inphi Corp. – via EE Times.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Why+migrate+to+DDR4%3F&rft.pub=Inphi+Corp.&rft.date=2013-03-12&rft.aulast=Wang&rft.aufirst=David&rft_id=https%3A%2F%2Fwww.eetimes.com%2Fdocument.asp%3Fdoc_id%3D1280577&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-SamsungIDF-9"><span class="mw-cite-backlink">^ <a href="#cite_ref-SamsungIDF_9-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-SamsungIDF_9-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-SamsungIDF_9-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-SamsungIDF_9-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFJung2012" class="citation cs2">Jung, JY (2012-09-11), "How DRAM Advancements are Impacting Server Infrastructure", <a rel="nofollow" class="external text" href="https://web.archive.org/web/20121127074139/https://intel.activeevents.com/sf12/scheduler/catalog.do"><i>Intel Developer Forum 2012</i></a>, Intel, Samsung; Active events, archived from <a rel="nofollow" class="external text" href="https://intel.activeevents.com/sf12/scheduler/catalog.do">the original</a> on 2012-11-27<span class="reference-accessdate">, retrieved <span class="nowrap">2012-09-15</span></span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=How+DRAM+Advancements+are+Impacting+Server+Infrastructure&rft.btitle=Intel+Developer+Forum+2012&rft.pub=Intel%2C+Samsung%3B+Active+events&rft.date=2012-09-11&rft.aulast=Jung&rft.aufirst=JY&rft_id=https%3A%2F%2Fintel.activeevents.com%2Fsf12%2Fscheduler%2Fcatalog.do&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-JEDEC-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-JEDEC_10-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.jedec.org/category/technology-focus-area/main-memory-ddr3-ddr4-sdram">"Main Memory: DDR4 & DDR5 SDRAM"</a>. <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a><span class="reference-accessdate">. Retrieved <span class="nowrap">2012-04-14</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Main+Memory%3A+DDR4+%26+DDR5+SDRAM&rft.pub=JEDEC&rft_id=https%3A%2F%2Fwww.jedec.org%2Fcategory%2Ftechnology-focus-area%2Fmain-memory-ddr3-ddr4-sdram&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://www.micron.com/products/dram/ddr3-to-ddr4">"DDR4 –  Advantages of Migrating from DDR3"</a>, <i>Products</i><span class="reference-accessdate">, retrieved <span class="nowrap">2014-08-20</span></span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=DDR4+%26ndash%3B%26%2332%3B+Advantages+of+Migrating+from+DDR3&rft.btitle=Products&rft_id=https%3A%2F%2Fwww.micron.com%2Fproducts%2Fdram%2Fddr3-to-ddr4&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span>.</span> </li> <li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techradar.com/amp/news/corsair-unleashes-worlds-fastest-ram-and-16gb-costs-more-than-your-gaming-pc-probably">"Corsair unleashes world's fastest DDR4 RAM and 16GB costs more than your gaming PC (probably) | TechRadar"</a>. <i>www.techradar.com</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.techradar.com&rft.atitle=Corsair+unleashes+world%27s+fastest+DDR4+RAM+and+16GB+costs+more+than+your+gaming+PC+%28probably%29+%26%23124%3B+TechRadar&rft_id=https%3A%2F%2Fwww.techradar.com%2Famp%2Fnews%2Fcorsair-unleashes-worlds-fastest-ram-and-16gb-costs-more-than-your-gaming-pc-probably&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-molex-ddr4-13"><span class="mw-cite-backlink">^ <a href="#cite_ref-molex-ddr4_13-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-molex-ddr4_13-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.arroweurope.com/services/arrow-download-center.html?tx_sfdownloadcenter%5Bdownload%5D=86">"Molex DDR4 DIMM Sockets, Halogen-free"</a>. <i>Arrow Europe</i>. <a href="/wiki/Molex" title="Molex">Molex</a>. 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">2015-06-22</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Arrow+Europe&rft.atitle=Molex+DDR4+DIMM+Sockets%2C+Halogen-free&rft.date=2012&rft_id=http%3A%2F%2Fwww.arroweurope.com%2Fservices%2Farrow-download-center.html%3Ftx_sfdownloadcenter%255Bdownload%255D%3D86&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-digitimes_2005-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-digitimes_2005_15-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFSobolev2005" class="citation web cs1">Sobolev, Vyacheslav (2005-05-31). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20131203181702/http://de.viatech.com/de/company/events/vtf2005/interview_desi_rhoden.jsp">"JEDEC: Memory standards on the way"</a>. <i>Digitimes</i>. Via tech. Archived from <a rel="nofollow" class="external text" href="http://de.viatech.com/de/company/events/vtf2005/interview_desi_rhoden.jsp">the original</a> on 2013-12-03<span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-28</span></span>. <q>Initial investigations have already started on memory technology beyond DDR3. JEDEC always has about three generations of memory in various stages of the standardization process: current generation, next generation, and future.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Digitimes&rft.atitle=JEDEC%3A+Memory+standards+on+the+way&rft.date=2005-05-31&rft.aulast=Sobolev&rft.aufirst=Vyacheslav&rft_id=http%3A%2F%2Fde.viatech.com%2Fde%2Fcompany%2Fevents%2Fvtf2005%2Finterview_desi_rhoden.jsp&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-16">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110728020853/http://www.kingston.com/channelmarketingcenter/hyperx/literature/MKF_1223-1_DDR3_FAQ.pdf">"DDR3: Frequently asked questions"</a> <span class="cs1-format">(PDF)</span>. <a href="/wiki/Kingston_Technology" title="Kingston Technology">Kingston Technology</a>. Archived from <a rel="nofollow" class="external text" href="http://www.kingston.com/channelmarketingcenter/hyperx/literature/MKF_1223-1_DDR3_FAQ.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2011-07-28<span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-28</span></span>. <q>DDR3 memory launched in June 2007</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=DDR3%3A+Frequently+asked+questions&rft.pub=Kingston+Technology&rft_id=http%3A%2F%2Fwww.kingston.com%2Fchannelmarketingcenter%2Fhyperx%2Fliterature%2FMKF_1223-1_DDR3_FAQ.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-17">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFValich2007" class="citation news cs1 cs1-prop-unfit">Valich, Theo (2007-05-02). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100205014802/http://www.theinquirer.net/inquirer/news/1016272/ddr3-launch-set-may-9th">"DDR3 launch set for May 9th"</a>. <i><a href="/wiki/The_Inquirer" title="The Inquirer">The Inquirer</a></i>. Archived from the original on February 5, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-28</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=The+Inquirer&rft.atitle=DDR3+launch+set+for+May+9th&rft.date=2007-05-02&rft.aulast=Valich&rft.aufirst=Theo&rft_id=http%3A%2F%2Fwww.theinquirer.net%2Finquirer%2Fnews%2F1016272%2Fddr3-launch-set-may-9th&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-18"><span class="mw-cite-backlink"><b><a href="#cite_ref-18">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFHammerschmidt2007" class="citation web cs1">Hammerschmidt, Christoph (2007-08-29). <a rel="nofollow" class="external text" href="https://www.eetimes.com/document.asp?doc_id=1248476">"Non-volatile memory is the secret star at JEDEC meeting"</a>. <i>EE Times</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-28</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=EE+Times&rft.atitle=Non-volatile+memory+is+the+secret+star+at+JEDEC+meeting&rft.date=2007-08-29&rft.aulast=Hammerschmidt&rft.aufirst=Christoph&rft_id=https%3A%2F%2Fwww.eetimes.com%2Fdocument.asp%3Fdoc_id%3D1248476&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-The_H-19"><span class="mw-cite-backlink">^ <a href="#cite_ref-The_H_19-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-The_H_19-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110526181258/http://www.h-online.com/newsticker/news/item/IDF-DDR4-the-successor-to-DDR3-memory-736983.html">"DDR4 –  the successor to DDR3 memory"</a>. <i>The "H"</i> (online ed.). 2008-08-21. Archived from <a rel="nofollow" class="external text" href="http://www.h-online.com/newsticker/news/item/IDF-DDR4-the-successor-to-DDR3-memory-736983.html">the original</a> on 26 May 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-28</span></span>. <q>The JEDEC standardisation committee cited similar figures around one year ago</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+%22H%22&rft.atitle=DDR4+%26ndash%3B%26%2332%3B+the+successor+to+DDR3+memory&rft.date=2008-08-21&rft_id=http%3A%2F%2Fwww.h-online.com%2Fnewsticker%2Fnews%2Fitem%2FIDF-DDR4-the-successor-to-DDR3-memory-736983.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-pc_pro_2008-20"><span class="mw-cite-backlink">^ <a href="#cite_ref-pc_pro_2008_20-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-pc_pro_2008_20-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFGraham-Smith2008" class="citation web cs1">Graham-Smith, Darien (2008-08-19). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110607101302/http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009">"IDF: DDR3 won't catch up with DDR2 during 2009"</a>. <i><a href="/wiki/PC_Pro" title="PC Pro">PC Pro</a></i>. Archived from <a rel="nofollow" class="external text" href="http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009">the original</a> on 2011-06-07<span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-28</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=PC+Pro&rft.atitle=IDF%3A+DDR3+won%27t+catch+up+with+DDR2+during+2009&rft.date=2008-08-19&rft.aulast=Graham-Smith&rft.aufirst=Darien&rft_id=http%3A%2F%2Fwww.pcpro.co.uk%2Fnews%2F220257%2Fidf-ddr3-wont-catch-up-with-ddr2-during-2009&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-computerbase_2008-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-computerbase_2008_21-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFVolker2008" class="citation web cs1 cs1-prop-foreign-lang-source">Volker, Rißka (2008-08-21). <a rel="nofollow" class="external text" href="https://www.computerbase.de/2008-08/idf-ddr4-als-hauptspeicher-ab-2012/">"IDF: DDR4 als Hauptspeicher ab 2012"</a> [Intel Developer Forum: DDR4 as the main memory from 2012]. <i>Computerbase</i> (in German). <a href="/wiki/Germany" title="Germany">DE</a><span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-28</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Computerbase&rft.atitle=IDF%3A+DDR4+als+Hauptspeicher+ab+2012&rft.date=2008-08-21&rft.aulast=Volker&rft.aufirst=Ri%C3%9Fka&rft_id=https%3A%2F%2Fwww.computerbase.de%2F2008-08%2Fidf-ddr4-als-hauptspeicher-ab-2012%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span> (<a rel="nofollow" class="external text" href="https://translate.google.com/translate?hl=en&sl=de&tl=en&u=https%3A%2F%2Fwww.computerbase.de%2F2008-08%2Fidf-ddr4-als-hauptspeicher-ab-2012%2F">English</a>)</span> </li> <li id="cite_note-inquirer_2008-22"><span class="mw-cite-backlink">^ <a href="#cite_ref-inquirer_2008_22-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-inquirer_2008_22-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFNovakovic2008" class="citation web cs1 cs1-prop-unfit">Novakovic, Nebojsa (2008-08-19). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20101125023042/http://www.theinquirer.net/inquirer/news/1012591/qimonda-ddr3-moving-forward">"Qimonda: DDR3 moving forward"</a>. <i>The Inquirer</i>. Archived from the original on November 25, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-28</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Inquirer&rft.atitle=Qimonda%3A+DDR3+moving+forward&rft.date=2008-08-19&rft.aulast=Novakovic&rft.aufirst=Nebojsa&rft_id=http%3A%2F%2Fwww.theinquirer.net%2Finquirer%2Fnews%2F1012591%2Fqimonda-ddr3-moving-forward&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-23"><span class="mw-cite-backlink"><b><a href="#cite_ref-23">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFGruener2009" class="citation news cs1">Gruener, Wolfgang (February 4, 2009). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090524133306/http://www.tgdaily.com/content/view/41316/139/">"Samsung hints to DDR4 with first validated 40 nm DRAM"</a>. TG daily. Archived from <a rel="nofollow" class="external text" href="http://www.tgdaily.com/content/view/41316/139/">the original</a> on May 24, 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">2009-06-16</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Samsung+hints+to+DDR4+with+first+validated+40+nm+DRAM&rft.date=2009-02-04&rft.aulast=Gruener&rft.aufirst=Wolfgang&rft_id=http%3A%2F%2Fwww.tgdaily.com%2Fcontent%2Fview%2F41316%2F139%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-24"><span class="mw-cite-backlink"><b><a href="#cite_ref-24">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFJansen2009" class="citation web cs1">Jansen, Ng (January 20, 2009). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090622084614/http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm">"DDR3 Will be Cheaper, Faster in 2009"</a>. Dailytech. Archived from <a rel="nofollow" class="external text" href="http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm">the original</a> on June 22, 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">2009-06-17</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=DDR3+Will+be+Cheaper%2C+Faster+in+2009&rft.pub=Dailytech&rft.date=2009-01-20&rft.aulast=Jansen&rft.aufirst=Ng&rft_id=http%3A%2F%2Fwww.dailytech.com%2FDDR3%2BWill%2Bbe%2BCheaper%2BFaster%2Bin%2B2009%2Farticle13977.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFGervasi" class="citation web cs1">Gervasi, Bill. <a rel="nofollow" class="external text" href="http://discobolusdesigns.com/personal/20100721a_gervasi_rethinking_ddr4.pdf">"Time to rethink DDR4"</a> <span class="cs1-format">(PDF)</span>. <i>July 2010</i>. Discobolus Designs<span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-29</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=July+2010&rft.atitle=Time+to+rethink+DDR4&rft.aulast=Gervasi&rft.aufirst=Bill&rft_id=http%3A%2F%2Fdiscobolusdesigns.com%2Fpersonal%2F20100721a_gervasi_rethinking_ddr4.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1 cs1-prop-foreign-lang-source"><a rel="nofollow" class="external text" href="http://www.heise.de/newsticker/meldung/DDR4-Speicher-kommt-wohl-spaeter-als-bisher-geplant-1060545.html">"DDR4-Speicher kommt wohl später als bisher geplant"</a> [DDR4 memory is probably later than previously planned]. <i>Heise</i> (in German). DE. 2010-08-17<span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-29</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Heise&rft.atitle=DDR4-Speicher+kommt+wohl+sp%C3%A4ter+als+bisher+geplant&rft.date=2010-08-17&rft_id=http%3A%2F%2Fwww.heise.de%2Fnewsticker%2Fmeldung%2FDDR4-Speicher-kommt-wohl-spaeter-als-bisher-geplant-1060545.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span> (<a rel="nofollow" class="external text" href="https://translate.google.com/translate?hl=en&sl=de&tl=en&u=http%3A%2F%2Fwww.heise.de%2Fnewsticker%2Fmeldung%2FDDR4-Speicher-kommt-wohl-spaeter-als-bisher-geplant-1060545.html">English</a>)</span> </li> <li id="cite_note-27"><span class="mw-cite-backlink"><b><a href="#cite_ref-27">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFNilsson2010" class="citation web cs1">Nilsson, Lars-Göran (2010-08-16). <a rel="nofollow" class="external text" href="http://semiaccurate.com/2010/08/16/ddr4-not-expected-until-2015/">"DDR4 not expected until 2015"</a>. <i>Semi accurate</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-29</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Semi+accurate&rft.atitle=DDR4+not+expected+until+2015&rft.date=2010-08-16&rft.aulast=Nilsson&rft.aufirst=Lars-G%C3%B6ran&rft_id=http%3A%2F%2Fsemiaccurate.com%2F2010%2F08%2F16%2Fddr4-not-expected-until-2015%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-28"><span class="mw-cite-backlink"><b><a href="#cite_ref-28">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFannihilator2010" class="citation web cs1">annihilator (2010-08-18). <a rel="nofollow" class="external text" href="http://wccftech.com/2010/08/18/ddr4-memory-works-reach-4266ghz/">"DDR4 memory in Works, Will reach 4.266 GHz"</a>. <i>WCCF tech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-29</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=WCCF+tech&rft.atitle=DDR4+memory+in+Works%2C+Will+reach+4.266+GHz&rft.date=2010-08-18&rft.au=annihilator&rft_id=http%3A%2F%2Fwccftech.com%2F2010%2F08%2F18%2Fddr4-memory-works-reach-4266ghz%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-samsung_1-29"><span class="mw-cite-backlink">^ <a href="#cite_ref-samsung_1_29-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-samsung_1_29-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110716003504/http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=1202">"Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology"</a>. <i><a href="/wiki/Samsung" title="Samsung">Samsung</a></i>. 2011-04-11. Archived from <a rel="nofollow" class="external text" href="http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=1202">the original</a> on 2011-07-16.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Samsung&rft.atitle=Samsung+Develops+Industry%27s+First+DDR4+DRAM%2C+Using+30nm+Class+Technology&rft.date=2011-04-11&rft_id=http%3A%2F%2Fwww.samsung.com%2Fus%2Fbusiness%2Fsemiconductor%2FnewsView.do%3Fnews_id%3D1202&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-techgage-30"><span class="mw-cite-backlink"><b><a href="#cite_ref-techgage_30-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFPerry2011" class="citation web cs1">Perry, Ryan (2011-01-06). <a rel="nofollow" class="external text" href="http://techgage.com/news/samsung_develops_the_first_30nm_ddr4_dram/">"Samsung Develops the First 30nm DDR4 DRAM"</a>. <i>Tech gage</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-29</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tech+gage&rft.atitle=Samsung+Develops+the+First+30nm+DDR4+DRAM&rft.date=2011-01-06&rft.aulast=Perry&rft.aufirst=Ryan&rft_id=http%3A%2F%2Ftechgage.com%2Fnews%2Fsamsung_develops_the_first_30nm_ddr4_dram%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-31">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFProtalinski2011" class="citation cs2">Protalinski, Emil (2011-01-04), <a rel="nofollow" class="external text" href="http://www.techspot.com/news/41818-samsung-develops-ddr4-memory-up-to-40-more-efficient.html"><i>Samsung develops DDR4 memory, up to 40% more efficient</i></a>, Techspot<span class="reference-accessdate">, retrieved <span class="nowrap">2012-01-23</span></span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Samsung+develops+DDR4+memory%2C+up+to+40%25+more+efficient&rft.pub=Techspot&rft.date=2011-01-04&rft.aulast=Protalinski&rft.aufirst=Emil&rft_id=http%3A%2F%2Fwww.techspot.com%2Fnews%2F41818-samsung-develops-ddr4-memory-up-to-40-more-efficient.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-PC_Watch-32"><span class="mw-cite-backlink">^ <a href="#cite_ref-PC_Watch_32-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-PC_Watch_32-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-PC_Watch_32-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-PC_Watch_32-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREF後藤2010" class="citation web cs1 cs1-prop-foreign-lang-source">後藤, 弘茂 [Gotou Shigehiro] (16 August 2010). <a rel="nofollow" class="external text" href="https://pc.watch.impress.co.jp/docs/column/kaigai/387444.html">"メモリ4Gbps時代へと向かう次世代メモリDDR4"</a> [Towards Next-Generation 4Gbps DDR4 Memory]. <i>2010-08-16</i> (in Japanese). <a href="/wiki/Japan" title="Japan">JP</a>: PC Watch<span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-25</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=2010-08-16&rft.atitle=%E3%83%A1%E3%83%A2%E3%83%AA4Gbps%E6%99%82%E4%BB%A3%E3%81%B8%E3%81%A8%E5%90%91%E3%81%8B%E3%81%86%E6%AC%A1%E4%B8%96%E4%BB%A3%E3%83%A1%E3%83%A2%E3%83%AADDR4&rft.date=2010-08-16&rft.aulast=%E5%BE%8C%E8%97%A4&rft.aufirst=%E5%BC%98%E8%8C%82+%5BGotou+Shigehiro%5D&rft_id=https%3A%2F%2Fpc.watch.impress.co.jp%2Fdocs%2Fcolumn%2Fkaigai%2F387444.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span> (<a rel="nofollow" class="external text" href="https://translate.google.com/translate?js=y&prev=_t&hl=en&ie=UTF-8&layout=1&eotf=1&u=http%3A%2F%2Fpc.watch.impress.co.jp%2Fdocs%2Fcolumn%2Fkaigai%2F20100816_387444.html&sl=ja&tl=en">English translation</a>)</span> </li> <li id="cite_note-PC_Watch_(diagram_1)-33"><span class="mw-cite-backlink"><b><a href="#cite_ref-PC_Watch_(diagram_1)_33-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://pc.watch.impress.co.jp/img/pcw/docs/387/444/html/kaigai-09.jpg.html">"Diagram: Anticipated DDR4 timeline"</a>. <i>2010-08-16</i>. <a href="/wiki/Japan" title="Japan">JP</a>: PC Watch<span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-25</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=2010-08-16&rft.atitle=Diagram%3A+Anticipated+DDR4+timeline&rft_id=http%3A%2F%2Fpc.watch.impress.co.jp%2Fimg%2Fpcw%2Fdocs%2F387%2F444%2Fhtml%2Fkaigai-09.jpg.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-34"><span class="mw-cite-backlink"><b><a href="#cite_ref-34">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131104021100/http://www.xbitlabs.com/news/memory/display/20120702221021_Samsung_Samples_Industry_s_First_DDR4_Memory_Modules_for_Servers.html">"Samsung Samples Industry's First DDR4 Memory Modules for Servers"</a> (press release). Samsung. Archived from <a rel="nofollow" class="external text" href="http://www.xbitlabs.com/news/memory/display/20120702221021_Samsung_Samples_Industry_s_First_DDR4_Memory_Modules_for_Servers.html">the original</a> on 2013-11-04.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Samsung+Samples+Industry%27s+First+DDR4+Memory+Modules+for+Servers&rft.pub=Samsung&rft_id=http%3A%2F%2Fwww.xbitlabs.com%2Fnews%2Fmemory%2Fdisplay%2F20120702221021_Samsung_Samples_Industry_s_First_DDR4_Memory_Modules_for_Servers.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-35"><span class="mw-cite-backlink"><b><a href="#cite_ref-35">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.samsung.com/global/business/semiconductor/news-events/press-releases/detail?newsId=11701">"Samsung Samples Industry's First 16-Gigabyte Server Modules Based on DDR4 Memory technology"</a> (press release). Samsung.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Samsung+Samples+Industry%27s+First+16-Gigabyte+Server+Modules+Based+on+DDR4+Memory+technology&rft.pub=Samsung&rft_id=http%3A%2F%2Fwww.samsung.com%2Fglobal%2Fbusiness%2Fsemiconductor%2Fnews-events%2Fpress-releases%2Fdetail%3FnewsId%3D11701&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-36"><span class="mw-cite-backlink"><b><a href="#cite_ref-36">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFEmily_Desjardins2012" class="citation web cs1">Emily Desjardins (25 September 2012). <a rel="nofollow" class="external text" href="https://www.jedec.org/news/pressreleases/jedec-announces-publication-ddr4-standard">"JEDEC Announces Publication of DDR4 Standard"</a>. <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a><span class="reference-accessdate">. Retrieved <span class="nowrap">5 April</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=JEDEC+Announces+Publication+of+DDR4+Standard&rft.pub=JEDEC&rft.date=2012-09-25&rft.au=Emily+Desjardins&rft_id=https%3A%2F%2Fwww.jedec.org%2Fnews%2Fpressreleases%2Fjedec-announces-publication-ddr4-standard&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-TechHive_April_2013-37"><span class="mw-cite-backlink"><b><a href="#cite_ref-TechHive_April_2013_37-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFShah2013" class="citation cs2">Shah, Agam (April 12, 2013), <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150111152722/http://www.techhive.com/article/2034175/adoption-of-ddr4-memory-facing-delays.html">"Adoption of DDR4 memory faces delays"</a>, <i>TechHive</i>, IDG, archived from <a rel="nofollow" class="external text" href="http://www.techhive.com/article/2034175/adoption-of-ddr4-memory-facing-delays.html">the original</a> on January 11, 2015<span class="reference-accessdate">, retrieved <span class="nowrap">June 30,</span> 2013</span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=TechHive&rft.atitle=Adoption+of+DDR4+memory+faces+delays&rft.date=2013-04-12&rft.aulast=Shah&rft.aufirst=Agam&rft_id=http%3A%2F%2Fwww.techhive.com%2Farticle%2F2034175%2Fadoption-of-ddr4-memory-facing-delays.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span>.</span> </li> <li id="cite_note-xbit-38"><span class="mw-cite-backlink">^ <a href="#cite_ref-xbit_38-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-xbit_38-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-xbit_38-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFShilov2010" class="citation cs2">Shilov, Anton (2010-08-16), <a rel="nofollow" class="external text" href="https://web.archive.org/web/20101219085440/http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html"><i>Next-Generation DDR4 Memory to Reach 4.266 GHz</i></a>, Xbit labs, archived from <a rel="nofollow" class="external text" href="http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html">the original</a> on 2010-12-19<span class="reference-accessdate">, retrieved <span class="nowrap">2011-01-03</span></span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Next-Generation+DDR4+Memory+to+Reach+4.266+GHz&rft.pub=Xbit+labs&rft.date=2010-08-16&rft.aulast=Shilov&rft.aufirst=Anton&rft_id=http%3A%2F%2Fwww.xbitlabs.com%2Fnews%2Fmemory%2Fdisplay%2F20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-39"><span class="mw-cite-backlink"><b><a href="#cite_ref-39">^</a></b></span> <span class="reference-text">1 Mbit = one million bits</span> </li> <li id="cite_note-40"><span class="mw-cite-backlink"><b><a href="#cite_ref-40">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160604222007/http://ddr4.org/samsung-mass-producing-first-10-nanometer-class-dram/">"Samsung Begins Production of 10-Nanometer Class DRAM"</a>. <i>Official DDR4 Memory Technology News Blog</i>. 2016-05-21. Archived from <a rel="nofollow" class="external text" href="https://ddr4.org/samsung-mass-producing-first-10-nanometer-class-dram/">the original</a> on 2016-06-04<span class="reference-accessdate">. Retrieved <span class="nowrap">2016-05-23</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Official+DDR4+Memory+Technology+News+Blog&rft.atitle=Samsung+Begins+Production+of+10-Nanometer+Class+DRAM&rft.date=2016-05-21&rft_id=https%3A%2F%2Fddr4.org%2Fsamsung-mass-producing-first-10-nanometer-class-dram%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-41"><span class="mw-cite-backlink"><b><a href="#cite_ref-41">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://semiengineering.com/1xnm-dram-challenges/">"1xnm DRAM Challenges"</a>. <i>Semiconductor Engineering</i>. 2016-02-18<span class="reference-accessdate">. Retrieved <span class="nowrap">2016-06-28</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Semiconductor+Engineering&rft.atitle=1xnm+DRAM+Challenges&rft.date=2016-02-18&rft_id=http%3A%2F%2Fsemiengineering.com%2F1xnm-dram-challenges%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-IDG_2013-42"><span class="mw-cite-backlink">^ <a href="#cite_ref-IDG_2013_42-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-IDG_2013_42-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-IDG_2013_42-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFShah2013" class="citation web cs1">Shah, Agam (2013-04-12). <a rel="nofollow" class="external text" href="https://www.pcworld.com/article/2034175/adoption-of-ddr4-memory-facing-delays.html">"Adoption of DDR4 memory faces delays"</a>. <a href="/wiki/International_Data_Group" title="International Data Group">IDG</a> News<span class="reference-accessdate">. Retrieved <span class="nowrap">22 April</span> 2013</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Adoption+of+DDR4+memory+faces+delays&rft.pub=IDG+News&rft.date=2013-04-12&rft.aulast=Shah&rft.aufirst=Agam&rft_id=https%3A%2F%2Fwww.pcworld.com%2Farticle%2F2034175%2Fadoption-of-ddr4-memory-facing-delays.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-43"><span class="mw-cite-backlink"><b><a href="#cite_ref-43">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techpowerup.com/185719/haswell-e-intels-first-8-core-desktop-processor-exposed">"Haswell-E –  Intel's First 8 Core Desktop Processor Exposed"</a>. <i>TechPowerUp</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TechPowerUp&rft.atitle=Haswell-E+%26ndash%3B%26%2332%3B+Intel%27s+First+8+Core+Desktop+Processor+Exposed&rft_id=https%3A%2F%2Fwww.techpowerup.com%2F185719%2Fhaswell-e-intels-first-8-core-desktop-processor-exposed&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-44"><span class="mw-cite-backlink"><b><a href="#cite_ref-44">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.techspot.com/news/63796-amd-zen-cpu-up-32-cores.html">"AMD's Zen processors to feature up to 32 cores, 8-channel DDR4"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD%27s+Zen+processors+to+feature+up+to+32+cores%2C+8-channel+DDR4&rft_id=http%3A%2F%2Fwww.techspot.com%2Fnews%2F63796-amd-zen-cpu-up-32-cores.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-bit-tech-45"><span class="mw-cite-backlink">^ <a href="#cite_ref-bit-tech_45-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-bit-tech_45-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFSwinburne2010" class="citation web cs1">Swinburne, Richard (2010-08-26). <a rel="nofollow" class="external text" href="http://www.bit-tech.net/hardware/memory/2010/08/26/ddr4-what-we-can-expect/1">"DDR4: What we can Expect"</a>. <i>Bit tech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2011-04-28</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Bit+tech&rft.atitle=DDR4%3A+What+we+can+Expect&rft.date=2010-08-26&rft.aulast=Swinburne&rft.aufirst=Richard&rft_id=http%3A%2F%2Fwww.bit-tech.net%2Fhardware%2Fmemory%2F2010%2F08%2F26%2Fddr4-what-we-can-expect%2F1&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span> <a rel="nofollow" class="external text" href="http://www.bit-tech.net/hardware/memory/2010/08/26/ddr4-what-we-can-expect/2">Page 1</a>, <a rel="nofollow" class="external text" href="http://www.bit-tech.net/hardware/memory/2010/08/26/ddr4-what-we-can-expect/2">2</a>, <a rel="nofollow" class="external text" href="http://www.bit-tech.net/hardware/memory/2010/08/26/ddr4-what-we-can-expect/3">3</a>.</span> </li> <li id="cite_note-jedec_1-46"><span class="mw-cite-backlink">^ <a href="#cite_ref-jedec_1_46-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-jedec_1_46-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.jedec.org/news/pressreleases/jedec-announces-broad-spectrum-3d-ic-standards-development">"JEDEC Announces Broad Spectrum of 3D-IC Standards Development"</a> (press release). <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a>. 2011-03-17<span class="reference-accessdate">. Retrieved <span class="nowrap">26 April</span> 2011</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=JEDEC+Announces+Broad+Spectrum+of+3D-IC+Standards+Development&rft.pub=JEDEC&rft.date=2011-03-17&rft_id=http%3A%2F%2Fwww.jedec.org%2Fnews%2Fpressreleases%2Fjedec-announces-broad-spectrum-3d-ic-standards-development&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-47"><span class="mw-cite-backlink"><b><a href="#cite_ref-47">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFTanTan2008" class="citation book cs1">Tan, Gutmann; Tan, Reif (2008). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=fhen8HeoC1AC&pg=PA278"><i>Wafer Level 3-D ICs Process Technology</i></a>. Springer. p. 278 (sections 12.3.4–12.3.5). <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-38776534-1" title="Special:BookSources/978-0-38776534-1"><bdi>978-0-38776534-1</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Wafer+Level+3-D+ICs+Process+Technology&rft.pages=278+%28sections+12.3.4-12.3.5%29&rft.pub=Springer&rft.date=2008&rft.isbn=978-0-38776534-1&rft.aulast=Tan&rft.aufirst=Gutmann&rft.au=Tan%2C+Reif&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3Dfhen8HeoC1AC%26pg%3DPA278&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-48"><span class="mw-cite-backlink"><b><a href="#cite_ref-48">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160304054739/https://doc.xdevs.com/doc/Standards/DDR4/JESD79-4%20DDR4%20SDRAM.pdf"><i>JESD79-4 – JEDEC Standard DDR4 SDRAM September 2012</i></a> <span class="cs1-format">(PDF)</span>, X devs, archived from <a rel="nofollow" class="external text" href="https://doc.xdevs.com/doc/Standards/DDR4/JESD79-4%20DDR4%20SDRAM.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2016-03-04<span class="reference-accessdate">, retrieved <span class="nowrap">2015-09-19</span></span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=JESD79-4+%E2%80%93+JEDEC+Standard+DDR4+SDRAM+September+2012&rft.pub=X+devs&rft_id=https%3A%2F%2Fdoc.xdevs.com%2Fdoc%2FStandards%2FDDR4%2FJESD79-4%2520DDR4%2520SDRAM.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span>.</span> </li> <li id="cite_note-:0-49"><span class="mw-cite-backlink">^ <a href="#cite_ref-:0_49-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:0_49-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-:0_49-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFBland" class="citation web cs1">Bland, Rod. <a rel="nofollow" class="external text" href="https://help.ramcity.com.au/hc/en-us/articles/360001143896-What-are-the-different-Memory-RAM-types-">"What are the different Memory (RAM) types?"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=What+are+the+different+Memory+%28RAM%29+types%3F&rft.aulast=Bland&rft.aufirst=Rod&rft_id=https%3A%2F%2Fhelp.ramcity.com.au%2Fhc%2Fen-us%2Farticles%2F360001143896-What-are-the-different-Memory-RAM-types-&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-ddr4-50"><span class="mw-cite-backlink">^ <a href="#cite_ref-ddr4_50-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-ddr4_50-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://www.jedec.org/standards-documents/docs/jesd79-4a"><i>JEDEC Standard JESD79-4: DDR4 SDRAM</i></a>, JEDEC Solid State Technology Association, September 2012<span class="reference-accessdate">, retrieved <span class="nowrap">2012-10-11</span></span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=JEDEC+Standard+JESD79-4%3A+DDR4+SDRAM&rft.pub=JEDEC+Solid+State+Technology+Association&rft.date=2012-09&rft_id=https%3A%2F%2Fwww.jedec.org%2Fstandards-documents%2Fdocs%2Fjesd79-4a&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span>. Username "<a href="/wiki/Cypherpunk" title="Cypherpunk">cypherpunks</a>" and password "cypherpunks" will allow download.</span> </li> <li id="cite_note-ddr4b-51"><span class="mw-cite-backlink"><b><a href="#cite_ref-ddr4b_51-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://www.jedec.org/system/files/docs/JESD79-4B.pdf"><i>JEDEC Standard JESD79-4B: DDR4 SDRAM</i></a> <span class="cs1-format">(PDF)</span>, JEDEC Solid State Technology Association, June 2017<span class="reference-accessdate">, retrieved <span class="nowrap">2017-08-18</span></span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=JEDEC+Standard+JESD79-4B%3A+DDR4+SDRAM&rft.pub=JEDEC+Solid+State+Technology+Association&rft.date=2017-06&rft_id=https%3A%2F%2Fwww.jedec.org%2Fsystem%2Ffiles%2Fdocs%2FJESD79-4B.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span>. Username "<a href="/wiki/Cypherpunk" title="Cypherpunk">cypherpunks</a>" and password "cypherpunks" will allow download.</span> </li> <li id="cite_note-52"><span class="mw-cite-backlink"><b><a href="#cite_ref-52">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFLynch2017" class="citation news cs1">Lynch, Steven (19 June 2017). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/gskill-ddr4-4800-memory-computex,34825.html">"G.Skill Brought Its Blazing Fast DDR4-4800 To Computex"</a>. <i><a href="/wiki/Tom%27s_Hardware" title="Tom's Hardware">Tom's Hardware</a></i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Tom%27s+Hardware&rft.atitle=G.Skill+Brought+Its+Blazing+Fast+DDR4-4800+To+Computex&rft.date=2017-06-19&rft.aulast=Lynch&rft.aufirst=Steven&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Fgskill-ddr4-4800-memory-computex%2C34825.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-Denali-53"><span class="mw-cite-backlink">^ <a href="#cite_ref-Denali_53-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Denali_53-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Denali_53-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-Denali_53-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131202235148/http://denalimemoryreport.com/2012/07/26/want-the-latest-scoop-on-ddr4-dram-here-are-some-technical-answers-from-the-micron-team-of-interest-to-ic-system-and-pcb-designers/">"Want the latest scoop on DDR4 DRAM? Here are some technical answers from the Micron team of interest to IC, system, and pcb designers"</a>. Denali Memory Report, a memory market reporting site. 2012-07-26. Archived from <a rel="nofollow" class="external text" href="http://denalimemoryreport.com/2012/07/26/want-the-latest-scoop-on-ddr4-dram-here-are-some-technical-answers-from-the-micron-team-of-interest-to-ic-system-and-pcb-designers/">the original</a> on 2013-12-02<span class="reference-accessdate">. Retrieved <span class="nowrap">22 April</span> 2013</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Want+the+latest+scoop+on+DDR4+DRAM%3F+Here+are+some+technical+answers+from+the+Micron+team+of+interest+to+IC%2C+system%2C+and+pcb+designers&rft.pub=Denali+Memory+Report%2C+a+memory+market+reporting+site&rft.date=2012-07-26&rft_id=http%3A%2F%2Fdenalimemoryreport.com%2F2012%2F07%2F26%2Fwant-the-latest-scoop-on-ddr4-dram-here-are-some-technical-answers-from-the-micron-team-of-interest-to-ic-system-and-pcb-designers%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-54"><span class="mw-cite-backlink"><b><a href="#cite_ref-54">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation cs2"><a rel="nofollow" class="external text" href="http://www.jedec.org/sites/default/files/docs/MO-309E.pdf"><i>MO-309E</i></a> <span class="cs1-format">(PDF)</span> (whitepaper), JEDEC<span class="reference-accessdate">, retrieved <span class="nowrap">Aug 20,</span> 2014</span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=MO-309E&rft.pub=JEDEC&rft_id=http%3A%2F%2Fwww.jedec.org%2Fsites%2Fdefault%2Ffiles%2Fdocs%2FMO-309E.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span>.</span> </li> <li id="cite_note-55"><span class="mw-cite-backlink"><b><a href="#cite_ref-55">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20141129035318/http://www.micron.com/-/media/documents/products/data%20sheet/modules/sodimm/ddr4/asf18c1gx72hz.pdf">"DDR4 SDRAM SO-DIMM (MTA18ASF1G72HZ, 8 GB) Datasheet"</a> <span class="cs1-format">(PDF)</span>. <a href="/wiki/Micron_Technology" title="Micron Technology">Micron Technology</a>. 2014-09-10. Archived from <a rel="nofollow" class="external text" href="http://www.micron.com/-/media/documents/products/data%20sheet/modules/sodimm/ddr4/asf18c1gx72hz.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2014-11-29<span class="reference-accessdate">. Retrieved <span class="nowrap">2014-11-20</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=DDR4+SDRAM+SO-DIMM+%28MTA18ASF1G72HZ%2C+8+GB%29+Datasheet&rft.pub=Micron+Technology&rft.date=2014-09-10&rft_id=http%3A%2F%2Fwww.micron.com%2F-%2Fmedia%2Fdocuments%2Fproducts%2Fdata%2520sheet%2Fmodules%2Fsodimm%2Fddr4%2Fasf18c1gx72hz.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-56"><span class="mw-cite-backlink"><b><a href="#cite_ref-56">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techpowerup.com/205231/how-intel-plans-to-transition-between-ddr3-and-ddr4-for-the-mainstream">"How Intel Plans to Transition Between DDR3 and DDR4 for the Mainstream"</a>. <i>Tech Power Up</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tech+Power+Up&rft.atitle=How+Intel+Plans+to+Transition+Between+DDR3+and+DDR4+for+the+Mainstream&rft_id=https%3A%2F%2Fwww.techpowerup.com%2F205231%2Fhow-intel-plans-to-transition-between-ddr3-and-ddr4-for-the-mainstream&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-59"><span class="mw-cite-backlink"><b><a href="#cite_ref-59">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFDenneman2015" class="citation web cs1">Denneman, Frank (2015-02-25). <a rel="nofollow" class="external text" href="http://frankdenneman.nl/2015/02/25/memory-deep-dive-ddr4/">"Memory Deep Dive: DDR4 Memory"</a>. <i>frankdenneman.nl</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2017-05-14</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=frankdenneman.nl&rft.atitle=Memory+Deep+Dive%3A+DDR4+Memory&rft.date=2015-02-25&rft.aulast=Denneman&rft.aufirst=Frank&rft_id=http%3A%2F%2Ffrankdenneman.nl%2F2015%2F02%2F25%2Fmemory-deep-dive-ddr4%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-60"><span class="mw-cite-backlink"><b><a href="#cite_ref-60">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.golem.de/news/arbeitsspeicher-ddr5-naehert-sich-langsam-der-marktreife-1608-122737.html">"Arbeitsspeicher: DDR5 nähert sich langsam der Marktreife"</a>. <i>Golem.de</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Golem.de&rft.atitle=Arbeitsspeicher%3A+DDR5+n%C3%A4hert+sich+langsam+der+Marktreife&rft_id=http%3A%2F%2Fwww.golem.de%2Fnews%2Farbeitsspeicher-ddr5-naehert-sich-langsam-der-marktreife-1608-122737.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-61"><span class="mw-cite-backlink"><b><a href="#cite_ref-61">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFRißka" class="citation web cs1">Rißka, Volker. <a rel="nofollow" class="external text" href="https://www.computerbase.de/2018-03/ddr-hbm3-hbm4-ram/">"<span class="cs1-kern-left"></span>"DDR is over": HBM3/HBM4 bringt Bandbreite für High-End-Systeme"</a>. <i>ComputerBase</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ComputerBase&rft.atitle=%22DDR+is+over%22%3A+HBM3%2FHBM4+bringt+Bandbreite+f%C3%BCr+High-End-Systeme&rft.aulast=Ri%C3%9Fka&rft.aufirst=Volker&rft_id=https%3A%2F%2Fwww.computerbase.de%2F2018-03%2Fddr-hbm3-hbm4-ram%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-extreme-62"><span class="mw-cite-backlink"><b><a href="#cite_ref-extreme_62-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.extremetech.com/computing/197720-beyond-ddr4-understand-the-differences-between-wide-io-hbm-and-hybrid-memory-cube">"Beyond DDR4: The differences between Wide I/O, HBM, and Hybrid Memory Cube"</a>. <i>Extreme Tech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">25 January</span> 2015</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Extreme+Tech&rft.atitle=Beyond+DDR4%3A+The+differences+between+Wide+I%2FO%2C+HBM%2C+and+Hybrid+Memory+Cube&rft_id=http%3A%2F%2Fwww.extremetech.com%2Fcomputing%2F197720-beyond-ddr4-understand-the-differences-between-wide-io-hbm-and-hybrid-memory-cube&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-63"><span class="mw-cite-backlink"><b><a href="#cite_ref-63">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.epdtonthenet.net/article/85020/Goodbye-DDR-hello-serial-memory.aspx">"Xilinx Ltd –  Goodbye DDR, hello serial memory"</a>. <i>EPDT on the Net</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=EPDT+on+the+Net&rft.atitle=Xilinx+Ltd+%26ndash%3B%26%2332%3B+Goodbye+DDR%2C+hello+serial+memory&rft_id=http%3A%2F%2Fwww.epdtonthenet.net%2Farticle%2F85020%2FGoodbye-DDR-hello-serial-memory.aspx&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-64"><span class="mw-cite-backlink"><b><a href="#cite_ref-64">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFSchmitz2014" class="citation web cs1">Schmitz, Tamara (October 27, 2014). <a rel="nofollow" class="external text" href="http://www.xilinx.com/support/documentation/white_papers/wp456-DDR-serial-mem.pdf">"The Rise of Serial Memory and the Future of DDR"</a> <span class="cs1-format">(PDF)</span><span class="reference-accessdate">. Retrieved <span class="nowrap">March 1,</span> 2015</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=The+Rise+of+Serial+Memory+and+the+Future+of+DDR&rft.date=2014-10-27&rft.aulast=Schmitz&rft.aufirst=Tamara&rft_id=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fwhite_papers%2Fwp456-DDR-serial-mem.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-65"><span class="mw-cite-backlink"><b><a href="#cite_ref-65">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.semiwiki.com/forum/content/3315-bye-bye-ddrn-protocol.html">"Bye-Bye DDRn Protocol?"</a>. <i>SemiWiki</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=SemiWiki&rft.atitle=Bye-Bye+DDRn+Protocol%3F&rft_id=http%3A%2F%2Fwww.semiwiki.com%2Fforum%2Fcontent%2F3315-bye-bye-ddrn-protocol.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-66"><span class="mw-cite-backlink"><b><a href="#cite_ref-66">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.pcworld.com/article/3109505/components/dram-will-live-on-as-ddr5-memory-is-slated-to-reach-computers-in-2020.html">"DRAM will live on as DDR5 memory is slated to reach computers in 2020"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=DRAM+will+live+on+as+DDR5+memory+is+slated+to+reach+computers+in+2020&rft_id=http%3A%2F%2Fwww.pcworld.com%2Farticle%2F3109505%2Fcomponents%2Fdram-will-live-on-as-ddr5-memory-is-slated-to-reach-computers-in-2020.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR4_SDRAM&action=edit&section=14" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation cs2"><a rel="nofollow" class="external text" href="http://www.jedec.org/category/technology-focus-area/main-memory-ddr3-ddr4-sdram"><i>Main Memory: DDR3 & DDR4 SDRAM</i></a>, JEDEC</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Main+Memory%3A+DDR3+%26+DDR4+SDRAM&rft.pub=JEDEC&rft_id=http%3A%2F%2Fwww.jedec.org%2Fcategory%2Ftechnology-focus-area%2Fmain-memory-ddr3-ddr4-sdram&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span>, <a rel="nofollow" class="external text" href="https://www.jedec.org/standards-documents/docs/jesd79-4a">DDR4 SDRAM STANDARD (JESD79-4)</a></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20141010000932/http://www.corsair.com/~/media/Corsair/download-files/manuals/dram/DDR4-White-Paper.pdf"><i>DDR4</i></a> <span class="cs1-format">(PDF)</span> (white paper), Corsair Components, archived from <a rel="nofollow" class="external text" href="http://www.corsair.com/~/media/Corsair/download-files/manuals/dram/DDR4-White-Paper.pdf">the original</a> <span class="cs1-format">(PDF)</span> on October 10, 2014</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=DDR4&rft.pub=Corsair+Components&rft_id=http%3A%2F%2Fwww.corsair.com%2F~%2Fmedia%2FCorsair%2Fdownload-files%2Fmanuals%2Fdram%2FDDR4-White-Paper.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR4+SDRAM" class="Z3988"></span>.</li></ul> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><style data-mw-deduplicate="TemplateStyles:r1236075235">.mw-parser-output .navbox{box-sizing:border-box;border:1px solid #a2a9b1;width:100%;clear:both;font-size:88%;text-align:center;padding:1px;margin:1em auto 0}.mw-parser-output .navbox .navbox{margin-top:0}.mw-parser-output .navbox+.navbox,.mw-parser-output .navbox+.navbox-styles+.navbox{margin-top:-1px}.mw-parser-output .navbox-inner,.mw-parser-output .navbox-subgroup{width:100%}.mw-parser-output .navbox-group,.mw-parser-output .navbox-title,.mw-parser-output .navbox-abovebelow{padding:0.25em 1em;line-height:1.5em;text-align:center}.mw-parser-output .navbox-group{white-space:nowrap;text-align:right}.mw-parser-output .navbox,.mw-parser-output .navbox-subgroup{background-color:#fdfdfd}.mw-parser-output .navbox-list{line-height:1.5em;border-color:#fdfdfd}.mw-parser-output .navbox-list-with-group{text-align:left;border-left-width:2px;border-left-style:solid}.mw-parser-output tr+tr>.navbox-abovebelow,.mw-parser-output tr+tr>.navbox-group,.mw-parser-output tr+tr>.navbox-image,.mw-parser-output tr+tr>.navbox-list{border-top:2px solid #fdfdfd}.mw-parser-output .navbox-title{background-color:#ccf}.mw-parser-output .navbox-abovebelow,.mw-parser-output .navbox-group,.mw-parser-output .navbox-subgroup .navbox-title{background-color:#ddf}.mw-parser-output .navbox-subgroup .navbox-group,.mw-parser-output .navbox-subgroup .navbox-abovebelow{background-color:#e6e6ff}.mw-parser-output .navbox-even{background-color:#f7f7f7}.mw-parser-output .navbox-odd{background-color:transparent}.mw-parser-output .navbox .hlist td dl,.mw-parser-output .navbox .hlist td ol,.mw-parser-output .navbox .hlist td ul,.mw-parser-output .navbox td.hlist dl,.mw-parser-output .navbox td.hlist ol,.mw-parser-output .navbox td.hlist ul{padding:0.125em 0}.mw-parser-output .navbox .navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="Dynamic_random-access_memory_(DRAM)148" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:DRAM" title="Template:DRAM"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:DRAM" title="Template talk:DRAM"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:DRAM" title="Special:EditPage/Template:DRAM"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Dynamic_random-access_memory_(DRAM)148" style="font-size:114%;margin:0 4em"><a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">Dynamic random-access memory</a> (DRAM)</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Asynchronous</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/FPM_DRAM" class="mw-redirect" title="FPM DRAM">FPM DRAM</a></li> <li><a href="/wiki/EDO_DRAM" class="mw-redirect" title="EDO DRAM">EDO DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">SDRAM</a></li> <li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> <ul><li><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a></li> <li><a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a></li> <li><a class="mw-selflink selflink">DDR4</a></li> <li><a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a></li></ul></li> <li><a href="/wiki/LPDDR" title="LPDDR">LPDDR</a> (Mobile DDR)</li> <li><a href="/wiki/Fast_Cycle_DRAM" title="Fast Cycle DRAM">Fast Cycle DRAM</a> (FCRAM)</li> <li><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a></li> <li><a href="/wiki/RLDRAM" title="RLDRAM">RLDRAM</a></li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a> <ul><li><a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a></li> <li><a href="/wiki/HBM2E" class="mw-redirect" title="HBM2E">HBM2E</a></li> <li><a href="/wiki/HBM3" class="mw-redirect" title="HBM3">HBM3</a></li> <li><a href="/wiki/HBM-PIM" class="mw-redirect" title="HBM-PIM">HBM-PIM</a></li> <li><a href="/wiki/HBM3E" class="mw-redirect" title="HBM3E">HBM3E</a></li></ul></li> <li><a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Graphics</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">VRAM</a></li> <li><a href="/wiki/WRAM_(memory)" class="mw-redirect" title="WRAM (memory)">WRAM</a></li> <li><a href="/wiki/MDRAM" class="mw-redirect" title="MDRAM">MDRAM</a></li> <li><a href="/wiki/SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a> <ul><li><a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR</a></li> <li><a href="/wiki/GDDR2_SDRAM" class="mw-redirect" title="GDDR2 SDRAM">GDDR2</a></li> <li><a href="/wiki/GDDR3_SDRAM" title="GDDR3 SDRAM">GDDR3</a></li> <li><a href="/wiki/GDDR4_SDRAM" title="GDDR4 SDRAM">GDDR4</a></li> <li><a href="/wiki/GDDR5_SDRAM" title="GDDR5 SDRAM">GDDR5</a></li> <li><a href="/wiki/GDDR6_SDRAM" title="GDDR6 SDRAM">GDDR6</a></li> <li><a href="/wiki/GDDR7_SDRAM" title="GDDR7 SDRAM">GDDR7</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Rambus" title="Rambus">Rambus</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a></li> <li><a href="/wiki/XDR_DRAM" title="XDR DRAM">XDR DRAM</a></li> <li><a href="/wiki/XDR2_DRAM" title="XDR2 DRAM">XDR2 DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Memory_module" title="Memory module">Memory modules</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/SIMM" title="SIMM">SIMM</a></li> <li><a href="/wiki/DIMM" title="DIMM">DIMM</a></li> <li><a href="/wiki/UniDIMM" title="UniDIMM">UniDIMM</a></li> <li><a href="/wiki/CAMM_(memory_module)" title="CAMM (memory module)">CAMM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Random-access_memory#DRAM" title="Random-access memory">DRAM timeline</a></li> <li><a href="/wiki/Synchronous_dynamic_random-access_memory#Timeline" title="Synchronous dynamic random-access memory">SDRAM timeline</a></li> <li><a href="/wiki/List_of_interface_bit_rates#Dynamic_random-access_memory" title="List of interface bit rates">Bandwidth</a></li> <li><a href="/wiki/Transistor_count#Memory" title="Transistor count">Transistor count</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://auth.wikimedia.org/loginwiki/wiki/Special:CentralAutoLogin/start?useformat=desktop&type=1x1&usesul3=1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=DDR4_SDRAM&oldid=1278891957">https://en.wikipedia.org/w/index.php?title=DDR4_SDRAM&oldid=1278891957</a>"</div></div> <div id="catlinks" class="catlinks" data-mw="interface"><div id="mw-normal-catlinks" class="mw-normal-catlinks"><a href="/wiki/Help:Category" title="Help:Category">Category</a>: <ul><li><a href="/wiki/Category:SDRAM" title="Category:SDRAM">SDRAM</a></li></ul></div><div id="mw-hidden-catlinks" class="mw-hidden-catlinks mw-hidden-cats-hidden">Hidden categories: <ul><li><a href="/wiki/Category:CS1:_unfit_URL" title="Category:CS1: unfit URL">CS1: unfit URL</a></li><li><a href="/wiki/Category:CS1_German-language_sources_(de)" title="Category:CS1 German-language sources (de)">CS1 German-language sources (de)</a></li><li><a href="/wiki/Category:CS1_Japanese-language_sources_(ja)" title="Category:CS1 Japanese-language sources (ja)">CS1 Japanese-language sources (ja)</a></li><li><a href="/wiki/Category:Articles_with_short_description" title="Category:Articles with short description">Articles with short description</a></li><li><a href="/wiki/Category:Short_description_is_different_from_Wikidata" title="Category:Short description is different from Wikidata">Short description is different from Wikidata</a></li><li><a href="/wiki/Category:All_articles_with_failed_verification" title="Category:All articles with failed verification">All articles with failed verification</a></li><li><a href="/wiki/Category:Articles_with_failed_verification_from_September_2019" title="Category:Articles with failed verification from September 2019">Articles with failed verification from September 2019</a></li><li><a href="/wiki/Category:Wikipedia_articles_in_need_of_updating_from_January_2014" title="Category:Wikipedia articles in need of updating from January 2014">Wikipedia articles in need of updating from January 2014</a></li><li><a href="/wiki/Category:All_Wikipedia_articles_in_need_of_updating" title="Category:All Wikipedia articles in need of updating">All Wikipedia articles in need of updating</a></li></ul></div></div> </div> </main> </div> <div class="mw-footer-container"> <footer id="footer" class="mw-footer" > <ul id="footer-info"> <li id="footer-info-lastmod"> This page was last edited on 5 March 2025, at 06:47<span class="anonymous-show"> (UTC)</span>.</li> <li id="footer-info-copyright">Text is available under the <a href="/wiki/Wikipedia:Text_of_the_Creative_Commons_Attribution-ShareAlike_4.0_International_License" title="Wikipedia:Text of the Creative Commons Attribution-ShareAlike 4.0 International License">Creative Commons Attribution-ShareAlike 4.0 License</a>; additional terms may apply. By using this site, you agree to the <a href="https://foundation.wikimedia.org/wiki/Special:MyLanguage/Policy:Terms_of_Use" class="extiw" title="foundation:Special:MyLanguage/Policy:Terms of Use">Terms of Use</a> and <a href="https://foundation.wikimedia.org/wiki/Special:MyLanguage/Policy:Privacy_policy" class="extiw" title="foundation:Special:MyLanguage/Policy:Privacy policy">Privacy Policy</a>. Wikipedia® is a registered trademark of the <a rel="nofollow" class="external text" href="https://wikimediafoundation.org/">Wikimedia Foundation, Inc.</a>, a non-profit organization.</li> </ul> <ul id="footer-places"> <li id="footer-places-privacy"><a href="https://foundation.wikimedia.org/wiki/Special:MyLanguage/Policy:Privacy_policy">Privacy policy</a></li> <li id="footer-places-about"><a href="/wiki/Wikipedia:About">About Wikipedia</a></li> <li id="footer-places-disclaimers"><a href="/wiki/Wikipedia:General_disclaimer">Disclaimers</a></li> <li id="footer-places-contact"><a href="//en.wikipedia.org/wiki/Wikipedia:Contact_us">Contact Wikipedia</a></li> <li id="footer-places-wm-codeofconduct"><a href="https://foundation.wikimedia.org/wiki/Special:MyLanguage/Policy:Universal_Code_of_Conduct">Code of Conduct</a></li> <li id="footer-places-developers"><a href="https://developer.wikimedia.org">Developers</a></li> <li id="footer-places-statslink"><a href="https://stats.wikimedia.org/#/en.wikipedia.org">Statistics</a></li> <li id="footer-places-cookiestatement"><a href="https://foundation.wikimedia.org/wiki/Special:MyLanguage/Policy:Cookie_statement">Cookie statement</a></li> <li id="footer-places-mobileview"><a href="//en.m.wikipedia.org/w/index.php?title=DDR4_SDRAM&mobileaction=toggle_view_mobile" class="noprint stopMobileRedirectToggle">Mobile view</a></li> </ul> <ul id="footer-icons" class="noprint"> <li id="footer-copyrightico"><a href="https://www.wikimedia.org/" class="cdx-button cdx-button--fake-button cdx-button--size-large cdx-button--fake-button--enabled"><picture><source media="(min-width: 500px)" srcset="/static/images/footer/wikimedia-button.svg" width="84" height="29"><img src="/static/images/footer/wikimedia.svg" width="25" height="25" alt="Wikimedia Foundation" lang="en" loading="lazy"></picture></a></li> <li id="footer-poweredbyico"><a href="https://www.mediawiki.org/" class="cdx-button cdx-button--fake-button cdx-button--size-large cdx-button--fake-button--enabled"><picture><source media="(min-width: 500px)" srcset="/w/resources/assets/poweredby_mediawiki.svg" width="88" height="31"><img src="/w/resources/assets/mediawiki_compact.svg" alt="Powered by MediaWiki" lang="en" width="25" height="25" loading="lazy"></picture></a></li> </ul> </footer> </div> </div> </div> <div class="vector-header-container vector-sticky-header-container"> <div id="vector-sticky-header" class="vector-sticky-header"> <div class="vector-sticky-header-start"> <div class="vector-sticky-header-icon-start vector-button-flush-left vector-button-flush-right" aria-hidden="true"> <button class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-sticky-header-search-toggle" tabindex="-1" data-event-name="ui.vector-sticky-search-form.icon"><span class="vector-icon mw-ui-icon-search mw-ui-icon-wikimedia-search"></span> <span>Search</span> </button> </div> <div role="search" class="vector-search-box-vue vector-search-box-show-thumbnail vector-search-box"> <div class="vector-typeahead-search-container"> <div class="cdx-typeahead-search cdx-typeahead-search--show-thumbnail"> <form action="/w/index.php" id="vector-sticky-search-form" class="cdx-search-input cdx-search-input--has-end-button"> <div class="cdx-search-input__input-wrapper" data-search-loc="header-moved"> <div class="cdx-text-input cdx-text-input--has-start-icon"> <input class="cdx-text-input__input" type="search" name="search" placeholder="Search Wikipedia"> <span class="cdx-text-input__icon cdx-text-input__start-icon"></span> </div> <input type="hidden" name="title" value="Special:Search"> </div> <button class="cdx-button cdx-search-input__end-button">Search</button> </form> </div> </div> </div> <div class="vector-sticky-header-context-bar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-sticky-header-toc" class="vector-dropdown mw-portlet mw-portlet-sticky-header-toc vector-sticky-header-toc vector-button-flush-left" > <input type="checkbox" id="vector-sticky-header-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-sticky-header-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-sticky-header-toc-label" for="vector-sticky-header-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-sticky-header-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <div class="vector-sticky-header-context-bar-primary" aria-hidden="true" ><span class="mw-page-title-main">DDR4 SDRAM</span></div> </div> </div> <div class="vector-sticky-header-end" aria-hidden="true"> <div class="vector-sticky-header-icons"> <a href="#" class="cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only" id="ca-talk-sticky-header" tabindex="-1" data-event-name="talk-sticky-header"><span class="vector-icon mw-ui-icon-speechBubbles mw-ui-icon-wikimedia-speechBubbles"></span> <span></span> </a> <a href="#" class="cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only" id="ca-subject-sticky-header" tabindex="-1" data-event-name="subject-sticky-header"><span class="vector-icon mw-ui-icon-article mw-ui-icon-wikimedia-article"></span> <span></span> </a> <a href="#" class="cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only" id="ca-history-sticky-header" tabindex="-1" data-event-name="history-sticky-header"><span class="vector-icon mw-ui-icon-wikimedia-history mw-ui-icon-wikimedia-wikimedia-history"></span> <span></span> </a> <a href="#" class="cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only mw-watchlink" id="ca-watchstar-sticky-header" tabindex="-1" data-event-name="watch-sticky-header"><span class="vector-icon mw-ui-icon-wikimedia-star mw-ui-icon-wikimedia-wikimedia-star"></span> <span></span> </a> <a href="#" class="cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only" id="ca-edit-sticky-header" tabindex="-1" data-event-name="wikitext-edit-sticky-header"><span class="vector-icon mw-ui-icon-wikimedia-wikiText mw-ui-icon-wikimedia-wikimedia-wikiText"></span> <span></span> </a> <a href="#" class="cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only" id="ca-ve-edit-sticky-header" tabindex="-1" data-event-name="ve-edit-sticky-header"><span class="vector-icon mw-ui-icon-wikimedia-edit mw-ui-icon-wikimedia-wikimedia-edit"></span> <span></span> </a> <a href="#" class="cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only" id="ca-viewsource-sticky-header" tabindex="-1" data-event-name="ve-edit-protected-sticky-header"><span class="vector-icon mw-ui-icon-wikimedia-editLock mw-ui-icon-wikimedia-wikimedia-editLock"></span> <span></span> </a> </div> <div class="vector-sticky-header-buttons"> <button class="cdx-button cdx-button--weight-quiet mw-interlanguage-selector" id="p-lang-btn-sticky-header" tabindex="-1" data-event-name="ui.dropdown-p-lang-btn-sticky-header"><span class="vector-icon mw-ui-icon-wikimedia-language mw-ui-icon-wikimedia-wikimedia-language"></span> <span>22 languages</span> </button> <a href="#" class="cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive" id="ca-addsection-sticky-header" tabindex="-1" data-event-name="addsection-sticky-header"><span class="vector-icon mw-ui-icon-speechBubbleAdd-progressive mw-ui-icon-wikimedia-speechBubbleAdd-progressive"></span> <span>Add topic</span> </a> </div> <div class="vector-sticky-header-icon-end"> <div class="vector-user-links"> </div> </div> </div> </div> </div> <div class="mw-portlet mw-portlet-dock-bottom emptyPortlet" id="p-dock-bottom"> <ul> </ul> </div> <script>(RLQ=window.RLQ||[]).push(function(){mw.config.set({"wgHostname":"mw-web.codfw.main-7dbbdd594f-4vf4b","wgBackendResponseTime":200,"wgPageParseReport":{"limitreport":{"cputime":"0.686","walltime":"0.863","ppvisitednodes":{"value":6534,"limit":1000000},"postexpandincludesize":{"value":148276,"limit":2097152},"templateargumentsize":{"value":5280,"limit":2097152},"expansiondepth":{"value":16,"limit":100},"expensivefunctioncount":{"value":6,"limit":500},"unstrip-depth":{"value":1,"limit":20},"unstrip-size":{"value":246136,"limit":5000000},"entityaccesscount":{"value":0,"limit":400},"timingprofile":["100.00% 743.723 1 -total"," 41.22% 306.555 2 Template:Reflist"," 28.36% 210.926 46 Template:Cite_web"," 9.60% 71.370 1 Template:Short_description"," 7.24% 53.815 1 Template:Infobox_memory"," 6.66% 49.549 1 Template:Infobox"," 6.41% 47.648 1 Template:Failed_verification"," 6.40% 47.583 7 Template:Main_other"," 6.23% 46.325 1 Template:DRAM"," 5.85% 43.482 1 Template:Fix"]},"scribunto":{"limitreport-timeusage":{"value":"0.367","limit":"10.000"},"limitreport-memusage":{"value":7936475,"limit":52428800}},"cachereport":{"origin":"mw-web.codfw.main-65585cc8dc-dllx4","timestamp":"20250401000620","ttl":2591626,"transientcontent":true}}});});</script> <script type="application/ld+json">{"@context":"https:\/\/schema.org","@type":"Article","name":"DDR4 SDRAM","url":"https:\/\/en.wikipedia.org\/wiki\/DDR4_SDRAM","sameAs":"http:\/\/www.wikidata.org\/entity\/Q1189682","mainEntity":"http:\/\/www.wikidata.org\/entity\/Q1189682","author":{"@type":"Organization","name":"Contributors to Wikimedia projects"},"publisher":{"@type":"Organization","name":"Wikimedia Foundation, Inc.","logo":{"@type":"ImageObject","url":"https:\/\/www.wikimedia.org\/static\/images\/wmf-hor-googpub.png"}},"datePublished":"2008-09-01T04:52:02Z","dateModified":"2025-03-05T06:47:24Z","headline":"fourth generation of double-data-rate synchronous dynamic random-access memory"}</script> </body> </html>