{"title":"Metal-Oxide-Semiconductor-Only Process Corner Monitoring Circuit","authors":"Davit Mirzoyan, Ararat Khachatryan","volume":123,"journal":"International Journal of Electronics and Communication Engineering","pagesStart":229,"pagesEnd":235,"ISSN":"1307-6892","URL":"https:\/\/publications.waset.org\/pdf\/10006453","abstract":"A process corner monitoring circuit (PCMC) is presented in this work. The circuit generates a signal, the logical value of which depends on the process corner only. The signal can be used in both digital and analog circuits for testing and compensation of process variations (PV). The presented circuit uses only metal-oxide-semiconductor (MOS) transistors, which allow increasing its detection accuracy, decrease power consumption and area. Due to its simplicity the presented circuit can be easily modified to monitor parametrical variations of only n-type and p-type MOS (NMOS and PMOS, respectively) transistors, resistors, as well as their combinations. Post-layout simulation results prove correct functionality of the proposed circuit, i.e. ability to monitor the process corner (equivalently die-to-die variations) even in the presence of within-die variations.","references":"[1]\tT. Chen, \u201cChallenges for silicon technology scaling in the Nanoscale Era,\u201d \tProc. of ESSCIRC, pp. 1-7, Sept. 2009.\r\n[2]\tY. Li, Ch. Hwang, T. Li, M. Han, \u201cProcess-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies,\u201d IEEE Trans. on Electron Devices, pp. 437 \u2013 447, Feb. 2010.\r\n[3]\tY. Ohnari, A.A. Khan, A. Dutta, M. M. Mattausch, H. J. Mattausch, \u201cDie-to-die and within-die variation extraction for circuit simulation with surface-potential compact model,\u201d IEEE Int. Conf. on Microelectronic Test Structures (ICMTS), pp. 146-150, March 2013.\r\n[4]\tL. Pang, B. Nikolic, \u201cMeasurements and analysis of process variability in 90nm CMOS,\u201d IEEE J. Solid-State Circuits, pp.1655-1663, May 2009.\r\n[5]\tC. H. Kim, K. Roy, S. Hsu, R. Krishnamurthy, S. Borkar, \u201cA process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits,\u201d IEEE Trans. on VLSI Systems, pp.646-649, 2006.\r\n[6]\tK. Kim, F. Ge, K. Choi, \u201cOn-chip process variation monitoring circuit based on gate leakage sensing\u201d, Electronics Letters, pp. 235 \u2013 236, 2010.\r\n[7]\tA. Ghosh, R. M. Rao, J. J. Kim, Ch. Chuang, R. B. Brown, \u201cSlew-Rate Monitoring Circuit for On-Chip Process Variation Detection,\u201d IEEE Trans. on VLSI Systems, pp. 1683-1692, 2013.\r\n[8]\tCh. Chen, H. Tseng, R. Kuo, Ch. Wang, \u201cOn-chip MOS PVT variation monitor for slew rate self-adjusting 2\u00d7VDD output buffers,\u201d IEEE Int. Conf. on IC Design & Technology, pp.1-4, 2012.\r\n[9]\tH. Mostafa, M. Anis, M. Elmasry, \u201cOn-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB),\u201d IEEE Trans. on VLSI Systems, pp. 770 \u2013 774, April 2012.\r\n[10]\tB. Razavi, \u201cDesign of Analog CMOS Integrated Circuits,\u201d McGraw- Hill Education, 2016.\r\n[11]\tN.Z. Butt, J.B. Johnson, \u201cModeling and Analysis of Transistor Mismatch Due to Variability in Short-Channel Effect Induced by Random Dopant Fluctuation,\u201d IEEE Electron Device Letters, pp.1099-1101, Aug. 2012.\r\n[12]\tH. Li, H. Chen, Q. Dong, L. Chen, J. Wang, J. Kim, Sh. Yu, J. Wu, Y. LinBashir, L. Milor, \u201cProcess optimization for random threshold voltage variation reduction in nanoscale MOSFET by 3D simulation,\u201d IEEE 11th Int. Conf. on Solid-State and Integrated Circuit Technology (ICSICT), pp.1-3, Oct. 2012.","publisher":"World Academy of Science, Engineering and Technology","index":"Open Science Index 123, 2017"}