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<!DOCTYPE html> <html lang="ko"> <head> <title>OASIS Repository@POSTECHLIBRARY: Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface</title> <meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /> <meta name="Generator" content="DSpace 5.5" /> <meta name="viewport" content="width=device-width, initial-scale=1.0"> <meta http-equiv="X-UA-Compatible" content="IE=edge"> <meta name="description" content="Postech OASIS Repository" /> <meta name="keywords" content="오아시스,레포지토리,리포지터리,저장소,포스텍,박태준학술정보관,포항공과대학교,포항공대,POSTECH,Pohang University of Science and Technology,도서관,IR,연구업적,학술실적,연구성과,dspace" /> <link rel="shortcut icon" href="/favicon.ico" type="image/x-icon"/> <link rel="search" type="application/opensearchdescription+xml" href="/open-search/description.xml" title="DSpace" /> <link rel="schema.DCTERMS" href="http://purl.org/dc/terms/" /> <link rel="schema.DC" href="http://purl.org/dc/elements/1.1/" /> <link rel="schema.OAK" href="http://www.oak.go.kr/terms/" /> <meta name="OAK.author" content="Ki-Hwan Seong" scheme="OAK.AUTHOR" /> <meta name="OAK.author" content="Ji-Hoon Lim" scheme="OAK.AUTHOR" /> <meta name="OAK.author" content="Kim, B" scheme="OAK.AUTHOR" /> <meta name="OAK.author" content="Sim, JY" scheme="OAK.AUTHOR" /> <meta name="OAK.author" content="Park, HJ" scheme="OAK.AUTHOR" /> <meta name="DCTERMS.dateAccepted" content="2016-03-31T07:30:14Z" scheme="DCTERMS.W3CDTF" /> <meta name="DCTERMS.available" content="2016-03-31T07:30:14Z" scheme="DCTERMS.W3CDTF" /> <meta name="DCTERMS.created" content="2015-02-09" scheme="DCTERMS.W3CDTF" /> <meta name="DCTERMS.issued" content="2014-08" scheme="DCTERMS.W3CDTF" /> <meta name="OAK.identifier.issn" content="1598-1657" scheme="OAK.ISSN" /> <meta name="DC.identifier" content="2014-OAK-0000032042" /> <meta name="DC.identifier" content="https://oasis.postech.ac.kr/handle/2014.oak/13703" scheme="DCTERMS.URI" /> <meta name="DCTERMS.abstract" content="A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit." /> <meta name="DC.description" content="X" /> <meta name="DC.language" content="English" /> <meta name="DC.publisher" content="대한전자공학회" /> <meta name="DC.relation" content="JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE" /> <meta name="DC.title" content="Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface" /> <meta name="DC.type" content="Article" /> <meta name="DC.contributor" content="전자전기공학과" /> <meta name="DC.identifier" content="10.5573/JSTS.2014.14.4.463" /> <meta name="DC.relation" content="14" /> <meta name="DC.relation" content="4" /> <meta name="DC.relation" content="463" /> <meta name="DC.relation" content="470" /> <meta name="DC.contributor" content="11082511" /> <meta name="DC.relation" content="JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE" /> <meta name="DC.relation" content="SCI급, SCOPUS 등재논문" /> <meta name="DC.relation" content="SCIE" /> <meta name="DC.identifier" content="16994" /> <meta name="DC.type" content="ART" /> <meta name="DC.identifier" content="JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.14, no.4, pp.463 - 470" /> <meta name="DC.identifier" content="000346136600013" /> <meta name="DC.date" content="2019-01-01" scheme="DCTERMS.W3CDTF" /> <meta name="OAK.relation.page" content="470" scheme="OAK.PAGE" /> <meta name="OAK.relation.issue" content="4" scheme="OAK.ISSUE" /> <meta name="OAK.relation.page" content="463" scheme="OAK.PAGE" /> <meta name="OAK.relation.journal" content="JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE" scheme="OAK.JOURNAL" /> <meta name="OAK.relation.volume" content="14" scheme="OAK.VOLUME" /> <meta name="DC.contributor" content="Kim, B" /> <meta name="DC.contributor" content="Sim, JY" /> <meta name="DC.contributor" content="Park, HJ" /> <meta name="DC.identifier" content="2-s2.0-84906887829" /> <meta name="DC.description" content="1" /> <meta name="DC.description" content="1" /> <meta name="DC.description" content="3" /> <meta name="DC.description" content="3" xml:lang="*" /> <meta name="DC.date" content="2018-05-121" xml:lang="*" scheme="DCTERMS.W3CDTF" /> <meta name="DC.description" content="Y" /> <meta name="DC.type" content="Article" /> <meta name="DC.subject" content="Verilog" /> <meta name="DC.subject" content="transmission line" /> <meta name="DC.subject" content="USB 2.0 high-speed PHY" /> <meta name="DC.subject" content="mixed-mode simulation" /> <meta name="DC.relation" content="Engineering, Electrical & Electronic" /> <meta name="DC.relation" content="Physics, Applied" /> <meta name="DC.description" content="scie" /> <meta name="DC.description" content="scopus" /> <meta name="DC.relation" content="Engineering" /> <meta name="DC.relation" content="Physics" /> <meta name="citation_keywords" content="Article" /> <meta name="citation_title" content="Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface" /> <meta name="citation_issn" content="1598-1657" /> <meta name="citation_publisher" content="대한전자공학회" /> <meta name="citation_author" content="Ki-Hwan Seong" /> <meta name="citation_author" content="Ji-Hoon Lim" /> <meta name="citation_author" content="Kim, B" /> <meta name="citation_author" content="Sim, JY" /> <meta name="citation_author" content="Park, HJ" /> <meta name="citation_pdf_url" content="https://oasis.postech.ac.kr/bitstream/2014.oak/13703/1/E1STAN_2014_v14n4_463.pdf" /> <meta name="citation_date" content="2014-08" /> <meta name="citation_abstract_html_url" content="https://oasis.postech.ac.kr/handle/2014.oak/13703" /> <link rel="stylesheet" href="/css/bootstrap.min.css" defer /> <link rel="stylesheet" href="/css/layout.css" async /> <link rel="stylesheet" href="/css/mquery.css" defer /> <link rel="stylesheet" href="/css/slidebars.css" defer />  <link rel="stylesheet" href="/css/owl.carousel.css" defer />  <link rel="stylesheet" href="/css/owl.theme.css" defer /> <link rel="stylesheet" href="/css/bootstrap-partof.css" defer /> <script src="/js/jquery-1.9.1.min.js"></script> <script src="/js/jquery-ui.js"></script> <script src="/js/bootstrap.min.js"></script> <script src="/js/owl.carousel.min.js"></script> <script src="/js/common.js" defer></script> <script src="/utils.js" defer></script> <script src="/static/js/holder.js" defer></script> <script src="/static/js/choice-support.js" defer></script> <script src="/js/ms-clarity.js"></script> <script async src="https://www.googletagmanager.com/gtag/js?id=G-B9EHYYGM78"></script> <script> window.dataLayer = window.dataLayer || []; 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Journal Papers</strong></a> </div></div> </div> <div class="col_width sub_container add_widget"> <div class="sub_contents"> <script src="https://apis.google.com/js/platform.js" async defer></script> <script type="text/javascript"> // google plus api window.___gcfg = {lang: 'ko'}; (function() { var po = document.createElement('script'); po.type = 'text/javascript'; po.async = true; po.src = 'https://apis.google.com/js/platform.js'; var s = document.getElementsByTagName('script')[0]; s.parentNode.insertBefore(po, s); })(); </script> <div class="sub_title"> <h3> </h3> <div class="type_icon"> <span class="article_type">Article</span> </div> </div> <div class="view_top_box"> <div class="view_bt_box"> <span class="cited_span science_span">Cited <em>3</em> time in <img src="/image/common/webofscience.png" alt="webofscience"></span> <span class="cited_span">Cited <em>3</em> time in <img src="/image/common/scopus.png" alt="scopus"></span> </div> <div class="view_bt_area"> <span>Metadata Downloads</span> <form action="/export" method="post"> <input type="hidden" name="item_id" value="13405"/> <div class="view_downbt"> <ul> <li> <input type="submit" name="submit_export_dc" value="DC(XML)"/> </li> <li> <input type="submit" name="submit_export_excel" value="EXCEL"/> </li> </ul> </div> </form> </div> </div> <div class="view_contents"> <p class="view_title">Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface <em class="a_l_ink a_l_scie">SCIE</em> <em class="a_l_ink a_l_scopus">SCOPUS</em> </p> <div class="view_inner_con"> <dl><dt>Title</dt><dd>Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface</dd></dl> <dl><dt>Authors</dt><dd><a class="author"href="/browse?type=author&value=Ki-Hwan+Seong">Ki-Hwan Seong</a>; <a class="author"href="/browse?type=author&value=Ji-Hoon+Lim">Ji-Hoon Lim</a>; <a class="author_a" href="/researcher-profile?ep=477">Kim, B</a>; <a class="author_a" href="/researcher-profile?ep=570">Sim, JY</a>; <a class="author_a" href="/researcher-profile?ep=369">Park, HJ</a></dd></dl> <dl><dt>Date Issued</dt><dd>2014-08 </dd></dl> <dl><dt>Publisher</dt><dd>대한전자공학회</dd></dl> <dl><dt>Abstract</dt><dd>A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.</dd></dl> <dl><dt>URI</dt><dd><a href="https://oasis.postech.ac.kr/handle/2014.oak/13703" class="link_type">https://oasis.postech.ac.kr/handle/2014.oak/13703</a></dd></dl> <dl><dt>DOI</dt><dd><a href="http://dx.doi.org/10.5573/JSTS.2014.14.4.463">10.5573/JSTS.2014.14.4.463</a></dd></dl> <dl><dt>ISSN</dt><dd>1598-1657</dd></dl> <dl><dt>Article Type</dt><dd>Article</dd></dl> <dl><dt>Citation</dt><dd>JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol. 14, no. 4, page. 463 - 470, 2014-08</dd></dl> <dl class="file_item_dl"><dt>Files in This Item:</dt> <dd class="file_download"> <ul> <li><a target="_blank" href="/bitstream/2014.oak/13703/1/E1STAN_2014_v14n4_463.pdf" class="file_text">E1STAN_2014_v14n4_463.pdf</a><a target="_blank" href="/bitstream/2014.oak/13703/1/E1STAN_2014_v14n4_463.pdf" class="download_right">2.46 MB</a></li></ul> </dd> </dl> </div> <div class="record_bt_box"> <a href="/handle/2014.oak/13703?mode=full">Show full item record</a> </div> <div class="al_right"> </div> <div class="sns_wrap"> <div class="sns_box"> <p class="qr_box"><img src="https://api.qrserver.com/v1/create-qr-code/?size=66x66&data=https://oasis.postech.ac.kr/handle/2014.oak/13703" alt="qr_code"></p> <div class="sns_inner"> <ul> <li> <p><a href="http://www.mendeley.com/import/?url=https://oasis.postech.ac.kr/handle/2014.oak/13703" target="_blank"><img src="/image/common/mendeley_icon.gif" alt="mendeley" /></a></p> <p class="twitter_box"> <a href="https://twitter.com/share" class="tweet_bt twitter-share-button" data-lang="en" data-size="large" data-dnt="true">트윗하기</a> <script> !function(d, s, id) { var js, fjs = d.getElementsByTagName(s)[0]; if (!d.getElementById(id)) { js = d.createElement(s); js.id = id; js.src = "//platform.twitter.com/widgets.js"; fjs.parentNode.insertBefore(js, fjs); } }(document, "script", "twitter-wjs"); </script> </p> </li> <li class="facebook_li"> <span id="fb-root"></span> <script> (function(d, s, id) { var js, fjs = d.getElementsByTagName(s)[0]; if (d.getElementById(id)) return; js = d.createElement(s); js.id = id; js.src = "//connect.facebook.net/ko_KR/all.js#xfbml=1"; fjs.parentNode.insertBefore(js, fjs); }(document, 'script', 'facebook-jssdk')); </script> <span class="fb-like" data-send="true" data-layout="standard" data-width="450" data-show-faces="false" data-font="verdana"></span> </li> </ul> </div> </div> <p class="sns_text"> <span> Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.</span> </p> </div> </div> </div>  <div class="sub_right_box"> <div class="w_cc"> <h4 class="widget_title">Communities & Collection</h4> <ul> <li><a href="/handle/2014.oak/418" class="cc_item">Department of Electrical Engineering (전자전기공학과)</a> <ul> <li><a href="/handle/2014.oak/419">1. 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