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SiFive Insight - Advanced Trace & Debug IP
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class="container"><div class="SectionContent_section__19wRK SectionContent_noBorder__o1wif"><div class="row"><div class="col-lg-2 col-12"><div class="SectionContent_square__ZsCGx"></div></div><div class="col-lg-9 col-12"><div class="SectionContent_title__UM4kh"><h2>Key <em>Features</em></h2></div><div class="SectionContent_text__fS9Jo"><p>From run-control debug, to cross-triggering, to advanced multi-core trace solutions, all SiFive Insight advanced trace and debug features are pre-integrated with SiFive’s RISC-V Core IP in a single deliverable and are verified together.</p><div class="SectionContent_image__NwWdg"><img alt="" loading="lazy" width="950" height="379.2140641158221" decoding="async" data-nimg="1" style="color:transparent" srcSet="https://images.prismic.io/sifive/76a10ba2-f19c-4f19-9b2b-8ca49a872970_tech-features-image.jpg?auto=compress,format&w=1080&q=70 1x, https://images.prismic.io/sifive/76a10ba2-f19c-4f19-9b2b-8ca49a872970_tech-features-image.jpg?auto=compress,format&w=1920&q=70 2x" src="https://images.prismic.io/sifive/76a10ba2-f19c-4f19-9b2b-8ca49a872970_tech-features-image.jpg?auto=compress,format&w=1920&q=70"/></div></div></div></div></div></div></div><div class="SectionContent_SectionContent__WUcS2"><div class="container"><div class="SectionContent_section__19wRK undefined"><div class="row"><div class="col-lg-2 col-12"><div class="SectionContent_square__ZsCGx"></div></div><div class="col-lg-9 col-12"><div class="SectionContent_title__UM4kh"><h2>Getting <em>Started</em></h2></div><div class="SectionContent_text__fS9Jo"><p>SiFive Insight is pre-integrated with SiFive RISC-V Core IP and can be easily configured using SiFive Core Designer to meet your specific requirements.</p></div></div></div></div></div></div><div class="SectionContent_SectionContent__WUcS2"><div class="container"><div class="SectionContent_section__19wRK undefined"><div class="row"><div class="col-lg-2 col-12"><div class="SectionContent_square__ZsCGx"></div></div><div class="col-lg-9 col-12"><div class="SectionContent_title__UM4kh"><h2>SiFive Insight Standard<br/><em>Debug</em></h2></div><div class="SectionContent_text__fS9Jo"><p>Every SiFive Core IP Series includes standard run-control debug. </p><p>Run-control debug is accessible over a number of industry standard interfaces and enables capabilities such as hardware breakpoints and external triggers that allow for SiFive cores to be halted by instruction accesses, data accesses, and external events, while System Bus Access (SBA) enables the debugger to access memories without interrupting the core.</p><div class="SectionContent_image__NwWdg"><img alt="" loading="lazy" width="950" height="517.7352637021717" decoding="async" data-nimg="1" style="color:transparent" srcSet="https://images.prismic.io/sifive/7689c56a-0e4b-4795-885e-5e5a790c18a5_tech-debug-image.jpg?auto=compress,format&w=1080&q=70 1x, https://images.prismic.io/sifive/7689c56a-0e4b-4795-885e-5e5a790c18a5_tech-debug-image.jpg?auto=compress,format&w=1920&q=70 2x" src="https://images.prismic.io/sifive/7689c56a-0e4b-4795-885e-5e5a790c18a5_tech-debug-image.jpg?auto=compress,format&w=1920&q=70"/></div></div></div></div></div></div></div><div class="SectionContent_SectionContent__WUcS2"><div class="container"><div class="SectionContent_section__19wRK undefined"><div class="row"><div class="col-lg-2 col-12"><div class="SectionContent_square__ZsCGx"></div></div><div class="col-lg-9 col-12"><div class="SectionContent_title__UM4kh"><h2>Standard Debug<br/><em>Key Features</em></h2></div><div class="SectionContent_text__fS9Jo"><ul><li>Support for JTAG, cJTAG, and AMBA APB interfaces</li><li>Heterogeneous multi-core debug capability</li><li>Up to 16 hardware breakpoints on instruction or data accesses</li><li>Up to 16 external breakpoint triggers</li><li>Option to include System Bus Access (SBA) to access memory without interrupting the core</li></ul></div></div></div></div></div></div><div class="SectionContent_SectionContent__WUcS2"><div class="container"><div class="SectionContent_section__19wRK undefined"><div class="row"><div class="col-lg-2 col-12"><div class="SectionContent_square__ZsCGx"></div></div><div class="col-lg-9 col-12"><div class="SectionContent_title__UM4kh"><h2>SiFive Insight Advanced<br/><em>Trace and Debug</em></h2></div><div class="SectionContent_text__fS9Jo"><p>Every SiFive Core IP series has the option to be coupled with a Nexus 5001-compliant trace encoder. Nexus 5001 has been an IEEE standard since 2003 and is well-supported by the software tool ecosystem. The SiFive Insight trace encoder is highly configurable to meet application specific requirements.</p><div class="SectionContent_image__NwWdg"><img alt="" loading="lazy" width="950" height="925.5406797116375" decoding="async" data-nimg="1" style="color:transparent" srcSet="https://images.prismic.io/sifive/a4a978d5-fe4f-480c-b4d1-2ccda4e74b47_tech-trace-image.jpg?auto=compress,format&w=1080&q=70 1x, https://images.prismic.io/sifive/a4a978d5-fe4f-480c-b4d1-2ccda4e74b47_tech-trace-image.jpg?auto=compress,format&w=1920&q=70 2x" src="https://images.prismic.io/sifive/a4a978d5-fe4f-480c-b4d1-2ccda4e74b47_tech-trace-image.jpg?auto=compress,format&w=1920&q=70"/></div></div></div></div></div></div></div><div class="SectionContent_SectionContent__WUcS2"><div class="container"><div class="SectionContent_section__19wRK undefined"><div class="row"><div class="col-lg-2 col-12"><div class="SectionContent_square__ZsCGx"></div></div><div class="col-lg-9 col-12"><div class="SectionContent_title__UM4kh"><h2><em>Trace</em> Key Features</h2></div><div class="SectionContent_text__fS9Jo"><ul><li>Heterogeneous multi-core trace capability</li><li>Optional time-stamping with configurable resolution and source</li><li>Up to 16 input and output hardware trace triggers for system-level interaction</li><li>Support for several trace sink options: SRAM, ATB, pins, and system memory</li><li>Optional Instrumented Trace Component (ITC) to embed print statements directly into the trace stream</li></ul></div></div></div></div></div></div><div class="SectionContent_SectionContent__WUcS2"><div class="container"><div class="SectionContent_section__19wRK undefined"><div class="row"><div class="col-lg-2 col-12"><div class="SectionContent_square__ZsCGx"></div></div><div class="col-lg-9 col-12"><div class="SectionContent_title__UM4kh"><h2>Industry <em>Support</em></h2></div><div class="SectionContent_text__fS9Jo"><p>SiFive Freedom Studio fully supports the SiFive Insight trace and debug IP, providing users access to a free Eclipse-based IDE for software development and system debug.</p><p>SiFive Insight is supported by leading tool vendors:</p><ul><li>Ashling</li><li>IAR</li><li>Lauterbach</li><li>SEGGER</li></ul></div></div></div></div></div></div><div class="SectionContent_SectionContent__WUcS2"><div class="container"><div class="SectionContent_section__19wRK undefined"><div class="row"><div class="col-lg-2 col-12"><div class="SectionContent_square__ZsCGx"></div></div><div class="col-lg-9 col-12"><div class="SectionContent_title__UM4kh"><h2>Compatible with Arm®<br/><em>CoreSight™ Technology</em></h2></div><div class="SectionContent_text__fS9Jo"><p>A unique feature of SiFive Insight is compatibility with Arm® CoreSight™ technology, enabling SiFive cores to easily coexist in mixed-ISA environments. This feature allows developers to continue to leverage their investments in existing hardware platforms as well as software and tools in mixed-ISA SoC designs, making it easier than ever to adopt SiFive RISC-V for your next-generation design.</p></div></div></div></div></div></div></main><footer class="Footer_footer__KQx25"><div class="container"><div style="z-index:10" class="relative row"><div class="col-xl-5 col-lg-12"><a class="Footer_logo__CBryw" title="SiFive" href="https://www.sifive.com/"><svg xmlns="http://www.w3.org/2000/svg" width="100" height="34" fill="none" viewBox="0 0 100 34"><path fill="#fff" d="M4.274 17.6 8.862 3.375H26.44l1.784 5.534H12.696l-.992 3.14h17.533l2.636 8.175L17.65 30.708 4.135 20.739h9.127l4.349 3.207 8.605-6.343zM28.56 0H6.742L0 21.016 17.651 34l17.651-12.988zM53.086 9.614l-1.083 2.329c-1.68-1.03-3.358-1.456-4.529-1.456-1.524 0-2.519.582-2.519 1.635 0 3.425 8.351 1.59 8.33 7.232 0 2.8-2.43 4.523-5.833 4.523-2.43 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Insight - Advanced Trace \u0026 Debug IP","meta_description":"The SiFive® Insight™ solution is the industry’s first comprehensive pre-integrated advanced trace and debug solution for RISC-V, offering SoC designers class-leading debug capabilities to bring-up first silicon, support hardware and software integration, and debug software applications.","share_image":{},"add_contact_form":false,"hero":[{"image":{},"title":[{"type":"heading1","text":"SiFive Insight","spans":[{"start":7,"end":14,"type":"em"}]}],"body":[{"type":"paragraph","text":"Advanced Trace and Debug IP","spans":[{"start":0,"end":27,"type":"strong"}]},{"type":"paragraph","text":"The SiFive® Insight™ solution is the industry’s first comprehensive pre-integrated advanced trace and debug solution for RISC-V, offering SoC designers class-leading debug capabilities to bring-up first silicon, support hardware and software integration, and debug software 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