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<span>Description</span> </div> </a> <button aria-controls="toc-Description-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Description subsection</span> </button> <ul id="toc-Description-sublist" class="vector-toc-list"> <li id="toc-Integer_execution" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Integer_execution"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Integer execution</span> </div> </a> <ul id="toc-Integer_execution-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Floating-point_execution" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Floating-point_execution"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>Floating-point execution</span> </div> </a> <ul id="toc-Floating-point_execution-sublist" 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<h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">R4000</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. 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title="R4000 – Esperanto" lang="eo" hreflang="eo" data-title="R4000" data-language-autonym="Esperanto" data-language-local-name="Esperanto" class="interlanguage-link-target"><span>Esperanto</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/R4000" title="R4000 – French" lang="fr" hreflang="fr" data-title="R4000" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/R4000" title="R4000 – Hungarian" lang="hu" hreflang="hu" data-title="R4000" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/R4000" title="R4000 – Japanese" lang="ja" hreflang="ja" data-title="R4000" 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class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"><span class="mw-redirectedfrom">(Redirected from <a href="/w/index.php?title=R4400&redirect=no" class="mw-redirect" title="R4400">R4400</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">MIPS microprocessor</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:KL_Toshiba_MIPS_R4000.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/cc/KL_Toshiba_MIPS_R4000.jpg/220px-KL_Toshiba_MIPS_R4000.jpg" decoding="async" width="220" height="233" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/cc/KL_Toshiba_MIPS_R4000.jpg/330px-KL_Toshiba_MIPS_R4000.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/cc/KL_Toshiba_MIPS_R4000.jpg/440px-KL_Toshiba_MIPS_R4000.jpg 2x" data-file-width="1560" data-file-height="1650" /></a><figcaption>A Toshiba R4000 microprocessor</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Ic-photo-IDT--79R4400SC-60GS447--(R4400-CPU).JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/f6/Ic-photo-IDT--79R4400SC-60GS447--%28R4400-CPU%29.JPG/220px-Ic-photo-IDT--79R4400SC-60GS447--%28R4400-CPU%29.JPG" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/f6/Ic-photo-IDT--79R4400SC-60GS447--%28R4400-CPU%29.JPG/330px-Ic-photo-IDT--79R4400SC-60GS447--%28R4400-CPU%29.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/f6/Ic-photo-IDT--79R4400SC-60GS447--%28R4400-CPU%29.JPG/440px-Ic-photo-IDT--79R4400SC-60GS447--%28R4400-CPU%29.JPG 2x" data-file-width="1000" data-file-height="1002" /></a><figcaption>A <a href="/wiki/Integrated_Device_Technology" title="Integrated Device Technology">IDT</a> R4000 microprocessor</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:MIPS_R4000_die.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/4a/MIPS_R4000_die.JPG/220px-MIPS_R4000_die.JPG" decoding="async" width="220" height="168" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/4a/MIPS_R4000_die.JPG/330px-MIPS_R4000_die.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/4a/MIPS_R4000_die.JPG/440px-MIPS_R4000_die.JPG 2x" data-file-width="4134" data-file-height="3162" /></a><figcaption>MIPS R4000 <a href="/wiki/Die_shot" title="Die shot">die shot</a></figcaption></figure> <p>The <b>R4000</b> is a <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a> developed by <a href="/wiki/MIPS_Technologies" title="MIPS Technologies">MIPS Computer Systems</a> that implements the <a href="/wiki/MIPS_III" class="mw-redirect" title="MIPS III">MIPS III</a> <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> (ISA). Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation. In the early 1990s, when <a href="/wiki/RISC" class="mw-redirect" title="RISC">RISC</a> microprocessors were expected to replace CISC microprocessors such as the Intel <a href="/wiki/I486" title="I486">i486</a>, the R4000 was selected to be the microprocessor of the <a href="/wiki/Advanced_Computing_Environment" title="Advanced Computing Environment">Advanced Computing Environment</a> (ACE), an industry standard that intended to define a common RISC platform. ACE ultimately failed for a <a href="/wiki/Advanced_Computing_Environment#Dissolution" title="Advanced Computing Environment">number of reasons</a>, but the R4000 found success in the workstation and server markets. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Models">Models</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=1" title="Edit section: Models"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>There are three configurations of the R4000: the R4000PC, an entry-level model with no support for a secondary cache; the R4000SC, a model with secondary cache but no multiprocessor capability; and the R4000MC, a model with secondary cache and support for the cache coherency protocols required by multiprocessor systems. </p> <div class="mw-heading mw-heading2"><h2 id="Description">Description</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=2" title="Edit section: Description"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The R4000 is a <a href="/wiki/Scalar_processor" title="Scalar processor">scalar</a> <a href="/wiki/Superpipelined" class="mw-redirect" title="Superpipelined">superpipelined</a> microprocessor with an eight-stage integer pipeline. During the first stage (IF), a virtual address for an instruction is generated and the instruction <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">translation lookaside buffer</a> (TLB) begins the translation of the address to a physical address. In the second stage (IS), translation is completed and the instruction is fetched from an internal 8 KB instruction cache. The instruction cache is <a href="/wiki/CPU_cache#Associativity" title="CPU cache">direct-mapped</a> and <a href="/wiki/CPU_cache#Address_translation" title="CPU cache">virtually indexed, physically tagged</a>. It has a 16- or 32-byte line size. Architecturally, it could be expanded to 32 KB. </p><p>During the third stage (RF), the instruction is decoded and the <a href="/wiki/Register_file" title="Register file">register file</a> is read. The MIPS III defines two register files, one for the integer unit and the other for floating-point. Each register file is 64 bits wide and contained 32 entries. The integer register file has two read ports and one write port, while the floating-point register file has two read ports and two write ports. Execution begins at stage four (EX) for both integer and floating-point instructions; and is written back to the register files when completed in stage eight (WB). Results may be bypassed if possible. </p> <div class="mw-heading mw-heading3"><h3 id="Integer_execution">Integer execution</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=3" title="Edit section: Integer execution"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The R4000 has an <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">arithmetic logic unit</a> (ALU), a shifter, multiplier and divider and load aligner for executing integer instructions. The ALU consists of a 64-bit <a href="/wiki/Carry-select_adder" title="Carry-select adder">carry-select adder</a> and a logic unit and is pipelined. The shifter is a 32-bit <a href="/wiki/Barrel_shifter" title="Barrel shifter">barrel shifter</a>. It performs 64-bit shifts in two cycles, stalling the pipeline as a result. This design was chosen to save die area. The multiplier and divider are not pipelined and have significant latencies: multiplies have a 10- or 20-cycle latency for 32-bit or 64-bit integers, respectively; whereas divides have a 69- or 133-cycle latency for 32-bit or 64-bit integers, respectively. Most instructions have a single cycle latency. The ALU adder is also used for calculating virtual addresses for loads, stores and branches. </p><p>Load and store instructions are executed by the integer pipeline, and access the on-chip 8 KB data cache. </p> <div class="mw-heading mw-heading3"><h3 id="Floating-point_execution">Floating-point execution</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=4" title="Edit section: Floating-point execution"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The R4000 has an on-die <a href="/wiki/IEEE_754-1985" title="IEEE 754-1985">IEEE 754-1985</a>-compliant <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> (FPU), referred to as the R4010. The FPU is a coprocessor designated CP1<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> (the MIPS ISA defined four coprocessors, designated CP0 to CP3). The FPU can operate in two modes, 32- or 64-bit which are selected by setting a bit, the FR bit, in the CPU status register. In 32-bit mode, the 32 floating-point registers become 32 bits wide when used to hold single-precision floating-point numbers. When used to hold double-precision numbers, there are 16 floating-point registers (the registers are paired). </p><p>The FPU can operate in parallel with the ALU unless there is a data or resource dependency, which causes it to stall. It contains three sub-units: an adder, a multiplier and a divider. The multiplier and divider can execute an instruction in parallel with the adder, but they use the adder in their final stages of execution, thus imposing limits to overlapping execution. Thus, under certain conditions, it can execute up to three instructions at any time, one in each unit. The FPU is capable of retiring one instruction per cycle. </p><p>The adder and multiplier are pipelined. The multiplier has a four-stage multiplier pipeline. It is clocked at twice the clock frequency of the microprocessor for adequate performance and uses <a href="/wiki/Dynamic_logic_(digital_electronics)" title="Dynamic logic (digital electronics)">dynamic logic</a> to achieve the high clock frequency. Division has a 23- or 36-cycle latency for single- or double-precision operations and square-root has a 54- or 112-cycle latency. Division and square-root uses the <a href="/wiki/Division_algorithm#SRT_division" title="Division algorithm">SRT</a> algorithm. </p> <div class="mw-heading mw-heading3"><h3 id="Memory_management">Memory management</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=5" title="Edit section: Memory management"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <a href="/wiki/Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU) uses a 48-entry <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">translation lookaside buffer</a> to translate <a href="/wiki/Virtual_address" class="mw-redirect" title="Virtual address">virtual addresses</a>. The R4000 uses a 64-bit virtual address, but only implements 40 of the 64 bits, allowing 1 TB of <a href="/wiki/Virtual_memory" title="Virtual memory">virtual memory</a>; the remaining bits are checked to ensure that they contain zero. The R4000 uses a 36-bit <a href="/wiki/Physical_address" title="Physical address">physical address</a>, thus is able to address 64 GB of <a href="/wiki/Physical_memory" class="mw-redirect" title="Physical memory">physical memory</a>. </p> <div class="mw-heading mw-heading3"><h3 id="Secondary_cache">Secondary cache</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=6" title="Edit section: Secondary cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The R4000 (SC and MC configurations only) supports an external secondary cache with a capacity of 128 KB to 4 MB. The cache is accessed via a dedicated 128-bit data bus. The secondary cache can be configured either as a unified cache or as a split instruction and data cache. In the latter configuration, each cache can have a capacity of 128 KB to 2 MB.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> The secondary cache is <a href="/wiki/CPU_cache#Address_translation" title="CPU cache">physically indexed, physically tagged</a> and has a programmable line size of 128, 256, 512 or 1,024 bytes. The cache controller is on-die. The cache is built from standard <a href="/wiki/Static_random_access_memory" class="mw-redirect" title="Static random access memory">static random access memory</a> (SRAM). The data and tag buses are ECC-protected. </p> <div class="mw-heading mw-heading3"><h3 id="System_bus">System bus</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=7" title="Edit section: System bus"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The R4000 uses a 64-bit system bus called the SysAD bus. The SysAD bus was an address and data multiplexed bus, that is, it used the same set of wires to transfer data and addresses. While this reduces bandwidth, it is also less expensive than providing a separate address bus, which requires more pins and increases the complexity of the system. The SysAD bus can be configured to operate at half, a third or a quarter of the internal clock frequency. The SysAD bus generates its clock signal by dividing the operating frequency. </p> <div class="mw-heading mw-heading3"><h3 id="Transistor_count,_die_dimensions_and_process_details"><span id="Transistor_count.2C_die_dimensions_and_process_details"></span>Transistor count, die dimensions and process details</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=8" title="Edit section: Transistor count, die dimensions and process details"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The R4000 contains 1.2 million transistors.<sup id="cite_ref-IEEE_Micro_P:10_3-0" class="reference"><a href="#cite_note-IEEE_Micro_P:10-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> It was designed for a 1.0 μm two-layer metal <a href="/wiki/CMOS" title="CMOS">complementary metal–oxide–semiconductor</a> (CMOS) process. As MIPS was a <a href="/wiki/Fabless" class="mw-redirect" title="Fabless">fabless</a> company, the R4000 was fabricated by partners in their own processes, which had a 0.8 μm minimum feature size.<sup id="cite_ref-IEEE_Micro_P:21_4-0" class="reference"><a href="#cite_note-IEEE_Micro_P:21-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Clocking">Clocking</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=9" title="Edit section: Clocking"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The R4000 generates the various clock signals from a master clock signal generated externally. For the operating frequency, the R4000 multiplies the master clock signal by two by use of an on-die <a href="/wiki/Phase-locked_loop" title="Phase-locked loop">phase-locked loop</a> (PLL). </p> <div class="mw-heading mw-heading3"><h3 id="Packaging">Packaging</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=10" title="Edit section: Packaging"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The R4000PC is packaged in a 179-pin ceramic <a href="/wiki/Pin_grid_array" title="Pin grid array">pin grid array</a> (CPGA). The R4000SC and R4000MC are packaged in a 447-pin ceramic <a href="/wiki/Staggered_Pin_Grid_Array" class="mw-redirect" title="Staggered Pin Grid Array">staggered pin grid array</a> (SPGA). The pin out of the R4000MC is different from the R4000SC, with some pins which are unused on the R4000SC used for signals to implement <a href="/wiki/Cache_coherency" class="mw-redirect" title="Cache coherency">cache coherency</a> on the R4000MC. The pin-out of the R4000PC is similar to that of the PGA-packaged <a href="/wiki/R4200" title="R4200">R4200</a> and <a href="/wiki/R4600" title="R4600">R4600</a> microprocessors. This characteristic enables a properly designed system to use any of the three microprocessors. </p> <div class="mw-heading mw-heading2"><h2 id="R4400">R4400</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=11" title="Edit section: R4400"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Toshiba_TC86R4400MC-200_9636YJA_top.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/6e/Toshiba_TC86R4400MC-200_9636YJA_top.jpg/220px-Toshiba_TC86R4400MC-200_9636YJA_top.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/6e/Toshiba_TC86R4400MC-200_9636YJA_top.jpg/330px-Toshiba_TC86R4400MC-200_9636YJA_top.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/6e/Toshiba_TC86R4400MC-200_9636YJA_top.jpg/440px-Toshiba_TC86R4400MC-200_9636YJA_top.jpg 2x" data-file-width="798" data-file-height="798" /></a><figcaption>An example of a R4400MC microprocessor fabricated by Toshiba</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Ic-photo-LSI--L1A7710-(R4400-CPU).png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/6f/Ic-photo-LSI--L1A7710-%28R4400-CPU%29.png/220px-Ic-photo-LSI--L1A7710-%28R4400-CPU%29.png" decoding="async" width="220" height="217" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/6f/Ic-photo-LSI--L1A7710-%28R4400-CPU%29.png/330px-Ic-photo-LSI--L1A7710-%28R4400-CPU%29.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/6f/Ic-photo-LSI--L1A7710-%28R4400-CPU%29.png/440px-Ic-photo-LSI--L1A7710-%28R4400-CPU%29.png 2x" data-file-width="778" data-file-height="768" /></a><figcaption>A <a href="/wiki/LSI_Logic" class="mw-redirect" title="LSI Logic">LSI Logic</a> R4400 microprocessor</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:NEC_VR4400_die.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/23/NEC_VR4400_die.JPG/220px-NEC_VR4400_die.JPG" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/23/NEC_VR4400_die.JPG/330px-NEC_VR4400_die.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/23/NEC_VR4400_die.JPG/440px-NEC_VR4400_die.JPG 2x" data-file-width="3782" data-file-height="2838" /></a><figcaption>NEC VR4400MC die shot</figcaption></figure> <p>The <b>R4400</b> is a further development of the R4000. It was announced in early November 1992. Samples of the microprocessor had been shipped to selected customers before then, with general availability in January 1993. The R4400 operates at clock frequencies of 100, 133, 150, 200, and 250 MHz. The only major improvement from the R4000 is larger primary caches, which were doubled in capacity to 16 KB each from 8 KB each. It contained 2.3 million transistors. </p><p>The R4400 was licensed by <a href="/wiki/Integrated_Device_Technology" title="Integrated Device Technology">Integrated Device Technology</a> (IDT), <a href="/wiki/LSI_Logic" class="mw-redirect" title="LSI Logic">LSI Logic</a>, <a href="/wiki/NEC" title="NEC">NEC</a>, Performance Semiconductor, <a href="/wiki/Siemens_AG" class="mw-redirect" title="Siemens AG">Siemens AG</a> and <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a>. IDT, NEC, Siemens and Toshiba fabricated and marketed the microprocessor. LSI Logic used the R4400 in custom products. Performance Semiconductor sold their logic division to <a href="/wiki/Cypress_Semiconductor" title="Cypress Semiconductor">Cypress Semiconductor</a> where the MIPS microprocessor products were discontinued. </p><p>NEC marketed their version as the VR4400. The first version, a 150 MHz part, was announced in November 1992. Early versions were fabricated in a 0.6 μm process.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> In mid-1995, a 250 MHz part began sampling. It was fabricated in a 0.35 μm four-layer-metal process.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> NEC also produced the MR4401, a ceramic <a href="/wiki/Multi-chip_module" title="Multi-chip module">multi-chip module</a> (MCM) that contained a VR4400SC with ten 1 Mbit SRAM chips that implemented a 1 MB secondary cache. The MCM was pin-compatible with the R4x00PC. The first version, a 150 MHz part, was announced in 1994. In 1995, a 200 MHz part was announced. </p><p>Toshiba marketed their version as the TC86R4400. A 200 MHz part containing 2.3 million transistors and measuring 134 mm<sup>2</sup> fabricated in a 0.3 μm process was introduced in mid-1994. The R4400PC was priced at <span style="white-space: nowrap">$1,600</span>, the R4400SC at <span style="white-space: nowrap">$1,950</span>, and the R4400MC at <span style="white-space: nowrap">$2,150</span> in quantities of 10,000.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Usage">Usage</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=12" title="Edit section: Usage"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The R4400 is used by: </p> <ul><li>Carrera Computers in their <a href="/wiki/Windows_NT" title="Windows NT">Windows NT</a> personal computers and workstations<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Concurrent_Computer_Corporation" title="Concurrent Computer Corporation">Concurrent Computer Corporation</a> in their real-time multiprocessor Maxion systems<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/DeskStation_Technology" title="DeskStation Technology">DeskStation Technology</a> in their Windows NT personal computers and <a href="/wiki/DeskStation_Tyne" class="mw-redirect" title="DeskStation Tyne">DeskStation Tyne</a> workstation<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Digital_Equipment_Corporation" title="Digital Equipment Corporation">Digital Equipment Corporation</a> in their <a href="/wiki/DECstation" title="DECstation">DECstation</a> 5000/260 workstation and server</li> <li><a href="/wiki/NEC" title="NEC">NEC Corporation</a> in their <a href="/wiki/NEC_RISCstation" title="NEC RISCstation">RISCstation</a> workstations, RISCserver servers, and Cenju-3 supercomputer<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup></li> <li>NeTPower in their Windows NT workstations and servers</li> <li><a href="/wiki/Pyramid_Technology" title="Pyramid Technology">Pyramid Technology</a> used the R4400MC in their Nile Series servers<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Siemens_Nixdorf_Informationssysteme" class="mw-redirect" title="Siemens Nixdorf Informationssysteme">Siemens Nixdorf Informationssysteme</a> (SNI) in their RM-series <a href="/wiki/Unix" title="Unix">UNIX</a> servers and SR2000 <a href="/wiki/Mainframe_computer" title="Mainframe computer">mainframe</a></li> <li><a href="/wiki/Silicon_Graphics" title="Silicon Graphics">Silicon Graphics</a> in their <a href="/wiki/SGI_Onyx" title="SGI Onyx">Onyx</a>, <a href="/wiki/SGI_Indigo" title="SGI Indigo">Indigo</a>, <a href="/wiki/SGI_Indigo%C2%B2_and_Challenge_M" title="SGI Indigo² and Challenge M">Indigo2</a>, and <a href="/wiki/SGI_Indy" title="SGI Indy">Indy</a> workstations; and in their <a href="/wiki/SGI_Challenge" title="SGI Challenge">Challenge</a> server</li> <li><a href="/wiki/Tandem_Computers" title="Tandem Computers">Tandem Computers</a> in their <a href="/wiki/NonStop_(server_computers)" title="NonStop (server computers)">NonStop Himalaya</a> fault-tolerant servers</li></ul> <div class="mw-heading mw-heading2"><h2 id="Chipsets">Chipsets</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=13" title="Edit section: Chipsets"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The R4000 and R4400 microprocessors were interfaced to the system by custom ASICs or by commercially available chipsets. System vendors such as SGI developed their own ASICs for their systems. Commercial chipsets were developed, fabricated and marketed by companies such as Toshiba with their the Tiger Shark chipset, which provided a <a href="/wiki/I486" title="I486">i486</a>-compatible bus.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=14" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><i>MIPS R4000 Microprocessor User's Manual, Second Edition</i>, p. 152</span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text">Heinrich, "MIPS R4000 Microprocessor User's Manual", p. 248</span> </li> <li id="cite_note-IEEE_Micro_P:10-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-IEEE_Micro_P:10_3-0">^</a></b></span> <span class="reference-text"><a href="#IEEE_Micro">Mirapuri, "The Mips R4000 Processor"</a>, p. 10</span> </li> <li id="cite_note-IEEE_Micro_P:21-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-IEEE_Micro_P:21_4-0">^</a></b></span> <span class="reference-text"><a href="#IEEE_Micro">Mirapuri, "The Mips R4000 Processor"</a>, p. 21</span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text">"NEC VR4400 Clock-Doubling RISC Has 2m Transistors"</span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text">"NEC Ready With 250MHz Version Of The 64-Bit MIPS R4400 RISC"</span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text">"Toshiba Has 200MHz MIPS R4400"</span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text">"...And From Carrera Computers"</span> </li> <li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text">"Concurrent Multiprocessors Feature New Bus Architecture"</span> </li> <li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text">"MIPS R-Based Windows NT Personal Computers From Deskstation..."</span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text">"NEC Goes After The Business Market With Its Latest Line Of RISC UNIX Workstations"</span> </li> <li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text">"Pyramid Technology Aims To Crash The Mainframe With Nile Series"</span> </li> <li id="cite_note-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-13">^</a></b></span> <span class="reference-text">"Toshiba Samples 80486-Bus Chip Set For R-Series".</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=R4000&action=edit&section=15" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Heinrich, Joe. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110607074823/http://techpubs.sgi.com/library/manuals/2000/007-2489-001/pdf/007-2489-001.pdf"><i>MIPS R4000 Microprocessor User's Manual</i></a>, Second Edition.</li> <li><cite id="IEEE_Micro">Sunil Mirapuri, Michael Woodacre, Nader Vasseghi, "The Mips R4000 Processor," <i><a href="/wiki/IEEE_Micro" title="IEEE Micro">IEEE Micro</a></i>, vol. 12. no. 2, pp. 10–22, March/April 1992</cite></li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output 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id="MIPS_microprocessors" style="font-size:114%;margin:0 4em">MIPS microprocessors</div></th></tr><tr><td class="navbox-abovebelow" colspan="2"><div> <ul><li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS architecture</a></li> <li><a href="/wiki/MIPS_architecture_processors" title="MIPS architecture processors">MIPS architecture processors</a></li> <li><a href="/wiki/List_of_MIPS_architecture_processors" title="List of MIPS architecture processors">List of MIPS architecture processors</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">General<br />processors</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="MIPS64compatible" scope="row" class="navbox-group" style="width:1%">MIPS64<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson#Loongson_3_Series" title="Loongson">Loongson 3 Series</a> <ul><li>LS3A1000/LS3A1000-I(LS3A1000-i)</li> <li>LS3A2000/LS3A1500-I</li> <li>LS3A3000/LS3A3000-I(LS3A3000-i)</li> <li>LS3A4000/LS3A4000-I(LS3A4000-i)</li> <li>LS3B1000</li> <li>LS3B1500</li> <li>LS3B2000</li> <li>LS3B3000</li> <li>LS3B4000</li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Application<br />processors</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">MIPS32<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Ingenic_Semiconductor" title="Ingenic Semiconductor">Ingenic XBurst</a> <ul><li>JZ4720 <ul><li><a href="/wiki/Ben_NanoNote" title="Ben NanoNote">Ben NanoNote</a></li></ul></li> <li>JZ4730 (<a href="/wiki/Skytone_Alpha-400" title="Skytone Alpha-400">Skytone Alpha-400</a>)</li> <li>JZ4740 (<a href="/wiki/Dingoo_A320" class="mw-redirect" title="Dingoo A320">Dingoo A320</a>)</li> <li>JZ4750 (<a href="/wiki/Game_Gadget" title="Game Gadget">Game Gadget</a>)</li> <li>JZ4760 <ul><li>Velocity Micro T103 Cruz</li> <li>Velocity Micro T301 Cruz</li></ul></li> <li>JZ4770 <ul><li><a href="/wiki/NOVO7" title="NOVO7">Ainol Novo7 Paladin</a></li> <li>NEOGEO-X</li> <li>GCW-Zero</li></ul></li> <li>JZ4780</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">MIPS64<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson#Loongson_2_Series" title="Loongson">Loongson 2 Series</a> <ul><li>LS2H</li> <li>LS2K1000/LS2K2000</li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Microcontroller" title="Microcontroller">Microcontrollers</a><br />(embedded device)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">M4K</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a> <a href="/wiki/PIC_microcontrollers#PIC32MX" title="PIC microcontrollers">PIC32MX</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">4Kc/4KEc</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>ATI/AMD/Broadcom <a href="/wiki/Xilleon" title="Xilleon">Xilleon</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">MIPS32<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson#Loongson_1_Series" title="Loongson">Loongson 1 Series</a> <ul><li>LS1A0300</li> <li>LS1B</li> <li>LS1C300</li> <li>LS1C101</li> <li>LS1D</li> <li>LS1G</li> <li>LS1H</li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Networking</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">4Kc/4KEc</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Qualcomm_Atheros" title="Qualcomm Atheros">Qualcomm Atheros</a> <ul><li>AR2313</li> <li>AR2318</li></ul></li> <li><a href="/wiki/MediaTek" title="MediaTek">MediaTek</a> <ul><li>RT2880</li></ul></li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a>/Infineon/Lantiq <ul><li>AR7</li></ul></li> <li><a href="/wiki/Lantiq" title="Lantiq">Lantiq</a> <ul><li>AMAZON</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">5Kc</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Marvell_Technology_Group" class="mw-redirect" title="Marvell Technology Group">Marvell</a> <ul><li>88E6318 "Link Street"</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">24Kc/24KEc</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Qualcomm_Atheros" title="Qualcomm Atheros">Qualcomm Atheros</a> <ul><li>AR7240</li> <li>AR7161</li> <li>AR9132</li> <li>AR9331</li></ul></li> <li><a href="/wiki/MediaTek" title="MediaTek">MediaTek</a> <ul><li>RT3050</li> <li>RT3052</li> <li>RT3350</li> <li>RT5350</li> <li>RT6856</li> <li>MT7620</li> <li>MT7628</li> <li>MT7688</li></ul></li> <li><a href="/wiki/Lantiq" title="Lantiq">Lantiq</a> <ul><li>DANUBE</li> <li>VINAX</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">34Kc</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Lantiq" title="Lantiq">Lantiq</a> <ul><li>AR188</li> <li>VRX288</li> <li>GRX388</li></ul></li> <li><a href="/wiki/Ikanos_Communications" title="Ikanos Communications">Ikanos</a> <ul><li>Fusiv Vx175/173</li> <li>Fusiv Vx180</li> <li>Fusiv Vx185/183</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">74Kc</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Qualcomm_Atheros" title="Qualcomm Atheros">Qualcomm Atheros</a> <ul><li>AR9344</li> <li>QCA9558</li></ul></li> <li><a href="/wiki/MediaTek" title="MediaTek">MediaTek</a> <ul><li>RT3662</li> <li>RT3883</li></ul></li> <li><a href="/wiki/Broadcom_Corporation" title="Broadcom Corporation">Broadcom</a> <ul><li>BCM4706</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">1004Kc</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/MediaTek" title="MediaTek">MediaTek</a> <ul><li>MT7621</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">1074Kc</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Realtek" title="Realtek">Realtek</a> <ul><li>RTL8198C</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">MIPS32<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Broadcom_Corporation" title="Broadcom Corporation">Broadcom</a> <ul><li>various</li></ul></li> <li><a href="/wiki/Cavium" title="Cavium">Cavium</a> <ul><li>various</li></ul></li> <li>Alchemy Semiconductor <ul><li><a href="/wiki/Alchemy_(processor)" title="Alchemy (processor)">Alchemy</a></li></ul></li> <li><a href="/wiki/RMI_Corporation" title="RMI Corporation">RMI Corporation</a> <ul><li>XLR</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">MIPS64<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Broadcom_Corporation" title="Broadcom Corporation">Broadcom</a> <ul><li>various</li></ul></li> <li><a href="/wiki/Cavium" title="Cavium">Cavium</a> <ul><li>Octeon</li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Gaming</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="various" scope="row" class="navbox-group" style="width:1%">various</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/PlayStation_(console)" title="PlayStation (console)">PlayStation 1</a> MIPS R3000A-compatible</li> <li><a href="/wiki/Nintendo_64" title="Nintendo 64">Nintendo 64</a> NEC VR4300</li> <li><a href="/wiki/PlayStation_Portable" title="PlayStation Portable">PlayStation Portable</a> R4000-based</li> <li><a href="/wiki/PlayStation_2" title="PlayStation 2">PlayStation 2</a> <a href="/wiki/Emotion_Engine" title="Emotion Engine">Emotion Engine</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Supercomputer" title="Supercomputer">Supercomputer</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="MIPS64compatible" scope="row" class="navbox-group" style="width:1%">MIPS64<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson" title="Loongson">Loongson-based systems</a> <ul><li>LS2F/LS2F1000</li> <li>LS3A1000</li> <li>LS3B1000</li></ul></li> <li><a href="/wiki/SiCortex" title="SiCortex">SiCortex</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Aerospace</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">MIPS64<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson#Loongson_1_Series" title="Loongson">Loongson 1 Series</a> <ul><li>LS1E0300/LS1E1000</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">MIPS32<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson#Loongson_1_Series" title="Loongson">Loongson 1 Series</a> <ul><li>LS1E04</li> <li>LS1F04/LS1F0300</li> <li>LS1J</li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Classic<br />processors</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS I</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/R2000_(microprocessor)" class="mw-redirect" title="R2000 (microprocessor)">R2000</a></li> <li><a href="/wiki/R3000" title="R3000">R3000</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/MIPS_II" class="mw-redirect" title="MIPS II">MIPS II</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/R6000" title="R6000">R6000</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/MIPS_III" class="mw-redirect" title="MIPS III">MIPS III</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a class="mw-selflink selflink">R4000</a> <ul><li><a class="mw-selflink-fragment" href="#R4400">R4400</a></li></ul></li> <li><a href="/wiki/R4200" title="R4200">R4200</a> <ul><li><a href="/wiki/R4200#R4300i" title="R4200">R4300i</a></li></ul></li> <li><a href="/wiki/R4600" title="R4600">R4600</a> <ul><li><a href="/wiki/R4600#R4700" title="R4600">R4700</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/MIPS_IV" class="mw-redirect" title="MIPS IV">MIPS IV</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/R5000" title="R5000">R5000</a></li> <li><a href="/wiki/R8000" title="R8000">R8000</a></li> <li><a href="/wiki/R10000" title="R10000">R10000</a> <ul><li><a href="/wiki/R10000#R12000" title="R10000">R12000</a></li> <li><a href="/wiki/R10000#R12000A" title="R10000">R12000A</a></li> <li><a href="/wiki/R10000#R14000" title="R10000">R14000</a></li> <li><a href="/wiki/R10000#R14000A" title="R10000">R14000A</a></li> <li><a href="/wiki/R10000#R16000" title="R10000">R16000</a></li> <li><a href="/wiki/R10000#R16000A" title="R10000">R16000A</a></li> <li><a href="/wiki/R10000#R18000" title="R10000">R18000</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/MIPS_V" class="mw-redirect" title="MIPS V">MIPS V</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><i><a href="/wiki/MIPS_Technologies#History" title="MIPS Technologies">H1 "Beast"</a></i></li> <li><i><a href="/wiki/MIPS_Technologies#History" title="MIPS Technologies">H2 "Capitan"</a></i></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox authority-control" aria-label="Navbox" style="padding:3px"><table class="nowraplinks hlist navbox-inner" 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