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href="#Special_function_registers"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Special function registers</span> </div> </a> <ul id="toc-Special_function_registers-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Register_windows" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Register_windows"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Register windows</span> </div> </a> <ul id="toc-Register_windows-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Bit_registers" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Bit_registers"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4</span> <span>Bit registers</span> </div> </a> <ul id="toc-Bit_registers-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Program_memory" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Program_memory"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.5</span> <span>Program memory</span> </div> </a> <ul id="toc-Program_memory-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_data_memory" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#External_data_memory"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.6</span> <span>External data memory</span> </div> </a> <ul id="toc-External_data_memory-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Registers" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Registers"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Registers</span> </div> </a> <ul id="toc-Registers-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Microarchitecture" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Microarchitecture</span> </div> </a> <ul id="toc-Microarchitecture-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Instruction_set" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Instruction_set"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Instruction set</span> </div> </a> <ul id="toc-Instruction_set-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Programming" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Programming"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Programming</span> </div> </a> <ul id="toc-Programming-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Related_processors" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Related_processors"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Related processors</span> </div> </a> <button aria-controls="toc-Related_processors-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Related processors subsection</span> </button> <ul id="toc-Related_processors-sublist" class="vector-toc-list"> <li id="toc-Derivative_vendors" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Derivative_vendors"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1</span> <span>Derivative vendors</span> </div> </a> <ul id="toc-Derivative_vendors-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Use_as_intellectual_property" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Use_as_intellectual_property"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>Use as intellectual property</span> </div> </a> <ul id="toc-Use_as_intellectual_property-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-MCUs_based_on_8051" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#MCUs_based_on_8051"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>MCUs based on 8051</span> </div> </a> <ul id="toc-MCUs_based_on_8051-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Digital_signal_processor_(DSP)_variants" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Digital_signal_processor_(DSP)_variants"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>Digital signal processor (DSP) variants</span> </div> </a> <ul id="toc-Digital_signal_processor_(DSP)_variants-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Enhanced_8-bit_binary_compatible_microcontroller:_MCS-151_family" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Enhanced_8-bit_binary_compatible_microcontroller:_MCS-151_family"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>Enhanced 8-bit binary compatible microcontroller: MCS-151 family</span> </div> </a> <ul id="toc-Enhanced_8-bit_binary_compatible_microcontroller:_MCS-151_family-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-8/16/32-bit_binary_compatible_microcontroller:_MCS-251_family" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#8/16/32-bit_binary_compatible_microcontroller:_MCS-251_family"> <div class="vector-toc-text"> <span class="vector-toc-numb">13</span> <span>8/16/32-bit binary compatible microcontroller: MCS-251 family</span> </div> </a> <ul id="toc-8/16/32-bit_binary_compatible_microcontroller:_MCS-251_family-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">14</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">15</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">16</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">17</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" title="Table of Contents" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" 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Available in 32 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-32" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">32 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%A5%D9%86%D8%AA%D9%84_MCS-51" title="إنتل MCS-51 – Arabic" lang="ar" hreflang="ar" data-title="إنتل MCS-51" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Catalan" lang="ca" hreflang="ca" data-title="Intel 8051" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/MCS-51" title="MCS-51 – Czech" lang="cs" hreflang="cs" data-title="MCS-51" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Intel_MCS-51" title="Intel MCS-51 – German" lang="de" hreflang="de" data-title="Intel MCS-51" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Estonian" lang="et" hreflang="et" data-title="Intel 8051" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-el mw-list-item"><a href="https://el.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Greek" lang="el" hreflang="el" data-title="Intel 8051" data-language-autonym="Ελληνικά" data-language-local-name="Greek" class="interlanguage-link-target"><span>Ελληνικά</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Spanish" lang="es" hreflang="es" data-title="Intel 8051" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eu mw-list-item"><a href="https://eu.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Basque" lang="eu" hreflang="eu" data-title="Intel 8051" data-language-autonym="Euskara" data-language-local-name="Basque" class="interlanguage-link-target"><span>Euskara</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%A7%DB%8C%D9%86%D8%AA%D9%84_%D8%A7%D9%85%E2%80%8C%D8%B3%DB%8C%E2%80%8C%D8%A7%D8%B3-%DB%B5%DB%B1" title="اینتل ام‌سی‌اس-۵۱ – Persian" lang="fa" hreflang="fa" data-title="اینتل ام‌سی‌اس-۵۱" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – French" lang="fr" hreflang="fr" data-title="Intel 8051" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-gl mw-list-item"><a href="https://gl.wikipedia.org/wiki/Intel_MCS-51" title="Intel MCS-51 – Galician" lang="gl" hreflang="gl" data-title="Intel MCS-51" data-language-autonym="Galego" data-language-local-name="Galician" class="interlanguage-link-target"><span>Galego</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%9D%B8%ED%85%94_8051" title="인텔 8051 – Korean" lang="ko" hreflang="ko" data-title="인텔 8051" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Indonesian" lang="id" hreflang="id" data-title="Intel 8051" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Italian" lang="it" hreflang="it" data-title="Intel 8051" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/%D7%9E%D7%99%D7%A7%D7%A8%D7%95-%D7%91%D7%A7%D7%A8_8051" title="מיקרו-בקר 8051 – Hebrew" lang="he" hreflang="he" data-title="מיקרו-בקר 8051" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/Intel_MCS-51" title="Intel MCS-51 – Hungarian" lang="hu" hreflang="hu" data-title="Intel MCS-51" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%87%E0%B4%A8%E0%B5%8D%E0%B4%B1%E0%B5%BD_8051" title="ഇന്റൽ 8051 – Malayalam" lang="ml" hreflang="ml" data-title="ഇന്റൽ 8051" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/8051-microcontroller" title="8051-microcontroller – Dutch" lang="nl" hreflang="nl" data-title="8051-microcontroller" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Japanese" lang="ja" hreflang="ja" data-title="Intel 8051" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Polish" lang="pl" hreflang="pl" data-title="Intel 8051" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Portuguese" lang="pt" hreflang="pt" data-title="Intel 8051" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Intel_MCS-51" title="Intel MCS-51 – Romanian" lang="ro" hreflang="ro" data-title="Intel MCS-51" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Russian" lang="ru" hreflang="ru" data-title="Intel 8051" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sq mw-list-item"><a href="https://sq.wikipedia.org/wiki/Mikrokontrolleri_8051" title="Mikrokontrolleri 8051 – Albanian" lang="sq" hreflang="sq" data-title="Mikrokontrolleri 8051" data-language-autonym="Shqip" data-language-local-name="Albanian" class="interlanguage-link-target"><span>Shqip</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/MCS-51" title="MCS-51 – Slovak" lang="sk" hreflang="sk" data-title="MCS-51" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Serbian" lang="sr" hreflang="sr" data-title="Intel 8051" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/Intel_8051" title="Intel 8051 – Swedish" lang="sv" hreflang="sv" data-title="Intel 8051" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/%E0%B8%AD%E0%B8%B4%E0%B8%99%E0%B9%80%E0%B8%97%E0%B8%A5_8051" title="อินเทล 8051 – Thai" lang="th" hreflang="th" data-title="อินเทล 8051" data-language-autonym="ไทย" data-language-local-name="Thai" class="interlanguage-link-target"><span>ไทย</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/8051" title="8051 – Turkish" lang="tr" hreflang="tr" data-title="8051" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/Intel_MCS-51" title="Intel MCS-51 – Ukrainian" lang="uk" hreflang="uk" data-title="Intel MCS-51" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/Intel_MCS-51" title="Intel MCS-51 – Vietnamese" lang="vi" hreflang="vi" data-title="Intel MCS-51" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/%E8%8B%B1%E7%89%B9%E7%88%BE8051" title="英特爾8051 – Chinese" lang="zh" hreflang="zh" data-title="英特爾8051" data-language-autonym="中文" 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href="/w/index.php?title=Intel_8051&redirect=no" class="mw-redirect" title="Intel 8051">Intel 8051</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Single chip microcontroller series by Intel</div> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">Intel 8051</caption><tbody><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:KL_Intel_P8051.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/f0/KL_Intel_P8051.jpg/220px-KL_Intel_P8051.jpg" decoding="async" width="220" height="134" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/f0/KL_Intel_P8051.jpg/330px-KL_Intel_P8051.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/f0/KL_Intel_P8051.jpg/440px-KL_Intel_P8051.jpg 2x" data-file-width="1386" data-file-height="846" /></a></span><div class="infobox-caption">Intel P8051 <a href="/wiki/Microcontroller" title="Microcontroller">microcontroller</a></div></td></tr><tr><th colspan="2" class="infobox-header">History</th></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="/wiki/Intel_MCS-48" title="Intel MCS-48">Intel MCS-48</a></td></tr><tr><th scope="row" class="infobox-label">Successor</th><td class="infobox-data">Intel MCS-151</td></tr></tbody></table> <p>The <b>Intel MCS-51</b> (commonly termed <b>8051</b>) is a single-chip <a href="/wiki/Microcontroller" title="Microcontroller">microcontroller</a> (MCU) series developed by <a href="/wiki/Intel" title="Intel">Intel</a> in 1980 for use in <a href="/wiki/Embedded_system" title="Embedded system">embedded systems</a>. The architect of the Intel MCS-51 instruction set was <a href="/wiki/John_H._Wharton" class="mw-redirect" title="John H. Wharton">John H. Wharton</a>.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Intel8051OralHistory_2-0" class="reference"><a href="#cite_note-Intel8051OralHistory-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> Intel's original versions were popular in the 1980s and early 1990s, and enhanced <a href="/wiki/Binary_compatible" class="mw-redirect" title="Binary compatible">binary compatible</a> derivatives remain popular today. It is a <a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">complex instruction set computer</a> with separate memory spaces for program instructions and data. </p><p>Intel's original MCS-51 family was developed using N-type metal–oxide–semiconductor (<a href="/wiki/NMOS_logic" title="NMOS logic">NMOS</a>) technology, like its predecessor <a href="/wiki/Intel_MCS-48" title="Intel MCS-48">Intel MCS-48</a>, but later versions, identified by a letter C in their name (e.g., 80C51) use complementary metal–oxide–semiconductor (<a href="/wiki/CMOS" title="CMOS">CMOS</a>) technology and consume less power than their NMOS predecessors. This made them more suitable for battery-powered devices. </p><p>The family was continued in 1996 with the enhanced <a href="/wiki/8-bit" class="mw-redirect" title="8-bit">8-bit</a> MCS-151 and the 8/<a href="/wiki/16-bit" class="mw-redirect" title="16-bit">16</a>/<a href="/wiki/32-bit" class="mw-redirect" title="32-bit">32-bit</a> MCS-251 family of binary compatible microcontrollers.<sup id="cite_ref-1+2-51_3-0" class="reference"><a href="#cite_note-1+2-51-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> While Intel no longer manufactures the MCS-51, MCS-151 and MCS-251 family, enhanced <a href="/wiki/Binary_compatible" class="mw-redirect" title="Binary compatible">binary compatible</a> derivatives made by numerous vendors remain popular today. Some derivatives integrate a <a href="/wiki/Digital_signal_processor" title="Digital signal processor">digital signal processor</a> (DSP) or a <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> (coprocessor, FPU). Beyond these physical devices, several companies also offer MCS-51 derivatives as <a href="/wiki/IP_core" class="mw-redirect" title="IP core">IP cores</a> for use in <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate array</a> (FPGA) or <a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuit</a> (ASIC) designs. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Important_features_and_applications">Important features and applications</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=1" title="Edit section: Important features and applications"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_8051_arch.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/cd/Intel_8051_arch.svg/250px-Intel_8051_arch.svg.png" decoding="async" width="220" height="242" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/cd/Intel_8051_arch.svg/330px-Intel_8051_arch.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/cd/Intel_8051_arch.svg/500px-Intel_8051_arch.svg.png 2x" data-file-width="1273" data-file-height="1400" /></a><figcaption>i8051 microarchitecture</figcaption></figure> <p>The 8051 architecture provides many functions (<a href="/wiki/Central_processing_unit" title="Central processing unit">central processing unit</a> (CPU), <a href="/wiki/Random-access_memory" title="Random-access memory">random-access memory</a> (RAM), <a href="/wiki/Read-only_memory" title="Read-only memory">read-only memory</a> (ROM), <a href="/wiki/Input/output" title="Input/output">input/output</a> (I/O) ports, serial port, <a href="/wiki/Interrupt" title="Interrupt">interrupt</a> control, <a href="/wiki/Timer" title="Timer">timers</a>) in one <a href="/wiki/Integrated_circuit_packaging" title="Integrated circuit packaging">package</a>: </p> <ul><li>8-<a href="/wiki/Bit" title="Bit">bit</a> <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">arithmetic logic unit</a> (ALU) and <a href="/wiki/Accumulator_(computing)" title="Accumulator (computing)">accumulator</a>, 8-bit <a href="/wiki/Processor_register" title="Processor register">registers</a> (one <a href="/wiki/16-bit" class="mw-redirect" title="16-bit">16-bit</a> register with special <a href="/wiki/Instruction_set#Data_handling_and_memory_operations" class="mw-redirect" title="Instruction set">move instructions</a>), 8-bit <a href="/wiki/Data_bus" class="mw-redirect" title="Data bus">data bus</a> and 2 × 16-bit <a href="/wiki/Address_bus" class="mw-redirect" title="Address bus">address buses</a>, <a href="/wiki/Program_counter" title="Program counter">program counter</a>, <a href="/wiki/Data_pointer" class="mw-redirect" title="Data pointer">data pointer</a>, and related 8/11/16-bit operations; hence it is mainly an 8-bit <a href="/wiki/Microcontroller" title="Microcontroller">microcontroller</a></li> <li><a href="/wiki/Boolean_data_type" title="Boolean data type">Boolean</a> processor with 17 instructions, 1-bit accumulator, 32 registers (4 × 8-bit, bit-addressable) and up to 144 special 1 bit-addressable RAM variables (18 × 8-bit)<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Binary_multiplier" title="Binary multiplier">Multiply</a>, divide and <a href="/wiki/Relational_operator" title="Relational operator">compare</a> instructions</li> <li>Four fast <a href="/wiki/Bank_switching" title="Bank switching">switchable register banks</a> with 8 registers each (memory-mapped)</li> <li>Fast interrupt with optional register bank switching</li> <li><a href="/wiki/Interrupt" title="Interrupt">Interrupts</a> and <a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> with selectable priority<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup></li> <li>128 or 256 <a href="/wiki/Byte" title="Byte">bytes</a> of on-chip RAM (IRAM)</li> <li>Dual 16-bit <a href="/wiki/Address_bus" class="mw-redirect" title="Address bus">address bus</a>; it can access 2 × 2<sup>16</sup> memory locations: 64 <a href="/wiki/Kilobyte" title="Kilobyte">KB</a> (65,536 locations) each of ROM (PMEM) and external RAM (XRAM), using two memory buses in a <a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard architecture</a>.</li> <li>On-chip ROM (not included on 803x variants)</li> <li>Four (three full) 8-<a href="/wiki/Bit" title="Bit">bit</a> bidirectional <a href="/wiki/Input/output" title="Input/output">input/output</a> ports, bit-addressable</li> <li>UART (<a href="/wiki/Serial_port" title="Serial port">serial port</a>)</li> <li>Two 16-bit counters/<a href="/wiki/Timer" title="Timer">timers</a></li> <li><a href="/wiki/Power_management" title="Power management">Power-saving</a> mode (on some derivatives)</li></ul> <p>One feature of the 8051 core is the inclusion of a Boolean processing engine, which allows <a href="/wiki/Bit" title="Bit">bit</a>-level <a href="/wiki/Boolean_logic" class="mw-redirect" title="Boolean logic">Boolean logic</a> operations to be carried out directly and efficiently on select internal <a href="/wiki/Processor_register" title="Processor register">registers</a>, ports and select <a href="/wiki/RAM" class="mw-redirect" title="RAM">RAM</a> locations. Another feature is the inclusion of four <a href="/wiki/Bank_switching" title="Bank switching">bank-selectable</a> working register sets, which greatly reduce the time required to perform the <a href="/wiki/Context_switch" title="Context switch">context switches</a> to enter and leave <a href="/wiki/Interrupt_service_routine" class="mw-redirect" title="Interrupt service routine">interrupt service routines</a>. With one instruction, the 8051 can switch register banks, avoiding the time-consuming task of transferring the critical registers to RAM. </p><p>Once a UART, and a timer if necessary, has been configured, the programmer needs only write a simple interrupt routine to refill the <i>send</i> shift register whenever the last bit is shifted out by the UART and/or empty the full <i>receive</i> shift register (copy the data somewhere else). The main program then performs serial reads and writes simply by reading and writing 8-bit data to stacks. </p> <div class="mw-heading mw-heading3"><h3 id="Derivative_features">Derivative features</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=2" title="Edit section: Derivative features"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>As of 2013<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=Intel_MCS-51&action=edit">[update]</a></sup>, new derivatives are still being developed by many major chipmakers, and major compiler suppliers such as <a href="/wiki/IAR_Systems" title="IAR Systems">IAR Systems</a>, <a href="/wiki/Keil_(company)" title="Keil (company)">Keil</a> and <a href="/wiki/TASKING" title="TASKING">TASKING</a><sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> continuously release updates. </p><p>MCS-51-based microcontrollers typically include one or two <a href="/wiki/UART" class="mw-redirect" title="UART">UARTs</a>, two or three timers, 128 or 256 bytes of internal data <a href="/wiki/RAM" class="mw-redirect" title="RAM">RAM</a> (16 bytes of which are bit-addressable), up to 128 bytes of <a href="/wiki/I/O" class="mw-redirect" title="I/O">I/O</a>, 512 bytes to 64 KB of internal program memory, and sometimes a quantity of extended data RAM (ERAM) located in the external data space. External RAM and ROM share the data and address buses. The original 8051 core ran at 12 clock cycles per machine cycle, with most instructions executing in one or two machine cycles. With a 12 MHz <a href="/wiki/Clock_frequency" class="mw-redirect" title="Clock frequency">clock frequency</a>, the 8051 could thus execute 1 million one-cycle instructions per second or 500,000 two-cycle instructions per second. Enhanced 8051 cores are now commonly used which run at six, four, two, or even one clock per machine cycle (denoted "1T") and have clock frequencies of up to 100 MHz, thus being capable of an even greater number of instructions per second. All <a href="/wiki/Silicon_Labs" title="Silicon Labs">Silicon Labs</a>, some <a href="/wiki/Dallas_Semiconductor" title="Dallas Semiconductor">Dallas</a> (now part of <a href="/wiki/Maxim_Integrated" title="Maxim Integrated">Maxim Integrated</a>) and a few <a href="/wiki/Atmel" title="Atmel">Atmel</a> (now part of <a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip</a>) devices have <a href="/wiki/Single-cycle_processor" title="Single-cycle processor">single-cycle cores</a>.<sup id="cite_ref-:0_7-0" class="reference"><a href="#cite_note-:0-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:1_9-0" class="reference"><a href="#cite_note-:1-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p><p>8051 variants may include built-in reset timers with <a href="/wiki/Brownout_(electricity)#Digital_systems" title="Brownout (electricity)">brown-out</a> detection, on-chip oscillators, self-programmable <a href="/wiki/Flash_ROM" class="mw-redirect" title="Flash ROM">flash ROM</a> program memory, built-in external RAM, extra internal program storage, <a href="/wiki/Bootloader" title="Bootloader">bootloader</a> code in ROM, <a href="/wiki/EEPROM" title="EEPROM">EEPROM</a> non-volatile data storage, <a href="/wiki/I2C" class="mw-redirect" title="I2C">I<sup>2</sup>C</a>, <a href="/wiki/Serial_Peripheral_Interface" title="Serial Peripheral Interface">SPI</a>, and <a href="/wiki/USB" title="USB">USB</a> host interfaces, <a href="/wiki/Controller%E2%80%93area_network" class="mw-redirect" title="Controller–area network">CAN</a> or <a href="/wiki/Local_Interconnect_Network" title="Local Interconnect Network">LIN</a> bus, <a href="/wiki/Zigbee" title="Zigbee">Zigbee</a> or <a href="/wiki/Bluetooth" title="Bluetooth">Bluetooth</a> radio modules, <a href="/wiki/Pulse-width_modulation" title="Pulse-width modulation">PWM</a> generators, analog <a href="/wiki/Comparator" title="Comparator">comparators</a>, <a href="/wiki/Analog-to-digital" class="mw-redirect" title="Analog-to-digital">analog-to-digital</a> and <a href="/wiki/Digital-to-analog_converter" title="Digital-to-analog converter">digital-to-analog converters</a>, <a href="/wiki/Real-time_clock" title="Real-time clock">RTCs</a>, extra counters and timers, in-circuit <a href="/wiki/Debugging" title="Debugging">debugging</a> facilities, more interrupt sources, extra power-saving modes, more or fewer parallel ports etc. Intel manufactured a mask-programmed version, 8052AH-BASIC, with a <a href="/wiki/BASIC" title="BASIC">BASIC</a> interpreter in ROM, capable of running user programs loaded into RAM. </p><p>MCS-51-based microcontrollers have been adapted to extreme environments. Examples for high-temperature variants are the Tekmos TK8H51 family for −40<span class="nowrap"> </span>°C to +250<span class="nowrap"> </span>°C<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> or the <a href="/wiki/Honeywell" title="Honeywell">Honeywell</a> HT83C51 for −55<span class="nowrap"> </span>°C to +225<span class="nowrap"> </span>°C (with operation for up to 1 year at +300<span class="nowrap"> </span>°C).<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Radiation_hardening" title="Radiation hardening">Radiation-hardenend</a> MCS-51 microcontrollers for use in spacecraft are available; e.g., from <a href="/wiki/Cobham_plc" class="mw-redirect" title="Cobham plc">Cobham</a> (formerly <a href="/wiki/Aeroflex" title="Aeroflex">Aeroflex</a>) as the UT69RH051<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> or from NIIET as the 1830VE32 (<a href="/wiki/Russian_language" title="Russian language">Russian</a>: <span lang="ru">1830ВЕ32</span>).<sup id="cite_ref-niiet_13-0" class="reference"><a href="#cite_note-niiet-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p><p>In some engineering schools, the 8051 microcontroller is used in introductory microcontroller courses.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Family_naming_conventions">Family naming conventions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=3" title="Edit section: Family naming conventions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/List_of_Intel_processors#Intel_8051" title="List of Intel processors">List of Intel processors § Intel 8051</a></div> <p>Intel's first MCS-51 microcontroller was the 8051, with 4 KB ROM and 128 byte RAM. Variants starting with 87 have a user-programmable EPROM, sometimes UV-erasable. Variants with a C as the third character are some kind of <a href="/wiki/CMOS" title="CMOS">CMOS</a>. 8031 and 8032 are ROM-less versions, with 128 and 256 bytes of RAM. The last digit can indicate memory size, e.g. 8052 with 8 KB ROM, 87C54 16 KB EPROM, and 87C58 with 32 KB EPROM, all with 256-byte RAM. </p> <div class="mw-heading mw-heading2"><h2 id="Memory_architecture">Memory architecture</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=4" title="Edit section: Memory architecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The MCS-51 has four distinct types of memory: internal RAM, special function registers, program memory, and external data memory. To access these efficiently, some compilers<sup id="cite_ref-keil_18-0" class="reference"><a href="#cite_note-keil-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> utilize as many as 7 types of memory definitions: internal RAM, single-bit access to internal RAM, special function registers, single-bit access to selected (divisible by 8) special function registers, program RAM, external RAM accessed using a register indirect access, using one of the standard 8-bit registers, and register indirect external RAM access utilizing the 16-bit indirect access register. </p><p>The 8051's instruction set is designed as a <a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard architecture</a> with segregated memory (data and instructions); it can only execute code fetched from program memory and has no instructions to write to program memory. However, the bus leaving the IC has a single address and data path, and strongly resembles a <a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">von Neumann architecture</a> bus. </p><p>Most 8051 systems respect the instruction set and require customized features to download new executable programs, e.g. in flash memory. </p> <div class="mw-heading mw-heading3"><h3 id="Internal_RAM">Internal RAM</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=5" title="Edit section: Internal RAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Internal_RAM" title="Internal RAM">Internal RAM</a> (IRAM) has an 8-bit address space, using addresses 0 through 0xFF. IRAM from 0x00 to 0x7F contains 128 directly addressable 1-byte registers, which can be accessed using an 8-bit absolute address that is part of the instruction. Alternatively, IRAM can be accessed indirectly: the address is loaded into R0 or R1, and the memory is accessed using the <code>@R0</code> or <code>@R1</code> syntax, or as stack memory through the stack pointer SP, with the <code>PUSH</code>/<code>POP</code> and <code>*CALL</code>/<code>RET</code> operations. </p><p>The original 8051 has only 128 bytes of IRAM. The 8052 added IRAM from 0x80 to 0xFF, which can <i>only</i> be accessed indirectly (e.g. for use as stack space). Most 8051 clones also have a full 256 bytes of IRAM. </p><p>Direct accesses to the IRAM addresses 0x80–0xFF are, instead, mapped onto the special function registers (SFR), where the accumulators A, B, carry bit C, and other special registers for control, status, etc., are located. </p> <div class="mw-heading mw-heading3"><h3 id="Special_function_registers">Special function registers</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=6" title="Edit section: Special function registers"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Special function registers (SFR) are located in the same address space as IRAM, at addresses 0x80 to 0xFF, and are accessed directly using the same instructions as for the lower half of IRAM. They cannot be accessed indirectly via <code>@R0</code> or <code>@R1</code> or by the stack pointer SP; indirect access to those addresses will access the second half of IRAM instead. </p><p>The special function registers (SFR) include the accumulators A (or ACC, at E0) and B (at F0) and program status word (or PSW, at D0), themselves, as well as the 16-bit data pointer DPTR (at 82, as DPL and 83 as DPH). In addition to these, a small core of other special function registers –  including the interrupt enable IE at A8 and interrupt priority IP at B8; the I/O ports P0 (80), P1 (90), P2 (A0), P3 (B0); the serial I/O control SCON (98) and buffer SBUF (99); the CPU/power control register PCON (87); and the registers for timers 0 and 1 control (TCON at 88) and operation mode (TMOD at 89), the 16-bit timer 0 (TL0 at 8A, TH0 at 8C) and timer 1 (TL1 at 8B, TH1 at 8D) –  are present on all versions of the 8051. Other addresses are version-dependent; in particular, the registers of timer 2 for the 8052, the control register T2CON (at C8), the 16-bit capture/latch (RCAP2L at CA, RCAP2H at CB) and timer 2 (TL2 at CC and TH2 at CD) are not included with the 8051. </p> <div class="mw-heading mw-heading3"><h3 id="Register_windows">Register windows</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=7" title="Edit section: Register windows"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The 32 bytes in IRAM from 0x00 to 0x1F contain space for four 8-byte <a href="/wiki/Register_window" title="Register window">register windows</a>, which the eight registers R0–R7 map to. The currently active window is determined by a two-bit address contained in the program status word. </p> <div class="mw-heading mw-heading3"><h3 id="Bit_registers">Bit registers</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=8" title="Edit section: Bit registers"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The 16 bytes (128 bits) at IRAM locations 0x20–0x2F contain space for 128 1-bit registers, which are separately addressable as bit registers 00–7F. </p><p>The remaining bit registers, addressed as 80–FF, are mapped onto the 16 special function registers 80, 88, 90, 98, ..., F0 and F8 (those whose addresses are multiples of 8), and therefore include the bits comprising the accumulators A, B and program status word PSW. The register window address, being bits 3 and 4 of the PSW, is itself addressable as bit registers D3 and D4 respectively; while the carry bit C (or CY), at bit 7 of the PSW, is addressable as bit register D7. </p> <div class="mw-heading mw-heading3"><h3 id="Program_memory">Program memory</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=9" title="Edit section: Program memory"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Program memory (PMEM, though less common in usage than IRAM and XRAM) is up to 64 KB of read-only memory, starting at address 0 in a separate address space. It may be on- or off-chip, depending on the particular model of chip being used. Program memory is read-only, though some variants of the 8051 use on-chip flash memory and provide a method of re-programming the memory in-system or in-application. </p><p>In addition to code, it is possible to store read-only data such as <a href="/wiki/Lookup_table" title="Lookup table">lookup tables</a> in program memory, retrieved by the <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVC</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="err">@</span><span class="no">A</span><span class="err">+</span><span class="no">DPTR</span></code> or <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVC</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="err">@</span><span class="no">A</span><span class="err">+</span><span class="no">PC</span></code> instructions. The address is computed as the sum of the 8-bit accumulator and a 16-bit register (PC or DPTR). </p><p>Special jump and call instructions (<code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">AJMP</span></code> and <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ACALL</span></code>) slightly reduce the size of code that accesses local (within the same 2 KB) program memory.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p><p>When code larger than 64 KB is required, a common system makes the code bank-switched, with general-purpose I/O selecting the upper address bits. Some 8051 compilers<sup id="cite_ref-keil_18-1" class="reference"><a href="#cite_note-keil-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> make provisions to automatically access paged code. In these systems, the interrupt vectors and paging table are placed in the first 32 KB of code and are always resident. </p> <div class="mw-heading mw-heading3"><h3 id="External_data_memory">External data memory</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=10" title="Edit section: External data memory"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>External data memory (XRAM) is a third address space, also starting at address 0, and allowing 16 bits of address space. It can also be on- or off-chip; what makes it "external" is that it must be accessed using the <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span></code> (move external) instruction. Many variants of the 8051 include the standard 256 bytes of IRAM plus a few kilobytes of XRAM on the chip. </p><p>The first 256 bytes of XRAM may be accessed using the <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="err">@</span><span class="no">R0</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="err">@</span><span class="no">R1</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="err">@</span><span class="no">R0</span><span class="p">,</span><span class="no">A</span></code>, and <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="err">@</span><span class="no">R1</span><span class="p">,</span><span class="no">A</span></code> instructions. The full 64 KB may be accessed using <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="err">@</span><span class="no">DPTR</span></code> and <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="err">@</span><span class="no">DPTR</span><span class="p">,</span><span class="no">A</span></code>. The 16-bit address requires the programmer to load the 16-bit index register. For this reason, RAM accesses with 16-bit addresses are substantially slower. </p><p>Some CPUs<sup id="cite_ref-teridian_20-0" class="reference"><a href="#cite_note-teridian-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> permit the 8-bit indirect address to use any 8-bit general-purpose register. </p><p>To permit the use of this feature, some 8051-compatible microcontrollers with internal RAM larger than 256 bytes, or an inability to access external RAM,<sup id="cite_ref-teridian_20-1" class="reference"><a href="#cite_note-teridian-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> access internal RAM as if it were external and have a special function register (e.g. PDATA) that permits them to set the upper address of the 256-byte page. This emulates the MCS8051 mode that can page the upper byte of a RAM address by setting the general-purpose I/O pins. </p><p>When RAM larger than 64 KB is required, a common system makes the RAM bank-switched, with general-purpose I/O selecting the upper address bits. Some 8051 compilers<sup id="cite_ref-keil_18-2" class="reference"><a href="#cite_note-keil-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> make provisions to automatically access paged data. </p> <div class="mw-heading mw-heading2"><h2 id="Registers">Registers</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=11" title="Edit section: Registers"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The only register on an 8051 that is not memory-mapped is the 16-bit program counter (PC). This specifies the address of the next instruction to execute. Relative branch instructions supply an 8-bit signed offset which is added to the PC. </p><p>Eight general-purpose registers R0–R7 may be accessed with instructions one byte shorter than others. They are mapped to IRAM between 0x00 and 0x1F. Only eight bytes of that range are used at any given time, determined by the two bank-select bits in the PSW. </p><p>The following is a partial list of the 8051's registers, which are memory-mapped into the special function register space: </p> <dl><dt>Stack pointer, SP (0x81)</dt> <dd>This is an 8-bit register used by subroutine call and return instructions. The stack grows upward; the SP is incremented before pushing and decremented after popping a value.</dd> <dt>Data pointer, DP (0x82–83)</dt> <dd>This is a 16-bit register that is used for accessing PMEM and XRAM.</dd> <dt>Program status word, PSW (0xD0)</dt> <dd>This contains important status flags, by bit number: <div><ol start="0"><li>Parity, P. Gives the parity (<a href="/wiki/XOR" class="mw-redirect" title="XOR">XOR</a> of the bits) of the accumulator, A.</li><li>User defined, UD. May be read and written by software; not otherwise affected by hardware.</li><li><a href="/wiki/Overflow_flag" title="Overflow flag">Overflow flag</a>, OV. Set when addition produces a signed overflow.</li><li>Register select 0, RS0. The low-order bit of the register bank. Set when banks at 0x08 or 0x18 are in use.</li><li>Register select 1, RS1. The high-order bit of the register bank. Set when banks at 0x10 or 0x18 are in use.</li><li>Flag 0, F0. May be read and written by software; not otherwise affected by hardware.</li><li><a href="/wiki/Adjust_flag" class="mw-redirect" title="Adjust flag">Auxiliary carry</a>, AC. Set when addition produces a carry from bit 3 to bit 4.</li><li><a href="/wiki/Carry_bit" class="mw-redirect" title="Carry bit">Carry bit</a>, C. Often used as the general register for bit computations, or the "Boolean accumulator".</li></ol></div></dd> <dt>Accumulator, A (0xE0)</dt> <dd>This register is used by most instructions.</dd> <dt>B register (0xF0)</dt> <dd>This is used as an extension to the accumulator for multiply and divide instructions.</dd></dl> <p>256 single bits are directly addressable. These are the 16 IRAM locations from 0x20–0x2F, and the 16 special function registers 0x80, 0x88, 0x90, ..., 0xF8. Any bit of these bytes may be directly accessed by a variety of logical operations and conditional branches. </p><p>Note that the PSW does not contain the common <a href="/wiki/Negative_flag" title="Negative flag">negative (N)</a>, or <a href="/wiki/Zero_flag" title="Zero flag">zero (Z) flags</a>. For the former, the most significant bit of the accumulator can be addressed directly, as it is a bit-addressable SFR. For the latter, there are explicit instructions to jump on whether or not the accumulator is zero. There is also a two-operand compare and jump operation. </p><p>The parity (P) bit is often used to implement serial modes that include parity. To support this, the standard MCS51 <a href="/wiki/UART" class="mw-redirect" title="UART">UARTs</a> could send 9 bits. </p> <div class="mw-heading mw-heading2"><h2 id="Microarchitecture">Microarchitecture</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=12" title="Edit section: Microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The microarchitecture of the Intel MCS8051 is proprietary, but published<sup id="cite_ref-mcs51um_21-0" class="reference"><a href="#cite_note-mcs51um-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> features suggest how it works. It is a <a href="/wiki/Multi-cycle_processor" title="Multi-cycle processor">multi-cycle processor</a>. The MCS8051 used 12 clock cycles<sup id="cite_ref-mcs51um_21-1" class="reference"><a href="#cite_note-mcs51um-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> for most instructions. Many instructions utilize an accumulator.<sup id="cite_ref-mcs51um_21-2" class="reference"><a href="#cite_note-mcs51um-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> In contrast, most compatible computers execute instructions in one to three cycles, except for the multiply and divide instructions. The much higher speed is a major reason why these have replaced the MCS8051 in most applications. </p><p>Each interrupt has four priorities.<sup id="cite_ref-mcs51um_21-3" class="reference"><a href="#cite_note-mcs51um-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> Within each priority, the interrupts of devices are in a fixed priority.<sup id="cite_ref-mcs51um_21-4" class="reference"><a href="#cite_note-mcs51um-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Instruction_set">Instruction set</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=13" title="Edit section: Instruction set"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Instructions are all 1 to 3 bytes long, consisting of an initial opcode byte, followed by up to 2 bytes of operands. </p><p><style data-mw-deduplicate="TemplateStyles:r1154941027">.mw-parser-output .frac{white-space:nowrap}.mw-parser-output .frac .num,.mw-parser-output .frac .den{font-size:80%;line-height:0;vertical-align:super}.mw-parser-output .frac .den{vertical-align:sub}.mw-parser-output .sr-only{border:0;clip:rect(0,0,0,0);clip-path:polygon(0px 0px,0px 0px,0px 0px);height:1px;margin:-1px;overflow:hidden;padding:0;position:absolute;width:1px}</style><span class="frac"><span class="num">1</span>⁄<span class="den">4</span></span> of the opcode bytes, <b><i>x</i>0–<i>x</i>3</b>, are used for irregular opcodes. </p><p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1154941027" /><span class="frac"><span class="num">3</span>⁄<span class="den">4</span></span> of the opcode bytes, <b><i>x</i>4–<i>x</i>F</b>, are assigned to 16 basic ALU instructions with 12 possible operands. The least significant <a href="/wiki/Nibble" title="Nibble">nibble</a> of the opcode selects the primary operand as follows: </p> <ul><li><b><i>x</i>8–<i>x</i>F</b>: Register direct, R0–R7.</li> <li><b><i>x</i>6–<i>x</i>7</b>: Register indirect, @R0 or @R1.</li> <li><b><i>x</i>5</b>: Memory direct, a following byte specifies an IRAM or SFR location.</li> <li><b><i>x</i>4</b>: Immediate, a following byte specifies an 8-bit constant. When the operand is a destination (<code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">INC</span><span class="w"> </span><span class="no">operand</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">DEC</span><span class="w"> </span><span class="no">operand</span></code>) <i>or</i> the operation already includes an immediate source (<code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">operand</span><span class="p">,</span><span class="c1">#data</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CJNE</span><span class="w"> </span><span class="no">operand</span><span class="p">,</span><span class="c1">#data,offset</span></code>), this instead specifies that the accumulator is used.</li></ul> <p>The most significant nibble specifies the operation as follows. Not all support all addressing modes; the immediate mode in particular is unavailable when the primary operand is written to. Instruction mnemonics use <i>destination</i>, <i>source</i> operand order. </p> <dl><dt>0<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">INC</span><span class="w"> </span><span class="no">operand</span></code></dt> <dd>Increment the specified operand. Immediate mode (opcode 0x04) specifies the accumulator, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">INC</span><span class="w"> </span><span class="no">A</span></code>.</dd> <dt>1<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">DEC</span><span class="w"> </span><span class="no">operand</span></code></dt> <dd>Decrement the specified operand. Immediate mode (opcode 0x14) specifies the accumulator, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">DEC</span><span class="w"> </span><span class="no">A</span></code>.</dd> <dt>2<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ADD</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">operand</span></code></dt> <dd>Add the operand to the accumulator, A. Opcode 0x23 (<code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">RL</span><span class="w"> </span><span class="no">A</span></code>, "rotate left" but actually a <a href="/wiki/Shift_left" class="mw-redirect" title="Shift left">shift left</a>) may be thought of as <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ADD</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">A</span></code>.</dd> <dt>3<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ADDC</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">operand</span></code></dt> <dd>Add the operand, plus the C bit, to the accumulator. Opcode 0x33 (<code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">RLC</span><span class="w"> </span><span class="no">A</span></code>, rotate left through carry) may be thought of as <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ADDC</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">A</span></code>.</dd> <dt>4<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ORL</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">operand</span></code></dt> <dd>Logical OR the operand into the accumulator. Two memory-destination forms of this operation, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ORL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="c1">#data</span></code> and <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ORL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="no">A</span></code>, are specified by opcodes 0x43 and 0x42.</dd> <dt>5<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ANL</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">operand</span></code></dt> <dd>Logical AND the operand into the accumulator. Two memory-destination forms of this operation, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ANL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="c1">#data</span></code> and <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ANL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="no">A</span></code>, are specified by opcodes 0x53 and 0x52.</dd> <dt>6<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">XRL</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">operand</span></code></dt> <dd>Logical exclusive-OR the operand into the accumulator. Two memory-destination forms of this operation, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">XRL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="c1">#data</span></code> and <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">XRL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="no">A</span></code>, are specified by opcodes 0x63 and 0x62.</dd> <dt>7<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">operand</span><span class="p">,</span><span class="c1">#data</span></code></dt> <dd>Move immediate to the operand. Immediate mode (opcode 0x74) specifies the accumulator, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="c1">#data</span></code>.</dd> <dt>8<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="no">operand</span></code></dt> <dd>Move value to an IRAM or SFR register. Immediate mode (opcode 0x84) is not used for this operation, as it duplicates opcode 0x75.</dd> <dt>9<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">SUBB</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">operand</span></code></dt> <dd>Subtract the operand from the accumulator. This operation borrows and there is no subtract <i>without</i> borrow.</dd> <dt>A<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">operand</span><span class="p">,</span><span class="no">address</span></code></dt> <dd>Move value from an IRAM or SFR register. Immediate mode (opcode 0xA4) is not used, as immediates serve only as sources. Memory direct mode (opcode 0xA5) is not used, as it duplicates 0x85.</dd> <dt>B<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CJNE</span><span class="w"> </span><span class="no">operand</span><span class="p">,</span><span class="c1">#data,offset</span></code></dt> <dd>Compare <i>operand</i> to the immediate <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="c1">#data</span></code>, and jump to <span class="nowrap">PC + <i>offset</i></span> if not equal. Immediate and memory direct modes (opcodes 0xB4 and 0xB5) compare the operand against the accumulator, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CJNE</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">operand</span><span class="p">,</span><span class="no">offset</span></code>. Note that there is no compare and jump if equal instruction, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CJE</span></code>.</dd> <dt>C<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">XCH</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">operand</span></code></dt> <dd>Exchange the accumulator and the operand. Immediate mode (opcode 0xC4) is not used for this operation.</dd> <dt>D<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">DJNZ</span><span class="w"> </span><span class="no">operand</span><span class="p">,</span><span class="no">offset</span></code></dt> <dd>Decrement the operand, and jump to <span class="nowrap">PC + <i>offset</i></span> if the result is non-zero. Immediate mode (opcode 0xD4), and register indirect mode (0xD6, 0xD7) are not used.</dd> <dt>E<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">operand</span></code></dt> <dd>Move operand to the accumulator. Immediate mode is not used for this operation (opcode 0xE4), as it duplicates opcode 0x74.</dd> <dt>F<i>y</i>: <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">operand</span><span class="p">,</span><span class="no">A</span></code></dt> <dd>Move accumulator to the operand. Immediate mode (opcode 0xF4) is not used, as it would have no effect.</dd></dl> <p>Only the <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ADD</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ADDC</span></code>, and <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">SUBB</span></code> instructions set PSW flags. The <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">INC</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">DEC</span></code>, and logical instructions do not. The <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CJNE</span></code> instruction modifies the C bit only, to the borrow that results from <span class="nowrap"><i>operand1</i> − <i>operand2</i></span>. </p><p>The irregular instructions comprise 64 opcodes, having more limited addressing modes, plus several opcodes scavenged from inapplicable modes in the regular instructions. </p> <table class="wikitable"> <caption>8051/8052 irregular instructions </caption> <tbody><tr> <th>Opcode</th> <th><i>x</i>0</th> <th><i>x</i>1</th> <th><i>x</i>2</th> <th><i>x</i>3</th> <th><i>x</i>4 </th></tr> <tr> <th>0<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">NOP</span></code> </td> <td rowspan="16"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">AJMP</span><span class="w"> </span><span class="no">addr11</span></code>,</li><li><span class="nowrap"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ACALL</span><span class="w"> </span><span class="no">addr11</span></code></span></li></ul></div> </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">LJMP</span><span class="w"> </span><span class="no">addr16</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">RR</span><span class="w"> </span><span class="no">A</span></code> (rotate right)</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">INC</span><span class="w"> </span><span class="no">A</span></code> </td></tr> <tr> <th>1<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">JBC</span><span class="w"> </span><span class="no">bit</span><span class="p">,</span><span class="no">offset</span></code> (jump if bit set with clear) </td> <td><span class="nowrap"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">LCALL</span><span class="w"> </span><span class="no">addr16</span></code></span></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">RRC</span><span class="w"> </span><span class="no">A</span></code> (rotate right through carry)</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">DEC</span><span class="w"> </span><span class="no">A</span></code> </td></tr> <tr> <th>2<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">JB</span><span class="w"> </span><span class="no">bit</span><span class="p">,</span><span class="no">offset</span></code> (jump if bit set) </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">RET</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">RL</span><span class="w"> </span><span class="no">A</span></code> (rotate left)</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ADD</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="c1">#data</span></code> </td></tr> <tr> <th>3<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">JNB</span><span class="w"> </span><span class="no">bit</span><span class="p">,</span><span class="no">offset</span></code> (jump if bit clear) </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">RETI</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">RLC</span><span class="w"> </span><span class="no">A</span></code> (rotate left through carry)</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ADDC</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="c1">#data</span></code> </td></tr> <tr> <th>4<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">JC</span><span class="w"> </span><span class="no">offset</span></code> (jump if carry set) </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ORL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="no">A</span></code></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ORL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="c1">#data</span></code></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ORL</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="c1">#data</span></code> </td></tr> <tr> <th>5<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">JNC</span><span class="w"> </span><span class="no">offset</span></code> (jump if carry clear) </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ANL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="no">A</span></code></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ANL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="c1">#data</span></code></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ANL</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="c1">#data</span></code> </td></tr> <tr> <th>6<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">JZ</span><span class="w"> </span><span class="no">offset</span></code> (jump if zero) </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">XRL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="no">A</span></code></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">XRL</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="c1">#data</span></code></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">XRL</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="c1">#data</span></code> </td></tr> <tr> <th>7<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">JNZ</span><span class="w"> </span><span class="no">offset</span></code> (jump if non-zero) </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ORL</span><span class="w"> </span><span class="no">C</span><span class="p">,</span><span class="no">bit</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">JMP</span><span class="w"> </span><span class="err">@</span><span class="no">A</span><span class="err">+</span><span class="no">DPTR</span></code></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="c1">#data</span></code> </td></tr> <tr> <th>8<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">SJMP</span><span class="w"> </span><span class="no">offset</span></code> (short jump) </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ANL</span><span class="w"> </span><span class="no">C</span><span class="p">,</span><span class="no">bit</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVC</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="err">@</span><span class="no">A</span><span class="err">+</span><span class="no">PC</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">DIV</span><span class="w"> </span><span class="no">AB</span></code> </td></tr> <tr> <th>9<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">DPTR</span><span class="p">,</span><span class="c1">#data16</span></code> </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">bit</span><span class="p">,</span><span class="no">C</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVC</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="err">@</span><span class="no">A</span><span class="err">+</span><span class="no">DPTR</span></code></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">SUBB</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="c1">#data</span></code> </td></tr> <tr> <th>A<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ORL</span><span class="w"> </span><span class="no">C</span><span class="p">,</span><span class="err">/</span><span class="no">bit</span></code> </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">C</span><span class="p">,</span><span class="no">bit</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">INC</span><span class="w"> </span><span class="no">DPTR</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MUL</span><span class="w"> </span><span class="no">AB</span></code> </td></tr> <tr> <th>B<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ANL</span><span class="w"> </span><span class="no">C</span><span class="p">,</span><span class="err">/</span><span class="no">bit</span></code> </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CPL</span><span class="w"> </span><span class="no">bit</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CPL</span><span class="w"> </span><span class="no">C</span></code></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CJNE</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="c1">#data,offset</span></code> </td></tr> <tr> <th>C<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">PUSH</span><span class="w"> </span><span class="no">address</span></code> </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CLR</span><span class="w"> </span><span class="no">bit</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CLR</span><span class="w"> </span><span class="no">C</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">SWAP</span><span class="w"> </span><span class="no">A</span></code> </td></tr> <tr> <th>D<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">POP</span><span class="w"> </span><span class="no">address</span></code> </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">SETB</span><span class="w"> </span><span class="no">bit</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">SETB</span><span class="w"> </span><span class="no">C</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">DA</span><span class="w"> </span><span class="no">A</span></code> (decimal adjust) </td></tr> <tr> <th>E<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="err">@</span><span class="no">DPTR</span></code> </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="err">@</span><span class="no">R0</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="err">@</span><span class="no">R1</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CLR</span><span class="w"> </span><span class="no">A</span></code> </td></tr> <tr> <th>F<i>y</i> </th> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="err">@</span><span class="no">DPTR</span><span class="p">,</span><span class="no">A</span></code> </td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="err">@</span><span class="no">R0</span><span class="p">,</span><span class="no">A</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOVX</span><span class="w"> </span><span class="err">@</span><span class="no">R1</span><span class="p">,</span><span class="no">A</span></code></td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CPL</span><span class="w"> </span><span class="no">A</span></code> </td></tr></tbody></table> <dl><dt>85</dt> <dd><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">address</span><span class="p">,</span><span class="no">address</span></code> move directly between two IRAM or SFR registers.</dd> <dt>A5</dt> <dd><i>Unused</i></dd> <dt>B5</dt> <dd><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CJNE</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="no">address</span><span class="p">,</span><span class="no">offset</span></code> compare accumulator to an IRAM or SFR register, and jump to <span class="nowrap">PC + <i>offset</i></span> if not equal.</dd> <dt>D6–7</dt> <dd><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">XCHD</span><span class="w"> </span><span class="no">A</span><span class="p">,</span><span class="err">@</span><span class="no">R0</span><span class="err">–</span><span class="mi">1</span></code> exchange low-order nibble of operands.</dd></dl> <p>The <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">SJMP</span></code> (short jump) opcode takes a signed relative offset byte operand and transfers control there relative to the address of the following instruction. The <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">AJMP</span></code>/<code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ACALL</span></code> opcodes combine the three most significant bits of the opcode byte with the following byte to specify an 11-bit destination that is used to replace 11 bottom bits of the PC register (top 5 bits of PC register remain intact). For larger addresses, the <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">LJMP</span></code> and <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">LCALL</span></code> instructions allow a 16-bit destination. </p><p>One of the reasons for the 8051's popularity is its range of operations on single bits. Bits are always specified by absolute addresses; there is no register-indirect or indexed addressing. Instructions that operate on single bits are: </p> <ul><li><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">SETB</span><span class="w"> </span><span class="no">bit</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CLR</span><span class="w"> </span><span class="no">bit</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CPL</span><span class="w"> </span><span class="no">bit</span></code>: Set, clear, or complement the specified bit</li> <li><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">JB</span><span class="w"> </span><span class="no">bit</span><span class="p">,</span><span class="no">offset</span></code>: Jump if bit set</li> <li><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">JNB</span><span class="w"> </span><span class="no">bit</span><span class="p">,</span><span class="no">offset</span></code>: Jump if bit clear</li> <li><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">JBC</span><span class="w"> </span><span class="no">bit</span><span class="p">,</span><span class="no">offset</span></code>: Jump if bit set, and clear bit</li> <li><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">C</span><span class="p">,</span><span class="no">bit</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">MOV</span><span class="w"> </span><span class="no">bit</span><span class="p">,</span><span class="no">C</span></code>: Move the specified bit to the carry bit, or vice versa</li> <li><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ORL</span><span class="w"> </span><span class="no">C</span><span class="p">,</span><span class="no">bit</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ORL</span><span class="w"> </span><span class="no">C</span><span class="p">,</span><span class="err">/</span><span class="no">bit</span></code>: Or the bit (or its complement) to the carry bit</li> <li><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ANL</span><span class="w"> </span><span class="no">C</span><span class="p">,</span><span class="no">bit</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">ANL</span><span class="w"> </span><span class="no">C</span><span class="p">,</span><span class="err">/</span><span class="no">bit</span></code>: And the bit (or its complement) to the carry bit</li></ul> <p>A bit operand is written in the form <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">address.number</code>. Because the carry flag is bit 7 of the bit-addressable program status word, the <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">SETB</span><span class="w"> </span><span class="no">C</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CLR</span><span class="w"> </span><span class="no">C</span></code> and <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CPL</span><span class="w"> </span><span class="no">C</span></code> instructions are shorter equivalents to <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">SETB</span><span class="w"> </span><span class="no">PSW.7</span></code>, <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CLR</span><span class="w"> </span><span class="no">PSW.7</span></code> and <code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr"><span class="nf">CPL</span><span class="w"> </span><span class="no">PSW.7</span></code>. </p> <div class="mw-heading mw-heading2"><h2 id="Programming">Programming</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=14" title="Edit section: Programming"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>There are various <a href="/wiki/High-level_programming_language" title="High-level programming language">high-level programming language</a> compilers for the 8051. Several <a href="/wiki/C_(programming_language)" title="C (programming language)">C</a> compilers are available for the 8051, most of which allow the programmer to specify where each variable should be stored in its six types of memory, and provide access to 8051-specific hardware features such as the multiple register banks and bit manipulation instructions. There are many commercial C compilers.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Small_Device_C_Compiler" title="Small Device C Compiler">Small Device C Compiler</a> (SDCC) is a popular open-source C compiler.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> Other high level languages such as <a href="/wiki/C%2B%2B" title="C++">C++</a>, <a href="/wiki/Forth_(programming_language)" title="Forth (programming language)">Forth</a>,<sup id="cite_ref-camelforth_24-0" class="reference"><a href="#cite_note-camelforth-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-bradford_25-0" class="reference"><a href="#cite_note-bradford-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> <a href="/wiki/BASIC" title="BASIC">BASIC</a>, <a href="/wiki/Object_Pascal" title="Object Pascal">Object Pascal</a>, <a href="/wiki/Pascal_(programming_language)" title="Pascal (programming language)">Pascal</a>, <a href="/wiki/PL/M" title="PL/M">PL/M</a> and <a href="/wiki/Modula-2" title="Modula-2">Modula-2</a> are available for the 8051, but they are less widely used<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> than C and <a href="/wiki/Assembly_language" title="Assembly language">assembly</a>. </p><p>Because IRAM, XRAM, and PMEM (read only) all have an address 0, C compilers for the 8051 architecture provide compiler-specific <a href="/wiki/Directive_(programming)" title="Directive (programming)">pragmas</a> or other extensions to indicate where a particular piece of data should be stored (i.e. constants in PMEM or variables needing fast access in IRAM). Since data could be in one of three memory spaces, a mechanism is usually provided to allow determining to which memory a pointer refers, either by constraining the pointer type to include the memory space or by storing metadata with the pointer. </p> <div class="mw-heading mw-heading2"><h2 id="Related_processors">Related processors</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=15" title="Edit section: Related processors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:INTEL8031AH.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/af/INTEL8031AH.png/220px-INTEL8031AH.png" decoding="async" width="220" height="164" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/af/INTEL8031AH.png/330px-INTEL8031AH.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/af/INTEL8031AH.png/440px-INTEL8031AH.png 2x" data-file-width="468" data-file-height="348" /></a><figcaption>Intel 8031 microcontrollers</figcaption></figure> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_D87C51-3183.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/06/Intel_D87C51-3183.jpg/250px-Intel_D87C51-3183.jpg" decoding="async" width="220" height="124" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/06/Intel_D87C51-3183.jpg/330px-Intel_D87C51-3183.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/06/Intel_D87C51-3183.jpg/500px-Intel_D87C51-3183.jpg 2x" data-file-width="4163" data-file-height="2342" /></a><figcaption>Intel D87C51 microcontroller</figcaption></figure> <p>Intel discontinued its MCS-51 product line in March 2007;<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> however, there are plenty of enhanced 8051 products or <a href="/wiki/Silicon_intellectual_property" class="mw-redirect" title="Silicon intellectual property">silicon intellectual property</a> added regularly from other vendors. </p><p>The 8051's predecessor, the <a href="/wiki/8048" class="mw-redirect" title="8048">8048</a>, was used in the keyboard of the first <a href="/wiki/IBM_PC" class="mw-redirect" title="IBM PC">IBM PC</a>, where it converted keypresses into the serial data stream which is sent to the main unit of the computer. An Intel 8049 served a similar role in the <a href="/wiki/Sinclair_QL" title="Sinclair QL">Sinclair QL</a>. The 8048 and derivatives are still used today<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=Intel_MCS-51&action=edit">[update]</a></sup> for basic model keyboards. </p><p>The <b>8031</b> was a reduced version of the original 8051 that had no internal program memory (<a href="/wiki/Read-only_memory" title="Read-only memory">read-only memory</a>, ROM). To use this chip, external ROM had to be added containing the program that the 8031 would fetch and execute. An 8051 chip could be sold as a ROM-less 8031, as the 8051's internal ROM is disabled by the normal state of the EA pin in an 8031-based design. A vendor might sell an 8051 as an 8031 for any number of reasons, such as faulty code in the 8051's ROM, or simply an oversupply of 8051s and undersupply of 8031s. </p> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_P8044AH.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/34/Intel_P8044AH.jpg/220px-Intel_P8044AH.jpg" decoding="async" width="220" height="76" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/34/Intel_P8044AH.jpg/330px-Intel_P8044AH.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/34/Intel_P8044AH.jpg/440px-Intel_P8044AH.jpg 2x" data-file-width="665" data-file-height="231" /></a><figcaption>Intel P8044AH microcontroller</figcaption></figure> <p>The <b>8044</b> (as well as the ROM-less 8344 and the 8744 with EPROM) added an <a href="/wiki/Synchronous_Data_Link_Control" title="Synchronous Data Link Control">SDLC</a> controller to the 8051 core (especially for <a href="/wiki/Bitbus" class="mw-redirect" title="Bitbus">Bitbus</a> applications).<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> </p><p>The <b>8052</b> was an enhanced version of the original 8051 that featured 256 bytes of internal RAM instead of 128 bytes, 8 KB of ROM instead of 4 KB, and a third 16-bit timer. Most modern 8051-compatible microcontrollers include these features. </p><p>The <b>8032</b> had these same features as the 8052 except it lacked internal ROM program memory. </p><p>The <b>8751</b> was an 8051 with 4 KB EPROM instead of 4 KB ROM. They were identical except for the non-volatile memory type. This part was available in a ceramic package with a clear <a href="/wiki/Quartz" title="Quartz">quartz</a> window over the top of the die so <a href="/wiki/Ultraviolet#Electrical_and_electronics_industry" title="Ultraviolet">UV light</a> could be used to erase the <a href="/wiki/EPROM" title="EPROM">EPROM</a>. Related parts are: 8752 had 8 KB EPROM, 8754 had 16 KB EPROM, 8758 had 32 KB EPROM. </p><p>The <b>80C537</b> (ROM-less) and <b>80C517</b> (8 KB ROM) are <a href="/wiki/CMOS" title="CMOS">CMOS</a> versions, designed for the <a href="/wiki/Automotive_industry" title="Automotive industry">automotive industry</a>. Enhancements mostly include new and enhanced peripherals. The 80C5x7 has fail-safe mechanisms, analog signal processing facilities, enhanced timer capabilities, and a 32-bit arithmetic peripheral. Other features include: </p> <ul><li>256-byte on-chip RAM</li> <li>256 directly addressable bits</li> <li>External program and data memory expandable up to 64 KB</li> <li>8-bit A/D converter with 12 multiplexed inputs</li> <li>Arithmetic peripheral can perform 16×16→32-bit multiplication, 32/16→16-bit division, 32-bit shift and 32-bit normalize operations</li> <li>Eight data pointers instead of one for indirect addressing of program and external data memory</li> <li>Extended watchdog facilities</li> <li>Nine I/O ports</li> <li>Two full-duplex serial interfaces with individual baud rate generators</li> <li>Four priority level interrupt systems, 14 interrupt vectors</li> <li>Three power-saving modes</li></ul> <ul class="gallery mw-gallery-packed"> <li class="gallerycaption">Intel MCS-51 <a href="/wiki/Second_source" title="Second source">second sources</a></li> <li class="gallerybox" style="width: 440px"> <div class="thumb" style="width: 438px;"><span typeof="mw:File"><a href="/wiki/File:Intel_D87C51_AMD.jpg" class="mw-file-description" title="AMD D87C51"><img alt="AMD D87C51" src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_D87C51_AMD.jpg/657px-Intel_D87C51_AMD.jpg" decoding="async" width="438" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_D87C51_AMD.jpg/987px-Intel_D87C51_AMD.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_D87C51_AMD.jpg/1314px-Intel_D87C51_AMD.jpg 2x" data-file-width="1734" data-file-height="594" /></a></span></div> <div class="gallerytext"><a href="/wiki/AMD" title="AMD">AMD</a> D87C51</div> </li> <li class="gallerybox" style="width: 446px"> <div class="thumb" style="width: 444px;"><span typeof="mw:File"><a href="/wiki/File:MBL8031AH.jpg" class="mw-file-description" title="Fujitsu MBL8031AH"><img alt="Fujitsu MBL8031AH" src="//upload.wikimedia.org/wikipedia/commons/thumb/9/92/MBL8031AH.jpg/666px-MBL8031AH.jpg" decoding="async" width="444" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/92/MBL8031AH.jpg/1000px-MBL8031AH.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/92/MBL8031AH.jpg/1331px-MBL8031AH.jpg 2x" data-file-width="4820" data-file-height="1630" /></a></span></div> <div class="gallerytext"><a href="/wiki/Fujitsu" title="Fujitsu">Fujitsu</a> MBL8031AH</div> </li> <li class="gallerybox" style="width: 148.66666666667px"> <div class="thumb" style="width: 146.66666666667px;"><span typeof="mw:File"><a href="/wiki/File:Ic-photo-MHS--S-80C31--(8031-MCU).png" class="mw-file-description" title="MHS S-80C31"><img alt="MHS S-80C31" src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b8/Ic-photo-MHS--S-80C31--%288031-MCU%29.png/250px-Ic-photo-MHS--S-80C31--%288031-MCU%29.png" decoding="async" width="147" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b8/Ic-photo-MHS--S-80C31--%288031-MCU%29.png/330px-Ic-photo-MHS--S-80C31--%288031-MCU%29.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b8/Ic-photo-MHS--S-80C31--%288031-MCU%29.png/439px-Ic-photo-MHS--S-80C31--%288031-MCU%29.png 2x" data-file-width="490" data-file-height="502" /></a></span></div> <div class="gallerytext">MHS S-80C31</div> </li> <li class="gallerybox" style="width: 152.66666666667px"> <div class="thumb" style="width: 150.66666666667px;"><span typeof="mw:File"><a href="/wiki/File:Ic-photo-OKI--M80C31F--(8031-MCU).JPG" class="mw-file-description" title="OKI M80C31"><img alt="OKI M80C31" src="//upload.wikimedia.org/wikipedia/commons/thumb/6/68/Ic-photo-OKI--M80C31F--%288031-MCU%29.JPG/226px-Ic-photo-OKI--M80C31F--%288031-MCU%29.JPG" decoding="async" width="151" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/68/Ic-photo-OKI--M80C31F--%288031-MCU%29.JPG/340px-Ic-photo-OKI--M80C31F--%288031-MCU%29.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/68/Ic-photo-OKI--M80C31F--%288031-MCU%29.JPG/452px-Ic-photo-OKI--M80C31F--%288031-MCU%29.JPG 2x" data-file-width="760" data-file-height="756" /></a></span></div> <div class="gallerytext"><a href="/wiki/Oki_Electric_Industry" title="Oki Electric Industry">OKI</a> M80C31</div> </li> <li class="gallerybox" style="width: 421.33333333333px"> <div class="thumb" style="width: 419.33333333333px;"><span typeof="mw:File"><a href="/wiki/File:Ic-photo-Philips--80C31BH-3_16P--(8031-MCU).png" class="mw-file-description" title="Philips PCB80C31"><img alt="Philips PCB80C31" src="//upload.wikimedia.org/wikipedia/commons/thumb/8/83/Ic-photo-Philips--80C31BH-3_16P--%288031-MCU%29.png/629px-Ic-photo-Philips--80C31BH-3_16P--%288031-MCU%29.png" decoding="async" width="420" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/83/Ic-photo-Philips--80C31BH-3_16P--%288031-MCU%29.png/945px-Ic-photo-Philips--80C31BH-3_16P--%288031-MCU%29.png 1.5x, //upload.wikimedia.org/wikipedia/commons/8/83/Ic-photo-Philips--80C31BH-3_16P--%288031-MCU%29.png 2x" data-file-width="1000" data-file-height="358" /></a></span></div> <div class="gallerytext"><a href="/wiki/Philips" title="Philips">Philips</a> PCB80C31</div> </li> <li class="gallerybox" style="width: 454px"> <div class="thumb" style="width: 452px;"><span typeof="mw:File"><a href="/wiki/File:Ic-photo-Signetics--SCN8031H--(8031-MCU).JPG" class="mw-file-description" title="Signetics SCN8031"><img alt="Signetics SCN8031" src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a5/Ic-photo-Signetics--SCN8031H--%288031-MCU%29.JPG/678px-Ic-photo-Signetics--SCN8031H--%288031-MCU%29.JPG" decoding="async" width="452" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a5/Ic-photo-Signetics--SCN8031H--%288031-MCU%29.JPG/1018px-Ic-photo-Signetics--SCN8031H--%288031-MCU%29.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a5/Ic-photo-Signetics--SCN8031H--%288031-MCU%29.JPG/1355px-Ic-photo-Signetics--SCN8031H--%288031-MCU%29.JPG 2x" data-file-width="2601" data-file-height="864" /></a></span></div> <div class="gallerytext"><a href="/wiki/Signetics" title="Signetics">Signetics</a> SCN8031</div> </li> <li class="gallerybox" style="width: 151.33333333333px"> <div class="thumb" style="width: 149.33333333333px;"><span typeof="mw:File"><a href="/wiki/File:Ic-photo-Temic--TS80C32X2-MCB-(8032-MCU).png" class="mw-file-description" title="Temic TS80C32X2"><img alt="Temic TS80C32X2" src="//upload.wikimedia.org/wikipedia/commons/thumb/e/eb/Ic-photo-Temic--TS80C32X2-MCB-%288032-MCU%29.png/224px-Ic-photo-Temic--TS80C32X2-MCB-%288032-MCU%29.png" decoding="async" width="150" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/eb/Ic-photo-Temic--TS80C32X2-MCB-%288032-MCU%29.png/336px-Ic-photo-Temic--TS80C32X2-MCB-%288032-MCU%29.png 1.5x, //upload.wikimedia.org/wikipedia/commons/e/eb/Ic-photo-Temic--TS80C32X2-MCB-%288032-MCU%29.png 2x" data-file-width="374" data-file-height="376" /></a></span></div> <div class="gallerytext">Temic TS80C32X2</div> </li> </ul> <div class="mw-heading mw-heading3"><h3 id="Derivative_vendors">Derivative vendors</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=16" title="Edit section: Derivative vendors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>More than 20 independent manufacturers produce MCS-51 compatible processors. <sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (July 2017)">citation needed</span></a></i>]</sup> </p> <ul class="gallery mw-gallery-packed"> <li class="gallerycaption">Intel MCS-51 derived microcontrollers</li> <li class="gallerybox" style="width: 268.66666666667px"> <div class="thumb" style="width: 266.66666666667px;"><span typeof="mw:File"><a href="/wiki/File:Atmel_89c2051_gfdl.jpg" class="mw-file-description" title="Atmel AT89C2051"><img alt="Atmel AT89C2051" src="//upload.wikimedia.org/wikipedia/commons/thumb/0/0d/Atmel_89c2051_gfdl.jpg/400px-Atmel_89c2051_gfdl.jpg" decoding="async" width="267" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/0d/Atmel_89c2051_gfdl.jpg/601px-Atmel_89c2051_gfdl.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/0d/Atmel_89c2051_gfdl.jpg/800px-Atmel_89c2051_gfdl.jpg 2x" data-file-width="1881" data-file-height="1058" /></a></span></div> <div class="gallerytext"><a href="/wiki/Atmel" title="Atmel">Atmel</a> <a href="/wiki/Atmel_AT89_series" title="Atmel AT89 series">AT89C2051</a></div> </li> <li class="gallerybox" style="width: 175.33333333333px"> <div class="thumb" style="width: 173.33333333333px;"><span typeof="mw:File"><a href="/wiki/File:SAB-C515-LN.jpg" class="mw-file-description" title="Infineon SAB-C515"><img alt="Infineon SAB-C515" src="//upload.wikimedia.org/wikipedia/commons/thumb/9/9f/SAB-C515-LN.jpg/330px-SAB-C515-LN.jpg" decoding="async" width="174" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/9f/SAB-C515-LN.jpg/500px-SAB-C515-LN.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/9f/SAB-C515-LN.jpg/960px-SAB-C515-LN.jpg 2x" data-file-width="1896" data-file-height="1640" /></a></span></div> <div class="gallerytext"><a href="/wiki/Infineon" class="mw-redirect" title="Infineon">Infineon</a> SAB-C515</div> </li> <li class="gallerybox" style="width: 175.33333333333px"> <div class="thumb" style="width: 173.33333333333px;"><span typeof="mw:File"><a href="/wiki/File:EPROM-Microcontroller_Philips_87C654.jpg" class="mw-file-description" title="Philips S87C654"><img alt="Philips S87C654" src="//upload.wikimedia.org/wikipedia/commons/thumb/d/d1/EPROM-Microcontroller_Philips_87C654.jpg/330px-EPROM-Microcontroller_Philips_87C654.jpg" decoding="async" width="174" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/d1/EPROM-Microcontroller_Philips_87C654.jpg/500px-EPROM-Microcontroller_Philips_87C654.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/d1/EPROM-Microcontroller_Philips_87C654.jpg/960px-EPROM-Microcontroller_Philips_87C654.jpg 2x" data-file-width="2990" data-file-height="2592" /></a></span></div> <div class="gallerytext"><a href="/wiki/Philips" title="Philips">Philips</a> S87C654</div> </li> <li class="gallerybox" style="width: 427.33333333333px"> <div class="thumb" style="width: 425.33333333333px;"><span typeof="mw:File"><a href="/wiki/File:Ic-photo-Siemens--SAB-C501G-1RP-(MCU).png" class="mw-file-description" title="Siemens SAB-C501"><img alt="Siemens SAB-C501" src="//upload.wikimedia.org/wikipedia/commons/thumb/9/95/Ic-photo-Siemens--SAB-C501G-1RP-%28MCU%29.png/960px-Ic-photo-Siemens--SAB-C501G-1RP-%28MCU%29.png" decoding="async" width="426" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/9/95/Ic-photo-Siemens--SAB-C501G-1RP-%28MCU%29.png 2x" data-file-width="978" data-file-height="345" /></a></span></div> <div class="gallerytext"><a href="/wiki/Siemens" title="Siemens">Siemens</a> SAB-C501</div> </li> <li class="gallerybox" style="width: 267.33333333333px"> <div class="thumb" style="width: 265.33333333333px;"><span typeof="mw:File"><a href="/wiki/File:STC89C52.jpg" class="mw-file-description" title="STC Micro STC89C52"><img alt="STC Micro STC89C52" src="//upload.wikimedia.org/wikipedia/commons/thumb/7/7e/STC89C52.jpg/500px-STC89C52.jpg" decoding="async" width="266" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/7e/STC89C52.jpg/960px-STC89C52.jpg 1.5x" data-file-width="1765" data-file-height="999" /></a></span></div> <div class="gallerytext">STC Micro STC89C52</div> </li> </ul> <p>Other ICs or IPs compatible with the MCS-51 have been developed by <a href="/wiki/Analog_Devices" title="Analog Devices">Analog Devices</a>,<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> Integral <a href="/wiki/Minsk" title="Minsk">Minsk</a>,<sup id="cite_ref-integral_33-0" class="reference"><a href="#cite_note-integral-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> Kristall <a href="/wiki/Kyiv" title="Kyiv">Kyiv</a>,<sup id="cite_ref-kristall5701_34-0" class="reference"><a href="#cite_note-kristall5701-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> and NIIET <a href="/wiki/Voronezh" title="Voronezh">Voronezh</a>.<sup id="cite_ref-niiet_13-1" class="reference"><a href="#cite_note-niiet-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Use_as_intellectual_property">Use as intellectual property</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=17" title="Edit section: Use as intellectual property"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Today, 8051s are still available as discrete parts, but they are mostly used as <a href="/wiki/Silicon_intellectual_property" class="mw-redirect" title="Silicon intellectual property">silicon intellectual property</a> cores.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> Available in hardware description language source code (such as <a href="/wiki/VHDL" title="VHDL">VHDL</a> or <a href="/wiki/Verilog" title="Verilog">Verilog</a>) or <a href="/wiki/FPGA" class="mw-redirect" title="FPGA">FPGA</a> <a href="/wiki/Netlist" title="Netlist">netlist</a> forms, these cores are typically integrated within embedded systems, in products ranging from <a href="/wiki/USB_flash_drive" title="USB flash drive">USB flash drives</a> to washing machines to complex wireless communication <a href="/wiki/System_on_a_chip" title="System on a chip">systems on a chip</a>. Designers use 8051 silicon IP cores, because of the smaller size, and lower power, compared to 32-bit processors like <a href="/wiki/ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M series</a>, <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> and BA22.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (July 2018)">citation needed</span></a></i>]</sup> </p><p>Subsequent 8051 core designs have increased performance while retaining compatibility with the original MCS 51 instruction set. The original Intel 8051 was a microcode engine using 12 clocked microcode cycles per machine cycle to minimize the number of NMOS logic gates consuming power in passive resistive pull-ups. Most instructions executed in one or two machine cycles. At the typical maximum clock frequency of 12 MHz the original 8051 types execute one million single-cycle instructions, or 500,000 two-cycle instructions, per second. The change to CMOS using active P-channel FET pull-ups makes it possible to realize the core without microcode. Enhanced 8051 IP cores run at one clock cycle per machine cycle. With clock frequencies of up to 450 MHz an 8051-compatible processor can execute up to 450 million instructions per second. </p> <div class="mw-heading mw-heading2"><h2 id="MCUs_based_on_8051">MCUs based on 8051</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=18" title="Edit section: MCUs based on 8051"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 1.5x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Intel_MCS-51&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">June 2021</span>)</i></span></div></td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Apple_TV,_1st_generation_-_mainboard_-_Silicon_Storage_Technology_89V54RD2-3214.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/49/Apple_TV%2C_1st_generation_-_mainboard_-_Silicon_Storage_Technology_89V54RD2-3214.jpg/250px-Apple_TV%2C_1st_generation_-_mainboard_-_Silicon_Storage_Technology_89V54RD2-3214.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/49/Apple_TV%2C_1st_generation_-_mainboard_-_Silicon_Storage_Technology_89V54RD2-3214.jpg/330px-Apple_TV%2C_1st_generation_-_mainboard_-_Silicon_Storage_Technology_89V54RD2-3214.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/49/Apple_TV%2C_1st_generation_-_mainboard_-_Silicon_Storage_Technology_89V54RD2-3214.jpg/500px-Apple_TV%2C_1st_generation_-_mainboard_-_Silicon_Storage_Technology_89V54RD2-3214.jpg 2x" data-file-width="2228" data-file-height="2228" /></a><figcaption>Silicon Storage Technology 89V54RD2</figcaption></figure> <ul><li>ABOV: MC94F, MC95F, MC96F series</li> <li>Analog Devices (formerly Maxim Integrated, originally Dallas): DS80-series etc.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a> <a href="/wiki/Cypress_PSoC#Series" title="Cypress PSoC">CY8C3xxxx series</a>, which has a dedicated <a href="/wiki/USB_2.0" class="mw-redirect" title="USB 2.0">USB 2.0</a> interface<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup></li> <li>Jin Rui (brand CACHIP): <a href="/w/index.php?title=CA51Fx&action=edit&redlink=1" class="new" title="CA51Fx (page does not exist)">CA51Fx</a> family 8-bit MCUs.<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup></li> <li>Infineon: <a href="/wiki/XC800" class="mw-redirect" title="XC800">XC800</a></li> <li>Mentor Graphics: M8051EW etc. designed for Mentor by <a href="/w/index.php?title=SYNTILL8&action=edit&redlink=1" class="new" title="SYNTILL8 (page does not exist)">SYNTILL8</a><sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup></li> <li>Megawin: 74, 82, 84, 86, 87, and 89 series</li> <li>Microchip (formerly Atmel): <a href="/wiki/Atmel_AT89_series" title="Atmel AT89 series">AT89C51, AT89S51</a>, AT83C5134, etc.<sup id="cite_ref-:1_9-1" class="reference"><a href="#cite_note-:1-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup></li> <li>NXP: NXP700 and NXP900 series</li> <li>Siemens 8-bit: SAB 8035/8048, SAB 80512/80532, SAB 80513, SAB 8352-2/8352-5, SAB 80(C)515/80(C)535, SAB 83515, SAB 80(C)517/80(C)537, SAB 8051A/8031A, SAB 8052A/8032A, SAB 8052B/8032B, SAB80C52/80C32, SDA 30C164-2 (ROMless)<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup></li> <li>Siemens 16-bit: <a href="/wiki/C166_family" title="C166 family">C166 family</a></li> <li><a href="/wiki/Silergy" title="Silergy">Silergy</a> electricity metering <a href="/wiki/System_On_Chip" class="mw-redirect" title="System On Chip">SoCs</a>: 71M6511, 71M6513, 71M6531, 71M6533, 71M6534, 71M6542, 71M6543<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> Energy measurement <a href="/wiki/System_On_Chip" class="mw-redirect" title="System On Chip">SoCs</a>: 78M6631, 78M6618, 78M6613, 78M6612<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup></li> <li>Silicon Labs: C8051 series and EFM8 series<sup id="cite_ref-:0_7-1" class="reference"><a href="#cite_note-:0-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Silicon_Storage_Technology" class="mw-redirect" title="Silicon Storage Technology">Silicon Storage Technology</a>: FlashFlex51 MCU (SST89E52RD2, SST89E54RD2, SST89E58RD2, SST89E516RD2SST89V52RD2, SST89V54RD2, SST89V58RD2, SST89V516RD2)<sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup></li> <li>STC Micro: STC89C51RC, STC90C51RC, STC90C58AD, STC10F08XE, STC11F60XE, STC12C5410AD, STC12C5202AD, STC12C5A60S2, STC12C5628AD, STC15F100, STC15F204EA, STC15F2K60S2, STC15F4K60S2, STC15F101W, STC15F408AD, STC15W104, STC15W408S, STC15W201S, STC15W408AS, STC15W1K16S and STC15W4K56S4 series<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup></li> <li>Texas Instruments CC111x, CC24xx and CC25xx families of RF SoCs</li> <li>WCH (<a href="/w/index.php?title=Nanjing_Qinheng_Microelectronics&action=edit&redlink=1" class="new" title="Nanjing Qinheng Microelectronics (page does not exist)">Nanjing Qinheng Microelectronics</a>): CH551, CH552, CH554, CH546, CH547, CH548, CH558, CH559<sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading2"><h2 id="Digital_signal_processor_(DSP)_variants"><span id="Digital_signal_processor_.28DSP.29_variants"></span>Digital signal processor (DSP) variants</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=19" title="Edit section: Digital signal processor (DSP) variants"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Several variants with an additional 16-bit <a href="/wiki/Digital_signal_processor" title="Digital signal processor">digital signal processor</a> (DSP) (for example for <a href="/wiki/MP3" title="MP3">MP3</a> or <a href="/wiki/Vorbis" title="Vorbis">Vorbis</a> coding/decoding) with up to 675 million instructions per second (MIPS)<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> and integrated <a href="/wiki/USB_2.0" class="mw-redirect" title="USB 2.0">USB 2.0</a> interface<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> or as intellectual property<sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> exist. </p> <div class="mw-heading mw-heading2"><h2 id="Enhanced_8-bit_binary_compatible_microcontroller:_MCS-151_family"><span class="anchor" id="MCS-151"></span>Enhanced 8-bit binary compatible microcontroller: MCS-151 family</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=20" title="Edit section: Enhanced 8-bit binary compatible microcontroller: MCS-151 family"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444" /><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 1.5x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Intel_MCS-51&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">May 2013</span>)</i></span></div></td></tr></tbody></table> <p>In 1996 Intel announced the MCS-151 family, an up to 6 times faster variant,<sup id="cite_ref-1+2-51_3-1" class="reference"><a href="#cite_note-1+2-51-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> that's fully binary and <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a> compatible with 8051. Unlike their 8051 MCS-151 is a pipelined CPU, with 16-bit internal code bus and is 6x the speed. The MCS-151 family was also discontinued by Intel, but is widely available in binary compatible and partly enhanced variants. </p> <div class="mw-heading mw-heading2"><h2 id="8/16/32-bit_binary_compatible_microcontroller:_MCS-251_family"><span id="8.2F16.2F32-bit_binary_compatible_microcontroller:_MCS-251_family"></span><span class="anchor" id="MCS-251"></span>8/16/32-bit binary compatible microcontroller: MCS-251 family</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=21" title="Edit section: 8/16/32-bit binary compatible microcontroller: MCS-251 family"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444" /><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 1.5x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Intel_MCS-51&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">May 2013</span>)</i></span></div></td></tr></tbody></table> <p>The 80251 8/16/32-bit microcontroller with 16 MB (<a href="/wiki/24-bit" class="mw-redirect" title="24-bit">24-bit</a>) address-space and 6 times faster instruction cycle was introduced by Intel in 1996.<sup id="cite_ref-1+2-51_3-2" class="reference"><a href="#cite_note-1+2-51-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> It can perform as an 8-bit 8051, has 24-bit <a href="/wiki/Linear_addressing" class="mw-redirect" title="Linear addressing">linear addressing</a>, an 8-bit ALU, 8-bit instructions, 16-bit instructions, a limited set of 32-bit instructions, 16 8-bit registers, 16 16-bit registers (8 16-bit registers which do not share space with any 8-bit registers, and 8 16-bit registers which contain 2 8-bit registers per 16-bit register), and 10 32-bit registers (2 dedicated 32-bit registers, and 8 32-bit registers which contain 2 16-bit registers per 32-bit register).<sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> </p><p>It features extended instructions<sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> – see also the programmer's guide<sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup> – and later variants with higher performance,<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup> also available as intellectual property (IP).<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup> It is 3-stage pipelined. The MCS-251 family was also discontinued by Intel, but is widely available in binary compatible and partly enhanced variants from many manufacturers. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=22" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/DS80C390" title="DS80C390">DS80C390</a></li> <li><a href="/wiki/Hitachi_HD44780" class="mw-redirect" title="Hitachi HD44780">Hitachi HD44780</a> - LCD controller with XRAM-compatible interface</li> <li><a href="/wiki/Intel_PL/M-51" class="mw-redirect" title="Intel PL/M-51">Intel PL/M-51</a></li> <li><a href="/wiki/Intel_system_development_kit#Intel_SDK-51" title="Intel system development kit">SDK-51 system design kit</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=23" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFJohn_Wharton1980" class="citation web cs1"><a href="/wiki/John_H._Wharton" class="mw-redirect" title="John H. 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Retrieved <span class="nowrap">2017-08-22</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Download+link+Youtube%3A+ELEC2700+%E2%80%93+8051+Ultrasonic+Radar&rft_id=http%3A%2F%2Fplay.tojsiab.com%2FWFhtU3d2djNXckUz&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-15">^</a></b></span> <span class="reference-text">Archived at <a rel="nofollow" class="external text" href="https://ghostarchive.org/varchive/youtube/20211205/H9sDn89EvD8">Ghostarchive</a> and the <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200608025501/https://www.youtube.com/watch?v=H9sDn89EvD8&gl=US&hl=en">Wayback Machine</a>: <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=H9sDn89EvD8">"ELEC2700 Assignment 1 2014: 1D Pong"</a>. <i><a href="/wiki/YouTube" title="YouTube">YouTube</a></i>. 10 April 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=YouTube&rft.atitle=ELEC2700+Assignment+1+2014%3A+1D+Pong&rft.date=2014-04-10&rft_id=https%3A%2F%2Fwww.youtube.com%2Fwatch%3Fv%3DH9sDn89EvD8&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-16">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20170727171633/https://www.zookal.com/">"ELEC2700 – Computer Engineering 2 (University of Newcastle Textbooks)"</a>. <i>Zookal</i>. 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Retrieved <span class="nowrap">2017-08-22</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Zookal&rft.atitle=ELEC2700+%E2%80%93+Computer+Engineering+2+%28University+of+Newcastle+Textbooks%29&rft_id=https%3A%2F%2Fwww.zookal.com%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-17">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://s3.amazonaws.com/f01.justanswer.com/88willy/2012-06-29_065532_assignment_03.pdf">"ELEC2700 Assignment 3: Ultrasonic Radar"</a> <span class="cs1-format">(PDF)</span>. <i>JustAnswer</i>. 29 June 2012<span class="reference-accessdate">. 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Keil, a division of ARM Inc. 2021<span class="reference-accessdate">. Retrieved <span class="nowrap">17 May</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Keil+C51+Users%27+Manual&rft.pub=Keil%2C+a+division+of+ARM+Inc.&rft.date=2021&rft_id=https%3A%2F%2Fwww.keil.com%2Fc51%2Fman%2Fc51.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-19"><span class="mw-cite-backlink"><b><a href="#cite_ref-19">^</a></b></span> <span class="reference-text">ACALL is a 2-byte subroutine calling instruction, it can access locations within the same 2<span class="nowrap"> </span>KB segment of memory. The absolute memory address is formed by the high 5 bits of the PC and the 11 bits defined by the instruction.</span> </li> <li id="cite_note-teridian-20"><span class="mw-cite-backlink">^ <a href="#cite_ref-teridian_20-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-teridian_20-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.silergy.com/download/upload/pdffile/71M6513_DS_Rev4.pdf/2673">"Silergy 71M6513 Data sheet"</a>. <i>Silergy electricity metering ICs</i>. Silergy Corp<span class="reference-accessdate">. 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Retrieved <span class="nowrap">2013-05-06</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=TI+Delivers+new+low-cost%2C+high-performance+audio+DSP+for+Home+and+Car+w%2F+8051&rft_id=http%3A%2F%2Fwww.8052.com%2Fnews%3FNEWSID%3D61&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-47"><span class="mw-cite-backlink"><b><a href="#cite_ref-47">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.keil.com/dd/docs/datashts/atmel/at85c51snd3.pdf">"Atmel AT85C51SND3 Audio DSP Data Sheet with USB 2.0"</a> <span class="cs1-format">(PDF)</span><span class="reference-accessdate">. Retrieved <span class="nowrap">30 April</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Atmel+AT85C51SND3+Audio+DSP+Data+Sheet+with+USB+2.0&rft_id=http%3A%2F%2Fwww.keil.com%2Fdd%2Fdocs%2Fdatashts%2Fatmel%2Fat85c51snd3.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-48"><span class="mw-cite-backlink"><b><a href="#cite_ref-48">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFSalimOthmanAli2006" class="citation book cs1">Salim, A.J.; Othman, M.; Ali, M.A. Mohd (October 5, 2006). "Integration of 8051 With DSP in Xilinx FPGA". <i>2006 IEEE International Conference on Semiconductor Electronics</i>. pp. <span class="nowrap">562–</span>566. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FSMELEC.2006.380694">10.1109/SMELEC.2006.380694</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-7803-9730-4" title="Special:BookSources/0-7803-9730-4"><bdi>0-7803-9730-4</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:21616742">21616742</a> – via IEEE Xplore.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Integration+of+8051+With+DSP+in+Xilinx+FPGA&rft.btitle=2006+IEEE+International+Conference+on+Semiconductor+Electronics&rft.pages=%3Cspan+class%3D%22nowrap%22%3E562-%3C%2Fspan%3E566&rft.date=2006-10-05&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A21616742%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FSMELEC.2006.380694&rft.isbn=0-7803-9730-4&rft.aulast=Salim&rft.aufirst=A.J.&rft.au=Othman%2C+M.&rft.au=Ali%2C+M.A.+Mohd&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-49"><span class="mw-cite-backlink"><b><a href="#cite_ref-49">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFKenneth_J_Ayala2005" class="citation book cs1">Kenneth J Ayala (2005). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=l6lveWkWqFoC&dq=intel+80251&pg=PA400"><i>The 8051 microcontroller</i></a>. Thomson Delmar Learning. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4018-6158-2" title="Special:BookSources/978-1-4018-6158-2"><bdi>978-1-4018-6158-2</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=The+8051+microcontroller&rft.pub=Thomson+Delmar+Learning&rft.date=2005&rft.isbn=978-1-4018-6158-2&rft.au=Kenneth+J+Ayala&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3Dl6lveWkWqFoC%26dq%3Dintel%2B80251%26pg%3DPA400&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-50"><span class="mw-cite-backlink"><b><a href="#cite_ref-50">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Intel/MCS51/DATASHTS/27262001.PDF">"MCSÉ 251 Architecture Overview"</a> <span class="cs1-format">(PDF)</span>. <i>chipdb.org</i><span class="reference-accessdate">. Retrieved <span class="nowrap">30 April</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=chipdb.org&rft.atitle=MCS%C3%89+251+Architecture+Overview&rft_id=http%3A%2F%2Fdatasheets.chipdb.org%2FIntel%2FMCS51%2FDATASHTS%2F27262001.PDF&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-51"><span class="mw-cite-backlink"><b><a href="#cite_ref-51">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://pe2bz.philpem.me.uk/pdf%20on%20typenumber/A-C/C251.pdf">"Temic TSC80251 Architecture"</a> <span class="cs1-format">(PDF)</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Temic+TSC80251+Architecture&rft_id=http%3A%2F%2Fpe2bz.philpem.me.uk%2Fpdf%2520on%2520typenumber%2FA-C%2FC251.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-52"><span class="mw-cite-backlink"><b><a href="#cite_ref-52">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160304051710/http://www.cs.unc.edu/~vicci/comp261/project/mcu/80251_prog_man.pdf">"Atmel TSC80251 Programmers Guide"</a> <span class="cs1-format">(PDF)</span>. Archived from <a rel="nofollow" class="external text" href="http://www.cs.unc.edu/~vicci/comp261/project/mcu/80251_prog_man.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2016-03-04<span class="reference-accessdate">. Retrieved <span class="nowrap">2013-05-06</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Atmel+TSC80251+Programmers+Guide&rft_id=http%3A%2F%2Fwww.cs.unc.edu%2F~vicci%2Fcomp261%2Fproject%2Fmcu%2F80251_prog_man.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-53"><span class="mw-cite-backlink"><b><a href="#cite_ref-53">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://dcd.pl/workspace/documentation/lat/dq80251_ds.pdf">"DQ80251 32bit Microcontroller"</a> <span class="cs1-format">(PDF)</span>. <i>DCD</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=DCD&rft.atitle=DQ80251+32bit+Microcontroller&rft_id=http%3A%2F%2Fdcd.pl%2Fworkspace%2Fdocumentation%2Flat%2Fdq80251_ds.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></span> </li> <li id="cite_note-54"><span class="mw-cite-backlink"><b><a href="#cite_ref-54">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.evatronix.pl/products/pdf/r80251xc_datasheet.pdf">"R80251XC 32bit Microcontroller"</a> <span class="cs1-format">(PDF)</span>. <i>Evatronix</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Evatronix&rft.atitle=R80251XC+32bit+Microcontroller&rft_id=http%3A%2F%2Fwww.evatronix.pl%2Fproducts%2Fpdf%2Fr80251xc_datasheet.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span><sup class="noprint Inline-Template"><span style="white-space: nowrap;">[<i><a href="/wiki/Wikipedia:Link_rot" title="Wikipedia:Link rot"><span title=" Dead link tagged October 2018">dead link</span></a></i><span style="visibility:hidden; color:transparent; padding-left:2px">‍</span>]</span></sup></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=24" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <dl><dt>Books</dt></dl> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFMazidiMcKinlayMazidi2012" class="citation book cs1">Mazidi; McKinlay; Mazidi (2012). <i>The 8051 Microcontroller: A Systems Approach</i>. Pearson. 648 pp. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-13-508044-3" title="Special:BookSources/978-0-13-508044-3"><bdi>978-0-13-508044-3</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=The+8051+Microcontroller%3A+A+Systems+Approach&rft.pages=648+pp.&rft.pub=Pearson&rft.date=2012&rft.isbn=978-0-13-508044-3&rft.au=Mazidi&rft.au=McKinlay&rft.au=Mazidi&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFSchultz2008" class="citation book cs1">Schultz, Thomas (2008). <i>C and the 8051</i> (4th ed.). Thomas W. Schultz. 464 pp. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-9783995-0-4" title="Special:BookSources/978-0-9783995-0-4"><bdi>978-0-9783995-0-4</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=C+and+the+8051&rft.pages=464+pp.&rft.edition=4th&rft.pub=Thomas+W.+Schultz&rft.date=2008&rft.isbn=978-0-9783995-0-4&rft.aulast=Schultz&rft.aufirst=Thomas&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFSteiner2005" class="citation book cs1">Steiner, Craig (2005). <i>The 8051/8052 Microcontroller: Architecture, Assembly Language, and Hardware Interfacing</i>. Universal-Publishers. 348 pp. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-58112-459-0" title="Special:BookSources/978-1-58112-459-0"><bdi>978-1-58112-459-0</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=The+8051%2F8052+Microcontroller%3A+Architecture%2C+Assembly+Language%2C+and+Hardware+Interfacing&rft.pages=348+pp.&rft.pub=Universal-Publishers&rft.date=2005&rft.isbn=978-1-58112-459-0&rft.aulast=Steiner&rft.aufirst=Craig&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFCalcuttCowanParchizadeh2000" class="citation book cs1">Calcutt; Cowan; Parchizadeh (2000). <i>8051 Microcontrollers: Hardware, Software and Applications</i>. Elsevier. 329 pp. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-340-67707-0" title="Special:BookSources/978-0-340-67707-0"><bdi>978-0-340-67707-0</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=8051+Microcontrollers%3A+Hardware%2C+Software+and+Applications&rft.pages=329+pp.&rft.pub=Elsevier&rft.date=2000&rft.isbn=978-0-340-67707-0&rft.au=Calcutt&rft.au=Cowan&rft.au=Parchizadeh&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFAxelson1994" class="citation book cs1"><a href="/wiki/Jan_Axelson" title="Jan Axelson">Axelson, Jan</a> (1994). <i>The Microcontroller Idea Book: Circuits, Programs, and Applications featuring the 8052-BASIC Microcontroller</i>. Lakeview research LLC. 277 pp. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-9650819-0-0" title="Special:BookSources/978-0-9650819-0-0"><bdi>978-0-9650819-0-0</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=The+Microcontroller+Idea+Book%3A+Circuits%2C+Programs%2C+and+Applications+featuring+the+8052-BASIC+Microcontroller&rft.pages=277+pp.&rft.pub=Lakeview+research+LLC&rft.date=1994&rft.isbn=978-0-9650819-0-0&rft.aulast=Axelson&rft.aufirst=Jan&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFPayne1990" class="citation book cs1">Payne, William (December 19, 1990) [1990]. <i>Embedded Controller FORTH for the 8051 Family</i> (hardcover). Boston: Academic Press. 528 pp. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-12-547570-9" title="Special:BookSources/978-0-12-547570-9"><bdi>978-0-12-547570-9</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Embedded+Controller+FORTH+for+the+8051+Family&rft.place=Boston&rft.pages=528+pp.&rft.pub=Academic+Press&rft.date=1990-12-19&rft.isbn=978-0-12-547570-9&rft.aulast=Payne&rft.aufirst=William&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span></li></ul> <dl><dt>Intel</dt></dl> <ul><li><i><a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Intel/MCS51/MANUALS/27238302.PDF">MCS-51 Microcontroller Family User's Manual</a></i>; Intel; 1994; publication number 121517.</li> <li><i>MCS-51 Macro Assembler User's Guide</i>; Intel; publication number 9800937.</li> <li><i>8-Bit Embedded Controllers</i>; Intel; 1991; publication number 270645-003.</li> <li><i>Microcontroller Handbook</i>; Intel; 1984; publication number 210918-002.</li> <li><i><a rel="nofollow" class="external text" href="https://archive.org/details/bitsavers_intel80518liminaryArchitecturalSpecificationMay80_6120863/">8051 Microcontroller Preliminary Architectural Specification and Functional Description</a></i>; Intel; 44 pages; 1980.</li></ul> <dl><dt>Misc</dt></dl> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFHennig-Roleff1993" class="citation web cs1 cs1-prop-foreign-lang-source">Hennig-Roleff, Werner (1993-02-01) [1988]. <a rel="nofollow" class="external text" href="http://spot.fho-emden.de/ftp/micro/sim51_04.zip">"HEX.DOC: EASM51 - HEX Format (elektor Assembler)"</a>. <i>SIM51</i>. 1.04 (in German). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170811161238/http://spot.fho-emden.de/ftp/micro/sim51_04.zip">Archived</a> from the original on 2017-08-11<span class="reference-accessdate">. Retrieved <span class="nowrap">2021-12-08</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=SIM51&rft.atitle=HEX.DOC%3A+EASM51+-+HEX+Format+%28elektor+Assembler%29&rft.date=1993-02-01&rft.aulast=Hennig-Roleff&rft.aufirst=Werner&rft_id=http%3A%2F%2Fspot.fho-emden.de%2Fftp%2Fmicro%2Fsim51_04.zip&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+MCS-51" class="Z3988"></span> <a rel="nofollow" class="external autonumber" href="https://web.archive.org/web/20210806202253/https://www.dos4ever.com/8031board/SIM51D_BASIC.zip">[1]</a><a rel="nofollow" class="external autonumber" href="https://web.archive.org/web/20210806202253/https://www.dos4ever.com/8031board/SIM51_06.zip">[2]</a> (Besides the <a href="/w/index.php?title=Elektor_assembler_hex_format&action=edit&redlink=1" class="new" title="Elektor assembler hex format (page does not exist)">EASM</a> format, the HEX.DOC file discusses various hex file formats by <a href="/wiki/Intel_HEX" title="Intel HEX">Intel</a>, <a href="/wiki/SREC_(file_format)" title="SREC (file format)">Motorola</a>, <a href="/wiki/Tektronix_hex_format" title="Tektronix hex format">Tektronix</a>, <a href="/wiki/MOS_Technology_file_format" title="MOS Technology file format">MOS Technology</a> and <a href="/wiki/Elektor" title="Elektor">elektor</a>.)</li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_MCS-51&action=edit&section=25" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><span class="noviewer" typeof="mw:File"><a href="/wiki/File:Commons-logo.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/20px-Commons-logo.svg.png" decoding="async" width="12" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/40px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></a></span> Media related to <a href="https://commons.wikimedia.org/wiki/Category:MCS-51" class="extiw" title="commons:Category:MCS-51">MCS-51</a> at Wikimedia Commons </p> <ul><li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20101123154437/http://ikalogic.com/tut_8051_1.php">Complete tutorial for 8051 microcontrollers</a></li> <li><a rel="nofollow" class="external text" href="http://www.edsim51.com/">the source website for tutorials and simulator for 8051</a></li> <li><a rel="nofollow" class="external text" href="http://www.dnatechindia.com/Tutorial/8051-Tutorial.html">Basic 8051 Interfacing Circuits</a></li> <li><a rel="nofollow" class="external text" href="http://www.oreganosystems.at/?page_id=96">Open source VHDL 8051 implementation (Oregano Systems)</a></li></ul> <div class="navbox-styles"><style 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Intel</a></div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_MCS-48" title="Intel MCS-48">MCS-48 (8048 family)</a></li> <li><a class="mw-selflink selflink">MCS-51 (8051 family)</a></li> <li><a href="/wiki/Intel_MCS-151" class="mw-redirect" title="Intel MCS-151">MCS-151 (80151 family)</a></li> <li><a href="/wiki/Intel_MCS-251" class="mw-redirect" title="Intel MCS-251">MCS-251 (80251 family)</a></li> <li><a href="/wiki/Intel_8061" title="Intel 8061">8061</a></li> <li><a href="/wiki/Intel_MCS-96" title="Intel MCS-96">MCS-96 (8x196 family)</a></li> <li><a href="/wiki/Intel_MCS-296" title="Intel MCS-296">MCS-296 (8x296 family)</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235" /></div><div role="navigation" class="navbox" aria-labelledby="Microcontrollers126" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231" /><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Microcontrollers" title="Template:Microcontrollers"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Microcontrollers" title="Template talk:Microcontrollers"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Microcontrollers" title="Special:EditPage/Template:Microcontrollers"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Microcontrollers126" style="font-size:114%;margin:0 4em"><a href="/wiki/Microcontroller" title="Microcontroller">Microcontrollers</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Main</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-board_microcontroller" title="Single-board microcontroller">Single-board microcontroller</a></li> <li><a href="/wiki/Special_function_register" title="Special function register">Special function register</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Microarchitecture" title="Microarchitecture">Architectures</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">68000</a></li> <li><a href="/wiki/Intel_8051" class="mw-redirect" title="Intel 8051">8051</a></li> <li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/AVR_microcontrollers" title="AVR microcontrollers">AVR</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/TI_MSP430" title="TI MSP430">MPS430</a></li> <li><a href="/wiki/PIC_microcontrollers" title="PIC microcontrollers">PIC</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/X86" title="X86">x86</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word length</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Am2900" title="AMD Am2900">Am2900</a></li> <li><a href="/wiki/COP400" title="COP400">COP400</a></li> <li>MARC4</li> <li><a href="/wiki/Rockwell_PPS-4" title="Rockwell PPS-4">PPS-4</a></li> <li><a href="/wiki/S1C6x" title="S1C6x">S1C6x</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-47</a></li> <li><a href="/wiki/Texas_Instruments_TMS1000" title="Texas Instruments TMS1000">TMS1000</a></li> <li><a href="/wiki/%CE%9CCOM-4" class="mw-redirect" title="ΜCOM-4">μCOM-4</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_6800" title="Motorola 6800">6800</a> <ul><li><a href="/wiki/Motorola_68HC05" title="Motorola 68HC05">68HC05</a></li> <li><a href="/wiki/Motorola_68HC08" title="Motorola 68HC08">68HC08</a></li> <li><a href="/wiki/Motorola_68HC11" title="Motorola 68HC11">68HC11</a></li> <li><a href="/wiki/Freescale_S08" class="mw-redirect" title="Freescale S08">S08</a></li> <li><a href="/wiki/Freescale_RS08" title="Freescale RS08">RS08</a></li></ul></li> <li><a href="/wiki/MOS_Technology_6502" title="MOS Technology 6502">6502</a> <ul><li><a href="/wiki/WDC_65C134" title="WDC 65C134">65C134</a></li> <li><a href="/wiki/WDC_65C265" title="WDC 65C265">65C265</a></li> <li><a href="/wiki/Mitsubishi_740" title="Mitsubishi 740">MELPS 740</a></li></ul></li> <li><a href="/wiki/78K" title="78K">78K</a></li> <li><a href="/wiki/Intel_MCS-48" title="Intel MCS-48">8048</a></li> <li><a href="/wiki/Intel_8051" class="mw-redirect" title="Intel 8051">8051</a> <ul><li><a href="/wiki/XC800_family" title="XC800 family">XC800</a></li></ul></li> <li><a href="/wiki/AVR_microcontrollers" title="AVR microcontrollers">AVR</a></li> <li><a href="/wiki/COP8" title="COP8">COP8</a></li> <li><a href="/wiki/H8_Family" title="H8 Family">H8</a></li> <li><a href="/wiki/PIC_microcontroller" class="mw-redirect" title="PIC microcontroller">PIC10/12/16/17/18</a></li> <li><a href="/wiki/ST6_and_ST7" title="ST6 and ST7">ST6/ST7</a></li> <li><a href="/wiki/STM8" title="STM8">STM8</a></li> <li><a href="/wiki/Zilog_Z8" title="Zilog Z8">Z8</a></li> <li><a href="/wiki/Zilog_Z80" title="Zilog Z80">Z80</a> <ul><li><a href="/wiki/Zilog_eZ80" title="Zilog eZ80">eZ80</a></li> <li><a href="/wiki/Rabbit_2000" title="Rabbit 2000">Rabbit 2000</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-870</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/WDC_65C816" title="WDC 65C816">65C816</a></li> <li><a href="/wiki/Freescale_68HC12" class="mw-redirect" title="Freescale 68HC12">68HC12</a>/<a href="/wiki/Freescale_68HC16" class="mw-redirect" title="Freescale 68HC16">16</a></li> <li><a href="/wiki/Intel_80186" title="Intel 80186">80186</a></li> <li><a href="/wiki/C166_family" title="C166 family">C166</a></li> <li><a href="/wiki/CompactRISC" title="CompactRISC">CR16/C</a></li> <li><a href="/wiki/H8_Family" title="H8 Family">H8S</a></li> <li><a href="/wiki/TI_MSP430" title="TI MSP430">MSP430</a></li> <li><a href="/wiki/PIC_microcontroller#PIC24_and_dsPIC" class="mw-redirect" title="PIC microcontroller">PIC24/dsPIC</a></li> <li><a href="/wiki/R8C" title="R8C">R8C</a></li> <li><a href="/wiki/RL78" title="RL78">RL78</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-900</a></li> <li><a href="/wiki/Zilog_Z8000" title="Zilog Z8000">Z8000</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Am29000" title="AMD Am29000">Am29000</a></li> <li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/List_of_applications_of_ARM_cores" class="mw-redirect" title="List of applications of ARM cores">ARM</a> <a href="/wiki/ARM_Cortex-M" title="ARM Cortex-M">Cortex-M</a> <ul><li><a href="/wiki/EFM32" title="EFM32">EFM32</a></li> <li><a href="/wiki/NXP_LPC" title="NXP LPC">LPC</a></li> <li><a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a></li> <li><a href="/wiki/STM32" title="STM32">STM32</a></li> <li><a href="/wiki/Infineon_XMC" title="Infineon XMC">XMC</a></li></ul></li> <li><a href="/wiki/ARM_Cortex-R" title="ARM Cortex-R">ARM Cortex-R</a></li> <li><a href="/wiki/AVR32" title="AVR32">AVR32</a></li> <li><a href="/wiki/CompactRISC" title="CompactRISC">CRX</a></li> <li><a href="/wiki/Fujitsu_FR" title="Fujitsu FR">FR</a></li> <li><a href="/wiki/FR-V_(microprocessor)" title="FR-V (microprocessor)">FR-V</a></li> <li><a href="/wiki/H8_Family" title="H8 Family">H8SX</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/MN103" title="MN103">MN103</a></li> <li><a href="/wiki/Motorola_68000" title="Motorola 68000">68000</a> <ul><li><a href="/wiki/NXP_ColdFire" title="NXP ColdFire">ColdFire</a></li></ul></li> <li><a href="/wiki/PIC_microcontroller#PIC32MX" class="mw-redirect" title="PIC microcontroller">PIC32</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> <ul><li><a href="/wiki/MPC5xx" title="MPC5xx">MPC5xx</a></li></ul></li> <li><a href="/wiki/Parallax_Propeller" title="Parallax Propeller">Propeller</a></li> <li><a href="/wiki/SuperH" title="SuperH">SuperH</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-900</a></li> <li><a href="/wiki/Infineon_TriCore" title="Infineon TriCore">TriCore</a></li> <li><a href="/wiki/V850" title="V850">V850</a></li> <li><a href="/wiki/RX_microcontroller_family" class="mw-redirect" title="RX microcontroller family">RX</a></li> <li><a href="/wiki/Tensilica" title="Tensilica">Xtensa</a></li> <li><a href="/wiki/Zilog_Z80000" title="Zilog Z80000">Z80000</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_Cortex-R" title="ARM Cortex-R">ARM Cortex-R</a></li> <li><a href="/wiki/PowerPC#64-bit_PowerPC" title="PowerPC">PowerPC64</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Interfaces</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Programming</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/In-system_programming" title="In-system programming">In-circuit serial programming</a> (ICSP)</li> <li><a href="/wiki/In-system_programming" title="In-system programming">In-system programming</a> (ISP)</li> <li><a href="/wiki/AVR_microcontrollers#PDI" title="AVR microcontrollers">Program and Debug Interface</a> (PDI)</li> <li><a href="/wiki/AVR_microcontrollers#High_voltage_serial" title="AVR microcontrollers">High-voltage serial programming</a> (HVSP)</li> <li><a href="/wiki/AVR_microcontrollers#High_voltage_parallel" title="AVR microcontrollers">High voltage parallel programming</a> (HVPP)</li> <li><a href="/wiki/AVR_microcontrollers#Bootloader" title="AVR microcontrollers">Bootloader</a></li> <li><a href="/wiki/AVR_microcontrollers#ROM" title="AVR microcontrollers">ROM</a></li> <li><a href="/wiki/AVR_microcontrollers#aWire" title="AVR microcontrollers">aWire</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Debugging</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Nexus_(standard)" title="Nexus (standard)">Nexus (standard)</a></li> <li><a href="/wiki/JTAG" title="JTAG">Joint Test Action Group</a> (JTAG) <ul><li><a href="/wiki/DebugWIRE" title="DebugWIRE">debugWIRE</a> (Atmel)</li></ul></li> <li><a href="/wiki/PIC_microcontroller#In-circuit_debugging" class="mw-redirect" title="PIC microcontroller">In-circuit debugging</a> (ICD)</li> <li><a href="/wiki/In-circuit_emulation" title="In-circuit emulation">In-circuit emulator</a> (ICE)</li> <li><a href="/wiki/In-target_probe" title="In-target probe">In-target probe</a> (ITP)</li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_common_microcontrollers" title="List of common microcontrollers">List of common microcontrollers</a></li> <li>By manufacturer <ul><li><a href="/wiki/Intel_microprocessor#Microcontrollers" class="mw-redirect" title="Intel microprocessor">Intel</a></li> <li><a href="/wiki/List_of_Freescale_products#Microcontrollers" class="mw-redirect" title="List of Freescale products">NXP/Freescale</a></li> <li><a href="/wiki/List_of_common_microcontrollers#Infineon" title="List of common microcontrollers">Infineon</a></li> <li><a href="/wiki/Renesas_Electronics#Products" title="Renesas Electronics">Renesas Electronics</a></li></ul></li> <li><a href="/wiki/List_of_Wi-Fi_microcontrollers" title="List of Wi-Fi microcontrollers">List of Wi-Fi microcontrollers</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">See also</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Programmable_logic_controller" title="Programmable logic controller">Programmable logic controller</a></li> <li><a href="/wiki/List_of_microprocessors" title="List of microprocessors">List of microprocessors</a></li></ul> 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