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<!DOCTYPE html> <html lang="en"> <head> <meta content="text/html; charset=utf-8" http-equiv="content-type"/> <title>Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI</title>  <meta content="width=device-width, initial-scale=1, shrink-to-fit=no" name="viewport"/> <link href="https://cdn.jsdelivr.net/npm/bootstrap@5.3.0/dist/css/bootstrap.min.css" rel="stylesheet" type="text/css"/> <link href="/static/browse/0.3.4/css/ar5iv.0.7.9.min.css" rel="stylesheet" type="text/css"/> <link href="/static/browse/0.3.4/css/ar5iv-fonts.0.7.9.min.css" rel="stylesheet" type="text/css"/> <link href="/static/browse/0.3.4/css/latexml_styles.css" rel="stylesheet" type="text/css"/> <script src="https://cdn.jsdelivr.net/npm/bootstrap@5.3.0/dist/js/bootstrap.bundle.min.js"></script> <script src="https://cdnjs.cloudflare.com/ajax/libs/html2canvas/1.3.3/html2canvas.min.js"></script> <script src="/static/browse/0.3.4/js/addons_new.js"></script> <script src="/static/browse/0.3.4/js/feedbackOverlay.js"></script> <meta content=" Analog Design, Automation, LLM " lang="en" name="keywords"/> <base href="/html/2411.14299v4/"/></head> <body> <nav class="ltx_page_navbar"> <nav class="ltx_TOC"> <ol class="ltx_toclist"> <li class="ltx_tocentry ltx_tocentry_section"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S1" title="In Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">I </span><span class="ltx_text ltx_font_smallcaps">Introduction</span></span></a></li> <li class="ltx_tocentry ltx_tocentry_section"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S2" title="In Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">II </span><span class="ltx_text ltx_font_smallcaps">Related Work</span></span></a></li> <li class="ltx_tocentry ltx_tocentry_section"> <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S3" title="In Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">III </span><span class="ltx_text ltx_font_smallcaps">Key Challenges in SPICE Netlist Extraction</span></span></a> <ol class="ltx_toclist ltx_toclist_section"> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S3.SS1" title="In III Key Challenges in SPICE Netlist Extraction ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref"><span class="ltx_text">III-A</span> </span><span class="ltx_text ltx_font_italic">Can GPT-4o detect electrical components accurately?</span></span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S3.SS2" title="In III Key Challenges in SPICE Netlist Extraction ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref"><span class="ltx_text">III-B</span> </span><span class="ltx_text ltx_font_italic">Can GPT-4o Properly Connect Circuit Components?</span></span></a></li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_section"> <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S4" title="In Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">IV </span><span class="ltx_text ltx_font_smallcaps">Methodology </span></span></a> <ol class="ltx_toclist ltx_toclist_section"> <li class="ltx_tocentry ltx_tocentry_subsection"> <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S4.SS1" title="In IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref"><span class="ltx_text">IV-A</span> </span><span class="ltx_text ltx_font_italic">Labeling Analog Circuit</span></span></a> <ol class="ltx_toclist ltx_toclist_subsection"> <li class="ltx_tocentry ltx_tocentry_subsubsection"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S4.SS1.SSS1" title="In IV-A Labeling Analog Circuit ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref"><span class="ltx_text">IV-A</span>1 </span>Detection of Circuit Components</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsubsection"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S4.SS1.SSS2" title="In IV-A Labeling Analog Circuit ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref"><span class="ltx_text">IV-A</span>2 </span>Net Detection</span></a></li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S4.SS2" title="In IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref"><span class="ltx_text">IV-B</span> </span><span class="ltx_text ltx_font_italic">Prompt Tuning</span></span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S4.SS3" title="In IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref"><span class="ltx_text">IV-C</span> </span><span class="ltx_text ltx_font_italic">SPICE netlist verification</span></span></a></li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_section"> <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S5" title="In Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">V </span><span class="ltx_text ltx_font_smallcaps">Results</span></span></a> <ol class="ltx_toclist ltx_toclist_section"> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S5.SS1" title="In V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref"><span class="ltx_text">V-A</span> </span><span class="ltx_text ltx_font_italic">Dataset Creation</span></span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S5.SS2" title="In V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref"><span class="ltx_text">V-B</span> </span><span class="ltx_text ltx_font_italic">Evaluation</span></span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S5.SS3" title="In V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref"><span class="ltx_text">V-C</span> </span><span class="ltx_text ltx_font_italic">Verifying against AMSNet <cite class="ltx_cite ltx_citemacro_cite">[<span class="ltx_ref">13</span>]</cite> netlists</span></span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S5.SS4" title="In V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref"><span class="ltx_text">V-D</span> </span><span class="ltx_text ltx_font_italic">Finetuning</span></span></a></li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_section"><a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S6" title="In Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">VI </span><span class="ltx_text ltx_font_smallcaps">Conclusion and Future Work</span></span></a></li> </ol></nav> </nav> <div class="ltx_page_main"> <div class="ltx_page_content"> <article class="ltx_document ltx_authors_1line"> <div class="ltx_para" id="p1"> <span class="ltx_ERROR undefined" id="p1.1">\lst@Key</span> <p class="ltx_p" id="p1.2">numbersnone<span class="ltx_ERROR undefined" id="p1.2.1">\lstKV@SwitchCases</span>#1none: <br class="ltx_break"/>left: <br class="ltx_break"/>right: </p> </div> <h1 class="ltx_title ltx_title_document">Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog <span class="ltx_text ltx_framed ltx_framed_underline" id="id1.id1">C</span>ircuits by <span class="ltx_text ltx_framed ltx_framed_underline" id="id2.id2">H</span>arnessing <span class="ltx_text ltx_framed ltx_framed_underline" id="id3.id3">AI</span> </h1> <div class="ltx_authors"> <span class="ltx_creator ltx_role_author"> <span class="ltx_personname">Jitendra Bhandari1, Vineet Bhat1, Yuheng He2, Hamed Rahmani1, Siddharth Garg1 and Ramesh Karri1 </span><span class="ltx_author_notes"> <span class="ltx_contact ltx_role_affiliation">1New York University Tandon School of Engineering 2Cornell University </span></span></span> </div> <div class="ltx_abstract"> <h6 class="ltx_title ltx_title_abstract">Abstract</h6> <p class="ltx_p" id="id4.id1">Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists. It addresses a long-standing challenge in automating netlist generation for analog circuits within circuit design automation. Automating this workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate the multi-modal capabilities of state-of-the-art LLMs, particularly GPT-4, to address these issues. We propose a three-step workflow to overcome current limitations: labeling analog circuits, prompt tuning, and netlist verification. This approach aims to create an end-to-end SPICE netlist generator from circuit schematic images, tackling the long-standing hurdle of accurate netlist generation. Our framework demonstrates significant performance improvements, tested on approximately 2,100 schematics of varying complexity. We open-source this solution for community-driven development.</p> </div> <div class="ltx_keywords"> <h6 class="ltx_title ltx_title_keywords">Index Terms: </h6> Analog Design, Automation, LLM </div> <section class="ltx_section" id="S1"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">I </span><span class="ltx_text ltx_font_smallcaps" id="S1.1.1">Introduction</span> </h2> <div class="ltx_para" id="S1.p1"> <p class="ltx_p" id="S1.p1.1">Large Language Models (LLMs) have received significant attention due to their wide-ranging applications, from text summarization to code generation, and have a growing impact across various fields. For hardware design, LLMs have primarily demonstrated potential in the digital domain. This includes tasks such as Verilog code generation <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib1" title="">1</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib2" title="">2</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib3" title="">3</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib4" title="">4</a>]</cite>, assertion generation <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib5" title="">5</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib6" title="">6</a>]</cite>, bug fixing <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib7" title="">7</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib8" title="">8</a>]</cite>, and electronic design automation (EDA) tool scripting <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib9" title="">9</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib10" title="">10</a>]</cite>. The success of these domain-tailored LLMs relies on access to large and high-quality datasets. For instance, 75K Verilog files from GitHub were used to train the Verigen code generation model <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib4" title="">4</a>]</cite>. Data scraped from Verilog textbooks was also used to improve the performance of LLMs for Verilog <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib4" title="">4</a>]</cite>. Textbooks have also proven useful in other domains, for instance, in systems biology <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib11" title="">11</a>]</cite> and in understanding protein interactions <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib12" title="">12</a>]</cite>.</p> </div> <div class="ltx_para" id="S1.p2"> <p class="ltx_p" id="S1.p2.1">Building on the success of LLMs in the digital domain, it is natural to explore their application in the <span class="ltx_text ltx_font_italic" id="S1.p2.1.1">analog domain</span>, specifically, in the automated generation of analog circuits from natural language specifications. Analog circuits are described in SPICE (and its many variants), the industry-standard textual representation for simulating analog circuits. SPICE is a low-level description that defines the interconnections between analog components like resistors, capacitors, inductors, and transistors. Open-source datasets for SPICE, unfortunately, are very limited compared to Verilog code, creating a gap in research in this area <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib13" title="">13</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib14" title="">14</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib15" title="">15</a>]</cite>. However, analog circuit textbooks and research papers are plentiful and contain a trove of analog circuit diagrams, but these are usually in <em class="ltx_emph ltx_font_italic" id="S1.p2.1.2">image</em> (or figure) format. These images must then be manually converted to SPICE netlists, which is painstaking and time-consuming.</p> </div> <div class="ltx_para" id="S1.p3"> <p class="ltx_p" id="S1.p3.1">To address this issue, a recently proposed method, AMSNet <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib13" title="">13</a>]</cite>, introduced a <em class="ltx_emph ltx_font_italic" id="S1.p3.1.1">semi</em>-automated way to create a SPICE dataset from analog circuit figures using the capabilities of multi-modal LLMs like GPT-4o that take both image and text inputs and produce both image and text outputs. However, AMSNet still requires manual annotations of nets to obtain accurate SPICE netlists. Even with manual annotations, AMSNet still fails to extract accurate netlists of complex circuits (the reasons for this are described in Section <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#S3" title="III Key Challenges in SPICE Netlist Extraction ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">III</span></a>).</p> </div> <div class="ltx_para ltx_noindent" id="S1.p4"> <p class="ltx_p" id="S1.p4.1"><span class="ltx_text ltx_font_bold" id="S1.p4.1.1">Contributions:</span> <span class="ltx_text ltx_font_bold" id="S1.p4.1.2">Masala-CHAI<span class="ltx_note ltx_role_footnote" id="footnote1"><sup class="ltx_note_mark">1</sup><span class="ltx_note_outer"><span class="ltx_note_content"><sup class="ltx_note_mark">1</sup><span class="ltx_tag ltx_tag_note"><span class="ltx_text ltx_font_medium" id="footnote1.1.1.1">1</span></span><span class="ltx_text ltx_font_medium" id="footnote1.9">Masala is the Hindi word for “SPICE”</span></span></span></span></span> is an <em class="ltx_emph ltx_font_italic" id="S1.p4.1.3">automated</em> method for SPICE netlist generation from analog circuit schematics. We incorporate various techniques, including (i) fine-tuned object detectors to extract passive and active components, (ii) deep Hough transform priors to identify nets, (iii) extensive prompt tuning for LLMs to fix common errors in netlist extraction, and (iv) post-extraction verification. We make four contributions:</p> <ol class="ltx_enumerate" id="S1.I1"> <li class="ltx_item" id="S1.I1.i1" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">1.</span> <div class="ltx_para" id="S1.I1.i1.p1"> <p class="ltx_p" id="S1.I1.i1.p1.1">An empirical case study to understand the limitations of state-of-the-art multi-modal LLMs like GPT-4o (shown in AMSNet <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib13" title="">13</a>]</cite>) in SPICE netlist extraction from schematics.</p> </div> </li> <li class="ltx_item" id="S1.I1.i2" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">2.</span> <div class="ltx_para" id="S1.I1.i2.p1"> <p class="ltx_p" id="S1.I1.i2.p1.1">Build <span class="ltx_text ltx_font_bold" id="S1.I1.i2.p1.1.1">Masala-CHAI</span>, the <em class="ltx_emph ltx_font_italic" id="S1.I1.i2.p1.1.2">first fully automated framework using LLMs along with custom-trained deep network models</em> for large-scale SPICE netlist extraction from circuit schematics present in textbooks and papers.</p> </div> </li> <li class="ltx_item" id="S1.I1.i3" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">3.</span> <div class="ltx_para" id="S1.I1.i3.p1"> <p class="ltx_p" id="S1.I1.i3.p1.1">Use Masala-CHAI to collect a dataset of <math alttext="\sim" class="ltx_Math" display="inline" id="S1.I1.i3.p1.1.m1.1"><semantics id="S1.I1.i3.p1.1.m1.1a"><mo id="S1.I1.i3.p1.1.m1.1.1" xref="S1.I1.i3.p1.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S1.I1.i3.p1.1.m1.1b"><csymbol cd="latexml" id="S1.I1.i3.p1.1.m1.1.1.cmml" xref="S1.I1.i3.p1.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S1.I1.i3.p1.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="S1.I1.i3.p1.1.m1.1d">∼</annotation></semantics></math>2,100 SPICE netlists (along with metadata like figure captions) from a sample textbook. We open-source our flow to the community to further research in this area <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib16" title="">16</a>]</cite>.</p> </div> </li> <li class="ltx_item" id="S1.I1.i4" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">4.</span> <div class="ltx_para" id="S1.I1.i4.p1"> <p class="ltx_p" id="S1.I1.i4.p1.1">Fine-tune GPT models using the Masala-CHAI dataset to demonstrate the potential use-case of the dataset in automated SPICE netlist generation from English prompts.</p> </div> </li> </ol> </div> </section> <section class="ltx_section" id="S2"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">II </span><span class="ltx_text ltx_font_smallcaps" id="S2.1.1">Related Work</span> </h2> <div class="ltx_para" id="S2.p1"> <p class="ltx_p" id="S2.p1.1">LLMs have gained significant attention in chip design <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib17" title="">17</a>]</cite>. Significant progress has been made in improving Verilog code generation <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib1" title="">1</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib2" title="">2</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib3" title="">3</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib4" title="">4</a>]</cite>, with studies introducing new methodologies that enhance the quality of generated Verilog code. These advances demonstrate how LLMs can streamline and improve digital hardware design workflows. In addition to code generation, prompt engineering has proven effective in chip design <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib18" title="">18</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib19" title="">19</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib20" title="">20</a>]</cite>. By using LLMs, researchers have conceptualized and designed complex digital hardware architectures efficiently, facilitating faster and more accurate chip development. Beyond code generation, LLMs have found applications in assistant chatbots, script generation, and bug analysis <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib10" title="">10</a>]</cite>. Similarly, <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib9" title="">9</a>]</cite> explores LLMs in planning and executing tasks in the Electronic Design Automation (EDA) flow. The use of LLMs in generating assertions and testbenches for verifying the correctness of Integrated Circuit (IC) designs has also seen notable improvements <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib5" title="">5</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib6" title="">6</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib8" title="">8</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib7" title="">7</a>]</cite>.</p> </div> <div class="ltx_para" id="S2.p2"> <p class="ltx_p" id="S2.p2.1"><cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib21" title="">21</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib22" title="">22</a>]</cite> have explored schematic-to-netlist generation using ML-based approaches. However, these solutions are not reproducible due to the unavailability of any open-source implementation. Recent advancements have extended LLM applications into analog design. Closed-loop Python code generation for analog circuits using LLM agents has shown promising results <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib14" title="">14</a>]</cite>. LLMs have also demonstrated the ability to generate various circuit topologies from given specifications <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib23" title="">23</a>]</cite>. Furthermore, a dataset for exploring SPICE netlist generation was recently released in <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib13" title="">13</a>]</cite>. However, existing approaches require manual modifications of circuit schematics, which significantly limits their scalability for large-scale applications.</p> </div> </section> <section class="ltx_section" id="S3"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">III </span><span class="ltx_text ltx_font_smallcaps" id="S3.1.1">Key Challenges in SPICE Netlist Extraction</span> </h2> <div class="ltx_para" id="S3.p1"> <p class="ltx_p" id="S3.p1.1">Despite advances in multi-modal LLM, as demonstrated by AMSNet <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib13" title="">13</a>]</cite>, current solutions like GPT-4o do not automatically extract accurate SPICE netlists from circuit schematics. Our work begins with an in-depth analysis of the specific failure modes encountered by GPT-4o. Building on these insights, we propose solutions to overcome these limitations, advancing the field toward a fully automated SPICE netlist extraction process that significantly reduces dependence on manual annotations.</p> </div> <section class="ltx_subsection" id="S3.SS1"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection"><span class="ltx_text" id="S3.SS1.5.1.1">III-A</span> </span><span class="ltx_text ltx_font_italic" id="S3.SS1.6.2">Can GPT-4o detect electrical components accurately?</span> </h3> <figure class="ltx_figure" id="S3.F1"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="454" id="S3.F1.g1" src="x1.png" width="872"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S3.F1.2.1.1" style="font-size:90%;">Figure 1</span>: </span><span class="ltx_text" id="S3.F1.3.2" style="font-size:90%;">GPT-4o responses when asked to list all components in three sample circuit schematics.</span></figcaption> </figure> <figure class="ltx_figure" id="S3.F2"><svg class="ltx_picture ltx_centering" height="78.25" id="S3.F2.pic1" overflow="visible" version="1.1" width="600"><g fill="#000000" stroke="#000000" stroke-width="0.4pt" transform="translate(0,78.25) matrix(1 0 0 -1 0 0)"><g fill="#000000" fill-opacity="1.0"><path d="M 0 6.6 L 0 71.65 C 0 75.29 2.95 78.25 6.6 78.25 L 593.4 78.25 C 597.05 78.25 600 75.29 600 71.65 L 600 6.6 C 600 2.95 597.05 0 593.4 0 L 6.6 0 C 2.95 0 0 2.95 0 6.6 Z" style="stroke:none"></path></g><g fill="#FFFFFF" fill-opacity="1.0"><path d="M 0.69 6.6 L 0.69 71.65 C 0.69 74.91 3.34 77.56 6.6 77.56 L 593.4 77.56 C 596.66 77.56 599.31 74.91 599.31 71.65 L 599.31 6.6 C 599.31 3.34 596.66 0.69 593.4 0.69 L 6.6 0.69 C 3.34 0.69 0.69 3.34 0.69 6.6 Z" style="stroke:none"></path></g><g fill-opacity="1.0" transform="matrix(1.0 0.0 0.0 1.0 8.61 8.61)"><foreignobject color="#000000" height="61.04" overflow="visible" transform="matrix(1 0 0 -1 0 16.6)" width="582.79"> <span class="ltx_inline-block ltx_minipage ltx_align_bottom" id="S3.F2.pic1.1.1.1.1.1" style="width:421.2pt;"> <span class="ltx_p" id="S3.F2.pic1.1.1.1.1.1.1"><span class="ltx_text" id="S3.F2.pic1.1.1.1.1.1.1.1" style="font-size:80%;">You are an expert analog designer. You will be provided with a schematic, your task is to follow the below instructions carefully:</span></span> <span class="ltx_enumerate ltx_align_left" id="S3.I1"> <span class="ltx_item" id="S3.I1.i1" style="list-style-type:none;"><span class="ltx_tag ltx_tag_item">1.</span> <span class="ltx_para" id="S3.I1.i1.p1"> <span class="ltx_p" id="S3.I1.i1.p1.1"><span class="ltx_text" id="S3.I1.i1.p1.1.1" style="font-size:80%;">To identify the NMOS and PMOS MOSFET, follow the instructions carefully. For NMOS, the arrow on the source terminal points outwards from the transistor. For PMOS, the arrow on the source terminal points inward towards the transistor.</span></span> </span></span> <span class="ltx_item" id="S3.I1.i2" style="list-style-type:none;"><span class="ltx_tag ltx_tag_item">2.</span> <span class="ltx_para" id="S3.I1.i2.p1"> <span class="ltx_p" id="S3.I1.i2.p1.1"><span class="ltx_text" id="S3.I1.i2.p1.1.1" style="font-size:80%;">List all the components correctly.</span></span> </span></span> </span> </span></foreignobject></g></g></svg> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S3.F2.2.1.1" style="font-size:90%;">Figure 2</span>: </span><span class="ltx_text" id="S3.F2.3.2" style="font-size:90%;">Prompt Tuning guides the GPT to differentiate between NMOS and PMOS.</span></figcaption> </figure> <div class="ltx_para" id="S3.SS1.p1"> <p class="ltx_p" id="S3.SS1.p1.1">When generating a SPICE netlist, accurately identifying all components is essential for designers but challenging for language models. To evaluate GPT-4o’s ability to recognize electrical components in circuit schematics, we curated a set of analog schematics featuring resistors, capacitors, inductors, MOSFETs, and various sources from a popular analog textbook <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib24" title="">24</a>]</cite>. As illustrated in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S3.F1" title="Figure 1 ‣ III-A Can GPT-4o detect electrical components accurately? ‣ III Key Challenges in SPICE Netlist Extraction ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 1</span></a>, GPT-4o often misclassifies components, confusing NMOS and PMOS transistors (left and middle schematics) and even omitting key elements such as PMOS transistors and current sources in some cases. However, GPT-4o demonstrates the ability to identify all components accurately in some cases (final schematic), revealing promise despite its inconsistencies.</p> </div> <div class="ltx_para" id="S3.SS1.p2"> <p class="ltx_p" id="S3.SS1.p2.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S3.SS1.p2.1.1">Solution 1:</span> <span class="ltx_text ltx_font_italic" id="S3.SS1.p2.1.2">Electrical Component Detection using Object Detection Networks -</span> Recognizing the limitations of GPT-4o in this task, we propose a dedicated solution using a CNN-based object detection model, using the strong performance of models such as YOLO <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib25" title="">25</a>]</cite>. By training a CNN model specifically designed for schematic components, we significantly improve the accuracy in detecting and bounding all circuit elements, a method detailed in more detail in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4" title="IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Section IV</span></a>.</p> </div> <div class="ltx_para" id="S3.SS1.p3"> <p class="ltx_p" id="S3.SS1.p3.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S3.SS1.p3.1.1">Solution 2:</span> <span class="ltx_text ltx_font_italic" id="S3.SS1.p3.1.2">Prompt Tuning -</span> We developed a targeted prompt enhancement strategy to refine LLM component differentiation, especially between NMOS and PMOS transistors. By emphasizing structural differences in prompts (see <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S3.F2" title="Figure 2 ‣ III-A Can GPT-4o detect electrical components accurately? ‣ III Key Challenges in SPICE Netlist Extraction ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 2</span></a>), we achieved notable improvements in accuracy. Our empirical findings support this approach in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4" title="IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Section IV</span></a>.</p> </div> </section> <section class="ltx_subsection" id="S3.SS2"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection"><span class="ltx_text" id="S3.SS2.5.1.1">III-B</span> </span><span class="ltx_text ltx_font_italic" id="S3.SS2.6.2">Can GPT-4o Properly Connect Circuit Components?</span> </h3> <figure class="ltx_figure" id="S3.F3"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="611" id="S3.F3.g1" src="x2.png" width="872"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S3.F3.2.1.1" style="font-size:90%;">Figure 3</span>: </span><span class="ltx_text" id="S3.F3.3.2" style="font-size:90%;">SPICE netlist generated by the GPT-4o. For brevity, we only show the part of the netlist that describes transistors.</span></figcaption> </figure> <div class="ltx_para" id="S3.SS2.p1"> <p class="ltx_p" id="S3.SS2.p1.1">Once all components are detected, the next step is ensuring that the components are connected correctly so the resulting netlist accurately reflects the schematic. While GPT-4o successfully maps 2-terminal devices, our study uncovered several critical failure modes that compromise the accuracy of netlist generation. These failure modes are illustrated in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S3.F3" title="Figure 3 ‣ III-B Can GPT-4o Properly Connect Circuit Components? ‣ III Key Challenges in SPICE Netlist Extraction ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 3</span></a>. Firstly, GPT-4o incorrectly assumes that intersecting nets are connected, even when no connection exists. This error arises partly from inconsistencies in how different schematic notations define connectivity. Secondly, GPT-4o frequently mixes up MOSFET terminals (drain, gate, source). Despite the drain and source’s electrical equivalence, this misidentification disrupts the final netlist’s correctness. Finally, differential input and output voltage pairs pose significant challenges for GPT-4o. For example, in the left schematic (<a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S3.F3" title="Figure 3 ‣ III-B Can GPT-4o Properly Connect Circuit Components? ‣ III Key Challenges in SPICE Netlist Extraction ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 3</span></a>), while components were correctly identified, the source connections for (M1 and M2) were incorrect, and the gate voltage for (M3 and M4) was wrongly assumed to be ‘Vb1’. Similar errors were observed in the right schematic, where differential output was mishandled, and the drain of M5 was incorrectly mapped.</p> </div> <div class="ltx_para" id="S3.SS2.p2"> <p class="ltx_p" id="S3.SS2.p2.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S3.SS2.p2.1.1">Solution 1:</span> <span class="ltx_text ltx_font_italic" id="S3.SS2.p2.1.2">Prompt Tuning -</span> We enhanced the input prompts by explicitly specifying critical design features such as differential pairs and diode-connected topologies. This approach improved GPT-4o’s ability to map terminals to their corresponding nets for simpler designs. However, the solution’s scalability was limited, as it struggled with larger schematics containing more complex net connections.</p> </div> <div class="ltx_para" id="S3.SS2.p3"> <p class="ltx_p" id="S3.SS2.p3.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S3.SS2.p3.1.1">Solution 2:</span> <span class="ltx_text ltx_font_italic" id="S3.SS2.p3.1.2">Automatic Net Annotation -</span> Leveraging our knowledge of component locations, we developed a framework to annotate nets with unique identifiers. By incorporating these annotations into the prompt (see <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4" title="IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Section IV</span></a>), GPT-4o’s performance in translating schematics to SPICE netlists improved significantly. This systematic annotation reduced ambiguities and enhanced the LLM’s ability to correctly interpret and connect components, particularly in complex schematics.</p> </div> </section> </section> <section class="ltx_section" id="S4"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">IV </span><span class="ltx_text ltx_font_smallcaps" id="S4.1.1">Methodology </span> </h2> <figure class="ltx_figure" id="S4.F4"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="304" id="S4.F4.g1" src="x3.png" width="830"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S4.F4.2.1.1" style="font-size:90%;">Figure 4</span>: </span><span class="ltx_text" id="S4.F4.3.2" style="font-size:90%;">Dataset preparation flow starting from a PDF document consisting of Schematic and related text. Masala-CHAI extracts the relevant information and generates the SPICE netlist for the schematic. </span></figcaption> </figure> <figure class="ltx_figure" id="S4.F5"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="185" id="S4.F5.g1" src="x4.png" width="830"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S4.F5.4.2.1" style="font-size:90%;">Figure 5</span>: </span><span class="ltx_text" id="S4.F5.2.1" style="font-size:90%;">Schematic <math alttext="\longrightarrow" class="ltx_Math" display="inline" id="S4.F5.2.1.m1.1"><semantics id="S4.F5.2.1.m1.1b"><mo id="S4.F5.2.1.m1.1.1" stretchy="false" xref="S4.F5.2.1.m1.1.1.cmml">⟶</mo><annotation-xml encoding="MathML-Content" id="S4.F5.2.1.m1.1c"><ci id="S4.F5.2.1.m1.1.1.cmml" xref="S4.F5.2.1.m1.1.1">⟶</ci></annotation-xml><annotation encoding="application/x-tex" id="S4.F5.2.1.m1.1d">\longrightarrow</annotation><annotation encoding="application/x-llamapun" id="S4.F5.2.1.m1.1e">⟶</annotation></semantics></math> Annotated Schematic. Colors denote different component types. Similarly, different nets are clustered.</span></figcaption> </figure> <div class="ltx_para" id="S4.p1"> <p class="ltx_p" id="S4.p1.1">This section details the methodology developed in this study, addressing the significant challenges outlined in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S3" title="III Key Challenges in SPICE Netlist Extraction ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Section III</span></a>. Specifically, the accurate generation of SPICE netlists remains a critical bottleneck for LLMs due to difficulties in correctly identifying circuit components and establishing net connections. To begin the dataset creation flow, as shown in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F4" title="Figure 4 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 4</span></a> (➊), it takes a document in PDF format. After that, it is subdivided into 2 parts: (I) Extraction/Summarization of text present in the document comprises of the description of schematic and Key Performance Indicators (KPI) like gain, linearity, bandwidth, noise, gain/phase margin, etc - This will be used as an additional context for fine-tuning LLMs, <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S5.SS4" title="V-D Finetuning ‣ V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Section <span class="ltx_text">V-D</span></span></a>, shown in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F4" title="Figure 4 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 4</span></a> (➏ - ➐); (II) Automatic SPICE Netlist Generation - <span class="ltx_text ltx_font_bold" id="S4.p1.1.1">Masala-CHAI</span>: This step starts with extraction of the schematics/image from the document, then goes through the three-step process: 1) Labeling Analog Circuit, 2) Prompt Tuning, and 3) SPICE netlist verification, to finally generate a SPICE netlist, shown in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F4" title="Figure 4 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 4</span></a> (➋ - ➎).</p> </div> <section class="ltx_subsection" id="S4.SS1"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection"><span class="ltx_text" id="S4.SS1.5.1.1">IV-A</span> </span><span class="ltx_text ltx_font_italic" id="S4.SS1.6.2">Labeling Analog Circuit</span> </h3> <div class="ltx_para" id="S4.SS1.p1"> <p class="ltx_p" id="S4.SS1.p1.1"><a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F4" title="Figure 4 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 4</span></a> (➋) step eases the job of the LLM in writing the SPICE netlist from schematics by detecting components and enabling net annotation. As discussed in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S3" title="III Key Challenges in SPICE Netlist Extraction ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Section III</span></a>, SPICE netlist generation is not straightforward, requiring the designer to feed information alongside the schematics. However, this manual process hinders generating large-scale datasets. Thus, we automate labeling all parts of the schematics.</p> </div> <section class="ltx_subsubsection" id="S4.SS1.SSS1"> <h4 class="ltx_title ltx_title_subsubsection"> <span class="ltx_tag ltx_tag_subsubsection"><span class="ltx_text" id="S4.SS1.SSS1.5.1.1">IV-A</span>1 </span>Detection of Circuit Components</h4> <div class="ltx_para" id="S4.SS1.SSS1.p1"> <p class="ltx_p" id="S4.SS1.SSS1.p1.1">We train YoloV8 <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib25" title="">25</a>]</cite>, a state-of-the-art object localization and classification model, specifically for detecting and classifying circuit components with high precision, similar to prior work <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib21" title="">21</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib22" title="">22</a>]</cite>. Given an input circuit image, YoloV8 localizes each component by regressing its center coordinates, bounding box parameters, and classification label. The model’s backbone, CSPDarknet53 <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib26" title="">26</a>]</cite>, enhanced with a Cross Stage Partial bottleneck <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib27" title="">27</a>]</cite>, effectively integrates high-level semantic information with low-level spatial details, enabling accurate detection even for small-scale components — a critical requirement for high-performance circuit analysis. This process results in schematic diagrams annotated with bounding boxes for all detected components, as illustrated in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F5" title="Figure 5 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 5</span></a> (➋). We utilize YoloV8 on the open-sourced dataset <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib28" title="">28</a>]</cite>. This dataset comprises approximately 4,300 circuit diagram snapshots annotated with bounding boxes across 12 component classes: <span class="ltx_text ltx_font_typewriter" id="S4.SS1.SSS1.p1.1.1">AC Source, BJT, Battery, Capacitor, DC Source, Diode, Ground, Inductor, MOSFET, Resistor, Current Source, Voltage Source</span>. We resized images to 640x640 and trained for 1000 epochs with a learning rate of 0.01.</p> </div> </section> <section class="ltx_subsubsection" id="S4.SS1.SSS2"> <h4 class="ltx_title ltx_title_subsubsection"> <span class="ltx_tag ltx_tag_subsubsection"><span class="ltx_text" id="S4.SS1.SSS2.5.1.1">IV-A</span>2 </span>Net Detection</h4> <div class="ltx_para" id="S4.SS1.SSS2.p1"> <p class="ltx_p" id="S4.SS1.SSS2.p1.1">We performed net detection in circuit schematics by leveraging pre-trained Deep Hough Transform Line priors <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib29" title="">29</a>]</cite>, a state-of-the-art approach for line detection in images. Unlike conventional methods, this model operates in the Hough domain, parametrizing line segments in polar coordinates to achieve precise line segmentation. We remove components from the schematic to address challenges posed by line segments within components such as capacitors and MOSFETs, leaving only the lines representing nets, as illustrated in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F5" title="Figure 5 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 5</span></a> (➌). This ensures a clean input for subsequent net analysis and eliminates potential sources of ambiguity. Following net detection, we propose a simple yet effective heuristic for clustering line segments into nets. Specifically, we group all line segments into a single cluster if their endpoints fall within a radius of 40 pixels, as demonstrated in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F5" title="Figure 5 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 5</span></a> (➍). To ensure reliability, we fine-tune the radius parameter and manually verify the consistency of the clustered nets.</p> </div> </section> </section> <section class="ltx_subsection" id="S4.SS2"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection"><span class="ltx_text" id="S4.SS2.5.1.1">IV-B</span> </span><span class="ltx_text ltx_font_italic" id="S4.SS2.6.2">Prompt Tuning</span> </h3> <div class="ltx_para" id="S4.SS2.p1"> <p class="ltx_p" id="S4.SS2.p1.1">Prompts are crucial in guiding LLMs to generate precise, high-quality outputs. Crafting effective prompts involves meticulous design of their language, structure, and contextual framing, enabling models to respond accurately and meaningfully to user inputs. Through prompt refinement, designers can precisely control model behavior, ensuring the generation of coherent and domain-specific responses. In this study, we systematically explore diverse prompt designs tailored to enhance understanding of schematics. Our approach demonstrates significant effectiveness, as illustrated in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S3.F2" title="Figure 2 ‣ III-A Can GPT-4o detect electrical components accurately? ‣ III Key Challenges in SPICE Netlist Extraction ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 2</span></a> and <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F6" title="Figure 6 ‣ IV-B Prompt Tuning ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 6</span></a>. Specifically, prompt in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F6" title="Figure 6 ‣ IV-B Prompt Tuning ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 6</span></a> is used at the stage <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F4" title="Figure 4 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 4</span></a> (➌), facilitating insightful queries to the GPT model.</p> </div> <figure class="ltx_figure" id="S4.F6"><svg class="ltx_picture ltx_centering" height="78.25" id="S4.F6.pic1" overflow="visible" version="1.1" width="600"><g fill="#000000" stroke="#000000" stroke-width="0.4pt" transform="translate(0,78.25) matrix(1 0 0 -1 0 0)"><g fill="#000000" fill-opacity="1.0"><path d="M 0 6.6 L 0 71.65 C 0 75.29 2.95 78.25 6.6 78.25 L 593.4 78.25 C 597.05 78.25 600 75.29 600 71.65 L 600 6.6 C 600 2.95 597.05 0 593.4 0 L 6.6 0 C 2.95 0 0 2.95 0 6.6 Z" style="stroke:none"></path></g><g fill="#FFFFFF" fill-opacity="1.0"><path d="M 0.69 6.6 L 0.69 71.65 C 0.69 74.91 3.34 77.56 6.6 77.56 L 593.4 77.56 C 596.66 77.56 599.31 74.91 599.31 71.65 L 599.31 6.6 C 599.31 3.34 596.66 0.69 593.4 0.69 L 6.6 0.69 C 3.34 0.69 0.69 3.34 0.69 6.6 Z" style="stroke:none"></path></g><g fill-opacity="1.0" transform="matrix(1.0 0.0 0.0 1.0 8.61 8.61)"><foreignobject color="#000000" height="61.04" overflow="visible" transform="matrix(1 0 0 -1 0 16.6)" width="582.79"> <span class="ltx_inline-block ltx_minipage ltx_align_bottom" id="S4.F6.pic1.1.1.1.1.1" style="width:421.2pt;"> <span class="ltx_p" id="S4.F6.pic1.1.1.1.1.1.1"><span class="ltx_text" id="S4.F6.pic1.1.1.1.1.1.1.1" style="font-size:80%;">You are an expert analog designer. You will be provided with a schematic, your task is to follow the below instructions carefully:</span></span> <span class="ltx_enumerate ltx_align_left" id="S4.I1"> <span class="ltx_item" id="S4.I1.i1" style="list-style-type:none;"><span class="ltx_tag ltx_tag_item">1.</span> <span class="ltx_para" id="S4.I1.i1.p1"> <span class="ltx_p" id="S4.I1.i1.p1.1"><span class="ltx_text" id="S4.I1.i1.p1.1.1" style="font-size:80%;">List all the components which you can observe from the figure.</span></span> </span></span> <span class="ltx_item" id="S4.I1.i2" style="list-style-type:none;"><span class="ltx_tag ltx_tag_item">2.</span> <span class="ltx_para" id="S4.I1.i2.p1"> <span class="ltx_p" id="S4.I1.i2.p1.1"><span class="ltx_text" id="S4.I1.i2.p1.1.1" style="font-size:80%;">MOSFET are 3 terminal devices with (drain, gate, source).</span></span> </span></span> <span class="ltx_item" id="S4.I1.i3" style="list-style-type:none;"><span class="ltx_tag ltx_tag_item">3.</span> <span class="ltx_para" id="S4.I1.i3.p1"> <span class="ltx_p" id="S4.I1.i3.p1.1"><span class="ltx_text" id="S4.I1.i3.p1.1.1" style="font-size:80%;">For each component, look at the net number highlighted in red.</span></span> </span></span> <span class="ltx_item" id="S4.I1.i4" style="list-style-type:none;"><span class="ltx_tag ltx_tag_item">4.</span> <span class="ltx_para" id="S4.I1.i4.p1"> <span class="ltx_p" id="S4.I1.i4.p1.1"><span class="ltx_text" id="S4.I1.i4.p1.1.1" style="font-size:80%;">To identify the source terminal of a MOSFET, choose the net highlighted in red which is nearest to the arrow of the MOSFET.</span></span> </span></span> <span class="ltx_item" id="S4.I1.i5" style="list-style-type:none;"><span class="ltx_tag ltx_tag_item">5.</span> <span class="ltx_para" id="S4.I1.i5.p1"> <span class="ltx_p" id="S4.I1.i5.p1.1"><span class="ltx_text" id="S4.I1.i5.p1.1.1" style="font-size:80%;">Write a SPICE netlist.</span></span> </span></span> </span> </span></foreignobject></g></g></svg> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S4.F6.2.1.1" style="font-size:90%;">Figure 6</span>: </span><span class="ltx_text" id="S4.F6.3.2" style="font-size:90%;">Prompt Tuning guides the GPT to generate SPICE netlist from Schematics.</span></figcaption> </figure> </section> <section class="ltx_subsection" id="S4.SS3"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection"><span class="ltx_text" id="S4.SS3.5.1.1">IV-C</span> </span><span class="ltx_text ltx_font_italic" id="S4.SS3.6.2">SPICE netlist verification</span> </h3> <div class="ltx_para" id="S4.SS3.p1"> <p class="ltx_p" id="S4.SS3.p1.1">Our case study revealed that some generated netlists (<a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F4" title="Figure 4 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 4</span></a> (➍)) exhibit issues such as floating nets. Although these issues may pass a simulator check, they pose significant risks for large-scale datasets where manual inspection is infeasible. To mitigate this, we developed a Python-based feedback mechanism (<a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F4" title="Figure 4 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 4</span></a> (➎)) that enables LLMs to identify and self-correct such errors automatically, eliminating the need for manual intervention. This solution establishes a robust, closed-loop verification process, which can be further enhanced with additional netlist verification features. We are also releasing this as part of our open-source contribution <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib16" title="">16</a>]</cite>.</p> </div> </section> </section> <section class="ltx_section" id="S5"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">V </span><span class="ltx_text ltx_font_smallcaps" id="S5.1.1">Results</span> </h2> <section class="ltx_subsection" id="S5.SS1"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection"><span class="ltx_text" id="S5.SS1.5.1.1">V-A</span> </span><span class="ltx_text ltx_font_italic" id="S5.SS1.6.2">Dataset Creation</span> </h3> <figure class="ltx_figure" id="S5.F7"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="220" id="S5.F7.g1" src="x5.png" width="830"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S5.F7.2.1.1" style="font-size:90%;">Figure 7</span>: </span><span class="ltx_text" id="S5.F7.3.2" style="font-size:90%;">Automatic SPICE Netlist generation using Masala-CHAI.</span></figcaption> </figure> <figure class="ltx_figure" id="S5.F8"> <div class="ltx_flex_figure"> <div class="ltx_flex_cell ltx_flex_size_1"> <figure class="ltx_figure ltx_figure_panel ltx_align_center" id="S5.F8.sf1"><img alt="Refer to caption" class="ltx_graphics ltx_img_landscape" height="239" id="S5.F8.sf1.g1" src="x6.png" width="398"/> <figcaption class="ltx_caption"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S5.F8.sf1.2.1.1" style="font-size:90%;">(a)</span> </span></figcaption> </figure> </div> <div class="ltx_flex_break"></div> <div class="ltx_flex_cell ltx_flex_size_1"> <figure class="ltx_figure ltx_figure_panel ltx_align_center" id="S5.F8.sf2"><img alt="Refer to caption" class="ltx_graphics ltx_img_landscape" height="239" id="S5.F8.sf2.g1" src="x7.png" width="398"/> <figcaption class="ltx_caption"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S5.F8.sf2.2.1.1" style="font-size:90%;">(b)</span> </span></figcaption> </figure> </div> <div class="ltx_flex_break"></div> <div class="ltx_flex_cell ltx_flex_size_1"> <figure class="ltx_figure ltx_figure_panel ltx_align_center" id="S5.F8.sf3"><img alt="Refer to caption" class="ltx_graphics ltx_img_landscape" height="239" id="S5.F8.sf3.g1" src="x8.png" width="398"/> <figcaption class="ltx_caption"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S5.F8.sf3.2.1.1" style="font-size:90%;">(c)</span> </span></figcaption> </figure> </div> <div class="ltx_flex_break"></div> <div class="ltx_flex_cell ltx_flex_size_1"> <figure class="ltx_figure ltx_figure_panel ltx_align_center" id="S5.F8.sf4"><img alt="Refer to caption" class="ltx_graphics ltx_img_landscape" height="239" id="S5.F8.sf4.g1" src="x9.png" width="398"/> <figcaption class="ltx_caption"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S5.F8.sf4.2.1.1" style="font-size:90%;">(d)</span> </span></figcaption> </figure> </div> </div> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S5.F8.2.1.1" style="font-size:90%;">Figure 8</span>: </span><span class="ltx_text" id="S5.F8.3.2" style="font-size:90%;">Distribution of (a) Number of Components, (b) Number of Nodes, (c) Number of MOSFETs, and (d) Number of lines of SPICE code, respectively in the dataset. </span></figcaption> </figure> <div class="ltx_para" id="S5.SS1.p1"> <p class="ltx_p" id="S5.SS1.p1.1">We curated a comprehensive dataset by selecting schematics from textbooks <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib24" title="">24</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib30" title="">30</a>]</cite>. Textbooks were chosen over research papers because they offer high-quality schematic images, clear context, and detailed explanations. This makes them more suitable for our purposes, as research papers often present high-level descriptions with advanced schematics that use abstract blocks for complex components. We collected over 2,100 schematic images and applied our proposed Masala-CHAI flow (<a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F4" title="Figure 4 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 4</span></a>) to generate the corresponding SPICE netlists. Alongside this, we collected captions and descriptions as detailed in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4" title="IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Section IV</span></a>. <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S5.F7" title="Figure 7 ‣ V-A Dataset Creation ‣ V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 7</span></a> demonstrates how Masala-CHAI translates a schematic into a SPICE netlist. Since our primary goal is to generate structurally correct netlists, each component is marked with default parameters.</p> </div> <div class="ltx_para" id="S5.SS1.p2"> <p class="ltx_p" id="S5.SS1.p2.1">Our dataset is carefully characterized to showcase its diversity and complexity, as shown in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S5.F8" title="Figure 8 ‣ V-A Dataset Creation ‣ V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 8</span></a>: (a) displays the variation in the number of components within the schematics, reflecting the complexity of the circuits - a higher number indicates a more complex design; (b) illustrates the distribution of nodes in the schematics, which corresponds to the connectivity between components. Notably, accurately identifying and mapping MOSFET terminals to the correct nets is a significant challenge for LLMs; (c) focuses on the number of MOSFETs present, indicating increased complexity for SPICE generation as the number rises; (d) presents the distribution of the number of lines in the generated SPICE netlists, further emphasizing the varying levels of complexity encompassed in our dataset. By creating this diverse and challenging dataset, we provide a robust benchmark for evaluating and enhancing the capabilities of LLMs in automated SPICE netlist generation.</p> </div> </section> <section class="ltx_subsection" id="S5.SS2"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection"><span class="ltx_text" id="S5.SS2.5.1.1">V-B</span> </span><span class="ltx_text ltx_font_italic" id="S5.SS2.6.2">Evaluation</span> </h3> <div class="ltx_para" id="S5.SS2.p1"> <p class="ltx_p" id="S5.SS2.p1.4">To evaluate the performance of our proposed method, we leverage graph-matching concepts to compare the structural similarity between SPICE netlists. Unlike traditional approaches, we parse the netlists to extract components and their connections. We identify components by their types (e.g., Resistor, Capacitor, MOSFET) to ensure that our graph representations remain invariant to varying component labels used during netlist generation. This results in a constructed graph “G”, where nodes represent circuit components and edges represent their interconnections, as illustrated <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S5.F9" title="Figure 9 ‣ V-C Verifying against AMSNet [13] netlists ‣ V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 9</span></a>. We use Graph Edit Distance (GED) as a quantitative metric to compare the representations of two SPICE netlists. GED (<math alttext="G_{1}" class="ltx_Math" display="inline" id="S5.SS2.p1.1.m1.1"><semantics id="S5.SS2.p1.1.m1.1a"><msub id="S5.SS2.p1.1.m1.1.1" xref="S5.SS2.p1.1.m1.1.1.cmml"><mi id="S5.SS2.p1.1.m1.1.1.2" xref="S5.SS2.p1.1.m1.1.1.2.cmml">G</mi><mn id="S5.SS2.p1.1.m1.1.1.3" xref="S5.SS2.p1.1.m1.1.1.3.cmml">1</mn></msub><annotation-xml encoding="MathML-Content" id="S5.SS2.p1.1.m1.1b"><apply id="S5.SS2.p1.1.m1.1.1.cmml" xref="S5.SS2.p1.1.m1.1.1"><csymbol cd="ambiguous" id="S5.SS2.p1.1.m1.1.1.1.cmml" xref="S5.SS2.p1.1.m1.1.1">subscript</csymbol><ci id="S5.SS2.p1.1.m1.1.1.2.cmml" xref="S5.SS2.p1.1.m1.1.1.2">𝐺</ci><cn id="S5.SS2.p1.1.m1.1.1.3.cmml" type="integer" xref="S5.SS2.p1.1.m1.1.1.3">1</cn></apply></annotation-xml><annotation encoding="application/x-tex" id="S5.SS2.p1.1.m1.1c">G_{1}</annotation><annotation encoding="application/x-llamapun" id="S5.SS2.p1.1.m1.1d">italic_G start_POSTSUBSCRIPT 1 end_POSTSUBSCRIPT</annotation></semantics></math>,<math alttext="G_{2}" class="ltx_Math" display="inline" id="S5.SS2.p1.2.m2.1"><semantics id="S5.SS2.p1.2.m2.1a"><msub id="S5.SS2.p1.2.m2.1.1" xref="S5.SS2.p1.2.m2.1.1.cmml"><mi id="S5.SS2.p1.2.m2.1.1.2" xref="S5.SS2.p1.2.m2.1.1.2.cmml">G</mi><mn id="S5.SS2.p1.2.m2.1.1.3" xref="S5.SS2.p1.2.m2.1.1.3.cmml">2</mn></msub><annotation-xml encoding="MathML-Content" id="S5.SS2.p1.2.m2.1b"><apply id="S5.SS2.p1.2.m2.1.1.cmml" xref="S5.SS2.p1.2.m2.1.1"><csymbol cd="ambiguous" id="S5.SS2.p1.2.m2.1.1.1.cmml" xref="S5.SS2.p1.2.m2.1.1">subscript</csymbol><ci id="S5.SS2.p1.2.m2.1.1.2.cmml" xref="S5.SS2.p1.2.m2.1.1.2">𝐺</ci><cn id="S5.SS2.p1.2.m2.1.1.3.cmml" type="integer" xref="S5.SS2.p1.2.m2.1.1.3">2</cn></apply></annotation-xml><annotation encoding="application/x-tex" id="S5.SS2.p1.2.m2.1c">G_{2}</annotation><annotation encoding="application/x-llamapun" id="S5.SS2.p1.2.m2.1d">italic_G start_POSTSUBSCRIPT 2 end_POSTSUBSCRIPT</annotation></semantics></math>) calculates the sum of the costs associated with transforming <math alttext="G_{1}" class="ltx_Math" display="inline" id="S5.SS2.p1.3.m3.1"><semantics id="S5.SS2.p1.3.m3.1a"><msub id="S5.SS2.p1.3.m3.1.1" xref="S5.SS2.p1.3.m3.1.1.cmml"><mi id="S5.SS2.p1.3.m3.1.1.2" xref="S5.SS2.p1.3.m3.1.1.2.cmml">G</mi><mn id="S5.SS2.p1.3.m3.1.1.3" xref="S5.SS2.p1.3.m3.1.1.3.cmml">1</mn></msub><annotation-xml encoding="MathML-Content" id="S5.SS2.p1.3.m3.1b"><apply id="S5.SS2.p1.3.m3.1.1.cmml" xref="S5.SS2.p1.3.m3.1.1"><csymbol cd="ambiguous" id="S5.SS2.p1.3.m3.1.1.1.cmml" xref="S5.SS2.p1.3.m3.1.1">subscript</csymbol><ci id="S5.SS2.p1.3.m3.1.1.2.cmml" xref="S5.SS2.p1.3.m3.1.1.2">𝐺</ci><cn id="S5.SS2.p1.3.m3.1.1.3.cmml" type="integer" xref="S5.SS2.p1.3.m3.1.1.3">1</cn></apply></annotation-xml><annotation encoding="application/x-tex" id="S5.SS2.p1.3.m3.1c">G_{1}</annotation><annotation encoding="application/x-llamapun" id="S5.SS2.p1.3.m3.1d">italic_G start_POSTSUBSCRIPT 1 end_POSTSUBSCRIPT</annotation></semantics></math> into <math alttext="G_{2}" class="ltx_Math" display="inline" id="S5.SS2.p1.4.m4.1"><semantics id="S5.SS2.p1.4.m4.1a"><msub id="S5.SS2.p1.4.m4.1.1" xref="S5.SS2.p1.4.m4.1.1.cmml"><mi id="S5.SS2.p1.4.m4.1.1.2" xref="S5.SS2.p1.4.m4.1.1.2.cmml">G</mi><mn id="S5.SS2.p1.4.m4.1.1.3" xref="S5.SS2.p1.4.m4.1.1.3.cmml">2</mn></msub><annotation-xml encoding="MathML-Content" id="S5.SS2.p1.4.m4.1b"><apply id="S5.SS2.p1.4.m4.1.1.cmml" xref="S5.SS2.p1.4.m4.1.1"><csymbol cd="ambiguous" id="S5.SS2.p1.4.m4.1.1.1.cmml" xref="S5.SS2.p1.4.m4.1.1">subscript</csymbol><ci id="S5.SS2.p1.4.m4.1.1.2.cmml" xref="S5.SS2.p1.4.m4.1.1.2">𝐺</ci><cn id="S5.SS2.p1.4.m4.1.1.3.cmml" type="integer" xref="S5.SS2.p1.4.m4.1.1.3">2</cn></apply></annotation-xml><annotation encoding="application/x-tex" id="S5.SS2.p1.4.m4.1c">G_{2}</annotation><annotation encoding="application/x-llamapun" id="S5.SS2.p1.4.m4.1d">italic_G start_POSTSUBSCRIPT 2 end_POSTSUBSCRIPT</annotation></semantics></math> through a series of edit operations on nodes and edges, such as insertions, deletions, and substitutions. To enhance the interpretability of our results, we normalize the GED to yield a final metric ranging from 0 to 100. This normalization is achieved by calculating the maximum possible GED, obtained by summing the total number of nodes and edges in both graphs and scaling accordingly. This standardized metric allows for a consistent and meaningful comparison across different circuits. Thus, the similarity score between the two netlists is:</p> </div> <div class="ltx_para" id="S5.SS2.p2"> <table class="ltx_equation ltx_eqn_table" id="S5.E1"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="S=\left(1-\frac{\text{GED}(G_{1},G_{2})}{\text{GED}_{\text{max}}}\right)\times 1% 00\%" class="ltx_Math" display="block" id="S5.E1.m1.3"><semantics id="S5.E1.m1.3a"><mrow id="S5.E1.m1.3.3" xref="S5.E1.m1.3.3.cmml"><mi id="S5.E1.m1.3.3.3" xref="S5.E1.m1.3.3.3.cmml">S</mi><mo id="S5.E1.m1.3.3.2" xref="S5.E1.m1.3.3.2.cmml">=</mo><mrow id="S5.E1.m1.3.3.1" xref="S5.E1.m1.3.3.1.cmml"><mrow id="S5.E1.m1.3.3.1.1.1" xref="S5.E1.m1.3.3.1.1.1.1.cmml"><mo id="S5.E1.m1.3.3.1.1.1.2" xref="S5.E1.m1.3.3.1.1.1.1.cmml">(</mo><mrow id="S5.E1.m1.3.3.1.1.1.1" xref="S5.E1.m1.3.3.1.1.1.1.cmml"><mn id="S5.E1.m1.3.3.1.1.1.1.2" xref="S5.E1.m1.3.3.1.1.1.1.2.cmml">1</mn><mo id="S5.E1.m1.3.3.1.1.1.1.1" xref="S5.E1.m1.3.3.1.1.1.1.1.cmml">−</mo><mfrac id="S5.E1.m1.2.2" xref="S5.E1.m1.2.2.cmml"><mrow id="S5.E1.m1.2.2.2" xref="S5.E1.m1.2.2.2.cmml"><mtext id="S5.E1.m1.2.2.2.4" xref="S5.E1.m1.2.2.2.4a.cmml">GED</mtext><mo id="S5.E1.m1.2.2.2.3" xref="S5.E1.m1.2.2.2.3.cmml">⁢</mo><mrow id="S5.E1.m1.2.2.2.2.2" xref="S5.E1.m1.2.2.2.2.3.cmml"><mo id="S5.E1.m1.2.2.2.2.2.3" stretchy="false" xref="S5.E1.m1.2.2.2.2.3.cmml">(</mo><msub id="S5.E1.m1.1.1.1.1.1.1" xref="S5.E1.m1.1.1.1.1.1.1.cmml"><mi id="S5.E1.m1.1.1.1.1.1.1.2" xref="S5.E1.m1.1.1.1.1.1.1.2.cmml">G</mi><mn id="S5.E1.m1.1.1.1.1.1.1.3" xref="S5.E1.m1.1.1.1.1.1.1.3.cmml">1</mn></msub><mo id="S5.E1.m1.2.2.2.2.2.4" xref="S5.E1.m1.2.2.2.2.3.cmml">,</mo><msub id="S5.E1.m1.2.2.2.2.2.2" xref="S5.E1.m1.2.2.2.2.2.2.cmml"><mi id="S5.E1.m1.2.2.2.2.2.2.2" xref="S5.E1.m1.2.2.2.2.2.2.2.cmml">G</mi><mn id="S5.E1.m1.2.2.2.2.2.2.3" xref="S5.E1.m1.2.2.2.2.2.2.3.cmml">2</mn></msub><mo id="S5.E1.m1.2.2.2.2.2.5" stretchy="false" xref="S5.E1.m1.2.2.2.2.3.cmml">)</mo></mrow></mrow><msub id="S5.E1.m1.2.2.4" xref="S5.E1.m1.2.2.4.cmml"><mtext id="S5.E1.m1.2.2.4.2" xref="S5.E1.m1.2.2.4.2a.cmml">GED</mtext><mtext id="S5.E1.m1.2.2.4.3" xref="S5.E1.m1.2.2.4.3a.cmml">max</mtext></msub></mfrac></mrow><mo id="S5.E1.m1.3.3.1.1.1.3" rspace="0.055em" xref="S5.E1.m1.3.3.1.1.1.1.cmml">)</mo></mrow><mo id="S5.E1.m1.3.3.1.2" rspace="0.222em" xref="S5.E1.m1.3.3.1.2.cmml">×</mo><mrow id="S5.E1.m1.3.3.1.3" xref="S5.E1.m1.3.3.1.3.cmml"><mn id="S5.E1.m1.3.3.1.3.2" xref="S5.E1.m1.3.3.1.3.2.cmml">100</mn><mo id="S5.E1.m1.3.3.1.3.1" xref="S5.E1.m1.3.3.1.3.1.cmml">%</mo></mrow></mrow></mrow><annotation-xml encoding="MathML-Content" id="S5.E1.m1.3b"><apply id="S5.E1.m1.3.3.cmml" xref="S5.E1.m1.3.3"><eq id="S5.E1.m1.3.3.2.cmml" xref="S5.E1.m1.3.3.2"></eq><ci id="S5.E1.m1.3.3.3.cmml" xref="S5.E1.m1.3.3.3">𝑆</ci><apply id="S5.E1.m1.3.3.1.cmml" xref="S5.E1.m1.3.3.1"><times id="S5.E1.m1.3.3.1.2.cmml" xref="S5.E1.m1.3.3.1.2"></times><apply id="S5.E1.m1.3.3.1.1.1.1.cmml" xref="S5.E1.m1.3.3.1.1.1"><minus id="S5.E1.m1.3.3.1.1.1.1.1.cmml" xref="S5.E1.m1.3.3.1.1.1.1.1"></minus><cn id="S5.E1.m1.3.3.1.1.1.1.2.cmml" type="integer" xref="S5.E1.m1.3.3.1.1.1.1.2">1</cn><apply id="S5.E1.m1.2.2.cmml" xref="S5.E1.m1.2.2"><divide id="S5.E1.m1.2.2.3.cmml" xref="S5.E1.m1.2.2"></divide><apply id="S5.E1.m1.2.2.2.cmml" xref="S5.E1.m1.2.2.2"><times id="S5.E1.m1.2.2.2.3.cmml" xref="S5.E1.m1.2.2.2.3"></times><ci id="S5.E1.m1.2.2.2.4a.cmml" xref="S5.E1.m1.2.2.2.4"><mtext id="S5.E1.m1.2.2.2.4.cmml" xref="S5.E1.m1.2.2.2.4">GED</mtext></ci><interval closure="open" id="S5.E1.m1.2.2.2.2.3.cmml" xref="S5.E1.m1.2.2.2.2.2"><apply id="S5.E1.m1.1.1.1.1.1.1.cmml" xref="S5.E1.m1.1.1.1.1.1.1"><csymbol cd="ambiguous" id="S5.E1.m1.1.1.1.1.1.1.1.cmml" xref="S5.E1.m1.1.1.1.1.1.1">subscript</csymbol><ci id="S5.E1.m1.1.1.1.1.1.1.2.cmml" xref="S5.E1.m1.1.1.1.1.1.1.2">𝐺</ci><cn id="S5.E1.m1.1.1.1.1.1.1.3.cmml" type="integer" xref="S5.E1.m1.1.1.1.1.1.1.3">1</cn></apply><apply id="S5.E1.m1.2.2.2.2.2.2.cmml" xref="S5.E1.m1.2.2.2.2.2.2"><csymbol cd="ambiguous" id="S5.E1.m1.2.2.2.2.2.2.1.cmml" xref="S5.E1.m1.2.2.2.2.2.2">subscript</csymbol><ci id="S5.E1.m1.2.2.2.2.2.2.2.cmml" xref="S5.E1.m1.2.2.2.2.2.2.2">𝐺</ci><cn id="S5.E1.m1.2.2.2.2.2.2.3.cmml" type="integer" xref="S5.E1.m1.2.2.2.2.2.2.3">2</cn></apply></interval></apply><apply id="S5.E1.m1.2.2.4.cmml" xref="S5.E1.m1.2.2.4"><csymbol cd="ambiguous" id="S5.E1.m1.2.2.4.1.cmml" xref="S5.E1.m1.2.2.4">subscript</csymbol><ci id="S5.E1.m1.2.2.4.2a.cmml" xref="S5.E1.m1.2.2.4.2"><mtext id="S5.E1.m1.2.2.4.2.cmml" xref="S5.E1.m1.2.2.4.2">GED</mtext></ci><ci id="S5.E1.m1.2.2.4.3a.cmml" xref="S5.E1.m1.2.2.4.3"><mtext id="S5.E1.m1.2.2.4.3.cmml" mathsize="70%" xref="S5.E1.m1.2.2.4.3">max</mtext></ci></apply></apply></apply><apply id="S5.E1.m1.3.3.1.3.cmml" xref="S5.E1.m1.3.3.1.3"><csymbol cd="latexml" id="S5.E1.m1.3.3.1.3.1.cmml" xref="S5.E1.m1.3.3.1.3.1">percent</csymbol><cn id="S5.E1.m1.3.3.1.3.2.cmml" type="integer" xref="S5.E1.m1.3.3.1.3.2">100</cn></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="S5.E1.m1.3c">S=\left(1-\frac{\text{GED}(G_{1},G_{2})}{\text{GED}_{\text{max}}}\right)\times 1% 00\%</annotation><annotation encoding="application/x-llamapun" id="S5.E1.m1.3d">italic_S = ( 1 - divide start_ARG GED ( italic_G start_POSTSUBSCRIPT 1 end_POSTSUBSCRIPT , italic_G start_POSTSUBSCRIPT 2 end_POSTSUBSCRIPT ) end_ARG start_ARG GED start_POSTSUBSCRIPT max end_POSTSUBSCRIPT end_ARG ) × 100 %</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_right" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_right">(1)</span></td> </tr></tbody> </table> </div> </section> <section class="ltx_subsection" id="S5.SS3"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection"><span class="ltx_text" id="S5.SS3.5.1.1">V-C</span> </span><span class="ltx_text ltx_font_italic" id="S5.SS3.6.2">Verifying against AMSNet <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib13" title="">13</a>]</cite> netlists</span> </h3> <div class="ltx_para" id="S5.SS3.p1"> <p class="ltx_p" id="S5.SS3.p1.1">We demonstrated the effectiveness of our approach by evaluating it using the AMSNet <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib13" title="">13</a>]</cite> dataset, which includes <math alttext="\sim" class="ltx_Math" display="inline" id="S5.SS3.p1.1.m1.1"><semantics id="S5.SS3.p1.1.m1.1a"><mo id="S5.SS3.p1.1.m1.1.1" xref="S5.SS3.p1.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S5.SS3.p1.1.m1.1b"><csymbol cd="latexml" id="S5.SS3.p1.1.m1.1.1.cmml" xref="S5.SS3.p1.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S5.SS3.p1.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="S5.SS3.p1.1.m1.1d">∼</annotation></semantics></math>800 circuit diagrams. Unlike AMSNet, which relies on an algorithmic method supplemented with some manual effort to generate SPICE netlists, our method introduces a fully automated flow (<a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S4.F4" title="Figure 4 ‣ IV Methodology ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 4</span></a>). When comparing the SPICE netlists generated by our method to those produced by AMSNet, our approach achieved a <span class="ltx_text ltx_font_bold" id="S5.SS3.p1.1.1">100%</span> similarity score, as defined earlier. This validates the robustness of our flow and motivates us to extend the evaluation to additional circuit diagrams. <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S5.F9" title="Figure 9 ‣ V-C Verifying against AMSNet [13] netlists ‣ V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 9</span></a> illustrates an example of graphs representation of SPICE netlist generated by AMSNet (➊) and our Masala-CHAI framework (➋). The results demonstrate that the number of components and their neighboring elements is identical across both methods, with differences in component and net naming conventions. These findings strengthen Masala-CHAI accuracy and scalability in generating accurate netlists for various circuit diagrams.</p> </div> <figure class="ltx_figure" id="S5.F9"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="264" id="S5.F9.g1" src="x10.png" width="830"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S5.F9.2.1.1" style="font-size:90%;">Figure 9</span>: </span><span class="ltx_text" id="S5.F9.3.2" style="font-size:90%;">Graph representation of SPICE netlists generated by AMSNet <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib13" title="">13</a>]</cite> and Masala-CHAI. They are identical.</span></figcaption> </figure> </section> <section class="ltx_subsection" id="S5.SS4"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection"><span class="ltx_text" id="S5.SS4.5.1.1">V-D</span> </span><span class="ltx_text ltx_font_italic" id="S5.SS4.6.2">Finetuning</span> </h3> <div class="ltx_para" id="S5.SS4.p1"> <p class="ltx_p" id="S5.SS4.p1.1">Finetuning entails adapting a pre-trained model to a specific downstream task <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib4" title="">4</a>, <a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib3" title="">3</a>]</cite>. This process entails further training the model on a smaller task-specific dataset, enabling it to adjust its parameters to capture new patterns and subtle nuances relevant to the task without training from scratch. The advantages of fine-tuning are: 1) It substantially reduces training time and computational resources by leveraging the foundational knowledge already embedded in the model; 2) It enhances performance on specialized tasks, particularly when data is scarce; and 3) It facilitates the transfer of learned representations across different domains, thereby improving efficiency and effectiveness in model deployment.</p> </div> <div class="ltx_para" id="S5.SS4.p2"> <p class="ltx_p" id="S5.SS4.p2.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S5.SS4.p2.1.1">GPT:</span> OpenAI <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib31" title="">31</a>]</cite> released GPT models up to the state-of-the-art GPT-4o model, which is expensive. Fine-tuning <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib32" title="">32</a>]</cite> reduces cost and latency by replacing the expensive GPT-4o, with a fine-tuned GPT-4o-mini model. The fine-tuned GPT-4o-mini can achieve quality results similar to those of GPT-4o.</p> </div> <div class="ltx_para" id="S5.SS4.p3"> <p class="ltx_p" id="S5.SS4.p3.1"><a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S5.T1" title="Table I ‣ V-D Finetuning ‣ V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Table I</span></a> reports preliminary results of fine-tuning the GPT’s models on the Masala-CHAI datasets generated. We picked 20 common design problems frequently used as a standalone circuit or sub-part of a bigger design. We prompted the LLM to generate (<span class="ltx_text ltx_font_italic" id="S5.SS4.p3.1.1">n</span> = 10) samples of SPICE netlist for each circuit description and manually validated their correctness (the score reported is the number of correct SPICE netlists). We subdivided the 20 benchmarks into 3 different categories: <span class="ltx_text ltx_font_italic" id="S5.SS4.p3.1.2">Easy</span> (ID=1-7), <span class="ltx_text ltx_font_italic" id="S5.SS4.p3.1.3">Medium</span> (ID=8-14), and <span class="ltx_text ltx_font_italic" id="S5.SS4.p3.1.4">Hard</span> (ID=15-20). <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S5.T1" title="Table I ‣ V-D Finetuning ‣ V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Table I</span></a> provides a comprehensive evaluation of the performance of GPT-3.5-turbo and GPT-4o-mini, both in their ‘base’ and ‘finetune’ states, on a diverse set of circuit design tasks. Finetuning demonstrates significant performance gains across nearly all circuits, particularly for complex designs. For instance, in the (ID=8), GPT-3.5-turbo improves from a score of 4 to 10. At the same time, GPT-4o-mini achieves a perfect score of 10 after fine-tuning, demonstrating the impact of domain-specific training. This pattern is evident across other tasks such as the (ID=5), where fine-tuning boosts GPT-3.5-turbo from 5 to 9 and GPT-4o-mini from 6 to 10.</p> </div> <div class="ltx_para" id="S5.SS4.p4"> <p class="ltx_p" id="S5.SS4.p4.1">The results reveal an important trend: simple circuits, such as the (ID=1) and (ID=3), are well-handled even by the base models. More advanced circuits like the (ID=14) and (ID=17) require fine-tuning to achieve meaningful results. Notably, finetuning enables GPT-4o-mini to score 8 on the (ID=10), doubling its base score of 4, illustrating the model’s scalability for complex tasks. GPT-4o-mini consistently outperforms GPT-3.5-turbo in handling advanced designs, achieving superior scores across several tasks.</p> </div> <div class="ltx_para" id="S5.SS4.p5"> <p class="ltx_p" id="S5.SS4.p5.1"><a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S5.T1" title="Table I ‣ V-D Finetuning ‣ V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Table I</span></a> reveals significant challenges, particularly with specialized circuits like the (ID=19) and (ID=20), where both models exhibit minimal gains even after finetuning. <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S5.F10" title="Figure 10 ‣ V-D Finetuning ‣ V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 10</span></a> showcases representative examples of both successful and failed netlists generated by LLMs, illustrating critical design challenges and the effectiveness of our approach. Notably, in <a class="ltx_ref ltx_refmacro_autoref" href="https://arxiv.org/html/2411.14299v4#S5.F10" title="Figure 10 ‣ V-D Finetuning ‣ V Results ‣ Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI"><span class="ltx_text ltx_ref_tag">Fig. 10</span></a>: (1) demonstrates the improper use of an NMOS as a current source rather than forming the intended cascode configuration; (2) highlights a fundamental error where the gate of a diode-connected transistor, expected to connect to the drain, is incorrectly connected to the source; (3) the complexity of a two-stage design further amplifies the difficulties in understanding and replicating the intended topology. These examples highlight the inherent limitations of unoptimized LLMs. Through the ‘Finetune’ GPT-4o-mini model, we successfully resolved these issues, achieving accurate connections and eliminating floating nets. This demonstrates the value of fine-tuning in enabling reliable and context-aware netlist generation.</p> </div> <figure class="ltx_figure" id="S5.F10"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="571" id="S5.F10.g1" src="x11.png" width="872"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure"><span class="ltx_text" id="S5.F10.2.1.1" style="font-size:90%;">Figure 10</span>: </span><span class="ltx_text" id="S5.F10.3.2" style="font-size:90%;">Examples of passed and failed design cases generated by the fine-tuned model.</span></figcaption> </figure> <figure class="ltx_table" id="S5.T1"> <figcaption class="ltx_caption"><span class="ltx_tag ltx_tag_table"><span class="ltx_text" id="S5.T1.2.1.1" style="font-size:90%;">TABLE I</span>: </span><span class="ltx_text" id="S5.T1.3.2" style="font-size:90%;">Results on 20 designs show the success rate of SPICE netlist generation (out of 10 samples, manually validated). ‘Base’ refers to the baseline model, and ‘Finetune’ indicates its fine-tuned version.</span></figcaption> <div class="ltx_inline-block ltx_align_center ltx_transformed_outer" id="S5.T1.4" style="width:433.6pt;height:344.4pt;vertical-align:-0.9pt;"><span class="ltx_transformed_inner" style="transform:translate(-33.2pt,26.3pt) scale(0.867334881455994,0.867334881455994) ;"> <table class="ltx_tabular ltx_align_middle" id="S5.T1.4.1"> <tbody class="ltx_tbody"> <tr class="ltx_tr" id="S5.T1.4.1.1.1"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r ltx_border_t" id="S5.T1.4.1.1.1.1" rowspan="2"><span class="ltx_text" id="S5.T1.4.1.1.1.1.1"><span class="ltx_text ltx_font_bold" id="S5.T1.4.1.1.1.1.1.1">ID</span></span></td> <td class="ltx_td ltx_align_left ltx_border_r ltx_border_t" id="S5.T1.4.1.1.1.2" rowspan="2"><span class="ltx_text" id="S5.T1.4.1.1.1.2.1"><span class="ltx_text ltx_font_bold" id="S5.T1.4.1.1.1.2.1.1">Circuit Description</span></span></td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" colspan="2" id="S5.T1.4.1.1.1.3"><span class="ltx_text ltx_font_bold" id="S5.T1.4.1.1.1.3.1">GPT-3.5-turbo</span> </td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" colspan="2" id="S5.T1.4.1.1.1.4"><span class="ltx_text ltx_font_bold" id="S5.T1.4.1.1.1.4.1">GPT-4o-mini</span> </td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.2.2"> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.2.2.1"><span class="ltx_text ltx_font_bold" id="S5.T1.4.1.2.2.1.1">Base</span></td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.2.2.2"><span class="ltx_text ltx_font_bold" id="S5.T1.4.1.2.2.2.1">Finetune</span></td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.2.2.3"><span class="ltx_text ltx_font_bold" id="S5.T1.4.1.2.2.3.1">Base</span></td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.2.2.4"><span class="ltx_text ltx_font_bold" id="S5.T1.4.1.2.2.4.1">Finetune</span></td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.3.3"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r ltx_border_t" id="S5.T1.4.1.3.3.1">1</td> <td class="ltx_td ltx_align_left ltx_border_r ltx_border_t" id="S5.T1.4.1.3.3.2">Common-source amplifier</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.3.3.3">8</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.3.3.4">10</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.3.3.5">8</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.3.3.6">10</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.4.4"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.4.4.1">2</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.4.4.2">2-stage common source amplifier with resistive load</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.4.4.3">6</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.4.4.4">10</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.4.4.5">8</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.4.4.6">10</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.5.5"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.5.5.1">3</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.5.5.2">Common-drain amplifier</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.5.5.3">8</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.5.5.4">10</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.5.5.5">10</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.5.5.6">10</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.6.6"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.6.6.1">4</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.6.6.2">common-gate amplifier</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.6.6.3">7</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.6.6.4">10</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.6.6.5">10</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.6.6.6">10</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.7.7"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.7.7.1">5</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.7.7.2">Single-Stage RC Low-Pass Filter</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.7.7.3">5</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.7.7.4">9</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.7.7.5">6</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.7.7.6">10</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.8.8"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.8.8.1">6</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.8.8.2">Source Degenerated Amplifier</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.8.8.3">6</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.8.8.4">8</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.8.8.5">6</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.8.8.6">10</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.9.9"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.9.9.1">7</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.9.9.2">Current Mirror</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.9.9.3">5</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.9.9.4">9</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.9.9.5">5</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.9.9.6">9</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.10.10"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r ltx_border_t" id="S5.T1.4.1.10.10.1">8</td> <td class="ltx_td ltx_align_left ltx_border_r ltx_border_t" id="S5.T1.4.1.10.10.2">Common-source amplifier using active load</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.10.10.3">4</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.10.10.4">10</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.10.10.5">7</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.10.10.6">10</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.11.11"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.11.11.1">9</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.11.11.2">Cascode amplifier using NMOS and resistive load</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.11.11.3">6</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.11.11.4">10</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.11.11.5">6</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.11.11.6">8</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.12.12"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.12.12.1">10</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.12.12.2">1-stage differential amplifier</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.12.12.3">2</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.12.12.4">7</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.12.12.5">4</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.12.12.6">8</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.13.13"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.13.13.1">11</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.13.13.2">Diode-connected Amplifier</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.13.13.3">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.13.13.4">3</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.13.13.5">3</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.13.13.6">9</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.14.14"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.14.14.1">12</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.14.14.2">Buffer design using MOSFET</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.14.14.3">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.14.14.4">4</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.14.14.5">2</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.14.14.6">8</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.15.15"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.15.15.1">13</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.15.15.2">2-input NAND gate</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.15.15.3">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.15.15.4">5</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.15.15.5">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.15.15.6">8</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.16.16"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.16.16.1">14</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.16.16.2">2-stage amplifier with miller compensation</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.16.16.3">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.16.16.4">1</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.16.16.5">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.16.16.6">7</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.17.17"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r ltx_border_t" id="S5.T1.4.1.17.17.1">15</td> <td class="ltx_td ltx_align_left ltx_border_r ltx_border_t" id="S5.T1.4.1.17.17.2">SRAM cell with 6 transistors</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.17.17.3">0</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.17.17.4">1</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.17.17.5">0</td> <td class="ltx_td ltx_align_center ltx_border_r ltx_border_t" id="S5.T1.4.1.17.17.6">6</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.18.18"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.18.18.1">16</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.18.18.2">2-stage op-amp with differential inputs and single-handled output</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.18.18.3">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.18.18.4">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.18.18.5">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.18.18.6">4</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.19.19"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.19.19.1">17</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.19.19.2">Fully Differential Amplifier with Common-Mode Feedback</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.19.19.3">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.19.19.4">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.19.19.5">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.19.19.6">3</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.20.20"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.20.20.1">18</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.20.20.2">Cross-coupled LC oscillator</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.20.20.3">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.20.20.4">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.20.20.5">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.20.20.6">3</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.21.21"> <td class="ltx_td ltx_align_center ltx_border_l ltx_border_r" id="S5.T1.4.1.21.21.1">19</td> <td class="ltx_td ltx_align_left ltx_border_r" id="S5.T1.4.1.21.21.2">Telescopic cascode operational amplifier</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.21.21.3">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.21.21.4">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.21.21.5">0</td> <td class="ltx_td ltx_align_center ltx_border_r" id="S5.T1.4.1.21.21.6">2</td> </tr> <tr class="ltx_tr" id="S5.T1.4.1.22.22"> <td class="ltx_td ltx_align_center ltx_border_b ltx_border_l ltx_border_r" id="S5.T1.4.1.22.22.1">20</td> <td class="ltx_td ltx_align_left ltx_border_b ltx_border_r" id="S5.T1.4.1.22.22.2">Bandgap Reference Amplifier</td> <td class="ltx_td ltx_align_center ltx_border_b ltx_border_r" id="S5.T1.4.1.22.22.3">0</td> <td class="ltx_td ltx_align_center ltx_border_b ltx_border_r" id="S5.T1.4.1.22.22.4">0</td> <td class="ltx_td ltx_align_center ltx_border_b ltx_border_r" id="S5.T1.4.1.22.22.5">0</td> <td class="ltx_td ltx_align_center ltx_border_b ltx_border_r" id="S5.T1.4.1.22.22.6">0</td> </tr> </tbody> </table> </span></div> </figure> </section> </section> <section class="ltx_section" id="S6"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">VI </span><span class="ltx_text ltx_font_smallcaps" id="S6.1.1">Conclusion and Future Work</span> </h2> <div class="ltx_para" id="S6.p1"> <p class="ltx_p" id="S6.p1.1">In this paper, we introduced Masala-CHAI, a novel framework to create large-scale datasets for SPICE netlists from documents comprising analog circuit schematics, addressing critical challenges in the design workflow. Through schematic preprocessing and prompt tuning, we developed a fully automated pipeline that leverages LLMs for scalable netlist generation. To the best of our knowledge, Masala-CHAI is the first LLM-based framework of its kind, and our released dataset and flow <cite class="ltx_cite ltx_citemacro_cite">[<a class="ltx_ref" href="https://arxiv.org/html/2411.14299v4#bib.bib16" title="">16</a>]</cite> provide a valuable resource for the community for future advancements.</p> </div> <div class="ltx_para" id="S6.p2"> <p class="ltx_p" id="S6.p2.1">Future work will focus on enhancing the framework with automated parameter tuning to ensure functionally validated netlists. Additionally, we aim to extend automation to the layout generation stage, addressing its inherent challenges by curating comprehensive datasets and fine-tuning LLMs for this task. These advancements will further streamline the analog design process, bridging the gap from schematic to GDSII and unlocking new efficiencies in IC design workflows.</p> </div> </section> <section class="ltx_bibliography" id="bib"> <h2 class="ltx_title ltx_title_bibliography">References</h2> <ul class="ltx_biblist"> <li class="ltx_bibitem" id="bib.bib1"> <span class="ltx_tag ltx_tag_bibitem">[1]</span> <span class="ltx_bibblock"> M. Liu, N. Pinckney, B. Khailany, and H. Ren, “Verilogeval: Evaluating large language models for verilog code generation,” in <em class="ltx_emph ltx_font_italic" id="bib.bib1.1.1">2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)</em>. IEEE, 2023, pp. 1–8. </span> </li> <li class="ltx_bibitem" id="bib.bib2"> <span class="ltx_tag ltx_tag_bibitem">[2]</span> <span class="ltx_bibblock"> S. Thakur, J. Blocklove, H. Pearce, B. Tan, S. Garg, and R. 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