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<div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Integrated circuit composed of several vertically stacked chips</div> A three-dimensional integrated circuit (3D IC) is a <a href="/wiki/MOSFET" title="MOSFET">MOS</a> (metal-oxide semiconductor) <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, <a href="/wiki/Through-silicon_via" title="Through-silicon via">through-silicon vias</a> (TSVs) or Cu-Cu connections,<a href="#cite_note-1">[1]</a><a href="#cite_note-2">[2]</a> so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in <a href="/wiki/Microelectronics" title="Microelectronics">microelectronics</a> and <a href="/wiki/Nanoelectronics" title="Nanoelectronics">nanoelectronics</a>. 3D integrated circuits can be classified by their level of interconnect hierarchy at the global (<a href="/wiki/Integrated_circuit_packaging" title="Integrated circuit packaging">package</a>), intermediate (bond pad) and local (<a href="/wiki/Transistor" title="Transistor">transistor</a>) level.<a href="#cite_note-3">[3]</a> In general, 3D integration is a broad term that includes such technologies as 3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based integration; 3D stacked ICs (3D-SICs); 3D heterogeneous integration; and 3D systems integration;<a href="#cite_note-4">[4]</a><a href="#cite_note-AutoRE-24-5">[5]</a> as well as true monolithic 3D ICs. International organizations such as the Jisso Technology Roadmap Committee (JIC) and the <a href="/wiki/International_Technology_Roadmap_for_Semiconductors" title="International Technology Roadmap for Semiconductors">International Technology Roadmap for Semiconductors</a> (ITRS) have worked to classify the various 3D integration technologies to further the establishment of standards and roadmaps of 3D integration.<a href="#cite_note-6">[6]</a> As of the 2010s, 3D ICs are widely used for <a href="/wiki/NAND_flash" class="mw-redirect" title="NAND flash">NAND</a> <a href="/wiki/Flash_memory" title="Flash memory">flash memory</a> and in <a href="/wiki/Mobile_device" title="Mobile device">mobile devices</a>. <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Types">Types</h2>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=1" title="Edit section: Types">edit</a>]</div> <div class="mw-heading mw-heading3"><h3 id="3D_ICs_vs._3D_packaging">3D ICs vs. 3D packaging</h3>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=2" title="Edit section: 3D ICs vs. 3D packaging">edit</a>]</div> 3D packaging refers to 3D integration schemes that rely on traditional interconnection methods such as <a href="/wiki/Wire_bonding" title="Wire bonding">wire bonding</a> and <a href="/wiki/Flip_chip" title="Flip chip">flip chip</a> to achieve vertical stacking. 3D packaging can be divided into 3D <a href="/wiki/System_in_package" class="mw-redirect" title="System in package">system in package</a> (3D SiP) and 3D <a href="/wiki/Wafer_level_package" class="mw-redirect" title="Wafer level package">wafer level package</a> (3D WLP). 3D SiPs that have been in mainstream manufacturing for some time and have a well-established infrastructure include stacked memory dies interconnected with wire bonds and <a href="/wiki/Package_on_package" class="mw-redirect" title="Package on package">package on package</a> (PoP) configurations interconnected with wire bonds or flip chip technology. PoP is used for vertically integrating disparate technologies. 3D WLP uses wafer level processes such as <a href="/wiki/Redistribution_layer" title="Redistribution layer">redistribution layers</a> (RDLs) and wafer bumping processes to form interconnects. 2.5D <a href="/wiki/Interposer" title="Interposer">interposer</a> is a 3D WLP that interconnects dies side-by-side on a silicon, glass, or organic interposer using through silicon vias (TSVs) and an RDL. In all types of 3D packaging, chips in the package communicate using off-chip signaling, much as if they were mounted in separate packages on a normal printed circuit board. The interposer may be made of silicon, and is under the dies it connects together. A design can be split into several dies, and then mounted on the interposer with micro bumps.<a href="#cite_note-7">[7]</a><a href="#cite_note-8">[8]</a><a href="#cite_note-9">[9]</a> 3D ICs can be divided into 3D Stacked ICs (3D SIC), which refers to <a href="/wiki/Advanced_packaging_(semiconductors)" title="Advanced packaging (semiconductors)">advanced packaging</a> techniques<a href="#cite_note-10">[10]</a><a href="#cite_note-11">[11]</a><a href="#cite_note-12">[12]</a> stacking IC chips using TSV interconnects, and monolithic 3D ICs, which use fab processes to realize 3D interconnects at the local levels of the on-chip wiring hierarchy as set forth by the ITRS, this results in direct vertical interconnects between device layers. The first examples of a monolithic approach are seen in <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a>'s 3D <a href="/wiki/V-NAND" class="mw-redirect" title="V-NAND">V-NAND</a> devices.<a href="#cite_note-13">[13]</a> As of the 2010s, 3D IC packages are widely used for <a href="/wiki/NAND_flash" class="mw-redirect" title="NAND flash">NAND flash</a> memory in <a href="/wiki/Mobile_devices" class="mw-redirect" title="Mobile devices">mobile devices</a>.<a href="#cite_note-James-14">[14]</a> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:3DS_die_stacking_concept_model.PNG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/25/3DS_die_stacking_concept_model.PNG/220px-3DS_die_stacking_concept_model.PNG" decoding="async" width="220" height="97" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/25/3DS_die_stacking_concept_model.PNG/330px-3DS_die_stacking_concept_model.PNG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/25/3DS_die_stacking_concept_model.PNG/440px-3DS_die_stacking_concept_model.PNG 2x" data-file-width="1000" data-file-height="440" /></a><figcaption>One master die and three slave dies</figcaption></figure> <div class="mw-heading mw-heading3"><h3 id="3D_SiCs">3D SiCs</h3>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=3" title="Edit section: 3D SiCs">edit</a>]</div> The digital electronics market requires a higher density <a href="/wiki/Semiconductor_memory" title="Semiconductor memory">semiconductor memory</a> chip to cater to recently released <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> components, and the multiple die stacking technique has been suggested as a solution to this problem. <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a> disclosed the upcoming <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a> technology includes the "3D SiC" die stacking plan at "Server Memory Forum", November 1–2, 2011, Santa Clara, CA. In August 2014, <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a> started producing 64 GB <a href="/wiki/SDRAM" class="mw-redirect" title="SDRAM">SDRAM</a> modules for servers based on emerging <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a> (double-data rate 4) memory using 3D TSV package technology.<a href="#cite_note-15">[15]</a> Newer proposed standards for 3D stacked DRAM include Wide I/O, Wide I/O 2, <a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a>, <a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a>. <div class="mw-heading mw-heading3"><h3 id="Monolithic_3D_ICs">Monolithic 3D ICs</h3>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=4" title="Edit section: Monolithic 3D ICs">edit</a>]</div> True monolithic 3D ICs are built in layers on a single <a href="/wiki/Wafer_(electronics)" title="Wafer (electronics)">semiconductor wafer</a>, which is then <a href="/wiki/Wafer_dicing" class="mw-redirect" title="Wafer dicing">diced</a> into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or <a href="/wiki/Through-silicon_via" title="Through-silicon via">through-silicon vias</a>. In general, monolithic 3D ICs are still a developing technology and are considered by most to be several years away from production. Process temperature limitations can be addressed by partitioning the transistor fabrication into two phases. A high temperature phase which is done before layer transfer followed by a layer transfer using <a rel="nofollow" class="external text" href="http://www.monolithic3d.com/ion-cut-the-building-block.html">ion-cut</a>, also known as layer transfer, which has been used to produce <a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">Silicon on Insulator (SOI)</a> wafers for the past two decades. Multiple thin (10s–100s nanometer scale) layers of virtually defect-free Silicon can be created by utilizing low temperature (<400 °C) bond and cleave techniques, and placed on top of active transistor circuitry, followed by permanent finalization of the transistors using etch and deposition processes. This monolithic 3D IC technology has been researched at <a href="/wiki/Stanford_University" title="Stanford University">Stanford University</a> under a <a href="/wiki/DARPA" title="DARPA">DARPA</a>-sponsored grant. CEA-Leti also developed monolithic 3D IC approaches, called sequential 3D IC. In 2014, the French research institute introduced its CoolCube™, a low-temperature process flow that provides a true path to 3DVLSI.<a href="#cite_note-16">[16]</a> At Stanford University, researchers designed monolithic 3D ICs using carbon nanotube (CNT) structures vs. silicon using a wafer-scale low temperature CNT transfer processes that can be done at 120 °C.<a href="#cite_note-17">[17]</a> <div class="mw-heading mw-heading2"><h2 id="Manufacturing_technologies_for_3D_SiCs">Manufacturing technologies for 3D SiCs</h2>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=5" title="Edit section: Manufacturing technologies for 3D SiCs">edit</a>]</div> There are several methods for 3D IC design, including recrystallization and wafer bonding methods. There are two major types of wafer bonding, Cu-Cu connections (copper-to-copper connections between stacked ICs, used in TSVs)<a href="#cite_note-18">[18]</a><a href="#cite_note-Reif-19">[19]</a> and <a href="/wiki/Through-silicon_via" title="Through-silicon via">through-silicon via</a> (TSV). 3D ICs with TSVs may use solder microbumps, small solder balls as an interface between two individual dies in a 3D IC.<a href="#cite_note-20">[20]</a> As of 2014, a number of memory products such as <a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a> (HBM) and the <a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a> have been launched that implement 3D IC stacking with TSVs. There are a number of key stacking approaches being implemented and explored. These include die-to-die, die-to-wafer, and wafer-to-wafer. <dl><dt>Die-to-Die</dt> <dd>Electronic components are built on multiple die, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding. One advantage of die-to-die is that each component die can be tested first, so that one bad die does not ruin an entire stack.<a href="#cite_note-AutoRE-5-21">[21]</a> Moreover, each die in the 3D IC can be binned beforehand, so that they can be mixed and matched to optimize power consumption and performance (e.g. matching multiple dice from the low power process corner for a mobile application).</dd> <dt>Die-to-Wafer</dt> <dd>Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">dice</a> are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional die may be added to the stacks before dicing.<a href="#cite_note-22">[22]</a></dd> <dt>Wafer-to-Wafer</dt> <dd><a href="/wiki/Electronic_component" title="Electronic component">Electronic components</a> are built on two or more <a href="/wiki/Wafer_(electronics)" title="Wafer (electronics)">semiconductor wafers</a>, which are then aligned, bonded, and <a href="/wiki/Wafer_dicing" class="mw-redirect" title="Wafer dicing">diced</a> into 3D ICs. Each wafer may be thinned before or after bonding. Vertical <a href="/wiki/Electrical_connection" class="mw-redirect" title="Electrical connection">connections</a> are either built into the wafers before bonding or else created in the stack after bonding. These "<a href="/wiki/Through-silicon_via" title="Through-silicon via">through-silicon vias</a>" (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad. Wafer-to-wafer bonding can reduce yields, since if any 1 of N chips in a 3D IC are defective, the entire 3D IC will be defective. Moreover, the wafers must be the same size, but many exotic materials (e.g. III-Vs) are manufactured on much smaller wafers than <a href="/wiki/CMOS_logic" class="mw-redirect" title="CMOS logic">CMOS logic</a> or <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a> (typically 300 mm), complicating heterogeneous integration.</dd></dl> <div class="mw-heading mw-heading2"><h2 id="Benefits">Benefits</h2>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=6" title="Edit section: Benefits">edit</a>]</div> While traditional <a href="/wiki/CMOS" title="CMOS">CMOS</a> scaling processes improves signal propagation speed, scaling from current manufacturing and chip-design technologies is becoming more difficult and costly, in part because of power-density constraints, and in part because interconnects do not become faster while transistors do.<a href="#cite_note-AutoRE-6-23">[23]</a> 3D ICs address the scaling challenge by stacking 2D dies and connecting them in the 3rd dimension. This promises to speed up communication between layered chips, compared to planar layout.<a href="#cite_note-AutoRE-7-24">[24]</a> 3D ICs promise many significant benefits, including: <dl><dt>Footprint</dt> <dd>More functionality fits into a small space. The smaller form factors are of great importance in embedded devices such as mobile phones, IoT systems for which 3D non-volatile memory stacks have been developed (e.g. 3D NAND chips) <a rel="nofollow" class="external autonumber" href="https://www.electronicdesign.com/technologies/embedded/article/21247462/electronic-design-3d-nand-memory-chips-stacked-high-at-micron">[1]</a> :: Moore's Law Extension: The increased number of transistors being packed in the same footprint is seen as an extension to <a href="/wiki/Moore%27s_law" title="Moore's law">Moore's law</a> by some researchers. This enables extending the Moore's Law without its traditional pair of Dennard Scaling towards a new generation of chips with increased computing capacity for the same footprint.<a rel="nofollow" class="external autonumber" href="https://spectrum.ieee.org/3d-cmos">[2]</a>:</dd> <dt>Cost</dt> <dd>Partitioning a large chip into multiple smaller dies with 3D stacking can improve the yield and reduce the fabrication cost if individual dies are tested separately.<a href="#cite_note-AutoRE-8-25">[25]</a><a href="#cite_note-AutoRE-9-26">[26]</a></dd> <dt>Heterogeneous Integration</dt> <dd>Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Moreover, components with incompatible manufacturing could be combined in a single 3D IC.<a href="#cite_note-AutoRE-10-27">[27]</a><a href="#cite_note-AutoRE-24-5">[5]</a></dd> <dt>Shorter Interconnect</dt> <dd>The average wire length is reduced. Common figures reported by researchers are on the order of 10–15%, but this reduction mostly applies to longer interconnect, which may affect circuit delay by a greater amount. Given that 3D wires have much higher capacitance than conventional in-die wires, circuit delay may or may not improve.</dd> <dt>Power</dt> <dd>Keeping a signal on-chip can reduce its <a href="/wiki/Power_consumption" class="mw-redirect" title="Power consumption">power consumption</a> by 10–100 times.<a href="#cite_note-AutoRE-11-28">[28]</a> Shorter wires also reduce power consumption by producing less <a href="/wiki/Parasitic_capacitance" title="Parasitic capacitance">parasitic capacitance</a>.<a href="#cite_note-AutoRE-12-29">[29]</a> Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.</dd> <dt>Design</dt> <dd>The vertical dimension adds a higher order of connectivity and offers new design possibilities.<a href="#cite_note-AutoRE-24-5">[5]</a></dd> <dt>Circuit Security</dt> <dd>3D integration can achieve <a href="/wiki/Security_through_obscurity" title="Security through obscurity">security through obscurity</a>; the stacked structure complicates attempts to <a href="/wiki/Reverse_engineering" title="Reverse engineering">reverse engineer</a> the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.<a href="#cite_note-AutoRE-13-30">[30]</a> Moreover, 3D integration allows to integrate dedicated, <a href="/wiki/System_monitor" title="System monitor">system monitor</a>-like features in separate layers.<a href="#cite_note-AutoRE-24-5">[5]</a> The objective here is to implement some kind of hardware <a href="/wiki/Firewall_(computing)" title="Firewall (computing)">firewall</a> for any commodity components/chips to be monitored at runtime, seeking to protect the whole <a href="/wiki/Electronic_system" class="mw-redirect" title="Electronic system">electronic system</a> against run-time attacks as well as malicious hardware modifications.</dd> <dt><a href="/wiki/Bandwidth_(signal_processing)" title="Bandwidth (signal processing)">Bandwidth</a></dt> <dd>3D integration allows large numbers of vertical vias between the layers. This allows construction of wide bandwidth <a href="/wiki/Bus_(computing)" title="Bus (computing)">buses</a> between functional blocks in different layers. A typical example would be a processor+memory 3D stack, with the cache memory stacked on top of the processor. This arrangement allows a bus much wider than the typical 128 or 256 bits between the cache and processor.<a href="#cite_note-AutoRE-14-31">[31]</a> Wide buses in turn alleviate the <a href="/wiki/Memory_wall" class="mw-redirect" title="Memory wall">memory wall</a> problem.<a href="#cite_note-AutoRE-15-32">[32]</a></dd></dl> Modularity 3D integration modular integration a wide range of custom stacks through standardizing the layer interfaces for numerous stacking options. As a result, custom stack designs can be manufactured with modular building blocks (e.g. custom number of DRAM or eDRAM layers, custom accelerator layers, customizable Non-Volatile Memory layers can be integrated to meet different design requirements). This provides design and cost advantages to semiconductor firms.<a rel="nofollow" class="external autonumber" href="https://ieeexplore.ieee.org/abstract/document/5510586">[3]</a> Other potential advantages include better integration of neuromorphic chips in computing systems. Despite being low power alternatives to general purpose CPUs and GPUs, neuromorphic chips use a fundamentally different "spike-based" computation, which is not directly compatible with legacy digital computation. 3D integration provides key opportunities in this integration.<a rel="nofollow" class="external autonumber" href="https://physicsworld.com/a/are-neuromorphic-systems-the-future-of-high-performance-computing/">[4]</a> <div class="mw-heading mw-heading2"><h2 id="Challenges">Challenges</h2>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=7" title="Edit section: Challenges">edit</a>]</div> Because this technology is new, it carries new challenges, including: <dl><dt>Cost</dt> <dd>While cost is a benefit when compared with scaling, it has also been identified as a challenge to the commercialization of 3D ICs in mainstream consumer applications. However, work is being done to address this. Although 3D technology is new and fairly complex, the cost of the manufacturing process is surprisingly straightforward when broken down into the activities that build up the entire process. By analyzing the combination of activities that lay at the base, cost drivers can be identified. Once the cost drivers are identified, it becomes a less complicated endeavor to determine where the majority of cost comes from and, more importantly, where cost has the potential to be reduced.<a href="#cite_note-33">[33]</a></dd> <dt>Yield</dt> <dd>Each extra manufacturing step adds a risk for defects. In order for 3D ICs to be commercially viable, defects could be repaired or tolerated, or defect density can be improved.<a href="#cite_note-AutoRE-16-34">[34]</a><a href="#cite_note-leedt09-35">[35]</a></dd> <dt>Heat</dt> <dd>Heat building up within the stack must be dissipated. This is an inevitable issue as electrical proximity correlates with thermal proximity. Specific thermal hotspots must be more carefully managed.</dd> <dt>Design Complexity</dt> <dd>Taking full advantage of 3D integration requires sophisticated design techniques and new <a href="/wiki/Computer-aided_design" title="Computer-aided design">CAD</a> tools.<a href="#cite_note-AutoRE-17-36">[36]</a></dd> <dt>TSV-introduced Overhead</dt> <dd><a href="/wiki/Through-silicon_via" title="Through-silicon via">TSVs</a> are large compared to gates and impact <a href="/wiki/Floorplan_(microelectronics)" title="Floorplan (microelectronics)">floorplans</a>. At the 45 nm technology node, the area footprint of a 10μm x 10μm TSV is comparable to that of about 50 gates.<a href="#cite_note-kim09-37">[37]</a> Furthermore, manufacturability demands landing pads and keep-out zones which further increase TSV area footprint. Depending on the technology choices, TSVs block some subset of layout resources.<a href="#cite_note-kim09-37">[37]</a> Via-first TSVs are manufactured before metallization, thus occupy the device layer and result in placement obstacles. Via-last TSVs are manufactured after metallization and pass through the chip. Thus, they occupy both the device and metal layers, resulting in placement and routing obstacles. While the usage of TSVs is generally expected to reduce wirelength, this depends on the number of TSVs and their characteristics.<a href="#cite_note-kim09-37">[37]</a> Also, the granularity of inter-die partitioning impacts wirelength. It typically decreases for moderate (blocks with 20-100 modules) and coarse (block-level partitioning) granularities, but increases for fine (gate-level partitioning) granularities.<a href="#cite_note-kim09-37">[37]</a></dd> <dt>Testing</dt> <dd>To achieve high overall yield and reduce costs, separate testing of independent dies is essential.<a href="#cite_note-leedt09-35">[35]</a><a href="#cite_note-S._Borkar,_2011,_pp._214-38">[38]</a> However, tight integration between adjacent active layers in 3D ICs entails a significant amount of interconnect between different sections of the same circuit module that were partitioned to different dies. Aside from the massive overhead introduced by required TSVs, sections of such a module, e.g., a multiplier, cannot be independently tested by conventional techniques. This particularly applies to timing-critical paths laid out in 3D.</dd> <dt>Lack of Standards</dt> <dd>There are few standards for TSV-based 3D IC design, manufacturing, and packaging, although this issue is being addressed.<a href="#cite_note-AutoRE-18-39">[39]</a><a href="#cite_note-AutoRE-19-40">[40]</a> In addition, there are many integration options being explored such as via-last, via-first, via-middle;<a href="#cite_note-AutoRE-20-41">[41]</a> <a href="/wiki/Interposer" title="Interposer">interposers</a><a href="#cite_note-AutoRE-21-42">[42]</a> or direct bonding; etc.</dd> <dt>Heterogeneous Integration Supply Chain</dt> <dd>In heterogeneously integrated systems, the delay of one part from one of the different parts suppliers delays the delivery of the whole product, and so delays the revenue for each of the 3D IC part suppliers.</dd> <dt>Lack of Clearly Defined Ownership</dt> <dd>It is unclear who should own the 3D IC integration and packaging/assembly. It could be assembly houses like <a href="/wiki/Advanced_Semiconductor_Engineering" class="mw-redirect" title="Advanced Semiconductor Engineering">ASE</a> or the product <a href="/wiki/OEM" class="mw-redirect" title="OEM">OEMs</a>.</dd></dl> Thermomechanical Stress and Reliability 3D stacks have more complex material compositions and thermomechanical profiles compared to 2D designs. The stacking of multiple thinned silicon layers, multiple wiring (BEOL) layers, insulators, through silicon vias, micro-C4s result in complex thermomechanical forces and stress patterns being exerted to the 3D stacks. As a result, local heating in one part of the stack (e.g. on thinned device layers) may result reliability challenges. This requires design-time analysis and reliability-aware design processes. <a rel="nofollow" class="external autonumber" href="https://ieeexplore.ieee.org/abstract/document/7955018">[5]</a> <div class="mw-heading mw-heading2"><h2 id="Design_styles">Design styles</h2>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=8" title="Edit section: Design styles">edit</a>]</div> Depending on partitioning granularity, different design styles can be distinguished. Gate-level integration faces multiple challenges and currently appears less practical than block-level integration.<a href="#cite_note-knechtel11-43">[43]</a> <dl><dt>Gate-level Integration</dt> <dd>This style partitions standard cells between multiple dies. It promises wirelength reduction and great flexibility. However, wirelength reduction may be undermined unless modules of certain minimal size are preserved. On the other hand, its adverse effects include the massive number of necessary TSVs for interconnects. This design style requires 3D <a href="/wiki/Place_and_route" title="Place and route">place-and-route</a> tools, which are unavailable yet. Also, partitioning a design block across multiple dies implies that it cannot be fully <a href="/wiki/Semiconductor_fabrication#Device_test" class="mw-redirect" title="Semiconductor fabrication">tested</a> before die stacking. After die stacking (post-bond testing), a single failed die can render several good dies unusable, undermining yield. This style also amplifies the impact of <a href="/wiki/Process_variation_(semiconductor)" title="Process variation (semiconductor)">process variation</a>, especially inter-die variation. In fact, a 3D layout may yield more poorly than the same circuit laid out in 2D, contrary to the original promise of 3D IC integration.<a href="#cite_note-AutoRE-22-44">[44]</a> Furthermore, this design style requires to redesign available Intellectual Property, since existing <a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">IP blocks</a> and EDA tools do not provision for 3D integration.</dd> <dt>Block-level Integration</dt> <dd>This style assigns entire design blocks to separate dies. Design blocks subsume most of the <a href="/wiki/Netlist" title="Netlist">netlist</a> connectivity and are linked by a small number of global interconnects. Therefore, block-level integration promises to reduce TSV overhead. Sophisticated 3D systems combining heterogeneous dies require distinct manufacturing processes at different technology nodes for fast and low-power random logic, several memory types, analog and RF circuits, etc. Block-level integration, which allows separate and optimized manufacturing processes, thus appears crucial for 3D integration. Furthermore, this style might facilitate the transition from current 2D design towards 3D IC design. Basically, 3D-aware tools are only needed for partitioning and thermal analysis.<a href="#cite_note-AutoRE-23-45">[45]</a> Separate dies will be designed using (adapted) 2D tools and 2D blocks. This is motivated by the broad availability of reliable IP blocks. It is more convenient to use available 2D IP blocks and to place the mandatory TSVs in the unoccupied space between blocks instead of redesigning IP blocks and embedding TSVs.<a href="#cite_note-knechtel11-43">[43]</a> <a href="/wiki/Design_for_test" class="mw-redirect" title="Design for test">Design-for-testability</a> structures are a key component of IP blocks and can therefore be used to facilitate testing for 3D ICs. Also, critical paths can be mostly embedded within 2D blocks, which limits the impact of TSV and inter-die variation on manufacturing yield. Finally, modern chip design often requires <a href="/wiki/Engineering_Change_Order#Chip_design" class="mw-redirect" title="Engineering Change Order">last-minute engineering changes</a>. Restricting the impact of such changes to single dies is essential to limit cost.</dd></dl> <div class="mw-heading mw-heading2"><h2 id="History">History</h2>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=9" title="Edit section: History">edit</a>]</div> Several years after the <a href="/wiki/MOS_integrated_circuit" class="mw-redirect" title="MOS integrated circuit">MOS integrated circuit</a> (MOS IC) chip was first proposed by <a href="/wiki/Mohamed_Atalla" class="mw-redirect" title="Mohamed Atalla">Mohamed Atalla</a> at <a href="/wiki/Bell_Labs" title="Bell Labs">Bell Labs</a> in 1960,<a href="#cite_note-Moskowitz-46">[46]</a> the concept of a three-dimensional MOS integrated circuit was proposed by <a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> researchers Robert W. Haisty, Rowland E. Johnson and Edward W. Mehal in 1964.<a href="#cite_note-47">[47]</a> In 1969, the concept of a three-dimensional MOS integrated circuit <a href="/wiki/Memory_chip" class="mw-redirect" title="Memory chip">memory chip</a> was proposed by <a href="/wiki/NEC" title="NEC">NEC</a> researchers Katsuhiro Onoda, Ryo Igarashi, Toshio Wada, Sho Nakanuma and Toru Tsujide.<a href="#cite_note-48">[48]</a> <a href="/wiki/Arm_(company)" class="mw-redirect" title="Arm (company)">Arm</a> has made a high-density 3D logic test chip,<a href="#cite_note-49">[49]</a> and <a href="/wiki/Intel" title="Intel">Intel</a> with its Foveros 3D logic chip packing is planning to ship CPUs using it.<a href="#cite_note-50">[50]</a> IBM demonstrated a fluid that could be used for both power delivery and cooling 3D ICs.<a href="#cite_note-51">[51]</a> <div class="mw-heading mw-heading3"><h3 id="Demonstrations_(1983–2012)">Demonstrations (1983–2012)</h3>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=10" title="Edit section: Demonstrations (1983–2012)">edit</a>]</div> <div class="mw-heading mw-heading4"><h4 id="Japan_(1983–2005)">Japan (1983–2005)</h4>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=11" title="Edit section: Japan (1983–2005)">edit</a>]</div> 3D ICs were first successfully demonstrated in <a href="/wiki/1980s_in_Japan" title="1980s in Japan">1980s Japan</a>, where <a href="/wiki/Research_and_development" title="Research and development">research and development</a> (R&D) on 3D ICs was initiated in 1981 with the "Three Dimensional Circuit Element R&D Project" by the Research and Development Association for Future (New) Electron Devices.<a href="#cite_note-Kada8-52">[52]</a> There were initially two forms of 3D IC design being investigated, recrystallization and <a href="/wiki/Wafer_bonding" title="Wafer bonding">wafer bonding</a>, with the earliest successful demonstrations using recrystallization.<a href="#cite_note-Reif-19">[19]</a> In October 1983, a <a href="/wiki/Fujitsu" title="Fujitsu">Fujitsu</a> research team including S. Kawamura, Nobuo Sasaki and T. Iwai successfully <a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">fabricated</a> a three-dimensional <a href="/wiki/Complementary_metal%E2%80%93oxide%E2%80%93semiconductor" class="mw-redirect" title="Complementary metal–oxide–semiconductor">complementary metal–oxide–semiconductor</a> (CMOS) integrated circuit, using laser beam recrystallization. It consisted of a structure in which one type of <a href="/wiki/Transistor" title="Transistor">transistor</a> is fabricated directly above a transistor of the opposite type, with separate gates and an insulator in between. A double-layer of <a href="/wiki/Silicon_nitride" title="Silicon nitride">silicon nitride</a> and <a href="/wiki/Phosphosilicate_glass" title="Phosphosilicate glass">phosphosilicate glass</a> (PSG) film was used as an intermediate insulating layer between the top and bottom devices. This provided the basis for realizing a multi-layered 3D device composed of vertically stacked transistors, with separate gates and an insulating layer in between.<a href="#cite_note-53">[53]</a> In December 1983, the same Fujitsu research team fabricated a 3D integrated circuit with a <a href="/wiki/Silicon-on-insulator" class="mw-redirect" title="Silicon-on-insulator">silicon-on-insulator</a> (SOI) CMOS structure.<a href="#cite_note-54">[54]</a> The following year, they fabricated a 3D <a href="/wiki/Gate_array" title="Gate array">gate array</a> with vertically stacked dual SOI/CMOS structure using beam recrystallization.<a href="#cite_note-55">[55]</a> In 1986, <a href="/wiki/Mitsubishi_Electric" title="Mitsubishi Electric">Mitsubishi Electric</a> researchers Yoichi Akasaka and Tadashi Nishimura laid out the basic concepts and proposed technologies for 3D ICs.<a href="#cite_note-Garrou-56">[56]</a><a href="#cite_note-57">[57]</a> The following year, a Mitsubishi research team including Nishimura, Akasaka and <a href="/wiki/Osaka_University" title="Osaka University">Osaka University</a> graduate Yasuo Inoue fabricated an <a href="/wiki/Image_signal_processor" class="mw-redirect" title="Image signal processor">image signal processor</a> (ISP) on a 3D IC, with an array of <a href="/wiki/Photosensors" class="mw-redirect" title="Photosensors">photosensors</a>, CMOS <a href="/wiki/A-to-D_converter" class="mw-redirect" title="A-to-D converter">A-to-D converters</a>, <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">arithmetic logic units</a> (ALU) and <a href="/wiki/Shift_registers" class="mw-redirect" title="Shift registers">shift registers</a> arranged in a three-layer structure.<a href="#cite_note-58">[58]</a> In 1989, an <a href="/wiki/NEC" title="NEC">NEC</a> research team led by Yoshihiro Hayashi fabricated a 3D IC with a four-layer structure using laser beam crystallisation.<a href="#cite_note-59">[59]</a><a href="#cite_note-Garrou-56">[56]</a> In 1990, a <a href="/wiki/Panasonic" title="Panasonic">Matsushita</a> research team including K. Yamazaki, Y. Itoh and A. Wada fabricated a <a href="/wiki/Parallel_processing_(DSP_implementation)" title="Parallel processing (DSP implementation)">parallel</a> image signal processor on a four-layer 3D IC, with SOI (<a href="/wiki/Silicon-on-insulator" class="mw-redirect" title="Silicon-on-insulator">silicon-on-insulator</a>) layers formed by laser recrystallization, and the four layers consisting of an <a href="/wiki/Optical_sensor" class="mw-redirect" title="Optical sensor">optical sensor</a>, level detector, <a href="/wiki/Semiconductor_memory" title="Semiconductor memory">memory</a> and ALU.<a href="#cite_note-60">[60]</a> The most common form of 3D IC design is wafer bonding.<a href="#cite_note-Reif-19">[19]</a> Wafer bonding was initially called "cumulatively bonded IC" (CUBIC), which began development in 1981 with the "Three Dimensional Circuit Element R&D Project" in Japan and was completed in 1990 by Yoshihiro Hayashi's NEC research team, who demonstrated a method where several <a href="/wiki/Thin-film" class="mw-redirect" title="Thin-film">thin-film</a> devices are bonded cumulatively, which would allow a large number of device layers. They proposed fabrication of separate devices in separate wafers, reduction in the thickness of the wafers, providing front and back leads, and connecting the thinned <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">die</a> to each other. They used CUBIC technology to fabricate and test a two active layer device in a top-to-bottom fashion, having a bulk-Si <a href="/wiki/NMOS_FET" class="mw-redirect" title="NMOS FET">NMOS FET</a> lower layer and a thinned NMOS FET upper layer, and proposed CUBIC technology that could fabricate 3D ICs with more than three active layers.<a href="#cite_note-Garrou-56">[56]</a><a href="#cite_note-Kada8-52">[52]</a><a href="#cite_note-61">[61]</a> The first 3D IC stacked chips fabricated with a <a href="/wiki/Through-silicon_via" title="Through-silicon via">through-silicon via</a> (TSV) process were invented in 1980s Japan. <a href="/wiki/Hitachi" title="Hitachi">Hitachi</a> filed a Japanese patent in 1983, followed by Fujitsu in 1984. In 1986, a Japanese patent filed by Fujitsu described a stacked chip structure using TSV.<a href="#cite_note-Kada8-52">[52]</a> In 1989, Mitsumasa Koyonagi of <a href="/wiki/Tohoku_University" title="Tohoku University">Tohoku University</a> pioneered the technique of wafer-to-wafer bonding with TSV, which he used to fabricate a 3D <a href="/wiki/Large-scale_integration" class="mw-redirect" title="Large-scale integration">LSI</a> chip in 1989.<a href="#cite_note-Kada8-52">[52]</a><a href="#cite_note-Fukushima-62">[62]</a><a href="#cite_note-63">[63]</a> In 1999, the Association of Super-Advanced Electronics Technologies (ASET) in Japan began funding the development of 3D IC chips using TSV technology, called the "R&D on High Density Electronic System Integration Technology" project.<a href="#cite_note-Kada8-52">[52]</a><a href="#cite_note-Takahashi-64">[64]</a> The term "through-silicon via" (TSV) was coined by Tru-Si Technologies researchers Sergey Savastiouk, O. Siniaguine, and E. Korczynski, who proposed a TSV method for a 3D <a href="/wiki/Wafer-level_packaging" title="Wafer-level packaging">wafer-level packaging</a> (WLP) solution in 2000.<a href="#cite_note-65">[65]</a> The Koyanagi Group at <a href="/wiki/Tohoku_University" title="Tohoku University">Tohoku University</a>, led by Mitsumasa Koyanagi, used TSV technology to fabricate a three-layer <a href="/wiki/Memory_chip" class="mw-redirect" title="Memory chip">memory chip</a> in 2000, a three-layer artificial retina chip in 2001, a three-layer <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a> in 2002, and a ten-layer memory chip in 2005.<a href="#cite_note-Fukushima-62">[62]</a> The same year, a <a href="/wiki/Stanford_University" title="Stanford University">Stanford University</a> research team consisting of <a href="/wiki/Kaustav_Banerjee" title="Kaustav Banerjee">Kaustav Banerjee</a>, Shukri J. Souri, Pawan Kapur and Krishna C. Saraswat presented a novel 3D chip design that exploits the vertical dimension to alleviate the interconnect related problems and facilitates heterogeneous integration of technologies to realize a <a href="/wiki/System-on-a-chip" class="mw-redirect" title="System-on-a-chip">system-on-a-chip</a> (SoC) design.<a href="#cite_note-66">[66]</a><a href="#cite_note-67">[67]</a> In 2001, a <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> research team including T. Imoto, M. Matsui and C. Takubo developed a "System Block Module" wafer bonding process for manufacturing 3D IC packages.<a href="#cite_note-Garrou-56">[56]</a><a href="#cite_note-68">[68]</a> <div class="mw-heading mw-heading4"><h4 id="Europe_(1988–2005)">Europe (1988–2005)</h4>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=12" title="Edit section: Europe (1988–2005)">edit</a>]</div> <a href="/wiki/Fraunhofer_Society" title="Fraunhofer Society">Fraunhofer</a> and <a href="/wiki/Siemens" title="Siemens">Siemens</a> began research on 3D IC integration in 1987.<a href="#cite_note-Kada8-52">[52]</a> In 1988, they fabricated 3D CMOS IC devices based on re-crystallization of poly-silicon.<a href="#cite_note-69">[69]</a> In 1997, the inter-chip via (ICV) method was developed by a Fraunhofer–Siemens research team including Peter Ramm, Manfred Engelhardt, Werner Pamler, Christof Landesberger and Armin Klumpp.<a href="#cite_note-70">[70]</a> It was a first industrial 3D IC process, based on Siemens CMOS fab wafers. A variation of that TSV process was later called TSV-SLID (solid liquid inter-diffusion) technology.<a href="#cite_note-71">[71]</a> It was an approach to 3D IC design based on low temperature wafer bonding and vertical integration of IC devices using inter-chip vias, which they patented. Ramm went on to develop industry-academic consortia for production of relevant 3D integration technologies. In the German funded cooperative VIC project between Siemens and Fraunhofer, they demonstrated a complete industrial 3D IC stacking process (1993–1996). With his Siemens and Fraunhofer colleagues, Ramm published results showing the details of key processes such as 3D metallization [T. Grassl, P. Ramm, M. Engelhardt, Z. Gabric, O. Spindler, First International Dielectrics for VLSI/ULSI Interconnection Metallization Conference – DUMIC, Santa Clara, CA, 20–22 Feb, 1995] and at ECTC 1995 they presented early investigations on stacked memory in processors.<a href="#cite_note-72">[72]</a> In the early 2000s, a team of Fraunhofer and Infineon Munich researchers investigated 3D TSV technologies with particular focus on die-to-substrate stacking within the German/Austrian EUREKA project VSI and initiated the European Integrating Projects e-CUBES, as a first European 3D technology platform, and e-BRAINS with a.o., Infineon, Siemens, EPFL, IMEC and Tyndall, where heterogeneous 3D integrated system demonstrators were fabricated and evaluated. A particular focus of the e-BRAINS project was the development of novel low-temperature processes for highly reliable 3D integrated sensor systems.<a href="#cite_note-73">[73]</a> <div class="mw-heading mw-heading4"><h4 id="United_States_(1999–2012)">United States (1999–2012)</h4>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=13" title="Edit section: United States (1999–2012)">edit</a>]</div> Copper-to-copper wafer bonding, also called Cu-Cu connections or Cu-Cu wafer bonding, was developed at <a href="/wiki/MIT" class="mw-redirect" title="MIT">MIT</a> by a research team consisting of Andy Fan, Adnan-ur Rahman and Rafael Reif in 1999.<a href="#cite_note-Reif-19">[19]</a><a href="#cite_note-74">[74]</a> Reif and Fan further investigated Cu-Cu wafer bonding with other MIT researchers including Kuan-Neng Chen, Shamik Das, Chuan Seng Tan and Nisha Checka during 2001–2002.<a href="#cite_note-Reif-19">[19]</a> In 2003, <a href="/wiki/DARPA" title="DARPA">DARPA</a> and the Microelectronics Center of North Carolina (MCNC) began funding R&D on 3D IC technology.<a href="#cite_note-Kada8-52">[52]</a> In 2004, Tezzaron Semiconductor<a href="#cite_note-75">[75]</a> built working 3D devices from six different designs.<a href="#cite_note-AutoRE-31-76">[76]</a> The chips were built in two layers with "via-first" tungsten TSVs for vertical interconnection. Two wafers were stacked face-to-face and bonded with a copper process. The top wafer was thinned and the two-wafer stack was then diced into chips. The first chip tested was a simple memory register, but the most notable of the set was an 8051 processor/memory stack<a href="#cite_note-77">[77]</a> that exhibited much higher speed and lower power consumption than an analogous 2D assembly. In 2004, <a href="/wiki/Intel" title="Intel">Intel</a> presented a 3D version of the <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a> CPU.<a href="#cite_note-AutoRE-1-78">[78]</a> The chip was manufactured with two dies using face-to-face stacking, which allowed a dense via structure. Backside TSVs are used for I/O and power supply. For the 3D floorplan, designers manually arranged functional blocks in each die aiming for power reduction and performance improvement. Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspots. The 3D design provides 15% performance improvement (due to eliminated pipeline stages) and 15% power saving (due to eliminated repeaters and reduced wiring) compared to the 2D Pentium 4. The <a href="/wiki/Teraflops_Research_Chip" title="Teraflops Research Chip">Teraflops Research Chip</a> introduced in 2007 by Intel is an experimental 80-core design with stacked memory. Due to the high demand for memory bandwidth, a traditional I/O approach would consume 10 to 25 W.<a href="#cite_note-S._Borkar,_2011,_pp._214-38">[38]</a> To improve upon that, Intel designers implemented a TSV-based memory bus. Each core is connected to one memory tile in the <a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a> die with a link that provides 12 GB/s bandwidth, resulting in a total bandwidth of 1 TB/s while consuming only 2.2 W. An academic implementation of a 3D processor was presented in 2008 at the <a href="/wiki/University_of_Rochester" title="University of Rochester">University of Rochester</a> by Professor Eby Friedman and his students. The chip runs at a 1.4 GHz and it was designed for optimized vertical processing between the stacked chips which gives the 3D processor abilities that the traditional one layered chip could not reach.<a href="#cite_note-AutoRE-2-79">[79]</a> One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in harmony without any obstacles that would interfere with a piece of information traveling from one layer to another.<a href="#cite_note-AutoRE-3-80">[80]</a> In ISSCC 2012, two 3D-IC-based multi-core designs using <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a>' 130 nm process and Tezzaron's FaStack technology were presented and demonstrated: <ul><li>3D-MAPS,<a href="#cite_note-AutoRE-4-81">[81]</a> a 64 custom core implementation with two-logic-die stack, was demonstrated by researchers from the School of Electrical and Computer Engineering at <a href="/wiki/Georgia_Institute_of_Technology" class="mw-redirect" title="Georgia Institute of Technology">Georgia Institute of Technology</a>.</li> <li>Centip3De,<a href="#cite_note-82">[82]</a> near-threshold design based on ARM Cortex-M3 cores, was from the Department of Electrical Engineering and Computer Science at <a href="/wiki/University_of_Michigan" title="University of Michigan">University of Michigan</a>.</li></ul> Though released much layer IBM Research and Semiconductor Research and Development Groups design and manufactured a number of 3D processor stacks successfully starting from 2007-2008. These stacks (dubbed Escher internally) have demonstrated successful implementation of eDRAM, logic and processor stacks as well as key experiments in power, thermal, noise and reliability characterization of 3D chips. <a rel="nofollow" class="external autonumber" href="https://ieeexplore.ieee.org/abstract/document/6176968">[6]</a> <div class="mw-heading mw-heading3"><h3 id="Commercial_3D_ICs_(2004–present)">Commercial 3D ICs (2004–present)</h3>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=14" title="Edit section: Commercial 3D ICs (2004–present)">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Psp-1000.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/46/Psp-1000.jpg/220px-Psp-1000.jpg" decoding="async" width="220" height="125" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/46/Psp-1000.jpg/330px-Psp-1000.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/46/Psp-1000.jpg/440px-Psp-1000.jpg 2x" data-file-width="3840" data-file-height="2180" /></a><figcaption><a href="/wiki/Sony" title="Sony">Sony</a>'s <a href="/wiki/PlayStation_Portable" title="PlayStation Portable">PlayStation Portable</a> (PSP) <a href="/wiki/Handheld_game_console" title="Handheld game console">handheld game console</a>, released in 2004, is the earliest commercial product to use a 3D IC, an <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a> <a href="/wiki/Memory_chip" class="mw-redirect" title="Memory chip">memory chip</a> manufactured by <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> in a 3D <a href="/wiki/System-in-package" class="mw-redirect" title="System-in-package">system-in-package</a>.</figcaption></figure> The earliest known commercial use of a 3D IC chip was in <a href="/wiki/Sony" title="Sony">Sony</a>'s <a href="/wiki/PlayStation_Portable" title="PlayStation Portable">PlayStation Portable</a> (PSP) <a href="/wiki/Handheld_game_console" title="Handheld game console">handheld game console</a>, released in 2004. The <a href="/wiki/PSP_hardware" class="mw-redirect" title="PSP hardware">PSP hardware</a> includes <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a> (embedded <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a>) <a href="/wiki/Computer_memory" title="Computer memory">memory</a> manufactured by <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> in a 3D <a href="/wiki/System-in-package" class="mw-redirect" title="System-in-package">system-in-package</a> chip with two <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">dies</a> stacked vertically.<a href="#cite_note-James-14">[14]</a> Toshiba called it "semi-embedded DRAM" at the time, before later calling it a stacked "<a href="/wiki/Package_on_package" class="mw-redirect" title="Package on package">chip-on-chip</a>" (CoC) solution.<a href="#cite_note-James-14">[14]</a><a href="#cite_note-83">[83]</a> In April 2007, Toshiba commercialized an eight-layer 3D IC, the 16 <a href="/wiki/Gibibyte" class="mw-redirect" title="Gibibyte">GB</a> THGAM <a href="/wiki/Embedded_system" title="Embedded system">embedded</a> <a href="/wiki/NAND_flash" class="mw-redirect" title="NAND flash">NAND flash</a> memory chip, which was manufactured with eight stacked 2 GB NAND flash chips.<a href="#cite_note-84">[84]</a> In September 2007, <a href="/wiki/Hynix" class="mw-redirect" title="Hynix">Hynix</a> introduced 24-layer 3D IC technology, with a 16 GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process.<a href="#cite_note-85">[85]</a> Toshiba also used an eight-layer 3D IC for their 32 GB THGBM flash chip in 2008.<a href="#cite_note-86">[86]</a> In 2010, Toshiba used a 16-layer 3D IC for their 128 GB THGBM2 flash chip, which was manufactured with 16 stacked 8 GB chips.<a href="#cite_note-toshiba2010-87">[87]</a> In the 2010s, 3D ICs came into widespread commercial use in the form of <a href="/wiki/Multi-chip_package" class="mw-redirect" title="Multi-chip package">multi-chip package</a> and <a href="/wiki/Package_on_package" class="mw-redirect" title="Package on package">package on package</a> solutions for <a href="/wiki/NAND_flash" class="mw-redirect" title="NAND flash">NAND flash</a> memory in <a href="/wiki/Mobile_devices" class="mw-redirect" title="Mobile devices">mobile devices</a>.<a href="#cite_note-James-14">[14]</a> <a href="/wiki/Elpida_Memory" class="mw-redirect" title="Elpida Memory">Elpida Memory</a> developed the first 8 <a href="/wiki/Gibibyte" class="mw-redirect" title="Gibibyte">GB</a> DRAM chip (stacked with four <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> <a href="/wiki/SDRAM" class="mw-redirect" title="SDRAM">SDRAM</a> dies) in September 2009, and released it in June 2011.<a href="#cite_note-Kada15-88">[88]</a> <a href="/wiki/TSMC" title="TSMC">TSMC</a> announced plans for 3D IC production with TSV technology in January 2010.<a href="#cite_note-Kada15-88">[88]</a> In 2011, <a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a> introduced 16 GB DDR3 SDRAM (<a href="/wiki/40_nanometer" class="mw-redirect" title="40 nanometer">40 nm</a> class) using TSV technology,<a href="#cite_note-hynix2010s-89">[89]</a> <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a> introduced 3D-stacked 32 GB DDR3 (<a href="/wiki/32_nanometer" class="mw-redirect" title="32 nanometer">30 nm</a> class) based on TSV in September, and then Samsung and <a href="/wiki/Micron_Technology" title="Micron Technology">Micron Technology</a> announced TSV-based <a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a> (HMC) technology in October.<a href="#cite_note-Kada15-88">[88]</a> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:High_Bandwidth_Memory_schematic.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b5/High_Bandwidth_Memory_schematic.svg/220px-High_Bandwidth_Memory_schematic.svg.png" decoding="async" width="220" height="124" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b5/High_Bandwidth_Memory_schematic.svg/330px-High_Bandwidth_Memory_schematic.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b5/High_Bandwidth_Memory_schematic.svg/440px-High_Bandwidth_Memory_schematic.svg.png 2x" data-file-width="960" data-file-height="540" /></a><figcaption>Cut through a <a href="/wiki/Graphics_card" title="Graphics card">graphics card</a> that uses <a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a> (HBM), based on <a href="/wiki/Through-silicon_via" title="Through-silicon via">through-silicon via</a> (TSV) 3D IC technology.</figcaption></figure> <a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a> (HBM), developed by Samsung, <a href="/wiki/AMD" title="AMD">AMD</a>, and SK Hynix, uses stacked chips and TSVs. The first HBM memory chip was manufactured by SK Hynix in 2013.<a href="#cite_note-hynix2010s-89">[89]</a> In January 2016, <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a> announced early mass production of <a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a>, at up to 8 GB per stack.<a href="#cite_note-samsung-hbm2-90">[90]</a><a href="#cite_note-extremetech=hbm2-91">[91]</a> In 2017, Samsung Electronics combined 3D IC stacking with its 3D <a href="/wiki/V-NAND" class="mw-redirect" title="V-NAND">V-NAND</a> technology (based on <a href="/wiki/Charge_trap_flash" title="Charge trap flash">charge trap flash</a> technology), manufacturing its 512 GB KLUFG8R1EM flash memory chip with eight stacked 64-layer V-NAND chips.<a href="#cite_note-anandtech-samsung-2017-92">[92]</a> In 2019, Samsung produced a 1 <a href="/wiki/Terabyte" class="mw-redirect" title="Terabyte">TB</a> flash chip with 16 stacked V-NAND dies.<a href="#cite_note-electronicsweekly-samsung-93">[93]</a><a href="#cite_note-anandtech-samsung-2018-94">[94]</a> As of 2018, Intel is considering the use of 3D ICs to improve performance.<a href="#cite_note-95">[95]</a> As of 2022<a class="external text" href="https://en.wikipedia.org/w/index.php?title=Three-dimensional_integrated_circuit&action=edit">[update]</a>, 232-layer NAND, i.e. memory device, chips are made by Micron,<a href="#cite_note-96">[96]</a> that previously in April 2019 were making 96-layer chips; and Toshiba made 96-layer devices in 2018. In 2022, AMD has introduced <a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> processors, and some Zen 4 processors have 3D Cache included. <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=15" title="Edit section: See also">edit</a>]</div> <ul><li><a href="/wiki/Advanced_packaging_(semiconductors)" title="Advanced packaging (semiconductors)">Advanced packaging (semiconductors)</a></li> <li><a href="/wiki/Charge_trap_flash" title="Charge trap flash">Charge trap flash</a> (CTF)</li> <li><a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a> (3D transistor)</li> <li><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a></li> <li><a href="/wiki/Multigate_device" title="Multigate device">Multigate device</a> (MuGFET)</li> <li><a href="/wiki/V-NAND" class="mw-redirect" title="V-NAND">V-NAND</a> (3D NAND)</li></ul> <div style="clear:both;" class=""></div> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=16" title="Edit section: Notes">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><a href="#cite_ref-1">^</a> <style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFHuLiuLiiRebibis2012" class="citation book cs1">Hu, Y.H.; Liu, C.S.; Lii, M.J.; Rebibis, K. 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Extremetech.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Extremetech&rft.atitle=Samsung+announces+mass+production+of+next-generation+HBM2+memory+%E2%80%93+ExtremeTech&rft.date=2016-01-19&rft.aulast=Hruska&rft.aufirst=Joel&rft_id=http%3A%2F%2Fwww.extremetech.com%2Fextreme%2F221473-samsung-announces-mass-production-of-next-generation-hbm2-memory&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"> </li> <li id="cite_note-anandtech-samsung-2017-92"><a href="#cite_ref-anandtech-samsung-2017_92-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShilov2017" class="citation news cs1">Shilov, Anton (December 5, 2017). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/12120/samsung-starts-production-of-512-gb-ufs-chips">"Samsung Starts Production of 512 GB UFS NAND Flash Memory: 64-Layer V-NAND, 860 MB/s Reads"</a>. <a href="/wiki/AnandTech" title="AnandTech">AnandTech</a>. Retrieved 23 June 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=AnandTech&rft.atitle=Samsung+Starts+Production+of+512+GB+UFS+NAND+Flash+Memory%3A+64-Layer+V-NAND%2C+860+MB%2Fs+Reads&rft.date=2017-12-05&rft.aulast=Shilov&rft.aufirst=Anton&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F12120%2Fsamsung-starts-production-of-512-gb-ufs-chips&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"> </li> <li id="cite_note-electronicsweekly-samsung-93"><a href="#cite_ref-electronicsweekly-samsung_93-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFManners2019" class="citation news cs1">Manners, David (30 January 2019). <a rel="nofollow" class="external text" href="https://www.electronicsweekly.com/news/business/samsung-makes-1tb-flash-module-2019-01/">"Samsung makes 1TB flash eUFS module"</a>. <a href="/wiki/Electronics_Weekly" title="Electronics Weekly">Electronics Weekly</a>. Retrieved 23 June 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Electronics+Weekly&rft.atitle=Samsung+makes+1TB+flash+eUFS+module&rft.date=2019-01-30&rft.aulast=Manners&rft.aufirst=David&rft_id=https%3A%2F%2Fwww.electronicsweekly.com%2Fnews%2Fbusiness%2Fsamsung-makes-1tb-flash-module-2019-01%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"> </li> <li id="cite_note-anandtech-samsung-2018-94"><a href="#cite_ref-anandtech-samsung-2018_94-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFTallis2018" class="citation news cs1">Tallis, Billy (October 17, 2018). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/13497/samsung-shares-ssd-roadmap-for-qlc-nand-and-96layer-3d-nand">"Samsung Shares SSD Roadmap for QLC NAND And 96-layer 3D NAND"</a>. <a href="/wiki/AnandTech" title="AnandTech">AnandTech</a>. Retrieved 27 June 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=AnandTech&rft.atitle=Samsung+Shares+SSD+Roadmap+for+QLC+NAND+And+96-layer+3D+NAND&rft.date=2018-10-17&rft.aulast=Tallis&rft.aufirst=Billy&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F13497%2Fsamsung-shares-ssd-roadmap-for-qlc-nand-and-96layer-3d-nand&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"> </li> <li id="cite_note-95"><a href="#cite_ref-95">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.engadget.com/2018/12/12/intel-foverus-3d-chip/">"Intel unveils a groundbreaking way to make 3D chips"</a>. Engadget. 8 August 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Engadget&rft.atitle=Intel+unveils+a+groundbreaking+way+to+make+3D+chips&rft.date=2019-08-08&rft_id=https%3A%2F%2Fwww.engadget.com%2F2018%2F12%2F12%2Fintel-foverus-3d-chip%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"> </li> <li id="cite_note-96"><a href="#cite_ref-96">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSmith" class="citation web cs1">Smith, Ryan. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/17509/microns-232-layer-nand-now-shipping">"Micron's 232 Layer NAND Now Shipping: 1Tbit, 6-Plane Dies With 50% More I/O Bandwidth"</a>. www.anandtech.com. Retrieved 2022-08-03.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=Micron%27s+232+Layer+NAND+Now+Shipping%3A+1Tbit%2C+6-Plane+Dies+With+50%25+More+I%2FO+Bandwidth&rft.aulast=Smith&rft.aufirst=Ryan&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F17509%2Fmicrons-232-layer-nand-now-shipping&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=17" title="Edit section: References">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1239549316">.mw-parser-output .refbegin{margin-bottom:0.5em}.mw-parser-output .refbegin-hanging-indents>ul{margin-left:0}.mw-parser-output .refbegin-hanging-indents>ul>li{margin-left:0;padding-left:3.2em;text-indent:-3.2em}.mw-parser-output .refbegin-hanging-indents ul,.mw-parser-output .refbegin-hanging-indents ul li{list-style:none}@media(max-width:720px){.mw-parser-output .refbegin-hanging-indents>ul>li{padding-left:1.6em;text-indent:-1.6em}}.mw-parser-output .refbegin-columns{margin-top:0.3em}.mw-parser-output .refbegin-columns ul{margin-top:0}.mw-parser-output .refbegin-columns li{page-break-inside:avoid;break-inside:avoid-column}@media screen{.mw-parser-output .refbegin{font-size:90%}}</style><div class="refbegin" style=""> <ul><li><a rel="nofollow" class="external text" href="http://pc.watch.impress.co.jp/docs/column/kaigai/20111107_488696.html">JEDECが「DDR4」とTSVを使う「3DS」メモリ技術の概要を明らかに</a> - 後藤弘茂のWeekly海外ニュース Impress Watch Co. (issued:2011-11-08, 2011-11-08)</li> <li><a rel="nofollow" class="external text" href="http://www.oki.com/jp/otr/2007/n211/pdf/211_r17.pdf">貫通電極を用いたチップ積層技術の開発</a> (Japanese) – oki technical review #211 Vol.74 #3 (issued:2007-10, 2011-11-08)</li> <li><a rel="nofollow" class="external text" href="http://www.a-elpida.com/ja/technology/tsv.html">TSV (Through Silicon Via:Si貫通電極)</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120425154900/http://www.a-elpida.com/ja/technology/tsv.html">Archived</a> 2012-04-25 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> (Japanese) – Akita Elpida Memory, inc (2011-11-08)</li></ul> </div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=18" title="Edit section: Further reading">edit</a>]</div> <ul><li>Philip Garrou, Christopher Bower, Peter Ramm: Handbook of 3D Integration, Technology and Applications of 3D Integrated Circuits Vol. 1 and Vol. 2, Wiley-VCH, Weinheim 2008, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-3-527-32034-9" title="Special:BookSources/978-3-527-32034-9">978-3-527-32034-9</a>.</li> <li>Yuan Xie, Jason Cong, Sachin Sapatnekar: Three-Dimensional Integrated Circuit Design: Eda, Design And Microarchitectures, Publisher: Springer, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/1-4419-0783-1" title="Special:BookSources/1-4419-0783-1">1-4419-0783-1</a>, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4419-0783-7" title="Special:BookSources/978-1-4419-0783-7">978-1-4419-0783-7</a>, 978–1441907837, Publishing Date: Dec. 2009.</li> <li>Philip Garrou, Mitsumasa Koyanagi, Peter Ramm: Handbook of 3D Integration, 3D Process Technology Vol. 3, Wiley-VCH, Weinheim 2014, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-3-527-33466-7" title="Special:BookSources/978-3-527-33466-7">978-3-527-33466-7</a>.</li> <li>Paul D. Franzon, Erik Jan Marinissen, Muhannad S. Bakir, Philip Garrou, Mitsumasa Koyanagi, Peter Ramm: Handbook of 3D Integration: "Design, Test, and Thermal Management of 3D Integrated Circuits", Vol. 4, Wiley-VCH, Weinheim 2019, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-3-527-33855-9" title="Special:BookSources/978-3-527-33855-9">978-3-527-33855-9</a>.</li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2>[<a href="/w/index.php?title=Three-dimensional_integrated_circuit&action=edit&section=19" title="Edit section: External links">edit</a>]</div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFEuronymous2007" class="citation web cs1">Euronymous (2007-05-02). <a rel="nofollow" class="external text" href="http://realworldtech.com/page.cfm?ArticleID=RWT050207213241">"3D Integration: A Revolution in Design"</a>. Real World Technologies. Retrieved 2014-05-15.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=3D+Integration%3A+A+Revolution+in+Design&rft.pub=Real+World+Technologies&rft.date=2007-05-02&rft.au=Euronymous&rft_id=http%3A%2F%2Frealworldtech.com%2Fpage.cfm%3FArticleID%3DRWT050207213241&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSemiconductors2006" class="citation web cs1">Semiconductors (2006). <a rel="nofollow" class="external text" href="https://archive.today/20130131192505/http://sst.pennnet.com/Articles/Article_Display.cfm?ARTICLE_ID=254615">"Mapping progress in 3D IC integration"</a>. Solid State Technology. Archived from <a rel="nofollow" class="external text" href="http://sst.pennnet.com/Articles/Article_Display.cfm?ARTICLE_ID=254615">the original</a> on January 31, 2013. Retrieved 2014-05-15.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Mapping+progress+in+3D+IC+integration&rft.pub=Solid+State+Technology&rft.date=2006&rft.au=Semiconductors&rft_id=http%3A%2F%2Fsst.pennnet.com%2FArticles%2FArticle_Display.cfm%3FARTICLE_ID%3D254615&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFPeter_Ramm2010" class="citation book cs1">Peter Ramm; et al. (2010-09-16). "3D Integration technology: Status and application development". 2010 Proceedings of ESSCIRC. IEEE. pp. 9–16. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FESSCIRC.2010.5619857">10.1109/ESSCIRC.2010.5619857</a>. <a href="/wiki/Hdl_(identifier)" class="mw-redirect" title="Hdl (identifier)">hdl</a>:<a rel="nofollow" class="external text" href="https://hdl.handle.net/11250%2F2463188">11250/2463188</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4244-6664-1" title="Special:BookSources/978-1-4244-6664-1"><bdi>978-1-4244-6664-1</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:1239311">1239311</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=3D+Integration+technology%3A+Status+and+application+development&rft.btitle=2010+Proceedings+of+ESSCIRC&rft.pages=9-16&rft.pub=IEEE&rft.date=2010-09-16&rft_id=info%3Ahdl%2F11250%2F2463188&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A1239311%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FESSCIRC.2010.5619857&rft.isbn=978-1-4244-6664-1&rft.au=Peter+Ramm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMingjie_LinAbbas_El_GamalYi-chang_LuSimon_Wong2006" class="citation book cs1">Mingjie Lin; Abbas El Gamal; Yi-chang Lu & Simon Wong (2006-02-22). "Performance benefits of monolithically stacked 3D-FPGA". Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays. Vol. 26. p. 113. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F1117201.1117219">10.1145/1117201.1117219</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/1595932925" title="Special:BookSources/1595932925"><bdi>1595932925</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:7818893">7818893</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Performance+benefits+of+monolithically+stacked+3D-FPGA&rft.btitle=Proceedings+of+the+2006+ACM%2FSIGDA+14th+international+symposium+on+Field+programmable+gate+arrays&rft.pages=113&rft.date=2006-02-22&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A7818893%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1145%2F1117201.1117219&rft.isbn=1595932925&rft.au=Mingjie+Lin&rft.au=Abbas+El+Gamal&rft.au=Yi-chang+Lu&rft.au=Simon+Wong&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.amkor.com/index.cfm?objectid=437C1C10-5056-AA0A-E2626E3C762307FF">"Joint Project for Mechanical Qualification of Next Generation High Density Package-on-Package (PoP) with Through Mold Via Technology"</a>. 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Journal of Microsystem Technologies. 16 (7): 1051–1055. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2010MiTec..16.1051R">2010MiTec..16.1051R</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1007%2Fs00542-009-0976-1">10.1007/s00542-009-0976-1</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:55824967">55824967</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Journal+of+Microsystem+Technologies&rft.atitle=3D+System-on-Chip+Technologies+for+More+than+Moore+Systems&rft.volume=16&rft.issue=7&rft.pages=1051-1055&rft.date=2010&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A55824967%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1007%2Fs00542-009-0976-1&rft_id=info%3Abibcode%2F2010MiTec..16.1051R&rft.au=Peter+Ramm&rft.au=Armin+Klumpp&rft.au=Josef+Weber&rft.au=Maaike+Taklo&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFPhilip_Garrou,_James_LuPeter_Ramm2012" class="citation book cs1">Philip Garrou, James Lu & Peter Ramm (2012). <a rel="nofollow" class="external text" href="http://www.wiley-vch.de/publish/dt/books/newTitles201201/3-527-32646-4/?sID=p2qlnooj68su7htl8qrrc2qjt3">"Chapter 15"</a>. Three-Dimensional Integration. Wiley-VCH. Retrieved 2014-05-15.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Chapter+15&rft.btitle=Three-Dimensional+Integration&rft.pub=Wiley-VCH&rft.date=2012&rft.au=Philip+Garrou%2C+James+Lu&rft.au=Peter+Ramm&rft_id=http%3A%2F%2Fwww.wiley-vch.de%2Fpublish%2Fdt%2Fbooks%2FnewTitles201201%2F3-527-32646-4%2F%3FsID%3Dp2qlnooj68su7htl8qrrc2qjt3&rfr_id=info%3Asid%2Fen.wikipedia.org%3AThree-dimensional+integrated+circuit" class="Z3988"> <code class="cs1-code">{{<a href="/wiki/Template:Cite_book" title="Template:Cite book">cite book</a>}}</code>: <code class="cs1-code">|work=</code> ignored (<a href="/wiki/Help:CS1_errors#periodical_ignored" title="Help:CS1 errors">help</a>)</li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist 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style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%;text-align: center;"><div style="display: inline-block; line-height: 1.2em; padding: .1em 0;"><a href="/wiki/Information_and_communications_technology" title="Information and communications technology">Information and communications</a></div></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Ambient_intelligence" title="Ambient intelligence">Ambient intelligence</a> <ul><li><a href="/wiki/Internet_of_things" title="Internet of things">Internet of things</a></li></ul></li> <li><a href="/wiki/Artificial_intelligence" title="Artificial intelligence">Artificial intelligence</a> <ul><li><a href="/wiki/Applications_of_artificial_intelligence" title="Applications of artificial intelligence">Applications of artificial intelligence</a></li> <li><a href="/wiki/Machine_translation" title="Machine translation">Machine translation</a></li> <li><a href="/wiki/Machine_vision" title="Machine vision">Machine vision</a></li> <li><a href="/wiki/Mobile_translation" title="Mobile translation">Mobile translation</a></li> <li><a href="/wiki/Progress_in_artificial_intelligence" title="Progress in artificial intelligence">Progress in artificial intelligence</a></li> <li><a href="/wiki/Semantic_Web" title="Semantic Web">Semantic Web</a></li> <li><a href="/wiki/Speech_recognition" title="Speech recognition">Speech recognition</a></li></ul></li> <li><a href="/wiki/Atomtronics" title="Atomtronics">Atomtronics</a></li> <li><a href="/wiki/Carbon_nanotube_field-effect_transistor" title="Carbon nanotube field-effect transistor">Carbon nanotube field-effect transistor</a></li> <li><a href="/wiki/Cybermethodology" title="Cybermethodology">Cybermethodology</a></li> <li><a href="/wiki/Extended_reality" title="Extended reality">Extended reality</a></li> <li><a href="/wiki/Optical_disc#Fourth-generation" title="Optical disc">Fourth-generation optical discs</a> <ul><li><a href="/wiki/3D_optical_data_storage" title="3D optical data storage">3D optical data storage</a></li> <li><a href="/wiki/Holographic_data_storage" title="Holographic data storage">Holographic data storage</a></li></ul></li> <li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li> <li>Memory <ul><li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">CBRAM</a></li> <li><a href="/wiki/Electrochemical_RAM" title="Electrochemical RAM">ECRAM</a></li> <li><a href="/wiki/Ferroelectric_RAM" title="Ferroelectric RAM">FRAM</a></li> <li><a href="/wiki/Millipede_memory" title="Millipede memory">Millipede</a></li> <li><a href="/wiki/Magnetoresistive_RAM" title="Magnetoresistive RAM">MRAM</a></li> <li><a href="/wiki/Nano-RAM" title="Nano-RAM">NRAM</a></li> <li><a href="/wiki/Phase-change_memory" title="Phase-change memory">PRAM</a></li> <li><a href="/wiki/Racetrack_memory" title="Racetrack memory">Racetrack memory</a></li> <li><a href="/wiki/Resistive_random-access_memory" title="Resistive random-access memory">RRAM</a></li> <li><a href="/wiki/SONOS" title="SONOS">SONOS</a></li> <li><a href="/wiki/UltraRAM" title="UltraRAM">UltraRAM</a></li></ul></li> <li><a href="/wiki/Optical_computing" title="Optical computing">Optical computing</a></li> <li><a href="/wiki/Radio-frequency_identification" title="Radio-frequency identification">RFID</a> <ul><li><a href="/wiki/Chipless_RFID" title="Chipless RFID">Chipless RFID</a></li></ul></li> <li><a href="/wiki/Software-defined_radio" title="Software-defined radio">Software-defined radio</a></li> <li><a class="mw-selflink selflink">Three-dimensional integrated circuit</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="text-align: center;;width:1%">Topics</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Automation" title="Automation">Automation</a></li> <li><a href="/wiki/Collingridge_dilemma" title="Collingridge dilemma">Collingridge dilemma</a></li> <li><a href="/wiki/Differential_technological_development" title="Differential technological development">Differential technological development</a></li> <li><a href="/wiki/Disruptive_innovation" title="Disruptive innovation">Disruptive innovation</a></li> <li><a href="/wiki/Ephemeralization" title="Ephemeralization">Ephemeralization</a></li> <li><a href="/wiki/Ethics_of_technology" title="Ethics of technology">Ethics</a> <ul><li><a href="/wiki/Bioethics" title="Bioethics">Bioethics</a></li> <li><a href="/wiki/Cyberethics" title="Cyberethics">Cyberethics</a></li> <li><a href="/wiki/Neuroethics" title="Neuroethics">Neuroethics</a></li> <li><a href="/wiki/Robot_ethics" title="Robot ethics">Robot ethics</a></li></ul></li> <li><a href="/wiki/Exploratory_engineering" title="Exploratory engineering">Exploratory engineering</a></li> <li><a href="/wiki/Proactionary_principle" title="Proactionary principle">Proactionary principle</a></li> <li><a href="/wiki/Technological_change" title="Technological change">Technological change</a> <ul><li><a href="/wiki/Technological_unemployment" title="Technological unemployment">Technological unemployment</a></li></ul></li> <li><a href="/wiki/Technological_convergence" title="Technological convergence">Technological convergence</a></li> <li><a href="/wiki/Technological_evolution" title="Technological evolution">Technological evolution</a></li> <li><a href="/wiki/Technological_paradigm" title="Technological paradigm">Technological paradigm</a></li> <li><a href="/wiki/Technology_forecasting" title="Technology forecasting">Technology forecasting</a> <ul><li><a href="/wiki/Accelerating_change" title="Accelerating change">Accelerating change</a></li> <li><a href="/wiki/Future-oriented_technology_analysis" title="Future-oriented technology analysis">Future-oriented technology analysis</a></li> <li><a href="/wiki/Horizon_scanning" title="Horizon scanning">Horizon scanning</a></li> <li><a href="/wiki/Moore%27s_law" title="Moore's law">Moore's law</a></li> <li><a href="/wiki/Technological_singularity" title="Technological singularity">Technological singularity</a></li> <li><a href="/wiki/Technology_scouting" title="Technology scouting">Technology scouting</a></li></ul></li> <li><a href="/wiki/Technology_in_science_fiction" title="Technology in science fiction">Technology in science fiction</a></li> <li><a href="/wiki/Technology_readiness_level" title="Technology readiness level">Technology readiness level</a></li> <li><a href="/wiki/Technology_roadmap" title="Technology roadmap">Technology roadmap</a></li> <li><a href="/wiki/Transhumanism" title="Transhumanism">Transhumanism</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2" style="text-align: center;"><div> <ul><li><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/d/db/Symbol_list_class.svg/16px-Symbol_list_class.svg.png" decoding="async" width="16" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/d/db/Symbol_list_class.svg/23px-Symbol_list_class.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/d/db/Symbol_list_class.svg/31px-Symbol_list_class.svg.png 2x" data-file-width="180" data-file-height="185" /> <a href="/wiki/List_of_emerging_technologies" title="List of emerging technologies">List</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Digital_electronics" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Digital_electronics" title="Template:Digital electronics"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Digital_electronics" title="Template talk:Digital electronics"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Digital_electronics" title="Special:EditPage/Template:Digital electronics"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Digital_electronics" style="font-size:114%;margin:0 4em"><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor" title="Transistor">Transistor</a></li> <li><a href="/wiki/Resistor" title="Resistor">Resistor</a></li> <li><a href="/wiki/Inductor" title="Inductor">Inductor</a></li> <li><a href="/wiki/Capacitor" title="Capacitor">Capacitor</a></li> <li><a href="/wiki/Printed_electronics" title="Printed electronics">Printed electronics</a></li> <li><a href="/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li> <li><a href="/wiki/Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li> <li><a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">Flip-flop</a></li> <li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational logic</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential logic</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li> <li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li> <li><a href="/wiki/Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li> <li><a class="mw-selflink selflink">Three-dimensional integrated circuit</a> (3D IC)</li> <li><a href="/wiki/Emitter-coupled_logic" title="Emitter-coupled logic">Emitter-coupled logic</a> (ECL)</li> <li><a href="/wiki/Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li> <li><a href="/wiki/Macrocell_array" title="Macrocell array">Macrocell array</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li> <li><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li> <li><a href="/wiki/Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Digital_signal" title="Digital signal">Digital signal</a></li> <li><a href="/wiki/Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li> <li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li> <li><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></li> <li><a href="/wiki/Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a> <ul><li><a href="/wiki/Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li> <li><a href="/wiki/Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li> <li><a href="/wiki/Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li> <li><a href="/wiki/Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Place_and_route" title="Place and route">Place and route</a> <ul><li><a href="/wiki/Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li> <li><a href="/wiki/Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li> <li><a href="/wiki/Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li> <li><a href="/wiki/Register-transfer_level" title="Register-transfer level">Register-transfer level</a> <ul><li><a href="/wiki/Hardware_description_language" title="Hardware description language">Hardware description language</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li> <li><a href="/wiki/Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li> <li><a href="/wiki/Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li> <li><a href="/wiki/Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_hardware" title="Computer hardware">Computer hardware</a> <ul><li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul></li> <li><a href="/wiki/Digital_audio" title="Digital audio">Digital audio</a> <ul><li><a href="/wiki/Digital_radio" title="Digital radio">radio</a></li></ul></li> <li><a href="/wiki/Digital_photography" title="Digital photography">Digital photography</a></li> <li><a href="/wiki/Telephony#Digital_telephony" title="Telephony">Digital telephone</a></li> <li><a href="/wiki/Digital_video" title="Digital video">Digital video</a> <ul><li><a href="/wiki/Digital_cinematography" title="Digital cinematography">cinematography</a></li> <li><a href="/wiki/Digital_television" title="Digital television">television</a></li></ul></li> <li><a href="/wiki/Electronic_literature" title="Electronic literature">Electronic literature</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Design issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Metastability_(electronics)" title="Metastability (electronics)">Metastability</a></li> <li><a href="/wiki/Runt_pulse" title="Runt pulse">Runt pulse</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Electronic_components" style="padding:3px"><table class="nowraplinks mw-collapsible mw-collapsed navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li 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0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/MOSFET" title="MOSFET">MOS transistors</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor" title="Transistor">Transistor</a></li> <li><a href="/wiki/NMOS_logic" title="NMOS logic">NMOS</a></li> <li><a href="/wiki/PMOS_logic" title="PMOS logic">PMOS</a></li> <li><a href="/wiki/BiCMOS" title="BiCMOS">BiCMOS</a></li> <li><a href="/wiki/Bio-FET" title="Bio-FET">BioFET</a></li> <li><a href="/wiki/Chemical_field-effect_transistor" title="Chemical field-effect transistor">Chemical field-effect transistor</a> (ChemFET)</li> <li><a href="/wiki/CMOS" title="CMOS">Complementary MOS</a> (CMOS)</li> <li><a href="/wiki/Depletion-load_NMOS_logic" title="Depletion-load NMOS logic">Depletion-load NMOS</a></li> <li><a href="/wiki/FinFET" class="mw-redirect" title="FinFET">Fin field-effect transistor</a> (FinFET)</li> <li><a href="/wiki/Floating-gate_MOSFET" title="Floating-gate MOSFET">Floating-gate MOSFET</a> (FGMOS)</li> <li><a href="/wiki/Insulated-gate_bipolar_transistor" title="Insulated-gate bipolar transistor">Insulated-gate bipolar transistor</a> (IGBT)</li> <li><a href="/wiki/ISFET" title="ISFET">ISFET</a></li> <li><a href="/wiki/LDMOS" title="LDMOS">LDMOS</a></li> <li><a href="/wiki/MOSFET" title="MOSFET">MOS field-effect transistor</a> (MOSFET)</li> <li><a href="/wiki/Multigate_device" title="Multigate device">Multi-gate field-effect transistor</a> (MuGFET)</li> <li><a href="/wiki/Power_MOSFET" title="Power MOSFET">Power MOSFET</a></li> <li><a href="/wiki/Thin-film_transistor" title="Thin-film transistor">Thin-film transistor</a> (TFT)</li> <li><a href="/wiki/VMOS" title="VMOS">VMOS</a></li> <li><a href="/wiki/Power_MOSFET#UMOS" title="Power MOSFET">UMOS</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Transistor" title="Transistor">Other transistors</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bipolar_junction_transistor" title="Bipolar junction transistor">Bipolar junction transistor</a> (BJT)</li> <li><a href="/wiki/Darlington_transistor" title="Darlington transistor">Darlington transistor</a></li> <li><a href="/wiki/Diffused_junction_transistor" title="Diffused junction transistor">Diffused junction transistor</a></li> <li><a href="/wiki/Field-effect_transistor" title="Field-effect transistor">Field-effect transistor</a> (FET) <ul><li><a href="/wiki/JFET" title="JFET">Junction Gate FET (JFET)</a></li> <li><a href="/wiki/Organic_field-effect_transistor" title="Organic field-effect transistor">Organic FET (OFET)</a></li></ul></li> <li><a href="/wiki/Light-emitting_transistor" title="Light-emitting transistor">Light-emitting transistor</a> (LET) <ul><li><a href="/wiki/Organic_light-emitting_transistor" title="Organic light-emitting transistor">Organic LET (OLET)</a></li></ul></li> <li><a href="/wiki/Pentode_transistor" title="Pentode transistor">Pentode transistor</a></li> <li><a href="/wiki/Point-contact_transistor" title="Point-contact transistor">Point-contact transistor</a></li> <li><a href="/wiki/Programmable_unijunction_transistor" title="Programmable unijunction transistor">Programmable unijunction transistor</a> (PUT)</li> <li><a href="/wiki/Static_induction_transistor" title="Static induction transistor">Static induction transistor</a> (SIT)</li> <li><a href="/wiki/Tetrode_transistor" title="Tetrode transistor">Tetrode transistor</a></li> <li><a href="/wiki/Unijunction_transistor" title="Unijunction transistor">Unijunction transistor</a> (UJT)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Diode" title="Diode">Diodes</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Avalanche_diode" title="Avalanche diode">Avalanche diode</a></li> <li><a href="/wiki/Constant-current_diode" title="Constant-current diode">Constant-current diode</a> (CLD, CRD)</li> <li><a href="/wiki/Gunn_diode" title="Gunn diode">Gunn diode</a></li> <li><a href="/wiki/Laser_diode" title="Laser diode">Laser diode</a> (LD)</li> <li><a href="/wiki/Light-emitting_diode" title="Light-emitting diode">Light-emitting diode</a> (LED)</li> <li><a href="/wiki/OLED" title="OLED">Organic light-emitting diode</a> (OLED)</li> <li><a href="/wiki/Photodiode" title="Photodiode">Photodiode</a></li> <li><a href="/wiki/PIN_diode" title="PIN diode">PIN diode</a></li> <li><a href="/wiki/Schottky_diode" title="Schottky diode">Schottky diode</a></li> <li><a href="/wiki/Step_recovery_diode" title="Step recovery diode">Step recovery diode</a></li> <li><a href="/wiki/Zener_diode" title="Zener diode">Zener diode</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other devices</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Printed_electronics" title="Printed electronics">Printed electronics</a></li> <li><a href="/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li> <li><a href="/wiki/DIAC" title="DIAC">DIAC</a></li> <li><a href="/wiki/Heterostructure_barrier_varactor" title="Heterostructure barrier varactor">Heterostructure barrier varactor</a></li> <li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li> <li><a href="/wiki/Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a></li> <li><a href="/wiki/Light_emitting_capacitor" class="mw-redirect" title="Light emitting capacitor">Light emitting capacitor</a> (LEC)</li> <li><a href="/wiki/Memistor" title="Memistor">Memistor</a></li> <li><a href="/wiki/Memristor" title="Memristor">Memristor</a></li> <li><a href="/wiki/Memtransistor" title="Memtransistor">Memtransistor</a></li> <li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Metal-oxide_varistor" class="mw-redirect" title="Metal-oxide varistor">Metal-oxide varistor</a> (MOV)</li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li> <li><a href="/wiki/MOS_integrated_circuit" class="mw-redirect" title="MOS integrated circuit">MOS integrated circuit</a> (MOS IC)</li> <li><a href="/wiki/Organic_semiconductor" title="Organic semiconductor">Organic semiconductor</a></li> <li><a href="/wiki/Photodetector" title="Photodetector">Photodetector</a></li> <li><a href="/wiki/Quantum_circuit" title="Quantum circuit">Quantum circuit</a></li> <li><a href="/wiki/RF_CMOS" title="RF CMOS">RF CMOS</a></li> <li><a href="/wiki/Silicon_controlled_rectifier" title="Silicon controlled rectifier">Silicon controlled rectifier</a> (SCR)</li> <li><a href="/wiki/Solaristor" title="Solaristor">Solaristor</a></li> <li><a href="/wiki/Static_induction_thyristor" title="Static induction thyristor">Static induction thyristor</a> (SITh)</li> <li><a class="mw-selflink selflink">Three-dimensional integrated circuit</a> (3D IC)</li> <li><a href="/wiki/Thyristor" title="Thyristor">Thyristor</a></li> <li><a href="/wiki/Trancitor" title="Trancitor">Trancitor</a></li> <li><a href="/wiki/TRIAC" title="TRIAC">TRIAC</a></li> <li><a href="/wiki/Varicap" title="Varicap">Varicap</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Voltage_regulator" title="Voltage regulator">Voltage regulators</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Linear_regulator" title="Linear regulator">Linear regulator</a></li> <li><a href="/wiki/Low-dropout_regulator" title="Low-dropout regulator">Low-dropout regulator</a></li> <li><a href="/wiki/Switching_regulator" class="mw-redirect" title="Switching regulator">Switching regulator</a></li> <li><a href="/wiki/Buck_converter" title="Buck converter">Buck</a></li> <li><a href="/wiki/Boost_converter" title="Boost converter">Boost</a></li> <li><a href="/wiki/Buck%E2%80%93boost_converter" title="Buck–boost converter">Buck–boost</a></li> <li><a href="/wiki/Split-pi_topology" title="Split-pi topology">Split-pi</a></li> <li><a href="/wiki/%C4%86uk_converter" title="Ćuk converter">Ćuk</a></li> <li><a href="/wiki/Single-ended_primary-inductor_converter" title="Single-ended primary-inductor converter">SEPIC</a></li> <li><a href="/wiki/Charge_pump" title="Charge pump">Charge pump</a></li> <li><a href="/wiki/Switched_capacitor" title="Switched capacitor">Switched capacitor</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Vacuum_tube" title="Vacuum tube">Vacuum tubes</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Acorn_tube" title="Acorn tube">Acorn tube</a></li> <li><a href="/wiki/Audion" title="Audion">Audion</a></li> <li><a href="/wiki/Beam_tetrode" title="Beam tetrode">Beam tetrode</a></li> <li><a href="/wiki/Hot-wire_barretter" title="Hot-wire barretter">Barretter</a></li> <li><a href="/wiki/Compactron" title="Compactron">Compactron</a></li> <li><a href="/wiki/Vacuum_diode" class="mw-redirect" title="Vacuum diode">Diode</a></li> <li><a href="/wiki/Fleming_valve" title="Fleming valve">Fleming valve</a></li> <li><a href="/wiki/Neutron_generator" title="Neutron generator">Neutron tube</a></li> <li><a href="/wiki/Nonode" title="Nonode">Nonode</a></li> <li><a href="/wiki/Nuvistor" title="Nuvistor">Nuvistor</a></li> <li><a href="/wiki/Pentagrid_converter" title="Pentagrid converter">Pentagrid</a> (Hexode, Heptode, Octode)</li> <li><a href="/wiki/Pentode" title="Pentode">Pentode</a></li> <li><a href="/wiki/Photomultiplier_tube" title="Photomultiplier tube">Photomultiplier</a></li> <li><a href="/wiki/Phototube" title="Phototube">Phototube</a></li> <li><a href="/wiki/Tetrode" title="Tetrode">Tetrode</a></li> <li><a href="/wiki/Triode" title="Triode">Triode</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Vacuum_tube" title="Vacuum tube">Vacuum tubes</a> (<a href="/wiki/Electromagnetic_radiation" title="Electromagnetic radiation">RF</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Backward-wave_oscillator" title="Backward-wave oscillator">Backward-wave oscillator</a> (BWO)</li> <li><a href="/wiki/Cavity_magnetron" title="Cavity magnetron">Cavity magnetron</a></li> <li><a href="/wiki/Crossed-field_amplifier" title="Crossed-field amplifier">Crossed-field amplifier</a> (CFA)</li> <li><a href="/wiki/Gyrotron" title="Gyrotron">Gyrotron</a></li> <li><a href="/wiki/Inductive_output_tube" title="Inductive output tube">Inductive output tube</a> (IOT)</li> <li><a href="/wiki/Klystron" title="Klystron">Klystron</a></li> <li><a href="/wiki/Maser" title="Maser">Maser</a></li> <li><a href="/wiki/Sutton_tube" title="Sutton tube">Sutton tube</a></li> <li><a href="/wiki/Traveling-wave_tube" title="Traveling-wave tube">Traveling-wave tube</a> (TWT)</li> <li><a href="/wiki/X-ray_tube" title="X-ray tube">X-ray tube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Cathode-ray_tube" title="Cathode-ray tube">Cathode-ray tubes</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Beam_deflection_tube" title="Beam deflection tube">Beam deflection tube</a></li> <li><a href="/wiki/Charactron" title="Charactron">Charactron</a></li> <li><a href="/wiki/Iconoscope" title="Iconoscope">Iconoscope</a></li> <li><a href="/wiki/Magic_eye_tube" title="Magic eye tube">Magic eye tube</a></li> <li><a href="/wiki/Monoscope" title="Monoscope">Monoscope</a></li> <li><a href="/wiki/Selectron_tube" title="Selectron tube">Selectron tube</a></li> <li><a href="/wiki/Storage_tube" title="Storage tube">Storage tube</a></li> <li><a href="/wiki/Trochotron" class="mw-redirect" title="Trochotron">Trochotron</a></li> <li><a href="/wiki/Video_camera_tube" title="Video camera tube">Video camera tube</a></li> <li><a href="/wiki/Williams_tube" title="Williams tube">Williams tube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Gas-filled_tube" title="Gas-filled tube">Gas-filled tubes</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Cold_cathode" title="Cold cathode">Cold cathode</a></li> <li><a href="/wiki/Crossatron" title="Crossatron">Crossatron</a></li> <li><a href="/wiki/Dekatron" title="Dekatron">Dekatron</a></li> <li><a href="/wiki/Ignitron" title="Ignitron">Ignitron</a></li> <li><a href="/wiki/Krytron" title="Krytron">Krytron</a></li> <li><a href="/wiki/Mercury-arc_valve" title="Mercury-arc valve">Mercury-arc valve</a></li> <li><a href="/wiki/Neon_lamp" title="Neon lamp">Neon lamp</a></li> <li><a href="/wiki/Nixie_tube" title="Nixie tube">Nixie tube</a></li> <li><a href="/wiki/Thyratron" title="Thyratron">Thyratron</a></li> <li><a href="/wiki/Trigatron" title="Trigatron">Trigatron</a></li> <li><a href="/wiki/Voltage-regulator_tube" title="Voltage-regulator tube">Voltage-regulator tube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Adjustable</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Potentiometer" title="Potentiometer">Potentiometer</a> <ul><li><a href="/wiki/Digital_potentiometer" title="Digital potentiometer">digital</a></li></ul></li> <li><a href="/wiki/Variable_capacitor" title="Variable capacitor">Variable capacitor</a></li> <li><a href="/wiki/Varicap" title="Varicap">Varicap</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Passive</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Connector <ul><li><a href="/wiki/Audio_and_video_interfaces_and_connectors" title="Audio and video interfaces and connectors">audio and video</a></li> <li><a href="/wiki/AC_power_plugs_and_sockets" title="AC power plugs and sockets">electrical power</a></li> <li><a href="/wiki/RF_connector" title="RF connector">RF</a></li></ul></li> <li><a href="/wiki/Electrolytic_detector" title="Electrolytic detector">Electrolytic detector</a></li> <li><a href="/wiki/Ferrite_core" title="Ferrite core">Ferrite</a></li> <li><a href="/wiki/Antifuse" title="Antifuse">Antifuse</a></li> <li><a href="/wiki/Fuse_(electrical)" title="Fuse (electrical)">Fuse</a> <ul><li><a href="/wiki/Resettable_fuse" title="Resettable fuse">resettable</a></li> <li><a href="/wiki/EFUSE" class="mw-redirect" title="EFUSE">eFUSE</a></li></ul></li> <li><a href="/wiki/Resistor" title="Resistor">Resistor</a></li> <li><a href="/wiki/Switch" title="Switch">Switch</a></li> <li><a href="/wiki/Thermistor" title="Thermistor">Thermistor</a></li> <li><a href="/wiki/Transformer" title="Transformer">Transformer</a></li> <li><a href="/wiki/Varistor" title="Varistor">Varistor</a></li> <li><a href="/wiki/Wire" title="Wire">Wire</a> <ul><li><a href="/wiki/Wollaston_wire" title="Wollaston wire">Wollaston wire</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electrical_reactance" title="Electrical reactance">Reactive</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Capacitor" title="Capacitor">Capacitor</a> <ul><li><a href="/wiki/Capacitor_types" title="Capacitor types">types</a></li></ul></li> <li><a href="/wiki/Ceramic_resonator" title="Ceramic resonator">Ceramic resonator</a></li> <li><a href="/wiki/Crystal_oscillator" title="Crystal oscillator">Crystal oscillator</a></li> <li><a href="/wiki/Inductor" title="Inductor">Inductor</a></li> <li><a href="/wiki/Parametron" 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