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<div class="vector-toc-text"> <span class="vector-toc-numb">1.1.1</span> <span>Ventajas</span> </div> </a> <ul id="toc-Ventajas-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Desventajas" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Desventajas"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.2</span> <span>Desventajas</span> </div> </a> <ul id="toc-Desventajas-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Historia" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Historia"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Historia</span> </div> </a> <button aria-controls="toc-Historia-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Alternar subsección Historia</span> </button> <ul id="toc-Historia-sublist" class="vector-toc-list"> <li id="toc-Desarrollo" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Desarrollo"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Desarrollo</span> </div> </a> <ul id="toc-Desarrollo-sublist" class="vector-toc-list"> <li id="toc-2005" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#2005"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.1</span> <span>2005</span> </div> </a> <ul id="toc-2005-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Lanzamiento" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Lanzamiento"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>Lanzamiento</span> </div> </a> <ul id="toc-Lanzamiento-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Predecesor" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Predecesor"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Predecesor</span> </div> </a> <ul id="toc-Predecesor-sublist" class="vector-toc-list"> <li id="toc-DDR2_SDRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#DDR2_SDRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.1</span> <span>DDR2 SDRAM</span> </div> </a> <ul id="toc-DDR2_SDRAM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Sucesor" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Sucesor"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>Sucesor</span> </div> </a> <ul id="toc-Sucesor-sublist" class="vector-toc-list"> <li id="toc-DDR4_SDRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#DDR4_SDRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.1</span> <span>DDR4 SDRAM</span> </div> </a> <ul id="toc-DDR4_SDRAM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Visión_detallada" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Visión_detallada"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Visión detallada</span> </div> </a> <button aria-controls="toc-Visión_detallada-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Alternar subsección Visión detallada</span> </button> <ul id="toc-Visión_detallada-sublist" class="vector-toc-list"> <li id="toc-Estándares" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Estándares"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Estándares</span> </div> </a> <ul id="toc-Estándares-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Tecnologías_relacionadas" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Tecnologías_relacionadas"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Tecnologías relacionadas</span> </div> </a> <button aria-controls="toc-Tecnologías_relacionadas-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Alternar subsección Tecnologías relacionadas</span> </button> <ul id="toc-Tecnologías_relacionadas-sublist" class="vector-toc-list"> <li id="toc-GDDR3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#GDDR3"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1</span> <span>GDDR3</span> </div> </a> <ul id="toc-GDDR3-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-DDR3L" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#DDR3L"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.2</span> <span>DDR3L</span> </div> </a> <ul id="toc-DDR3L-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Véase_también" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Véase_también"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Véase también</span> </div> </a> <ul id="toc-Véase_también-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Referencias" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Referencias"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Referencias</span> </div> </a> <ul id="toc-Referencias-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contenidos" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" title="Tabla de contenidos" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Cambiar a la tabla de contenidos" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Cambiar a la tabla de contenidos</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">DDR3 SDRAM</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Ir a un artículo en otro idioma. Disponible en 27 idiomas" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-27" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">27 idiomas</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%AF%D9%8A_%D8%AF%D9%8A_%D8%A2%D8%B1_3_%D8%A5%D8%B3_%D8%AF%D9%8A_%D8%B1%D8%A7%D9%85" title="دي دي آر 3 إس دي رام – árabe" lang="ar" hreflang="ar" data-title="دي دي آر 3 إس دي رام" data-language-autonym="العربية" data-language-local-name="árabe" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – catalán" lang="ca" hreflang="ca" data-title="DDR3 SDRAM" data-language-autonym="Català" data-language-local-name="catalán" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – checo" lang="cs" hreflang="cs" data-title="DDR3 SDRAM" data-language-autonym="Čeština" data-language-local-name="checo" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de badge-Q70894304 mw-list-item" title=""><a href="https://de.wikipedia.org/wiki/DDR3-SDRAM" title="DDR3-SDRAM – alemán" lang="de" hreflang="de" data-title="DDR3-SDRAM" data-language-autonym="Deutsch" data-language-local-name="alemán" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-en mw-list-item"><a href="https://en.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – inglés" lang="en" hreflang="en" data-title="DDR3 SDRAM" data-language-autonym="English" data-language-local-name="inglés" class="interlanguage-link-target"><span>English</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – estonio" lang="et" hreflang="et" data-title="DDR3 SDRAM" data-language-autonym="Eesti" data-language-local-name="estonio" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – francés" lang="fr" hreflang="fr" data-title="DDR3 SDRAM" data-language-autonym="Français" data-language-local-name="francés" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – indonesio" lang="id" hreflang="id" data-title="DDR3 SDRAM" data-language-autonym="Bahasa Indonesia" data-language-local-name="indonesio" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/DDR3" title="DDR3 – italiano" lang="it" hreflang="it" data-title="DDR3" data-language-autonym="Italiano" data-language-local-name="italiano" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – japonés" lang="ja" hreflang="ja" data-title="DDR3 SDRAM" data-language-autonym="日本語" data-language-local-name="japonés" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – coreano" lang="ko" hreflang="ko" data-title="DDR3 SDRAM" data-language-autonym="한국어" data-language-local-name="coreano" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-lt mw-list-item"><a href="https://lt.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – lituano" lang="lt" hreflang="lt" data-title="DDR3 SDRAM" data-language-autonym="Lietuvių" data-language-local-name="lituano" class="interlanguage-link-target"><span>Lietuvių</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%A1%E0%B4%BF%E0%B4%A1%E0%B4%BF%E0%B4%86%E0%B5%BC_3_%E0%B4%8E%E0%B4%B8%E0%B5%8D%E0%B4%A1%E0%B4%BF%E0%B4%B1%E0%B4%BE%E0%B4%82" title="ഡിഡിആർ 3 എസ്ഡിറാം – malayálam" lang="ml" hreflang="ml" data-title="ഡിഡിആർ 3 എസ്ഡിറാം" data-language-autonym="മലയാളം" data-language-local-name="malayálam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-ms mw-list-item"><a href="https://ms.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – malayo" lang="ms" hreflang="ms" data-title="DDR3 SDRAM" data-language-autonym="Bahasa Melayu" data-language-local-name="malayo" class="interlanguage-link-target"><span>Bahasa Melayu</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – noruego bokmal" lang="nb" hreflang="nb" data-title="DDR3 SDRAM" data-language-autonym="Norsk bokmål" data-language-local-name="noruego bokmal" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/DDR3" title="DDR3 – polaco" lang="pl" hreflang="pl" data-title="DDR3" data-language-autonym="Polski" data-language-local-name="polaco" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – portugués" lang="pt" hreflang="pt" data-title="DDR3 SDRAM" data-language-autonym="Português" data-language-local-name="portugués" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – ruso" lang="ru" hreflang="ru" data-title="DDR3 SDRAM" data-language-autonym="Русский" data-language-local-name="ruso" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – eslovaco" lang="sk" hreflang="sk" data-title="DDR3 SDRAM" data-language-autonym="Slovenčina" data-language-local-name="eslovaco" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – serbio" lang="sr" hreflang="sr" data-title="DDR3 SDRAM" data-language-autonym="Српски / srpski" data-language-local-name="serbio" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – sueco" lang="sv" hreflang="sv" data-title="DDR3 SDRAM" data-language-autonym="Svenska" data-language-local-name="sueco" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – tailandés" lang="th" hreflang="th" data-title="DDR3 SDRAM" data-language-autonym="ไทย" data-language-local-name="tailandés" class="interlanguage-link-target"><span>ไทย</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – turco" lang="tr" hreflang="tr" data-title="DDR3 SDRAM" data-language-autonym="Türkçe" data-language-local-name="turco" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – ucraniano" lang="uk" hreflang="uk" data-title="DDR3 SDRAM" data-language-autonym="Українська" data-language-local-name="ucraniano" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-uz mw-list-item"><a href="https://uz.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – uzbeko" lang="uz" hreflang="uz" data-title="DDR3 SDRAM" data-language-autonym="Oʻzbekcha / ўзбекча" data-language-local-name="uzbeko" class="interlanguage-link-target"><span>Oʻzbekcha / ўзбекча</span></a></li><li class="interlanguage-link interwiki-wuu mw-list-item"><a href="https://wuu.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – chino wu" lang="wuu" hreflang="wuu" data-title="DDR3 SDRAM" data-language-autonym="吴语" data-language-local-name="chino wu" class="interlanguage-link-target"><span>吴语</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/DDR3_SDRAM" title="DDR3 SDRAM – chino" lang="zh" hreflang="zh" data-title="DDR3 SDRAM" data-language-autonym="中文" data-language-local-name="chino" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q847207#sitelinks-wikipedia" title="Editar enlaces interlingüísticos" class="wbc-editpage">Editar enlaces</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> <nav aria-label="Espacios de nombres"> <div id="p-associated-pages" class="vector-menu vector-menu-tabs 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class="mw-default-size" typeof="mw:File"><a href="/wiki/Archivo:Spanish_Language_Wiki.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/2a/Spanish_Language_Wiki.svg/60px-Spanish_Language_Wiki.svg.png" decoding="async" width="44" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/2a/Spanish_Language_Wiki.svg/120px-Spanish_Language_Wiki.svg.png 1.5x" data-file-width="220" data-file-height="200" /></a></span></td> <td class="ambox-text"><div class="ambox-text-div"><strong>Este artículo o sección sobre tecnología e informática necesita ser <a href="/wiki/Ayuda:Wikificar" title="Ayuda:Wikificar">wikificado</a>, por favor, <a class="external text" href="https://es.wikipedia.org/w/index.php?title=DDR3_SDRAM&action=edit">edítalo</a> para que cumpla con las <a href="/wiki/Wikipedia:Manual_de_estilo" title="Wikipedia:Manual de estilo">convenciones de estilo</a>.</strong></div><div class="hide-when-compact"><small><div>Este aviso fue puesto el 29 de noviembre de 2014.</div></small></div></td> </tr> </tbody></table> <style data-mw-deduplicate="TemplateStyles:r157776694">.mw-parser-output .infobox .imagen{max-width:100%;margin:0 auto}.mw-parser-output .infobox .imagen img{max-width:100%;height:auto}.mw-parser-output .infobox .mw-kartographer-container .thumbinner,.mw-parser-output .infobox .mw-kartographer-map{box-sizing:border-box;width:100%!important}body.skin-timeless .mw-parser-output .infobox .imagen a.image>img{max-width:100%!important;height:auto!important}</style><table class="infobox" style="width:22.7em; line-height: 1.4em; text-align:left; padding:.23em;"><tbody><tr><th colspan="3" class="cabecera hardware" style="text-align:center;background-color:transparent;color:inherit;background-color: #ccccff; color:#000;">DDR3 SDRAM</th></tr><tr><td colspan="3" class="imagen" style="text-align:center;width:65%;"> <span typeof="mw:File"><a href="/wiki/Archivo:2013_Transcend_TS512MLK72V6N-(straightened).jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/6b/2013_Transcend_TS512MLK72V6N-%28straightened%29.jpg/250px-2013_Transcend_TS512MLK72V6N-%28straightened%29.jpg" decoding="async" width="250" height="59" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/6b/2013_Transcend_TS512MLK72V6N-%28straightened%29.jpg/500px-2013_Transcend_TS512MLK72V6N-%28straightened%29.jpg 1.5x" data-file-width="1964" data-file-height="466" /></a></span></td></tr><tr><th colspan="3" style="text-align:center;background-color: #ccccff; color:#000;">Información</th></tr><tr><th scope="row" style="text-align:left;background-color: #ddddff; width:35%;">Tipo</th><td colspan="2" style="width:65%;"> norma técnica</td></tr><tr><th colspan="3" style="text-align:center;background-color: #ccccff; color:#000;">Cronología</th></tr><tr style="font-size:88%;text-align:center;"><td colspan="3" style="padding:0;"><table style="width:100%;"><tbody><tr><td style="width:33%;padding:0.2em 0.1em 0.2em 0;vertical-align:middle;"><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2 SDRAM</a></td><td style="width:33%;padding:0.2em 0.1em;vertical-align:middle;background-color:#E6E8FA;"><div style="display:inline;font-weight:bold;font-style:;">DDR3 SDRAM</div></td><td style="width:33%;padding:0.2em 0 0.2em 0.1em;vertical-align:middle;"><a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a></td></tr></tbody></table></td></tr><tr><td class="noprint" colspan="3" style="text-align:left;"><div class="plainlinks wikidata-link" style="font-size: 0.85em">[<a href="https://www.wikidata.org/wiki/Q847207" class="extiw" title="d:Q847207">editar datos en Wikidata</a>]</div></td></tr></tbody></table> <p><b> DDR3 SDRAM</b> (de las siglas en <a href="/wiki/Idioma_ingl%C3%A9s" title="Idioma inglés">inglés</a>, <i><b>D</b>ouble <b>D</b>ata <b>R</b>ate type <b>three</b> <b>S</b>ynchronous <b>D</b>ynamic <b>R</b>andom-<b>A</b>ccess <b>M</b>emory</i>) es un tipo de <a href="/wiki/Memoria_de_ordenador" class="mw-redirect" title="Memoria de ordenador">memoria</a> <a href="/wiki/Memoria_de_acceso_aleatorio" title="Memoria de acceso aleatorio">RAM</a>, de la familia de las <a href="/wiki/SDRAM" title="SDRAM">SDRAM</a> usadas desde principios de 2007.<sup id="cite_ref-1" class="mw-references reference separada"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-2" class="mw-references reference separada"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Visión_general"><span id="Visi.C3.B3n_general"></span>Visión general</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=1" title="Editar sección: Visión general"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>DDR3 SDRAM permite usar integrados de 1 <a href="/wiki/Gibibyte" title="Gibibyte">GiB</a> a 8 GiB, siendo posible soportar módulos de hasta 16 GiB. </p> <div class="mw-heading mw-heading3"><h3 id="Características"><span id="Caracter.C3.ADsticas"></span>Características</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=2" title="Editar sección: Características"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/Archivo:Desktop_DDR_Memory_Comparison.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1b/Desktop_DDR_Memory_Comparison.svg/250px-Desktop_DDR_Memory_Comparison.svg.png" decoding="async" width="220" height="331" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1b/Desktop_DDR_Memory_Comparison.svg/330px-Desktop_DDR_Memory_Comparison.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1b/Desktop_DDR_Memory_Comparison.svg/500px-Desktop_DDR_Memory_Comparison.svg.png 2x" data-file-width="575" data-file-height="865" /></a><figcaption>Comparación gráfica entre memorias DDR, DDR2, DDR3 y DDR4</figcaption></figure> <p>Los DDR3 tienen 240 pines al igual que DDR2 pero los <a href="/wiki/DIMM" title="DIMM">DIMM</a> son físicamente incompatibles, debido a una ubicación diferente de la muesca. DDR3 continúa la tendencia, duplicando el mínimo de lectura o escritura en la unidad a 8 bits por ciclo. Esto permite otra duplicación de la velocidad de bus sin tener que cambiar la velocidad de reloj de las operaciones internas. Para mantener las transferencias de 800-1600 Mb/s, la matriz RAM interna tiene que realizar sólo 100-200 millones de accesos por segundo.<sup id="cite_ref-3" class="mw-references reference separada"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Ventajas">Ventajas</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=3" title="Editar sección: Ventajas"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>El principal beneficio de DDR3 frente a DDR2 es la posibilidad de hacer transferencias de datos más rápidamente, y con esto obtener velocidades de transferencia y de bus más altas.</li> <li>Proporciona significativas mejoras de rendimiento en niveles de bajo voltaje(1,5 a 1,2 V), lo que conlleva una disminución global del consumo eléctrico.</li></ul> <div class="mw-heading mw-heading4"><h4 id="Desventajas">Desventajas</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=4" title="Editar sección: Desventajas"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>La desventaja es que como sucedió con DDR2, las <a href="/wiki/Latencia" title="Latencia">Latencia</a> de acceso es proporcionalmente más alta. Compensando ese aumento de latencias con mayor velocidad de transferencia.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Historia">Historia</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=5" title="Editar sección: Historia"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Se preveía, que la tecnología DDR3 pudiera ser dos veces más rápida que la DDR2 y el alto ancho de banda que prometía ofrecer DDR3 era la mejor opción para la combinación de un sistema con procesadores <a href="/wiki/Dual-core" title="Dual-core">dual-core</a>, <a href="/w/index.php?title=Quad-core&action=edit&redlink=1" class="new" title="Quad-core (aún no redactado)">quad-core</a> y <a href="/w/index.php?title=HexaCore&action=edit&redlink=1" class="new" title="HexaCore (aún no redactado)">hexa-Core</a> (2,4 y 6 núcleos por microprocesador). Las tensiones más bajas del DDR3 (1,5 V frente 1,8 V de DDR2) ofrecen una solución térmica y energética más eficientes. </p><p>Teóricamente, estos módulos podían transferir datos a una tasa de reloj efectiva de 800-2600 MHz, comparado con el rango del DDR2 de 400-1200 MHz ó 200-533 MHz del DDR. Existen módulos de memoria <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR</a> y <a href="/wiki/DDR2" class="mw-redirect" title="DDR2">DDR2</a> de mayor frecuencia pero no estandarizados por <a href="/wiki/Joint_Electron_Device_Engineering_Council" title="Joint Electron Device Engineering Council">JEDEC</a>. </p><p>Si bien las latencias típicas DDR2 fueron 5-5-5-15 para el estándar <a href="/wiki/Joint_Electron_Device_Engineering_Council" title="Joint Electron Device Engineering Council">JEDEC</a>, para dispositivos DDR3 son 7-7-7-20 para DDR3-1066 y 9-9-9-24 para DDR3-1333. </p> <div class="mw-heading mw-heading3"><h3 id="Desarrollo">Desarrollo</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=6" title="Editar sección: Desarrollo"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="2005">2005</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=7" title="Editar sección: 2005"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>En 2005, <a href="/wiki/Samsung" title="Samsung">Samsung</a> anunció un chip prototipo de 512 <a href="/wiki/Mebibyte" title="Mebibyte"><b>MiB</b></a> (denominado "512 MB") a 1.066 <a href="/wiki/MHz" class="mw-redirect" title="MHz">MHz</a> (la misma velocidad de bus frontal del <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a> Extreme Edition más rápido) con una reducción de consumo de energía de un 40% comparado con los actuales módulos comerciales DDR2, debido a la tecnología de 80 <a href="/wiki/Nan%C3%B3metros" class="mw-redirect" title="Nanómetros">nanómetros</a> usada en el diseño del DDR3 que permite más bajas corrientes de operación y tensiones (1,5V , comparado con los 1,8 del DDR2 o los 2,6 del DDR). Dispositivos pequeños, ahorradores de energía, como <a href="/wiki/Ordenador_port%C3%A1til" class="mw-redirect" title="Ordenador portátil">computadoras portátiles</a> quizás se puedan beneficiar de la tecnología DDR3.<sup id="cite_ref-4" class="mw-references reference separada"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-5" class="mw-references reference separada"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Lanzamiento">Lanzamiento</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=8" title="Editar sección: Lanzamiento"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>En 2008, <a href="/wiki/Kingston_Technology" title="Kingston Technology">Kingston Technology</a> lanzó los primeros módulos de memoria a 2GB, para plataformas Intel Core i7 (<a href="/wiki/Intel_Core_i5_(Nehalem)" title="Intel Core i5 (Nehalem)">Nehalem</a> y <a href="/w/index.php?title=Intel_Core_i7_(Bloomfield)&action=edit&redlink=1" class="new" title="Intel Core i7 (Bloomfield) (aún no redactado)">Bloomfield </a>).<sup id="cite_ref-6" class="mw-references reference separada"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Predecesor">Predecesor</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=9" title="Editar sección: Predecesor"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="DDR2_SDRAM">DDR2 SDRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=10" title="Editar sección: DDR2 SDRAM"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="noprint AP rellink"><span style="font-size:88%">Artículo principal:</span> <i><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM"> DDR2 SDRAM</a></i></div> <div class="mw-heading mw-heading3"><h3 id="Sucesor">Sucesor</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=11" title="Editar sección: Sucesor"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="DDR4_SDRAM">DDR4 SDRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=12" title="Editar sección: DDR4 SDRAM"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="noprint AP rellink"><span style="font-size:88%">Artículo principal:</span> <i><a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM"> DDR4 SDRAM</a></i></div> <p>Sus principales ventajas en comparación con <a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> y <a class="mw-selflink selflink">DDR3</a> son una tasa más alta de frecuencias de reloj y de transferencias de datos (1600 a 4400 MHz en comparación con DDR3 de 800Mhz a 2400MHz), la tensión es también menor a sus antecesoras (1,45 a 1,05 para DDR4 y 1,65 a 1,2 para DDR3) DDR4 también apunta un cambio en la topología descartando los enfoques de doble y triple canal, cada controlador de memoria está conectado a un módulo único. </p> <div class="mw-heading mw-heading2"><h2 id="Visión_detallada"><span id="Visi.C3.B3n_detallada"></span>Visión detallada</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=13" title="Editar sección: Visión detallada"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Estándares"><span id="Est.C3.A1ndares"></span>Estándares</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=14" title="Editar sección: Estándares"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Estos son los estándares de memoria DDR3 actualmente en el mercado: </p> <table class="wikitable"> <tbody><tr> <th>Nombre estándar </th> <th>Velocidad del reloj </th> <th>Tiempo entre señales </th> <th>Velocidad del reloj de entrada/salida </th> <th>Datos transferidos por segundo </th> <th>Nombre del módulo </th> <th>Máxima capacidad de transferencia según el ancho de banda </th></tr> <tr> <td>DDR3-800</td> <td>100 MHz</td> <td>9,5 ns</td> <td>400 MHz</td> <td>80055 <p>millones || PC3-6400 || 6400 <a href="/w/index.php?title=MB/s&action=edit&redlink=1" class="new" title="MB/s (aún no redactado)">MB/s</a> </p> </td></tr> <tr> <td>DDR3-1066</td> <td>133 MHz</td> <td>7,5 ns</td> <td>533 MHz</td> <td>1066 millones</td> <td>PC3-8500</td> <td>8528 <a href="/w/index.php?title=MB/s&action=edit&redlink=1" class="new" title="MB/s (aún no redactado)">MB/s</a> </td></tr> <tr> <td>DDR3-1333</td> <td>166 MHz</td> <td>6 ns</td> <td>666 MHz</td> <td>1333 millones</td> <td>PC3-10600</td> <td>10664 <a href="/w/index.php?title=MB/s&action=edit&redlink=1" class="new" title="MB/s (aún no redactado)">MB/s</a> </td></tr> <tr> <td>DDR3-1600</td> <td>200 MHz</td> <td>5 ns</td> <td>800 MHz</td> <td>1600 millones</td> <td>PC3-12800</td> <td>12800 <a href="/w/index.php?title=MB/s&action=edit&redlink=1" class="new" title="MB/s (aún no redactado)">MB/s</a> </td></tr> <tr> <td>DDR3-1866</td> <td>233 MHz</td> <td>4,3 ns</td> <td>933 MHz</td> <td>1866 millones</td> <td>PC3-14900</td> <td>14928 <a href="/w/index.php?title=MB/s&action=edit&redlink=1" class="new" title="MB/s (aún no redactado)">MB/s</a> </td></tr> <tr> <td>DDR3-2133</td> <td>266 MHz</td> <td>3,3 ns</td> <td>1066 MHz</td> <td>2133 millones</td> <td>PC3-17000</td> <td>17064 <a href="/w/index.php?title=MB/s&action=edit&redlink=1" class="new" title="MB/s (aún no redactado)">MB/s</a> </td></tr> <tr> <td>DDR3-2400</td> <td>300 MHz</td> <td>3 ns</td> <td>1200 MHz</td> <td>2400 millones</td> <td>PC3-19200</td> <td>19200 <a href="/w/index.php?title=MB/s&action=edit&redlink=1" class="new" title="MB/s (aún no redactado)">MB/s</a> </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Tecnologías_relacionadas"><span id="Tecnolog.C3.ADas_relacionadas"></span>Tecnologías relacionadas</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=15" title="Editar sección: Tecnologías relacionadas"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="GDDR3">GDDR3</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=16" title="Editar sección: GDDR3"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="noprint AP rellink"><span style="font-size:88%">Artículo principal:</span> <i><a href="/wiki/GDDR3" title="GDDR3"> GDDR3</a></i></div> <p>La memoria GDDR3, con un nombre similar pero con una tecnología completamente distinta, ha sido usada durante varios años en <a href="/wiki/Tarjeta_gr%C3%A1fica" title="Tarjeta gráfica">tarjetas gráficas</a> de gama alta como las series <a href="/wiki/GeForce" title="GeForce">GeForce</a> 6x00 o <a href="/wiki/Radeon" title="Radeon">ATI Radeon X800 Pro</a>, y es la utilizada como memoria principal de la <a href="/wiki/Xbox_360" title="Xbox 360">Xbox 360</a>. A veces es incorrectamente citada como "DDR3". </p> <div class="mw-heading mw-heading3"><h3 id="DDR3L">DDR3L</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=17" title="Editar sección: DDR3L"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Aunque es compatible con la especificación, los DDR3L (PC3L o SoDIMM) operan a un voltaje menor de 1,35 V y fue diseñado para los procesadores de cuarta generación de Intel.<sup id="cite_ref-Dell_7-0" class="mw-references reference separada"><a href="#cite_note-Dell-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Véase_también"><span id="V.C3.A9ase_tambi.C3.A9n"></span>Véase también</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=18" title="Editar sección: Véase también"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="Referencias">Referencias</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR3_SDRAM&action=edit&section=19" title="Editar sección: Referencias"><span>editar</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="listaref" style="list-style-type: decimal;"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><a href="#cite_ref-1">↑</a></span> <span class="reference-text"><cite class="web"></cite><span class="citation web"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110629125858/http://www.ieee.org/portal/cms_docs_societies/sscs/PrintEditions/200801.pdf">«The DRAM Story»</a> <span style="color:var(--color-subtle, #555 );">(PDF)</span> <span style="color:var(--color-subtle, #555 );">(en inglés)</span>. www.ieee.org. Archivado desde <a rel="nofollow" class="external text" href="http://www.ieee.org/portal/cms_docs_societies/sscs/PrintEditions/200801.pdf">el original</a> el 29 de junio de 2011.</span><span title="ctx_ver=Z39.88-2004&rfr_id=info%3Asid%2Fes.wikipedia.org%3ADDR3+SDRAM&rft.btitle=The+DRAM+Story&rft.genre=book&rft.pub=www.ieee.org&rft_id=http%3A%2F%2Fwww.ieee.org%2Fportal%2Fcms_docs_societies%2Fsscs%2FPrintEditions%2F200801.pdf&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook" class="Z3988"><span style="display:none;"> </span></span></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><a href="#cite_ref-2">↑</a></span> <span class="reference-text"><cite class="web"></cite><span class="citation web"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110715115615/http://www.ocmodshop.com/ddr3-faq/">«DDR3 FAQ»</a> <span style="color:var(--color-subtle, #555 );">(en inglés)</span>. www.ocmodshop.com. Archivado desde <a rel="nofollow" class="external text" href="http://www.ocmodshop.com/ddr3-faq/">el original</a> el 15 de julio de 2011<span class="reference-accessdate">. Consultado el 8 de febrero de 2013</span>.</span><span title="ctx_ver=Z39.88-2004&rfr_id=info%3Asid%2Fes.wikipedia.org%3ADDR3+SDRAM&rft.btitle=DDR3+FAQ&rft.genre=book&rft.pub=www.ocmodshop.com&rft_id=http%3A%2F%2Fwww.ocmodshop.com%2Fddr3-faq%2F&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook" class="Z3988"><span style="display:none;"> </span></span></span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><a href="#cite_ref-3">↑</a></span> <span class="reference-text"><cite class="web"></cite><span class="citation web"><a rel="nofollow" class="external text" href="http://www.jedec.org/standards-documents/docs/module-42018">«204-Pin DDR3 SDRAM Unbuffered SODIMM Design Specification»</a> <span style="color:var(--color-subtle, #555 );">(en inglés)</span>. www.jedex.org.</span><span title="ctx_ver=Z39.88-2004&rfr_id=info%3Asid%2Fes.wikipedia.org%3ADDR3+SDRAM&rft.btitle=204-Pin+DDR3+SDRAM+Unbuffered+SODIMM+Design+Specification&rft.genre=book&rft.pub=www.jedex.org&rft_id=http%3A%2F%2Fwww.jedec.org%2Fstandards-documents%2Fdocs%2Fmodule-42018&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook" class="Z3988"><span style="display:none;"> </span></span></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><a href="#cite_ref-4">↑</a></span> <span class="reference-text"><cite class="web"></cite><span class="citation web"><a rel="nofollow" class="external text" href="http://www.xataka.com/perifericos/samsung-presenta-las-memorias-ddr3">«Samsung presenta las memorias DDR3»</a>. www.xataka.com.</span><span title="ctx_ver=Z39.88-2004&rfr_id=info%3Asid%2Fes.wikipedia.org%3ADDR3+SDRAM&rft.btitle=Samsung+presenta+las+memorias+DDR3&rft.genre=book&rft.pub=www.xataka.com&rft_id=http%3A%2F%2Fwww.xataka.com%2Fperifericos%2Fsamsung-presenta-las-memorias-ddr3&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook" class="Z3988"><span style="display:none;"> </span></span></span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><a href="#cite_ref-5">↑</a></span> <span class="reference-text"><cite class="web"></cite><span class="citation web"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110726202302/http://www.jedex.org/images/pdf/samsung%20-%20jaci_chang.pdf">«Design Considerations for the DDR3 Memory Sub-system»</a> <span style="color:var(--color-subtle, #555 );">(PDF)</span> <span style="color:var(--color-subtle, #555 );">(en inglés)</span>. www.jedex.org. Archivado desde <a rel="nofollow" class="external text" href="http://www.jedex.org/images/pdf/samsung%20-%20jaci_chang.pdf">el original</a> el 26 de julio de 2011.</span><span title="ctx_ver=Z39.88-2004&rfr_id=info%3Asid%2Fes.wikipedia.org%3ADDR3+SDRAM&rft.btitle=Design+Considerations+for+the+DDR3+Memory+Sub-system&rft.genre=book&rft.pub=www.jedex.org&rft_id=http%3A%2F%2Fwww.jedex.org%2Fimages%2Fpdf%2Fsamsung%2520-%2520jaci_chang.pdf&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook" class="Z3988"><span style="display:none;"> </span></span></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><a href="#cite_ref-6">↑</a></span> <span class="reference-text"><cite class="web"></cite><span class="citation web"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20081101113745/http://www.xbitlabs.com/news/memory/display/20081029141143_Kingston_Rolls_Out_Industry_s_First_2GHz_Memory_Modules_for_Intel_Core_i7_Platforms.html">«Kingston Rolls Out Industry’s First 2GHz Memory Modules for Intel Core i7 Platforms»</a> <span style="color:var(--color-subtle, #555 );">(PDF)</span> <span style="color:var(--color-subtle, #555 );">(en inglés)</span>. www.xbitlabs.com. Archivado desde <a rel="nofollow" class="external text" href="http://www.xbitlabs.com/news/memory/display/20081029141143_Kingston_Rolls_Out_Industry_s_First_2GHz_Memory_Modules_for_Intel_Core_i7_Platforms.html">el original</a> el 1 de noviembre de 2008.</span><span title="ctx_ver=Z39.88-2004&rfr_id=info%3Asid%2Fes.wikipedia.org%3ADDR3+SDRAM&rft.btitle=Kingston+Rolls+Out+Industry%E2%80%99s+First+2GHz+Memory+Modules+for+Intel+Core+i7+Platforms&rft.genre=book&rft.pub=www.xbitlabs.com&rft_id=http%3A%2F%2Fwww.xbitlabs.com%2Fnews%2Fmemory%2Fdisplay%2F20081029141143_Kingston_Rolls_Out_Industry_s_First_2GHz_Memory_Modules_for_Intel_Core_i7_Platforms.html&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook" class="Z3988"><span style="display:none;"> </span></span></span> </li> <li id="cite_note-Dell-7"><span class="mw-cite-backlink"><a href="#cite_ref-Dell_7-0">↑</a></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://www.dell.com/support/article/es-ve/sln153768/qué-es-la-memoria-ddr3l?lang=es">¿Qué es la memoria DDR3L?</a>, <a href="/wiki/Dell" title="Dell">Dell</a></span> </li> </ol></div> <style data-mw-deduplicate="TemplateStyles:r161257576">.mw-parser-output .mw-authority-control{margin-top:1.5em}.mw-parser-output .mw-authority-control .navbox table{margin:0}.mw-parser-output .mw-authority-control .navbox hr:last-child{display:none}.mw-parser-output .mw-authority-control .navbox+.mw-mf-linked-projects{display:none}.mw-parser-output .mw-authority-control .mw-mf-linked-projects{display:flex;padding:0.5em;border:1px solid var(--border-color-base,#a2a9b1);background-color:var(--background-color-neutral,#eaecf0);color:var(--color-base,#202122)}.mw-parser-output .mw-authority-control .mw-mf-linked-projects ul li{margin-bottom:0}.mw-parser-output .mw-authority-control .navbox{border:1px solid var(--border-color-base,#a2a9b1);background-color:var(--background-color-neutral-subtle,#f8f9fa)}.mw-parser-output .mw-authority-control .navbox-list{border-color:#f8f9fa}.mw-parser-output .mw-authority-control .navbox th{background-color:#eeeeff}html.skin-theme-clientpref-night .mw-parser-output .mw-authority-control .mw-mf-linked-projects{border:1px solid var(--border-color-base,#72777d);background-color:var(--background-color-neutral,#27292d);color:var(--color-base,#eaecf0)}html.skin-theme-clientpref-night .mw-parser-output .mw-authority-control .navbox{border:1px solid var(--border-color-base,#72777d)!important;background-color:var(--background-color-neutral-subtle,#202122)!important}html.skin-theme-clientpref-night .mw-parser-output .mw-authority-control .navbox-list{border-color:#202122!important}html.skin-theme-clientpref-night .mw-parser-output .mw-authority-control .navbox th{background-color:#27292d!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .mw-authority-control .mw-mf-linked-projects{border:1px solid var(--border-color-base,#72777d)!important;background-color:var(--background-color-neutral,#27292d)!important;color:var(--color-base,#eaecf0)!important}html.skin-theme-clientpref-os .mw-parser-output .mw-authority-control .navbox{border:1px solid var(--border-color-base,#72777d)!important;background-color:var(--background-color-neutral-subtle,#202122)!important}html.skin-theme-clientpref-os .mw-parser-output .mw-authority-control .navbox-list{border-color:#202122!important}html.skin-theme-clientpref-os .mw-parser-output .mw-authority-control .navbox th{background-color:#27292d!important}}</style><div class="mw-authority-control"><div role="navigation" class="navbox" aria-label="Navbox" style="width: inherit;padding:3px"><table class="hlist navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="row" class="navbox-group" style="width: 12%; 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