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mw-ui-icon-wikimedia-expand"></span> <span>Afficher / masquer la sous-section Détails techniques</span> </button> <ul id="toc-Détails_techniques-sublist" class="vector-toc-list"> <li id="toc-Les_sockets_utilisés" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Les_sockets_utilisés"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>Les sockets utilisés</span> </div> </a> <ul id="toc-Les_sockets_utilisés-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-L'hyper-threading" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#L'hyper-threading"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2</span> <span>L'hyper-threading</span> </div> </a> <ul id="toc-L'hyper-threading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Le_Turbo_Boost" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Le_Turbo_Boost"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.3</span> <span>Le Turbo Boost</span> </div> </a> <ul id="toc-Le_Turbo_Boost-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Le_contrôleur_mémoire" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Le_contrôleur_mémoire"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4</span> <span>Le contrôleur mémoire</span> </div> </a> <ul id="toc-Le_contrôleur_mémoire-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Bug_et_autres_problèmes" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Bug_et_autres_problèmes"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.5</span> <span>Bug et autres problèmes</span> </div> </a> <ul id="toc-Bug_et_autres_problèmes-sublist" class="vector-toc-list"> <li id="toc-Sockets_1156_défectueux" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Sockets_1156_défectueux"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.5.1</span> <span>Sockets 1156 défectueux</span> </div> </a> <ul id="toc-Sockets_1156_défectueux-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Surchauffe_des_Skylake_et_Kaby_Lake" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Surchauffe_des_Skylake_et_Kaby_Lake"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.5.2</span> <span>Surchauffe des Skylake et Kaby Lake</span> </div> </a> <ul id="toc-Surchauffe_des_Skylake_et_Kaby_Lake-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-La_gamme_pour_PC_de_Bureau" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#La_gamme_pour_PC_de_Bureau"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>La gamme pour PC de Bureau</span> </div> </a> <button aria-controls="toc-La_gamme_pour_PC_de_Bureau-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Afficher / masquer la sous-section La gamme pour PC de Bureau</span> </button> <ul id="toc-La_gamme_pour_PC_de_Bureau-sublist" class="vector-toc-list"> <li id="toc-Westmere_'Gulftown'" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Westmere_'Gulftown'"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Westmere 'Gulftown'</span> </div> </a> <ul id="toc-Westmere_'Gulftown'-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Nehalem_'Bloomfield'" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Nehalem_'Bloomfield'"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>Nehalem 'Bloomfield'</span> </div> </a> <ul id="toc-Nehalem_'Bloomfield'-sublist" class="vector-toc-list"> <li id="toc-Révision_D0" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Révision_D0"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.1</span> <span>Révision D0</span> </div> </a> <ul id="toc-Révision_D0-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Liste_des_processeurs" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Liste_des_processeurs"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.2</span> <span>Liste des processeurs</span> </div> </a> <ul id="toc-Liste_des_processeurs-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Nehalem_'Lynnfield'" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Nehalem_'Lynnfield'"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Nehalem 'Lynnfield'</span> </div> </a> <ul id="toc-Nehalem_'Lynnfield'-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Sandy_Bridge" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Sandy_Bridge"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>Sandy Bridge</span> </div> </a> <ul id="toc-Sandy_Bridge-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Ivy_Bridge" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Ivy_Bridge"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.5</span> <span>Ivy Bridge</span> </div> </a> <ul id="toc-Ivy_Bridge-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Haswell" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Haswell"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.6</span> <span>Haswell</span> </div> </a> <ul id="toc-Haswell-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Skylake" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Skylake"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.7</span> <span>Skylake</span> </div> </a> <ul id="toc-Skylake-sublist" class="vector-toc-list"> <li id="toc-Kaby_Lake" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.7.1</span> <span>Kaby Lake</span> </div> </a> <ul id="toc-Kaby_Lake-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Coffee_Lake" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Coffee_Lake"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.7.2</span> <span>Coffee Lake</span> </div> </a> <ul id="toc-Coffee_Lake-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-La_gamme_pour_PC_portables" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#La_gamme_pour_PC_portables"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>La gamme pour PC portables</span> </div> </a> <button aria-controls="toc-La_gamme_pour_PC_portables-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Afficher / masquer la sous-section La gamme pour PC portables</span> </button> <ul id="toc-La_gamme_pour_PC_portables-sublist" class="vector-toc-list"> <li id="toc-Clarksfield" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Clarksfield"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Clarksfield</span> </div> </a> <ul id="toc-Clarksfield-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Arrandale" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Arrandale"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Arrandale</span> </div> </a> <ul id="toc-Arrandale-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Sandy_Bridge_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Sandy_Bridge_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Sandy Bridge</span> </div> </a> <ul id="toc-Sandy_Bridge_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Ivy_Bridge_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Ivy_Bridge_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4</span> <span>Ivy Bridge</span> </div> </a> <ul id="toc-Ivy_Bridge_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Haswell_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Haswell_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.5</span> <span>Haswell</span> </div> </a> <ul id="toc-Haswell_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Skylake_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Skylake_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.6</span> <span>Skylake</span> </div> </a> <ul id="toc-Skylake_2-sublist" class="vector-toc-list"> <li id="toc-Kaby_Lake_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.6.1</span> <span>Kaby Lake</span> </div> </a> <ul id="toc-Kaby_Lake_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Chipsets_compatibles" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Chipsets_compatibles"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Chipsets compatibles</span> </div> </a> <ul id="toc-Chipsets_compatibles-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Performances_relatives_brutes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Performances_relatives_brutes"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Performances relatives brutes</span> </div> </a> <ul id="toc-Performances_relatives_brutes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes_et_références" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Notes_et_références"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Notes et références</span> </div> </a> <button aria-controls="toc-Notes_et_références-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Afficher / masquer la sous-section Notes et références</span> </button> <ul id="toc-Notes_et_références-sublist" class="vector-toc-list"> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">6.1</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Références" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Références"> <div class="vector-toc-text"> <span class="vector-toc-numb">6.2</span> <span>Références</span> </div> </a> <ul id="toc-Références-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Voir_aussi" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Voir_aussi"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Voir aussi</span> </div> </a> <button aria-controls="toc-Voir_aussi-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Afficher / masquer la sous-section Voir aussi</span> </button> <ul id="toc-Voir_aussi-sublist" class="vector-toc-list"> <li id="toc-Articles_connexes" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Articles_connexes"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.1</span> <span>Articles connexes</span> </div> </a> <ul id="toc-Articles_connexes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Liens_externes" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Liens_externes"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.2</span> <span>Liens externes</span> </div> </a> <ul id="toc-Liens_externes-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Sommaire" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" title="Table des matières" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Basculer la table des matières" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Basculer la table des matières</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">Intel Core i7</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Aller à un article dans une autre langue. Disponible en 28 langues." > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-28" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">28 langues</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%A5%D9%86%D8%AA%D9%84_%D9%83%D9%88%D8%B1_%D8%A2%D9%8A_7" title="إنتل كور آي 7 – arabe" lang="ar" hreflang="ar" data-title="إنتل كور آي 7" data-language-autonym="العربية" data-language-local-name="arabe" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Core_i7" title="Core i7 – catalan" lang="ca" hreflang="ca" data-title="Core i7" data-language-autonym="Català" data-language-local-name="catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-de badge-Q70894304 mw-list-item" title=""><a href="https://de.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – allemand" lang="de" hreflang="de" data-title="Intel Core i7" data-language-autonym="Deutsch" data-language-local-name="allemand" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-en badge-Q70893996 mw-list-item" title=""><a href="https://en.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – anglais" lang="en" hreflang="en" data-title="Intel Core i7" data-language-autonym="English" data-language-local-name="anglais" class="interlanguage-link-target"><span>English</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Intel_Core_i7_(Nehalem)" title="Intel Core i7 (Nehalem) – espagnol" lang="es" hreflang="es" data-title="Intel Core i7 (Nehalem)" data-language-autonym="Español" data-language-local-name="espagnol" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/Core_i7" title="Core i7 – estonien" lang="et" hreflang="et" data-title="Core i7" data-language-autonym="Eesti" data-language-local-name="estonien" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%A7%DB%8C%D9%86%D8%AA%D9%84_%DA%A9%D9%88%D8%B1_%D8%A2%DB%8C-%DB%B7" title="اینتل کور آی-۷ – persan" lang="fa" hreflang="fa" data-title="اینتل کور آی-۷" data-language-autonym="فارسی" data-language-local-name="persan" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-gl mw-list-item"><a href="https://gl.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – galicien" lang="gl" hreflang="gl" data-title="Intel Core i7" data-language-autonym="Galego" data-language-local-name="galicien" class="interlanguage-link-target"><span>Galego</span></a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – croate" lang="hr" hreflang="hr" data-title="Intel Core i7" data-language-autonym="Hrvatski" data-language-local-name="croate" class="interlanguage-link-target"><span>Hrvatski</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – indonésien" lang="id" hreflang="id" data-title="Intel Core i7" data-language-autonym="Bahasa Indonesia" data-language-local-name="indonésien" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Core_i7" title="Core i7 – italien" lang="it" hreflang="it" data-title="Core i7" data-language-autonym="Italiano" data-language-local-name="italien" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – japonais" lang="ja" hreflang="ja" data-title="Intel Core i7" data-language-autonym="日本語" data-language-local-name="japonais" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%9D%B8%ED%85%94_%EC%BD%94%EC%96%B4_i7" title="인텔 코어 i7 – coréen" lang="ko" hreflang="ko" data-title="인텔 코어 i7" data-language-autonym="한국어" data-language-local-name="coréen" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – néerlandais" lang="nl" hreflang="nl" data-title="Intel Core i7" data-language-autonym="Nederlands" data-language-local-name="néerlandais" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – norvégien bokmål" lang="nb" hreflang="nb" data-title="Intel Core i7" data-language-autonym="Norsk bokmål" data-language-local-name="norvégien bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-oc mw-list-item"><a href="https://oc.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – occitan" lang="oc" hreflang="oc" data-title="Intel Core i7" data-language-autonym="Occitan" data-language-local-name="occitan" class="interlanguage-link-target"><span>Occitan</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – polonais" lang="pl" hreflang="pl" data-title="Intel Core i7" data-language-autonym="Polski" data-language-local-name="polonais" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pnt mw-list-item"><a href="https://pnt.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – pontique" lang="pnt" hreflang="pnt" data-title="Intel Core i7" data-language-autonym="Ποντιακά" data-language-local-name="pontique" class="interlanguage-link-target"><span>Ποντιακά</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Intel_Core_i7" title="Intel Core i7 – portugais" lang="pt" hreflang="pt" data-title="Intel Core i7" data-language-autonym="Português" data-language-local-name="portugais" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro 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class="bandeau-container metadata homonymie hatnote"><div class="bandeau-cell bandeau-icone" style="display:table-cell;padding-right:0.5em"><span class="noviewer" typeof="mw:File"><a href="/wiki/Aide:Homonymie" title="Aide:Homonymie"><img alt="Page d’aide sur l’homonymie" src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Logo_disambig.svg/20px-Logo_disambig.svg.png" decoding="async" width="20" height="15" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Logo_disambig.svg/30px-Logo_disambig.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Logo_disambig.svg/40px-Logo_disambig.svg.png 2x" data-file-width="512" data-file-height="375" /></a></span></div><div class="bandeau-cell" style="display:table-cell;padding-right:0.5em"> <p>Pour les articles homonymes, voir <a href="/wiki/Core" class="mw-disambig" title="Core">Core</a> et <a href="/wiki/Intel_Core" class="mw-disambig" title="Intel Core">Intel Core</a>. </p> </div></div> <div class="infobox_v3 infobox infobox--frwiki noarchive"> <div class="entete" style="background-color: #127cc1; color: #ffffff;"> <div>Core i7</div> </div> <div class="images"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/Fichier:Intel_Core_i7_Logo_2020.png" class="mw-file-description"><img alt="Description de l'image Intel Core i7 Logo 2020.png." src="//upload.wikimedia.org/wikipedia/commons/thumb/c/ce/Intel_Core_i7_Logo_2020.png/250px-Intel_Core_i7_Logo_2020.png" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/ce/Intel_Core_i7_Logo_2020.png/330px-Intel_Core_i7_Logo_2020.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/ce/Intel_Core_i7_Logo_2020.png/500px-Intel_Core_i7_Logo_2020.png 2x" data-file-width="549" data-file-height="550" /></a></span> </div><table><caption style="background-color:#127cc1;color:#ffffff;">Informations générales</caption> <tbody><tr> <th scope="row"> Production </th> <td> Depuis <a href="/wiki/2008_en_informatique" title="2008 en informatique">2008</a></td> </tr> <tr> <th scope="row">Fabricant</th> <td> Intel</td> </tr> </tbody></table><table><caption style="background-color:#127cc1;color:#ffffff;">Performances</caption> <tbody><tr> <th scope="row"> Fréquence </th> <td> 1,06 <abbr class="abbr" title="gigahertz"><a href="/wiki/Hertz" title="Hertz">GHz</a></abbr> à 5 <abbr class="abbr" title="gigahertz"><a href="/wiki/Hertz" title="Hertz">GHz</a></abbr></td> </tr> <tr> <th scope="row"> Fréquence du <a href="/wiki/Front_side_bus" title="Front side bus">FSB</a> </th> <td> 2,5 <a href="/wiki/GT/s" class="mw-redirect" title="GT/s">GT/s</a> à 6,4 <a href="/wiki/GT/s" class="mw-redirect" title="GT/s">GT/s</a></td> </tr> </tbody></table><table><caption style="background-color:#127cc1;color:#ffffff;">Spécifications physiques</caption> <tbody><tr> <th scope="row"> Finesse de gravure </th> <td> 14 <a href="/wiki/Nanom%C3%A8tre" title="Nanomètre">nm</a> à 45 <abbr class="abbr" title="nanomètre"><a href="/wiki/Microm%C3%A8tre" title="Micromètre">nm</a></abbr></td> </tr> <tr> <th scope="row"> <a href="/wiki/Microprocesseur_multi-c%C5%93ur" title="Microprocesseur multi-cœur">Cœur</a> </th> <td> <ul><li>Nehalem (Gulftown, Bloomfield, Lynnfield, Clarksfield, Arrandale)</li> <li>Sandy Bridge</li> <li>Ivy Bridge</li> <li>Haswell</li> <li>Skylake</li> <li>Kaby Lake</li> <li>Coffee Lake</li></ul></td> </tr> <tr> <th scope="row"> <a href="/wiki/Socket_(processeur)" title="Socket (processeur)">Socket(s)</a> </th> <td> <a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a>, <a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a>, <a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a>, <a href="/wiki/LGA_2011" title="LGA 2011">LGA 2011</a>, <a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a>, <a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151</a> , <a href="/wiki/LGA_1700" title="LGA 1700">LGA 1700</a></td> </tr> </tbody></table><table><caption style="background-color:#127cc1;color:#ffffff;">Architecture et classification</caption> <tbody><tr> <th scope="row"> <a href="/wiki/Architecture_de_processeur" title="Architecture de processeur">Architecture</a> </th> <td> <a href="/wiki/X86" title="X86">x86</a>, <a href="/wiki/X86-64" class="mw-redirect" title="X86-64">x86-64</a>, <a href="/wiki/Jeu_d%27instructions_MMX" title="Jeu d'instructions MMX">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/Streaming_SIMD_Extension_2" title="Streaming SIMD Extension 2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a></td> </tr> <tr> <th scope="row"> <a href="/wiki/Microarchitecture" title="Microarchitecture">Micro-architecture</a> </th> <td> <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a>, <a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a>, <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a></td> </tr> </tbody></table> <p class="mw-empty-elt"> </p> <p class="navbar bordered noprint" style="border-color:#127cc1;"><span class="plainlinks navigation-not-searchable"><a class="external text" href="https://fr.wikipedia.org/w/index.php?title=Intel_Core_i7&action=edit">modifier</a></span> <span typeof="mw:File"><a href="/wiki/Mod%C3%A8le:Infobox_Microprocesseur" title="Consultez la documentation du modèle"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/3/38/Info_Simple.svg/12px-Info_Simple.svg.png" decoding="async" width="12" height="12" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/38/Info_Simple.svg/18px-Info_Simple.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/38/Info_Simple.svg/24px-Info_Simple.svg.png 2x" data-file-width="512" data-file-height="512" /></a></span></p></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/Fichier:Core_i7_920_quad_front_and_back.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/eb/Core_i7_920_quad_front_and_back.jpg/220px-Core_i7_920_quad_front_and_back.jpg" decoding="async" width="220" height="470" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/eb/Core_i7_920_quad_front_and_back.jpg/330px-Core_i7_920_quad_front_and_back.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/eb/Core_i7_920_quad_front_and_back.jpg/440px-Core_i7_920_quad_front_and_back.jpg 2x" data-file-width="1181" data-file-height="2522" /></a><figcaption>Intel Core i7 920.</figcaption></figure> <p>La marque <b>Core i7</b> d'<a href="/wiki/Intel" title="Intel">Intel</a> est utilisée pour ses <a href="/wiki/Microprocesseur" title="Microprocesseur">microprocesseurs</a> grand public haut de gamme depuis <time class="nowrap" datetime="2008-11" data-sort-value="2008-11">novembre 2008</time>. Les marques <a href="/wiki/Intel_Core_i5" title="Intel Core i5">Core i5</a>, <a href="/wiki/Intel_Core_i3" title="Intel Core i3">Core i3</a> et <a href="/wiki/Intel_Core_i9" title="Intel Core i9">Core i9</a> sont apparues ensuite. </p><p>Techniquement, les Core i7 peuvent appartenir aux familles <a href="/wiki/Nehalem_(microarchitecture)#Processeurs_de_la_famille_Nehalem_(gravure_45_nm)" title="Nehalem (microarchitecture)">Nehalem</a>, <a href="/wiki/Nehalem_(microarchitecture)#Processeurs_de_la_famille_Westmere_(gravure_32_nm)" title="Nehalem (microarchitecture)">Westmere</a>, <a href="/wiki/Sandy_Bridge#Famille_Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a>, <a href="/wiki/Ivy_Bridge" class="mw-redirect" title="Ivy Bridge">Ivy Bridge</a>, <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>, <a href="/wiki/Skylake" title="Skylake">Skylake</a>, <a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a> et <a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a>. </p><p>Ces processeurs sont généralement utilisés pour le rendu 3D et autres logiciels, en général accompagnés d'une <a href="/wiki/Carte_graphique" title="Carte graphique">carte graphique</a> hors processeur. </p><p>Leurs indices Passmark vont en entrée de gamme de 2 534 pour le modèle 4500U<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> (2013, 1,8 GHz), et 10 076 pour le 10710U (2019, 1,10 GHz), destinés aux portables, à 2,50 <abbr class="abbr" title="gigahertz">GHz</abbr> à 19 000 (6950X à 3,00 <abbr class="abbr" title="gigahertz">GHz</abbr>). Les Core i7 ont de deux à dix cœurs selon la gamme et la génération. On remarquera les progrès effectués tant en vitesse qu'en consommation pour les modèles U. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Détails_techniques"><span id="D.C3.A9tails_techniques"></span>Détails techniques</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=1" title="Modifier la section : Détails techniques" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=1" title="Modifier le code source de la section : Détails techniques"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css loupe">Articles connexes : <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem (microarchitecture)</a> et <a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a>.</div></div> <p>En 2008, la commercialisation des Core i7 marque l'avènement de la nouvelle <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">microarchitecture Nehalem</a> chargée de remplacer l'ancienne architecture <a href="/wiki/Core_(microarchitecture)" title="Core (microarchitecture)">Core</a>. </p> <div class="mw-heading mw-heading3"><h3 id="Les_sockets_utilisés"><span id="Les_sockets_utilis.C3.A9s"></span>Les sockets utilisés</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=2" title="Modifier la section : Les sockets utilisés" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=2" title="Modifier le code source de la section : Les sockets utilisés"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>LGA 1156</li> <li>LGA 1366</li> <li>LGA 1155</li> <li>LGA 1150</li> <li>LGA 1151</li> <li>LGA 2011</li> <li>LGA 2011-3</li> <li>LGA 2066</li> <li>LGA 1200</li> <li>LGA 1700</li></ul> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/Fichier:Socket_LGA_1366_open_R7309468_wp.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b2/Socket_LGA_1366_open_R7309468_wp.jpg/220px-Socket_LGA_1366_open_R7309468_wp.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b2/Socket_LGA_1366_open_R7309468_wp.jpg/330px-Socket_LGA_1366_open_R7309468_wp.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b2/Socket_LGA_1366_open_R7309468_wp.jpg/440px-Socket_LGA_1366_open_R7309468_wp.jpg 2x" data-file-width="2000" data-file-height="1500" /></a><figcaption>Socket LGA 1366.</figcaption></figure> <p>Les Core i7 de la famille Nehalem utilisent deux sockets différents : LGA 1366 pour les modèles Bloomfield (Core i7 9xx) et LGA 1156 pour les modèles Lynnfield (Core i7 8xx et Core i5). La présence au sein d'une même gamme de deux sockets distincts pose un problème d'une part en termes d'évolution là où Intel ne proposait précédemment que le <a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> et d'autre part en termes de communication vis-à-vis du consommateur. </p> <div class="mw-heading mw-heading3"><h3 id="L'hyper-threading"><span id="L.27hyper-threading"></span>L'hyper-threading</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=3" title="Modifier la section : L'hyper-threading" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=3" title="Modifier le code source de la section : L'hyper-threading"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>La commercialisation des Core i7 marque le retour de la technologie <a href="/wiki/Hyper-threading" title="Hyper-threading">Hyper-threading</a> (SMT deux voies) qui avait disparu depuis les <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a>. </p> <div class="mw-heading mw-heading3"><h3 id="Le_Turbo_Boost">Le Turbo Boost</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=4" title="Modifier la section : Le Turbo Boost" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=4" title="Modifier le code source de la section : Le Turbo Boost"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>La technologie <span class="lang-en" lang="en"><i>Turbo Boost</i></span> a été officiellement présentée au cours de l'IDF 2008 de San Francisco<sup id="cite_ref-comm_20080819_2-0" class="reference"><a href="#cite_note-comm_20080819-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup>. Elle permet de désactiver à la volée certains cœurs tout en augmentant la fréquence des autres. Son impact sur le(s) processeur(s) est d'autant plus grand que l'on désactive des cœurs. La hausse de fréquence s'effectue par pas de 133 MHz, appelés <i>bins</i> par la documentation technique d'Intel<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>. Une hausse de 2 bins équivaut ainsi à une augmentation de 266 MHz de chaque cœur actif. Cette solution permet ainsi de mieux tirer profit des applications non développées pour la gestion multi-cœur. Elle se distingue toutefois de la technologie employée sur les <a href="/wiki/Penryn_(microprocesseur)" title="Penryn (microprocesseur)">Penryn</a> mobiles, qui se fonde sur les informations fournies par le <a href="/wiki/Syst%C3%A8me_d%27exploitation" title="Système d'exploitation">système d'exploitation</a>. Avec le Turbo Boost, la gestion est interne au processeur. </p><p>Le mois suivant, Intel officialisait sa technologie sous le terme Dynamic Speed Technology (DST)<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>, qui a depuis été renommée Turbo Boost. </p> <div class="mw-heading mw-heading3"><h3 id="Le_contrôleur_mémoire"><span id="Le_contr.C3.B4leur_m.C3.A9moire"></span>Le contrôleur mémoire</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=5" title="Modifier la section : Le contrôleur mémoire" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=5" title="Modifier le code source de la section : Le contrôleur mémoire"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Le contrôleur des processeurs <a href="/wiki/Bloomfield_(microprocesseur)" title="Bloomfield (microprocesseur)">Bloomfield</a> communique avec la mémoire à travers trois canaux, tandis que celui des processeurs <a href="/wiki/Lynnfield" title="Lynnfield">Lynnfield</a> communique avec la mémoire à travers deux canaux. Plus récemment, les modèles basés sur la plateforme <a href="/wiki/LGA_2011" title="LGA 2011">LGA 2011-3</a> profitent d'un contrôleur quad-channel (quatre canaux mémoire). </p> <div class="mw-heading mw-heading3"><h3 id="Bug_et_autres_problèmes"><span id="Bug_et_autres_probl.C3.A8mes"></span>Bug et autres problèmes</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=6" title="Modifier la section : Bug et autres problèmes" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=6" title="Modifier le code source de la section : Bug et autres problèmes"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Sockets_1156_défectueux"><span id="Sockets_1156_d.C3.A9fectueux"></span>Sockets 1156 défectueux</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=7" title="Modifier la section : Sockets 1156 défectueux" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=7" title="Modifier le code source de la section : Sockets 1156 défectueux"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>À la suite de tests poussés d'augmentation de fréquence sur un Core i7 870, le site <a href="/wiki/AnandTech" title="AnandTech">AnandTech</a><sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> ainsi que plusieurs utilisateurs<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> ont endommagé sérieusement leurs cartes-mères à base de <a href="/wiki/Chipset" title="Chipset">chipset</a> P55 et leurs processeurs. À la suite d'investigations, le responsable serait le socket LGA 1156 conçu par <a href="/wiki/Foxconn" title="Foxconn">Foxconn</a> dont les mauvais contacts socket-processeur empêcheraient ce dernier de recevoir correctement toute l'énergie nécessaire. En réponse à ce problème, les fabricants de cartes-mères ont échangé leur socket pour des modèles de marques Lotes ou Tyco/AMP. Dans le même temps, <a href="/wiki/Foxconn" title="Foxconn">Foxconn</a> a réagi en réalisant de nouveaux sockets. </p> <div class="mw-heading mw-heading4"><h4 id="Surchauffe_des_Skylake_et_Kaby_Lake">Surchauffe des Skylake et Kaby Lake</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=8" title="Modifier la section : Surchauffe des Skylake et Kaby Lake" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=8" title="Modifier le code source de la section : Surchauffe des Skylake et Kaby Lake"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Après beaucoup de messages d'utilisateurs mécontents sur le forum Intel, la marque a confirmé des problèmes de surchauffe sur certains i7 7700K. Il est déconseillé, dans le même communiqué, de surcadencer son processeur<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup>. Le souci serait en partie dû à la pâte thermique utilisée entre le die et l'IHS qui serait de qualité moyenne, notamment sur les modèles de <abbr class="abbr" title="Sixième">6<sup>e</sup></abbr> et <abbr class="abbr" title="Septième">7<sup>e</sup></abbr> génération. </p> <div class="mw-heading mw-heading2"><h2 id="La_gamme_pour_PC_de_Bureau">La gamme pour PC de Bureau</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=9" title="Modifier la section : La gamme pour PC de Bureau" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=9" title="Modifier le code source de la section : La gamme pour PC de Bureau"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Westmere_'Gulftown'"><span id="Westmere_.27Gulftown.27"></span>Westmere 'Gulftown'</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=10" title="Modifier la section : Westmere 'Gulftown'" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=10" title="Modifier le code source de la section : Westmere 'Gulftown'"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css loupe">Article connexe : <a href="/wiki/Gulftown" title="Gulftown">Gulftown</a>.</div></div> <p>Pressenti pour être nommé <a href="/wiki/Intel_Core_i9" title="Intel Core i9">Core i9</a><sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup>, le premier processeur sextuple-cœur conçu par Intel pour le grand public est finalement commercialisé sous le nom de Core i7 980X<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup>. C'est le premier de la gamme à appartenir à la famille <a href="/wiki/Westmere" title="Westmere">Westmere</a> et donc à être gravé en <a href="/wiki/32_nm" title="32 nm">32 nm</a>. </p> <table class="wikitable centre"> <tbody><tr> <th rowspan="2">Modèle</th> <th rowspan="2">Cœurs</th> <th rowspan="2"><a href="/wiki/Thread_(informatique)" title="Thread (informatique)">Threads</a></th> <th rowspan="2">Fréquence</th> <th rowspan="2">Turbo Boost<sup id="cite_ref-turboboost_10-0" class="reference"><a href="#cite_note-turboboost-10"><span class="cite-bracket">[</span>note 1<span class="cite-bracket">]</span></a></sup></th> <th colspan="3" style="text-align:center;">Cache</th> <th rowspan="2">Mult.</th> <th rowspan="2">Tension</th> <th rowspan="2">Révision</th> <th rowspan="2"><a href="/wiki/Enveloppe_thermique" title="Enveloppe thermique">TDP</a></th> <th rowspan="2">bus</th> <th rowspan="2"><a href="/wiki/Socket_(processeur)" title="Socket (processeur)"> Socket</a></th> <th rowspan="2">Référence</th> <th colspan="3" style="text-align:center;">Commercialisation </th></tr> <tr> <th width="70">L1</th> <th width="70">L2</th> <th width="70">L3</th> <th>Début</th> <th>Fin </th></tr> <tr align="center"> <td align="left" colspan="17" style="background:#444E50;color: white"><b>Core i7 900 Extreme Edition</b> </td></tr> <tr align="center"> <td align="left">990X</td> <td>6</td> <td>12</td> <td>3,46 GHz</td> <td>3,60 (1) - 3,60 (1) - 3,60 (1) - 3,60 (1) - 3,73 (2) - 3,73 (2)</td> <td>6 × 64 Kio</td> <td>6 × 256 Kio</td> <td>12 Mio</td> <td>26</td> <td></td> <td>D0</td> <td>130 W</td> <td><a href="/wiki/QuickPath_Interconnect" title="QuickPath Interconnect">QPI</a> 6,4 GT/s + 3×DDR3 1,333 GT/s</td> <td><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></td> <td><small></small></td> <td>01 jan 2011</td> <td> </td></tr> <tr align="center"> <td align="left">980X</td> <td>6</td> <td>12</td> <td>3,33 GHz</td> <td>3,46 (1) - 3,46 (1) - 3,46 (1) - 3,46 (1) - 3,60 (2) - 3,60 (2)</td> <td>6 × 64 Kio</td> <td>6 × 256 Kio</td> <td>12 Mio</td> <td>25</td> <td></td> <td>D0</td> <td>130 W</td> <td><a href="/wiki/QuickPath_Interconnect" title="QuickPath Interconnect">QPI</a> 6,4 GT/s + 3×DDR3 1,333 GT/s</td> <td><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></td> <td><small></small></td> <td><time class="nowrap" datetime="2010-03-11" data-sort-value="2010-03-11">11 mars 2010</time></td> <td> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 900</b> </td></tr> <tr align="center"> <td align="left">970</td> <td>6</td> <td>12</td> <td>3,20 GHz</td> <td>3,33 (1) - 3,33 (1) - 3,33 (1) - 3,33 (1) - 3,46 (2) - 3,46 (2)</td> <td>6 × 64 Kio</td> <td>6 × 256 Kio</td> <td>12 Mio</td> <td>24</td> <td></td> <td></td> <td>130 W</td> <td>QPI 4,8 GT/s + 3×DDR3 1,333 GT/s</td> <td>LGA 1366</td> <td><small></small></td> <td><time class="nowrap" datetime="2010-07" data-sort-value="2010-07">juillet 2010</time><sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup></td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Nehalem_'Bloomfield'"><span id="Nehalem_.27Bloomfield.27"></span>Nehalem 'Bloomfield'</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=11" title="Modifier la section : Nehalem 'Bloomfield'" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=11" title="Modifier le code source de la section : Nehalem 'Bloomfield'"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css loupe">Article connexe : <a href="/wiki/Bloomfield_(microprocesseur)" title="Bloomfield (microprocesseur)">Bloomfield (microprocesseur)</a>.</div></div> <p>La gamme Core i7 9xx correspond au segment très haut de gamme en dehors du Gulftown. La révision D0 est apparue à la suite de la commercialisation du Core i7 975 XE et a entrainé une légère refonte de la gamme : les Core i7 940 et 965 XE ont respectivement été remplacés par les modèles 950 et 975 XE tandis que le 920 a lui aussi bénéficié de cette nouvelle révision. Ce dernier est toutefois remplacé par le i7 930 à partir de <time class="nowrap" datetime="2010-01" data-sort-value="2010-01">janvier 2010</time>. </p> <div class="mw-heading mw-heading4"><h4 id="Révision_D0"><span id="R.C3.A9vision_D0"></span>Révision D0</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=12" title="Modifier la section : Révision D0" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=12" title="Modifier le code source de la section : Révision D0"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>La première révision des Bloomfield Core i7 a été introduite à la suite de la commercialisation du Core i7 975. Bien que Intel n'ait pas communiqué sur les évolutions de ce stepping, on peut noter une légère amélioration des performances par rapport aux révisions C0. La consommation en charge diminue légèrement et permet une meilleure stabilité du processeur pour l'overclocking, ainsi le 975 XE peut aisément atteindre les 4 GHz contrairement au 965 XE qui reste en dessous<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup>. </p> <div class="mw-heading mw-heading4"><h4 id="Liste_des_processeurs">Liste des processeurs</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=13" title="Modifier la section : Liste des processeurs" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=13" title="Modifier le code source de la section : Liste des processeurs"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable centre"> <tbody><tr> <th rowspan="2">Modèle</th> <th rowspan="2">Cœurs</th> <th rowspan="2">Threads</th> <th rowspan="2">Fréquence</th> <th rowspan="2">Turbo Boost<sup id="cite_ref-turboboost_10-1" class="reference"><a href="#cite_note-turboboost-10"><span class="cite-bracket">[</span>note 1<span class="cite-bracket">]</span></a></sup></th> <th colspan="3" style="text-align:center;">Cache</th> <th rowspan="2">Mult.</th> <th rowspan="2">Tension</th> <th rowspan="2">Révision</th> <th rowspan="2"><a href="/wiki/Enveloppe_thermique" title="Enveloppe thermique">TDP</a></th> <th rowspan="2">bus</th> <th rowspan="2"><a href="/wiki/Socket_(processeur)" title="Socket (processeur)"> Socket</a></th> <th rowspan="2">Référence</th> <th colspan="3" style="text-align:center;">Commercialisation </th></tr> <tr> <th width="70">L1</th> <th width="70">L2</th> <th width="70">L3</th> <th>Début</th> <th>Fin </th></tr> <tr align="center"> <td align="left" colspan="17" style="background:#444E50;color: white"><b>Core i7 900 Extreme Edition</b> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=37153">975 XE</a></td> <td>4</td> <td>8</td> <td>3,33 GHz</td> <td>3,46 (1) - 3,46 (1) - 3,46 (1) - 3,60 (2)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>×25</td> <td>0,8 - 1,375 V</td> <td>D0</td> <td>130 W</td> <td rowspan="2"><a href="/wiki/QPI" class="mw-redirect" title="QPI">QPI</a> 6,4 GT/s + 3×DDR3 1,333 GT/s</td> <td><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></td> <td><small>AT80601002274AA</small></td> <td><time class="nowrap" datetime="2009-06-02" data-sort-value="2009-06-02">2 juin 2009</time></td> <td><time class="nowrap" datetime="2011-02-18" data-sort-value="2011-02-18">18 février 2011</time> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=37149">965 XE</a></td> <td>4</td> <td>8</td> <td>3,20 GHz</td> <td>3,33 (1) - 3,33 (1) - 3,33 (1) - 3,46 (2)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>×24</td> <td>0,8 - 1,375 V</td> <td>C0</td> <td>130 W</td> <td><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></td> <td><small>AT80601000921AA</small></td> <td><time class="nowrap" datetime="2008-11-17" data-sort-value="2008-11-17">17 novembre 2008</time></td> <td><time class="nowrap" datetime="2009-09-04" data-sort-value="2009-09-04">4 septembre 2009</time> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 900</b> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=37151">960</a></td> <td>4</td> <td>8</td> <td>3,20 GHz</td> <td>3,33 (1) - 3,33 (1) - 3,33 (1) - 3,46 (2)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>×24</td> <td>0,8 - 1,375 V</td> <td>D0</td> <td>130 W</td> <td rowspan="5">QPI 4,8 GT/s + 3×DDR3 1,066 GT/s</td> <td><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></td> <td><small>AT80601002112AA</small></td> <td><time class="nowrap" datetime="2009-10-20" data-sort-value="2009-10-20">20 octobre 2009</time></td> <td> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=37150">950</a></td> <td>4</td> <td>8</td> <td>3,06 GHz</td> <td>3,20 (1) - 3,20 (1) - 3,20 (1) - 3,33 (2)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>×23</td> <td>0,8 - 1,375 V</td> <td>D0</td> <td>130 W</td> <td><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></td> <td><small>AT80601002112AA</small></td> <td><time class="nowrap" datetime="2009-06-02" data-sort-value="2009-06-02">2 juin 2009</time></td> <td> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=37148">940</a></td> <td>4</td> <td>8</td> <td>2,93 GHz</td> <td>3,06 (1) - 3,06 (1) - 3,06 (1) - 3,20 (2)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>×22</td> <td>0,8 - 1,375 V</td> <td>C0</td> <td>130 W</td> <td><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></td> <td><small>AT80601000918AA</small></td> <td><time class="nowrap" datetime="2008-11-17" data-sort-value="2008-11-17">17 novembre 2008</time></td> <td><time class="nowrap" datetime="2009-09-04" data-sort-value="2009-09-04">4 septembre 2009</time> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=41447">930</a></td> <td>4</td> <td>8</td> <td>2,80 GHz</td> <td>2,93 (1) - 2,93 (1) - 2,93 (1) - 3,06 (2)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>×21</td> <td>0,8 - 1,375 V</td> <td>D0</td> <td>130 W</td> <td><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></td> <td><small>AT80601000897AA</small></td> <td><time class="nowrap" datetime="2010-03-01" data-sort-value="2010-03-01"><abbr class="abbr" title="premier">1<sup>er</sup></abbr> mars 2010</time></td> <td> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=37147">920</a></td> <td>4</td> <td>8</td> <td>2,66 GHz</td> <td>2,80 (1) - 2,80 (1) - 2,80 (1) - 2,93 (2)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>×20</td> <td>0,8 - 1,375 V</td> <td>C0 - D0</td> <td>130 W</td> <td><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></td> <td><small>AT80601000741AA</small></td> <td><time class="nowrap" datetime="2008-11-17" data-sort-value="2008-11-17">17 novembre 2008</time></td> <td><time class="nowrap" datetime="2010-09-24" data-sort-value="2010-09-24">24 septembre 2010</time> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Nehalem_'Lynnfield'"><span id="Nehalem_.27Lynnfield.27"></span>Nehalem 'Lynnfield'</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=14" title="Modifier la section : Nehalem 'Lynnfield'" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=14" title="Modifier le code source de la section : Nehalem 'Lynnfield'"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css loupe">Article connexe : <a href="/wiki/Lynnfield" title="Lynnfield">Lynnfield</a>.</div></div> <p>Déclinaison supérieure de la gamme <a href="/wiki/Intel_Core_i5#Lynnfield" title="Intel Core i5">Core i5 Lynnfield</a>, le Core i7 Lynnfield se présente comme une déclinaison abordable du haut de gamme grâce entre autres à son socket LGA1156. Bénéficiant d'un TDP inférieur au Bloomfield, il se distingue aussi par un Turbo Boost plus généreux (jusqu'à 5 bins) mais reste cantonné à des fréquences initiales inférieures. </p> <table class="wikitable centre"> <tbody><tr> <th rowspan="2">Modèle</th> <th rowspan="2">Cœurs</th> <th rowspan="2">Threads</th> <th rowspan="2">Fréquence</th> <th rowspan="2">Turbo Boost<sup id="cite_ref-turboboost_10-2" class="reference"><a href="#cite_note-turboboost-10"><span class="cite-bracket">[</span>note 1<span class="cite-bracket">]</span></a></sup></th> <th colspan="3" style="text-align:center;">Cache</th> <th rowspan="2">Mult.</th> <th rowspan="2">Tension</th> <th rowspan="2">Révision</th> <th rowspan="2"><a href="/wiki/Enveloppe_thermique" title="Enveloppe thermique">TDP</a></th> <th rowspan="2">bus</th> <th rowspan="2">Socket</th> <th rowspan="2">Référence</th> <th colspan="3" style="text-align:center;">Commercialisation </th></tr> <tr> <th width="70">L1</th> <th width="70">L2</th> <th width="70">L3</th> <th>Début</th> <th>Fin </th></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 800K</b> </td></tr> <tr align="center"> <td align="left">875K</td> <td>4</td> <td>8</td> <td>2,93 GHz</td> <td>3,20 (2) - 3,20 (2) - 3,46 (4) - 3,60 (5)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>22+</td> <td></td> <td>B1</td> <td>95 W</td> <td><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2,5 GT/s + 2×DDR3 + 16×PCI-express 2.0</td> <td><a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a></td> <td><small></small></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 800</b> </td></tr> <tr align="center"> <td align="left">880</td> <td>4</td> <td>8</td> <td>3,06 GHz</td> <td>3,33 (2) - 3,33 (2) - 3,60 (4) - 3,73 (5)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>23</td> <td></td> <td>B1</td> <td>95 W</td> <td rowspan="3"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2,5 GT/s + 2×DDR3 + 16×PCI-express 2.0</td> <td><a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a></td> <td><small></small></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=41315">870</a></td> <td>4</td> <td>8</td> <td>2,93 GHz</td> <td>3,20 (2) - 3,20 (2) - 3,46 (4) - 3,60 (5)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>22</td> <td></td> <td>B1</td> <td>95 W</td> <td><a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a></td> <td><small>BV80605001905AI </small></td> <td><time class="nowrap" datetime="2009-09-09" data-sort-value="2009-09-09">9 septembre 2009</time></td> <td> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=41316">860</a></td> <td>4</td> <td>8</td> <td>2,80 GHz</td> <td>2,93 (1) - 2,93 (1) - 3,33 (4) - 3,46 (5)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>21</td> <td></td> <td>B1</td> <td>95 W</td> <td>LGA 1156</td> <td><small>BV80605001908AK </small></td> <td><time class="nowrap" datetime="2009-09-09" data-sort-value="2009-09-09">9 septembre 2009</time></td> <td><time class="nowrap" datetime="2010-08-01" data-sort-value="2010-08-01"><abbr class="abbr" title="premier">1<sup>er</sup></abbr> août 2010</time> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 800S</b> </td></tr> <tr align="center"> <td align="left">870S</td> <td>4</td> <td>8</td> <td>2,66 GHz</td> <td>2,80 (1) - 2,80 (1) - 3,20 (4) - 3,20 (4)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>20</td> <td></td> <td>B1</td> <td>82 W</td> <td rowspan="2"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2,5 GT/s + 2×DDR3 + 16×PCI-express 2.0</td> <td><a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a></td> <td><small></small></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left">860S</td> <td>4</td> <td>8</td> <td>2,53 GHz</td> <td>2,53 (0) - 2,53 (0) - 3,33 (6) - 3,46 (7)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>19</td> <td></td> <td>B1</td> <td>82 W</td> <td>LGA 1156</td> <td><small></small></td> <td><abbr class="abbr" title="Premier">1<sup>er</sup></abbr> trim. 2010<sup id="cite_ref-pcinpact-210709_13-0" class="reference"><a href="#cite_note-pcinpact-210709-13"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup></td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Sandy_Bridge">Sandy Bridge</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=15" title="Modifier la section : Sandy Bridge" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=15" title="Modifier le code source de la section : Sandy Bridge"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css loupe">Article détaillé : <a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a>.</div></div> <p>Note : les IGP marqués d'une étoile (*) sont des modèles HD 2000, les IGP marqués de deux étoiles (**) sont des modèles HD 3000. </p> <table class="wikitable centre"> <tbody><tr> <th rowspan="2">Modèle</th> <th rowspan="2" style="text-align:center;">Cœurs (threads)</th> <th colspan="3">Fréquence</th> <th colspan="3" style="text-align:center;">Cache</th> <th rowspan="2">Mult.</th> <th rowspan="2">Tension</th> <th rowspan="2">Révision<br />(Sspec)</th> <th rowspan="2"><a href="/wiki/Enveloppe_thermique" title="Enveloppe thermique">TDP</a></th> <th rowspan="2">bus</th> <th rowspan="2">Socket</th> <th rowspan="2">Référence</th> <th colspan="3" style="text-align:center;">Commercialisation </th></tr> <tr> <th>Cœurs</th> <th>Turbo</th> <th>IGP</th> <th>L1</th> <th>L2</th> <th>L3</th> <th>Début</th> <th>Fin </th></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 2000K</b> </td></tr> <tr align="center"> <td align="left">2600K<sup id="cite_ref-modelK_14-0" class="reference"><a href="#cite_note-modelK-14"><span class="cite-bracket">[</span>note 2<span class="cite-bracket">]</span></a></sup></td> <td>4 (8)</td> <td>3,4 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>3,8 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>850 <abbr class="abbr" title="mégahertz">MHz</abbr><br />(1,35 <abbr class="abbr" title="gigahertz">GHz</abbr>)**</td> <td>4 × 64 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>4 × 256 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>8 <abbr class="abbr" title="million">Mio</abbr></td> <td>×34</td> <td></td> <td>D2 (SR00C)</td> <td>95 W</td> <td rowspan="2">2×DDR3 + DMI 20 Gbit/s + FDI + 16×PCI-express 2.0</td> <td><a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a></td> <td><small>CM8062300833908<br />BX80623I72600K</small></td> <td>T1 2011</td> <td><time class="nowrap date-lien" datetime="2013-03-29" data-sort-value="2013-03-29"><a href="/wiki/29_mars" title="29 mars">29</a> <a href="/wiki/Mars_2013" title="Mars 2013">mars</a> <a href="/wiki/2013_en_informatique" title="2013 en informatique">2013</a></time><sup id="cite_ref-THFR_26092012_15-0" class="reference"><a href="#cite_note-THFR_26092012-15"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </td></tr> <tr align="center"> <td align="left">2700K<sup id="cite_ref-modelK_14-1" class="reference"><a href="#cite_note-modelK-14"><span class="cite-bracket">[</span>note 2<span class="cite-bracket">]</span></a></sup></td> <td>4 (8)</td> <td>3,5 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>3,9 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>850 <abbr class="abbr" title="mégahertz">MHz</abbr><br />(1,35 <abbr class="abbr" title="gigahertz">GHz</abbr>)**</td> <td>4 × 64 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>4 × 256 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>8 <abbr class="abbr" title="million">Mio</abbr></td> <td>×35</td> <td></td> <td>D2 (SR0DG)</td> <td>95 W</td> <td>LGA 1155</td> <td><small>CM8062301124100<br />BX80623I72700K</small></td> <td><time class="nowrap date-lien" datetime="2011-10" data-sort-value="2011-10"><a href="/wiki/Octobre_2011" title="Octobre 2011">octobre</a> <a href="/wiki/2011_en_informatique" title="2011 en informatique">2011</a></time></td> <td><time class="nowrap date-lien" datetime="2013-03-29" data-sort-value="2013-03-29"><a href="/wiki/29_mars" title="29 mars">29</a> <a href="/wiki/Mars_2013" title="Mars 2013">mars</a> <a href="/wiki/2013_en_informatique" title="2013 en informatique">2013</a></time><sup id="cite_ref-THFR_26092012_15-1" class="reference"><a href="#cite_note-THFR_26092012-15"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 2000</b> </td></tr> <tr align="center"> <td align="left">2600</td> <td>4 (8)</td> <td>3,4 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>3,8 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>850 <abbr class="abbr" title="mégahertz">MHz</abbr><br />(1,35 <abbr class="abbr" title="gigahertz">GHz</abbr>)*</td> <td>4 × 64 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>4 × 256 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>8 <abbr class="abbr" title="million">Mio</abbr></td> <td>×34</td> <td></td> <td>D2 (SR00B)</td> <td>95 W</td> <td rowspan="1">2×DDR3 + DMI 20 Gbit/s + FDI + 16×PCI-express 2.0</td> <td>LGA 1155</td> <td><small>CM8062300834302<br />BX80623I72600</small></td> <td><time class="nowrap date-lien" datetime="2011-01-05" data-sort-value="2011-01-05"><a href="/wiki/5_janvier" title="5 janvier">5</a> <a href="/wiki/Janvier_2011" title="Janvier 2011">janvier</a> <a href="/wiki/2011_en_informatique" title="2011 en informatique">2011</a></time></td> <td><time class="nowrap date-lien" datetime="2013-03-29" data-sort-value="2013-03-29"><a href="/wiki/29_mars" title="29 mars">29</a> <a href="/wiki/Mars_2013" title="Mars 2013">mars</a> <a href="/wiki/2013_en_informatique" title="2013 en informatique">2013</a></time><sup id="cite_ref-THFR_26092012_15-2" class="reference"><a href="#cite_note-THFR_26092012-15"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 2000S</b> </td></tr> <tr align="center"> <td align="left">2600S</td> <td>4 (8)</td> <td>2,8 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>3,8 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>850 <abbr class="abbr" title="mégahertz">MHz</abbr><br />(1,35 <abbr class="abbr" title="gigahertz">GHz</abbr>)*</td> <td>4 × 64 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>4 × 256 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>8 <abbr class="abbr" title="million">Mio</abbr></td> <td>×28</td> <td></td> <td>D2 (SR00E)</td> <td>65 W</td> <td rowspan="1">2×DDR3 + DMI 20 Gbit/s + FDI + 16×PCI-express 2.0</td> <td>LGA 1155</td> <td><small>CM8062300835604<br />BX80623I72600S</small></td> <td>T1 2011</td> <td><time class="nowrap date-lien" datetime="2013-03-29" data-sort-value="2013-03-29"><a href="/wiki/29_mars" title="29 mars">29</a> <a href="/wiki/Mars_2013" title="Mars 2013">mars</a> <a href="/wiki/2013_en_informatique" title="2013 en informatique">2013</a></time><sup id="cite_ref-THFR_26092012_15-3" class="reference"><a href="#cite_note-THFR_26092012-15"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 3000</b> </td></tr> <tr align="center"> <td align="left">3820</td> <td>4 (8)</td> <td>3,6 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>3,8 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>-</td> <td>4 × 64 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>4 × 256 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>10 <abbr class="abbr" title="million">Mio</abbr></td> <td>×36</td> <td>0,6 <abbr class="abbr" title="volt">V</abbr> – 1,35 <abbr class="abbr" title="volt">V</abbr></td> <td>M1 (SR0LD)</td> <td>130 W</td> <td rowspan="1">4×DDR3 + DMI 20 Gbit/s + 40×PCI-express 2.0</td> <td><a href="/wiki/LGA_2011" title="LGA 2011">LGA 2011</a></td> <td><small>CM8061901049606<br />BX80619I73820</small></td> <td>T1 2012</td> <td> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 3000K</b> </td></tr> <tr align="center"> <td align="left">3930K<sup id="cite_ref-modelK_14-2" class="reference"><a href="#cite_note-modelK-14"><span class="cite-bracket">[</span>note 2<span class="cite-bracket">]</span></a></sup></td> <td>6 (12)</td> <td>3,2 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>3,8 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>-</td> <td>6 × 64 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>6 × 256 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>12 <abbr class="abbr" title="million">Mio</abbr></td> <td>×32</td> <td>0,6 <abbr class="abbr" title="volt">V</abbr> – 1,35 <abbr class="abbr" title="volt">V</abbr></td> <td>C1<sup id="cite_ref-revC1_VTd_16-0" class="reference"><a href="#cite_note-revC1_VTd-16"><span class="cite-bracket">[</span>note 3<span class="cite-bracket">]</span></a></sup> (SR0H9)<br />C2 (SR0KY)</td> <td>130 W</td> <td rowspan="1">4×DDR3 + DMI 20 Gbit/s + 40×PCI-express 2.0</td> <td>LGA 2011</td> <td><small>CM8061901100802<br />BX80619I73930K</small></td> <td><time class="nowrap date-lien" datetime="2011-11-14" data-sort-value="2011-11-14"><a href="/wiki/14_novembre" title="14 novembre">14</a> <a href="/wiki/Novembre_2011" title="Novembre 2011">novembre</a> <a href="/wiki/2011_en_informatique" title="2011 en informatique">2011</a></time></td> <td> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 3000X</b> </td></tr> <tr align="center"> <td align="left">3960X<sup id="cite_ref-modelK_14-3" class="reference"><a href="#cite_note-modelK-14"><span class="cite-bracket">[</span>note 2<span class="cite-bracket">]</span></a></sup></td> <td>6 (12)</td> <td>3,3 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>3,9 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>-</td> <td>6 × 64 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>6 × 256 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>15 <abbr class="abbr" title="million">Mio</abbr></td> <td>×33</td> <td>0,6 <abbr class="abbr" title="volt">V</abbr> – 1,35 <abbr class="abbr" title="volt">V</abbr></td> <td>C1<sup id="cite_ref-revC1_VTd_16-1" class="reference"><a href="#cite_note-revC1_VTd-16"><span class="cite-bracket">[</span>note 3<span class="cite-bracket">]</span></a></sup> (SR0GW)<br />C2 (SR0KF)</td> <td>130 W</td> <td rowspan="2">4×DDR3 + DMI 20 Gbit/s + 40×PCI-express 2.0</td> <td>LGA 2011</td> <td><small>CM8061907184018<br />BX80619I73960X</small></td> <td><time class="nowrap date-lien" datetime="2011-11-14" data-sort-value="2011-11-14"><a href="/wiki/14_novembre" title="14 novembre">14</a> <a href="/wiki/Novembre_2011" title="Novembre 2011">novembre</a> <a href="/wiki/2011_en_informatique" title="2011 en informatique">2011</a></time></td> <td> </td></tr> <tr align="center"> <td align="left">3970X<sup id="cite_ref-modelK_14-4" class="reference"><a href="#cite_note-modelK-14"><span class="cite-bracket">[</span>note 2<span class="cite-bracket">]</span></a></sup></td> <td>6 (12)</td> <td>3,5 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>4 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>-</td> <td>6 × 64 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>6 × 256 <abbr class="abbr" title="kibioctet">Kio</abbr></td> <td>15 <abbr class="abbr" title="million">Mio</abbr></td> <td>×35</td> <td>0,6 <abbr class="abbr" title="volt">V</abbr> – 1,35 <abbr class="abbr" title="volt">V</abbr></td> <td>C2 (SR0WR)</td> <td>150 W</td> <td>LGA 2011</td> <td><small>CM8061901281201<br />BX80619I73970X</small></td> <td>T4 2012</td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Ivy_Bridge">Ivy Bridge</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=16" title="Modifier la section : Ivy Bridge" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=16" title="Modifier le code source de la section : Ivy Bridge"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Gravés en 22 <abbr class="abbr" title="nanomètre">nm</abbr> et 32 <abbr class="abbr" title="nanomètre">nm</abbr>, les processeurs Core i7 Ivy Bridge embarquent un IGP HD Graphics 4000. </p> <table class="wikitable centre"> <tbody><tr> <th rowspan="2">Modèle</th> <th rowspan="2" style="text-align:center;">Cœurs (threads)</th> <th colspan="3">Fréquence</th> <th colspan="3" style="text-align:center;">Cache</th> <th rowspan="2">Mult.</th> <th rowspan="2">Tension</th> <th rowspan="2">Révision (Sspec)</th> <th rowspan="2" width="35"><a href="/wiki/Enveloppe_thermique" title="Enveloppe thermique">TDP</a></th> <th rowspan="2">bus</th> <th rowspan="2">Socket</th> <th rowspan="2">Référence</th> <th colspan="3" style="text-align:center;">Commercialisation </th></tr> <tr> <th>Cœurs</th> <th>Turbo</th> <th width="65">IGP</th> <th width="55">L1</th> <th width="55">L2</th> <th>L3</th> <th>Début</th> <th>Fin </th></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 3700</b> </td></tr> <tr align="center"> <td align="left">3770K</td> <td>4 (8)</td> <td>3,5 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>3,9 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>650 MHz<br />(1,15 GHz)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 <abbr class="abbr" title="mégaoctet">Mo</abbr></td> <td>×35</td> <td></td> <td>E1 (SR0PL)</td> <td>77 W</td> <td rowspan="4">2×DDR3 + DMI + FDI + 16×PCI-express 3.0</td> <td>LGA 1155</td> <td><small>CM8063701211700<br />BX80637I73770K</small></td> <td><time class="nowrap" datetime="2012-04-29" data-sort-value="2012-04-29">29 avril 2012</time><sup id="cite_ref-THFR_1_17-0" class="reference"><a href="#cite_note-THFR_1-17"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></td> <td> </td></tr> <tr align="center"> <td align="left">3770T</td> <td>4 (8)</td> <td>2,5 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>3,7 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>650 MHz<br />(1,15 GHz)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 <abbr class="abbr" title="mégaoctet">Mo</abbr></td> <td>×25</td> <td></td> <td>E1 (SR0PQ)</td> <td>45 W</td> <td>LGA 1155</td> <td><small>CM8063701212200</small></td> <td><time class="nowrap" datetime="2012-04-29" data-sort-value="2012-04-29">29 avril 2012</time><sup id="cite_ref-THFR_1_17-1" class="reference"><a href="#cite_note-THFR_1-17"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></td> <td> </td></tr> <tr align="center"> <td align="left">3770S</td> <td>4 (8)</td> <td>3,1 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>3,9 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>650 MHz<br />(1,15 GHz)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 <abbr class="abbr" title="mégaoctet">Mo</abbr></td> <td>×31</td> <td></td> <td>E1 (SR0PN)</td> <td>65 W</td> <td>LGA 1155</td> <td><small>CM8063701211900<br />BX80637I73770S</small></td> <td><time class="nowrap" datetime="2012-04-29" data-sort-value="2012-04-29">29 avril 2012</time><sup id="cite_ref-THFR_1_17-2" class="reference"><a href="#cite_note-THFR_1-17"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></td> <td> </td></tr> <tr align="center"> <td align="left">3770</td> <td>4 (8)</td> <td>3,4 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>3,9 <abbr class="abbr" title="gigahertz">GHz</abbr></td> <td>650 MHz<br />(1,15 GHz)</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 <abbr class="abbr" title="mégaoctet">Mo</abbr></td> <td>×34</td> <td></td> <td>E1 (SR0PK)</td> <td>77 W</td> <td>LGA 1155</td> <td><small>CM8063701211600<br />BX80637I73770</small></td> <td><time class="nowrap" datetime="2012-04-29" data-sort-value="2012-04-29">29 avril 2012</time><sup id="cite_ref-THFR_1_17-3" class="reference"><a href="#cite_note-THFR_1-17"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Haswell">Haswell</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=17" title="Modifier la section : Haswell" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=17" title="Modifier le code source de la section : Haswell"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Cette gamme de processeurs gravés en <a href="/wiki/22_nm" title="22 nm">22 nm</a> et <a href="/wiki/14_nm" title="14 nm">14 nm</a> (sortis en 2013) embarquent un IGP HD Graphics 4600 </p> <div class="mw-heading mw-heading3"><h3 id="Skylake">Skylake</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=18" title="Modifier la section : Skylake" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=18" title="Modifier le code source de la section : Skylake"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Sorti en 2015. </p> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css loupe">Article détaillé : <a href="/wiki/Skylake" title="Skylake">Skylake</a>.</div></div> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake">Kaby Lake</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=19" title="Modifier la section : Kaby Lake" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=19" title="Modifier le code source de la section : Kaby Lake"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Sorti en <time class="nowrap" datetime="2016-09" data-sort-value="2016-09">septembre 2016</time>. </p> <div class="mw-heading mw-heading4"><h4 id="Coffee_Lake">Coffee Lake</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=20" title="Modifier la section : Coffee Lake" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=20" title="Modifier le code source de la section : Coffee Lake"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>sorti en <time class="nowrap" datetime="2017-09" data-sort-value="2017-09">septembre 2017</time>. </p> <div class="mw-heading mw-heading2"><h2 id="La_gamme_pour_PC_portables">La gamme pour PC portables</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=21" title="Modifier la section : La gamme pour PC portables" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=21" title="Modifier le code source de la section : La gamme pour PC portables"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>La gamme pour PC portables, initiée avec les cœurs Clarksfield, ne fait plus partie de la gamme <a href="/wiki/Centrino" title="Centrino">Centrino</a> qui disparait en 2009. </p> <div class="mw-heading mw-heading3"><h3 id="Clarksfield">Clarksfield</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=22" title="Modifier la section : Clarksfield" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=22" title="Modifier le code source de la section : Clarksfield"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css loupe">Article détaillé : <a href="/wiki/Clarksfield" title="Clarksfield">Clarksfield</a>.</div></div> <table class="wikitable centre"> <tbody><tr> <th rowspan="2">Modèle</th> <th rowspan="2">Cœurs</th> <th rowspan="2">Threads</th> <th rowspan="2">Fréquence</th> <th rowspan="2">Turbo Boost<sup id="cite_ref-turboboost_10-3" class="reference"><a href="#cite_note-turboboost-10"><span class="cite-bracket">[</span>note 1<span class="cite-bracket">]</span></a></sup></th> <th colspan="3" style="text-align:center;">Cache</th> <th rowspan="2">Mult.</th> <th rowspan="2">Tension</th> <th rowspan="2">Révision</th> <th rowspan="2"><a href="/wiki/Enveloppe_thermique" title="Enveloppe thermique">TDP</a></th> <th rowspan="2">bus</th> <th rowspan="2">Socket</th> <th rowspan="2">Référence</th> <th colspan="3" style="text-align:center;">Commercialisation </th></tr> <tr> <th width="70">L1</th> <th width="70">L2</th> <th width="70">L3</th> <th>Début</th> <th>Fin </th></tr> <tr align="center"> <td align="left" colspan="17" style="background:#444E50;color: white"><b>Core i7 900XM Extreme Edition</b> </td></tr> <tr align="center"> <td align="left">940XM</td> <td>4</td> <td>8</td> <td>2,13 GHz</td> <td>2,40 (2) - 2,40 (2) - 3.20 (8) - 3,33 (9)</td> <td>4 × 32 kio</td> <td>4 × 256 kio</td> <td>8 Mio</td> <td>16</td> <td></td> <td>B1</td> <td>55 W</td> <td rowspan="2"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2,5 GT/s + 2×DDR3 + 16×PCI-express 2.0</td> <td>PGA 988</td> <td></td> <td> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=43126">920XM</a></td> <td>4</td> <td>8</td> <td>2,00 GHz</td> <td>2,26 (2) - 2,26 (2) - 3.06 (8) - 3,20 (9)</td> <td>4 × 32 kio</td> <td>4 × 256 kio</td> <td>8 Mio</td> <td>15</td> <td></td> <td>B1</td> <td>55 W</td> <td>PGA 988</td> <td><small>BY80607002529AF</small></td> <td><time class="nowrap" datetime="2009-09-23" data-sort-value="2009-09-23">23 septembre 2009</time><sup id="cite_ref-pcinpact-130809_18-0" class="reference"><a href="#cite_note-pcinpact-130809-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 800QM</b> </td></tr> <tr align="center"> <td align="left">840QM</td> <td>4</td> <td>8</td> <td>1,86 GHz</td> <td>2,13 (2) - 2,13 (2) - 2,93 (8) - 3,20 (10)</td> <td>4 × 32 kio</td> <td>4 × 256 kio</td> <td>8 Mio</td> <td>14</td> <td></td> <td>B1</td> <td>45 W</td> <td rowspan="2">DMI 2,5 GT/s + 2×DDR3 + 16×PCI-express 2.0</td> <td>PGA 988</td> <td></td> <td> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=43124">820QM</a></td> <td>4</td> <td>8</td> <td>1,73 GHz</td> <td>2,00 (2) - 2,00 (2) - 2,80 (8) - 3,06 (10)</td> <td>4 × 32 kio</td> <td>4 × 256 kio</td> <td>8 Mio</td> <td>13</td> <td></td> <td>B1</td> <td>45 W</td> <td>PGA 988</td> <td><small>BY80607002904AK</small></td> <td><time class="nowrap" datetime="2009-09-23" data-sort-value="2009-09-23">23 septembre 2009</time><sup id="cite_ref-pcinpact-130809_18-1" class="reference"><a href="#cite_note-pcinpact-130809-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 700QM</b> </td></tr> <tr align="center"> <td align="left">740QM</td> <td>4</td> <td>8</td> <td>1,73 GHz</td> <td>1,86 (1) - 1,86 (1) - 2,53 (6) - 2,93 (9)</td> <td>4 × 32 kio</td> <td>4 × 256 kio</td> <td>6 Mio</td> <td>13</td> <td></td> <td>B1</td> <td>45 W</td> <td rowspan="2">DMI 2,5 GT/s + 2×DDR3 + 16×PCI-express 2.0</td> <td>PGA 988</td> <td></td> <td> </td></tr> <tr align="center"> <td align="left"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=43122">720QM</a></td> <td>4</td> <td>8</td> <td>1,60 GHz</td> <td>1,73 (1) - 1,73 (1) - 2,40 (6) - 2,80 (9)</td> <td>4 × 32 kio</td> <td>4 × 256 kio</td> <td>6 Mio</td> <td>12</td> <td></td> <td>B1</td> <td>45 W</td> <td>PGA 988</td> <td><small>BX80607I7720QM</small></td> <td><time class="nowrap" datetime="2009-09-23" data-sort-value="2009-09-23">23 septembre 2009</time><sup id="cite_ref-pcinpact-130809_18-2" class="reference"><a href="#cite_note-pcinpact-130809-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Arrandale">Arrandale</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=23" title="Modifier la section : Arrandale" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=23" title="Modifier le code source de la section : Arrandale"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css loupe">Article connexe : <a href="/wiki/Arrandale" title="Arrandale">Arrandale</a>.</div></div> <table class="wikitable centre"> <tbody><tr> <th rowspan="2">Modèle</th> <th rowspan="2">Cœurs (Thread)</th> <th rowspan="2">Fréquence</th> <th rowspan="2">Turbo Boost<sup id="cite_ref-turboboost_10-4" class="reference"><a href="#cite_note-turboboost-10"><span class="cite-bracket">[</span>note 1<span class="cite-bracket">]</span></a></sup></th> <th colspan="3" style="text-align:center;">Cache</th> <th rowspan="2">Mult.</th> <th rowspan="2">Tension</th> <th rowspan="2">Révision</th> <th rowspan="2"><a href="/wiki/Enveloppe_thermique" title="Enveloppe thermique">TDP</a></th> <th rowspan="2">bus</th> <th rowspan="2">Socket</th> <th rowspan="2">Référence</th> <th colspan="3" style="text-align:center;">Commercialisation </th></tr> <tr> <th width="70">L1</th> <th width="70">L2</th> <th width="70">L3</th> <th>Début</th> <th>Fin </th></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 600M</b> </td></tr> <tr align="center"> <td align="left">640M</td> <td>2 (4)</td> <td>2,80 GHz</td> <td>3,20 (3) - 3,46 (5)</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>21</td> <td></td> <td></td> <td>35 W</td> <td rowspan="2"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2,5 GT/s + FDI + 2×DDR3 + 16×PCI-express 2.0</td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left">620M</td> <td>2 (4)</td> <td>2,66 GHz</td> <td>3,06 (3) - 3,33 (5)</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>20</td> <td></td> <td></td> <td>35 W</td> <td></td> <td></td> <td><abbr class="abbr" title="Premier">1<sup>er</sup></abbr> trim. 2010<sup id="cite_ref-tom-220909_19-0" class="reference"><a href="#cite_note-tom-220909-19"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup></td> <td> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 600LM</b> </td></tr> <tr align="center"> <td align="left">660LM</td> <td>2 (4)</td> <td>2,26 GHz</td> <td>2,80 (4) - 3,06 (6)</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>17</td> <td></td> <td></td> <td>25 W</td> <td rowspan="3">DMI 2,5 GT/s + FDI + 2×DDR3 + 16×PCI-express 2.0</td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left">640LM</td> <td>2 (4)</td> <td>2,13 GHz</td> <td>2,66 (4) - 2,93 (6)</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>16</td> <td></td> <td></td> <td>25 W</td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left">620LM</td> <td>2 (4)</td> <td>2,00 GHz</td> <td>2,53 (4) - 2,80 (6)</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>15</td> <td></td> <td></td> <td>25 W</td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 600UM</b> </td></tr> <tr align="center"> <td align="left">680UM</td> <td>2 (4)</td> <td>1,46 GHz</td> <td>2,13 (5) - 2,53 (8)</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>11</td> <td></td> <td></td> <td>18 W</td> <td rowspan="4">DMI 2,5 GT/s + FDI + 2×DDR3 + 16×PCI-express 2.0</td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left">660UM</td> <td>2 (4)</td> <td>1,33 GHz</td> <td>2,00 (5) - 2,40 (8)</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>10</td> <td></td> <td></td> <td>18 W</td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left">640UM</td> <td>2 (4)</td> <td>1,20 GHz</td> <td>1,86 (5) - 2,26 (8)</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>9</td> <td></td> <td></td> <td>18 W</td> <td></td> <td></td> <td><abbr class="abbr" title="Premier">1<sup>er</sup></abbr> trim. 2010<sup id="cite_ref-tom-220909_19-1" class="reference"><a href="#cite_note-tom-220909-19"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup></td> <td> </td></tr> <tr align="center"> <td align="left">620UM</td> <td>2 (4)</td> <td>1,06 GHz</td> <td>1,76 (5) - 2,13 (8)</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>8</td> <td></td> <td></td> <td>18 W</td> <td></td> <td></td> <td><abbr class="abbr" title="Premier">1<sup>er</sup></abbr> trim. 2010<sup id="cite_ref-tom-220909_19-2" class="reference"><a href="#cite_note-tom-220909-19"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup></td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Sandy_Bridge_2">Sandy Bridge</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=24" title="Modifier la section : Sandy Bridge" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=24" title="Modifier le code source de la section : Sandy Bridge"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css loupe">Article détaillé : <a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a>.</div></div> <table class="wikitable centre"> <tbody><tr> <th rowspan="2">Modèle</th> <th rowspan="2">Cœurs (Thread)</th> <th rowspan="2">Fréquence</th> <th rowspan="2">Turbo Boost<sup id="cite_ref-turboboost_10-5" class="reference"><a href="#cite_note-turboboost-10"><span class="cite-bracket">[</span>note 1<span class="cite-bracket">]</span></a></sup></th> <th colspan="3" style="text-align:center;">Cache</th> <th rowspan="2">Mult.</th> <th rowspan="2">Tension</th> <th rowspan="2">Révision</th> <th rowspan="2"><a href="/wiki/Enveloppe_thermique" title="Enveloppe thermique">TDP</a></th> <th rowspan="2">bus</th> <th rowspan="2">Socket</th> <th rowspan="2">Référence</th> <th colspan="3" style="text-align:center;">Commercialisation </th></tr> <tr> <th width="70">L1</th> <th width="70">L2</th> <th width="70">L3</th> <th>Début</th> <th>Fin </th></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 2800QM</b> </td></tr> <tr align="center"> <td align="left">2820QM</td> <td>4 (8)</td> <td>2,30 GHz</td> <td>3,40 GHz</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>8 Mio</td> <td>23</td> <td></td> <td></td> <td>45 W</td> <td></td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 2700QM</b> </td></tr> <tr align="center"> <td align="left">2720QM</td> <td>4 (8)</td> <td>2,20 GHz</td> <td>3,30 GHz</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>6 Mio</td> <td>22</td> <td></td> <td></td> <td>45 W</td> <td></td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 2600QM</b> </td></tr> <tr align="center"> <td align="left">2635QM</td> <td>4 (8)</td> <td>2,00 GHz</td> <td>2,90 GHz</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>6 Mio</td> <td>20</td> <td></td> <td></td> <td>45 W</td> <td></td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left">2630QM</td> <td>4 (8)</td> <td>2,00 GHz</td> <td>2,90 GHz</td> <td>4 × 64 Kio</td> <td>4 × 256 Kio</td> <td>6 Mio</td> <td>20</td> <td></td> <td></td> <td>45 W</td> <td></td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 2600M</b> </td></tr> <tr align="center"> <td align="left">2620M</td> <td>2 (4)</td> <td>2,70 GHz</td> <td>3,40 GHz</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>27</td> <td></td> <td></td> <td>35 W</td> <td></td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 2600M LV</b> </td></tr> <tr align="center"> <td align="left">2649M</td> <td>2 (4)</td> <td>2,30 GHz</td> <td>3,20 GHz</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>23</td> <td></td> <td></td> <td>25 W</td> <td></td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left">2629M</td> <td>2 (4)</td> <td>2,10 GHz</td> <td>3,00 GHz</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>21</td> <td></td> <td></td> <td>25 W</td> <td></td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left" colspan="17" style="background:#127cc1;color: white"><b>Core i7 2600M ULV</b> </td></tr> <tr align="center"> <td align="left">2657M</td> <td>2 (4)</td> <td>1,60 GHz</td> <td>2,70 GHz</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>16</td> <td></td> <td></td> <td>17 W</td> <td></td> <td></td> <td></td> <td></td> <td> </td></tr> <tr align="center"> <td align="left">2617M</td> <td>2 (4)</td> <td>1,50 GHz</td> <td>2,60 GHz</td> <td>2 × 64 Kio</td> <td>2 × 256 Kio</td> <td>4 Mio</td> <td>15</td> <td></td> <td></td> <td>17 W</td> <td></td> <td></td> <td></td> <td></td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Ivy_Bridge_2">Ivy Bridge</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=25" title="Modifier la section : Ivy Bridge" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=25" title="Modifier le code source de la section : Ivy Bridge"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css general">Article principal : <a href="/wiki/Sandy_Bridge#Famille_Ivy_Bridge" title="Sandy Bridge">Sandy Bridge#Famille Ivy Bridge</a>.</div></div> <div class="mw-heading mw-heading3"><h3 id="Haswell_2">Haswell</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=26" title="Modifier la section : Haswell" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=26" title="Modifier le code source de la section : Haswell"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css general">Article principal : <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell (microarchitecture)</a>.</div></div> <div class="mw-heading mw-heading3"><h3 id="Skylake_2">Skylake</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=27" title="Modifier la section : Skylake" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=27" title="Modifier le code source de la section : Skylake"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css loupe">Article détaillé : <a href="/wiki/Skylake" title="Skylake">Skylake</a>.</div></div> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake_2">Kaby Lake</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=28" title="Modifier la section : Kaby Lake" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=28" title="Modifier le code source de la section : Kaby Lake"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="bandeau-container bandeau-section metadata bandeau-niveau-information"><div class="bandeau-cell bandeau-icone-css loupe">Article détaillé : <a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a>.</div></div> <p><abbr class="abbr" title="Septième">7<sup>e</sup></abbr> génération Intel Core, sortie en <time class="nowrap" datetime="2016-08" data-sort-value="2016-08">août 2016</time>. </p> <div class="mw-heading mw-heading2"><h2 id="Chipsets_compatibles">Chipsets compatibles</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=29" title="Modifier la section : Chipsets compatibles" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=29" title="Modifier le code source de la section : Chipsets compatibles"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable centre" style="font-size: 90%;"> <tbody><tr> <th rowspan="2">Chipset </th> <th rowspan="2">Commercialisation </th> <th colspan="4" style="text-align:center;">Architecture </th> <th colspan="5" style="text-align:center;">Processeur Graphique </th></tr> <tr> <th>Nom de code</th> <th>Gravure</th> <th>TDP</th> <th>Interface bus </th> <th>Modèle</th> <th>Fréquence</th> <th>DirectX</th> <th>OpenGL</th> <th>Moteur HD </th></tr> <tr align="left"> <td colspan="19" style="background:#127cc1;color: white"><b>Intel</b> </td></tr> <tr align="center"> <td align="left">X58</td> <td><time class="nowrap" datetime="2008-10" data-sort-value="2008-10">octobre 2008</time></td> <td>Tylersburg</td> <td></td> <td>24,1 W</td> <td>QPI</td> <td colspan="5">- </td></tr> <tr align="center"> <td align="left">P55</td> <td><time class="nowrap" datetime="2009-09" data-sort-value="2009-09">septembre 2009</time></td> <td>Ibex Peak</td> <td></td> <td></td> <td>DMI</td> <td colspan="5">- </td></tr> <tr align="center"> <td align="left">PM55</td> <td><time class="nowrap" datetime="2009-09" data-sort-value="2009-09">septembre 2009</time></td> <td>Ibex Peak-M</td> <td></td> <td>3,5 W</td> <td>DMI</td> <td colspan="5">- </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Performances_relatives_brutes">Performances relatives brutes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=30" title="Modifier la section : Performances relatives brutes" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=30" title="Modifier le code source de la section : Performances relatives brutes"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Pour évaluer les ordres de grandeur des puissances relatives de ces processeurs, un repère possible est l'indice <i><span class="lang-en" lang="en">Passmark</span></i><sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup>. Au <time class="nowrap" datetime="2015-09-15" data-sort-value="2015-09-15">15 septembre 2015</time>, cet indice est de 16 000 pour le Core i7-5960X à 3,00 GHz (bureau), de 4 000 pour le Core i7-3667U à 2,00 GHz (ultraportables). </p> <div class="mw-heading mw-heading2"><h2 id="Notes_et_références"><span id="Notes_et_r.C3.A9f.C3.A9rences"></span>Notes et références</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=31" title="Modifier la section : Notes et références" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=31" title="Modifier le code source de la section : Notes et références"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Notes">Notes</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=32" title="Modifier la section : Notes" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=32" title="Modifier le code source de la section : Notes"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="references-small decimal" style=""><div class="mw-references-wrap"><ol class="references"> <li id="cite_note-turboboost-10"><span class="mw-cite-backlink noprint">↑ <sup><a href="#cite_ref-turboboost_10-0">a</a> <a href="#cite_ref-turboboost_10-1">b</a> <a href="#cite_ref-turboboost_10-2">c</a> <a href="#cite_ref-turboboost_10-3">d</a> <a href="#cite_ref-turboboost_10-4">e</a> et <a href="#cite_ref-turboboost_10-5">f</a></sup> </span><span class="reference-text">Les valeurs sont présentées respectivement avec 4, 3, 2 et 1 cœur(s) actif(s). Entre parenthèses est indiqué le nombre de bins.</span> </li> <li id="cite_note-modelK-14"><span class="mw-cite-backlink noprint">↑ <sup><a href="#cite_ref-modelK_14-0">a</a> <a href="#cite_ref-modelK_14-1">b</a> <a href="#cite_ref-modelK_14-2">c</a> <a href="#cite_ref-modelK_14-3">d</a> et <a href="#cite_ref-modelK_14-4">e</a></sup> </span><span class="reference-text">Bénéficie d'un coefficient multiplicateur débloqué.</span> </li> <li id="cite_note-revC1_VTd-16"><span class="mw-cite-backlink noprint">↑ <sup><a href="#cite_ref-revC1_VTd_16-0">a</a> et <a href="#cite_ref-revC1_VTd_16-1">b</a></sup> </span><span class="reference-text">La technologie VT-d n'est pas prise en charge par le stepping C1.</span> </li> </ol></div> </div> <div class="mw-heading mw-heading3"><h3 id="Références"><span id="R.C3.A9f.C3.A9rences"></span>Références</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=33" title="Modifier la section : Références" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=33" title="Modifier le code source de la section : Références"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="references-small decimal" style=""><div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><a href="#cite_ref-1">↑</a> </span><span class="reference-text">U = <span class="lang-en" lang="en">Ultra-low-voltage</span>.</span> </li> <li id="cite_note-comm_20080819-2"><span class="mw-cite-backlink"><a href="#cite_ref-comm_20080819_2-0">↑</a> </span><span class="reference-text"><abbr class="abbr indicateur-langue" title="Langue : anglais">(en)</abbr> Communiqué de presse Intel, <a rel="nofollow" class="external text" href="http://www.intel.com/pressroom/archive/releases/20080819comp.htm"><span class="lang-en" lang="en"><i>Intel Shifts Future Core™ Processors Into Turbo Mode</i></span></a> dans Intel News Release, le 19 août 2008.</span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><a href="#cite_ref-3">↑</a> </span><span class="reference-text">David Legrand, <span class="noarchive">« <a rel="nofollow" class="external text" href="https://web.archive.org/web/20080824015330/http://www.pcinpact.com/actu/news/45467-Intel-IDF-Core-i7-Overclocking-Bin.htm">IDF 2008 : l'overclocking sur Nehalem, la grande inconnue</a> »</span>, sur <i><a href="/wiki/Next_(site_web)" title="Next (site web)">pcinpact.com</a></i>, <time class="nowrap" datetime="2009-08-21" data-sort-value="2009-08-21">21 août 2009</time> <small>(version du <time class="nowrap" datetime="2008-08-24" data-sort-value="2008-08-24">24 août 2008</time> sur <i><a href="/wiki/Internet_Archive" title="Internet Archive">Internet Archive</a></i>)</small></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><a href="#cite_ref-4">↑</a> </span><span class="reference-text">David Legrand, <span class="noarchive">« <a rel="nofollow" class="external text" href="https://web.archive.org/web/20080926114611/http://www.pcinpact.com/actu/news/46284-Intel-Core-i7-DST.htm">Mode Turbo des Core i7 : ça sera Dynamic Speed Technology</a> »</span>, sur <i><a href="/wiki/Next_(site_web)" title="Next (site web)">pcinpact.com</a></i>, <time class="nowrap" datetime="2009-09-26" data-sort-value="2009-09-26">26 septembre 2009</time> <small>(version du <time class="nowrap" datetime="2008-09-26" data-sort-value="2008-09-26">26 septembre 2008</time> sur <i><a href="/wiki/Internet_Archive" title="Internet Archive">Internet Archive</a></i>)</small></span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><a href="#cite_ref-5">↑</a> </span><span class="reference-text">Rajinder Gill, <a rel="nofollow" class="external text" href="http://www.anandtech.com/mb/showdoc.aspx?i=3661">P55 <i>Extreme Overclockers: Check your sockets!</i></a>, dans AnandTech, le 15 octobre 2009.</span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><a href="#cite_ref-6">↑</a> </span><span class="reference-text">Massman, <a rel="nofollow" class="external text" href="http://www.xtremesystems.org/forums/showthread.php?s=195eec42876dc6078cfa6cbca58daf3d&t=234723"><i>P55-UD6 socket burn</i></a>, dans XtremeSystems Forums, le 18 septembre 2009.</span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><a href="#cite_ref-7">↑</a> </span><span class="reference-text"><span class="ouvrage" id="Moammer2017"><span class="ouvrage" id="Khalid_Moammer2017"><abbr class="abbr indicateur-langue" title="Langue : anglais">(en)</abbr> Khalid Moammer, « <a rel="nofollow" class="external text" href="https://wccftech.com/intel-i7-7700k-owners-flood-forums-with-overheating-complaints/"><cite style="font-style:normal;" lang="en">Intel Says i7 7700K CPUs Shouldn’t Be Overclocked In Response To Countless Overheating Complaints</cite></a> », sur <span class="italique">Wccftech.com</span>, <time class="nowrap" datetime="2017-05-05" data-sort-value="2017-05-05">5 mai 2017</time> <small style="line-height:1em;">(consulté le <time class="nowrap" datetime="2020-07-30" data-sort-value="2020-07-30">30 juillet 2020</time>)</small></span></span>.</span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><a href="#cite_ref-8">↑</a> </span><span class="reference-text">David Legrand, <span class="noarchive">« <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090622154129/http://www.pcinpact.com/actu/news/51516-intel-havendale-clarkdale-gulftown-core-i9.htm">Intel saute l'Havendale en 45 nm, pour le Clarkdale en 32 nm</a> »</span>, sur <i><a href="/wiki/Next_(site_web)" title="Next (site web)">pcinpact.com</a></i>, <time class="nowrap" datetime="2009-06-19" data-sort-value="2009-06-19">19 juin 2009</time> <small>(version du <time class="nowrap" datetime="2009-06-22" data-sort-value="2009-06-22">22 juin 2009</time> sur <i><a href="/wiki/Internet_Archive" title="Internet Archive">Internet Archive</a></i>)</small></span> </li> <li id="cite_note-9"><span class="mw-cite-backlink"><a href="#cite_ref-9">↑</a> </span><span class="reference-text">Florian Vieru, <a rel="nofollow" class="external text" href="http://www.pcworld.fr/2009/12/14/materiel/cpu/intel-core-i7-980x-core-i7-930/464071/"><i>Gulftown sera le Core i7-980X, Core i7-930 pour bientôt !</i></a>, dans PCWorld.fr, le 14 décembre 2009.</span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><a href="#cite_ref-11">↑</a> </span><span class="reference-text">Florian Vieru, <span class="ouvrage"><span class="noarchive">« <a rel="nofollow" class="external text" href="http://www.pcworld.fr/2010/07/19/materiel/cpu/intel-core-i7-970-core-i5-760-i7-870s/501961/"><cite style="font-style:normal; color:var(--color-link-red, #d73333);"><i>Intel lance le Core i7-970 et baisse le prix de plusieurs CPU</i></cite></a> »<sup class="plainlinks">(<a rel="nofollow" class="external text" href="https://web.archive.org/web/*/http://www.pcworld.fr/2010/07/19/materiel/cpu/intel-core-i7-970-core-i5-760-i7-870s/501961/">Archive.org</a> • <a rel="nofollow" class="external text" href="https://archive.wikiwix.com/cache/?url=http://www.pcworld.fr/2010/07/19/materiel/cpu/intel-core-i7-970-core-i5-760-i7-870s/501961/">Wikiwix</a> • <a rel="nofollow" class="external text" href="https://archive.is/http://www.pcworld.fr/2010/07/19/materiel/cpu/intel-core-i7-970-core-i5-760-i7-870s/501961/">Archive.is</a> • <a rel="nofollow" class="external text" href="https://webcache.googleusercontent.com/search?hl=fr&q=cache:http://www.pcworld.fr/2010/07/19/materiel/cpu/intel-core-i7-970-core-i5-760-i7-870s/501961/">Google</a> • <a href="/wiki/Projet:Correction_des_liens_externes#J'ai_trouvé_un_lien_mort,_que_faire_?" title="Projet:Correction des liens externes">Que faire ?</a>)</sup></span></span>, , dans PCWorld.fr, le 19 juillet 2010.</span> </li> <li id="cite_note-12"><span class="mw-cite-backlink"><a href="#cite_ref-12">↑</a> </span><span class="reference-text">Patrick Schmid, <a rel="nofollow" class="external text" href="http://www.presence-pc.com/tests/core-i7-stepping-23153/"><i>Core i7 : C0 (965) VS D0 (975)</i></a>, dans Tom's hardware, le 24 août 2009.</span> </li> <li id="cite_note-pcinpact-210709-13"><span class="mw-cite-backlink"><a href="#cite_ref-pcinpact-210709_13-0">↑</a> </span><span class="reference-text">David Legrand, <span class="noarchive">« <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090724142023/http://www.pcinpact.com/actu/news/52073-intel-core-i5-i7-clarkdale.htm">La roadmap de la rentrée d'Intel se dévoile dans le détail</a> »</span>, sur <i><a href="/wiki/Next_(site_web)" title="Next (site web)">pcinpact.com</a></i>, <time class="nowrap" datetime="2009-07-21" data-sort-value="2009-07-21">21 juillet 2009</time> <small>(version du <time class="nowrap" datetime="2009-07-24" data-sort-value="2009-07-24">24 juillet 2009</time> sur <i><a href="/wiki/Internet_Archive" title="Internet Archive">Internet Archive</a></i>)</small></span> </li> <li id="cite_note-THFR_26092012-15"><span class="mw-cite-backlink noprint">↑ <sup><a href="#cite_ref-THFR_26092012_15-0">a</a> <a href="#cite_ref-THFR_26092012_15-1">b</a> <a href="#cite_ref-THFR_26092012_15-2">c</a> et <a href="#cite_ref-THFR_26092012_15-3">d</a></sup> </span><span class="reference-text"><a rel="nofollow" class="external text" href="http://www.presence-pc.com/actualite/Celeron-Core-i5-i7-48883/">Un Celeron, dix Core i5 et quatre Core i7 sont sur un bateau…</a>, Tom's Hardware (26 septembre 2012).</span> </li> <li id="cite_note-THFR_1-17"><span class="mw-cite-backlink noprint">↑ <sup><a href="#cite_ref-THFR_1_17-0">a</a> <a href="#cite_ref-THFR_1_17-1">b</a> <a href="#cite_ref-THFR_1_17-2">c</a> et <a href="#cite_ref-THFR_1_17-3">d</a></sup> </span><span class="reference-text"><a rel="nofollow" class="external text" href="http://www.presence-pc.com/actualite/Ivy-Bridge-Core-47172/">Premiers Ivy Bridge en avril, la suite en juin</a>, Tom's Hardware (29 mars 2012).</span> </li> <li id="cite_note-pcinpact-130809-18"><span class="mw-cite-backlink noprint">↑ <sup><a href="#cite_ref-pcinpact-130809_18-0">a</a> <a href="#cite_ref-pcinpact-130809_18-1">b</a> et <a href="#cite_ref-pcinpact-130809_18-2">c</a></sup> </span><span class="reference-text">Bruno Cormier, <span class="noarchive">« <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090816155958/http://www.pcinpact.com/actu/news/52489-premier-core-i7-mobile-fin-septembre.htm">Les premiers Core i7 mobiles prévus pour fin septembre</a> »</span>, sur <i><a href="/wiki/Next_(site_web)" title="Next (site web)">pcinpact.com</a></i>, <time class="nowrap" datetime="2009-08-13" data-sort-value="2009-08-13">13 août 2009</time> <small>(version du <time class="nowrap" datetime="2009-08-16" data-sort-value="2009-08-16">16 août 2009</time> sur <i><a href="/wiki/Internet_Archive" title="Internet Archive">Internet Archive</a></i>)</small></span> </li> <li id="cite_note-tom-220909-19"><span class="mw-cite-backlink noprint">↑ <sup><a href="#cite_ref-tom-220909_19-0">a</a> <a href="#cite_ref-tom-220909_19-1">b</a> et <a href="#cite_ref-tom-220909_19-2">c</a></sup> </span><span class="reference-text">Matthieu Lamelot, <a rel="nofollow" class="external text" href="http://www.presence-pc.com/actualite/Core-i7-620M-i5-540M-36513/"><i>Cinq Core i7/i5 "Arrandale" prévus début 2010</i></a>, dans Tom's hardware, le 22 septembre 2009.</span> </li> <li id="cite_note-20"><span class="mw-cite-backlink"><a href="#cite_ref-20">↑</a> </span><span class="reference-text"><abbr class="abbr indicateur-langue" title="Langue : anglais">(en)</abbr> <a rel="nofollow" class="external text" href="https://www.cpubenchmark.net/high_end_cpus.html">« <span class="lang-en" lang="en">High End CPUs - Intel vs AMD</span> »</a>, <span class="lang-en" lang="en">CPU Benchmarks</span>.</span> </li> </ol></div> </div> <div class="mw-heading mw-heading2"><h2 id="Voir_aussi">Voir aussi</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=34" title="Modifier la section : Voir aussi" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=34" title="Modifier le code source de la section : Voir aussi"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Articles_connexes">Articles connexes</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=35" title="Modifier la section : Articles connexes" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=35" title="Modifier le code source de la section : Articles connexes"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Intel_Core_i3" title="Intel Core i3">Intel Core i3</a></li> <li><a href="/wiki/Intel_Core_i5" title="Intel Core i5">Intel Core i5</a></li> <li><a href="/wiki/Intel_Core_i9" title="Intel Core i9">Intel Core i9</a></li></ul> <div class="mw-heading mw-heading3"><h3 id="Liens_externes">Liens externes</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core_i7&veaction=edit&section=36" title="Modifier la section : Liens externes" class="mw-editsection-visualeditor"><span>modifier</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=Intel_Core_i7&action=edit&section=36" title="Modifier le code source de la section : Liens externes"><span>modifier le code</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><abbr class="abbr indicateur-langue" title="Langue : anglais">(en)</abbr> <a rel="nofollow" class="external text" href="http://www.clunk.org.uk/forums/overclocking/22106-core-i7-overclocking-guide-beginners.html">Core i7 Overclocking Guide For Beginners.</a> dans Clunk.org.uk</li> <li><a rel="nofollow" class="external text" href="http://www.pcinpact.com/articles/intel-core-i7/348-1.htm">Tout savoir de l'architecture Nehalem</a> dans PC INpact</li> <li><a rel="nofollow" class="external text" href="https://www.tt-hardware.com/modules.php?name=News&file=article&sid=12109">Nehalem : visite du cœur du Core i7...</a> dans TT-Hardware</li> <li><a rel="nofollow" class="external text" href="http://www.xbitlabs.com/articles/cpu/display/core-i7-920-overclocking.html">Intel Core i7-920 Overclocking Guide</a> dans X-bit Labs</li></ul> <div class="navbox-container" style="clear:both;"> <table class="navbox collapsible noprint autocollapse" style="background:#fdfdfd;"> <tbody><tr><th class="navbox-title" colspan="2" style=""><div style="float:left; width:6em; text-align:left"><div class="noprint plainlinks nowrap tnavbar" style="padding:0; font-size:xx-small; color:var(--color-emphasized, #000000);"><a href="/wiki/Mod%C3%A8le:Palette_Microprocesseurs_Intel" title="Modèle:Palette Microprocesseurs Intel"><abbr class="abbr" title="Voir ce modèle.">v</abbr></a> · <a class="external text" href="https://fr.wikipedia.org/w/index.php?title=Mod%C3%A8le:Palette_Microprocesseurs_Intel&action=edit"><abbr class="abbr" title="Modifier ce modèle. Merci de prévisualiser avant de sauvegarder.">m</abbr></a></div></div><div style="font-size:110%"><a href="/wiki/Liste_des_microprocesseurs_Intel" title="Liste des microprocesseurs Intel">Processeurs</a> <a href="/wiki/Intel" title="Intel">Intel</a></div></th> </tr> <tr> <th class="navbox-group" style="width:10em; text-align:right;">Abandonnés</th> <td class="navbox-list" style=""><table class="navbox-subgroup" style=""> <tbody><tr> <th class="navbox-group" style="width:120px; text-align:right; background:#e6e6ff;">4 bits</th> <td class="navbox-list" style="text-align:left;;"><div class="liste-horizontale"> <ul><li><a href="/wiki/Intel_4004" title="Intel 4004">4004</a></li> <li><a href="/wiki/Intel_4040" title="Intel 4040">4040</a></li></ul> </div></td> </tr> <tr> <th class="navbox-group" style="width:120px; text-align:right; background:#e6e6ff;">Pré-x86 (<a href="/wiki/Architecture_8_bits" title="Architecture 8 bits">8-bits</a>)</th> <td class="navbox-list navbox-even" style="text-align:left;;background:#f7f7f7;"><div class="liste-horizontale"> <ul><li><a href="/wiki/Intel_8008" title="Intel 8008">8008</a></li> <li><a href="/wiki/Intel_8080" title="Intel 8080">8080</a></li> <li><a href="/wiki/Intel_8085" title="Intel 8085">8085</a></li></ul> </div></td> </tr> <tr> <th class="navbox-group" style="width:120px; text-align:right; background:#e6e6ff;"><a href="/wiki/X86" title="X86">x86</a>-16 (<a href="/wiki/Architecture_16_bits" title="Architecture 16 bits">16-bits</a>)</th> <td class="navbox-list" style="text-align:left;;"><div class="liste-horizontale"> <ul><li><a href="/wiki/Intel_8086" title="Intel 8086">8086</a></li> <li><a href="/wiki/Intel_8088" title="Intel 8088">8088</a></li> <li><a href="/wiki/Intel_80186" title="Intel 80186">80186</a></li> <li><a href="/wiki/Intel_80188" title="Intel 80188">80188</a></li> <li><a href="/wiki/Intel_80286" title="Intel 80286">80286</a></li></ul> </div></td> </tr> <tr> <th class="navbox-group" style="width:120px; text-align:right; background:#e6e6ff;"><a href="/wiki/X87" title="X87">x87</a> (<a href="/wiki/Unit%C3%A9_de_calcul_en_virgule_flottante" title="Unité de calcul en virgule flottante">FPU</a> externes)</th> <td class="navbox-list navbox-even" style="text-align:left;;background:#f7f7f7;"><div class="liste-horizontale"> <ul><li>Bus 8/16 bits : <a href="/wiki/Intel_8087" title="Intel 8087">8087</a></li> <li>Bus 16 bits : <a href="/wiki/Intel_80287" title="Intel 80287">80287</a></li> <li>Bus 32 bits : <a href="/wiki/Intel_80387" title="Intel 80387">80387</a>, <a href="/wiki/Intel_80487" title="Intel 80487">80487</a></li></ul> </div></td> </tr> <tr> <th class="navbox-group" style="width:120px; text-align:right; background:#e6e6ff;">x86-32/<a href="/wiki/X86" title="X86">IA-32</a> (<a href="/wiki/Architecture_32_bits" title="Architecture 32 bits">32-bit</a>)</th> <td class="navbox-list" style="text-align:left;;"><div class="liste-horizontale"> <ul><li><a href="/wiki/Intel_80386" title="Intel 80386">80386</a> <ul><li><a href="/wiki/Intel_80386" title="Intel 80386">SX</a></li> <li><a href="/wiki/Intel_80376" title="Intel 80376">376</a></li> <li><a href="/wiki/Intel_80386EX" title="Intel 80386EX">EX</a></li></ul></li> <li><a href="/wiki/Intel_80486" title="Intel 80486">80486</a> <ul><li><a href="/wiki/Intel_80486DX" title="Intel 80486DX">DX</a></li> <li><a href="/wiki/Intel_80486SX" title="Intel 80486SX">SX</a></li> <li><a href="/wiki/Intel_80486" title="Intel 80486">DX2</a></li> <li><a href="/wiki/Intel_80486DX4" title="Intel 80486DX4">DX4</a></li> <li><a href="/wiki/Intel_80486SL" title="Intel 80486SL">SL</a></li> <li><a href="/w/index.php?title=RapidCAD&action=edit&redlink=1" class="new" title="RapidCAD (page inexistante)">RapidCAD</a> <a href="https://en.wikipedia.org/wiki/RapidCAD" class="extiw" title="en:RapidCAD"><span class="indicateur-langue" title="Article en anglais : « RapidCAD »">(en)</span></a></li> <li><a href="/w/index.php?title=Intel_80486_OverDrive&action=edit&redlink=1" class="new" title="Intel 80486 OverDrive (page inexistante)">80486 OverDrive</a> <a href="https://en.wikipedia.org/wiki/i486_OverDrive" class="extiw" title="en:i486 OverDrive"><span class="indicateur-langue" title="Article en anglais : « i486 OverDrive »">(en)</span></a></li></ul></li> <li><a href="/wiki/Pentium_(marque)" title="Pentium (marque)">Pentium</a> <ul><li><a href="/wiki/Intel_Pentium" title="Intel Pentium">Original</a></li> <li><a href="/w/index.php?title=Pentium_OverDrive&action=edit&redlink=1" class="new" title="Pentium OverDrive (page inexistante)">OverDrive</a> <a href="https://en.wikipedia.org/wiki/Pentium_OverDrive" class="extiw" title="en:Pentium OverDrive"><span class="indicateur-langue" title="Article en anglais : « Pentium OverDrive »">(en)</span></a></li> <li><a href="/wiki/Pentium_Pro" title="Pentium Pro">Pro</a></li> <li><a href="/wiki/Pentium_II" title="Pentium II">II</a></li> <li><a href="/w/index.php?title=Pentium_II_OverDrive&action=edit&redlink=1" class="new" title="Pentium II OverDrive (page inexistante)">II OverDrive</a></li> <li><a href="/wiki/Pentium_III" title="Pentium III">III</a></li> <li><a href="/wiki/Pentium_4" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_4-M" title="Pentium 4-M">4-M</a></li> <li><a href="/wiki/Pentium_M" title="Pentium M">M</a></li> <li><a href="/wiki/Pentium_M#Celeron_M" title="Pentium M">Celeron M</a></li></ul></li> <li><a href="/wiki/Yonah" title="Yonah">Core Solo/Duo</a></li> <li><a href="/wiki/Celeron#Celeron_D" title="Celeron">Celeron D</a></li> <li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/Intel_Atom#Stealey" title="Intel Atom">A100/A110</a></li></ul></li> <li><a href="/w/index.php?title=EP80579&action=edit&redlink=1" class="new" title="EP80579 (page inexistante)">EP80579</a> <a href="https://en.wikipedia.org/wiki/Tolapai" class="extiw" title="en:Tolapai"><span class="indicateur-langue" title="Article en anglais : « Tolapai »">(en)</span></a></li></ul> </div></td> </tr> <tr> <th class="navbox-group" style="width:120px; text-align:right; background:#e6e6ff;"><span class="nowrap"><a href="/wiki/X64" title="X64">x86-64</a>/<a href="/wiki/Intel_64" title="Intel 64">EM64T</a> (<a href="/wiki/Processeur_64_bits" title="Processeur 64 bits">64-bit</a>)</span></th> <td class="navbox-list navbox-even" style="text-align:left;;background:#f7f7f7;"><div class="liste-horizontale"> <ul><li><a href="/wiki/Pentium_4#Prescott_2M_(Extreme_Edition)" title="Pentium 4">Pentium 4</a></li> <li><a href="/wiki/Pentium_D" title="Pentium D">Pentium D</a></li> <li><a href="/wiki/Pentium_Extreme_Edition" title="Pentium Extreme Edition">Pentium Extreme Edition</a></li> <li><a href="/wiki/Celeron#Celeron_D" title="Celeron">Celeron D</a></li> <li><a href="/wiki/Intel_Core_2" title="Intel Core 2">Core 2</a></li> <li><a href="/wiki/Intel_Core_2_Extreme" title="Intel Core 2 Extreme">Core 2 Extreme</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Pentium Dual-Core</a></li> <li><a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a></li> <li><a href="/wiki/Pentium_(marque)" title="Pentium (marque)">Pentium</a></li></ul> </div></td> </tr> <tr> <th class="navbox-group" style="width:120px; text-align:right; background:#e6e6ff;"><a href="/wiki/Processeur_%C3%A0_jeu_d%27instructions_r%C3%A9duit" title="Processeur à jeu d'instructions réduit">RISC</a></th> <td class="navbox-list" style="text-align:left;;"><div class="liste-horizontale"> <ul><li><a href="/wiki/Intel_i860" title="Intel i860">i860</a></li> <li><a href="/wiki/Intel_i960" title="Intel i960">i960</a></li> <li><a href="/wiki/StrongARM" title="StrongARM">StrongARM</a></li> <li><a href="/wiki/XScale" title="XScale">IOP et XScale</a></li></ul> </div></td> </tr> <tr> <th class="navbox-group" style="width:120px; text-align:right; background:#e6e6ff;"><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a> (<a href="/wiki/IA-64" title="IA-64">IA-64</a>)</th> <td class="navbox-list navbox-even" style="text-align:left;;background:#f7f7f7;"><div class="liste-horizontale"> <ul><li><a href="/wiki/Itanium" title="Itanium">Itanium</a></li> <li><a href="/wiki/Intel_Itanium_2" title="Intel Itanium 2">Itanium 2</a></li> <li><a href="/wiki/Montecito_(processeur)" title="Montecito (processeur)">Montecito</a></li> <li><a href="/wiki/Tukwila_(processeur)" title="Tukwila (processeur)">Itanium 3</a></li></ul> </div></td> </tr> <tr> <th class="navbox-group" style="width:120px; text-align:right; background:#e6e6ff;">Autres</th> <td class="navbox-list" style="text-align:left;;"><div class="liste-horizontale"> <ul><li><a href="/wiki/Centrino" title="Centrino">Centrino</a></li></ul> </div></td> </tr> </tbody></table></td> </tr> <tr> <th class="navbox-group" style="width:10em; text-align:right;">Actuels</th> <td class="navbox-list navbox-even" style="background:#f7f7f7;"><table class="navbox-subgroup" style=""> <tbody><tr> <th class="navbox-group" style="width:50px; text-align:right; background:#e6e6ff;">x86-64</th> <td class="navbox-list" style="text-align:left;;"><div class="liste-horizontale"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a></li> <li><a href="/wiki/Intel_Core_i3" title="Intel Core i3">Core i3</a></li> <li><a href="/wiki/Intel_Core_i5" title="Intel Core i5">Core i5</a></li> <li><a class="mw-selflink selflink">Core i7</a></li> <li><a href="/wiki/Intel_Core_i9" title="Intel Core i9">Core i9</a></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a></li> <li><a href="/wiki/Intel_Core_M" title="Intel Core M">Core M</a></li></ul> </div></td> </tr> </tbody></table></td> </tr> <tr> <th class="navbox-group" style="width:10em; text-align:right;"><a href="/wiki/Intel#Microprocesseurs_x86" title="Intel">Microarchitectures</a></th> <td class="navbox-list" style=""><table class="navbox-subgroup" style=""> <tbody><tr> <th class="navbox-group" style="width:50px; text-align:right; background:#e6e6ff;">x86-32</th> <td class="navbox-list" style="text-align:left;;"><div class="liste-horizontale"> <ul><li><a href="/wiki/Intel_Pentium" title="Intel Pentium">P5</a></li> <li><a href="/wiki/Intel_P6" title="Intel P6">P6</a> <ul><li><a href="/wiki/Pentium_M" title="Pentium M">Pentium M</a></li> <li><a href="/wiki/Yonah" title="Yonah">Yonah</a></li></ul></li> <li><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></li></ul> </div></td> </tr> <tr> <th class="navbox-group" style="width:50px; text-align:right; background:#e6e6ff;"><a href="/wiki/X64" title="X64">x86-64</a></th> <td class="navbox-list navbox-even" style="text-align:left;;background:#f7f7f7;"><div class="liste-horizontale"> <ul><li><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></li> <li><a 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Lake</a></li></ul></li> <li><a href="/w/index.php?title=CSunny_Cove&action=edit&redlink=1" class="new" title="CSunny Cove (page inexistante)">ypress Cove</a> <ul><li><a href="/wiki/Rocket_Lake" title="Rocket Lake">Rocket Lake</a></li></ul></li> <li><a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a> <ul><li><a href="/wiki/Alder_Lake" title="Alder Lake">Alder Lake</a></li></ul></li> <li><a href="/wiki/Golden_Cove#Raptor_Cove" title="Golden Cove">Raptor Cove</a> <ul><li><a href="/wiki/Raptor_Lake" title="Raptor Lake">Raptor Lake</a></li></ul></li> <li><a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a></li> <li><a href="/wiki/Lunar_Lake" title="Lunar Lake">Lunar Lake</a></li></ul> </div></td> </tr> <tr> <th class="navbox-group" style="width:50px; text-align:right; background:#e6e6ff;">Faible consommation</th> <td class="navbox-list" style="text-align:left;;"><div class="liste-horizontale"> <ul><li><a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a> <ul><li><a href="/wiki/Bonnell_(microarchitecture)#Saltwell" title="Bonnell (microarchitecture)">Saltwell</a></li></ul></li> <li><a href="/wiki/Silvermont" title="Silvermont">Silvermont</a> <ul><li><a href="/wiki/Silvermont" title="Silvermont">Airmont</a></li></ul></li> <li><a href="/wiki/Goldmont" title="Goldmont">Goldmont</a> <ul><li><a href="/w/index.php?title=Goldmont_Plus&action=edit&redlink=1" class="new" title="Goldmont Plus (page inexistante)">Goldmont Plus</a> <a href="https://en.wikipedia.org/wiki/Goldmont_Plus" class="extiw" title="en:Goldmont Plus"><span class="indicateur-langue" title="Article en anglais : « Goldmont Plus »">(en)</span></a></li></ul></li> <li><a href="/w/index.php?title=Tremont_(microarchitecture)&action=edit&redlink=1" class="new" title="Tremont (microarchitecture) (page inexistante)">Tremont</a> <a href="https://en.wikipedia.org/wiki/Tremont_(microarchitecture)" class="extiw" title="en:Tremont (microarchitecture)"><span class="indicateur-langue" title="Article en anglais : « Tremont (microarchitecture) »">(en)</span></a></li> <li><a href="/w/index.php?title=Gracemont_(microarchitecture)&action=edit&redlink=1" class="new" title="Gracemont (microarchitecture) (page inexistante)">Gracemont</a> <a href="https://en.wikipedia.org/wiki/Gracemont_(microarchitecture)" class="extiw" title="en:Gracemont (microarchitecture)"><span class="indicateur-langue" title="Article en anglais : « Gracemont (microarchitecture) »">(en)</span></a></li></ul> </div></td> </tr> </tbody></table></td> </tr> <tr> <td class="navbox-banner" style="" colspan="2"><div class="liste-horizontale"> <ul><li><a href="/wiki/Socket_(processeur)" title="Socket (processeur)">Sockets</a></li> <li><a href="/wiki/Intel_I/O_Controller_Hub" title="Intel I/O Controller Hub">ICH</a></li> <li><a href="/wiki/Memory_Controller_Hub" title="Memory Controller Hub">MCH</a></li> <li><a href="/wiki/Platform_controller_hub" title="Platform controller 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