<?xml version="1.0" encoding="UTF-8"?> <collection> <dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:invenio="http://invenio-software.org/elements/1.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd"><dc:identifier>doi:10.1016/j.nima.2022.167020</dc:identifier><dc:language>eng</dc:language><dc:creator>Sieberer, Patrick</dc:creator><dc:creator>Irmler, Christian</dc:creator><dc:creator>Steininger, Helmut</dc:creator><dc:creator>Bergauer, Thomas</dc:creator><dc:title>Design and characterization of depleted monolithic active pixel sensors within the RD50 collaboration</dc:title><dc:subject>Detectors and Experimental Techniques</dc:subject><dc:description>The CERN RD50 CMOS working group is designing and characterizing depleted monolithic active pixel sensors (DMAPS) for use in high radiation environments fabricated in the LFoundry 150聽nm HV-CMOS process. The first iteration of this chip, RD50-MPW1, suffered from high leakage current, low breakdown voltage and crosstalk. In order to mitigate these shortcomings, an improved version with improved pixel geometry was designed. The RD50-MPW2 integrates a matrix of 8 $\times$ 8 pixels with analog front-end, but no digital readout. It was delivered in early 2020 and characterized within lab-measurements, an irradiation campaign and test beams. To read out the chips the Caribou DAQ system is used with a custom chipboard as well as specific firmware and software modules. A third iteration of the chip, the RD50-MPW3, has been submitted to LFoundry in December 2021 and is expected to be delivered in May 2022. It will keep the well working analog part of its predecessor, completed by an in-pixel digital logic and an optimized peripheral readout for effective pixel configuration and fast serial data transmission. The chip will comprise a matrix of 64 $\times$ 64 pixels arranged in 32 double-columns. We will present an overview of the RD50 HV-CMOS activities focusing on the measurement results of RD50-MPW2 chip, as well as the design and readout of the RD50-MPW3.</dc:description><dc:publisher/><dc:date>2022</dc:date><dc:source>http://cds.cern.ch/record/2835873</dc:source><dc:doi>10.1016/j.nima.2022.167020</dc:doi><dc:identifier>http://cds.cern.ch/record/2835873</dc:identifier><dc:identifier>oai:cds.cern.ch:2835873</dc:identifier></dc:dc> </collection>