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class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Electronic design automation company based in Henderson, Nevada</div> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output 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.ib-company-country{display:inline}</style><table class="infobox ib-company vcard"><caption class="infobox-title fn org">ALDEC, Inc.</caption><tbody><tr><td colspan="2" class="infobox-image ib-company-logo logo"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:Aldec,_Inc._Company_Logo,_Crescent_style.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/5/56/Aldec%2C_Inc._Company_Logo%2C_Crescent_style.svg/220px-Aldec%2C_Inc._Company_Logo%2C_Crescent_style.svg.png" decoding="async" width="220" height="70" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/56/Aldec%2C_Inc._Company_Logo%2C_Crescent_style.svg/330px-Aldec%2C_Inc._Company_Logo%2C_Crescent_style.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/56/Aldec%2C_Inc._Company_Logo%2C_Crescent_style.svg/440px-Aldec%2C_Inc._Company_Logo%2C_Crescent_style.svg.png 2x" data-file-width="487" data-file-height="156" /></a></span></td></tr><tr><th scope="row" class="infobox-label">Company type</th><td class="infobox-data category"><a href="/wiki/Private_company" class="mw-redirect" title="Private company">Private</a></td></tr><tr><th scope="row" class="infobox-label">Industry</th><td class="infobox-data category"><a href="/wiki/Electronic_design_automation" title="Electronic design automation">EDA</a></td></tr><tr><th scope="row" class="infobox-label">Founded</th><td class="infobox-data">1984</td></tr><tr><th scope="row" class="infobox-label">Headquarters</th><td class="infobox-data label"><a href="/wiki/Henderson,_Nevada" title="Henderson, Nevada">Henderson, Nevada</a>, <br /><a href="/wiki/United_States" title="United States">United States</a></td></tr><tr><th scope="row" class="infobox-label">Products</th><td class="infobox-data">Active-HDL, ALINT-PRO, Riviera-PRO, Spec-TRACER, RTAX/RTSX Prototyping, HES-DVM, HES-7, TySOM</td></tr><tr><th scope="row" class="infobox-label">Website</th><td class="infobox-data"><span class="url"><a rel="nofollow" class="external text" href="https://www.aldec.com/">aldec.com</a></span></td></tr></tbody></table> <p><b>Aldec, Inc.</b> is a privately owned <a href="/wiki/Electronic_design_automation" title="Electronic design automation">electronic design automation</a> company based in <a href="/wiki/Henderson,_Nevada" title="Henderson, Nevada">Henderson, Nevada</a>, providing <a href="/wiki/Software" title="Software">software</a> and <a href="/wiki/Electronic_hardware" title="Electronic hardware">hardware</a> used in creation and verification of digital designs targeting <a href="/wiki/FPGA" class="mw-redirect" title="FPGA">FPGA</a> and <a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a> technologies. </p><p>As a member of <a href="/wiki/Accellera" title="Accellera">Accellera</a> and <a href="/wiki/IEEE_Standards_Association" title="IEEE Standards Association">IEEE Standards Association,</a> Aldec actively participates in the process of developing new standards and updating existing standards (e.g. <a href="/wiki/VHDL" title="VHDL">VHDL</a>, <a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a>). Aldec provides a <a href="/wiki/Hardware_description_language" title="Hardware description language">hardware description language</a> (HDL) simulation engine for other EDA tools such as <a href="/wiki/Altium" title="Altium">Altium</a> <a href="/wiki/Altium_Designer" title="Altium Designer">Designer</a> and bundles special version of its tools with <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a> vendors software such as <a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a>.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Aldec&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="1984-1999">1984-1999</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Aldec&action=edit&section=2" title="Edit section: 1984-1999"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Aldec was founded in 1984 by Dr. Stanley M. Hyduke.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2024)">citation needed</span></a></i>]</sup> In 1985 the company released its first product: the <a href="/wiki/MS-DOS" title="MS-DOS">MS-DOS</a>-based gate-level simulator <b>SUSIE</b>. For the next couple of years several versions of the product were used as companion simulators for popular schematic entry tools such as <a href="/wiki/OrCAD" title="OrCAD">OrCAD</a>.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2024)">citation needed</span></a></i>]</sup> Sensing the growing popularity of <a href="/wiki/Microsoft_Windows" title="Microsoft Windows">Microsoft Windows</a>, Aldec ported its simulator to this platform and added schematic entry and design management tool. The new software suite was released in 1992 as <b>Active-CAD</b> (some low-end versions of the suite were for some time sold under <b>Susie-CAD</b> brand). One of the distinguishing features of Active-CAD was the ability of instantaneous transfer of schematic changes to the simulator, allowing quick verification of the behavior of the modified circuit.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2024)">citation needed</span></a></i>]</sup> </p><p>In 1996 Aldec signed an agreement with <a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> that allowed distribution of the Xilinx-only version of Active-CAD under the <b>Foundation</b> name. While <a href="/wiki/VHDL" title="VHDL">VHDL</a> and <a href="/wiki/Verilog" title="Verilog">Verilog</a> were supported by Active-CAD in the form of schematic macros, the release of <b>Active-VHDL</b> in 1997 marked the shift from netlist-based design to HDL-based design. After adding Verilog support, Active-VHDL was renamed to <b>Active-HDL</b> and was still available as of 2020.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2024)">citation needed</span></a></i>]</sup> </p> <div class="mw-heading mw-heading3"><h3 id="2000-2024">2000-2024</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Aldec&action=edit&section=3" title="Edit section: 2000-2024"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 2000 Aldec released a high-performance HDL simulator working not only on <a href="/wiki/Microsoft_Windows" title="Microsoft Windows">Windows</a>, but also on <a href="/wiki/Solaris_(operating_system)" class="mw-redirect" title="Solaris (operating system)">Solaris</a> and <a href="/wiki/Linux" title="Linux">Linux</a> platforms.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> In 2001 ALDEC added hardware to its product line: the <b>HES (Hardware Embedded Simulation) Platform</b> allowing hardware acceleration of HDL simulation and incremental prototyping of hardware. 2003 marked the release of Riviera-PRO supporting <a href="/w/index.php?title=Assertion_based_verification&action=edit&redlink=1" class="new" title="Assertion based verification (page does not exist)">assertion based verification</a> (OpenVera, <a href="/wiki/Property_Specification_Language" title="Property Specification Language">PSL</a> and <a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a> can be used to write properties, assertions and coverage).<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2024)">citation needed</span></a></i>]</sup> Support for <a href="/wiki/SystemC" title="SystemC">SystemC</a> and non-assertion part of <a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a> was added in 2004. Interfaces to <a href="/wiki/MATLAB" title="MATLAB">MATLAB</a> and <a href="/wiki/Simulink" title="Simulink">Simulink</a> appeared in Aldec tools for the first time in 2005.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2024)">citation needed</span></a></i>]</sup> In 2006 Riviera-PRO was the first simulator supporting <b>Open IP Encryption Initiative</b> by <a href="/wiki/Synplicity" class="mw-redirect" title="Synplicity">Synplicity</a>.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p><p>Stimulated by requests from Verilog users, Aldec released in 2007 an advanced, user-configurable <a href="/wiki/Lint_(software)" title="Lint (software)">lint</a> tool implementing rules created by STJapanese consortium of major silicon vendors. In 2008, the company released ALINT: Design Rule Checker (STARC – Japanese Consortium of 11 ASIC Companies). In 2010, it released support for VHDL IEEE 1076-2008. Also in 2010, Aldec's Active-HDL won the Best FPGA Design & Simulation Tool in China. In 2011, Aldec delivered UVM 1.0, OVM 2.1.2 and VMM 1.1.1a support, and released a 4 MHz Design Emulator. It also won Best FPGA Design & Verification Platform Provider in China. In 2012, Aldec entered the SoC/ASIC prototyping market with HES-7, and jointly launched OSVVM and VHDL Verification. In 2013, Aldec released Spec-TRACER Requirements Lifecycle Management. In 2015, Aldec released ALINT-PRO with CDC Verification, and in 2016, Aldec released TySOM Product Line for Embedded Development using SoC FPGAs. In 2020, it released support for VHDL IEEE 1076-2019.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2024)">citation needed</span></a></i>]</sup> </p> <div class="mw-heading mw-heading2"><h2 id="Products">Products</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Aldec&action=edit&section=4" title="Edit section: Products"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Software">Software</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Aldec&action=edit&section=5" title="Edit section: Software"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><b>Active-HDL</b> - FPGA development environment built around common kernel HDL simulator. Supports text-based and graphical design entry and debugging tools, allows mixed-language simulation (VHDL/Verilog/EDIF/SystemC/SystemVerilog) and provides unified interface to various synthesis and implementation tools. Also supports assertion based verification with Open Vera, PSL, or Systemverilog Assertion statements. Special versions of the software that support just one FPGA vendor are available, e.g. <i>Active-HDL Lattice Edition</i>. Only available on MS Windows platform.</li> <li><b>Riviera-PRO</b> - high-end HDL simulator targeting ASIC and large FPGA designs. Riviera-PRO extends Active-HDL's simulation features with support for advanced verification methodologies such as linting, functional coverage, <a href="/wiki/Open_Verification_Methodology" title="Open Verification Methodology">OVM</a> and <a href="/wiki/Universal_Verification_Methodology" title="Universal Verification Methodology">UVM</a>, hardware acceleration, and prototyping. Riviera-PRO is a new generation of the tool known as Riviera-Classic and is available in 32-bit and 64-bit on MS Windows and Linux.</li> <li><b>HES-DVM</b> - solution allowing acceleration of HDL simulation (10x to 50x verification time reduction), emulation of the entire design and hardware/software co-simulation (useful in <a href="/wiki/Embedded_System" class="mw-redirect" title="Embedded System">Embedded System</a> development).</li> <li><b>ALINT-PRO</b> - single framework for design rule checker/linting and CDC analysis. ALINT-PRO is able to conduct extensive textual analysis of individual Verilog, VHDL and SystemVerilog design sources and advanced checks of the entire design hierarchy. Multiple sets of highly configurable, predefined rules are available and new, custom rules can be created using provided <a href="/wiki/API" title="API">API</a>. Built-in Phase-Based Linting methodology allows faster, more efficient checking of rules. ALINT-PRO smoothly supports running the rule checks for designs that target FPGA implementation using <a href="/wiki/Xilinx" title="Xilinx">Xilinx</a>, <a href="/wiki/Intel" title="Intel">Intel</a>, <a href="/wiki/Microsemi" title="Microsemi">Microsemi</a>, and <a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a> technologies with minimal setup</li> <li><b>Spec-TRACER</b> - unified requirements life-cycle management application designed specifically for FPGA and ASIC designs. Facilitates requirements capture, management, analysis, traceability and reporting; integrates with Windows-based HDL design and simulation tools.</li> <li><b>IP Products</b> - a set of general-purpose Intellectual Property blocks created by Aldec and its partners, validated in Active-HDL and Riviera-PRO environments.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Hardware">Hardware</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Aldec&action=edit&section=6" title="Edit section: Hardware"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><b>HES-7</b> - high capacity, high density, <a href="/wiki/FPGA" class="mw-redirect" title="FPGA">FPGA</a>-based <a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a> prototyping solution. With help of <a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> Virtex-7 <a href="/wiki/FPGA" class="mw-redirect" title="FPGA">FPGA</a>-based prototyping boards, HES-7 allows testing designs of up to 24 million ASIC gates.</li> <li><b>Microsemi RTAX/RTSX Prototyping</b> - the efficient way of prototyping designs with radiation hardened FPGA by using footprint-compatible prototyping boards with flash-based, reprogrammable chips on top. The solution includes optional software for netlist translation.</li> <li><b>DO-254 Compliance Test System (CTS)</b> - It is a complete verification solution that can assure the FPGA on your system to be DO-254/ED80 compliant. The CTS gives the user the ability to perform an advanced way of In-Hardware Simulation instead of the traditional Hardware Testing. As test vectors for the In-Hardware Simulation, you can reuse the same testbench with 100% Code Coverage results captured from RTL simulation. By reusing the same testbench, the Hardware Verification can easily achieve requirements traceability. You can perform the In-Hardware Simulation at speed at the target device. The CTS also allows easy comparison and debugging of the In-Hardware Simulation and HDL Simulation results via waveform format.</li> <li><b>TySOM</b> - Embedded development boards and FMC daughter cards based on <a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> Zynq-7000 series targeting IoT, ADAS and Industrial Machine Vision.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Education">Education</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Aldec&action=edit&section=7" title="Edit section: Education"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 1999 the company contributed to the establishment of the "Aldec Digital Design Laboratory" at the <a href="/wiki/UNLV" class="mw-redirect" title="UNLV">UNLV</a>.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Aldec&action=edit&section=8" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/VHDL" title="VHDL">VHDL</a></li> <li><a href="/wiki/SystemC" title="SystemC">SystemC</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Aldec&action=edit&section=9" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text">EN-genius Programmable logic ZONE, <a rel="nofollow" class="external text" href="http://www.en-genius.net/site/zones/programmablelogicZONE/product_reviews/plp_050508">"Lattice And Aldec Form Alliance For FPGA Design And Design Verification"</a></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text">Richard Goering, <a rel="nofollow" class="external text" href="http://www.eetimes.com/story/OEG20001113S0089">"Aldec rolls out Linux-based mixed-language simulator"</a>, EETimes.com, November 13, 2000</span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text">Christine Evans-Pughe, <a rel="nofollow" class="external text" href="http://www.electronicsweekly.com/Articles/2006/10/13/39925/protecting+your+ip+just+got+simpler.htm">"Protecting your IP just got simpler"</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20061018072416/http://www.electronicsweekly.com/Articles/2006/10/13/39925/Protecting+your+IP+just+got+simpler.htm">Archived</a> 2006-10-18 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, Paragraph 11, Electronics Weekly, October 13, 2006</span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text">ECE-UNLV staff, <a rel="nofollow" class="external text" href="http://www.ee.unlv.edu/05EngNews.pdf">"ALDEC, (...) plays a significant role in ECE programs"</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20060720171452/http://www.ee.unlv.edu/05EngNews.pdf">Archived</a> 2006-07-20 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, Page 3, ECE-UNLV News, Vol 5, 2005</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Aldec&action=edit&section=10" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><span class="official-website"><span class="url"><a rel="nofollow" class="external text" href="https://www.aldec.com/">Official website</a></span></span> <span class="mw-valign-text-top" typeof="mw:File/Frameless"><a href="https://www.wikidata.org/wiki/Q4033684#P856" title="Edit this at Wikidata"><img alt="Edit this at Wikidata" src="//upload.wikimedia.org/wikipedia/en/thumb/8/8a/OOjs_UI_icon_edit-ltr-progressive.svg/10px-OOjs_UI_icon_edit-ltr-progressive.svg.png" decoding="async" width="10" height="10" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/8/8a/OOjs_UI_icon_edit-ltr-progressive.svg/15px-OOjs_UI_icon_edit-ltr-progressive.svg.png 1.5x, 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href="/wiki/Programmable_logic_array" title="Programmable logic array">PLA</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Generic_array_logic" class="mw-redirect" title="Generic array logic">GAL</a></li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">PSoC</a></li> <li><a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a> <ul><li><a href="/wiki/Xputer" title="Xputer">Xputer</a></li></ul></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li> <li><a href="/wiki/Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Verilog" title="Verilog">Verilog</a> <ul><li><a href="/wiki/Verilog-A" title="Verilog-A">A</a></li> <li><a href="/wiki/Verilog-AMS" title="Verilog-AMS">AMS</a></li></ul></li> <li><a href="/wiki/VHDL" title="VHDL">VHDL</a> <ul><li><a href="/wiki/VHDL-AMS" title="VHDL-AMS">AMS</a></li> <li><a href="/wiki/VHDL-VITAL" title="VHDL-VITAL">VITAL</a></li></ul></li> <li><a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a> <ul><li><a href="/wiki/SystemVerilog_DPI" title="SystemVerilog DPI">DPI</a></li></ul></li> <li><a href="/wiki/SystemC" title="SystemC">SystemC</a></li> <li><a href="/wiki/Altera_Hardware_Description_Language" title="Altera Hardware Description Language">AHDL</a></li> <li><a href="/wiki/Handel-C" title="Handel-C">Handel-C</a></li> <li><a href="/wiki/Lola_(computing)" title="Lola (computing)">Lola</a></li> <li><a href="/wiki/Property_Specification_Language" title="Property Specification Language">PSL</a></li> <li><a href="/wiki/Unified_Power_Format" title="Unified Power Format">UPF</a></li> <li><a href="/wiki/PALASM" title="PALASM">PALASM</a></li> <li><a href="/wiki/Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a></li> <li><a href="/wiki/Programmable_Array_Logic#CUPL" title="Programmable Array Logic">CUPL</a></li> <li><a href="/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li> <li><a href="/wiki/Flow_to_HDL" title="Flow to HDL">Flow to HDL</a></li> <li><a href="/wiki/MyHDL" title="MyHDL">MyHDL</a></li> <li><a href="/wiki/ELLA_(programming_language)" title="ELLA (programming language)">ELLA</a></li> <li><a href="/wiki/Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Accellera" title="Accellera">Accellera</a></li> <li><a href="/wiki/Achronix" title="Achronix">Achronix</a></li> <li><a href="/wiki/AMD" title="AMD">AMD</a></li> <li><a class="mw-selflink selflink">Aldec</a></li> <li><a href="/wiki/Arm_Holdings" title="Arm Holdings">Arm</a></li> <li><a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li> <li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a></li> <li><a href="/wiki/Intel" title="Intel">Intel</a></li> <li><a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li> <li><a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a></li> <li><a href="/wiki/Siemens" title="Siemens">Siemens</a></li> <li><a href="/wiki/Synopsys" title="Synopsys">Synopsys</a></li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ICE_(FPGA)" title="ICE (FPGA)">iCE</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Quartus_Prime" title="Intel Quartus Prime">Intel Quartus Prime</a></li> <li><a href="/wiki/Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li> <li><a href="/wiki/Vivado" title="Vivado">Vivado</a></li> <li><a href="/wiki/ModelSim" title="ModelSim">ModelSim</a></li> <li><a href="/wiki/Verilog-to-Routing" title="Verilog-to-Routing">VTR</a></li> <li><a href="/wiki/List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Intellectual_property" title="Intellectual property">Intellectual<br />property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li> <li><a href="/wiki/LEON" title="LEON">LEON</a></li> <li><a href="/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a></li> <li><a href="/wiki/Nios_embedded_processor" title="Nios embedded processor">Nios</a></li> <li><a href="/wiki/Nios_II" title="Nios II">Nios II</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Java_Optimized_Processor" title="Java Optimized Processor">JOP</a></li> <li><a href="/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a></li> <li><a href="/wiki/OpenCores" title="OpenCores">OpenCores</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a> <ul><li><a href="/wiki/OpenRISC_1200" title="OpenRISC 1200">1200</a></li></ul></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <ul><li><a href="/wiki/Libre-SOC" title="Libre-SOC">Libre-SOC</a></li> <li><a href="/wiki/OpenPOWER_Microwatt" title="OpenPOWER Microwatt">Microwatt</a></li></ul></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/Zet_(hardware)" title="Zet (hardware)">Zet</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div>    </div><noscript><img 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