<?xml version="1.0" encoding="UTF-8"?> <article key="pdf/10007406" mdate="2017-05-01 00:00:00"> <author>Mojtaba Valinataj</author> <title>Design of ParityPreserving Reversible Logic Signed Array Multipliers</title> <pages>260 - 267</pages> <year>2017</year> <volume>11</volume> <number>7</number> <journal>International Journal of Physical and Mathematical Sciences</journal> <ee>https://publications.waset.org/pdf/10007406</ee> <url>https://publications.waset.org/vol/127</url> <publisher>World Academy of Science, Engineering and Technology</publisher> <abstract>Reversible logic as a new favorable design domain can be used for various fields especially creating quantum computers because of its speed and intangible power consumption. However, its susceptibility to a variety of environmental effects may lead to yield the incorrect results. In this paper, because of the importance of multiplication operation in various computing systems, some novel reversible logic array multipliers are proposed with error detection capability by incorporating the paritypreserving gates. The new designs are presented for two main parts of array multipliers, partial product generation and multioperand addition, by exploiting the new arrangements of existing gates, which results in two signed paritypreserving array multipliers. The experimental results reveal that the best proposed 4&amp;amp;times;4 multiplier in this paper reaches 12, 24, and 26 enhancements in the number of constant inputs, number of required gates, and quantum cost, respectively, compared to previous design. Moreover, the best proposed design is generalized for n&amp;amp;times;n multipliers with general formulations to estimate the main reversible logic criteria as the functions of the multiplier size.</abstract> <index>Open Science Index 127, 2017</index> </article>