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This includes important industry information and key content from major SEMI events. </div> </div> </div> <div class="content"> <table border="0"><tbody style="width: 1px;"><tr><td colspan="3" valign="top"><p>SEMI Membership is required to access these SEMI Members Only content. If your company is a SEMI member, but you do not have a profile <a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/UserIdentification.aspx" target="_top">create one now</a>. Be sure to use your company e-mail when you create or update your profile. SEMI recognizes your membership status using your company email address.</p><p><strong>Not yet a SEMI Member?</strong>  <a href="https://web.archive.org/web/20140629120535/http://www.semi.org/membership">Learn more</a> about SEMI Membership or <a href="https://web.archive.org/web/20140629120535/https://dom.semi.org/membership.nsf/membershipapplication!openform">apply for SEMI membership online</a>.</p></td></tr><tr><td valign="top"><h2><strong> </strong><span style="font-size: small;"><strong>Recent Event Highlights</strong></span></h2><p><a href="https://web.archive.org/web/20140629120535/http://www.semi.org/en/node/50146">SEMI Member Day 2014</a><br/>May 29,2014</p><p><span style="font-size: small;"><a href="https://web.archive.org/web/20140629120535/http://www.semi.org/en/node/49621">SEMI Silicon Breakfast Forum</a><a href="https://web.archive.org/web/20140629120535/http://www.semi.org/en/node/49621">: Internet of Things</a><br/>April 17, 2014 </span></p><p><a href="https://web.archive.org/web/20140629120535/http://www.semi.org/en/node/49491">SEMI Northeast Forum: Wafers to Wall Street - A Semiconductor Outlook</a><br/>March 24, 2014 </p><p><a href="https://web.archive.org/web/20140629120535/http://www.semi.org/en/node/49806">The 450mm Wafer Size Transition - Opportunities for Europe</a><br/>February 7, 2014</p><p><a href="https://web.archive.org/web/20140629120535/http://www.semi.org/en/node/48761">Industry Strategy Symposium 2014</a><br/>January 12-14, 2014 </p><p><a href="https://web.archive.org/web/20140629120535/http://www.semi.org/en/node/49816">SEMI Malaysia Forum</a><br/>November 20, 2013</p><p><a href="https://web.archive.org/web/20140629120535/http://www.semi.org/en/node/47806">Annual SEMI Texas Fall Outlook</a><br/>October 30, 2013</p><p><a href="https://web.archive.org/web/20140629120535/http://www.semi.org/en/node/47746">Strategic Materials Conference</a><br/>October 16-17, 2013 </p><p><a href="https://web.archive.org/web/20140629120535/http://www.semi.org/en/node/47741/">MEMS Tech Seminar</a><br/>September 26, 2013</p></td><td style="width: 10px;"> </td><td valign="top"><h2><strong> </strong><span style="font-size: small;"><strong>SEMI Webinars</strong></span></h2><p><a href="/web/20140629120535/http://semi.org/en/node/38101">Access recorded presentations and download slides from past featured webinars</a></p><ul><li><a href="/web/20140629120535/http://semi.org/en/node/38101">Semiconductor Webinar Series</a></li><li><a href="/web/20140629120535/http://semi.org/en/node/38101">LED Webinar Series</a></li><li><a href="/web/20140629120535/http://semi.org/en/node/38101">Photovoltaic/solar Webinars</a></li><li><a href="/web/20140629120535/http://semi.org/en/node/38101#Regional Update Webinars">SEMI Americas Membership Updates</a></li></ul>              </td></tr><tr><td valign="top"><h2><span style="font-size: small;"><strong>Event Archive</strong></span></h2><strong>Highlighted Content from Past SEMI Events</strong><ul><li><a href="/web/20140629120535/http://semi.org/en/node/38096">Event Highlight Archive</a></li></ul></td><td> </td><td valign="top"><h2><span style="font-size: small;"><strong> </strong><strong>Industry Research & Statistics</strong></span></h2><ul><li><a href="/web/20140629120535/http://semi.org/en/node/43731">Semiconductor Equipment Briefs</a></li><li><a href="/web/20140629120535/http://semi.org/en/node/43781">Semiconductor Materials Briefs</a></li><li><a href="/web/20140629120535/http://semi.org/en/node/43786">PV Quarterly Outlooks</a></li></ul></td></tr></tbody></table><h2><span style="font-size: small;">SEMI Member Logo</span></h2><table cellpadding="0"><tbody><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="/web/20140629120535/http://semi.org/en/node/36966">SEMI Member Logo Download<br/></a>SEMI has developed a special membership logo for SEMI Members to display notice of their association membership in exhibit booths and on letterheads, advertisement, and other printed matter. Available in web and print versions to SEMI Members Only. </div></td></tr></tbody></table><table cellpadding="0"><tbody><tr><td colspan="2" valign="top"> </td></tr><tr><td colspan="2" valign="top"><h2 style="font-size: 12px;"><span style="font-size: small; border-collapse: separate;">Semiconductor Equipment</span></h2></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1699">SEMI Equipment Brief: Wafer Fab Brief (PDF)</a><br/>Semiconductor fabrication consists of a series of processes in which a device structure is manufactured by applying a series of layers onto a substrate, most commonly on silicon. This involves the deposition and removal of various thin film layers. The areas of the thin film that are to be deposited or removed are controlled through photolithography. Each deposition and removal process is generally followed by cleaning as well as inspection steps. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1698">SEMI Equipment Brief: Test Equipment (PDF)</a><br/>There are various types of electrical and reliability tests conducted at different stages of assembly and for different purposes once the wafer fabrication process is finished. Tests include die sort test on wafers, electrical and environmental testing, and burn-in on packaged devices. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1696">SEMI Equipment Brief: Assembly and Packaging (PDF)</a><br/>There are two main purposes for assembling the bare semiconductor device into a package. First, the package provides mechanical and environmental protection to the bare die. Second, the package provides an electrical connection between the die and the printed circuit board (PCB). Nowadays, there are a tremendous number of package types, form factors, and process techniques used in assembly and packaging. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1697">SEMI Equipment Brief: Other Front-End Equipment Brief (PDF)</a><br/>Other Front-End equipment is a “catch-all” phrase for equipment that is used in frontend manufacturing but not in wafer processing. It includes: Wafer Manufacturing equipment, Photomask/Reticle equipment and Fabrication Facility equipment. </div></td></tr></tbody></table><table cellpadding="0"><tbody><tr><td colspan="2" valign="top"><h2><span style="font-size: small; border-collapse: separate;">Semiconductor Materials</span></h2></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1703">SEMI Materials Brief: Silicon-on-Insulator (SOI) Wafers (PDF)</a><br/>Silicon-on-insulator (SOI) wafers were first developed for military applications in the 1960s. During the past 45 years, SOI technology has evolved and is being be adopted in the production of very sophisticated semiconductor devices. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1704">SEMI Materials Brief: Sputtering Targets (PDF)</a><br/>Sputtering is a type of physical vapor deposition (PVD) that is used to deposit thin films onto various surfaces (e.g. semiconductor wafers) by physical means, as compared to chemical vapor deposition (CVD). In PVD, the target source is bombarded with argon ions, which knock off atoms from the target that coat a receiving wafer creating a uniform metal film on the wafer. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1707">SEMI Materials Brief: Semiconductor Process Chemicals (PDF)</a><br/>The International Technology Road Map for Semiconductors (ITRS) outlines increasingly higher chemical purity levels required by the semiconductor industry. Currently, there are several grades of chemicals available, and the migration to the highest purity levels has been relatively slow. This can be attributed to the substantially higher costs associated with producing these chemicals and their associated higher prices. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1701">SEMI Materials Brief: Organic Substrates (PDF)</a><br/>In the past decade, high volume IC packaging has shifted from the era of ceramic packages to organic substrate-based packages, especially the plastic ball grid array (PBGA). The shift from ceramic to laminate substrates for packaging central processing unit (CPU) microprocessors facilitated this migration to organic substrates by providing a volume application that enabled the technology to mature faster. Flex circuit or tape substrates are a niche market for large die packaging, but are also used in volume for chip scale packages (CSPs) including some stacked die packages. Increasingly many of the new CSP designs are using a rigid laminate substrate rather than flex circuit. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1702">SEMI Materials Brief: Leadframes (PDF)</a><br/>A leadframe consists of a die mounting paddle and lead fingers. The die paddle serves primarily to mechanically support the die during package manufacture. The lead fingers connect the die to the circuitry external to the package. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1708">SEMI Materials Brief: Die Attach Materials (PDF)</a><br/>Die attach materials provide the mechanical and thermal connection between the semiconductor device and the package. These materials are used in paste, tape or solder form. This market brief covers paste and tape materials only. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1705">SEMI Materials Brief: Encapsulant Materials (PDF)</a><br/>Encapsulant materials are polymeric-based materials used to provide mechanical and environmental protection of a semiconductor device. Mold compounds, underfill, and liquid encapsulants fall into this category. At the most basic level, these materials are formulated using a combination of raw materials: organic resins, fillers, catalysts, and a pigment or coloration. Additives include flame retardants, adhesion promoters, mold release materials, ion traps, and stress relievers. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1706">SEMI Materials Brief: Bonding Wire (PDF)</a><br/>Wire bonding is used throughout the microelectronics industry as a means of interconnecting chips, substrates, and output pins. Wire forms the connections between the bond pad on the IC and the bonding fingers of the leadframe, plastic laminate, or ceramic substrate. The bonding method utilized is a function of the wire material and the substrate. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1709">SEMI Materials Brief: Semiconductor Photoresists (PDF)</a><br/>Improvements in semiconductor performance continue to be made, largely driven by advances in optical lithography equipment, photomask, and photoresist (resist) materials. In particular, the design and development of photoresists that are sensitive to short exposure wavelengths have enabled the industry to migrate to smaller device sizes. Photoresist allows precise pattern formation upon exposure to light through a template called a photomask and subsequent etching of portions of the photoresist, resulting in the permanent transfer of patterns to the wafer substrate. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1700">SEMI Materials Brief: Prime Polished Silicon Wafers (PDF)</a><br/>A wafer is a thin slice of semiconducting material upon which microcircuits are constructed by doping (via diffusion or ion implantation), chemical etching, and deposition of various materials. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1712">SEMI Materials Brief: Semiconductor Photoresist Removers (PDF)</a><br/>Removal Materials are wet chemical solutions used to remove the photoresist left on the wafer after processing as well as for cleaning wafers immediately after etch processes on aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), dielectric oxides, and polysilicon surfaces. Resist removal for greater than 0.50 micron geometries is referred to as a wet-wet process, since these chemical solutions are used to remove both the photoresist mask and photoresist residues. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1710">SEMI Materials Brief: Polycrystalline Silicon (PDF)</a><br/>Polycrystalline silicon, also called poly or polysilicon, is one of the purest materials ever manufactured by mankind. Nonetheless, much work is still being done to reduce metal contamination levels and improve uniformity. It is used as the charge material in the silicon ingot growth process and therefore dictates the purity of wafers. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1715">Materials Brief: Semiconductor Photomasks (PDF)</a><br/>A photomask, also called a reticle, is a transparent glass or quartz plate with an array of patterns or images. These materials permit the passage of light in intricate and precise patterns. The patterns or images emerge by creating transparent and opaque regions on the plate through the photolithography process in semiconductor manufacturing. Each pattern consists of opaque and transparent areas that precisely control the passage of light to cast the image of the size and shape of the device elements in a semiconductor circuit. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1714">SEMI Materials Brief: Epitaxial or Epi Silicon Wafers (PDF)</a><br/>There are two types of epitaxial or epi silicon wafers used in the semiconductor industry: discrete and MOS. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1711">SEMI Materials Brief: Chemical Mechanical Planarization Materials (PDF)</a><br/>The manufacture of a semiconductor device is essentially achieved by building alternating layers of metal and insulator materials on a silicon substrate. Prior to the 1990s Chemical Mechanical Planarization (CMP) was looked on as too "dirty" to be included in high-precision fabrication processes, since abrasion tends to create particles and the abrasives themselves are not without impurities. However, given the small size and complexity of today’s advanced semiconductor devices, it is essential that these layers be extremely flat for lithographic processing. In order to achieve the required flatness, CMP is utilized. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1713">SEMI Materials Brief: Semiconductor Photoresists Developers (PDF)</a><br/>Aqueous or water-based developers are used in the lithography process to pattern photoresist films immediately after the exposure process. For positive photoresists, the developer removes film in the exposed wafer regions to produce device patterns. For negative photoresists, the developer removes film in the unexposed wafer regions to produce device patterns. </div></td></tr><tr><td valign="top"><img src="/web/20140629120535im_/http://semi.org/sites/semi.org/files/cms/fragments//semi_en_idoc_dynamic_list/moecicon.gif" alt="Member Only Content" hspace="0" vspace="2" border="0"/></td><td><div style="font-size: 12px;"><a href="https://web.archive.org/web/20140629120535/http://ams.semi.org/ebusiness/CustomerService/MemberDownloadDocument.aspx?ID=1716">SEMI Materials Brief: Semiconductor Anti-Reflective Coatings (PDF)</a><br/>Extending performance of lithography and photoresists to meet shrinking device requirements is challenged by film properties on levels such as polysilicon, aluminum, and copper. Patterning devices during lithography exposure is difficult due to the highly reflective nature of these films, varying photoresist thickness, and device topography. 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