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class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Precursors"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>Precursors</span> </div> </a> <ul id="toc-Precursors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Single_MOS_DRAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Single_MOS_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2</span> <span>Single MOS DRAM</span> </div> </a> <ul id="toc-Single_MOS_DRAM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Principles_of_operation" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Principles_of_operation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Principles of operation</span> </div> </a> <button aria-controls="toc-Principles_of_operation-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Principles of operation subsection</span> </button> <ul id="toc-Principles_of_operation-sublist" class="vector-toc-list"> <li id="toc-Operations_to_read_a_data_bit_from_a_DRAM_storage_cell" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Operations_to_read_a_data_bit_from_a_DRAM_storage_cell"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Operations to read a data bit from a DRAM storage cell</span> </div> </a> <ul id="toc-Operations_to_read_a_data_bit_from_a_DRAM_storage_cell-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-To_write_to_memory" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#To_write_to_memory"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>To write to memory</span> </div> </a> <ul id="toc-To_write_to_memory-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Refresh_rate" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Refresh_rate"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Refresh rate</span> </div> </a> <ul id="toc-Refresh_rate-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Memory_timing" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Memory_timing"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>Memory timing</span> </div> </a> <ul id="toc-Memory_timing-sublist" class="vector-toc-list"> <li id="toc-Timing_abbreviations" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Timing_abbreviations"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.1</span> <span>Timing abbreviations</span> </div> </a> <ul id="toc-Timing_abbreviations-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Memory_cell_design" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Memory_cell_design"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Memory cell design</span> </div> </a> <button aria-controls="toc-Memory_cell_design-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Memory cell design subsection</span> </button> <ul id="toc-Memory_cell_design-sublist" class="vector-toc-list"> <li id="toc-Capacitor_design" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Capacitor_design"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Capacitor design</span> </div> </a> <ul id="toc-Capacitor_design-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Historical_cell_designs" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Historical_cell_designs"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Historical cell designs</span> </div> </a> <ul id="toc-Historical_cell_designs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Proposed_cell_designs" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Proposed_cell_designs"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Proposed cell designs</span> </div> </a> <ul id="toc-Proposed_cell_designs-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Array_structures" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Array_structures"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Array structures</span> </div> </a> <button aria-controls="toc-Array_structures-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Array structures subsection</span> </button> <ul id="toc-Array_structures-sublist" class="vector-toc-list"> <li id="toc-Bitline_architecture" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Bitline_architecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1</span> <span>Bitline architecture</span> </div> </a> <ul id="toc-Bitline_architecture-sublist" class="vector-toc-list"> <li id="toc-Open_bitline_arrays" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Open_bitline_arrays"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1.1</span> <span>Open bitline arrays</span> </div> </a> <ul id="toc-Open_bitline_arrays-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Folded_bitline_arrays" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Folded_bitline_arrays"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1.2</span> <span>Folded bitline arrays</span> </div> </a> <ul id="toc-Folded_bitline_arrays-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Future_array_architectures" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Future_array_architectures"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1.3</span> <span>Future array architectures</span> </div> </a> <ul id="toc-Future_array_architectures-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Row_and_column_redundancy" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Row_and_column_redundancy"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.2</span> <span>Row and column redundancy</span> </div> </a> <ul id="toc-Row_and_column_redundancy-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Error_detection_and_correction" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Error_detection_and_correction"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Error detection and correction</span> </div> </a> <ul id="toc-Error_detection_and_correction-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Security" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Security"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Security</span> </div> </a> <button aria-controls="toc-Security-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Security subsection</span> </button> <ul id="toc-Security-sublist" class="vector-toc-list"> <li id="toc-Data_remanence" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Data_remanence"> <div class="vector-toc-text"> <span class="vector-toc-numb">6.1</span> <span>Data remanence</span> </div> </a> <ul id="toc-Data_remanence-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Memory_corruption" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Memory_corruption"> <div class="vector-toc-text"> <span class="vector-toc-numb">6.2</span> <span>Memory corruption</span> </div> </a> <ul id="toc-Memory_corruption-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Packaging" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Packaging"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Packaging</span> </div> </a> <button aria-controls="toc-Packaging-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Packaging subsection</span> </button> <ul id="toc-Packaging-sublist" class="vector-toc-list"> <li id="toc-Memory_module" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Memory_module"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.1</span> <span>Memory module</span> </div> </a> <ul id="toc-Memory_module-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Embedded" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Embedded"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.2</span> <span>Embedded</span> </div> </a> <ul id="toc-Embedded-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Versions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Versions"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Versions</span> </div> </a> <button aria-controls="toc-Versions-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Versions subsection</span> </button> <ul id="toc-Versions-sublist" class="vector-toc-list"> <li id="toc-Asynchronous_DRAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Asynchronous_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1</span> <span>Asynchronous DRAM</span> </div> </a> <ul id="toc-Asynchronous_DRAM-sublist" class="vector-toc-list"> <li id="toc-Principles_of_operation_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Principles_of_operation_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.1</span> <span>Principles of operation</span> </div> </a> <ul id="toc-Principles_of_operation_2-sublist" class="vector-toc-list"> <li id="toc-RAS-only_refresh" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#RAS-only_refresh"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.1.1</span> <span>RAS-only refresh</span> </div> </a> <ul id="toc-RAS-only_refresh-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-CAS_before_RAS_refresh" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#CAS_before_RAS_refresh"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.1.2</span> <span>CAS before RAS refresh</span> </div> </a> <ul id="toc-CAS_before_RAS_refresh-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Hidden_refresh" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Hidden_refresh"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.1.3</span> <span>Hidden refresh</span> </div> </a> <ul id="toc-Hidden_refresh-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Page_mode_DRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Page_mode_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.2</span> <span>Page mode DRAM</span> </div> </a> <ul id="toc-Page_mode_DRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Extended_data_out_DRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Extended_data_out_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.3</span> <span>Extended data out DRAM</span> </div> </a> <ul id="toc-Extended_data_out_DRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Burst_EDO_DRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Burst_EDO_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.4</span> <span>Burst EDO DRAM</span> </div> </a> <ul id="toc-Burst_EDO_DRAM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Synchronous_dynamic_RAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Synchronous_dynamic_RAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2</span> <span>Synchronous dynamic RAM</span> </div> </a> <ul id="toc-Synchronous_dynamic_RAM-sublist" class="vector-toc-list"> <li id="toc-Single_data_rate_synchronous_DRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Single_data_rate_synchronous_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2.1</span> <span>Single data rate synchronous DRAM</span> </div> </a> <ul id="toc-Single_data_rate_synchronous_DRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Double_data_rate_synchronous_DRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Double_data_rate_synchronous_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2.2</span> <span>Double data rate synchronous DRAM</span> </div> </a> <ul id="toc-Double_data_rate_synchronous_DRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Direct_Rambus_DRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Direct_Rambus_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2.3</span> <span>Direct Rambus DRAM</span> </div> </a> <ul id="toc-Direct_Rambus_DRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Reduced_Latency_DRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Reduced_Latency_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2.4</span> <span>Reduced Latency DRAM</span> </div> </a> <ul id="toc-Reduced_Latency_DRAM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Graphics_RAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Graphics_RAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.3</span> <span>Graphics RAM</span> </div> </a> <ul id="toc-Graphics_RAM-sublist" class="vector-toc-list"> <li id="toc-Video_DRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Video_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.3.1</span> <span>Video DRAM</span> </div> </a> <ul id="toc-Video_DRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Window_DRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Window_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.3.2</span> <span>Window DRAM</span> </div> </a> <ul id="toc-Window_DRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Multibank_DRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Multibank_DRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.3.3</span> <span>Multibank DRAM</span> </div> </a> <ul id="toc-Multibank_DRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Synchronous_graphics_RAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Synchronous_graphics_RAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.3.4</span> <span>Synchronous graphics RAM</span> </div> </a> <ul id="toc-Synchronous_graphics_RAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Graphics_double_data_rate_SDRAM" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Graphics_double_data_rate_SDRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.3.5</span> <span>Graphics double data rate SDRAM</span> </div> </a> <ul id="toc-Graphics_double_data_rate_SDRAM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Pseudostatic_RAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Pseudostatic_RAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.4</span> <span>Pseudostatic RAM</span> </div> </a> <ul id="toc-Pseudostatic_RAM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" title="Table of Contents" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet 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Available in 45 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-45" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">45 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-af mw-list-item"><a href="https://af.wikipedia.org/wiki/Dinamiese_ewetoeganklike_geheue" title="Dinamiese ewetoeganklike geheue – Afrikaans" lang="af" hreflang="af" data-title="Dinamiese ewetoeganklike geheue" data-language-autonym="Afrikaans" data-language-local-name="Afrikaans" class="interlanguage-link-target"><span>Afrikaans</span></a></li><li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%B0%D8%A7%D9%83%D8%B1%D8%A9_%D9%88%D8%B5%D9%88%D9%84_%D8%B9%D8%B4%D9%88%D8%A7%D8%A6%D9%8A_%D8%AD%D8%B1%D9%83%D9%8A%D8%A9" title="ذاكرة وصول عشوائي حركية – Arabic" lang="ar" hreflang="ar" data-title="ذاكرة وصول عشوائي حركية" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ast mw-list-item"><a href="https://ast.wikipedia.org/wiki/DRAM" title="DRAM – Asturian" lang="ast" hreflang="ast" data-title="DRAM" data-language-autonym="Asturianu" data-language-local-name="Asturian" class="interlanguage-link-target"><span>Asturianu</span></a></li><li class="interlanguage-link interwiki-be-x-old mw-list-item"><a href="https://be-tarask.wikipedia.org/wiki/DRAM" title="DRAM – Belarusian (Taraškievica orthography)" lang="be-tarask" hreflang="be-tarask" data-title="DRAM" data-language-autonym="Беларуская (тарашкевіца)" data-language-local-name="Belarusian (Taraškievica orthography)" class="interlanguage-link-target"><span>Беларуская (тарашкевіца)</span></a></li><li class="interlanguage-link interwiki-bg mw-list-item"><a href="https://bg.wikipedia.org/wiki/%D0%94%D0%B8%D0%BD%D0%B0%D0%BC%D0%B8%D1%87%D0%BD%D0%B0_%D0%BF%D0%B0%D0%BC%D0%B5%D1%82_%D1%81_%D0%BF%D1%80%D0%BE%D0%B8%D0%B7%D0%B2%D0%BE%D0%BB%D0%B5%D0%BD_%D0%B4%D0%BE%D1%81%D1%82%D1%8A%D0%BF" title="Динамична памет с произволен достъп – Bulgarian" lang="bg" hreflang="bg" data-title="Динамична памет с произволен достъп" data-language-autonym="Български" data-language-local-name="Bulgarian" class="interlanguage-link-target"><span>Български</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/DRAM" title="DRAM – Catalan" lang="ca" hreflang="ca" data-title="DRAM" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/DRAM" title="DRAM – Czech" lang="cs" hreflang="cs" data-title="DRAM" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Dynamic_Random_Access_Memory" title="Dynamic Random Access Memory – German" lang="de" hreflang="de" data-title="Dynamic Random Access Memory" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/D%C3%BCnaamiline_muutm%C3%A4lu" title="Dünaamiline muutmälu – Estonian" lang="et" hreflang="et" data-title="Dünaamiline muutmälu" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/DRAM" title="DRAM – Spanish" lang="es" hreflang="es" data-title="DRAM" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eu mw-list-item"><a href="https://eu.wikipedia.org/wiki/DRAM" title="DRAM – Basque" lang="eu" hreflang="eu" data-title="DRAM" data-language-autonym="Euskara" data-language-local-name="Basque" class="interlanguage-link-target"><span>Euskara</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%AD%D8%A7%D9%81%D8%B8%D9%87_%D8%AA%D8%B5%D8%A7%D8%AF%D9%81%DB%8C_%D9%BE%D9%88%DB%8C%D8%A7" title="حافظه تصادفی پویا – Persian" lang="fa" hreflang="fa" data-title="حافظه تصادفی پویا" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/M%C3%A9moire_vive_dynamique" title="Mémoire vive dynamique – French" lang="fr" hreflang="fr" data-title="Mémoire vive dynamique" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EB%8F%99%EC%A0%81_%EB%9E%A8" title="동적 램 – Korean" lang="ko" hreflang="ko" data-title="동적 램" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/DRAM" title="DRAM – Croatian" lang="hr" hreflang="hr" data-title="DRAM" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target"><span>Hrvatski</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Memori_akses_acak_dinamis" title="Memori akses acak dinamis – Indonesian" lang="id" hreflang="id" data-title="Memori akses acak dinamis" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/DRAM" title="DRAM – Italian" lang="it" hreflang="it" data-title="DRAM" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/DRAM" title="DRAM – Hebrew" lang="he" hreflang="he" data-title="DRAM" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-kk mw-list-item"><a href="https://kk.wikipedia.org/wiki/%D0%94%D0%B8%D0%BD%D0%B0%D0%BC%D0%B8%D0%BA%D0%B0%D0%BB%D1%8B%D2%9B_%D0%B6%D0%B0%D0%B4" title="Динамикалық жад – Kazakh" lang="kk" hreflang="kk" data-title="Динамикалық жад" data-language-autonym="Қазақша" data-language-local-name="Kazakh" class="interlanguage-link-target"><span>Қазақша</span></a></li><li class="interlanguage-link interwiki-la mw-list-item"><a href="https://la.wikipedia.org/wiki/Memoria_volatilis_dynamica" title="Memoria volatilis dynamica – Latin" lang="la" hreflang="la" data-title="Memoria volatilis dynamica" data-language-autonym="Latina" data-language-local-name="Latin" class="interlanguage-link-target"><span>Latina</span></a></li><li class="interlanguage-link interwiki-lt mw-list-item"><a href="https://lt.wikipedia.org/wiki/Dinamin%C4%97_atmintis" title="Dinaminė atmintis – Lithuanian" lang="lt" hreflang="lt" data-title="Dinaminė atmintis" data-language-autonym="Lietuvių" data-language-local-name="Lithuanian" class="interlanguage-link-target"><span>Lietuvių</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/DRAM" title="DRAM – Hungarian" lang="hu" hreflang="hu" data-title="DRAM" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-mk mw-list-item"><a href="https://mk.wikipedia.org/wiki/%D0%94%D0%B8%D0%BD%D0%B0%D0%BC%D0%B8%D1%87%D0%BA%D0%B0_%D0%BC%D0%B5%D0%BC%D0%BE%D1%80%D0%B8%D1%98%D0%B0_%D1%81%D0%BE_%D1%81%D0%BB%D1%83%D1%87%D0%B0%D0%B5%D0%BD_%D0%BF%D1%80%D0%B8%D1%81%D1%82%D0%B0%D0%BF" title="Динамичка меморија со случаен пристап – Macedonian" lang="mk" hreflang="mk" data-title="Динамичка меморија со случаен пристап" data-language-autonym="Македонски" data-language-local-name="Macedonian" class="interlanguage-link-target"><span>Македонски</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%A1%E0%B5%88%E0%B4%A8%E0%B4%BE%E0%B4%AE%E0%B4%BF%E0%B4%95%E0%B5%8D_%E0%B4%B1%E0%B4%BE%E0%B5%BB%E0%B4%A1%E0%B4%82-%E0%B4%86%E0%B4%95%E0%B5%8D%E0%B4%B8%E0%B4%B8%E0%B5%8D_%E0%B4%AE%E0%B5%86%E0%B4%AE%E0%B5%8D%E0%B4%AE%E0%B4%B1%E0%B4%BF" title="ഡൈനാമിക് റാൻഡം-ആക്സസ് മെമ്മറി – Malayalam" lang="ml" hreflang="ml" data-title="ഡൈനാമിക് റാൻഡം-ആക്സസ് മെമ്മറി" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory – Dutch" lang="nl" hreflang="nl" data-title="Dynamic random-access memory" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/Dynamic_Random_Access_Memory" title="Dynamic Random Access Memory – Japanese" lang="ja" hreflang="ja" data-title="Dynamic Random Access Memory" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/DRAM" title="DRAM – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="DRAM" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Pami%C4%99%C4%87_dynamiczna_(informatyka)" title="Pamięć dynamiczna (informatyka) – Polish" lang="pl" hreflang="pl" data-title="Pamięć dynamiczna (informatyka)" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Dynamic_random_access_memory" title="Dynamic random access memory – Portuguese" lang="pt" hreflang="pt" data-title="Dynamic random access memory" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Memorie_DRAM" title="Memorie DRAM – Romanian" lang="ro" hreflang="ro" data-title="Memorie DRAM" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/DRAM" title="DRAM – Russian" lang="ru" hreflang="ru" data-title="DRAM" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sq mw-list-item"><a href="https://sq.wikipedia.org/wiki/Kujtes%C3%AB_hyr%C3%ABse_e_fuqishme_rast%C3%ABsore" title="Kujtesë hyrëse e fuqishme rastësore – Albanian" lang="sq" hreflang="sq" data-title="Kujtesë hyrëse e fuqishme rastësore" data-language-autonym="Shqip" data-language-local-name="Albanian" class="interlanguage-link-target"><span>Shqip</span></a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory – Simple English" lang="en-simple" hreflang="en-simple" data-title="Dynamic random-access memory" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target"><span>Simple English</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/DRAM" title="DRAM – Slovak" lang="sk" hreflang="sk" data-title="DRAM" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/%D0%94%D0%B8%D0%BD%D0%B0%D0%BC%D0%B8%D1%87%D0%BA%D0%B8_RAM" title="Динамички RAM – Serbian" lang="sr" hreflang="sr" data-title="Динамички RAM" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-sh mw-list-item"><a href="https://sh.wikipedia.org/wiki/Dinami%C4%8Dki_RAM" title="Dinamički RAM – Serbo-Croatian" lang="sh" hreflang="sh" data-title="Dinamički RAM" data-language-autonym="Srpskohrvatski / српскохрватски" data-language-local-name="Serbo-Croatian" class="interlanguage-link-target"><span>Srpskohrvatski / српскохрватски</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/DRAM" title="DRAM – Finnish" lang="fi" hreflang="fi" data-title="DRAM" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/Dynamiskt_minne" title="Dynamiskt minne – Swedish" lang="sv" hreflang="sv" data-title="Dynamiskt minne" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/%E0%B8%AB%E0%B8%99%E0%B9%88%E0%B8%A7%E0%B8%A2%E0%B8%84%E0%B8%A7%E0%B8%B2%E0%B8%A1%E0%B8%88%E0%B8%B3%E0%B9%80%E0%B8%82%E0%B9%89%E0%B8%B2%E0%B8%96%E0%B8%B6%E0%B8%87%E0%B9%82%E0%B8%94%E0%B8%A2%E0%B8%AA%E0%B8%B8%E0%B9%88%E0%B8%A1%E0%B9%81%E0%B8%9A%E0%B8%9A%E0%B8%9E%E0%B8%A5%E0%B8%A7%E0%B8%B1%E0%B8%95" title="หน่วยความจำเข้าถึงโดยสุ่มแบบพลวัต – Thai" lang="th" hreflang="th" data-title="หน่วยความจำเข้าถึงโดยสุ่มแบบพลวัต" data-language-autonym="ไทย" data-language-local-name="Thai" class="interlanguage-link-target"><span>ไทย</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/DRAM_(bilgisayar)" title="DRAM (bilgisayar) – Turkish" lang="tr" hreflang="tr" data-title="DRAM (bilgisayar)" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/DRAM" title="DRAM – Ukrainian" lang="uk" hreflang="uk" data-title="DRAM" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/RAM_%C4%91%E1%BB%99ng" title="RAM động – Vietnamese" lang="vi" hreflang="vi" data-title="RAM động" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-wuu mw-list-item"><a href="https://wuu.wikipedia.org/wiki/%E5%8A%A8%E6%80%81%E9%9A%8F%E6%9C%BA%E5%AD%98%E5%8F%96%E5%AD%98%E5%82%A8%E5%99%A8" title="动态随机存取存储器 – Wu" lang="wuu" hreflang="wuu" data-title="动态随机存取存储器" data-language-autonym="吴语" data-language-local-name="Wu" class="interlanguage-link-target"><span>吴语</span></a></li><li class="interlanguage-link interwiki-zh-yue mw-list-item"><a href="https://zh-yue.wikipedia.org/wiki/DRAM" title="DRAM – Cantonese" lang="yue" hreflang="yue" data-title="DRAM" data-language-autonym="粵語" data-language-local-name="Cantonese" class="interlanguage-link-target"><span>粵語</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/%E5%8A%A8%E6%80%81%E9%9A%8F%E6%9C%BA%E5%AD%98%E5%82%A8%E5%99%A8" title="动态随机存储器 – Chinese" lang="zh" hreflang="zh" data-title="动态随机存储器" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q189396#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div 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class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Type of computer memory</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">"DRAM" redirects here. For other uses, see <a href="/wiki/Dram_(disambiguation)" class="mw-redirect mw-disambig" title="Dram (disambiguation)">Dram</a>.</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Transistorized memory, such as RAM, ROM, flash and cache sizes as well as file sizes are specified using <a href="/wiki/Binary_prefix" title="Binary prefix">binary meanings</a> for K (1024<sup>1</sup>), M (1024<sup>2</sup>), G (1024<sup>3</sup>), etc.</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:MT4C1024-HD.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/9b/MT4C1024-HD.jpg/310px-MT4C1024-HD.jpg" decoding="async" width="310" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/9b/MT4C1024-HD.jpg/465px-MT4C1024-HD.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/9b/MT4C1024-HD.jpg/620px-MT4C1024-HD.jpg 2x" data-file-width="10944" data-file-height="5312" /></a><figcaption>A <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">die</a> photograph of the <a href="/wiki/Micron_Technology" title="Micron Technology">Micron Technology</a> MT4C1024 DRAM <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> (1994). It has a capacity of 1 <a href="/wiki/Megabit" class="mw-redirect" title="Megabit">megabit</a> equivalent to <span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle 2^{20}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msup> <mn>2</mn> <mrow class="MJX-TeXAtom-ORD"> <mn>20</mn> </mrow> </msup> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle 2^{20}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/30ccc1bd960deeb4fa9aa01b7e403c5e67dd1de4" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.338ex; width:3.039ex; height:2.676ex;" alt="{\displaystyle 2^{20}}" /></span>bits or <span class="nowrap">128 <a href="/wiki/KiB" class="mw-redirect" title="KiB">KiB</a>.</span><sup id="cite_ref-mt4acid_1-0" class="reference"><a href="#cite_note-mt4acid-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup></figcaption></figure> <style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output .hlist dt::after{content:": "}.mw-parser-output .hlist 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href="/wiki/Computer_memory" title="Computer memory">Computer memory</a> and <a href="/wiki/Computer_data_storage" title="Computer data storage">data storage</a> types</th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">General</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Memory_coherence" title="Memory coherence">Memory coherence</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">Cache coherence</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a></li> <li><a href="/wiki/Memory_access_pattern" title="Memory access pattern">Memory access pattern</a></li> <li><a href="/wiki/Memory_map" title="Memory map">Memory map</a></li> <li><a href="/wiki/Computer_data_storage#Secondary_storage" title="Computer data storage">Secondary storage</a></li> <li><a href="/wiki/Semiconductor_memory" title="Semiconductor memory">MOS memory</a> <ul><li><a href="/wiki/Floating-gate_MOSFET" title="Floating-gate MOSFET">floating-gate</a></li></ul></li> <li><a href="/wiki/Continuous_availability" title="Continuous availability">Continuous availability</a></li> <li><a href="/wiki/Areal_density_(computer_storage)" class="mw-redirect" title="Areal density (computer storage)">Areal density (computer storage)</a></li> <li><a href="/wiki/Block_(data_storage)" title="Block (data storage)">Block (data storage)</a></li> <li><a href="/wiki/Object_storage" title="Object storage">Object storage</a></li> <li><a href="/wiki/Direct-attached_storage" title="Direct-attached storage">Direct-attached storage</a></li> <li><a href="/wiki/Network-attached_storage" title="Network-attached storage">Network-attached storage</a> <ul><li><a href="/wiki/Storage_area_network" title="Storage area network">Storage area network</a></li> <li><a href="/wiki/Block-level_storage" title="Block-level storage">Block-level storage</a></li></ul></li> <li><a href="/wiki/Single-instance_storage" title="Single-instance storage">Single-instance storage</a></li> <li><a href="/wiki/Data" title="Data">Data</a></li> <li><a href="/wiki/Data_model" title="Data model">Structured data</a></li> <li><a href="/wiki/Unstructured_data" title="Unstructured data">Unstructured data</a></li> <li><a href="/wiki/Big_data" title="Big data">Big data</a></li> <li><a href="/wiki/Metadata" title="Metadata">Metadata</a></li> <li><a href="/wiki/Data_compression" title="Data compression">Data compression</a></li> <li><a href="/wiki/Data_corruption" title="Data corruption">Data corruption</a></li> <li><a href="/wiki/Data_cleansing" title="Data cleansing">Data cleansing</a></li> <li><a href="/wiki/Data_degradation" title="Data degradation">Data degradation</a></li> <li><a href="/wiki/Data_integrity" title="Data integrity">Data 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system</a></li> <li><a href="/wiki/Clustered_file_system#Distributed_file_systems" title="Clustered file system">Distributed file system</a></li> <li><a href="/wiki/Distributed_file_system_for_cloud" title="Distributed file system for cloud">Distributed file system for cloud</a></li> <li><a href="/wiki/Distributed_data_store" title="Distributed data store">Distributed data store</a></li> <li><a href="/wiki/Distributed_database" title="Distributed database">Distributed database</a></li> <li><a href="/wiki/Database" title="Database">Database</a></li> <li><a href="/wiki/Data_bank" title="Data bank">Data bank</a></li> <li><a href="/wiki/Data_storage" title="Data storage">Data storage</a></li> <li><a href="/wiki/Data_store" title="Data store">Data store</a></li> <li><a href="/wiki/Data_deduplication" title="Data deduplication">Data deduplication</a></li> <li><a href="/wiki/Data_structure" title="Data structure">Data structure</a></li> <li><a href="/wiki/Data_redundancy" title="Data redundancy">Data redundancy</a></li> <li><a href="/wiki/Replication_(computing)" title="Replication (computing)">Replication (computing)</a></li> <li><a href="/wiki/Memory_refresh" title="Memory refresh">Memory refresh</a></li> <li><a href="/wiki/Storage_record" title="Storage record">Storage record</a></li> <li><a href="/wiki/Information_repository" title="Information repository">Information repository</a></li> <li><a href="/wiki/Knowledge_base" title="Knowledge base">Knowledge base</a></li> <li><a href="/wiki/Computer_file" title="Computer file">Computer file</a></li> <li><a href="/wiki/Object_file" title="Object file">Object file</a></li> <li><a href="/wiki/File_deletion" title="File deletion">File deletion</a></li> <li><a href="/wiki/File_copying" title="File copying">File copying</a></li> <li><a href="/wiki/Backup" title="Backup">Backup</a></li> <li><a href="/wiki/Core_dump" title="Core dump">Core dump</a></li> <li><a href="/wiki/Hex_dump" title="Hex dump">Hex dump</a></li> <li><a href="/wiki/Data_communication" title="Data communication">Data communication</a></li> <li><a href="/wiki/Information_transfer" title="Information transfer">Information transfer</a></li> <li><a href="/wiki/Temporary_file" title="Temporary file">Temporary file</a></li> <li><a href="/wiki/Copy_protection" title="Copy protection">Copy protection</a></li> <li><a href="/wiki/Digital_rights_management" title="Digital rights management">Digital rights management</a></li> <li><a href="/wiki/Volume_(computing)" title="Volume (computing)">Volume (computing)</a></li> <li><a href="/wiki/Boot_sector" title="Boot sector">Boot sector</a></li> <li><a href="/wiki/Master_boot_record" title="Master boot record">Master boot record</a></li> <li><a href="/wiki/Volume_boot_record" title="Volume boot record">Volume boot record</a></li> <li><a href="/wiki/Disk_array" title="Disk array">Disk array</a></li> <li><a href="/wiki/Disk_image" title="Disk image">Disk image</a></li> <li><a href="/wiki/Disk_mirroring" title="Disk mirroring">Disk mirroring</a></li> <li><a href="/wiki/Disk_aggregation" title="Disk aggregation">Disk aggregation</a></li> <li><a href="/wiki/Disk_partitioning" title="Disk partitioning">Disk partitioning</a></li> <li><a href="/wiki/Memory_segmentation" title="Memory segmentation">Memory segmentation</a></li> <li><a href="/wiki/Locality_of_reference" title="Locality of reference">Locality of reference</a></li> <li><a href="/wiki/Logical_disk" title="Logical disk">Logical disk</a></li> <li><a href="/wiki/Storage_virtualization" title="Storage virtualization">Storage virtualization</a></li> <li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Memory-mapped_file" title="Memory-mapped file">Memory-mapped file</a></li> <li><a href="/wiki/Software_entropy" class="mw-redirect" title="Software entropy">Software entropy</a></li> <li><a href="/wiki/Software_rot" title="Software rot">Software rot</a></li> <li><a href="/wiki/In-memory_database" title="In-memory database">In-memory database</a></li> <li><a href="/wiki/In-memory_processing" title="In-memory processing">In-memory processing</a></li> <li><a href="/wiki/Persistence_(computer_science)" title="Persistence (computer science)">Persistence (computer science)</a></li> <li><a href="/wiki/Persistent_data_structure" title="Persistent data structure">Persistent data structure</a></li> <li><a href="/wiki/RAID" title="RAID">RAID</a></li> <li><a href="/wiki/Non-RAID_drive_architectures" title="Non-RAID drive architectures">Non-RAID drive architectures</a></li> <li><a href="/wiki/Memory_paging" title="Memory paging">Memory paging</a></li> <li><a href="/wiki/Bank_switching" title="Bank switching">Bank switching</a></li> <li><a href="/wiki/Grid_computing" title="Grid computing">Grid computing</a></li> <li><a href="/wiki/Cloud_computing" title="Cloud computing">Cloud computing</a></li> <li><a href="/wiki/Cloud_storage" title="Cloud storage">Cloud storage</a></li> <li><a href="/wiki/Fog_computing" title="Fog computing">Fog computing</a></li> <li><a href="/wiki/Edge_computing" title="Edge computing">Edge computing</a></li> <li><a href="/wiki/Dew_computing" title="Dew computing">Dew computing</a></li> <li><a href="/wiki/Amdahl%27s_law" title="Amdahl's law">Amdahl's law</a></li> <li><a href="/wiki/Moore%27s_law" title="Moore's law">Moore's law</a></li> <li><a href="/wiki/Mark_Kryder#Kryder's_law_projection" title="Mark Kryder">Kryder's law</a></li></ul></div></div></td> </tr><tr><th class="sidebar-heading"> <a href="/wiki/Volatile_memory" title="Volatile memory">Volatile</a></th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Random-access_memory" title="Random-access memory">RAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Cache_(computing)#HARDWARE" title="Cache (computing)">Hardware cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li></ul></li> <li><a class="mw-selflink selflink">DRAM</a> <ul><li><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a></li> <li><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">SDRAM</a></li> <li><a href="/wiki/Synchronous_dynamic_random-access_memory#Synchronous_Graphics_RAM_(SGRAM)" title="Synchronous dynamic random-access memory">SGRAM</a></li> <li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR</a></li> <li><a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR</a></li> <li><a href="/wiki/LPDDR" title="LPDDR">LPDDR</a></li> <li><a href="/wiki/Quad_Data_Rate_SRAM" title="Quad Data Rate SRAM">QDRSRAM</a></li> <li><a class="mw-selflink-fragment" href="#Extended_data_out_DRAM">EDO DRAM</a></li> <li><a href="/wiki/XDR_DRAM" title="XDR DRAM">XDR DRAM</a></li> <li><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a></li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a></li></ul></li> <li><a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a> <ul><li><a href="/wiki/1T-SRAM" title="1T-SRAM">1T-SRAM</a></li></ul></li> <li><a href="/wiki/Resistive_random-access_memory" title="Resistive random-access memory">ReRAM</a></li> <li><a href="/wiki/Quantum_memory" title="Quantum memory">QRAM</a></li> <li><a href="/wiki/Content-addressable_memory" title="Content-addressable memory">Content-addressable memory</a> (CAM)</li> <li><a href="/wiki/Computational_RAM" title="Computational RAM">Computational RAM</a></li> <li><a href="/wiki/Video_random_access_memory" class="mw-redirect" title="Video random access memory">VRAM</a></li> <li><a href="/wiki/Dual-ported_RAM" title="Dual-ported RAM">Dual-ported RAM</a> <ul><li><a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">Video RAM (dual-ported DRAM)</a></li></ul></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Historical</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Williams_tube" title="Williams tube">Williams–Kilburn tube</a> (1946–1947)</li> <li><a href="/wiki/Delay-line_memory" title="Delay-line memory">Delay-line memory</a> (1947)</li> <li><a href="/wiki/Mellon_optical_memory" title="Mellon optical memory">Mellon optical memory</a> (1951)</li> <li><a href="/wiki/Selectron_tube" title="Selectron tube">Selectron tube</a> (1952)</li> <li><a href="/wiki/Dekatron" title="Dekatron">Dekatron</a></li> <li><a href="/wiki/T-RAM" title="T-RAM">T-RAM</a> (2009)</li> <li><a href="/wiki/Z-RAM" title="Z-RAM">Z-RAM</a> (2002–2010)</li></ul></div></div></td> </tr><tr><th class="sidebar-heading"> <a href="/wiki/Non-volatile_memory" title="Non-volatile memory">Non-volatile</a></th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Read-only_memory" title="Read-only memory">ROM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Diode_matrix" title="Diode matrix">Diode matrix</a></li> <li><a href="/wiki/Read-only_memory#Factory-programmed" title="Read-only memory">MROM</a></li> <li><a href="/wiki/Programmable_ROM" title="Programmable ROM">PROM</a> <ul><li><a href="/wiki/EPROM" title="EPROM">EPROM</a></li> <li><a href="/wiki/EEPROM" title="EEPROM">EEPROM</a></li></ul></li> <li><a href="/wiki/ROM_cartridge" title="ROM cartridge">ROM cartridge</a></li> <li><a href="/wiki/Solid-state_storage" title="Solid-state storage">Solid-state storage</a> (SSS) <ul><li><a href="/wiki/Flash_memory" title="Flash memory">Flash memory</a> is used in:</li> <li><a href="/wiki/Solid-state_drive" title="Solid-state drive">Solid-state drive</a> (SSD)</li> <li><a href="/wiki/Solid-state_hybrid_drive" class="mw-redirect" title="Solid-state hybrid drive">Solid-state hybrid drive</a> (SSHD)</li> <li><a href="/wiki/USB_flash_drive" title="USB flash drive">USB flash drive</a></li> <li><a href="/wiki/IBM_FlashSystem" title="IBM FlashSystem">IBM FlashSystem</a></li> <li><a href="/wiki/Flash_Core_Module" title="Flash Core Module">Flash Core Module</a></li></ul></li> <li><a href="/wiki/Memory_card" title="Memory card">Memory card</a> <ul><li><a href="/wiki/Memory_Stick" title="Memory Stick">Memory Stick</a></li> <li><a href="/wiki/CompactFlash" title="CompactFlash">CompactFlash</a></li> <li><a href="/wiki/PC_Card" title="PC Card">PC Card</a></li> <li><a href="/wiki/MultiMediaCard" title="MultiMediaCard">MultiMediaCard</a></li> <li><a href="/wiki/SD_card" title="SD card">SD card</a></li> <li><a href="/wiki/SIM_card" title="SIM card">SIM card</a></li> <li><a href="/wiki/SmartMedia" title="SmartMedia">SmartMedia</a></li> <li><a href="/wiki/Universal_Flash_Storage" title="Universal Flash Storage">Universal Flash Storage</a></li> <li><a href="/wiki/SxS" title="SxS">SxS</a></li> <li><a href="/wiki/MicroP2" title="MicroP2">MicroP2</a></li> <li><a href="/wiki/XQD_card" title="XQD card">XQD card</a></li></ul></li> <li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">Programmable metallization cell</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Non-volatile_random-access_memory" title="Non-volatile random-access memory">NVRAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Memistor" title="Memistor">Memistor</a></li> <li><a href="/wiki/Memristor" title="Memristor">Memristor</a></li> <li><a href="/wiki/Phase-change_memory" title="Phase-change memory">PCM</a> (<a href="/wiki/3D_XPoint" title="3D XPoint">3D XPoint</a>)</li> <li><a href="/wiki/Magnetoresistive_RAM" title="Magnetoresistive RAM">MRAM</a></li> <li><a href="/wiki/Electrochemical_RAM" title="Electrochemical RAM">Electrochemical RAM</a> (ECRAM)</li> <li><a href="/wiki/Nano-RAM" title="Nano-RAM">Nano-RAM</a></li> <li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">CBRAM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Early-stage <a href="/wiki/Non-volatile_random-access_memory" title="Non-volatile random-access memory">NVRAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Ferroelectric_RAM" title="Ferroelectric RAM">FeRAM</a></li> <li><a href="/wiki/Resistive_random-access_memory" title="Resistive random-access memory">ReRAM</a></li> <li><a href="/wiki/Fe_FET" title="Fe FET">FeFET memory</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Analog_recording" title="Analog recording">Analog recording</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Phonograph_cylinder" title="Phonograph cylinder">Phonograph cylinder</a></li> <li><a href="/wiki/Phonograph_record" title="Phonograph record">Phonograph record</a></li> <li><a href="/wiki/Quadruplex_videotape" title="Quadruplex videotape">Quadruplex videotape</a></li> <li><a href="/wiki/Vision_Electronic_Recording_Apparatus" title="Vision Electronic Recording Apparatus">Vision Electronic Recording Apparatus</a></li> <li><a href="/wiki/Magnetic_recording" class="mw-redirect" title="Magnetic recording">Magnetic recording</a> <ul><li><a href="/wiki/Magnetic_storage" title="Magnetic storage">Magnetic storage</a></li> <li><a href="/wiki/Magnetic_tape" title="Magnetic tape">Magnetic tape</a></li> <li><a href="/wiki/Magnetic-tape_data_storage" title="Magnetic-tape data storage">Magnetic-tape data storage</a></li> <li><a href="/wiki/Tape_drive" title="Tape drive">Tape drive</a></li> <li><a href="/wiki/Tape_library" title="Tape library">Tape library</a></li> <li><a href="/wiki/Digital_Data_Storage" title="Digital Data Storage">Digital Data Storage</a> (DDS)</li> <li><a href="/wiki/Videotape" title="Videotape">Videotape</a></li> <li><a href="/wiki/Videocassette" class="mw-redirect" title="Videocassette">Videocassette</a></li> <li><a href="/wiki/Cassette_tape" class="mw-redirect" title="Cassette tape">Cassette tape</a></li> <li><a href="/wiki/Linear_Tape-Open" title="Linear Tape-Open">Linear Tape-Open</a></li> <li><a href="/wiki/Betamax" title="Betamax">Betamax</a></li> <li><a href="/wiki/8_mm_video_format" title="8 mm video format">8 mm video format</a></li> <li><a href="/wiki/DV_(video_format)" title="DV (video format)">DV</a></li> <li><a href="/wiki/MiniDV" class="mw-redirect" title="MiniDV">MiniDV</a></li> <li><a href="/wiki/MicroMV" title="MicroMV">MicroMV</a></li> <li><a href="/wiki/U-matic" title="U-matic">U-matic</a></li> <li><a href="/wiki/VHS" title="VHS">VHS</a></li> <li><a href="/wiki/S-VHS" title="S-VHS">S-VHS</a></li> <li><a href="/wiki/VHS-C" title="VHS-C">VHS-C</a></li> <li><a href="/wiki/D-VHS" title="D-VHS">D-VHS</a></li></ul></li> <li><a href="/wiki/Hard_disk_drive" title="Hard disk drive">Hard disk drive</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Optical_storage" title="Optical storage">Optical</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/3D_optical_data_storage" title="3D optical data storage">3D optical data storage</a> <ul><li><a href="/wiki/Optical_disc" title="Optical disc">Optical disc</a></li> <li><a href="/wiki/LaserDisc" title="LaserDisc">LaserDisc</a></li> <li><a href="/wiki/Compact_Disc_Digital_Audio" title="Compact Disc Digital Audio">Compact Disc Digital Audio</a> (CDDA)</li> <li><a href="/wiki/Compact_disc" title="Compact disc">CD</a></li> <li><a href="/wiki/CD_Video" title="CD Video">CD Video</a></li> <li><a href="/wiki/CD-R" title="CD-R">CD-R</a></li> <li><a href="/wiki/CD-RW" title="CD-RW">CD-RW</a></li> <li><a href="/wiki/Video_CD" title="Video CD">Video CD</a></li> <li><a href="/wiki/Super_Video_CD" title="Super Video CD">Super Video CD</a></li> <li><a href="/wiki/Mini_CD" title="Mini CD">Mini CD</a></li> <li><a href="/wiki/Nintendo_optical_discs" title="Nintendo optical discs">Nintendo optical discs</a></li> <li><a href="/wiki/CD-ROM" title="CD-ROM">CD-ROM</a></li> <li><a href="/wiki/Hyper_CD-ROM" title="Hyper CD-ROM">Hyper CD-ROM</a></li> <li><a href="/wiki/DVD" title="DVD">DVD</a></li> <li><a href="/wiki/DVD_recordable#DVD+R_and_DVD+RW_(DVD_"plus")" title="DVD recordable">DVD+R</a></li> <li><a href="/wiki/DVD-Video" title="DVD-Video">DVD-Video</a></li> <li><a href="/wiki/DVD_card" title="DVD card">DVD card</a></li> <li><a href="/wiki/DVD-RAM" title="DVD-RAM">DVD-RAM</a></li> <li><a href="/wiki/MiniDVD" title="MiniDVD">MiniDVD</a></li> <li><a href="/wiki/HD_DVD" title="HD DVD">HD DVD</a></li> <li><a href="/wiki/Blu-ray" title="Blu-ray">Blu-ray</a></li> <li><a href="/wiki/Ultra_HD_Blu-ray" title="Ultra HD Blu-ray">Ultra HD Blu-ray</a></li> <li><a href="/wiki/Holographic_Versatile_Disc" title="Holographic Versatile Disc">Holographic Versatile Disc</a></li></ul></li> <li><a href="/wiki/Write_once_read_many" title="Write once read many">WORM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">In development</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">CBRAM</a></li> <li><a href="/wiki/Racetrack_memory" title="Racetrack memory">Racetrack memory</a></li> <li><a href="/wiki/Nano-RAM" title="Nano-RAM">NRAM</a></li> <li><a href="/wiki/Millipede_memory" title="Millipede memory">Millipede memory</a></li> <li><a href="/wiki/Electrochemical_RAM" title="Electrochemical RAM">ECRAM</a></li> <li><a href="/wiki/Patterned_media" title="Patterned media">Patterned media</a></li> <li><a href="/wiki/Holographic_data_storage" title="Holographic data storage">Holographic data storage</a> <ul><li><a href="/wiki/Electronic_quantum_holography" title="Electronic quantum holography">Electronic quantum holography</a></li></ul></li> <li><a href="/wiki/5D_optical_data_storage" title="5D optical data storage">5D optical data storage</a></li> <li><a href="/wiki/DNA_digital_data_storage" title="DNA digital data storage">DNA digital data storage</a></li> <li><a href="/wiki/Universal_memory" title="Universal memory">Universal memory</a></li> <li><a href="/wiki/Time_crystal" title="Time crystal">Time crystal</a></li> <li><a href="/wiki/Quantum_memory" title="Quantum memory">Quantum memory</a></li> <li><a href="/wiki/UltraRAM" title="UltraRAM">UltraRAM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Historical</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Paper_data_storage" title="Paper data storage">Paper data storage</a> (1725)</li> <li><a href="/wiki/Punched_card" title="Punched card">Punched card</a> (1725)</li> <li><a href="/wiki/Punched_tape" title="Punched tape">Punched tape</a> (1725)</li> <li><a href="/wiki/Plugboard" title="Plugboard">Plugboard</a></li> <li><a href="/wiki/Drum_memory" title="Drum memory">Drum memory</a> (1932)</li> <li><a href="/wiki/Magnetic-core_memory" title="Magnetic-core memory">Magnetic-core memory</a> (1949)</li> <li><a href="/wiki/Plated-wire_memory" title="Plated-wire memory">Plated-wire memory</a> (1957)</li> <li><a href="/wiki/Core_rope_memory" title="Core rope memory">Core rope memory</a> (1960s)</li> <li><a href="/wiki/Thin-film_memory" title="Thin-film memory">Thin-film memory</a> (1962)</li> <li><a href="/wiki/Disk_pack" title="Disk pack">Disk pack</a> (1962)</li> <li><a href="/wiki/Twistor_memory" title="Twistor memory">Twistor memory</a> (~1968)</li> <li><a href="/wiki/Bubble_memory" title="Bubble memory">Bubble memory</a> (~1970)</li> <li><a href="/wiki/Floppy_disk" title="Floppy disk">Floppy disk</a> (1971)</li></ul></div></div></td> </tr><tr><td class="sidebar-navbar"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output 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abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Memory_types" title="Template:Memory types"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Memory_types" title="Template talk:Memory types"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Memory_types" title="Special:EditPage/Template:Memory types"><abbr title="Edit this template">e</abbr></a></li></ul></div></td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:NeXTcube_motherboard.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/d6/NeXTcube_motherboard.jpg/250px-NeXTcube_motherboard.jpg" decoding="async" width="220" height="216" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/d6/NeXTcube_motherboard.jpg/330px-NeXTcube_motherboard.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/d6/NeXTcube_motherboard.jpg/500px-NeXTcube_motherboard.jpg 2x" data-file-width="3371" data-file-height="3310" /></a><figcaption><a href="/wiki/Motherboard" title="Motherboard">Motherboard</a> of the <a href="/wiki/NeXTcube" title="NeXTcube">NeXTcube</a> computer, 1990, with 64 MiB main memory DRAM (top left) and 256 KiB of <a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">VRAM</a><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> (lower edge, right of middle)</figcaption></figure> <p><b>Dynamic random-access memory</b> (<b>dynamic RAM</b> or <b>DRAM</b>) is a type of <a href="/wiki/Random-access_memory" title="Random-access memory">random-access</a> <a href="/wiki/Semiconductor_memory" title="Semiconductor memory">semiconductor memory</a> that stores each <a href="/wiki/Bit" title="Bit">bit</a> of data in a <a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">memory cell</a>, usually consisting of a tiny <a href="/wiki/Capacitor" title="Capacitor">capacitor</a> and a <a href="/wiki/Transistor" title="Transistor">transistor</a>, both typically based on <a href="/wiki/Metal%E2%80%93oxide%E2%80%93semiconductor" class="mw-redirect" title="Metal–oxide–semiconductor">metal–oxide–semiconductor</a> (MOS) technology. While most DRAM memory cell designs use a capacitor and transistor, some only use two transistors. In the designs where a capacitor is used, the capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The <a href="/wiki/Electric_charge" title="Electric charge">electric charge</a> on the capacitors gradually leaks away; without intervention the data on the capacitor would soon be lost. To prevent this, DRAM requires an external <a href="/wiki/Memory_refresh" title="Memory refresh">memory refresh</a> circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to <a href="/wiki/Static_random-access_memory" title="Static random-access memory">static random-access memory</a> (SRAM) which does not require data to be refreshed. Unlike <a href="/wiki/Flash_memory" title="Flash memory">flash memory</a>, DRAM is <a href="/wiki/Volatile_memory" title="Volatile memory">volatile memory</a> (vs. <a href="/wiki/Non-volatile_memory" title="Non-volatile memory">non-volatile memory</a>), since it loses its data quickly when power is removed. However, DRAM does exhibit limited <a href="/wiki/Data_remanence" title="Data remanence">data remanence</a>. </p><p>DRAM typically takes the form of an <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> chip, which can consist of dozens to billions of DRAM memory cells. DRAM chips are widely used in <a href="/wiki/Digital_electronics" title="Digital electronics">digital electronics</a> where low-cost and high-capacity <a href="/wiki/Computer_memory" title="Computer memory">computer memory</a> is required. One of the largest applications for DRAM is the <i><a href="/wiki/Main_memory" class="mw-redirect" title="Main memory">main memory</a></i> (colloquially called the RAM) in modern <a href="/wiki/Computer" title="Computer">computers</a> and <a href="/wiki/Graphics_card" title="Graphics card">graphics cards</a> (where the main memory is called the <i><a href="/wiki/Video_random_access_memory" class="mw-redirect" title="Video random access memory">graphics memory</a></i>). It is also used in many portable devices and <a href="/wiki/Video_game" title="Video game">video game</a> consoles. In contrast, SRAM, which is faster and more expensive than DRAM, is typically used where speed is of greater concern than cost and size, such as the <a href="/wiki/CPU_cache" title="CPU cache">cache memories</a> in <a href="/wiki/Central_processing_unit" title="Central processing unit">processors</a>. </p><p>The need to refresh DRAM demands more complicated circuitry and timing than SRAM. This complexity is offset by the structural simplicity of DRAM memory cells: only one transistor and a capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high <a href="/wiki/Computer_storage_density" class="mw-redirect" title="Computer storage density">densities</a> with a simultaneous reduction in cost per bit. Refreshing the data consumes power, causing a variety of techniques to be used to manage the overall power consumption. For this reason, DRAM usually needs to operate with a <a href="/wiki/Memory_controller" title="Memory controller">memory controller</a>; the <a href="/wiki/Memory_controller" title="Memory controller">memory controller</a> needs to know DRAM parameters, especially <a href="/wiki/Memory_timings" title="Memory timings">memory timings</a>, to initialize DRAMs, which may be different depending on different DRAM manufacturers and part numbers. </p><p>DRAM had a 47% increase in the price-per-bit in 2017, the largest jump in 30 years since the 45% jump in 1988, while in recent years the price has been going down.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> In 2018, a "key characteristic of the DRAM market is that there are currently only three major suppliers — <a href="/wiki/Micron_Technology" title="Micron Technology">Micron Technology</a>, <a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a> and <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a>" that are "keeping a pretty tight rein on their capacity".<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> There is also <a href="/wiki/Kioxia" title="Kioxia">Kioxia</a> (previously <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> Memory Corporation after 2017 spin-off) which doesn't manufacture DRAM. Other manufacturers make and sell <a href="/wiki/DIMM" title="DIMM">DIMMs</a> (but not the DRAM chips in them), such as <a href="/wiki/Kingston_Technology" title="Kingston Technology">Kingston Technology</a>, and some manufacturers that sell <a href="/wiki/Stacked_DRAM" class="mw-redirect" title="Stacked DRAM">stacked DRAM</a> (used e.g. in the fastest <a href="/wiki/Supercomputer" title="Supercomputer">supercomputers</a> on the <a href="/wiki/Exascale_computing" title="Exascale computing">exascale</a>), separately such as <a href="/w/index.php?title=Viking_Technology&action=edit&redlink=1" class="new" title="Viking Technology (page does not exist)">Viking Technology</a>. Others sell such integrated into other products, such as <a href="/wiki/Fujitsu" title="Fujitsu">Fujitsu</a> into its CPUs, AMD in GPUs, and <a href="/wiki/Nvidia" title="Nvidia">Nvidia</a>, with <a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a> in some of their GPU chips. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Precursors">Precursors</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=2" title="Edit section: Precursors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Original_1T1C_DRAM_design.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/6a/Original_1T1C_DRAM_design.svg/350px-Original_1T1C_DRAM_design.svg.png" decoding="async" width="350" height="263" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/6a/Original_1T1C_DRAM_design.svg/525px-Original_1T1C_DRAM_design.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/6a/Original_1T1C_DRAM_design.svg/700px-Original_1T1C_DRAM_design.svg.png 2x" data-file-width="800" data-file-height="600" /></a><figcaption>A schematic drawing depicting the cross-section of the original one-transistor, one-capacitor <a href="/wiki/NMOS_logic" title="NMOS logic">NMOS</a> DRAM cell. It was patented in 1968.</figcaption></figure> <p>The <a href="/wiki/Cryptanalysis" title="Cryptanalysis">cryptanalytic</a> machine code-named <i>Aquarius</i> used at <a href="/wiki/Bletchley_Park" title="Bletchley Park">Bletchley Park</a> during <a href="/wiki/World_War_II" title="World War II">World War II</a> incorporated a hard-wired dynamic memory. Paper tape was read and the characters on it "were remembered in a dynamic store." The store used a large bank of capacitors, which were either charged or not, a charged capacitor representing cross (1) and an uncharged capacitor dot (0). Since the charge gradually leaked away, a periodic pulse was applied to top up those still charged (hence the term 'dynamic')".<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p><p>In November 1965, <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> introduced a bipolar dynamic RAM for its <a href="/wiki/Electronic_calculator" class="mw-redirect" title="Electronic calculator">electronic calculator</a> Toscal BC-1411.<sup id="cite_ref-toscal_6-0" class="reference"><a href="#cite_note-toscal-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> In 1966, Tomohisa Yoshimaru and Hiroshi Komikawa from Toshiba applied for a Japanese patent of a memory circuit composed of several transistors and a capacitor, in 1967 they applied for a patent in the US.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p><p>The earliest forms of DRAM mentioned above used <a href="/wiki/Bipolar_transistors" class="mw-redirect" title="Bipolar transistors">bipolar transistors</a>. While it offered improved performance over <a href="/wiki/Magnetic-core_memory" title="Magnetic-core memory">magnetic-core memory</a>, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> Capacitors had also been used for earlier memory schemes, such as the drum of the <a href="/wiki/Atanasoff%E2%80%93Berry_Computer" class="mw-redirect" title="Atanasoff–Berry Computer">Atanasoff–Berry Computer</a>, the <a href="/wiki/Williams_tube" title="Williams tube">Williams tube</a> and the <a href="/wiki/Selectron_tube" title="Selectron tube">Selectron tube</a>. </p> <div class="mw-heading mw-heading3"><h3 id="Single_MOS_DRAM">Single MOS DRAM</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=3" title="Edit section: Single MOS DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 1966, Dr. <a href="/wiki/Robert_Dennard" class="mw-redirect" title="Robert Dennard">Robert Dennard</a> invented modern DRAM architecture in which there's a single MOS transistor per capacitor,<sup id="cite_ref-ibm100_11-0" class="reference"><a href="#cite_note-ibm100-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> at the <a href="/wiki/IBM_Thomas_J._Watson_Research_Center" class="mw-redirect" title="IBM Thomas J. Watson Research Center">IBM Thomas J. Watson Research Center</a>, while he was working on MOS memory and was trying to create an alternative to SRAM which required six MOS transistors for each <a href="/wiki/Bit" title="Bit">bit</a> of data. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of the single-transistor MOS DRAM memory cell.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> He filed a patent in 1967, and was granted U.S. patent number <a rel="nofollow" class="external text" href="https://web.archive.org/web/20151231134927/http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=3387286">3,387,286</a> in 1968.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> MOS memory offered higher performance, was cheaper, and consumed less power, than magnetic-core memory.<sup id="cite_ref-computerhistory1970_14-0" class="reference"><a href="#cite_note-computerhistory1970-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> The patent describes the invention: "Each cell is formed, in one embodiment, using a single field-effect transistor and a single capacitor."<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p><p>MOS DRAM chips were commercialized in 1969 by Advanced Memory Systems, Inc of <a href="/wiki/Sunnyvale,_California" title="Sunnyvale, California">Sunnyvale, CA</a>. This 1024 bit chip was sold to <a href="/wiki/Honeywell" title="Honeywell">Honeywell</a>, <a href="/wiki/Raytheon" title="Raytheon">Raytheon</a>, <a href="/wiki/Wang_Laboratories" title="Wang Laboratories">Wang Laboratories</a>, and others. The same year, Honeywell asked <a href="/wiki/Intel" title="Intel">Intel</a> to make a DRAM using a three-transistor cell that they had developed. This became the Intel 1102 in early 1970.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> However, the 1102 had many problems, prompting Intel to begin work on their own improved design, in secrecy to avoid conflict with Honeywell. This became the first commercially available DRAM, the <a href="/wiki/Intel_1103" title="Intel 1103">Intel 1103</a>, in October 1970, despite initial problems with low yield until the fifth revision of the <a href="/wiki/Photomask" title="Photomask">masks</a>. The 1103 was designed by Joel Karp and laid out by Pat Earhart. The masks were cut by Barbara Maness and Judy Garcia.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup><sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:No_original_research" title="Wikipedia:No original research"><span title="The material near this tag possibly contains original research. (December 2016)">original research?</span></a></i>]</sup> MOS memory overtook magnetic-core memory as the dominant memory technology in the early 1970s.<sup id="cite_ref-computerhistory1970_14-1" class="reference"><a href="#cite_note-computerhistory1970-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> </p><p>The first DRAM with multiplexed row and column <a href="/wiki/Address_bus" class="mw-redirect" title="Address bus">address lines</a> was the <a href="/wiki/Mostek" title="Mostek">Mostek</a> MK4096 4 Kbit DRAM designed by Robert Proebsting and introduced in 1973. This addressing scheme uses the same address pins to receive the low half and the high half of the address of the memory cell being referenced, switching between the two halves on alternating bus cycles. This was a radical advance, effectively halving the number of address lines required, which enabled it to fit into packages with fewer pins, a cost advantage that grew with every jump in memory size. The MK4096 proved to be a very robust design for customer applications. At the 16 Kbit density, the cost advantage increased; the 16 Kbit Mostek MK4116 DRAM,<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> introduced in 1976, achieved greater than 75% worldwide DRAM market share. However, as density increased to 64 Kbit in the early 1980s, Mostek and other US manufacturers were overtaken by Japanese DRAM manufacturers, which dominated the US and worldwide markets during the 1980s and 1990s. </p><p>Early in 1985, <a href="/wiki/Gordon_Moore" title="Gordon Moore">Gordon Moore</a> decided to withdraw Intel from producing DRAM.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> By 1986, many, but not all, United States chip makers had stopped making DRAMs.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> Micron Technology and Texas Instruments continued to produce them commercially, and IBM produced them for internal use. </p><p>In 1985, when 64K DRAM memory chips were the most common memory chips used in computers, and when more than 60 percent of those chips were produced by Japanese companies, semiconductor makers in the United States accused Japanese companies of <a href="/wiki/Export_dumping" class="mw-redirect" title="Export dumping">export dumping</a> for the purpose of driving makers in the United States out of the commodity memory chip business. Prices for the 64K product plummeted to as low as 35 cents apiece from $3.50 within 18 months, with disastrous financial consequences for some U.S. firms. On 4 December 1985 the US Commerce Department's International Trade Administration ruled in favor of the complaint.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous dynamic random-access memory</a> (SDRAM) was developed by <a href="/wiki/Samsung" title="Samsung">Samsung</a>. The first commercial SDRAM chip was the Samsung KM48SL2000, which had a capacity of 16<span class="nowrap"> </span><a href="/wiki/Mebibit" class="mw-redirect" title="Mebibit">Mb</a>,<sup id="cite_ref-electronic-design_26-0" class="reference"><a href="#cite_note-electronic-design-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> and was introduced in 1992.<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> The first commercial <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> (<a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a> SDRAM) memory chip was Samsung's 64<span class="nowrap"> </span>Mb DDR SDRAM chip, released in 1998.<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> </p><p>Later, in 2001, Japanese DRAM makers accused Korean DRAM manufacturers of dumping.<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> </p><p>In 2002, US computer makers made claims of <a href="/wiki/DRAM_price_fixing" class="mw-redirect" title="DRAM price fixing">DRAM price fixing</a>. </p> <div class="mw-heading mw-heading2"><h2 id="Principles_of_operation"><span class="anchor" id="ROW"></span>Principles of operation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=4" title="Edit section: Principles of operation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure typeof="mw:File/Thumb"><a href="/wiki/File:Square_array_of_mosfet_cells_read.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3d/Square_array_of_mosfet_cells_read.png/250px-Square_array_of_mosfet_cells_read.png" decoding="async" width="250" height="369" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3d/Square_array_of_mosfet_cells_read.png/375px-Square_array_of_mosfet_cells_read.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3d/Square_array_of_mosfet_cells_read.png/500px-Square_array_of_mosfet_cells_read.png 2x" data-file-width="630" data-file-height="930" /></a><figcaption>The principles of operation for reading a simple 4 <span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \times }"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mo>×</mo> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \times }</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/0ffafff1ad26cbe49045f19a67ce532116a32703" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: 0.019ex; margin-bottom: -0.19ex; width:1.808ex; height:1.509ex;" alt="{\displaystyle \times }" /></span>4 DRAM array</figcaption></figure> <figure typeof="mw:File/Thumb"><a href="/wiki/File:DRAM_cell_field_(details).png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/9c/DRAM_cell_field_%28details%29.png/250px-DRAM_cell_field_%28details%29.png" decoding="async" width="250" height="278" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/9c/DRAM_cell_field_%28details%29.png/375px-DRAM_cell_field_%28details%29.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/9c/DRAM_cell_field_%28details%29.png/500px-DRAM_cell_field_%28details%29.png 2x" data-file-width="1569" data-file-height="1745" /></a><figcaption>Basic structure of a DRAM cell array</figcaption></figure> <p>DRAM is usually arranged in a rectangular array of charge storage cells consisting of one capacitor and transistor per data bit. The figure to the right shows a simple example with a four-by-four cell matrix. Some DRAM matrices are many thousands of cells in height and width.<sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> </p><p>The long horizontal lines connecting each row are known as word-lines. Each column of cells is composed of two bit-lines, each connected to every other storage cell in the column (the illustration to the right does not include this important detail). They are generally known as the <i>+</i> and <i>−</i> bit lines. </p><p>A <a href="/wiki/Sense_amplifier" title="Sense amplifier">sense amplifier</a> is essentially a pair of cross-connected <a href="/wiki/Inverter_(logic_gate)" title="Inverter (logic gate)">inverters</a> between the bit-lines. The first inverter is connected with input from the + bit-line and output to the − bit-line. The second inverter's input is from the − bit-line with output to the + bit-line. This results in <a href="/wiki/Positive_feedback" title="Positive feedback">positive feedback</a> which stabilizes after one bit-line is fully at its highest voltage and the other bit-line is at the lowest possible voltage. </p> <div class="mw-heading mw-heading3"><h3 id="Operations_to_read_a_data_bit_from_a_DRAM_storage_cell">Operations to read a data bit from a DRAM storage cell</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=5" title="Edit section: Operations to read a data bit from a DRAM storage cell"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ol><li>The sense amplifiers are disconnected.<sup id="cite_ref-Kenner:24,30_35-0" class="reference"><a href="#cite_note-Kenner:24,30-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup></li> <li>The bit-lines are precharged to exactly equal voltages that are in between high and low logic levels (e.g., 0.5 V if the two levels are 0 and 1 V). The bit-lines are physically symmetrical to keep the capacitance equal, and therefore at this time their voltages are equal.<sup id="cite_ref-Kenner:24,30_35-1" class="reference"><a href="#cite_note-Kenner:24,30-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup></li> <li>The precharge circuit is switched off. Because the bit-lines are relatively long, they have enough <a href="/wiki/Capacitance" title="Capacitance">capacitance</a> to maintain the precharged voltage for a brief time. This is an example of <a href="/wiki/Dynamic_logic_(digital_logic)" class="mw-redirect" title="Dynamic logic (digital logic)">dynamic logic</a>.<sup id="cite_ref-Kenner:24,30_35-2" class="reference"><a href="#cite_note-Kenner:24,30-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup></li> <li>The desired row's word-line is then driven high to connect a cell's storage capacitor to its bit-line. This causes the transistor to conduct, transferring <a href="/wiki/Electric_charge" title="Electric charge">charge</a> from the storage cell to the connected bit-line (if the stored value is 1) or from the connected bit-line to the storage cell (if the stored value is 0). Since the capacitance of the bit-line is typically much higher than the capacitance of the storage cell, the voltage on the bit-line increases very slightly if the storage cell's capacitor is discharged and decreases very slightly if the storage cell is charged (e.g., 0.54 and 0.45 V in the two cases). As the other bit-line holds 0.50 V there is a small voltage difference between the two twisted bit-lines.<sup id="cite_ref-Kenner:24,30_35-3" class="reference"><a href="#cite_note-Kenner:24,30-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup></li> <li>The sense amplifiers are now connected to the bit-lines pairs. Positive feedback then occurs from the cross-connected inverters, thereby amplifying the small voltage difference between the odd and even row bit-lines of a particular column until one bit line is fully at the lowest voltage and the other is at the maximum high voltage. Once this has happened, the row is <i>open</i> (the desired cell data is available).<sup id="cite_ref-Kenner:24,30_35-4" class="reference"><a href="#cite_note-Kenner:24,30-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup></li> <li>All storage cells in the open row are sensed simultaneously, and the sense amplifier outputs latched. A column address then selects which latch bit to connect to the external data bus. Reads of different columns in the same row can be performed without a <a href="/wiki/Memory_timings" title="Memory timings">row opening delay</a> because, for the open row, all data has already been sensed and latched.<sup id="cite_ref-Kenner:24,30_35-5" class="reference"><a href="#cite_note-Kenner:24,30-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup></li> <li>While reading of columns in an open row is occurring, current is flowing back up the bit-lines from the output of the sense amplifiers and recharging the storage cells. This reinforces (i.e. refreshes) the charge in the storage cell by increasing the voltage in the storage capacitor if it was charged to begin with, or by keeping it discharged if it was empty. Note that due to the length of the bit-lines there is a fairly long propagation delay for the charge to be transferred back to the cell's capacitor. This takes significant time past the end of sense amplification, and thus overlaps with one or more column reads.<sup id="cite_ref-Kenner:24,30_35-6" class="reference"><a href="#cite_note-Kenner:24,30-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup></li> <li>When done with reading all the columns in the current open row, the word-line is switched off to disconnect the storage cell capacitors (the row is closed) from the bit-lines. The sense amplifier is switched off, and the bit-lines are precharged again.<sup id="cite_ref-Kenner:24,30_35-7" class="reference"><a href="#cite_note-Kenner:24,30-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup></li></ol> <div class="mw-heading mw-heading3"><h3 id="To_write_to_memory">To write to memory</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=6" title="Edit section: To write to memory"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Square_array_of_mosfet_cells_write.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/80/Square_array_of_mosfet_cells_write.png/250px-Square_array_of_mosfet_cells_write.png" decoding="async" width="250" height="363" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/80/Square_array_of_mosfet_cells_write.png/375px-Square_array_of_mosfet_cells_write.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/80/Square_array_of_mosfet_cells_write.png/500px-Square_array_of_mosfet_cells_write.png 2x" data-file-width="640" data-file-height="930" /></a><figcaption>Writing to a DRAM cell</figcaption></figure> <p>To store data, a row is opened and a given column's sense amplifier is temporarily forced to the desired high or low-voltage state, thus causing the bit-line to charge or discharge the cell storage capacitor to the desired value. Due to the sense amplifier's positive feedback configuration, it will hold a bit-line at stable voltage even after the forcing voltage is removed. During a write to a particular cell, all the columns in a row are sensed simultaneously just as during reading, so although only a single column's storage-cell capacitor charge is changed, the entire row is refreshed (written back in), as illustrated in the figure to the right.<sup id="cite_ref-Kenner:24,30_35-8" class="reference"><a href="#cite_note-Kenner:24,30-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Refresh_rate">Refresh rate</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=7" title="Edit section: Refresh rate"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Memory_refresh" title="Memory refresh">Memory refresh</a></div> <p><br /> Typically, manufacturers specify that each row must be refreshed every 64 ms or less, as defined by the <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a> standard. </p><p>Some systems refresh every row in a burst of activity involving all rows every 64 ms. Other systems refresh one row at a time staggered throughout the 64 ms interval. For example, a system with 2<sup>13</sup> = 8,192 rows would require a staggered <a href="/wiki/Refresh_rate" title="Refresh rate">refresh rate</a> of one row every 7.8 μs which is 64 ms divided by 8,192 rows. A few real-time systems refresh a portion of memory at a time determined by an external timer function that governs the operation of the rest of a system, such as the <a href="/wiki/Vertical_blanking_interval" title="Vertical blanking interval">vertical blanking interval</a> that occurs every 10–20 ms in video equipment. </p><p>The row address of the row that will be refreshed next is maintained by external logic or a <a href="/wiki/Counter_(digital)" title="Counter (digital)">counter</a> within the DRAM. A system that provides the row address (and the refresh command) does so to have greater control over when to refresh and which row to refresh. This is done to minimize conflicts with memory accesses, since such a system has both knowledge of the memory access patterns and the refresh requirements of the DRAM. When the row address is supplied by a counter within the DRAM, the system relinquishes control over which row is refreshed and only provides the refresh command. Some modern DRAMs are capable of self-refresh; no external logic is required to instruct the DRAM to refresh or to provide a row address. </p><p>Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Memory_timing">Memory timing</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=8" title="Edit section: Memory timing"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Memory_timings" title="Memory timings">Memory timings</a></div> <p>Many parameters are required to fully describe the timing of DRAM operation. Here are some examples for two timing grades of asynchronous DRAM, from a data sheet published in 1998:<sup id="cite_ref-Micron1_37-0" class="reference"><a href="#cite_note-Micron1-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="text-align:center;"> <caption>Asynchronous DRAM typical timing </caption> <tbody><tr> <th></th> <th>"50 ns"</th> <th>"60 ns"</th> <th>Description </th></tr> <tr> <td><i>t</i><sub>RC</sub></td> <td>84 ns</td> <td>104 ns</td> <td align="left">Random read or write cycle time (from one full /RAS cycle to another) </td></tr> <tr> <td><i>t</i><sub>RAC</sub></td> <td>50 ns</td> <td>60 ns</td> <td align="left">Access time: /RAS low to valid data out </td></tr> <tr> <td><i>t</i><sub>RCD</sub></td> <td>11 ns</td> <td>14 ns</td> <td align="left">/RAS low to /CAS low time </td></tr> <tr> <td><i>t</i><sub>RAS</sub></td> <td>50 ns</td> <td>60 ns</td> <td align="left">/RAS pulse width (minimum /RAS low time) </td></tr> <tr> <td><i>t</i><sub>RP</sub></td> <td>30 ns</td> <td>40 ns</td> <td align="left">/RAS precharge time (minimum /RAS high time) </td></tr> <tr> <td><i>t</i><sub>PC</sub></td> <td>20 ns</td> <td>25 ns</td> <td align="left">Page-mode read or write cycle time (/CAS to /CAS) </td></tr> <tr> <td><i>t</i><sub>AA</sub></td> <td>25 ns</td> <td>30 ns</td> <td align="left">Access time: Column address valid to valid data out (includes address <a href="/wiki/Setup_time" class="mw-redirect" title="Setup time">setup time</a> before /CAS low) </td></tr> <tr> <td><i>t</i><sub>CAC</sub></td> <td>13 ns</td> <td>15 ns</td> <td align="left">Access time: /CAS low to valid data out </td></tr> <tr> <td><i>t</i><sub>CAS</sub></td> <td>8 ns</td> <td>10 ns</td> <td align="left">/CAS low pulse width minimum </td></tr></tbody></table> <p>Thus, the generally quoted number is the /RAS low to valid data out time. This is the time to open a row, settle the sense amplifiers, and deliver the selected column data to the output. This is also the minimum /RAS low time, which includes the time for the amplified data to be delivered back to recharge the cells. The time to read additional bits from an open page is much less, defined by the /CAS to /CAS cycle time. The quoted number is the clearest way to compare between the performance of different DRAM memories, as it sets the slower limit regardless of the row length or page size. Bigger arrays forcibly result in larger bit line capacitance and longer propagation delays, which cause this time to increase as the sense amplifier settling time is dependent on both the capacitance as well as the propagation latency. This is countered in modern DRAM chips by instead integrating many more complete DRAM arrays within a single chip, to accommodate more capacity without becoming too slow. </p><p>When such a RAM is accessed by clocked logic, the times are generally rounded up to the nearest clock cycle. For example, when accessed by a 100 MHz state machine (i.e. a 10 ns clock), the 50 ns DRAM can perform the first read in five clock cycles, and additional reads within the same page every two clock cycles. This was generally described as <span class="nowrap">"5-2-2-2"</span> timing, as bursts of four reads within a page were common. </p><p>When describing synchronous memory, timing is described by clock cycle counts separated by hyphens. These numbers represent <span class="nowrap"><i>t</i><sub>CL</sub>-<i>t</i><sub>RCD</sub>-<i>t</i><sub>RP</sub>-<i>t</i><sub>RAS</sub></span> in multiples of the DRAM clock cycle time. Note that this is half of the data transfer rate when <a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a> signaling is used. JEDEC standard PC3200 timing is <span class="nowrap">3-4-4-8</span><sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> with a 200 MHz clock, while premium-priced high performance PC3200 DDR DRAM DIMM might be operated at <span class="nowrap">2-2-2-5</span> timing.<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="text-align:center;"> <caption>Synchronous DRAM typical timing </caption> <tbody><tr> <th rowspan="2" colspan="2"></th> <th colspan="2">PC-3200 (DDR-400)</th> <th colspan="2">PC2-6400 (DDR2-800)</th> <th colspan="2">PC3-12800 (DDR3-1600)</th> <th rowspan="2">Description </th></tr> <tr> <th>cycles</th> <th>time</th> <th>cycles</th> <th>time</th> <th>cycles</th> <th>time </th></tr> <tr> <th rowspan="2"><i>t</i><sub>CL</sub></th> <th>Typical </th> <td>3</td> <td>15 ns</td> <td>5</td> <td>12.5 ns</td> <td>9</td> <td>11.25 ns </td> <td rowspan="2" align="left">/CAS low to valid data out (equivalent to <i>t</i><sub>CAC</sub>) </td></tr> <tr> <th>Fast </th> <td>2</td> <td>10 ns</td> <td>4</td> <td>10 ns</td> <td>8</td> <td>10 ns </td></tr> <tr> <th rowspan="2"><i>t</i><sub>RCD</sub></th> <th>Typical </th> <td>4</td> <td>20 ns</td> <td>5</td> <td>12.5 ns</td> <td>9</td> <td>11.25 ns </td> <td rowspan="2" align="left">/RAS low to /CAS low time </td></tr> <tr> <th>Fast </th> <td>2</td> <td>10 ns</td> <td>4</td> <td>10 ns</td> <td>8</td> <td>10 ns </td></tr> <tr> <th rowspan="2"><i>t</i><sub>RP</sub></th> <th>Typical </th> <td>4</td> <td>20 ns</td> <td>5</td> <td>12.5 ns</td> <td>9</td> <td>11.25 ns </td> <td rowspan="2" align="left">/RAS precharge time (minimum precharge to active time) </td></tr> <tr> <th>Fast </th> <td>2</td> <td>10 ns</td> <td>4</td> <td>10 ns</td> <td>8</td> <td>10 ns </td></tr> <tr> <th rowspan="2"><i>t</i><sub>RAS</sub></th> <th>Typical </th> <td>8</td> <td>40 ns</td> <td>16</td> <td>40 ns</td> <td>27</td> <td>33.75 ns </td> <td rowspan="2" align="left">Row active time (minimum active to precharge time) </td></tr> <tr> <th>Fast </th> <td>5</td> <td>25 ns</td> <td>12</td> <td>30 ns</td> <td>24</td> <td>30 ns </td></tr></tbody></table> <p>Minimum random access time has improved from <i>t</i><sub>RAC</sub> = 50 ns to <span class="nowrap"><i>t</i><sub>RCD</sub> + <i>t</i><sub>CL</sub> = 22.5 ns</span>, and even the premium 20 ns variety is only 2.5 times faster than the asynchronous DRAM. <a href="/wiki/CAS_latency" title="CAS latency">CAS latency</a> has improved even less, from <span class="nowrap"><i>t</i><sub>CAC</sub> = 13 ns</span> to 10 ns. However, the DDR3 memory does achieve 32 times higher bandwidth; due to internal pipelining and wide data paths, it can output two words every 1.25 ns <span style="white-space:nowrap">(1<span style="margin-left:0.25em">600</span> Mword/s)</span>, while the EDO DRAM can output one word per <i>t</i><sub>PC</sub> = 20 ns (50 Mword/s). </p> <div class="mw-heading mw-heading4"><h4 id="Timing_abbreviations">Timing abbreviations</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=9" title="Edit section: Timing abbreviations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table> <tbody><tr> <td> <ul><li><i>t</i><sub>CL</sub> – CAS latency</li> <li><i>t</i><sub>CR</sub> – Command rate</li> <li><i>t</i><sub>PTP</sub> – precharge to precharge delay</li> <li><i>t</i><sub>RAS</sub> – RAS active time</li> <li><i>t</i><sub>RCD</sub> – RAS to CAS delay</li> <li><i>t</i><sub>REF</sub> – Refresh period</li> <li><i>t</i><sub>RFC</sub> – Row refresh cycle time</li> <li><i>t</i><sub>RP</sub> – RAS precharge</li></ul> </td> <td> <ul><li><i>t</i><sub>RRD</sub> – RAS to RAS delay</li> <li><i>t</i><sub>RTP</sub> – Read to precharge delay</li> <li><i>t</i><sub>RTR</sub> – Read to read delay</li> <li><i>t</i><sub>RTW</sub> – Read to write delay</li> <li><i>t</i><sub>WR</sub> – Write recovery time</li> <li><i>t</i><sub>WTP</sub> – Write to precharge delay</li> <li><i>t</i><sub>WTR</sub> – Write to read delay</li> <li><i>t</i><sub>WTW</sub> – Write to write delay</li></ul> </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Memory_cell_design">Memory cell design</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=10" title="Edit section: Memory cell design"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell (computing)</a></div> <p>Each bit of data in a DRAM is stored as a positive or negative electrical charge in a capacitive structure. The structure providing the capacitance, as well as the transistors that control access to it, is collectively referred to as a <i>DRAM cell</i>. They are the fundamental building block in DRAM arrays. Multiple DRAM memory cell variants exist, but the most commonly used variant in modern DRAMs is the one-transistor, one-capacitor (1T1C) cell. The transistor is used to admit current into the capacitor during writes, and to discharge the capacitor during reads. The access transistor is designed to maximize drive strength and minimize transistor-transistor leakage (Kenner, p. 34). </p><p>The capacitor has two terminals, one of which is connected to its access transistor, and the other to either ground or V<sub>CC</sub>/2. In modern DRAMs, the latter case is more common, since it allows faster operation. In modern DRAMs, a voltage of +V<sub>CC</sub>/2 across the capacitor is required to store a logic one; and a voltage of −V<sub>CC</sub>/2 across the capacitor is required to store a logic zero. The resultant charge is <span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\textstyle Q=\pm {V_{CC} \over 2}\cdot C}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="false" scriptlevel="0"> <mi>Q</mi> <mo>=</mo> <mo>±</mo> <mrow class="MJX-TeXAtom-ORD"> <mfrac> <msub> <mi>V</mi> <mrow class="MJX-TeXAtom-ORD"> <mi>C</mi> <mi>C</mi> </mrow> </msub> <mn>2</mn> </mfrac> </mrow> <mo>⋅</mo> <mi>C</mi> </mstyle> </mrow> <annotation encoding="application/x-tex">{\textstyle Q=\pm {V_{CC} \over 2}\cdot C}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/3a69d5071d892275b96e1622a5830d197829a643" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -1.171ex; width:14.177ex; height:4.009ex;" alt="{\textstyle Q=\pm {V_{CC} \over 2}\cdot C}" /></span>, where <i>Q</i> is the charge in <a href="/wiki/Coulomb" title="Coulomb">coulombs</a> and <i>C</i> is the capacitance in <a href="/wiki/Farad" title="Farad">farads</a>.<sup id="cite_ref-Kenner:22_40-0" class="reference"><a href="#cite_note-Kenner:22-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </p><p>Reading or writing a logic one requires the wordline be driven to a voltage greater than the sum of V<sub>CC</sub> and the access transistor's threshold voltage (V<sub>TH</sub>). This voltage is called <i>V<sub>CC</sub> pumped</i> (V<sub>CCP</sub>). The time required to discharge a capacitor thus depends on what logic value is stored in the capacitor. A capacitor containing logic one begins to discharge when the voltage at the access transistor's gate terminal is above V<sub>CCP</sub>. If the capacitor contains a logic zero, it begins to discharge when the gate terminal voltage is above V<sub>TH</sub>.<sup id="cite_ref-Kenner:24_41-0" class="reference"><a href="#cite_note-Kenner:24-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Capacitor_design">Capacitor design</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=11" title="Edit section: Capacitor design"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Up until the mid-1980s, the capacitors in DRAM cells were co-planar with the access transistor (they were constructed on the surface of the substrate), thus they were referred to as <i>planar</i> capacitors. The drive to increase both density and, to a lesser extent, performance, required denser designs. This was strongly motivated by economics, a major consideration for DRAM devices, especially commodity DRAMs. The minimization of DRAM cell area can produce a denser device and lower the cost per bit of storage. Starting in the mid-1980s, the capacitor was moved above or below the silicon substrate in order to meet these objectives. DRAM cells featuring capacitors above the substrate are referred to as <i>stacked</i> or <i>folded plate</i> capacitors. Those with capacitors buried beneath the substrate surface are referred to as <i>trench</i> capacitors. In the 2000s, manufacturers were sharply divided by the type of capacitor used in their DRAMs and the relative cost and long-term scalability of both designs have been the subject of extensive debate. The majority of DRAMs, from major manufactures such as <a href="/wiki/Hynix" class="mw-redirect" title="Hynix">Hynix</a>, <a href="/wiki/Micron_Technology" title="Micron Technology">Micron Technology</a>, <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a> use the stacked capacitor structure, whereas smaller manufacturers such Nanya Technology use the trench capacitor structure (Jacob, pp. 355–357). </p><p>The capacitor in the stacked capacitor scheme is constructed above the surface of the substrate. The capacitor is constructed from an oxide-nitride-oxide (ONO) dielectric sandwiched in between two layers of polysilicon plates (the top plate is shared by all DRAM cells in an IC), and its shape can be a rectangle, a cylinder, or some other more complex shape. There are two basic variations of the stacked capacitor, based on its location relative to the bitline—capacitor-under-bitline (CUB) and capacitor-over-bitline (COB). In the former, the capacitor is underneath the bitline, which is usually made of metal, and the bitline has a polysilicon contact that extends downwards to connect it to the access transistor's source terminal. In the latter, the capacitor is constructed above the bitline, which is almost always made of polysilicon, but is otherwise identical to the COB variation. The advantage the COB variant possesses is the ease of fabricating the contact between the bitline and the access transistor's source as it is physically close to the substrate surface. However, this requires the active area to be laid out at a 45-degree angle when viewed from above, which makes it difficult to ensure that the capacitor contact does not touch the bitline. CUB cells avoid this, but suffer from difficulties in inserting contacts in between bitlines, since the size of features this close to the surface are at or near the minimum feature size of the process technology (Kenner, pp. 33–42). </p><p>The trench capacitor is constructed by etching a deep hole into the silicon substrate. The substrate volume surrounding the hole is then heavily doped to produce a buried n<sup>+</sup> plate with low resistance. A layer of oxide-nitride-oxide dielectric is grown or deposited, and finally the hole is filled by depositing doped polysilicon, which forms the top plate of the capacitor. The top of the capacitor is connected to the access transistor's drain terminal via a polysilicon strap (Kenner, pp. 42–44). A trench capacitor's depth-to-width ratio in DRAMs of the mid-2000s can exceed 50:1 (Jacob, p. 357). </p><p>Trench capacitors have numerous advantages. Since the capacitor is buried in the bulk of the substrate instead of lying on its surface, the area it occupies can be minimized to what is required to connect it to the access transistor's drain terminal without decreasing the capacitor's size, and thus capacitance (Jacob, pp. 356–357). Alternatively, the capacitance can be increased by etching a deeper hole without any increase to surface area (Kenner, p. 44). Another advantage of the trench capacitor is that its structure is under the layers of metal interconnect, allowing them to be more easily made planar, which enables it to be integrated in a logic-optimized process technology, which have many levels of interconnect above the substrate. The fact that the capacitor is under the logic means that it is constructed before the transistors are. This allows high-temperature processes to fabricate the capacitors, which would otherwise degrade the logic transistors and their performance. This makes trench capacitors suitable for constructing <a href="/wiki/Embedded_DRAM" class="mw-redirect" title="Embedded DRAM">embedded DRAM</a> (eDRAM) (Jacob, p. 357). Disadvantages of trench capacitors are difficulties in reliably constructing the capacitor's structures within deep holes and in connecting the capacitor to the access transistor's drain terminal (Kenner, p. 44). </p> <div class="mw-heading mw-heading3"><h3 id="Historical_cell_designs">Historical cell designs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=12" title="Edit section: Historical cell designs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>First-generation DRAM ICs (those with capacities of 1 Kbit), such as the archetypical <a href="/wiki/Intel_1103" title="Intel 1103">Intel 1103</a>, used a three-transistor, one-capacitor (3T1C) DRAM cell with separate read and write circuitry. The write wordline drove a write transistor which connected the capacitor to the write bitline just as in the 1T1C cell, but there was a separate read wordline and read transistor which connected an amplifier transistor to the read bitline. By the second generation, the drive to reduce cost by fitting the same amount of bits in a smaller area led to the almost universal adoption of the 1T1C DRAM cell, although a couple of devices with 4 and 16 Kbit capacities continued to use the 3T1C cell for performance reasons (Kenner, p. 6). These performance advantages included, most significantly, the ability to read the state stored by the capacitor without discharging it, avoiding the need to write back what was read out (non-destructive read). A second performance advantage relates to the 3T1C cell's separate transistors for reading and writing; the memory controller can exploit this feature to perform atomic read-modify-writes, where a value is read, modified, and then written back as a single, indivisible operation (Jacob, p. 459). </p> <div class="mw-heading mw-heading3"><h3 id="Proposed_cell_designs">Proposed cell designs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=13" title="Edit section: Proposed cell designs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The one-transistor, zero-capacitor (1T, or 1T0C) DRAM cell has been a topic of research since the late-1990s. <i>1T DRAM</i> is a different way of constructing the basic DRAM memory cell, distinct from the classic one-transistor/one-capacitor (1T/1C) DRAM cell, which is also sometimes referred to as <i>1T DRAM</i>, particularly in comparison to the 3T and 4T DRAM which it replaced in the 1970s. </p><p>In 1T DRAM cells, the bit of data is still stored in a capacitive region controlled by a transistor, but this capacitance is no longer provided by a separate capacitor. 1T DRAM is a "capacitorless" bit cell design that stores data using the parasitic body capacitance that is inherent to <a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">silicon on insulator</a> (SOI) transistors. Considered a nuisance in logic design, this <a href="/wiki/Floating_body_effect" title="Floating body effect">floating body effect</a> can be used for data storage. This gives 1T DRAM cells the greatest density as well as allowing easier integration with high-performance logic circuits since they are constructed with the same SOI process technologies.<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> </p><p>Refreshing of cells remains necessary, but unlike with 1T1C DRAM, reads in 1T DRAM are non-destructive; the stored charge causes a detectable shift in the <a href="/wiki/Threshold_voltage" title="Threshold voltage">threshold voltage</a> of the transistor.<sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> Performance-wise, access times are significantly better than capacitor-based DRAMs, but slightly worse than SRAM. There are several types of 1T DRAMs: the commercialized <a href="/wiki/Z-RAM" title="Z-RAM">Z-RAM</a> from Innovative Silicon, the TTRAM<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> from Renesas and the <a href="/wiki/A-RAM" title="A-RAM">A-RAM</a> from the <a href="/wiki/University_of_Granada" title="University of Granada">UGR</a>/<a href="/wiki/CNRS" class="mw-redirect" title="CNRS">CNRS</a> consortium. </p> <div class="mw-heading mw-heading2"><h2 id="Array_structures">Array structures</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=14" title="Edit section: Array structures"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:DRAM_self-aligned_storage_node_locations.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/cd/DRAM_self-aligned_storage_node_locations.png/220px-DRAM_self-aligned_storage_node_locations.png" decoding="async" width="220" height="171" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/cd/DRAM_self-aligned_storage_node_locations.png/330px-DRAM_self-aligned_storage_node_locations.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/cd/DRAM_self-aligned_storage_node_locations.png/440px-DRAM_self-aligned_storage_node_locations.png 2x" data-file-width="706" data-file-height="550" /></a><figcaption>Self-aligned storage node locations simplify the fabrication process in modern DRAM.<sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup></figcaption></figure> <p>DRAM cells are laid out in a regular rectangular, grid-like pattern to facilitate their control and access via wordlines and bitlines. The physical layout of the DRAM cells in an array is typically designed so that two adjacent DRAM cells in a column share a single bitline contact to reduce their area. DRAM cell area is given as <i>n</i>F<sup>2</sup>, where <i>n</i> is a number derived from the DRAM cell design, and <i>F</i> is the smallest feature size of a given process technology. This scheme permits comparison of DRAM size over different process technology generations, as DRAM cell area scales at linear or near-linear rates with respect to feature size. The typical area for modern DRAM cells varies between 6–8 F<sup>2</sup>. </p><p>The horizontal wire, the wordline, is connected to the gate terminal of every access transistor in its row. The vertical bitline is connected to the source terminal of the transistors in its column. The lengths of the wordlines and bitlines are limited. The wordline length is limited by the desired performance of the array, since propagation time of the signal that must transverse the wordline is determined by the <a href="/wiki/RC_time_constant" title="RC time constant">RC time constant</a>. The bitline length is limited by its capacitance (which increases with length), which must be kept within a range for proper sensing (as DRAMs operate by sensing the charge of the capacitor released onto the bitline). Bitline length is also limited by the amount of operating current the DRAM can draw and by how power can be dissipated, since these two characteristics are largely determined by the charging and discharging of the bitline. </p> <div class="mw-heading mw-heading3"><h3 id="Bitline_architecture">Bitline architecture</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=15" title="Edit section: Bitline architecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Sense_amplifier" title="Sense amplifier">Sense amplifiers</a> are required to read the state contained in the DRAM cells. When the access transistor is activated, the electrical charge in the capacitor is shared with the bitline. The bitline's capacitance is much greater than that of the capacitor (approximately ten times). Thus, the change in bitline voltage is minute. Sense amplifiers are required to resolve the voltage differential into the levels specified by the logic signaling system. Modern DRAMs use differential sense amplifiers, and are accompanied by requirements as to how the DRAM arrays are constructed. Differential sense amplifiers work by driving their outputs to opposing extremes based on the relative voltages on pairs of bitlines. The sense amplifiers function effectively and efficient only if the capacitance and voltages of these bitline pairs are closely matched. Besides ensuring that the lengths of the bitlines and the number of attached DRAM cells attached to them are equal, two basic architectures to array design have emerged to provide for the requirements of the sense amplifiers: open and folded bitline arrays. </p> <div class="mw-heading mw-heading4"><h4 id="Open_bitline_arrays">Open bitline arrays</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=16" title="Edit section: Open bitline arrays"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The first generation (1 Kbit) DRAM ICs, up until the 64 Kbit generation (and some 256 Kbit generation devices) had open bitline array architectures. In these architectures, the bitlines are divided into multiple segments, and the differential sense amplifiers are placed in between bitline segments. Because the sense amplifiers are placed between bitline segments, to route their outputs outside the array, an additional layer of interconnect placed above those used to construct the wordlines and bitlines is required. </p><p>The DRAM cells that are on the edges of the array do not have adjacent segments. Since the differential sense amplifiers require identical capacitance and bitline lengths from both segments, dummy bitline segments are provided. The advantage of the open bitline array is a smaller array area, although this advantage is slightly diminished by the dummy bitline segments. The disadvantage that caused the near disappearance of this architecture is the inherent vulnerability to <a href="/wiki/Noise_(electronics)" title="Noise (electronics)">noise</a>, which affects the effectiveness of the differential sense amplifiers. Since each bitline segment does not have any spatial relationship to the other, it is likely that noise would affect only one of the two bitline segments. </p> <div class="mw-heading mw-heading4"><h4 id="Folded_bitline_arrays">Folded bitline arrays</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=17" title="Edit section: Folded bitline arrays"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The folded bitline array architecture routes bitlines in pairs throughout the array. The close proximity of the paired bitlines provide superior <a href="/wiki/Common-mode_signal" title="Common-mode signal">common-mode</a> noise rejection characteristics over open bitline arrays. The folded bitline array architecture began appearing in DRAM ICs during the mid-1980s, beginning with the 256 Kbit generation. This architecture is favored in modern DRAM ICs for its superior noise immunity. </p><p>This architecture is referred to as <i>folded</i> because it takes its basis from the open array architecture from the perspective of the circuit schematic. The folded array architecture appears to remove DRAM cells in alternate pairs (because two DRAM cells share a single bitline contact) from a column, then move the DRAM cells from an adjacent column into the voids. </p><p>The location where the bitline twists occupies additional area. To minimize area overhead, engineers select the simplest and most area-minimal twisting scheme that is able to reduce noise under the specified limit. As process technology improves to reduce minimum feature sizes, the signal to noise problem worsens, since coupling between adjacent metal wires is inversely proportional to their pitch. The array folding and bitline twisting schemes that are used must increase in complexity in order to maintain sufficient noise reduction. Schemes that have desirable noise immunity characteristics for a minimal impact in area is the topic of current research (Kenner, p. 37). </p> <div class="mw-heading mw-heading4"><h4 id="Future_array_architectures">Future array architectures</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=18" title="Edit section: Future array architectures"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Advances in process technology could result in open bitline array architectures being favored if it is able to offer better long-term area efficiencies; since folded array architectures require increasingly complex folding schemes to match any advance in process technology. The relationship between process technology, array architecture, and area efficiency is an active area of research. </p> <div class="mw-heading mw-heading3"><h3 id="Row_and_column_redundancy">Row and column redundancy</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=19" title="Edit section: Row and column redundancy"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The first DRAM <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuits</a> did not have any redundancy. An integrated circuit with a defective DRAM cell would be discarded. Beginning with the 64 Kbit generation, DRAM arrays have included spare rows and columns to improve yields. Spare rows and columns provide tolerance of minor fabrication defects which have caused a small number of rows or columns to be inoperable. The defective rows and columns are physically disconnected from the rest of the array by a triggering a <a href="/wiki/Polyfuse_(PROM)" title="Polyfuse (PROM)">programmable fuse</a> or by cutting the wire by a laser. The spare rows or columns are substituted in by remapping logic in the row and column decoders (Jacob, pp. 358–361). </p> <div class="mw-heading mw-heading2"><h2 id="Error_detection_and_correction">Error detection and correction</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=20" title="Edit section: Error detection and correction"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/RAM_parity" title="RAM parity">RAM parity</a> and <a href="/wiki/ECC_memory" title="ECC memory">ECC memory</a></div> <p>Electrical or magnetic interference inside a computer system can cause a single bit of DRAM to <a href="/wiki/RAM_parity" title="RAM parity">spontaneously flip</a> to the opposite state. The majority of one-off ("<a href="/wiki/Soft_error" title="Soft error">soft</a>") errors in DRAM chips occur as a result of <a href="/wiki/Background_radiation" title="Background radiation">background radiation</a>, chiefly <a href="/wiki/Neutron" title="Neutron">neutrons</a> from <a href="/wiki/Cosmic_ray" title="Cosmic ray">cosmic ray</a> secondaries, which may change the contents of one or more memory cells or interfere with the circuitry used to read/write them. </p><p>The problem can be mitigated by using <a href="/wiki/Redundancy_(engineering)" title="Redundancy (engineering)">redundant</a> memory bits and additional circuitry that use these bits to detect and correct soft errors. In most cases, the detection and correction are performed by the <a href="/wiki/Memory_controller" title="Memory controller">memory controller</a>; sometimes, the required logic is transparently implemented within DRAM chips or modules, enabling the ECC memory functionality for otherwise ECC-incapable systems.<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> The extra memory bits are used to record <a href="/wiki/RAM_parity" title="RAM parity">parity</a> and to enable missing data to be reconstructed by <a href="/wiki/Error-correcting_code" class="mw-redirect" title="Error-correcting code">error-correcting code</a> (ECC). Parity allows the detection of all single-bit errors (actually, any odd number of wrong bits). The most common error-correcting code, a <a href="/wiki/Hamming_code#Hamming_codes_with_additional_parity_(SECDED)" title="Hamming code">SECDED Hamming code</a>, allows a single-bit error to be corrected and, in the usual configuration, with an extra parity bit, double-bit errors to be detected.<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </p><p>Recent studies give widely varying error rates with over seven orders of magnitude difference, ranging from <span class="nowrap">10<sup>−10</sup>−10<sup>−17</sup> error/bit·h</span>, roughly one bit error, per hour, per gigabyte of memory to one bit error, per century, per gigabyte of memory.<sup id="cite_ref-Borucki1_48-0" class="reference"><a href="#cite_note-Borucki1-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Schroeder1_49-0" class="reference"><a href="#cite_note-Schroeder1-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Xin1_50-0" class="reference"><a href="#cite_note-Xin1-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> The Schroeder et al. 2009 study reported a 32% chance that a given computer in their study would suffer from at least one correctable error per year, and provided evidence that most such errors are intermittent hard rather than soft errors and that trace amounts of radioactive material that had gotten into the chip packaging were emitting alpha particles and corrupting the data.<sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> A 2010 study at the University of Rochester also gave evidence that a substantial fraction of memory errors are intermittent hard errors.<sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup> Large scale studies on non-ECC main memory in PCs and laptops suggest that undetected memory errors account for a substantial number of system failures: the 2011 study reported a 1-in-1700 chance per 1.5% of memory tested (extrapolating to an approximately 26% chance for total memory) that a computer would have a memory error every eight months.<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Security">Security</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=21" title="Edit section: Security"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Data_remanence">Data remanence</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=22" title="Edit section: Data remanence"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Data_remanence" title="Data remanence">Data remanence</a></div> <p>Although dynamic memory is only specified and <i>guaranteed</i> to retain its contents when supplied with power and refreshed every short period of time (often <span class="nowrap">64 ms</span>), the memory cell <a href="/wiki/Capacitor" title="Capacitor">capacitors</a> often retain their values for significantly longer time, particularly at low temperatures.<sup id="cite_ref-citp_54-0" class="reference"><a href="#cite_note-citp-54"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup> Under some conditions most of the data in DRAM can be recovered even if it has not been refreshed for several minutes.<sup id="cite_ref-Scheick1_55-0" class="reference"><a href="#cite_note-Scheick1-55"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup> </p><p>This property can be used to circumvent security and recover data stored in the main memory that is assumed to be destroyed at power-down. The computer could be quickly rebooted, and the contents of the main memory read out; or by removing a computer's memory modules, cooling them to prolong data remanence, then transferring them to a different computer to be read out. Such an attack was demonstrated to circumvent popular disk encryption systems, such as the <a href="/wiki/Open-source_software" title="Open-source software">open source</a> <a href="/wiki/TrueCrypt" title="TrueCrypt">TrueCrypt</a>, Microsoft's <a href="/wiki/BitLocker_Drive_Encryption" class="mw-redirect" title="BitLocker Drive Encryption">BitLocker Drive Encryption</a>, and <a href="/wiki/Apple_Inc." title="Apple Inc.">Apple</a>'s <a href="/wiki/FileVault" title="FileVault">FileVault</a>.<sup id="cite_ref-citp_54-1" class="reference"><a href="#cite_note-citp-54"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup> This type of attack against a computer is often called a <a href="/wiki/Cold_boot_attack" title="Cold boot attack">cold boot attack</a>. </p> <div class="mw-heading mw-heading3"><h3 id="Memory_corruption">Memory corruption</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=23" title="Edit section: Memory corruption"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Dynamic memory, by definition, requires periodic refresh. Furthermore, reading 1T dynamic memory is a destructive operation, requiring a recharge of the storage cells in the row that has been read. If these processes are imperfect, a read operation can cause <a href="/wiki/Soft_error" title="Soft error">soft errors</a>. In particular, there is a risk that some charge can leak between nearby cells, causing the refresh or read of one row to cause a <i>disturbance error</i> in an adjacent or even nearby row. The awareness of disturbance errors dates back to the first commercially available DRAM in the early 1970s (the <a href="/wiki/Intel_1103" title="Intel 1103">Intel 1103</a>). Despite the mitigation techniques employed by manufacturers, commercial researchers proved in a 2014 analysis that commercially available <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> DRAM chips manufactured in 2012 and 2013 are susceptible to disturbance errors.<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup> The associated side effect that led to observed bit flips has been dubbed <i><a href="/wiki/Row_hammer" title="Row hammer">row hammer</a></i>. </p> <div class="mw-heading mw-heading2"><h2 id="Packaging">Packaging</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=24" title="Edit section: Packaging"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Memory_module">Memory module</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=25" title="Edit section: Memory module"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Memory_module" title="Memory module">Memory module</a></div> <p>Dynamic RAM ICs can be packaged in molded epoxy cases, with an internal lead frame for interconnections between the <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">silicon die</a> and the package leads. The original <a href="/wiki/IBM_PC" class="mw-redirect" title="IBM PC">IBM PC</a> design used ICs, including those for DRAM, packaged in <a href="/wiki/Dual_in-line_package" title="Dual in-line package">dual in-line packages</a> (DIP), soldered directly to the main board or mounted in sockets. As memory density skyrocketed, the DIP package was no longer practical. For convenience in handling, several dynamic RAM integrated circuits may be mounted on a single memory module, allowing installation of 16-bit, 32-bit or 64-bit wide memory in a single unit, without the requirement for the installer to insert multiple individual integrated circuits. Memory modules may include additional devices for parity checking or error correction. Over the evolution of desktop computers, several standardized types of memory module have been developed. Laptop computers, game consoles, and specialized devices may have their own formats of memory modules not interchangeable with standard desktop parts for packaging or proprietary reasons. </p> <div class="mw-heading mw-heading3"><h3 id="Embedded">Embedded</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=26" title="Edit section: Embedded"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a></div> <p>DRAM that is integrated into an integrated circuit designed in a logic-optimized process (such as an <a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuit</a>, <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a>, or an entire <a href="/wiki/System_on_a_chip" title="System on a chip">system on a chip</a>) is called <i>embedded DRAM</i> (eDRAM). Embedded DRAM requires DRAM cell designs that can be <a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">fabricated</a> without preventing the fabrication of fast-switching transistors used in high-performance logic, and modification of the basic logic-optimized process technology to accommodate the process steps required to build DRAM cell structures. </p> <div class="mw-heading mw-heading2"><h2 id="Versions">Versions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=27" title="Edit section: Versions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Since the fundamental DRAM cell and array has maintained the same basic structure for many years, the types of DRAM are mainly distinguished by the many different interfaces for communicating with DRAM chips. </p> <div class="mw-heading mw-heading3"><h3 id="Asynchronous_DRAM">Asynchronous DRAM</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=28" title="Edit section: Asynchronous DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The original DRAM, now known by the <a href="/wiki/Retronym" title="Retronym">retronym</a> <i>asynchronous DRAM</i> was the first type of DRAM in use. From its origins in the late 1960s, it was commonplace in computing up until around 1997, when it was mostly replaced by <i>synchronous DRAM</i>. In the present day, manufacture of asynchronous RAM is relatively rare.<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Principles_of_operation_2">Principles of operation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=29" title="Edit section: Principles of operation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>An asynchronous DRAM chip has power connections, some number of address inputs (typically 12), and a few (typically one or four) bidirectional data lines. There are three main <a href="/wiki/Active-low" class="mw-redirect" title="Active-low">active-low</a> control signals: </p> <ul><li><span style="text-decoration:overline;">RAS</span>, the Row Address Strobe. The address inputs are captured on the falling edge of <span style="text-decoration:overline;">RAS</span>, and select a row to open. The row is held open as long as <span style="text-decoration:overline;">RAS</span> is low.</li> <li><span style="text-decoration:overline;">CAS</span>, the Column Address Strobe. The address inputs are captured on the falling edge of <span style="text-decoration:overline;">CAS</span>, and select a column from the currently open row to read or write.</li> <li><span style="text-decoration:overline;">WE</span>, Write Enable. This signal determines whether a given falling edge of <span style="text-decoration:overline;">CAS</span> is a read (if high) or write (if low). If low, the data inputs are also captured on the falling edge of <span style="text-decoration:overline;">CAS</span>. If high, the data outputs are enabled by the falling edge of <span style="text-decoration:overline;">CAS</span> and produce valid output after the internal access time.</li></ul> <p>This interface provides direct control of internal timing: when <span style="text-decoration:overline;">RAS</span> is driven low, a <span style="text-decoration:overline;">CAS</span> cycle must not be attempted until the sense amplifiers have sensed the memory state, and <span style="text-decoration:overline;">RAS</span> must not be returned high until the storage cells have been refreshed. When <span style="text-decoration:overline;">RAS</span> is driven high, it must be held high long enough for precharging to complete. </p><p>Although the DRAM is asynchronous, the signals are typically generated by a clocked memory controller, which limits their timing to multiples of the controller's clock cycle. </p><p>For completeness, we mention two other control signals which are not essential to DRAM operation, but are provided for the convenience of systems using DRAM: </p> <ul><li><span style="text-decoration:overline;">CS</span>, Chip Select. When this is high, all other inputs are ignored. This makes it easy to build an array of DRAM chips which share the same control signals. Just as DRAM internally uses the word lines to select one row of storage cells connect to the shared bit lines and sense amplifiers, <span style="text-decoration:overline;">CS</span> is used to select one row of DRAM chips to connect to the shared control, address, and data lines.</li> <li><span style="text-decoration:overline;">OE</span>, Output Enable. This is an additional signal that (if high) inhibits output on the data I/‍O pins, while allowing all other operations to proceed normally. In many applications, <span style="text-decoration:overline;">OE</span> can be permanently connected low (output enabled whenever <span style="text-decoration:overline;">CS</span>, <span style="text-decoration:overline;">RAS</span> and <span style="text-decoration:overline;">CAS</span> are low and <span style="text-decoration:overline;">WE</span> is high), but in high-speed applications, judicious use of <span style="text-decoration:overline;">OE</span> can prevent <a href="/wiki/Bus_contention" title="Bus contention">bus contention</a> between two DRAM chips connected to the same data lines. For example, it is possible to have two <a href="/wiki/Interleaved_memory" title="Interleaved memory">interleaved memory</a> banks sharing the address and data lines, but each having their own <span style="text-decoration:overline;">RAS</span>, <span style="text-decoration:overline;">CAS</span>, <span style="text-decoration:overline;">WE</span> and <span style="text-decoration:overline;">OE</span> connections. The memory controller can begin a read from the second bank while a read from the first bank is in progress, using the two <span style="text-decoration:overline;">OE</span> signals to only permit one result to appear on the data bus at a time.</li></ul> <div class="mw-heading mw-heading5"><h5 id="RAS-only_refresh">RAS-only refresh</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=30" title="Edit section: RAS-only refresh"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Classic asynchronous DRAM is refreshed by opening each row in turn. </p><p>The refresh cycles are distributed across the entire refresh interval in such a way that all rows are refreshed within the required interval. To refresh one row of the memory array using <span style="text-decoration:overline;">RAS</span> only refresh (ROR), the following steps must occur: </p> <ol><li>The row address of the row to be refreshed must be applied at the address input pins.</li> <li><span style="text-decoration:overline;">RAS</span> must switch from high to low. <span style="text-decoration:overline;">CAS</span> must remain high.</li> <li>At the end of the required amount of time, <span style="text-decoration:overline;">RAS</span> must return high.</li></ol> <p>This can be done by supplying a row address and pulsing <span style="text-decoration:overline;">RAS</span> low; it is not necessary to perform any <span style="text-decoration:overline;">CAS</span> cycles. An external counter is needed to iterate over the row addresses in turn.<sup id="cite_ref-IBM96_58-0" class="reference"><a href="#cite_note-IBM96-58"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup> In some designs, the CPU handled RAM refresh. The <a href="/wiki/Zilog_Z80" title="Zilog Z80">Zilog Z80</a> is perhaps the best known example, as it has an internal row counter R which supplies the address for a special refresh cycle generated after each instruction fetch.<sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup> In other systems, especially <a href="/wiki/Home_computer" title="Home computer">home computers</a>, refresh was handled by the video circuitry as a side effect of its periodic scan of the <a href="/wiki/Frame_buffer" class="mw-redirect" title="Frame buffer">frame buffer</a>.<sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading5"><h5 id="CAS_before_RAS_refresh">CAS before RAS refresh</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=31" title="Edit section: CAS before RAS refresh"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>For convenience, the counter was quickly incorporated into the DRAM chips themselves. If the <span style="text-decoration:overline;">CAS</span> line is driven low before <span style="text-decoration:overline;">RAS</span> (normally an illegal operation), then the DRAM ignores the address inputs and uses an internal counter to select the row to open.<sup id="cite_ref-IBM96_58-1" class="reference"><a href="#cite_note-IBM96-58"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-TN-04-30_61-0" class="reference"><a href="#cite_note-TN-04-30-61"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup> This is known as <span style="text-decoration:overline;">CAS</span>-before-<span style="text-decoration:overline;">RAS</span> (CBR) refresh. This became the standard form of refresh for asynchronous DRAM, and is the only form generally used with SDRAM. </p> <div class="mw-heading mw-heading5"><h5 id="Hidden_refresh">Hidden refresh</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=32" title="Edit section: Hidden refresh"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Given support of <span style="text-decoration:overline;">CAS</span>-before-<span style="text-decoration:overline;">RAS</span> refresh, it is possible to deassert <span style="text-decoration:overline;">RAS</span> while holding <span style="text-decoration:overline;">CAS</span> low to maintain data output. If <span style="text-decoration:overline;">RAS</span> is then asserted again, this performs a CBR refresh cycle while the DRAM outputs remain valid. Because data output is not interrupted, this is known as <i>hidden refresh</i>.<sup id="cite_ref-TN-04-30_61-1" class="reference"><a href="#cite_note-TN-04-30-61"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup> Hidden refresh is no faster than a normal read followed by a normal refresh, but does maintain the data output valid during the refresh cycle. </p> <div class="mw-heading mw-heading4"><h4 id="Page_mode_DRAM">Page mode DRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=33" title="Edit section: Page mode DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><b>Page mode DRAM</b> is a minor modification to the first-generation DRAM IC interface which improves the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column. In page mode DRAM, after a row is opened by holding <span style="text-decoration:overline;">RAS</span> low, the row can be kept open, and multiple reads or writes can be performed to any of the columns in the row. Each column access is initiated by presenting a column address and asserting <span style="text-decoration:overline;">CAS</span>. For reads, after a delay (<i>t</i><sub>CAC</sub>), valid data appears on the data out pins, which are held at high-Z before the appearance of valid data. For writes, the write enable signal and write data is presented along with the column address.<sup id="cite_ref-Kenner_13_62-0" class="reference"><a href="#cite_note-Kenner_13-62"><span class="cite-bracket">[</span>62<span class="cite-bracket">]</span></a></sup> </p><p>Page mode DRAM was in turn later improved with a small modification which further reduced latency. DRAMs with this improvement are called <b>fast page mode DRAMs</b> (<b>FPM DRAMs</b>). In page mode DRAM, the chip does not capture the column address until <span style="text-decoration:overline;">CAS</span> is asserted, so column access time (until data out was valid) begins when <span style="text-decoration:overline;">CAS</span> is asserted. In FPM DRAM, the column address can be supplied while <span style="text-decoration:overline;">CAS</span> is still deasserted, and the main column access time (<i>t</i><sub>AA</sub>) begins as soon as the address is stable. The <span style="text-decoration:overline;">CAS</span> signal is only needed to enable the output (the data out pins were held at high-Z while <span style="text-decoration:overline;">CAS</span> was deasserted), so time from <span style="text-decoration:overline;">CAS</span> assertion to data valid (<i>t</i><sub>CAC</sub>) is greatly reduced.<sup id="cite_ref-Kenner_14_63-0" class="reference"><a href="#cite_note-Kenner_14-63"><span class="cite-bracket">[</span>63<span class="cite-bracket">]</span></a></sup> Fast page mode DRAM was introduced in 1986 and was used with the <a href="/wiki/Intel_80486" class="mw-redirect" title="Intel 80486">Intel 80486</a>. </p><p><i>Static column</i> is a variant of fast page mode in which the column address does not need to be latched, but rather the address inputs may be changed with <span style="text-decoration:overline;">CAS</span> held low, and the data output will be updated accordingly a few nanoseconds later.<sup id="cite_ref-Kenner_14_63-1" class="reference"><a href="#cite_note-Kenner_14-63"><span class="cite-bracket">[</span>63<span class="cite-bracket">]</span></a></sup> </p><p><i>Nibble mode</i> is another variant in which four sequential locations within the row can be accessed with four consecutive pulses of <span style="text-decoration:overline;">CAS</span>. The difference from normal page mode is that the address inputs are not used for the second through fourth <span style="text-decoration:overline;">CAS</span> edges but are generated internally starting with the address supplied for the first <span style="text-decoration:overline;">CAS</span> edge.<sup id="cite_ref-Kenner_14_63-2" class="reference"><a href="#cite_note-Kenner_14-63"><span class="cite-bracket">[</span>63<span class="cite-bracket">]</span></a></sup> The predictable addresses let the chip prepare the data internally and respond very quickly to the subsequent <span style="text-decoration:overline;">CAS</span> pulses. </p> <div class="mw-heading mw-heading4"><h4 id="Extended_data_out_DRAM">Extended data out DRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=34" title="Edit section: Extended data out DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Pair32mbEDO-DRAMdimms.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e4/Pair32mbEDO-DRAMdimms.jpg/220px-Pair32mbEDO-DRAMdimms.jpg" decoding="async" width="220" height="210" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e4/Pair32mbEDO-DRAMdimms.jpg/330px-Pair32mbEDO-DRAMdimms.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e4/Pair32mbEDO-DRAMdimms.jpg/440px-Pair32mbEDO-DRAMdimms.jpg 2x" data-file-width="1868" data-file-height="1784" /></a><figcaption>A pair of 32 <a href="/wiki/Megabyte" title="Megabyte">MB</a> EDO DRAM modules</figcaption></figure> <p>Extended data out DRAM (EDO DRAM) was invented and patented in the 1990s by <a href="/wiki/Micron_Technology" title="Micron Technology">Micron Technology</a> who then licensed technology to many other memory manufacturers.<sup id="cite_ref-64" class="reference"><a href="#cite_note-64"><span class="cite-bracket">[</span>64<span class="cite-bracket">]</span></a></sup> EDO RAM, sometimes referred to as <i>hyper page mode</i> enabled DRAM, is similar to fast page mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved performance.<sup id="cite_ref-IBM96b_65-0" class="reference"><a href="#cite_note-IBM96b-65"><span class="cite-bracket">[</span>65<span class="cite-bracket">]</span></a></sup> It is up to 30% faster than FPM DRAM,<sup id="cite_ref-66" class="reference"><a href="#cite_note-66"><span class="cite-bracket">[</span>66<span class="cite-bracket">]</span></a></sup> which it began to replace in 1995 when <a href="/wiki/Intel" title="Intel">Intel</a> introduced the <a href="/wiki/Mercury_chipset" class="mw-redirect" title="Mercury chipset">430FX chipset</a> with EDO DRAM support. Irrespective of the performance gains, FPM and EDO SIMMs can be used interchangeably in many (but not all) applications.<sup id="cite_ref-67" class="reference"><a href="#cite_note-67"><span class="cite-bracket">[</span>67<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-68" class="reference"><a href="#cite_note-68"><span class="cite-bracket">[</span>68<span class="cite-bracket">]</span></a></sup> </p><p>To be precise, EDO DRAM begins data output on the falling edge of <span style="text-decoration:overline;">CAS</span> but does not disable the output when <span style="text-decoration:overline;">CAS</span> rises again. Instead, it holds the current output valid (thus extending the data output time) even as the DRAM begins decoding a new column address, until either a new column's data is selected by another <span style="text-decoration:overline;">CAS</span> falling edge, or the output is switched off by the rising edge of <span style="text-decoration:overline;">RAS</span>. (Or, less commonly, a change in <span style="text-decoration:overline;">CS</span>, <span style="text-decoration:overline;">OE</span>, or <span style="text-decoration:overline;">WE</span>.) </p><p>This ability to start a new access even before the system has received the preceding column's data made it possible to design memory controllers which could carry out a <span style="text-decoration:overline;">CAS</span> access (in the currently open row) in one clock cycle, or at least within two clock cycles instead of the previously required three. EDO's capabilities were able to partially compensate for the performance lost due to the lack of an L2 cache in low-cost, commodity PCs. More expensive notebooks also often lacked an L2 cache die to size and power limitations, and benefitted similarly. Even for systems <i>with</i> an L2 cache, the availability of EDO memory improved the average memory latency seen by applications over earlier FPM implementations. </p><p>Single-cycle EDO DRAM became very popular on video cards toward the end of the 1990s. It was very low cost, yet nearly as efficient for performance as the far more costly VRAM. </p> <div class="mw-heading mw-heading4"><h4 id="Burst_EDO_DRAM">Burst EDO DRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=35" title="Edit section: Burst EDO DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>An evolution of EDO DRAM, burst EDO DRAM (BEDO DRAM), could process four memory addresses in one burst, for a maximum of <span class="nowrap">5-1-1-1</span>, saving an additional three clocks over optimally designed EDO memory. It was done by adding an address counter on the chip to keep track of the next address. BEDO also added a pipeline stage allowing page-access cycle to be divided into two parts. During a memory-read operation, the first part accessed the data from the memory array to the output stage (second latch). The second part drove the data bus from this latch at the appropriate logic level. Since the data is already in the output buffer, quicker access time is achieved (up to 50% for large blocks of data) than with traditional EDO. </p><p>Although BEDO DRAM showed additional optimization over EDO, by the time it was available the market had made a significant investment towards synchronous DRAM, or SDRAM.<sup id="cite_ref-69" class="reference"><a href="#cite_note-69"><span class="cite-bracket">[</span>69<span class="cite-bracket">]</span></a></sup> Even though BEDO RAM was superior to SDRAM in some ways, the latter technology quickly displaced BEDO. </p> <div class="mw-heading mw-heading3"><h3 id="Synchronous_dynamic_RAM"><span class="anchor" id="ROW-ACTIVATION"></span>Synchronous dynamic RAM</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=36" title="Edit section: Synchronous dynamic RAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous dynamic random-access memory</a></div> <p>Synchronous dynamic RAM (SDRAM) significantly revises the asynchronous memory interface, adding a clock (and a clock enable) line. All other signals are received on the rising edge of the clock. </p><p>The <span style="text-decoration:overline;">RAS</span> and <span style="text-decoration:overline;">CAS</span> inputs no longer act as strobes, but are instead, along with <span style="text-decoration:overline;">WE</span>, part of a 3-bit command: </p> <table class="wikitable"> <caption>SDRAM Command summary </caption> <tbody><tr> <th><span style="text-decoration:overline;">CS</span> </th> <th><span style="text-decoration:overline;">RAS</span> </th> <th><span style="text-decoration:overline;">CAS</span> </th> <th><span style="text-decoration:overline;">WE</span> </th> <th>Address </th> <th>Command </th></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">x</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">x</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">x</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">x</td> <td>Command inhibit (no operation) </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">x</td> <td>No operation </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">x</td> <td>Burst Terminate: stop a read or write burst in progress. </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="text-align:center;">Column</td> <td>Read from currently active row. </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="text-align:center;">Column</td> <td>Write to currently active row. </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="text-align:center;">Row</td> <td>Activate a row for read and write. </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">x</td> <td>Precharge (deactivate) the current row. </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">x</td> <td>Auto refresh: refresh one row of each bank, using an internal counter. </td></tr> <tr> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="text-align:center;">Mode</td> <td>Load mode register: address bus specifies DRAM operation mode. </td></tr></tbody></table> <p>The <span style="text-decoration:overline;">OE</span> line's function is extended to a per-byte DQM signal, which controls data input (writes) in addition to data output (reads). This allows DRAM chips to be wider than 8 bits while still supporting byte-granularity writes. </p><p>Many timing parameters remain under the control of the DRAM controller. For example, a minimum time must elapse between a row being activated and a read or write command. One important parameter must be programmed into the SDRAM chip itself, namely the <a href="/wiki/CAS_latency" title="CAS latency">CAS latency</a>. This is the number of clock cycles allowed for internal operations between a read command and the first data word appearing on the data bus. The <i>Load mode register</i> command is used to transfer this value to the SDRAM chip. Other configurable parameters include the length of read and write bursts, i.e. the number of words transferred per read or write command. </p><p>The most significant change, and the primary reason that SDRAM has supplanted asynchronous RAM, is the support for multiple internal banks inside the DRAM chip. Using a few bits of <i>bank address</i> that accompany each command, a second bank can be activated and begin reading data <i>while a read from the first bank is in progress</i>. By alternating banks, a single SDRAM device can keep the data bus continuously busy, in a way that asynchronous DRAM cannot. </p> <div class="mw-heading mw-heading4"><h4 id="Single_data_rate_synchronous_DRAM">Single data rate synchronous DRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=37" title="Edit section: Single data rate synchronous DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">SDR SDRAM</a></div> <p>Single data rate SDRAM (SDR SDRAM or SDR) is the original generation of SDRAM; it made a single transfer of data per clock cycle. </p> <div class="mw-heading mw-heading4"><h4 id="Double_data_rate_synchronous_DRAM">Double data rate synchronous DRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=38" title="Edit section: Double data rate synchronous DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>, <a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2 SDRAM</a>, <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a>, <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a>, and <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5 SDRAM</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:SAMSUNG@DDR-SDRAM@64MBit@K4D62323HA-QC60_Stack-DSC03539-DSC03556_-_ZS-DMap.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b9/SAMSUNG%40DDR-SDRAM%4064MBit%40K4D62323HA-QC60_Stack-DSC03539-DSC03556_-_ZS-DMap.jpg/220px-SAMSUNG%40DDR-SDRAM%4064MBit%40K4D62323HA-QC60_Stack-DSC03539-DSC03556_-_ZS-DMap.jpg" decoding="async" width="220" height="149" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b9/SAMSUNG%40DDR-SDRAM%4064MBit%40K4D62323HA-QC60_Stack-DSC03539-DSC03556_-_ZS-DMap.jpg/330px-SAMSUNG%40DDR-SDRAM%4064MBit%40K4D62323HA-QC60_Stack-DSC03539-DSC03556_-_ZS-DMap.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b9/SAMSUNG%40DDR-SDRAM%4064MBit%40K4D62323HA-QC60_Stack-DSC03539-DSC03556_-_ZS-DMap.jpg/440px-SAMSUNG%40DDR-SDRAM%4064MBit%40K4D62323HA-QC60_Stack-DSC03539-DSC03556_-_ZS-DMap.jpg 2x" data-file-width="5628" data-file-height="3821" /></a><figcaption>The <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">die</a> of a Samsung DDR-SDRAM 64-MBit package</figcaption></figure> <p>Double data rate SDRAM (DDR SDRAM or DDR) was a later development of SDRAM, used in PC memory beginning in 2000. Subsequent versions are numbered sequentially (<i>DDR2</i>, <i>DDR3</i>, etc.). DDR SDRAM internally performs double-width accesses at the clock rate, and uses a <a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a> interface to transfer one half on each clock edge. DDR2 and DDR3 increased this factor to 4× and 8×, respectively, delivering 4-word and 8-word bursts over 2 and 4 clock cycles, respectively. The internal access rate is mostly unchanged (200 million per second for DDR-400, DDR2-800 and DDR3-1600 memory), but each access transfers more data. </p> <div class="mw-heading mw-heading4"><h4 id="Direct_Rambus_DRAM">Direct Rambus DRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=39" title="Edit section: Direct Rambus DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/RDRAM" title="RDRAM">RDRAM</a></div> <p><i>Direct RAMBUS DRAM</i> (<i>DRDRAM</i>) was developed by Rambus. First supported on <a href="/wiki/Motherboard" title="Motherboard">motherboards</a> in 1999, it was intended to become an industry standard, but was outcompeted by <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>, making it technically obsolete by 2003. </p> <div class="mw-heading mw-heading4"><h4 id="Reduced_Latency_DRAM">Reduced Latency DRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=40" title="Edit section: Reduced Latency DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/RLDRAM" title="RLDRAM">RLDRAM</a></div> <p>Reduced Latency DRAM (RLDRAM) is a high performance double data rate (DDR) SDRAM that combines fast, random access with high bandwidth, mainly intended for networking and caching applications. </p> <div class="mw-heading mw-heading3"><h3 id="Graphics_RAM">Graphics RAM</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=41" title="Edit section: Graphics RAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Graphics RAMs are asynchronous and synchronous DRAMs designed for graphics-related tasks such as <a href="/wiki/Texture_memory" title="Texture memory">texture memory</a> and <a href="/wiki/Framebuffer" title="Framebuffer">framebuffers</a>, found on <a href="/wiki/Video_card" class="mw-redirect" title="Video card">video cards</a>. </p> <div class="mw-heading mw-heading4"><h4 id="Video_DRAM">Video DRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=42" title="Edit section: Video DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/VRAM" class="mw-redirect" title="VRAM">VRAM</a></div> <p>Video DRAM (VRAM) is a <a href="/wiki/Dual-ported_RAM" title="Dual-ported RAM">dual-ported</a> variant of DRAM that was once commonly used to store the frame-buffer in some <a href="/wiki/Graphics_card" title="Graphics card">graphics adaptors</a>. </p> <div class="mw-heading mw-heading4"><h4 id="Window_DRAM"><span class="anchor" id="WRAM"></span>Window DRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=43" title="Edit section: Window DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Window DRAM (WRAM) is a variant of VRAM that was once used in graphics adaptors such as the <a href="/wiki/Matrox" title="Matrox">Matrox</a> Millennium and <a href="/wiki/Rage_Pro#3D_Rage_Pro_&_Rage_IIc" class="mw-redirect" title="Rage Pro">ATI 3D Rage Pro</a>. WRAM was designed to perform better and cost less than VRAM. WRAM offered up to 25% greater bandwidth than VRAM and accelerated commonly used graphical operations such as text drawing and block fills.<sup id="cite_ref-wramdef_70-0" class="reference"><a href="#cite_note-wramdef-70"><span class="cite-bracket">[</span>70<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Multibank_DRAM"><span class="anchor" id="MDRAM"></span>Multibank DRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=44" title="Edit section: Multibank DRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:MoSys_MD908.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3d/MoSys_MD908.png/250px-MoSys_MD908.png" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3d/MoSys_MD908.png/330px-MoSys_MD908.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3d/MoSys_MD908.png/500px-MoSys_MD908.png 2x" data-file-width="627" data-file-height="627" /></a><figcaption><a href="/wiki/MoSys" title="MoSys">MoSys</a> MDRAM MD908</figcaption></figure> <p>Multibank DRAM (MDRAM) is a type of specialized DRAM developed by <a href="/wiki/MoSys" title="MoSys">MoSys</a>. It is constructed from small <a href="/wiki/Memory_bank" title="Memory bank">memory banks</a> of <span class="nowrap">256 kB</span>, which are operated in an <a href="/wiki/Interleaved_memory" title="Interleaved memory">interleaved</a> fashion, providing bandwidths suitable for graphics cards at a lower cost to memories such as <a href="/wiki/Static_Random_Access_Memory" class="mw-redirect" title="Static Random Access Memory">SRAM</a>. MDRAM also allows operations to two banks in a single clock cycle, permitting multiple concurrent accesses to occur if the accesses were independent. MDRAM was primarily used in graphic cards, such as those featuring the <a href="/wiki/Tseng_Labs" title="Tseng Labs">Tseng Labs</a> ET6x00 chipsets. Boards based upon this chipset often had the unusual capacity of <span class="nowrap">2.25 MB</span> because of MDRAM's ability to be implemented more easily with such capacities. A graphics card with <span class="nowrap">2.25 MB</span> of MDRAM had enough memory to provide 24-bit color at a resolution of 1024×768—a very popular setting at the time. </p> <div class="mw-heading mw-heading4"><h4 id="Synchronous_graphics_RAM"><span class="anchor" id="SGRAM"></span>Synchronous graphics RAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=45" title="Edit section: Synchronous graphics RAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Synchronous graphics RAM (SGRAM) is a specialized form of SDRAM for graphics adaptors. It adds functions such as <a href="/wiki/Bit_mask" class="mw-redirect" title="Bit mask">bit masking</a> (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike VRAM and WRAM, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the dual-port nature of other video RAM technologies. </p> <div class="mw-heading mw-heading4"><h4 id="Graphics_double_data_rate_SDRAM">Graphics double data rate SDRAM</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=46" title="Edit section: Graphics double data rate SDRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/GDDR" class="mw-redirect" title="GDDR">GDDR</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Sapphire_Ultimate_HD_4670_512MB_-_Qimonda_HYB18H512321BF-10-93577.jpg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c2/Sapphire_Ultimate_HD_4670_512MB_-_Qimonda_HYB18H512321BF-10-93577.jpg/220px-Sapphire_Ultimate_HD_4670_512MB_-_Qimonda_HYB18H512321BF-10-93577.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c2/Sapphire_Ultimate_HD_4670_512MB_-_Qimonda_HYB18H512321BF-10-93577.jpg/330px-Sapphire_Ultimate_HD_4670_512MB_-_Qimonda_HYB18H512321BF-10-93577.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c2/Sapphire_Ultimate_HD_4670_512MB_-_Qimonda_HYB18H512321BF-10-93577.jpg/440px-Sapphire_Ultimate_HD_4670_512MB_-_Qimonda_HYB18H512321BF-10-93577.jpg 2x" data-file-width="3753" data-file-height="2815" /></a><figcaption>A 512-MBit <a href="/wiki/Qimonda" title="Qimonda">Qimonda</a> GDDR3 SDRAM package</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:SAMSUNG@QDDR3-SDRAM@256MBit@K5J55323QF-GC16_Stack-DSC01340-DSC01367_-_ZS-retouched.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a0/SAMSUNG%40QDDR3-SDRAM%40256MBit%40K5J55323QF-GC16_Stack-DSC01340-DSC01367_-_ZS-retouched.jpg/220px-SAMSUNG%40QDDR3-SDRAM%40256MBit%40K5J55323QF-GC16_Stack-DSC01340-DSC01367_-_ZS-retouched.jpg" decoding="async" width="220" height="153" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a0/SAMSUNG%40QDDR3-SDRAM%40256MBit%40K5J55323QF-GC16_Stack-DSC01340-DSC01367_-_ZS-retouched.jpg/330px-SAMSUNG%40QDDR3-SDRAM%40256MBit%40K5J55323QF-GC16_Stack-DSC01340-DSC01367_-_ZS-retouched.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a0/SAMSUNG%40QDDR3-SDRAM%40256MBit%40K5J55323QF-GC16_Stack-DSC01340-DSC01367_-_ZS-retouched.jpg/440px-SAMSUNG%40QDDR3-SDRAM%40256MBit%40K5J55323QF-GC16_Stack-DSC01340-DSC01367_-_ZS-retouched.jpg 2x" data-file-width="5305" data-file-height="3691" /></a><figcaption>Inside a Samsung GDDR3 256-MBit package</figcaption></figure> <p>Graphics double data rate SDRAM is a type of specialized <a href="/wiki/Double_data_rate" title="Double data rate">DDR</a> <a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">SDRAM</a> designed to be used as the main memory of <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">graphics processing units</a> (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 2020, there are seven, successive generations of GDDR: <a href="/wiki/GDDR2" class="mw-redirect" title="GDDR2">GDDR2</a>, <a href="/wiki/GDDR3" class="mw-redirect" title="GDDR3">GDDR3</a>, <a href="/wiki/GDDR4" class="mw-redirect" title="GDDR4">GDDR4</a>, <a href="/wiki/GDDR5" class="mw-redirect" title="GDDR5">GDDR5</a>, <a href="/wiki/GDDR5X" class="mw-redirect" title="GDDR5X">GDDR5X</a>, <a href="/wiki/GDDR6" class="mw-redirect" title="GDDR6">GDDR6</a> and <a href="/wiki/GDDR6X" class="mw-redirect" title="GDDR6X">GDDR6X</a>. </p> <div class="mw-heading mw-heading3"><h3 id="Pseudostatic_RAM"><span class="anchor" id="PSRAM"></span>Pseudostatic RAM</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=47" title="Edit section: Pseudostatic RAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Olivetti_JP90_-_Toshiba_TC518129CFWL-80_on_controller-8514.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/68/Olivetti_JP90_-_Toshiba_TC518129CFWL-80_on_controller-8514.jpg/220px-Olivetti_JP90_-_Toshiba_TC518129CFWL-80_on_controller-8514.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/68/Olivetti_JP90_-_Toshiba_TC518129CFWL-80_on_controller-8514.jpg/330px-Olivetti_JP90_-_Toshiba_TC518129CFWL-80_on_controller-8514.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/68/Olivetti_JP90_-_Toshiba_TC518129CFWL-80_on_controller-8514.jpg/440px-Olivetti_JP90_-_Toshiba_TC518129CFWL-80_on_controller-8514.jpg 2x" data-file-width="3168" data-file-height="2376" /></a><figcaption>1 Mbit high speed <a href="/wiki/CMOS" title="CMOS">CMOS</a> pseudostatic RAM, made by <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> </figcaption></figure> <p>Pseudostatic RAM (PSRAM or PSDRAM) is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to static RAM (SRAM). It combines the high density of DRAM with the ease of use of true SRAM. PSRAM is used in the Apple iPhone and other embedded systems such as XFlar Platform.<sup id="cite_ref-71" class="reference"><a href="#cite_note-71"><span class="cite-bracket">[</span>71<span class="cite-bracket">]</span></a></sup> </p><p>Some DRAM components have a <i>self-refresh mode</i>. While this involves much of the same logic that is needed for pseudo-static operation, this mode is often equivalent to a standby mode. It is provided primarily to allow a system to suspend operation of its DRAM controller to save power without losing data stored in DRAM, rather than to allow operation without a separate DRAM controller as is in the case of mentioned PSRAMs. </p><p>An <a href="/wiki/EDRAM" title="EDRAM">embedded</a> variant of PSRAM was sold by MoSys under the name <a href="/wiki/1T-SRAM" title="1T-SRAM">1T-SRAM</a>. It is a set of small DRAM banks with an SRAM cache in front to make it behave much like a true SRAM. It is used in <a href="/wiki/Nintendo" title="Nintendo">Nintendo</a> <a href="/wiki/GameCube" title="GameCube">GameCube</a> and <a href="/wiki/Wii" title="Wii">Wii</a> video game consoles. </p><p><a href="/wiki/Cypress_Semiconductor" title="Cypress Semiconductor">Cypress Semiconductor</a>'s HyperRAM<sup id="cite_ref-72" class="reference"><a href="#cite_note-72"><span class="cite-bracket">[</span>72<span class="cite-bracket">]</span></a></sup> is a type of PSRAM supporting a <a href="/wiki/JEDEC_memory_standards" title="JEDEC memory standards">JEDEC</a>-compliant 8-pin HyperBus<sup id="cite_ref-73" class="reference"><a href="#cite_note-73"><span class="cite-bracket">[</span>73<span class="cite-bracket">]</span></a></sup> or Octal xSPI interface. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=48" title="Edit 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memory</a></li> <li><a href="/wiki/List_of_interface_bit_rates" title="List of interface bit rates">List of interface bit rates</a></li> <li><a href="/wiki/Memory_bank" title="Memory bank">Memory bank</a></li> <li><a href="/wiki/Memory_geometry" title="Memory geometry">Memory geometry</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=49" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output 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.cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://zeptobars.com/en/read/how-to-open-microchip-asic-what-inside">"How to "open" microchip and what's inside? : ZeptoBars"</a>. 2012-11-15. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160314015357/http://zeptobars.com/en/read/how-to-open-microchip-asic-what-inside">Archived</a> from the original on 2016-03-14<span class="reference-accessdate">. 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Retrieved <span class="nowrap">2018-04-16</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.icinsights.com&rft.atitle=Are+the+Major+DRAM+Suppliers+Stunting+DRAM+Demand%3F&rft_id=http%3A%2F%2Fwww.icinsights.com%2Fnews%2Fbulletins%2FAre-The-Major-DRAM-Suppliers-Stunting-DRAM-Demand%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+random-access+memory" class="Z3988"></span></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFEETimesHilson2018" class="citation web cs1">EETimes; Hilson, Gary (2018-09-20). <a rel="nofollow" class="external text" href="https://www.eetimes.com/dram-boom-and-bust-is-business-as-usual/">"DRAM Boom and Bust is Business as Usual"</a>. <i>EETimes</i><span class="reference-accessdate">. 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Archived from <a rel="nofollow" class="external text" href="http://www.eetimes.com/showArticle.jhtml?articleID=209000014#selection-1371.0-1383.10">the original</a> on 2013-01-22.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=EETimes&rft.atitle=Under+the+Hood+%E2%80%94+Update%3A+Apple+iPhone+3G+exposed&rft.date=2008-07-12&rft.aulast=Mannion&rft.aufirst=Patrick&rft_id=http%3A%2F%2Fwww.eetimes.com%2FshowArticle.jhtml%3FarticleID%3D209000014%23selection-1371.0-1383.10&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+random-access+memory" class="Z3988"></span></span> </li> <li id="cite_note-72"><span class="mw-cite-backlink"><b><a href="#cite_ref-72">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cypress.com/products/hyperram-octal-xspi-ram-memory">"psRAM(HyperRAM)"</a>. Cypress semiconductor.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=psRAM%28HyperRAM%29&rft.pub=Cypress+semiconductor&rft_id=https%3A%2F%2Fwww.cypress.com%2Fproducts%2Fhyperram-octal-xspi-ram-memory&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+random-access+memory" class="Z3988"></span></span> </li> <li id="cite_note-73"><span class="mw-cite-backlink"><b><a href="#cite_ref-73">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cypress.com/products/hyperbus-memory">"Hyperbus"</a>. Cypress semiconductor.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Hyperbus&rft.pub=Cypress+semiconductor&rft_id=https%3A%2F%2Fwww.cypress.com%2Fproducts%2Fhyperbus-memory&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+random-access+memory" class="Z3988"></span></span> </li> </ol></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFKeethBakerJohnsonLin2007" class="citation book cs1">Keeth, Brent; Baker, R. Jacob; Johnson, Brian; Lin, Feng (2007). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=TgW3LTubREQC"><i>DRAM Circuit Design: Fundamental and High-Speed Topics</i></a>. Wiley. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0470184752" title="Special:BookSources/978-0470184752"><bdi>978-0470184752</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=DRAM+Circuit+Design%3A+Fundamental+and+High-Speed+Topics&rft.pub=Wiley&rft.date=2007&rft.isbn=978-0470184752&rft.aulast=Keeth&rft.aufirst=Brent&rft.au=Baker%2C+R.+Jacob&rft.au=Johnson%2C+Brian&rft.au=Lin%2C+Feng&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DTgW3LTubREQC&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+random-access+memory" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=50" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFJacobWangNg2010" class="citation book cs1">Jacob, Bruce; Wang, David; Ng, Spencer (2010) [2008]. <a rel="nofollow" class="external text" href="https://books.google.com/books?id=SrP3aWed-esC"><i>Memory Systems: Cache, DRAM, Disk</i></a>. Morgan Kaufmann. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-08-055384-9" title="Special:BookSources/978-0-08-055384-9"><bdi>978-0-08-055384-9</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Memory+Systems%3A+Cache%2C+DRAM%2C+Disk&rft.pub=Morgan+Kaufmann&rft.date=2010&rft.isbn=978-0-08-055384-9&rft.aulast=Jacob&rft.aufirst=Bruce&rft.au=Wang%2C+David&rft.au=Ng%2C+Spencer&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DSrP3aWed-esC&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+random-access+memory" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_random-access_memory&action=edit&section=51" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFCuller2005" class="citation book cs1">Culler, David (2005). "Memory Capacity (Single Chip DRAM)". <a rel="nofollow" class="external text" href="http://www.eecs.berkeley.edu/~culler/courses/cs252-s05/lectures/cs252s05-lec01-intro.ppt#359,15,Memory%20Capacity%20%20(Single%20Chip%20DRAM"><i>EECS 252 Graduate Computer Architecture: Lecture 1</i></a>. Electrical Engineering and Computer Sciences,University of California, Berkeley. p. 15.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Memory+Capacity+%28Single+Chip+DRAM%29&rft.btitle=EECS+252+Graduate+Computer+Architecture%3A+Lecture+1&rft.pages=15&rft.pub=Electrical+Engineering+and+Computer+Sciences%2CUniversity+of+California%2C+Berkeley&rft.date=2005&rft.aulast=Culler&rft.aufirst=David&rft_id=http%3A%2F%2Fwww.eecs.berkeley.edu%2F~culler%2Fcourses%2Fcs252-s05%2Flectures%2Fcs252s05-lec01-intro.ppt%23359%2C15%2CMemory%2520Capacity%2520%2520%28Single%2520Chip%2520DRAM&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+random-access+memory" class="Z3988"></span> Logarithmic graph 1980–2003 showing size and cycle time.</li> <li><a rel="nofollow" class="external text" href="http://www-1.ibm.com/servers/eserver/pseries/campaigns/chipkill.pdf">Benefits of Chipkill-Correct ECC for PC Server Main Memory</a> — A 1997 discussion of SDRAM reliability—some interesting information on soft errors from <a href="/wiki/Cosmic_ray" title="Cosmic ray">cosmic rays</a>, especially with respect to <a href="/wiki/Error-correcting_code" class="mw-redirect" title="Error-correcting code">error-correcting code</a> schemes</li> <li><a rel="nofollow" class="external text" href="http://www.tezzaron.com/about/papers/soft_errors_1_1_secure.pdf">Tezzaron Semiconductor Soft Error White Paper</a> 1994 literature review of memory error rate measurements.</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFJohnston2000" class="citation web cs1">Johnston, A. (October 2000). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20041103124422/http://www.nepp.nasa.gov/docuploads/40D7D6C9-D5AA-40FC-829DC2F6A71B02E9/Scal-00.pdf">"Scaling and Technology Issues for Soft Error Rates"</a> <span class="cs1-format">(PDF)</span>. <i>4th Annual Research Conference on Reliability Stanford University</i>. Archived from <a rel="nofollow" class="external text" href="https://www.nepp.nasa.gov/docuploads/40D7D6C9-D5AA-40FC-829DC2F6A71B02E9/Scal-00.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2004-11-03.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=4th+Annual+Research+Conference+on+Reliability+Stanford+University&rft.atitle=Scaling+and+Technology+Issues+for+Soft+Error+Rates&rft.date=2000-10&rft.aulast=Johnston&rft.aufirst=A.&rft_id=http%3A%2F%2Fwww.nepp.nasa.gov%2Fdocuploads%2F40D7D6C9-D5AA-40FC-829DC2F6A71B02E9%2FScal-00.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+random-access+memory" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFMandelmanDennardBronnerDebrosse2002" class="citation journal cs1">Mandelman, J. A.; Dennard, R. H.; Bronner, G. B.; Debrosse, J. K.; Divakaruni, R.; Li, Y.; Radens, C. J. (2002). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20050322211513/http://www.research.ibm.com/journal/rd/462/mandelman.html">"Challenges and future directions for the scaling of dynamic random-access memory (DRAM)"</a>. <i>IBM Journal of Research and Development</i>. <b>46</b> (2.3): <span class="nowrap">187–</span>212. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1147%2Frd.462.0187">10.1147/rd.462.0187</a>. Archived from <a rel="nofollow" class="external text" href="http://www.research.ibm.com/journal/rd/462/mandelman.html">the original</a> on 2005-03-22.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IBM+Journal+of+Research+and+Development&rft.atitle=Challenges+and+future+directions+for+the+scaling+of+dynamic+random-access+memory+%28DRAM%29&rft.volume=46&rft.issue=2.3&rft.pages=%3Cspan+class%3D%22nowrap%22%3E187-%3C%2Fspan%3E212&rft.date=2002&rft_id=info%3Adoi%2F10.1147%2Frd.462.0187&rft.aulast=Mandelman&rft.aufirst=J.+A.&rft.au=Dennard%2C+R.+H.&rft.au=Bronner%2C+G.+B.&rft.au=Debrosse%2C+J.+K.&rft.au=Divakaruni%2C+R.&rft.au=Li%2C+Y.&rft.au=Radens%2C+C.+J.&rft_id=http%3A%2F%2Fwww.research.ibm.com%2Fjournal%2Frd%2F462%2Fmandelman.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+random-access+memory" class="Z3988"></span></li> <li><a rel="nofollow" class="external text" href="https://arstechnica.com/paedia/r/ram_guide/ram_guide.part1-2.html">Ars Technica: RAM Guide</a></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFWang2005" class="citation thesis cs1">Wang, David Tawei (2005). <a rel="nofollow" class="external text" href="http://www.ece.umd.edu/~blj/papers/thesis-PhD-wang--DRAM.pdf"><i>Modern DRAM Memory Systems: Performance Analysis and a High Performance, Power-Constrained DRAM-Scheduling Algorithm</i></a> <span class="cs1-format">(PDF)</span> (PhD). University of Maryland, College Park. <a href="/wiki/Hdl_(identifier)" class="mw-redirect" title="Hdl (identifier)">hdl</a>:<a rel="nofollow" class="external text" href="https://hdl.handle.net/1903%2F2432">1903/2432</a><span class="reference-accessdate">. Retrieved <span class="nowrap">2007-03-10</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adissertation&rft.title=Modern+DRAM+Memory+Systems%3A+Performance+Analysis+and+a+High+Performance%2C+Power-Constrained+DRAM-Scheduling+Algorithm&rft.inst=University+of+Maryland%2C+College+Park&rft.date=2005&rft_id=info%3Ahdl%2F1903%2F2432&rft.aulast=Wang&rft.aufirst=David+Tawei&rft_id=http%3A%2F%2Fwww.ece.umd.edu%2F~blj%2Fpapers%2Fthesis-PhD-wang--DRAM.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+random-access+memory" class="Z3988"></span> A detailed description of current DRAM technology.</li> <li><a rel="nofollow" class="external text" href="http://www.cs.berkeley.edu/~pattrsn/294">Multi-port Cache DRAM — <b>MP-RAM</b></a></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFDrepper2007" class="citation web cs1">Drepper, Ulrich (2007). <a rel="nofollow" class="external text" href="https://lwn.net/Articles/250967/">"What every programmer should know about memory"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=What+every+programmer+should+know+about+memory&rft.date=2007&rft.aulast=Drepper&rft.aufirst=Ulrich&rft_id=https%3A%2F%2Flwn.net%2FArticles%2F250967%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+random-access+memory" class="Z3988"></span></li></ul> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><style data-mw-deduplicate="TemplateStyles:r1236075235">.mw-parser-output .navbox{box-sizing:border-box;border:1px solid #a2a9b1;width:100%;clear:both;font-size:88%;text-align:center;padding:1px;margin:1em auto 0}.mw-parser-output .navbox .navbox{margin-top:0}.mw-parser-output .navbox+.navbox,.mw-parser-output .navbox+.navbox-styles+.navbox{margin-top:-1px}.mw-parser-output .navbox-inner,.mw-parser-output .navbox-subgroup{width:100%}.mw-parser-output .navbox-group,.mw-parser-output .navbox-title,.mw-parser-output .navbox-abovebelow{padding:0.25em 1em;line-height:1.5em;text-align:center}.mw-parser-output .navbox-group{white-space:nowrap;text-align:right}.mw-parser-output .navbox,.mw-parser-output .navbox-subgroup{background-color:#fdfdfd}.mw-parser-output .navbox-list{line-height:1.5em;border-color:#fdfdfd}.mw-parser-output .navbox-list-with-group{text-align:left;border-left-width:2px;border-left-style:solid}.mw-parser-output tr+tr>.navbox-abovebelow,.mw-parser-output tr+tr>.navbox-group,.mw-parser-output tr+tr>.navbox-image,.mw-parser-output tr+tr>.navbox-list{border-top:2px solid #fdfdfd}.mw-parser-output .navbox-title{background-color:#ccf}.mw-parser-output .navbox-abovebelow,.mw-parser-output .navbox-group,.mw-parser-output .navbox-subgroup .navbox-title{background-color:#ddf}.mw-parser-output .navbox-subgroup .navbox-group,.mw-parser-output .navbox-subgroup .navbox-abovebelow{background-color:#e6e6ff}.mw-parser-output .navbox-even{background-color:#f7f7f7}.mw-parser-output .navbox-odd{background-color:transparent}.mw-parser-output .navbox .hlist td dl,.mw-parser-output .navbox .hlist td ol,.mw-parser-output .navbox .hlist td ul,.mw-parser-output .navbox td.hlist dl,.mw-parser-output .navbox td.hlist ol,.mw-parser-output .navbox td.hlist ul{padding:0.125em 0}.mw-parser-output .navbox .navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="Dynamic_random-access_memory_(DRAM)148" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231" /><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:DRAM" title="Template:DRAM"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:DRAM" title="Template talk:DRAM"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:DRAM" title="Special:EditPage/Template:DRAM"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Dynamic_random-access_memory_(DRAM)148" style="font-size:114%;margin:0 4em"><a class="mw-selflink selflink">Dynamic random-access memory</a> (DRAM)</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Asynchronous</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/FPM_DRAM" class="mw-redirect" title="FPM DRAM">FPM DRAM</a></li> <li><a href="/wiki/EDO_DRAM" class="mw-redirect" title="EDO DRAM">EDO DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">SDRAM</a></li> <li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> <ul><li><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a></li> <li><a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a></li> <li><a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a></li> <li><a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a></li></ul></li> <li><a href="/wiki/LPDDR" title="LPDDR">LPDDR</a> (Mobile DDR)</li> <li><a href="/wiki/Fast_Cycle_DRAM" title="Fast Cycle DRAM">Fast Cycle DRAM</a> (FCRAM)</li> <li><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a></li> <li><a href="/wiki/RLDRAM" title="RLDRAM">RLDRAM</a></li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a> <ul><li><a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a></li> <li><a href="/wiki/HBM2E" class="mw-redirect" title="HBM2E">HBM2E</a></li> <li><a href="/wiki/HBM3" class="mw-redirect" title="HBM3">HBM3</a></li> <li><a href="/wiki/HBM-PIM" class="mw-redirect" title="HBM-PIM">HBM-PIM</a></li> <li><a href="/wiki/HBM3E" class="mw-redirect" title="HBM3E">HBM3E</a></li></ul></li> <li><a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Graphics</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">VRAM</a></li> <li><a href="/wiki/WRAM_(memory)" class="mw-redirect" title="WRAM (memory)">WRAM</a></li> <li><a href="/wiki/MDRAM" class="mw-redirect" title="MDRAM">MDRAM</a></li> <li><a href="/wiki/SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a> <ul><li><a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR</a></li> <li><a href="/wiki/GDDR2_SDRAM" class="mw-redirect" title="GDDR2 SDRAM">GDDR2</a></li> <li><a href="/wiki/GDDR3_SDRAM" title="GDDR3 SDRAM">GDDR3</a></li> <li><a href="/wiki/GDDR4_SDRAM" title="GDDR4 SDRAM">GDDR4</a></li> <li><a href="/wiki/GDDR5_SDRAM" title="GDDR5 SDRAM">GDDR5</a></li> <li><a href="/wiki/GDDR6_SDRAM" title="GDDR6 SDRAM">GDDR6</a></li> <li><a href="/wiki/GDDR7_SDRAM" title="GDDR7 SDRAM">GDDR7</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Rambus" title="Rambus">Rambus</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a></li> <li><a href="/wiki/XDR_DRAM" title="XDR DRAM">XDR DRAM</a></li> <li><a href="/wiki/XDR2_DRAM" title="XDR2 DRAM">XDR2 DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Memory_module" title="Memory module">Memory modules</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/SIMM" title="SIMM">SIMM</a></li> <li><a href="/wiki/DIMM" title="DIMM">DIMM</a></li> <li><a href="/wiki/UniDIMM" title="UniDIMM">UniDIMM</a></li> <li><a href="/wiki/CAMM_(memory_module)" title="CAMM (memory module)">CAMM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" 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