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circuits</title> <meta name="description" content="Search results for: circuits"> <meta name="keywords" content="circuits"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> <button class="d-block d-lg-none navbar-toggler ml-auto" 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id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="circuits"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 306</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: circuits</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">306</span> One Period Loops of Memristive Circuits with Mixed-Mode Oscillations</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Wieslaw%20Marszalek">Wieslaw Marszalek</a>, <a href="https://publications.waset.org/abstracts/search?q=Zdzislaw%20Trzaska"> Zdzislaw Trzaska</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Interesting properties of various one-period loops of singularly perturbed memristive circuits with mixed-mode oscillations (MMOs) are analyzed in this paper. The analysis is mixed, both analytical and numerical and focused on the properties of pinched hysteresis of the memristive element and other one-period loops formed by pairs of time-series solutions for various circuits' variables. The memristive element is the only nonlinear element in the two circuits. A theorem on periods of mixed-mode oscillations of the circuits is formulated and proved. Replacements of memristors by parallel G-C or series R-L circuits for a MMO response with equivalent RMS values is also discussed. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=mixed-mode%20oscillations" title="mixed-mode oscillations">mixed-mode oscillations</a>, <a href="https://publications.waset.org/abstracts/search?q=memristive%20circuits" title=" memristive circuits"> memristive circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=pinched%20hysteresis" title=" pinched hysteresis"> pinched hysteresis</a>, <a href="https://publications.waset.org/abstracts/search?q=one-period%20loops" title=" one-period loops"> one-period loops</a>, <a href="https://publications.waset.org/abstracts/search?q=singularly%20perturbed%20circuits" title=" singularly perturbed circuits"> singularly perturbed circuits</a> </p> <a href="https://publications.waset.org/abstracts/20949/one-period-loops-of-memristive-circuits-with-mixed-mode-oscillations" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/20949.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">470</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">305</span> Efficient Study of Substrate Integrated Waveguide Devices</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=J.%20Hajri">J. Hajri</a>, <a href="https://publications.waset.org/abstracts/search?q=H.%20Hrizi"> H. Hrizi</a>, <a href="https://publications.waset.org/abstracts/search?q=N.%20Sboui"> N. Sboui</a>, <a href="https://publications.waset.org/abstracts/search?q=H.%20Baudrand"> H. Baudrand</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a study of SIW circuits (Substrate Integrated Waveguide) with a rigorous and fast original approach based on Iterative process (WCIP). The theoretical suggested study is validated by the simulation of two different examples of SIW circuits. The obtained results are in good agreement with those of measurement and with software HFSS. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=convergence%20study" title="convergence study">convergence study</a>, <a href="https://publications.waset.org/abstracts/search?q=HFSS" title=" HFSS"> HFSS</a>, <a href="https://publications.waset.org/abstracts/search?q=modal%20decomposition" title=" modal decomposition"> modal decomposition</a>, <a href="https://publications.waset.org/abstracts/search?q=SIW%20circuits" title=" SIW circuits"> SIW circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=WCIP%20method" title=" WCIP method"> WCIP method</a> </p> <a href="https://publications.waset.org/abstracts/22247/efficient-study-of-substrate-integrated-waveguide-devices" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/22247.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">498</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">304</span> Two Kinds of Self-Oscillating Circuits Mechanically Demonstrated</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Shiang-Hwua%20Yu">Shiang-Hwua Yu</a>, <a href="https://publications.waset.org/abstracts/search?q=Po-Hsun%20Wu"> Po-Hsun Wu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This study introduces two types of self-oscillating circuits that are frequently found in power electronics applications. Special effort is made to relate the circuits to the analogous mechanical systems of some important scientific inventions: Galileo’s pendulum clock and Coulomb’s friction model. A little touch of related history and philosophy of science will hopefully encourage curiosity, advance the understanding of self-oscillating systems and satisfy the aspiration of some students for scientific literacy. Finally, the two self-oscillating circuits are applied to design a simple class-D audio amplifier. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=self-oscillation" title="self-oscillation">self-oscillation</a>, <a href="https://publications.waset.org/abstracts/search?q=sigma-delta%20modulator" title=" sigma-delta modulator"> sigma-delta modulator</a>, <a href="https://publications.waset.org/abstracts/search?q=pendulum%20clock" title=" pendulum clock"> pendulum clock</a>, <a href="https://publications.waset.org/abstracts/search?q=Coulomb%20friction" title=" Coulomb friction"> Coulomb friction</a>, <a href="https://publications.waset.org/abstracts/search?q=class-D%20amplifier" title=" class-D amplifier"> class-D amplifier</a> </p> <a href="https://publications.waset.org/abstracts/9932/two-kinds-of-self-oscillating-circuits-mechanically-demonstrated" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/9932.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">356</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">303</span> Optimization and Design of Current-Mode Multiplier Circuits with Applications in Analog Signal Processing for Gas Industrial Package Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mohamad%20Baqer%20Heidari">Mohamad Baqer Heidari</a>, <a href="https://publications.waset.org/abstracts/search?q=Hefzollah.Mohammadian"> Hefzollah.Mohammadian </a> </p> <p class="card-text"><strong>Abstract:</strong></p> This brief presents two original implementations of improved accuracy current-mode multiplier/divider circuits. Besides the advantage of their simplicity, these original multiplier/divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.75% and 0.9%, respectively, for an extended range of the input currents). The original multiplier/divider circuits permit a facile reconfiguration, the presented structures representing the functional basis for implementing complex function synthesizer circuits. The proposed computational structures are designed for implementing in 0.18-µm CMOS technology, with a low-voltage operation (a supply voltage of 1.2 V). The circuits’ power consumptions are 60 and 75 µW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=analog%20signal%20processing" title="analog signal processing">analog signal processing</a>, <a href="https://publications.waset.org/abstracts/search?q=current-mode%20%20operation" title=" current-mode operation"> current-mode operation</a>, <a href="https://publications.waset.org/abstracts/search?q=functional%20core" title=" functional core"> functional core</a>, <a href="https://publications.waset.org/abstracts/search?q=multiplier" title=" multiplier"> multiplier</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20circuits" title=" reconfigurable circuits"> reconfigurable circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=industrial%20package%20systems" title=" industrial package systems"> industrial package systems</a> </p> <a href="https://publications.waset.org/abstracts/36406/optimization-and-design-of-current-mode-multiplier-circuits-with-applications-in-analog-signal-processing-for-gas-industrial-package-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/36406.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">374</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">302</span> Comparative Performance Analysis of Nonlinearity Cancellation Techniques for MOS-C Realization in Integrator Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hasan%20%C3%87i%C3%A7ekli">Hasan Çiçekli</a>, <a href="https://publications.waset.org/abstracts/search?q=Ahmet%20G%C3%B6k%C3%A7en"> Ahmet Gökçen</a>, <a href="https://publications.waset.org/abstracts/search?q=U%C4%9Fur%20%C3%87am"> Uğur Çam</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, a comparative performance analysis of mostly used four nonlinearity cancellation techniques used to realize the passive resistor by MOS transistors is presented. The comparison is done by using an integrator circuit which is employing sequentially Op-amp, OTRA and ICCII as active element. All of the circuits are implemented by MOS-C realization and simulated by PSPICE program using 0.35 µm process TSMC MOSIS model parameters. With MOS-C realization, the circuits became electronically tunable and fully integrable which is very important in IC design. The output waveforms, frequency responses, THD analysis results and features of the nonlinearity cancellation techniques are also given. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=integrator%20circuits" title="integrator circuits">integrator circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=MOS-C%20realization" title=" MOS-C realization"> MOS-C realization</a>, <a href="https://publications.waset.org/abstracts/search?q=nonlinearity%20cancellation" title=" nonlinearity cancellation"> nonlinearity cancellation</a>, <a href="https://publications.waset.org/abstracts/search?q=tuneable%20resistors" title=" tuneable resistors"> tuneable resistors</a> </p> <a href="https://publications.waset.org/abstracts/38167/comparative-performance-analysis-of-nonlinearity-cancellation-techniques-for-mos-c-realization-in-integrator-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/38167.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">533</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">301</span> Tamper Resistance Evaluation Tests with Noise Resources</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Masaya%20Yoshikawa">Masaya Yoshikawa</a>, <a href="https://publications.waset.org/abstracts/search?q=Toshiya%20Asai"> Toshiya Asai</a>, <a href="https://publications.waset.org/abstracts/search?q=Ryoma%20Matsuhisa"> Ryoma Matsuhisa</a>, <a href="https://publications.waset.org/abstracts/search?q=Yusuke%20Nozaki"> Yusuke Nozaki</a>, <a href="https://publications.waset.org/abstracts/search?q=Kensaku%20Asahi"> Kensaku Asahi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Recently, side-channel attacks, which estimate secret keys using side-channel information such as power consumption and compromising emanations of cryptography circuits embedded in hardware, have become a serious problem. In particular, electromagnetic analysis attacks against cryptographic circuits between information processing and electromagnetic fields, which are related to secret keys in cryptography circuits, are the most threatening side-channel attacks. Therefore, it is important to evaluate tamper resistance against electromagnetic analysis attacks for cryptography circuits. The present study performs basic examination of the tamper resistance of cryptography circuits using electromagnetic analysis attacks with noise resources. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=tamper%20resistance" title="tamper resistance">tamper resistance</a>, <a href="https://publications.waset.org/abstracts/search?q=cryptographic%20circuit" title=" cryptographic circuit"> cryptographic circuit</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20security%20evaluation" title=" hardware security evaluation"> hardware security evaluation</a>, <a href="https://publications.waset.org/abstracts/search?q=noise%20resources" title=" noise resources "> noise resources </a> </p> <a href="https://publications.waset.org/abstracts/25852/tamper-resistance-evaluation-tests-with-noise-resources" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/25852.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">504</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">300</span> Memristor-A Promising Candidate for Neural Circuits in Neuromorphic Computing Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Juhi%20Faridi">Juhi Faridi</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohd.%20Ajmal%20Kafeel"> Mohd. Ajmal Kafeel</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The advancements in the field of Artificial Intelligence (AI) and technology has led to an evolution of an intelligent era. Neural networks, having the computational power and learning ability similar to the brain is one of the key AI technologies. Neuromorphic computing system (NCS) consists of the synaptic device, neuronal circuit, and neuromorphic architecture. Memristor are a promising candidate for neuromorphic computing systems, but when it comes to neuromorphic computing, the conductance behavior of the synaptic memristor or neuronal memristor needs to be studied thoroughly in order to fathom the neuroscience or computer science. Furthermore, there is a need of more simulation work for utilizing the existing device properties and providing guidance to the development of future devices for different performance requirements. Hence, development of NCS needs more simulation work to make use of existing device properties. This work aims to provide an insight to build neuronal circuits using memristors to achieve a Memristor based NCS.  Here we throw a light on the research conducted in the field of memristors for building analog and digital circuits in order to motivate the research in the field of NCS by building memristor based neural circuits for advanced AI applications. This literature is a step in the direction where we describe the various Key findings about memristors and its analog and digital circuits implemented over the years which can be further utilized in implementing the neuronal circuits in the NCS. This work aims to help the electronic circuit designers to understand how the research progressed in memristors and how these findings can be used in implementing the neuronal circuits meant for the recent progress in the NCS. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=analog%20circuits" title="analog circuits">analog circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=digital%20circuits" title=" digital circuits"> digital circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=memristors" title=" memristors"> memristors</a>, <a href="https://publications.waset.org/abstracts/search?q=neuromorphic%20computing%20systems" title=" neuromorphic computing systems"> neuromorphic computing systems</a> </p> <a href="https://publications.waset.org/abstracts/100057/memristor-a-promising-candidate-for-neural-circuits-in-neuromorphic-computing-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/100057.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">174</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">299</span> Characteization and Optimization of S-Parameters of Microwave Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=N.%20Ourabia">N. Ourabia</a>, <a href="https://publications.waset.org/abstracts/search?q=M.%20Boubaker%20Ourabia"> M. Boubaker Ourabia</a> </p> <p class="card-text"><strong>Abstract:</strong></p> An approach for modeling and numerical simulation of passive planar structures using the edge line concept is developed. With this method, we develop an efficient modeling technique for microstrip discontinuities. The technique obtains closed form expressions for the equivalent circuits which are used to model these discontinuities. Then, it would be easy to handle and to characterize complicated structures like T and Y junctions, truncated junctions, arbitrarily shaped junctions, cascading junctions and more generally planar multiport junctions. Another advantage of this method is that the edge line concept for arbitrary shape junctions operates with real parameters circuits. The validity of the method was further confirmed by comparing our results for various discontinuities (bend, filters) with those from HFSS as well as from other published sources. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=optimization" title="optimization">optimization</a>, <a href="https://publications.waset.org/abstracts/search?q=CAD%20analysis" title=" CAD analysis"> CAD analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=microwave%20circuits" title=" microwave circuits"> microwave circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=S-parameters" title=" S-parameters"> S-parameters</a> </p> <a href="https://publications.waset.org/abstracts/25946/characteization-and-optimization-of-s-parameters-of-microwave-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/25946.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">454</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">298</span> Paper-Based Detection Using Synthetic Gene Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Vanessa%20Funk">Vanessa Funk</a>, <a href="https://publications.waset.org/abstracts/search?q=Steven%20Blum"> Steven Blum</a>, <a href="https://publications.waset.org/abstracts/search?q=Stephanie%20Cole"> Stephanie Cole</a>, <a href="https://publications.waset.org/abstracts/search?q=Jorge%20Maciel"> Jorge Maciel</a>, <a href="https://publications.waset.org/abstracts/search?q=Matthew%20Lux"> Matthew Lux</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Paper-based synthetic gene circuits offer a new paradigm for programmable, fieldable biodetection. We demonstrate that by freeze-drying gene circuits with in vitro expression machinery, we can use complimentary RNA sequences to trigger colorimetric changes upon rehydration. We have successfully utilized both green fluorescent protein and luciferase-based reporters for easy visualization purposes in solution. Through several efforts, we are aiming to use this new platform technology to address a variety of needs in portable detection by demonstrating several more expression and reporter systems for detection functions on paper. In addition to RNA-based biodetection, we are exploring the use of various mechanisms that cells use to respond to environmental conditions to move towards all-hazards detection. Examples include explosives, heavy metals for water quality, and toxic chemicals. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cell-free%20lysates" title="cell-free lysates">cell-free lysates</a>, <a href="https://publications.waset.org/abstracts/search?q=detection" title=" detection"> detection</a>, <a href="https://publications.waset.org/abstracts/search?q=gene%20circuits" title=" gene circuits"> gene circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=in%20vitro" title=" in vitro"> in vitro</a> </p> <a href="https://publications.waset.org/abstracts/71047/paper-based-detection-using-synthetic-gene-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/71047.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">394</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">297</span> First Order Filter Based Current-Mode Sinusoidal Oscillators Using Current Differencing Transconductance Amplifiers (CDTAs)</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=S.%20Summart">S. Summart</a>, <a href="https://publications.waset.org/abstracts/search?q=C.%20Saetiaw"> C. Saetiaw</a>, <a href="https://publications.waset.org/abstracts/search?q=T.%20Thosdeekoraphat"> T. Thosdeekoraphat</a>, <a href="https://publications.waset.org/abstracts/search?q=C.%20Thongsopa"> C. Thongsopa</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This article presents new current-mode oscillator circuits using CDTAs which is designed from block diagram. The proposed circuits consist of two CDTAs and two grounded capacitors. The condition of oscillation and the frequency of oscillation can be adjusted by electronic method. The circuits have high output impedance and use only grounded capacitors without any external resistor which is very appropriate to future development into an integrated circuit. The results of PSPICE simulation program are corresponding to the theoretical analysis. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=current-mode" title="current-mode">current-mode</a>, <a href="https://publications.waset.org/abstracts/search?q=quadrature%20oscillator" title=" quadrature oscillator"> quadrature oscillator</a>, <a href="https://publications.waset.org/abstracts/search?q=block%20diagram" title=" block diagram"> block diagram</a>, <a href="https://publications.waset.org/abstracts/search?q=CDTA" title=" CDTA"> CDTA</a> </p> <a href="https://publications.waset.org/abstracts/8914/first-order-filter-based-current-mode-sinusoidal-oscillators-using-current-differencing-transconductance-amplifiers-cdtas" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/8914.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">453</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">296</span> Importance of Hardware Systems and Circuits in Secure Software Development Life Cycle</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mir%20Shahriar%20Emami">Mir Shahriar Emami</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Although it is fully impossible to ensure that a software system is quite secure, developing an acceptable secure software system in a convenient platform is not unreachable. In this paper, we attempt to analyze software development life cycle (SDLC) models from the hardware systems and circuits point of view. To date, the SDLC models pay merely attention to the software security from the software perspectives. In this paper, we present new features for SDLC stages to emphasize the role of systems and circuits in developing secure software system through the software development stages, the point that has not been considered previously in the SDLC models. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SDLC" title="SDLC">SDLC</a>, <a href="https://publications.waset.org/abstracts/search?q=SSDLC" title=" SSDLC"> SSDLC</a>, <a href="https://publications.waset.org/abstracts/search?q=software%20security" title=" software security"> software security</a>, <a href="https://publications.waset.org/abstracts/search?q=software%20process%20engineering" title=" software process engineering"> software process engineering</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20systems%20and%20circuits%20security" title=" hardware systems and circuits security"> hardware systems and circuits security</a> </p> <a href="https://publications.waset.org/abstracts/55558/importance-of-hardware-systems-and-circuits-in-secure-software-development-life-cycle" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/55558.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">261</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">295</span> Efficient Modeling Technique for Microstrip Discontinuities</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nassim%20Ourabia">Nassim Ourabia</a>, <a href="https://publications.waset.org/abstracts/search?q=Malika%20Ourabia"> Malika Ourabia</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A new and efficient method is presented for the analysis of arbitrarily shaped discontinuities. The technique obtains closed form expressions for the equivalent circuits which are used to model these discontinuities. Then it would be easy to handle and to characterize complicated structures like T and Y junctions, truncated junctions, arbitrarily shaped junctions, cascading junctions, and more generally planar multiport junctions. Another advantage of this method is that the edge line concept for arbitrary shape junctions operates with real parameters circuits. The validity of the method was further confirmed by comparing our results for various discontinuities (bend, filters) with those from HFSS as well as from other published sources. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CAD%20analysis" title="CAD analysis">CAD analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=contour%20integral%20approach" title=" contour integral approach"> contour integral approach</a>, <a href="https://publications.waset.org/abstracts/search?q=microwave%20circuits" title=" microwave circuits"> microwave circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=s-parameters" title=" s-parameters"> s-parameters</a> </p> <a href="https://publications.waset.org/abstracts/25945/efficient-modeling-technique-for-microstrip-discontinuities" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/25945.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">516</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">294</span> Design and Implementation of Testable Reversible Sequential Circuits Optimized Power</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=B.%20Manikandan">B. Manikandan</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Vijayaprabhu"> A. Vijayaprabhu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The conservative reversible gates are used to designed reversible sequential circuits. The sequential circuits are flip-flops and latches. The conservative logic gates are Feynman, Toffoli, and Fredkin. The design of two vectors testable sequential circuits based on conservative logic gates. All sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum- dot cellular automata (QCA) layout of the Fredkin gate. The conservative logic gates are in terms of complexity, speed, and area. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=DET" title="DET">DET</a>, <a href="https://publications.waset.org/abstracts/search?q=QCA" title=" QCA"> QCA</a>, <a href="https://publications.waset.org/abstracts/search?q=reversible%20logic%20gates" title=" reversible logic gates"> reversible logic gates</a>, <a href="https://publications.waset.org/abstracts/search?q=POS" title=" POS"> POS</a>, <a href="https://publications.waset.org/abstracts/search?q=SOP" title=" SOP"> SOP</a>, <a href="https://publications.waset.org/abstracts/search?q=latches" title=" latches"> latches</a>, <a href="https://publications.waset.org/abstracts/search?q=flip%20flops" title=" flip flops"> flip flops</a> </p> <a href="https://publications.waset.org/abstracts/42418/design-and-implementation-of-testable-reversible-sequential-circuits-optimized-power" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/42418.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">304</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">293</span> SPICE Modeling for Evaluation of Distribution System Reliability Indices</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=G.%20N.%20Srinivas">G. N. Srinivas</a>, <a href="https://publications.waset.org/abstracts/search?q=K.%20Raju"> K. Raju</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents Markov processes for determining the reliability indices of distribution system. The continuous Markov modeling is applied to a complex radial distribution system and electrical equivalent circuits are developed for the modeling. In general PSPICE is being used for electrical and electronic circuits and various applications of power system like fault analysis, transient analysis etc. In this paper, the SPICE modeling equivalent circuits which are developed are applied in a novel way to Distribution System reliability analysis. These circuits are simulated using PSPICE software to obtain the state probabilities, the basic and performance indices. Thus the basic indices and the performance indices obtained by this method are compared with those obtained by FMEA technique. The application of the concepts presented in this paper are illustrated and analyzed for IEEE-Roy Billinton Test System (RBTS). <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=distribution%20system" title="distribution system">distribution system</a>, <a href="https://publications.waset.org/abstracts/search?q=Markov%20Model" title=" Markov Model"> Markov Model</a>, <a href="https://publications.waset.org/abstracts/search?q=reliability%20indices" title=" reliability indices"> reliability indices</a>, <a href="https://publications.waset.org/abstracts/search?q=spice%20simulation" title=" spice simulation "> spice simulation </a> </p> <a href="https://publications.waset.org/abstracts/2903/spice-modeling-for-evaluation-of-distribution-system-reliability-indices" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/2903.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">539</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">292</span> Design and Characterization of CMOS Readout Circuit for ISFET and ISE Based Sensors</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yuzman%20Yusoff">Yuzman Yusoff</a>, <a href="https://publications.waset.org/abstracts/search?q=Siti%20Noor%20Harun"> Siti Noor Harun</a>, <a href="https://publications.waset.org/abstracts/search?q=Noor%20Shelida%20Salleh"> Noor Shelida Salleh</a>, <a href="https://publications.waset.org/abstracts/search?q=Tan%20Kong%20Yew"> Tan Kong Yew</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=readout%20interface%20circuit%20%28ROIC%29" title="readout interface circuit (ROIC)">readout interface circuit (ROIC)</a>, <a href="https://publications.waset.org/abstracts/search?q=analog%20interface%20circuit" title=" analog interface circuit"> analog interface circuit</a>, <a href="https://publications.waset.org/abstracts/search?q=ion%20sensitive%20field%20effect%20transistor%20%28ISFET%29" title=" ion sensitive field effect transistor (ISFET)"> ion sensitive field effect transistor (ISFET)</a>, <a href="https://publications.waset.org/abstracts/search?q=ion%20selective%20electrode%20%28ISE%29" title=" ion selective electrode (ISE)"> ion selective electrode (ISE)</a>, <a href="https://publications.waset.org/abstracts/search?q=ion%20sensor%20electronics" title=" ion sensor electronics"> ion sensor electronics</a> </p> <a href="https://publications.waset.org/abstracts/1577/design-and-characterization-of-cmos-readout-circuit-for-isfet-and-ise-based-sensors" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/1577.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">314</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">291</span> An Appraisal of Grade 12 Educators’ Difficulties in Understanding Electric Circuits in South Africa: A Case Study of Umgungundlovu District of Kwazulu-Natal</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Akinrogunde%20Omolere%20Moses">Akinrogunde Omolere Moses</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A plethora of studies indicated that teaching and learning of the physical sciences in the Further Education and Training (FET) Phase (Grades 10–12) have long been declared problematic in South Africa. For instance, the results from the National Senior Certificate Matric Examination in Physical Sciences, especially in the questions related to practical skills, more specifically, electric circuits, have been unsatisfactory in the past decades. Learner difficulties in understanding electric circuits are well stated. Thus, this study appraised the difficulties Grade 12 Educators often face in understanding Electric Circuits in Umgungundlovu, District of Kwazulu-Natal, South Africa. A mixed-methods research methodology was employed, while a total of 30 schools were sampled, including Ex-Model C, Independent Exam Board, community, rural, and deep rural schools. Data were collected through semi-structured questionnaires. The findings revealed that a large percentage of the Grade 12 physical sciences educators have difficulties with the Grade 9 and 12 physical sciences content. It was also observed that most of the educators who had difficulties were unable to detect the type of difficulties learners would experience; as a result, they were unable to explain why learners experience such difficulties. The results also showed that only those educators with more experience in teaching the physical sciences were able to provide clearer explanations of both the why and how of dealing with learner difficulties with this section on electric circuits. The study recommended that there is a need to recruit more qualified educators, with at least a Bachelor of Science in Physics in particular, in order to combat the misconceptions. Also, Educators with an inadequate understanding of physical sciences should be orientated in order to meet the standard of classroom practice. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=grade%2012%20educators%27%20difficulties" title="grade 12 educators' difficulties">grade 12 educators' difficulties</a>, <a href="https://publications.waset.org/abstracts/search?q=electric%20circuits" title=" electric circuits"> electric circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=learners%27%20difficulties" title=" learners' difficulties"> learners' difficulties</a>, <a href="https://publications.waset.org/abstracts/search?q=educators%20understanding%20of%20EC." title=" educators understanding of EC."> educators understanding of EC.</a> </p> <a href="https://publications.waset.org/abstracts/189606/an-appraisal-of-grade-12-educators-difficulties-in-understanding-electric-circuits-in-south-africa-a-case-study-of-umgungundlovu-district-of-kwazulu-natal" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/189606.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">33</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">290</span> Deep Reinforcement Learning Model Using Parameterised Quantum Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Lokes%20Parvatha%20Kumaran%20S.">Lokes Parvatha Kumaran S.</a>, <a href="https://publications.waset.org/abstracts/search?q=Sakthi%20Jay%20Mahenthar%20C."> Sakthi Jay Mahenthar C.</a>, <a href="https://publications.waset.org/abstracts/search?q=Sathyaprakash%20P."> Sathyaprakash P.</a>, <a href="https://publications.waset.org/abstracts/search?q=Jayakumar%20V."> Jayakumar V.</a>, <a href="https://publications.waset.org/abstracts/search?q=Shobanadevi%20A."> Shobanadevi A.</a> </p> <p class="card-text"><strong>Abstract:</strong></p> With the evolution of technology, the need to solve complex computational problems like machine learning and deep learning has shot up. But even the most powerful classical supercomputers find it difficult to execute these tasks. With the recent development of quantum computing, researchers and tech-giants strive for new quantum circuits for machine learning tasks, as present works on Quantum Machine Learning (QML) ensure less memory consumption and reduced model parameters. But it is strenuous to simulate classical deep learning models on existing quantum computing platforms due to the inflexibility of deep quantum circuits. As a consequence, it is essential to design viable quantum algorithms for QML for noisy intermediate-scale quantum (NISQ) devices. The proposed work aims to explore Variational Quantum Circuits (VQC) for Deep Reinforcement Learning by remodeling the experience replay and target network into a representation of VQC. In addition, to reduce the number of model parameters, quantum information encoding schemes are used to achieve better results than the classical neural networks. VQCs are employed to approximate the deep Q-value function for decision-making and policy-selection reinforcement learning with experience replay and the target network. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=quantum%20computing" title="quantum computing">quantum computing</a>, <a href="https://publications.waset.org/abstracts/search?q=quantum%20machine%20learning" title=" quantum machine learning"> quantum machine learning</a>, <a href="https://publications.waset.org/abstracts/search?q=variational%20quantum%20circuit" title=" variational quantum circuit"> variational quantum circuit</a>, <a href="https://publications.waset.org/abstracts/search?q=deep%20reinforcement%20learning" title=" deep reinforcement learning"> deep reinforcement learning</a>, <a href="https://publications.waset.org/abstracts/search?q=quantum%20information%20encoding%20scheme" title=" quantum information encoding scheme"> quantum information encoding scheme</a> </p> <a href="https://publications.waset.org/abstracts/152629/deep-reinforcement-learning-model-using-parameterised-quantum-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/152629.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">134</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">289</span> Pushing the Boundary of Parallel Tractability for Ontology Materialization via Boolean Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Zhangquan%20Zhou">Zhangquan Zhou</a>, <a href="https://publications.waset.org/abstracts/search?q=Guilin%20Qi"> Guilin Qi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Materialization is an important reasoning service for applications built on the Web Ontology Language (OWL). To make materialization efficient in practice, current research focuses on deciding tractability of an ontology language and designing parallel reasoning algorithms. However, some well-known large-scale ontologies, such as YAGO, have been shown to have good performance for parallel reasoning, but they are expressed in ontology languages that are not parallelly tractable, i.e., the reasoning is inherently sequential in the worst case. This motivates us to study the problem of parallel tractability of ontology materialization from a theoretical perspective. That is we aim to identify the ontologies for which materialization is parallelly tractable, i.e., in the NC complexity. Since the NC complexity is defined based on Boolean circuit that is widely used to investigate parallel computing problems, we first transform the problem of materialization to evaluation of Boolean circuits, and then study the problem of parallel tractability based on circuits. In this work, we focus on datalog rewritable ontology languages. We use Boolean circuits to identify two classes of datalog rewritable ontologies (called parallelly tractable classes) such that materialization over them is parallelly tractable. We further investigate the parallel tractability of materialization of a datalog rewritable OWL fragment DHL (Description Horn Logic). Based on the above results, we analyze real-world datasets and show that many ontologies expressed in DHL belong to the parallelly tractable classes. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=ontology%20materialization" title="ontology materialization">ontology materialization</a>, <a href="https://publications.waset.org/abstracts/search?q=parallel%20reasoning" title=" parallel reasoning"> parallel reasoning</a>, <a href="https://publications.waset.org/abstracts/search?q=datalog" title=" datalog"> datalog</a>, <a href="https://publications.waset.org/abstracts/search?q=Boolean%20circuit" title=" Boolean circuit"> Boolean circuit</a> </p> <a href="https://publications.waset.org/abstracts/57402/pushing-the-boundary-of-parallel-tractability-for-ontology-materialization-via-boolean-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/57402.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">271</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">288</span> Analysis of Lightweight Register Hardware Threat</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yang%20Luo">Yang Luo</a>, <a href="https://publications.waset.org/abstracts/search?q=Beibei%20Wang"> Beibei Wang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=side-channel%20analysis" title="side-channel analysis">side-channel analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20Trojan" title=" hardware Trojan"> hardware Trojan</a>, <a href="https://publications.waset.org/abstracts/search?q=register%20transfer%20level" title=" register transfer level"> register transfer level</a>, <a href="https://publications.waset.org/abstracts/search?q=dynamic%20power" title=" dynamic power"> dynamic power</a> </p> <a href="https://publications.waset.org/abstracts/58138/analysis-of-lightweight-register-hardware-threat" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/58138.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">279</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">287</span> Experimental Partial Discharge Localization for Internal Short Circuits of Transformers Windings </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jalal%20M.%20Abdallah">Jalal M. Abdallah </a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents experimental studies carried out on a three phase transformer to investigate and develop the transformer models, which help in testing procedures, describing and evaluating the transformer dielectric conditions process and methods such as: the partial discharge (PD) localization in windings. The measurements are based on the transfer function methods in transformer windings by frequency response analysis (FRA). Numbers of tests conditions were applied to obtain the sensitivity frequency responses of a transformer for different type of faults simulated in a particular phase. The frequency responses were analyzed for the sensitivity of different test conditions to detect and identify the starting of small faults, which are sources of PD. In more detail, the aim is to explain applicability and sensitivity of advanced PD measurements for small short circuits and its localization. The experimental results presented in the paper will help in understanding the sensitivity of FRA measurements in detecting various types of internal winding short circuits in the transformer. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=frequency%20response%20analysis%20%28FRA%29" title="frequency response analysis (FRA)">frequency response analysis (FRA)</a>, <a href="https://publications.waset.org/abstracts/search?q=measurements" title=" measurements"> measurements</a>, <a href="https://publications.waset.org/abstracts/search?q=transfer%20function" title=" transfer function"> transfer function</a>, <a href="https://publications.waset.org/abstracts/search?q=transformer" title=" transformer"> transformer</a> </p> <a href="https://publications.waset.org/abstracts/7119/experimental-partial-discharge-localization-for-internal-short-circuits-of-transformers-windings" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/7119.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">281</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">286</span> A Machine Learning Approach for Detecting and Locating Hardware Trojans</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Kaiwen%20Zheng">Kaiwen Zheng</a>, <a href="https://publications.waset.org/abstracts/search?q=Wanting%20Zhou"> Wanting Zhou</a>, <a href="https://publications.waset.org/abstracts/search?q=Nan%20Tang"> Nan Tang</a>, <a href="https://publications.waset.org/abstracts/search?q=Lei%20Li"> Lei Li</a>, <a href="https://publications.waset.org/abstracts/search?q=Yuanhang%20He"> Yuanhang He</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The integrated circuit industry has become a cornerstone of the information society, finding widespread application in areas such as industry, communication, medicine, and aerospace. However, with the increasing complexity of integrated circuits, Hardware Trojans (HTs) implanted by attackers have become a significant threat to their security. In this paper, we proposed a hardware trojan detection method for large-scale circuits. As HTs introduce physical characteristic changes such as structure, area, and power consumption as additional redundant circuits, we proposed a machine-learning-based hardware trojan detection method based on the physical characteristics of gate-level netlists. This method transforms the hardware trojan detection problem into a machine-learning binary classification problem based on physical characteristics, greatly improving detection speed. To address the problem of imbalanced data, where the number of pure circuit samples is far less than that of HTs circuit samples, we used the SMOTETomek algorithm to expand the dataset and further improve the performance of the classifier. We used three machine learning algorithms, K-Nearest Neighbors, Random Forest, and Support Vector Machine, to train and validate benchmark circuits on Trust-Hub, and all achieved good results. In our case studies based on AES encryption circuits provided by trust-hub, the test results showed the effectiveness of the proposed method. To further validate the method’s effectiveness for detecting variant HTs, we designed variant HTs using open-source HTs. The proposed method can guarantee robust detection accuracy in the millisecond level detection time for IC, and FPGA design flows and has good detection performance for library variant HTs. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=hardware%20trojans" title="hardware trojans">hardware trojans</a>, <a href="https://publications.waset.org/abstracts/search?q=physical%20properties" title=" physical properties"> physical properties</a>, <a href="https://publications.waset.org/abstracts/search?q=machine%20learning" title=" machine learning"> machine learning</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20security" title=" hardware security"> hardware security</a> </p> <a href="https://publications.waset.org/abstracts/164285/a-machine-learning-approach-for-detecting-and-locating-hardware-trojans" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/164285.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">147</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">285</span> Time Parameter Based for the Detection of Catastrophic Faults in Analog Circuits </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Arabi%20Abderrazak">Arabi Abderrazak</a>, <a href="https://publications.waset.org/abstracts/search?q=Bourouba%20Nacerdine"> Bourouba Nacerdine</a>, <a href="https://publications.waset.org/abstracts/search?q=Ayad%20Mouloud"> Ayad Mouloud</a>, <a href="https://publications.waset.org/abstracts/search?q=Belaout%20Abdeslam"> Belaout Abdeslam</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, a new test technique of analog circuits using time mode simulation is proposed for the single catastrophic faults detection in analog circuits. This test process is performed to overcome the problem of catastrophic faults being escaped in a DC mode test applied to the inverter amplifier in previous research works. The circuit under test is a second-order low pass filter constructed around this type of amplifier but performing a function that differs from that of the previous test. The test approach performed in this work is based on two key- elements where the first one concerns the unique square pulse signal selected as an input vector test signal to stimulate the fault effect at the circuit output response. The second element is the filter response conversion to a square pulses sequence obtained from an analog comparator. This signal conversion is achieved through a fixed reference threshold voltage of this comparison circuit. The measurement of the three first response signal pulses durations is regarded as fault effect detection parameter on one hand, and as a fault signature helping to hence fully establish an analog circuit fault diagnosis on another hand. The results obtained so far are very promising since the approach has lifted up the fault coverage ratio in both modes to over 90% and has revealed the harmful side of faults that has been masked in a DC mode test. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=analog%20circuits" title="analog circuits">analog circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=analog%20faults%20diagnosis" title=" analog faults diagnosis"> analog faults diagnosis</a>, <a href="https://publications.waset.org/abstracts/search?q=catastrophic%20faults" title=" catastrophic faults"> catastrophic faults</a>, <a href="https://publications.waset.org/abstracts/search?q=fault%20detection" title=" fault detection"> fault detection</a> </p> <a href="https://publications.waset.org/abstracts/38309/time-parameter-based-for-the-detection-of-catastrophic-faults-in-analog-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/38309.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">442</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">284</span> Influence of Temperature on Properties of MOSFETs</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Azizi%20Cherifa">Azizi Cherifa</a>, <a href="https://publications.waset.org/abstracts/search?q=O.%20Benzaoui"> O. Benzaoui </a> </p> <p class="card-text"><strong>Abstract:</strong></p> The thermal aspects in the design of power circuits often deserve as much attention as pure electric components aspects as the operating temperature has a direct influence on their static and dynamic characteristics. MOSFET is fundamental in the circuits, it is the most widely used device in the current production of semiconductor components using their honorable performance. The aim of this contribution is devoted to the effect of the temperature on the properties of MOSFETs. The study enables us to calculate the drain current as function of bias in both linear and saturated modes. The effect of temperature is evaluated using a numerical simulation, using the laws of mobility and saturation velocity of carriers as a function of temperature. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=temperature" title="temperature">temperature</a>, <a href="https://publications.waset.org/abstracts/search?q=MOSFET" title=" MOSFET"> MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=mobility" title=" mobility"> mobility</a>, <a href="https://publications.waset.org/abstracts/search?q=transistor" title=" transistor"> transistor</a> </p> <a href="https://publications.waset.org/abstracts/42385/influence-of-temperature-on-properties-of-mosfets" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/42385.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">346</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">283</span> High Frequency Memristor-Based BFSK and 8QAM Demodulators</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nahla%20Elazab">Nahla Elazab</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohamed%20Aboudina"> Mohamed Aboudina</a>, <a href="https://publications.waset.org/abstracts/search?q=Ghada%20Ibrahim"> Ghada Ibrahim</a>, <a href="https://publications.waset.org/abstracts/search?q=Hossam%20Fahmy"> Hossam Fahmy</a>, <a href="https://publications.waset.org/abstracts/search?q=Ahmed%20Khalil"> Ahmed Khalil</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents the developed memristor based demodulators for eight circular Quadrature Amplitude Modulation (QAM) and Binary Frequency Shift Keying (BFSK) operating at relatively high frequency. In our implementations, the experimental-based ‘nonlinear’ dopant drift model is adopted along with the proposed circuits providing incorporation of all known non-idealities of practically realized memristor and gaining high operation frequency. The suggested designs leverage the distinctive characteristics of the memristor device, definitely, its changeable average memristance versus the frequency, phase and amplitude of the periodic excitation input. The proposed demodulators feature small integration area, low power consumption, and easy implementation. Moreover, the proposed QAM demodulator precludes the requirement for the carrier recovery circuits. In doing so, the designs were validated by transient simulations using the nonlinear dopant drift memristor model. The simulations results show high agreement with the theory presented. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=BFSK" title="BFSK">BFSK</a>, <a href="https://publications.waset.org/abstracts/search?q=demodulator" title=" demodulator"> demodulator</a>, <a href="https://publications.waset.org/abstracts/search?q=high%20frequency%20memristor%20applications" title=" high frequency memristor applications"> high frequency memristor applications</a>, <a href="https://publications.waset.org/abstracts/search?q=memristor%20based%20analog%20circuits" title=" memristor based analog circuits"> memristor based analog circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=nonlinear%20dopant%20drift%20model" title=" nonlinear dopant drift model"> nonlinear dopant drift model</a>, <a href="https://publications.waset.org/abstracts/search?q=QAM" title=" QAM"> QAM</a> </p> <a href="https://publications.waset.org/abstracts/125099/high-frequency-memristor-based-bfsk-and-8qam-demodulators" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/125099.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">167</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">282</span> Design and Simulation of Coupled-Line Coupler with Different Values of Coupling Efficiency</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Suleiman%20Babani">Suleiman Babani</a>, <a href="https://publications.waset.org/abstracts/search?q=Jazuli%20Sanusi%20Kazaure"> Jazuli Sanusi Kazaure</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, two coupled-line couplers are designed and simulated using stripline technology. The coupled-line couplers (A and B) are designed with different values of coupling coefficient 6dB and 10dB respectively. Both of circuits have a coupled output port, a through output port and an isolated output port. Moreover, both circuits are tuned to function around 2.45 GHz. The design results are presented by simulation results obtained using ADS 2012.08 (Advanced Design System) software. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=ADS" title="ADS">ADS</a>, <a href="https://publications.waset.org/abstracts/search?q=coupled-line%20coupler" title=" coupled-line coupler"> coupled-line coupler</a>, <a href="https://publications.waset.org/abstracts/search?q=directional%20coupler" title=" directional coupler"> directional coupler</a>, <a href="https://publications.waset.org/abstracts/search?q=stripline" title=" stripline"> stripline</a> </p> <a href="https://publications.waset.org/abstracts/28524/design-and-simulation-of-coupled-line-coupler-with-different-values-of-coupling-efficiency" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/28524.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">512</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">281</span> Optimizing Power in Sequential Circuits by Reducing Leakage Current Using Enhanced Multi Threshold CMOS </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Patikineti%20Sreenivasulu">Patikineti Sreenivasulu</a>, <a href="https://publications.waset.org/abstracts/search?q=K.%20srinivasa%20Rao"> K. srinivasa Rao</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Vinaya%20Babu"> A. Vinaya Babu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The demand for portability, performance and high functional integration density of digital devices leads to the scaling of complementary metal oxide semiconductor (CMOS) devices inevitable. The increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. MTCMOS technology provides low leakage and high performance operation by utilizing high speed, low Vt (LVT) transistors for logic cells and low leakage, high Vt (HVT) devices as sleep transistors. Sleep transistors disconnect logic cells from the supply and/or ground to reduce the leakage in the sleep mode. In this technology, energy consumption while doing the mode transition and minimum time required to turn ON the circuit upon receiving the wake up signal are issues to be considered because these can adversely impact the performance of VLSI circuit. In this paper we are introducing an enhancing method of MTCMOS technology to optimize the power in MTCMOS sequential circuits. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=power%20consumption" title="power consumption">power consumption</a>, <a href="https://publications.waset.org/abstracts/search?q=ultra-low%20power" title=" ultra-low power"> ultra-low power</a>, <a href="https://publications.waset.org/abstracts/search?q=leakage" title=" leakage"> leakage</a>, <a href="https://publications.waset.org/abstracts/search?q=sub%20threshold" title=" sub threshold"> sub threshold</a>, <a href="https://publications.waset.org/abstracts/search?q=MTCMOS" title=" MTCMOS"> MTCMOS</a> </p> <a href="https://publications.waset.org/abstracts/35180/optimizing-power-in-sequential-circuits-by-reducing-leakage-current-using-enhanced-multi-threshold-cmos" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/35180.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">407</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">280</span> Analysis of Silicon Controlled Rectifier-Based Electrostatic Discharge Protection Circuits with Electrical Characteristics for the 5V Power Clamp</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jun-Geol%20Park">Jun-Geol Park</a>, <a href="https://publications.waset.org/abstracts/search?q=Kyoung-Il%20Do"> Kyoung-Il Do</a>, <a href="https://publications.waset.org/abstracts/search?q=Min-Ju%20Kwon"> Min-Ju Kwon</a>, <a href="https://publications.waset.org/abstracts/search?q=Kyung-Hyun%20Park"> Kyung-Hyun Park</a>, <a href="https://publications.waset.org/abstracts/search?q=Yong-Seo%20Koo"> Yong-Seo Koo</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper analyzed the SCR (Silicon Controlled Rectifier)-based ESD (Electrostatic Discharge) protection circuits with the turn-on time characteristics. The structures are the LVTSCR (Low Voltage Triggered SCR), the ZTSCR (Zener Triggered SCR) and the PTSCR (P-Substrate Triggered SCR). The three structures are for the 5V power clamp. In general, the structures with the low trigger voltage structure can have the fast turn-on characteristics than other structures. All the ESD protection circuits have the low trigger voltage by using the N+ bridge region of LVTSCR, by using the zener diode structure of ZTSCR, by increasing the trigger current of PTSCR. The simulation for the comparison with the turn-on time was conducted by the Synopsys TCAD simulator. As the simulation results, the LVTSCR has the turn-on time of 2.8 ns, ZTSCR of 2.1 ns and the PTSCR of 2.4 ns. The HBM simulation results, however, show that the PTSCR is the more robust structure of 430K in HBM 8kV standard than 450K of LVTSCR and 495K of ZTSCR. Therefore the PTSCR is the most effective ESD protection circuit for the 5V power clamp. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=ESD" title="ESD">ESD</a>, <a href="https://publications.waset.org/abstracts/search?q=SCR" title=" SCR"> SCR</a>, <a href="https://publications.waset.org/abstracts/search?q=turn-on%20time" title=" turn-on time"> turn-on time</a>, <a href="https://publications.waset.org/abstracts/search?q=trigger%20voltage" title=" trigger voltage"> trigger voltage</a>, <a href="https://publications.waset.org/abstracts/search?q=power%20clamp" title=" power clamp"> power clamp</a> </p> <a href="https://publications.waset.org/abstracts/65650/analysis-of-silicon-controlled-rectifier-based-electrostatic-discharge-protection-circuits-with-electrical-characteristics-for-the-5v-power-clamp" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/65650.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">348</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">279</span> A Development of Portable Intrinsically Safe Explosion-Proof Type of Dual Gas Detector</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Sangguk%20Ahn">Sangguk Ahn</a>, <a href="https://publications.waset.org/abstracts/search?q=Youngyu%20Kim"> Youngyu Kim</a>, <a href="https://publications.waset.org/abstracts/search?q=Jaheon%20Gu"> Jaheon Gu</a>, <a href="https://publications.waset.org/abstracts/search?q=Gyoutae%20Park"> Gyoutae Park</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, we developed a dual gas leak instrument to detect Hydrocarbon (HC) and Monoxide (CO) gases. To two kinds of gases, it is necessary to design compact structure for sensors. And then it is important to draw sensing circuits such as measuring, amplifying and filtering. After that, it should be well programmed with robust, systematic and module coding methods. In center of them, improvement of accuracy and initial response time are a matter of vital importance. To manufacture distinguished gas leak detector, we applied intrinsically safe explosion-proof structure to lithium ion battery, main circuits, a pump with motor, color LCD interfaces and sensing circuits. On software, to enhance measuring accuracy we used numerical analysis such as Lagrange and Neville interpolation. Performance test result is conducted by using standard Methane with seven different concentrations with three other products. We want raise risk prevention and efficiency of gas safe management through distributing to the field of gas safety. Acknowledgment: This study was supported by Small and Medium Business Administration under the research theme of ‘Commercialized Development of a portable intrinsically safe explosion-proof type dual gas leak detector’, (task number S2456036). <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=gas%20leak" title="gas leak">gas leak</a>, <a href="https://publications.waset.org/abstracts/search?q=dual%20gas%20detector" title=" dual gas detector"> dual gas detector</a>, <a href="https://publications.waset.org/abstracts/search?q=intrinsically%20safe" title=" intrinsically safe"> intrinsically safe</a>, <a href="https://publications.waset.org/abstracts/search?q=explosion%20proof" title=" explosion proof"> explosion proof</a> </p> <a href="https://publications.waset.org/abstracts/69836/a-development-of-portable-intrinsically-safe-explosion-proof-type-of-dual-gas-detector" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/69836.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">228</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">278</span> Design and Study of a Low Power High Speed Full Adder Using GDI Multiplexer</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Biswarup%20Mukherjee">Biswarup Mukherjee</a>, <a href="https://publications.waset.org/abstracts/search?q=Aniruddha%20Ghosal"> Aniruddha Ghosal</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, we propose a new technique for implementing a low power full adder using a set of GDI multiplexers. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have low power operation for the sub components. The explored method of implementation achieves a low power design for the full adder. Simulated results using state-of-art Tanner tool indicates the superior performance of the proposed technique over conventional CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=low%20power%20full%20adder" title="low power full adder">low power full adder</a>, <a href="https://publications.waset.org/abstracts/search?q=2-T%20GDI%20MUX" title=" 2-T GDI MUX"> 2-T GDI MUX</a>, <a href="https://publications.waset.org/abstracts/search?q=ASIC%0D%0A%28application%20specific%20integrated%20circuit%29" title=" ASIC (application specific integrated circuit)"> ASIC (application specific integrated circuit)</a>, <a href="https://publications.waset.org/abstracts/search?q=12-T%20FA" title=" 12-T FA"> 12-T FA</a>, <a href="https://publications.waset.org/abstracts/search?q=CMOS%20%28complementary%20metal%20oxide%20semiconductor%29" title=" CMOS (complementary metal oxide semiconductor)"> CMOS (complementary metal oxide semiconductor)</a> </p> <a href="https://publications.waset.org/abstracts/21647/design-and-study-of-a-low-power-high-speed-full-adder-using-gdi-multiplexer" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/21647.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">348</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">277</span> Design Dual Band Band-Pass Filter by Using Stepped Impedance</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Fawzia%20Al-Sakeer">Fawzia Al-Sakeer</a>, <a href="https://publications.waset.org/abstracts/search?q=Hassan%20Aldeeb"> Hassan Aldeeb</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Development in the communications field is proceeding at an amazing speed, which has led researchers to improve and develop electronic circuits by increasing their efficiency and reducing their size to reduce the weight of electronic devices. One of the most important of these circuits is the band-pass filter, which is what made us carry out this research, which aims to use an alternate technology to design a dual band-pass filter by using a stepped impedance microstrip transmission line. We designed a filter that works at two center frequency bands by designing with the ADS program, and the results were excellent, as we obtained the two design frequencies, which are 1 and 3GHz, and the values of insertion loss S11, which was more than 21dB with a small area. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=band%20pass%20filter" title="band pass filter">band pass filter</a>, <a href="https://publications.waset.org/abstracts/search?q=dual%20band%20band-pass%20filter" title=" dual band band-pass filter"> dual band band-pass filter</a>, <a href="https://publications.waset.org/abstracts/search?q=ADS" title=" ADS"> ADS</a>, <a href="https://publications.waset.org/abstracts/search?q=microstrip%20filter" title=" microstrip filter"> microstrip filter</a>, <a href="https://publications.waset.org/abstracts/search?q=stepped%20impedance" title=" stepped impedance"> stepped impedance</a> </p> <a href="https://publications.waset.org/abstracts/177757/design-dual-band-band-pass-filter-by-using-stepped-impedance" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/177757.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">69</span> </span> </div> </div> <ul class="pagination"> <li class="page-item disabled"><span class="page-link">&lsaquo;</span></li> <li class="page-item active"><span class="page-link">1</span></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=circuits&page=2">2</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=circuits&page=3">3</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=circuits&page=4">4</a></li> <li class="page-item"><a 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