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style="-webkit-line-clamp:0" tabindex="0">972 views</span></div><div class="author Author_root___6Bx5"><a data-cy="author-link" class="Author_link___lVxw ellipsis" title="AdrianOShaughnessy" href="https://www.slideshare.net/AdrianOShaughnessy"><div class="Avatar_root__GNWHY Avatar_initials__EJfVt" style="width:24px;height:24px;line-height:24px">A</div><span>AdrianOShaughnessy</span></a></div><div class="description Description_root__kt4uq Description_clamped__PaV_1"><div class="Description_wrapper__hYE9_" data-cy="document-description"><p>The document discusses layout challenges at the 90nm technology node. It covers analog layout challenges including shallow trench isolation (STI) stress and well proximity effects that can degrade transistor performance. For RF layout, it discusses the importance of minimizing interconnect and device parasitics. Interconnect parasitics like resistance and capacitance can be reduced by shorter lengths, wider widths, and using higher metal layers. Device parasitics are also discussed and how optimizing the drain area of differential pairs by folding can help minimize parasitic capacitance effects.<button type="button" class="Button_root__i1yp0 Button_primary__K25Gq Button_text__ZT_3O Button_small__sqsEx Description_less__BvWbY Description_hidden__a9QZJ" data-testid="button" aria-label="Read less"><span>Read less</span></button></p></div><button type="button" class="Button_root__i1yp0 Button_primary__K25Gq Button_text__ZT_3O Button_small__sqsEx Description_more__ChrRK" data-testid="button" aria-label="Read more" data-cy="read-more-button"><span>Read more</span></button></div></div><div class="MetadataToolbar_root__c03ao metadata-toolbar" data-cy="slideshow-toolbar"><div class="MetadataToolbar_wrapper__r7XEc"><div class="actions Actions_root__00yIC"><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_regular__i28NX Button_icon__1C4qi like-button unliked" data-testid="button" aria-label="Like" data-favorited="false" data-cy="like-button" aria-haspopup="dialog" aria-controls=":R2654f6:" popovertarget=":R2654f6:" style="anchor-name:--popover-R2654f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/like.3870b074.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R2654f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R2654f6"></div><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_regular__i28NX Button_icon__1C4qi save-slideshow-button SaveToListButton_root__T0ltL" data-testid="button" aria-label="Save for later" data-cy="save-slideshow-logged-out-button" aria-haspopup="dialog" aria-controls=":R3654f6:" popovertarget=":R3654f6:" style="anchor-name:--popover-R3654f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R3654f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R3654f6"></div><button type="button" class="unstyled-button more-button MoreDropdownButton_trigger__x7wGs" aria-label="More options" data-cy="more-options-icon" data-testid="ellipsis" aria-haspopup="dialog" aria-controls=":Rc654f6:" popovertarget=":Rc654f6:" style="anchor-name:--popover-Rc654f6"><span class="icon Icon_root__AjZyv" style="anchor-name:--popover-R3c654f6" aria-haspopup="dialog" aria-controls=":R3c654f6:" popovertarget=":R3c654f6:"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/more-horizontal.f69be1b8.svg);background-color:currentColor"></span><span class="sr-only"></span></span><div class="Tooltip_root__7FS0Y" id=":R3c654f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R3c654f6"></div></button><div class="" id=":Rc654f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rc654f6"></div></div><span data-cy="page-number" class="MetadataToolbar_pageNumber__i6Bhj">1 of 5</span><div class="MetadataToolbar_actions__FB33C"><div class="DownloadButton_root__adY00"><button type="button" class="Button_root__i1yp0 Button_primary__K25Gq Button_contained__gyjai Button_large__Yv_oe" data-testid="download-button" data-cy="download-button-toolbar"><span><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/download.b1b2622c.svg);background-color:currentColor"></span><span class="sr-only"></span></span>Download now</span></button><span class="Text_root__is73U Text_secondary__EPWj0 Text_xsmall__vYp9p text" style="-webkit-line-clamp:0">Downloaded 24 times</span></div></div><div class="MetadataToolbar_underline__QQn0C"></div></div></div><div class="player Player_root__L1AmF"><div id="new-player" class="vertical-player VerticalPlayer_root__K8_YS" data-slideshow-id="5443659"><div><div id="slide1" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:595 / 842" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-0" alt="NMI Presentation Notes 12th September 2007 IC Mask Design Limited Unit 12G Maynooth Business Campus Maynooth, Co. Kildare, Ireland. Topics: 1. Analog Layout at 90 nanometer 2. RF Layout at 90 nanometer Analog Layout at 90 nanometer There are various challages in Analog layout at 90 nanometer.The topics for discussion are:  Shallow Trench Isolation Stress (STI)  Well Proximity Effect (WPE) RF Layout at 90 nanometer As frequencies increase, with some CMOS circuits operating in the RF range, layout quality has a larger influence on circuit perfomance. The topics for discussion are:  Interconnect  Interconnect Parasitics  Device Parasitics  Understanding and optimising device parasitics ICMaskDesign Adrian O'Shaughnessy " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="eager" srcSet="https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-1-320.jpg 320w, https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-1-638.jpg 638w, https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/75/Nmi-Presentation-Sept-2007-1-2048.jpg 2048w" src="https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-1-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide2" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:595 / 842" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-1" alt="STI So what exactly is it? STI is a technique to electrically isolate mos transistors from each other. LOCUS (local oxidation of silicon) was the technique used previous to this. Basically this involved growing a thick pad of oxide between adjacent devices. The problem with it really was scalability. As geometries were getting smaller it wasn't really an option, so Shallow Trench Isolation was introduced. This involved etching out a shallow trench into the substrate between devices and then filling with an oxide. So why is it so important that we understand it? Basically if STI isn't taking into account it can lead to circuit failure. So the designer has to be aware of it and most importantly the layout engineer has to understand and know how to deal with it. So what problems does it introduce? The STI process stresses the mos transistors which can lead to a degradation or variation in performance. So this can affect things like matching. If your current mirror is experiencing a variation across it's transistors then they won't be matched and offsets could be introduced. Worse still will be that the current output will be much less than expected so things like biasing currents could be affected. So how does it stress the mos transistors? First of all when the trench is etched into the substrate this will cause some mechanical stress. In other words the silicon itself will experience stress and the degree of stress that the transistor experiences is related to the distance of the gate to the closest STI region, that is the distance of the channel to the closest oxide. So how can we as layout engineers fix it? 1. Well we could match it. If for example in a current mirror we ensure that each transistor experiences the same STI stress then they are matched. The problem with this though is the designer has to be aware that this is the technique that we are using because this technique could result in a degradation in current output and so the designer has to allow for this in their simulations. 2. Another technique is to share regions. Here we have utilised area and we have eliminated the STI stress. The important thing to note is we that must extend the poly to active distance on the outer mos transistors. We can do this by simply drawing in the extra diffusion area or by adding in dummy devices ICMaskDesign Adrian O'Shaughnessy " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-2-320.jpg 320w, https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-2-638.jpg 638w, https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/75/Nmi-Presentation-Sept-2007-2-2048.jpg 2048w" src="https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-2-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide3" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:595 / 842" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-2" alt="WPE The Well Proximity Effect is another effect that if not understood has the potential to cause circuit failure. So what is it? Basically this involves the scattering of ions (ion scattering) during the implantation of the wells. So what does this cause? The result is a well surface concentration that changes with lateral distance from the mask edge over the range of 1 micron or more. This later non-uniformity in well doping causes the MOS threshold voltages and other electrical characteristics to vary with the distance of the transistor to the well edge. In some instances Vt has been found to increase by as much as 50mV as the device moves closer to the edge. If this isn't taken into account such things as current mirrors can be shifted out of saturation leading to circuit failure. So how is it fixed? The layout engineer must insure that the mos devices either experience the same WPE effect or must ensure that there is enough of a distance from the well edge so as to negate the effects of WPE. Characterisation tests reveal that 2-5 microns should be sufficient. ICMaskDesign Adrian O'Shaughnessy " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-3-320.jpg 320w, https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-3-638.jpg 638w, https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/75/Nmi-Presentation-Sept-2007-3-2048.jpg 2048w" src="https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-3-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide4" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:595 / 842" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-3" alt="RF Layout at 90 Nanometres INTRO Good layout practice at high frequencies is extremely important because bad layout can and will introduce parasitics that may result in extra current needed to drive these parasitic loads. It could also of course stop your circuit from working at all as it may limit it's frequency response. Interconnect Lets look at the parasitics that's introduced by interconnect. Every single piece of interconnect we put down will have an associated parasitic resistance. This resistance is calculated by multiplying it's sheet resistance by it's length over width – Rs * (L/W) Interconnect will also introduce different types of parasitic capacitance such as parallel plate, Fringe and cross coupling which will all have a combinational affect and create one overall parasitic capacitance. So have can we improve on the parasitic resistance? 1. Reduce Length. If we properly floorplan our blocks it should be possible to minimise the interconnect between them. 2. Increase Width. Increasing the width will reduce the number of squares. It is common for differential signals to be wider than the minimum width. 3. Use Higher Layers. Higher metals have a lower sheet resistance than lower ones therefore reducing its overall resistance. This will also have the added advantage of decreasing the capacitance to substrate. ICMaskDesign Adrian O'Shaughnessy " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-4-320.jpg 320w, https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-4-638.jpg 638w, https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/75/Nmi-Presentation-Sept-2007-4-2048.jpg 2048w" src="https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-4-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide5" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:595 / 842" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-4" alt="Device Parasitics INTRO When we put down a device in layout we introduce parasitics. Simple as that. So what happens when we put down a mos device? Simple MOS Parasitics We introduce a whole host of resistive and capacitive parasitics and as a layout engineer there are some on these parasitics that can be optimised and there's some that can't. Parasitics that we can't optimise are directly related to the length of the device which we can't change. We can optimise the gate resistance by tying both ends of the poly in metal thereby connecting another resistor, in this case metal1, in parallel with in. Connecting the gate in metal will improve the resistance by 200% - 400%. We can improve the drain and source parasitic capacitance by folding the device. But which one do we optimise? This is particularly done on differential pairs. If we optimise the source area then we're optimising a region that is going to ground if it's an NMOS device. Any good? If we optimise the drain area then we're optimising the output node which in RF circuits is highly sensitive to capacitance. So it's best to optimise this. We can also improve the substrate resistance by putting in lots of well contacts. This will help prevent against latch-up and also serve as noise protection. ICMaskDesign Adrian O'Shaughnessy " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-5-320.jpg 320w, https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-5-638.jpg 638w, https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/75/Nmi-Presentation-Sept-2007-5-2048.jpg 2048w" src="https://image.slidesharecdn.com/nmipresentationsept2007-12870663346649-phpapp01/85/Nmi-Presentation-Sept-2007-5-320.jpg" sizes="100vw"/></div></div></div></div></div><div id="sidebar" class="sidebar hide-scrollbar Sidebar_root__1BbNu" style="--slots:2"><div class="above-recs-ad-wrapper AboveRecsAd_root__iTmTR"><div class="AboveRecsAd_desktopAd__ymykj"><div class="freestar-ad-container FreestarAdContainer_root__qPPC_" style="--fallback-aspect-ratio:300 / 260" data-testid="freestar-ad-container"><div><div class="" id="above-recs-desktop-ad-sm"></div></div></div></div></div><div class="rail-recs RailRecommendations_root__zqtZQ"><h2 class="RailRecommendations_title__kt1D2">Recommended</h2><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-0" aria-haspopup="dialog" aria-controls=":Rgql4f6:" popovertarget=":Rgql4f6:" style="anchor-name:--popover-Rgql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/ntn-moat-noiseanalysis/33214012"><span class="sr-only">NT_N Guard Ring Noise Analysis</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:0" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="NT_N Guard Ring Noise Analysis" src="https://cdn.slidesharecdn.com/ss_thumbnails/linkedinmoatnoiseanalysis-signed-140407045535-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="NT_N Guard Ring Noise Analysis" src="https://cdn.slidesharecdn.com/ss_thumbnails/linkedinmoatnoiseanalysis-signed-140407045535-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">NT_N Guard Ring Noise Analysis</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save NT_N Guard Ring Noise Analysis for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mgql4f6:" popovertarget=":R5mgql4f6:" style="anchor-name:--popover-R5mgql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mgql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mgql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/AdrianOShaughnessy">AdrianOShaughnessy</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The purpose of this report is to provide a detailed example and analysis of a N_TN guard ring structure. This scheme could be used to separate the analogue and digital domains on chip, and thus used for noise attenuation and noise collection. Furthermore this report will hypothesis additional noise performance improvements that could be made for added noise isolation. </span></div></div><div class="" id=":Rgql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rgql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-1" aria-haspopup="dialog" aria-controls=":Rhal4f6:" popovertarget=":Rhal4f6:" style="anchor-name:--popover-Rhal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/WPE/912927"><span class="sr-only">WPE</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:1" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="WPE" src="https://cdn.slidesharecdn.com/ss_thumbnails/WPE-123184826661-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="WPE" src="https://cdn.slidesharecdn.com/ss_thumbnails/WPE-123184826661-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">WPE</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save WPE for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mhal4f6:" popovertarget=":R5mhal4f6:" style="anchor-name:--popover-R5mhal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mhal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mhal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/AdrianOShaughnessy">AdrianOShaughnessy</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses the Well Proximity Effect (WPE) where transistors located near the edge of a well will have different thresholds and currents compared to those located remotely from the edge. The WPE effect occurs for all types of MOS transistors including standard, high, low, and thick/thin oxide devices. It provides a diagram from an IC Mask Design course illustrating the WPE effect.</span></div></div><div class="" id=":Rhal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rhal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-2" aria-haspopup="dialog" aria-controls=":Rhql4f6:" popovertarget=":Rhql4f6:" style="anchor-name:--popover-Rhql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/double-patterning-for-32nm-and-beyond/30955526"><span class="sr-only">Double patterning for 32nm and beyond</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:2" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Double patterning for 32nm and beyond" src="https://cdn.slidesharecdn.com/ss_thumbnails/presentationdp-140207121538-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Double patterning for 32nm and beyond" src="https://cdn.slidesharecdn.com/ss_thumbnails/presentationdp-140207121538-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Double patterning for 32nm and beyond</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Double patterning for 32nm and beyond for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mhql4f6:" popovertarget=":R5mhql4f6:" style="anchor-name:--popover-R5mhql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mhql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mhql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ManikandanSampathkum">Manikandan Sampathkumar</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Multiple patterning is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. The simplest case of multiple patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected number of features. The resolution of a photoresist pattern is believed to blur at around 45 nm half-pitch. For the semiconductor industry, therefore, double patterning was introduced for the 32 nm half-pitch node and below. This presentation gives us an insight of why multiple patterning is an important to give us a better resolution below 32nm. </span></div></div><div class="" id=":Rhql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rhql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-3" aria-haspopup="dialog" aria-controls=":Rial4f6:" popovertarget=":Rial4f6:" style="anchor-name:--popover-Rial4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/double-patterning-3621214/3621214"><span class="sr-only">Double Patterning (4/2 update)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:3" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Double Patterning (4/2 update)" src="https://cdn.slidesharecdn.com/ss_thumbnails/3621214-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Double Patterning (4/2 update)" src="https://cdn.slidesharecdn.com/ss_thumbnails/3621214-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Double Patterning (4/2 update)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Double Patterning (4/2 update) for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mial4f6:" popovertarget=":R5mial4f6:" style="anchor-name:--popover-R5mial4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mial4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mial4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/luk036">Danny Luk</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses double patterning lithography techniques. It introduces how optical lithography is approaching its limits and double patterning is needed for smaller feature sizes. It describes the double patterning process and challenges including feature distortion and decreased yield. The document outlines techniques for polygon cutting, priority search trees, and decomposing conflict graphs into tri-connected components to solve the layout splitting problem. Experimental results on test cases including a 320k polygon design show the method achieves 3-10x speedup.</span></div></div><div class="" id=":Rial4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rial4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-4" aria-haspopup="dialog" aria-controls=":Riql4f6:" popovertarget=":Riql4f6:" style="anchor-name:--popover-Riql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/introduction-to-finfet-details-of-finfet/239800902"><span class="sr-only">Introduction to FINFET, Details of FinFET</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:4" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Introduction to FINFET, Details of FinFET" src="https://cdn.slidesharecdn.com/ss_thumbnails/finfetppt-201205162426-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Introduction to FINFET, Details of FinFET" src="https://cdn.slidesharecdn.com/ss_thumbnails/finfetppt-201205162426-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Introduction to FINFET, Details of FinFET</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Introduction to FINFET, Details of FinFET for later" role="switch" aria-haspopup="dialog" aria-controls=":R5miql4f6:" popovertarget=":R5miql4f6:" style="anchor-name:--popover-R5miql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5miql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5miql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/justingeorge55">Justin George</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">1) The document discusses FinFET, a type of non-planar transistor used in modern semiconductor fabrication. It describes the construction of FinFET which involves etching fins on an SOI substrate and wrapping gates around the fins. 2) FinFET works by having an elevated fin-shaped channel that the gate wraps around. This allows FinFET to operate at lower voltage and offer higher drive current compared to planar transistors. 3) FinFET technology is being widely adopted in integrated circuits due to advantages like suppressed short channel effect, better drive current, lower leakage power, and no random dopant fluctuation.</span></div></div><div class="" id=":Riql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Riql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-5" aria-haspopup="dialog" aria-controls=":Rjal4f6:" popovertarget=":Rjal4f6:" style="anchor-name:--popover-Rjal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/optimazation-of-standard-cell-layout-70517450/70517450"><span class="sr-only">optimazation of standard cell layout</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:5" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="optimazation of standard cell layout" src="https://cdn.slidesharecdn.com/ss_thumbnails/8d1d2c82-57db-4662-b92e-d5dbe95d951e-161229063603-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="optimazation of standard cell layout" src="https://cdn.slidesharecdn.com/ss_thumbnails/8d1d2c82-57db-4662-b92e-d5dbe95d951e-161229063603-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">optimazation of standard cell layout</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save optimazation of standard cell layout for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mjal4f6:" popovertarget=":R5mjal4f6:" style="anchor-name:--popover-R5mjal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mjal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mjal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/EERYashnagaria">E ER Yash nagaria</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses various layout optimizations that can be made to standard cells to reduce both internal power and area. These include removing "hammer head" structures to decrease transistor length, moving gate contacts over active areas to reduce transistor height, and reducing source/drain capacitances to decrease dynamic current without impacting speed. Post-layout simulations showed a new D flip-flop design with these optimizations reduced internal power by 20% while maintaining clock-to-Q delay, and improved saturation current by 15-50% while reducing area by 20%.</span></div></div><div class="" id=":Rjal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rjal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-6" aria-haspopup="dialog" aria-controls=":Rjql4f6:" popovertarget=":Rjql4f6:" style="anchor-name:--popover-Rjql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/finfet-47143716/47143716"><span class="sr-only">Finfet</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:6" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Finfet" src="https://cdn.slidesharecdn.com/ss_thumbnails/finfet-150418093709-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Finfet" src="https://cdn.slidesharecdn.com/ss_thumbnails/finfet-150418093709-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Finfet</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Finfet for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mjql4f6:" popovertarget=":R5mjql4f6:" style="anchor-name:--popover-R5mjql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mjql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mjql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/AdityaSingh155">Aditya Singh</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses the history and development of FinFET transistors. FinFETs were developed to overcome short channel effects by using a thin silicon fin as the channel between the source and drain. This allows the gate to control the channel from both sides and edges of the fin. FinFET fabrication involves depositing fins using electron beam lithography then depositing a gate material around the fins. FinFETs suppress short channel effects and allow for higher density transistors compared to planar MOSFETs, though they also have some disadvantages like reduced mobility.</span></div></div><div class="" id=":Rjql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rjql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-7" aria-haspopup="dialog" aria-controls=":Rkal4f6:" popovertarget=":Rkal4f6:" style="anchor-name:--popover-Rkal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/analog-design-cit-f/29991014"><span class="sr-only">Analog Layout design </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:7" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Analog Layout design " src="https://cdn.slidesharecdn.com/ss_thumbnails/analogdesigncitf-140114022933-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Analog Layout design " src="https://cdn.slidesharecdn.com/ss_thumbnails/analogdesigncitf-140114022933-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Analog Layout design </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Analog Layout design for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mkal4f6:" popovertarget=":R5mkal4f6:" style="anchor-name:--popover-R5mkal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mkal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mkal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/slpinjare">slpinjare</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document provides an overview of analog layout design. It discusses that analog circuits require careful attention to geometry during layout due to process variations. The analog design flow includes electrical design, physical design involving layout, and fabrication/testing. Key considerations for analog layout include minimizing parasitic resistances and capacitances, reducing noise, and ensuring matching between identical components using techniques like common-centroid layout. Resistors and capacitors must be carefully laid out to minimize non-ideal effects and provide accurate values.</span></div></div><div class="" id=":Rkal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rkal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-8" aria-haspopup="dialog" aria-controls=":Rkql4f6:" popovertarget=":Rkql4f6:" style="anchor-name:--popover-Rkql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/matching-concept-in-microelectronics/237111064"><span class="sr-only">Matching concept in Microelectronics</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:8" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Matching concept in Microelectronics" src="https://cdn.slidesharecdn.com/ss_thumbnails/microelectronicsmatchingpresentation3matchingied3030harishivem177319-200721134926-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Matching concept in Microelectronics" src="https://cdn.slidesharecdn.com/ss_thumbnails/microelectronicsmatchingpresentation3matchingied3030harishivem177319-200721134926-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Matching concept in Microelectronics</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Matching concept in Microelectronics for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mkql4f6:" popovertarget=":R5mkql4f6:" style="anchor-name:--popover-R5mkql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mkql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mkql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/HarishSingh8">Tallinn University of Technology</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This presentation speaks about type of matching in microelectronics. Dependencies of matching are discussed.</span></div></div><div class="" id=":Rkql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rkql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-9" aria-haspopup="dialog" aria-controls=":Rlal4f6:" popovertarget=":Rlal4f6:" style="anchor-name:--popover-Rlal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/venkat1234_nxp/layout02-1"><span class="sr-only">Layout02 (1)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:9" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Layout02 (1)" src="https://cdn.slidesharecdn.com/ss_thumbnails/layout021-160229081601-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Layout02 (1)" src="https://cdn.slidesharecdn.com/ss_thumbnails/layout021-160229081601-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Layout02 (1)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Layout02 (1) for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mlal4f6:" popovertarget=":R5mlal4f6:" style="anchor-name:--popover-R5mlal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mlal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mlal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/venkat1234_nxp">venkat1234_nxp</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses the layout of analog CMOS integrated circuits. It focuses on the layout of transistors and basic cells. Key topics covered include: - Layout of a single transistor, use of multiple fingers, and interdigitated transistors for matching. - Common centroid layouts and dummy devices to reduce mismatch. - Ensuring matched interconnect resistance, capacitance, and parasitics. - Stacked layout of analog cells with stick diagrams to represent multiple transistors. - Two examples of laying out basic cells - a two-stage op-amp and folded cascode. Design considerations like transistor sizing and grouping are discussed.</span></div></div><div class="" id=":Rlal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rlal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-10" aria-haspopup="dialog" aria-controls=":Rlql4f6:" popovertarget=":Rlql4f6:" style="anchor-name:--popover-Rlql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/latch-up/26735030"><span class="sr-only">Latch up</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:10" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Latch up" src="https://cdn.slidesharecdn.com/ss_thumbnails/latch-up-131001053300-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Latch up" src="https://cdn.slidesharecdn.com/ss_thumbnails/latch-up-131001053300-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Latch up</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Latch up for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mlql4f6:" popovertarget=":R5mlql4f6:" style="anchor-name:--popover-R5mlql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mlql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mlql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ishan111">ishan111</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Latch-up occurs in CMOS chips due to the interaction of parasitic bipolar transistors that form a silicon-controlled rectifier between the power and ground rails. This can cause excessive currents and potentially damage devices. Latch-up can be triggered by disturbances that increase the collector current of one of the parasitic transistors, activating positive feedback between the transistors. Guidelines for preventing latch-up include using guard rings connected to power and ground around transistors to reduce resistance and capture minority carriers, as well as placing wells and substrate contacts close to transistor sources.</span></div></div><div class="" id=":Rlql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rlql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-11" aria-haspopup="dialog" aria-controls=":Rmal4f6:" popovertarget=":Rmal4f6:" style="anchor-name:--popover-Rmal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/ic-technology/59364472"><span class="sr-only">IC Technology </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:11" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="IC Technology " src="https://cdn.slidesharecdn.com/ss_thumbnails/ictechnologysachin-160310103932-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="IC Technology " src="https://cdn.slidesharecdn.com/ss_thumbnails/ictechnologysachin-160310103932-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">IC Technology </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save IC Technology for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mmal4f6:" popovertarget=":R5mmal4f6:" style="anchor-name:--popover-R5mmal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mmal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mmal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/sdpable">sdpable</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses integrated circuit technology. It begins with an overview of the IC market breakdown by sector. It then discusses advantages of ICs such as smaller size, higher speed, lower power consumption compared to discrete components. The document provides a history of important IC inventions from 1904 to the present. It also discusses transistor scaling that has allowed achieving more complex ICs through reduced dimensions over time. Finally, it covers different IC design styles such as full custom, standard cell, gate array, and FPGA and their tradeoffs in terms of performance, cost, area, and time-to-market.</span></div></div><div class="" id=":Rmal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rmal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-12" aria-haspopup="dialog" aria-controls=":Rmql4f6:" popovertarget=":Rmql4f6:" style="anchor-name:--popover-Rmql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/ic-tech-unit-5-vlsi-process-integration/70256121"><span class="sr-only">Ic tech unit 5- VLSI Process Integration</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:12" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Ic tech unit 5- VLSI Process Integration" src="https://cdn.slidesharecdn.com/ss_thumbnails/ictechunit5-161219055549-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Ic tech unit 5- VLSI Process Integration" src="https://cdn.slidesharecdn.com/ss_thumbnails/ictechunit5-161219055549-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Ic tech unit 5- VLSI Process Integration</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Ic tech unit 5- VLSI Process Integration for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mmql4f6:" popovertarget=":R5mmql4f6:" style="anchor-name:--popover-R5mmql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mmql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mmql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/kritickasharma">kriticka sharma</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">junction oxide and isolation techniques, LOCOS, Metallization, NMOS and CMOS technology, FAult diagnosis</span></div></div><div class="" id=":Rmql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rmql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-13" aria-haspopup="dialog" aria-controls=":Rnal4f6:" popovertarget=":Rnal4f6:" style="anchor-name:--popover-Rnal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/mosfet-soifet-and-finfet/236290962"><span class="sr-only">MOSFET, SOI-FET and FIN-FET-ABU SYED KUET</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:13" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="MOSFET, SOI-FET and FIN-FET-ABU SYED KUET" src="https://cdn.slidesharecdn.com/ss_thumbnails/mosfetsoi-fetandfinfet-200627074207-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="MOSFET, SOI-FET and FIN-FET-ABU SYED KUET" src="https://cdn.slidesharecdn.com/ss_thumbnails/mosfetsoi-fetandfinfet-200627074207-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">MOSFET, SOI-FET and FIN-FET-ABU SYED KUET</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save MOSFET, SOI-FET and FIN-FET-ABU SYED KUET for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mnal4f6:" popovertarget=":R5mnal4f6:" style="anchor-name:--popover-R5mnal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mnal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mnal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/syedsumon">A. S. M. Jannatul Islam</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document provides an overview of the history and scaling of transistors and integrated circuits. It discusses how vacuum tubes were replaced by transistors, with the first transistor invented in 1947 and the first integrated circuit in 1958. It describes how continuous scaling and improvements in silicon manufacturing have led to billions of transistors being integrated onto a single chip today. The document then discusses different transistor technologies, including MOSFETs, and how scaling to smaller sizes introduced challenges like short channel effects that new transistor designs like FinFETs help address.</span></div></div><div class="" id=":Rnal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rnal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-14" aria-haspopup="dialog" aria-controls=":Rnql4f6:" popovertarget=":Rnql4f6:" style="anchor-name:--popover-Rnql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/second-order-effects/89683801"><span class="sr-only">Second order effects</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:14" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Second order effects" src="https://cdn.slidesharecdn.com/ss_thumbnails/secondordereffects-180305173314-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Second order effects" src="https://cdn.slidesharecdn.com/ss_thumbnails/secondordereffects-180305173314-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Second order effects</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Second order effects for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mnql4f6:" popovertarget=":R5mnql4f6:" style="anchor-name:--popover-R5mnql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mnql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mnql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/rppvch">PRAVEEN KUMAR CHITLURI</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses four topics related to transistors: 1. Threshold voltage is the minimum gate voltage needed to create a conducting path between source and drain, and depends on oxide thickness, temperature, and random dopant fluctuations. 2. Latchup refers to a short circuit formed between power and ground rails in an integrated circuit, caused by interaction between parasitic bipolar transistors. 3. Electromigration is the forced movement of metal ions due to an electric field, with atoms traveling toward the positive conductor end and vacancies toward the negative end. 4. Mobility degradation occurs due to lateral and vertical electric fields scattering carriers, reducing surface mobility as channel lengths shrink.</span></div></div><div class="" id=":Rnql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rnql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-15" aria-haspopup="dialog" aria-controls=":Roal4f6:" popovertarget=":Roal4f6:" style="anchor-name:--popover-Roal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/lightly-doped-drain/79861534"><span class="sr-only">Lightly Doped Drain</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:15" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Lightly Doped Drain" src="https://cdn.slidesharecdn.com/ss_thumbnails/ldd-170917150611-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Lightly Doped Drain" src="https://cdn.slidesharecdn.com/ss_thumbnails/ldd-170917150611-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Lightly Doped Drain</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Lightly Doped Drain for later" role="switch" aria-haspopup="dialog" aria-controls=":R5moal4f6:" popovertarget=":R5moal4f6:" style="anchor-name:--popover-R5moal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5moal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5moal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/shudhanshu29">Sudhanshu Janwadkar</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This presentation discusses about the need for Lightly Doped Drain. Also, why are LDD implants required in nMOS but not in pMOS</span></div></div><div class="" id=":Roal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Roal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-16" aria-haspopup="dialog" aria-controls=":Roql4f6:" popovertarget=":Roql4f6:" style="anchor-name:--popover-Roql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/subhradeeptoton/crosstalk-minimisation-using-vlsi-26184039"><span class="sr-only">crosstalk minimisation using vlsi</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:16" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="crosstalk minimisation using vlsi" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsialmostfinal-130913214006-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="crosstalk minimisation using vlsi" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsialmostfinal-130913214006-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">crosstalk minimisation using vlsi</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save crosstalk minimisation using vlsi for later" role="switch" aria-haspopup="dialog" aria-controls=":R5moql4f6:" popovertarget=":R5moql4f6:" style="anchor-name:--popover-R5moql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5moql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5moql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/subhradeeptoton">subhradeep mitra</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document summarizes techniques for minimizing crosstalk in VLSI designs. It discusses the VLSI design cycle and physical design cycle. Routing is a key stage that involves global and detailed routing. Crosstalk occurs due to mutual inductance and capacitance between wires and can affect signal integrity, delay, and timing. Basic approaches to reduce crosstalk include segregating wires, increasing spacing between wires, using ground shields, optimizing the net ordering and layer assignments. Specific techniques mentioned are widening spacing, minimizing wire heights and lengths of parallel runs, using differential routing, and routing orthogonal layers.</span></div></div><div class="" id=":Roql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Roql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-17" aria-haspopup="dialog" aria-controls=":Rpal4f6:" popovertarget=":Rpal4f6:" style="anchor-name:--popover-Rpal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/mosfet-124149811/124149811"><span class="sr-only">Mosfet</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:17" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Mosfet" src="https://cdn.slidesharecdn.com/ss_thumbnails/mosfet-181127115058-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Mosfet" src="https://cdn.slidesharecdn.com/ss_thumbnails/mosfet-181127115058-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Mosfet</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Mosfet for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mpal4f6:" popovertarget=":R5mpal4f6:" style="anchor-name:--popover-R5mpal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mpal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mpal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/sarunkutti">sarunkutti</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses the I-V characteristics of MOSFETs, which occur in three regions: cutoff, linear, and saturation. In cutoff region (VGS < VT), no channel is formed and IDS = 0. In linear region (VGS > VT, VDS < VGS - VT), IDS varies linearly with VDS. In saturation region (VGS > VT, VDS > VGS - VT), further increases in VDS do not increase IDS due to channel pinch-off. Equations are provided to describe IDS in each region.</span></div></div><div class="" id=":Rpal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rpal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-18" aria-haspopup="dialog" aria-controls=":Rpql4f6:" popovertarget=":Rpql4f6:" style="anchor-name:--popover-Rpql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/bandgap-ppt/57274756"><span class="sr-only">bandgap ppt</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:18" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="bandgap ppt" src="https://cdn.slidesharecdn.com/ss_thumbnails/79768869-c307-4439-87aa-81b230495570-160120124422-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="bandgap ppt" src="https://cdn.slidesharecdn.com/ss_thumbnails/79768869-c307-4439-87aa-81b230495570-160120124422-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">bandgap ppt</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save bandgap ppt for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mpql4f6:" popovertarget=":R5mpql4f6:" style="anchor-name:--popover-R5mpql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mpql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mpql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/lingadharreddy">lingadhar reddy</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document describes the implementation of a bandgap reference circuit. It was designed by M. Lingadhar Reddy under the guidance of Mr. G. Shiva Kumar at GITAM University in Hyderabad, India from 2013-2015. The document outlines the basic operation of a bandgap reference circuit, which produces a reference voltage that is stable over changes in temperature, supply voltage, and process parameters. It discusses the tool and technology used, different approaches to bandgap references, and details the design and simulation results of a two-stage CMOS operational amplifier and final bandgap reference circuit implemented in a 90nm CMOS technology using Cadence Virtuoso.</span></div></div><div class="" id=":Rpql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rpql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-19" aria-haspopup="dialog" aria-controls=":Rqal4f6:" popovertarget=":Rqal4f6:" style="anchor-name:--popover-Rqal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-design-and-fabrication-ppt/47160694"><span class="sr-only">Vlsi design and fabrication ppt</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:19" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Vlsi design and fabrication ppt" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsidesignandfabricationppt-150419062609-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Vlsi design and fabrication ppt" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsidesignandfabricationppt-150419062609-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Vlsi design and fabrication ppt</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Vlsi design and fabrication ppt for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mqal4f6:" popovertarget=":R5mqal4f6:" style="anchor-name:--popover-R5mqal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mqal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mqal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/manjushreemm">Manjushree Mashal</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document provides information about a paper presentation on VLSI design and fabrication by two students. It includes an outline of topics to be covered such as introduction to VLSI, MOS transistors, CMOS circuits, and fabrication. The presentation aims to provide an introduction to VLSI design including how MOS transistors work and are used to build logic gates, as well as the process of designing masks and layouts for chips. It also gives an overview of the fabrication process used to manufacture chips.</span></div></div><div class="" id=":Rqal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rqal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-20" aria-haspopup="dialog" aria-controls=":Rqql4f6:" popovertarget=":Rqql4f6:" style="anchor-name:--popover-Rqql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/introduction-to-finfet-89025450/89025450"><span class="sr-only">Introduction to FinFET</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:20" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Introduction to FinFET" src="https://cdn.slidesharecdn.com/ss_thumbnails/introductiontofinfet-180227020253-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Introduction to FinFET" src="https://cdn.slidesharecdn.com/ss_thumbnails/introductiontofinfet-180227020253-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Introduction to FinFET</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Introduction to FinFET for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mqql4f6:" popovertarget=":R5mqql4f6:" style="anchor-name:--popover-R5mqql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mqql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mqql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ManishKenchi">ManishKenchi</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">For more information regarding the "Construction of finFET" you can contact through mail (manishkenchi111296@gmail.com)</span></div></div><div class="" id=":Rqql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rqql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-21" aria-haspopup="dialog" aria-controls=":Rral4f6:" popovertarget=":Rral4f6:" style="anchor-name:--popover-Rral4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/bgr-57274715/57274715"><span class="sr-only">BGR</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:21" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="BGR" src="https://cdn.slidesharecdn.com/ss_thumbnails/fe67e1bd-c993-4e70-9b81-ab711473d201-160120124327-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="BGR" src="https://cdn.slidesharecdn.com/ss_thumbnails/fe67e1bd-c993-4e70-9b81-ab711473d201-160120124327-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">BGR</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save BGR for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mral4f6:" popovertarget=":R5mral4f6:" style="anchor-name:--popover-R5mral4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mral4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mral4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/lingadharreddy">lingadhar reddy</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document describes the implementation of a bandgap reference circuit. It begins by acknowledging those who supported the project. It then provides an abstract stating that bandgap reference circuits are used to generate stable reference voltages and currents on integrated circuits. The main goal of the project was to understand bandgap reference design and limitations, and implement a bandgap reference circuit in a 90nm CMOS technology using CADENCE.</span></div></div><div class="" id=":Rral4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rral4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-22" aria-haspopup="dialog" aria-controls=":Rrql4f6:" popovertarget=":Rrql4f6:" style="anchor-name:--popover-Rrql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-designfabrication/49132602"><span class="sr-only">VLSI Design(Fabrication)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:22" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="VLSI Design(Fabrication)" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsi2-150608165741-lva1-app6891-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="VLSI Design(Fabrication)" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsi2-150608165741-lva1-app6891-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">VLSI Design(Fabrication)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save VLSI Design(Fabrication) for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mrql4f6:" popovertarget=":R5mrql4f6:" style="anchor-name:--popover-R5mrql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mrql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mrql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/TrijitMallick">Trijit Mallick</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">this ppt provides fabrication on SI wafer, CMOS fabrication process, basic CMOS inverter, future, application, advantage, disadvantage etc.</span></div></div><div class="" id=":Rrql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rrql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-23" aria-haspopup="dialog" aria-controls=":Rsal4f6:" popovertarget=":Rsal4f6:" style="anchor-name:--popover-Rsal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/short-channel-effects-115332110/115332110"><span class="sr-only">Short channel effects</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:23" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Short channel effects" src="https://cdn.slidesharecdn.com/ss_thumbnails/shortchanneleffects-180919050414-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Short channel effects" src="https://cdn.slidesharecdn.com/ss_thumbnails/shortchanneleffects-180919050414-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Short channel effects</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Short channel effects for later" role="switch" aria-haspopup="dialog" aria-controls=":R5msal4f6:" popovertarget=":R5msal4f6:" style="anchor-name:--popover-R5msal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5msal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5msal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/aditiagrawal97">aditiagrawal97</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses short channel effects that occur in MOSFET devices when the channel length decreases to the same order of magnitude as the source/drain junction depth. It describes five main short channel effects: drain induced barrier lowering, drain punch through, velocity saturation, impact ionization, and hot electron effects. For each effect, it provides an explanation of the physical phenomenon and how it impacts device performance as the channel length decreases. It concludes by listing three references for further reading on leakage current mechanisms and MOSFET modeling.</span></div></div><div class="" id=":Rsal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rsal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-24" aria-haspopup="dialog" aria-controls=":Rsql4f6:" popovertarget=":Rsql4f6:" style="anchor-name:--popover-Rsql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/finfet-technology/227466347"><span class="sr-only">Finfet Technology</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:24" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Finfet Technology" src="https://cdn.slidesharecdn.com/ss_thumbnails/17304013-navya-200209170047-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Finfet Technology" src="https://cdn.slidesharecdn.com/ss_thumbnails/17304013-navya-200209170047-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Finfet Technology</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Finfet Technology for later" role="switch" aria-haspopup="dialog" aria-controls=":R5msql4f6:" popovertarget=":R5msql4f6:" style="anchor-name:--popover-R5msql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5msql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5msql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/SrinivasVasamsetti2">Srinivas Vasamsetti </a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses FinFET technology. It begins with an introduction to FinFETs, explaining that they are a type of double-gate CMOS that offers advantages over traditional CMOS for scaling to short gate lengths. It then discusses why FinFET technology is needed as traditional CMOS scaling faces challenges from subthreshold and gate leakage. It provides details on double-gate FET structure and operation, including how it controls short-channel effects better than single-gate FETs. It also covers FinFET features, applications, challenges and concludes that FinFETs can help continue CMOS scaling if key issues like fin patterning and gate work functions are addressed.</span></div></div><div class="" id=":Rsql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rsql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-25" aria-haspopup="dialog" aria-controls=":Rtal4f6:" popovertarget=":Rtal4f6:" style="anchor-name:--popover-Rtal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-2/11350708"><span class="sr-only">Vlsi 2</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:25" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Vlsi 2" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsi2-120131080155-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Vlsi 2" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsi2-120131080155-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Vlsi 2</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Vlsi 2 for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mtal4f6:" popovertarget=":R5mtal4f6:" style="anchor-name:--popover-R5mtal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mtal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mtal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/idris01111">idris01111</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document describes the key steps in CMOS fabrication: 1. A p-type substrate is used, and n-well regions are defined through implantation to create isolation for p-MOSFETs. 2. Active device regions and field oxide isolation are then patterned, followed by gate oxide growth and polysilicon deposition. 3. Self-aligned implantation creates n-type and p-type source/drain regions. Additional metallization layers connect the transistors.</span></div></div><div class="" id=":Rtal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rtal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-26" aria-haspopup="dialog" aria-controls=":Rtql4f6:" popovertarget=":Rtql4f6:" style="anchor-name:--popover-Rtql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/powerplanning/16883536"><span class="sr-only">Powerplanning</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:26" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Powerplanning" src="https://cdn.slidesharecdn.com/ss_thumbnails/powerplanning-130302112400-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Powerplanning" src="https://cdn.slidesharecdn.com/ss_thumbnails/powerplanning-130302112400-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Powerplanning</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Powerplanning for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mtql4f6:" popovertarget=":R5mtql4f6:" style="anchor-name:--popover-R5mtql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mtql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mtql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/vlsisyst">VLSI SYSTEM Design</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">https://www.udemy.com/vlsi-academy Usually, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. But on a chip, it becomes necessary to have a grid structure of power, with more than one 'vdd' and 'vss'. The concept of power grid structure would be uploaded soon. It is actually the scaling trend that drives chip designers for power grid structure. </span></div></div><div class="" id=":Rtql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rtql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-27" aria-haspopup="dialog" aria-controls=":Rual4f6:" popovertarget=":Rual4f6:" style="anchor-name:--popover-Rual4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/cmos-fabrication-71314286/71314286"><span class="sr-only">Cmos fabrication</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:27" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Cmos fabrication" src="https://cdn.slidesharecdn.com/ss_thumbnails/cmosfabrication-170124042413-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Cmos fabrication" src="https://cdn.slidesharecdn.com/ss_thumbnails/cmosfabrication-170124042413-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Cmos fabrication</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Cmos fabrication for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mual4f6:" popovertarget=":R5mual4f6:" style="anchor-name:--popover-R5mual4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mual4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mual4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/KANAGARAJT4">KANAGARAJ T</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document summarizes the basic steps in CMOS fabrication: (1) dopants are diffused or implanted into a silicon wafer to form n-well and p-substrate regions; (2) a gate oxide and polysilicon layer are deposited and patterned to form transistors; (3) n+ and p+ diffusion regions are implanted or diffused to form sources, drains and contacts; (4) a metallization process deposits aluminum wires to connect the transistors together into circuits. The process involves repeatedly depositing materials and using lithography to pattern layers from the bottom up on the silicon wafer.</span></div></div><div class="" id=":Rual4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rual4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-28" aria-haspopup="dialog" aria-controls=":Ruql4f6:" popovertarget=":Ruql4f6:" style="anchor-name:--popover-Ruql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/concept-note-env-laboratory-infrastructureppp-min-of-env-48790598/48790598"><span class="sr-only">Concept note env laboratory infrastructure-ppp min of env</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:28" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Concept note env laboratory infrastructure-ppp min of env" src="https://cdn.slidesharecdn.com/ss_thumbnails/conceptnote-envlaboratoryinfrastructure-pppminofenv-150530173651-lva1-app6892-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Concept note env laboratory infrastructure-ppp min of env" src="https://cdn.slidesharecdn.com/ss_thumbnails/conceptnote-envlaboratoryinfrastructure-pppminofenv-150530173651-lva1-app6892-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" 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RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-0" aria-haspopup="dialog" aria-controls=":R45ipkf6:" popovertarget=":R45ipkf6:" style="anchor-name:--popover-R45ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/matching-concept-in-microelectronics/237111064"><span class="sr-only">Matching concept in Microelectronics</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:0" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Matching concept in Microelectronics" src="https://cdn.slidesharecdn.com/ss_thumbnails/microelectronicsmatchingpresentation3matchingied3030harishivem177319-200721134926-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Matching concept in Microelectronics" src="https://cdn.slidesharecdn.com/ss_thumbnails/microelectronicsmatchingpresentation3matchingied3030harishivem177319-200721134926-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Matching concept in Microelectronics</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Matching concept in Microelectronics for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dk5ipkf6:" popovertarget=":R1dk5ipkf6:" style="anchor-name:--popover-R1dk5ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dk5ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dk5ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/HarishSingh8">Tallinn University of Technology</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This presentation speaks about type of matching in microelectronics. Dependencies of matching are discussed.</span></div></div><div class="" id=":R45ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R45ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-1" aria-haspopup="dialog" aria-controls=":R49ipkf6:" popovertarget=":R49ipkf6:" style="anchor-name:--popover-R49ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/venkat1234_nxp/layout02-1"><span class="sr-only">Layout02 (1)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:1" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Layout02 (1)" src="https://cdn.slidesharecdn.com/ss_thumbnails/layout021-160229081601-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Layout02 (1)" src="https://cdn.slidesharecdn.com/ss_thumbnails/layout021-160229081601-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Layout02 (1)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Layout02 (1) for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dk9ipkf6:" popovertarget=":R1dk9ipkf6:" style="anchor-name:--popover-R1dk9ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dk9ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dk9ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/venkat1234_nxp">venkat1234_nxp</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses the layout of analog CMOS integrated circuits. It focuses on the layout of transistors and basic cells. Key topics covered include: - Layout of a single transistor, use of multiple fingers, and interdigitated transistors for matching. - Common centroid layouts and dummy devices to reduce mismatch. - Ensuring matched interconnect resistance, capacitance, and parasitics. - Stacked layout of analog cells with stick diagrams to represent multiple transistors. - Two examples of laying out basic cells - a two-stage op-amp and folded cascode. Design considerations like transistor sizing and grouping are discussed.</span></div></div><div class="" id=":R49ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R49ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-2" aria-haspopup="dialog" aria-controls=":R4dipkf6:" popovertarget=":R4dipkf6:" style="anchor-name:--popover-R4dipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/latch-up/26735030"><span class="sr-only">Latch up</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:2" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Latch up" src="https://cdn.slidesharecdn.com/ss_thumbnails/latch-up-131001053300-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Latch up" src="https://cdn.slidesharecdn.com/ss_thumbnails/latch-up-131001053300-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Latch up</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Latch up for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkdipkf6:" popovertarget=":R1dkdipkf6:" style="anchor-name:--popover-R1dkdipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkdipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkdipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ishan111">ishan111</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Latch-up occurs in CMOS chips due to the interaction of parasitic bipolar transistors that form a silicon-controlled rectifier between the power and ground rails. This can cause excessive currents and potentially damage devices. Latch-up can be triggered by disturbances that increase the collector current of one of the parasitic transistors, activating positive feedback between the transistors. Guidelines for preventing latch-up include using guard rings connected to power and ground around transistors to reduce resistance and capture minority carriers, as well as placing wells and substrate contacts close to transistor sources.</span></div></div><div class="" id=":R4dipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4dipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-3" aria-haspopup="dialog" aria-controls=":R4hipkf6:" popovertarget=":R4hipkf6:" style="anchor-name:--popover-R4hipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/ic-technology/59364472"><span class="sr-only">IC Technology </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:3" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="IC Technology " src="https://cdn.slidesharecdn.com/ss_thumbnails/ictechnologysachin-160310103932-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="IC Technology " src="https://cdn.slidesharecdn.com/ss_thumbnails/ictechnologysachin-160310103932-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">IC Technology </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save IC Technology for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkhipkf6:" popovertarget=":R1dkhipkf6:" style="anchor-name:--popover-R1dkhipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkhipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkhipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/sdpable">sdpable</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses integrated circuit technology. It begins with an overview of the IC market breakdown by sector. It then discusses advantages of ICs such as smaller size, higher speed, lower power consumption compared to discrete components. The document provides a history of important IC inventions from 1904 to the present. It also discusses transistor scaling that has allowed achieving more complex ICs through reduced dimensions over time. Finally, it covers different IC design styles such as full custom, standard cell, gate array, and FPGA and their tradeoffs in terms of performance, cost, area, and time-to-market.</span></div></div><div class="" id=":R4hipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4hipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-4" aria-haspopup="dialog" aria-controls=":R4lipkf6:" popovertarget=":R4lipkf6:" style="anchor-name:--popover-R4lipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/ic-tech-unit-5-vlsi-process-integration/70256121"><span class="sr-only">Ic tech unit 5- VLSI Process Integration</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:4" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Ic tech unit 5- VLSI Process Integration" src="https://cdn.slidesharecdn.com/ss_thumbnails/ictechunit5-161219055549-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Ic tech unit 5- VLSI Process Integration" src="https://cdn.slidesharecdn.com/ss_thumbnails/ictechunit5-161219055549-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Ic tech unit 5- VLSI Process Integration</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Ic tech unit 5- VLSI Process Integration for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dklipkf6:" popovertarget=":R1dklipkf6:" style="anchor-name:--popover-R1dklipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dklipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dklipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/kritickasharma">kriticka sharma</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">junction oxide and isolation techniques, LOCOS, Metallization, NMOS and CMOS technology, FAult diagnosis</span></div></div><div class="" id=":R4lipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4lipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-5" aria-haspopup="dialog" aria-controls=":R4pipkf6:" popovertarget=":R4pipkf6:" style="anchor-name:--popover-R4pipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/mosfet-soifet-and-finfet/236290962"><span class="sr-only">MOSFET, SOI-FET and FIN-FET-ABU SYED KUET</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:5" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="MOSFET, SOI-FET and FIN-FET-ABU SYED KUET" src="https://cdn.slidesharecdn.com/ss_thumbnails/mosfetsoi-fetandfinfet-200627074207-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="MOSFET, SOI-FET and FIN-FET-ABU SYED KUET" src="https://cdn.slidesharecdn.com/ss_thumbnails/mosfetsoi-fetandfinfet-200627074207-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">MOSFET, SOI-FET and FIN-FET-ABU SYED KUET</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save MOSFET, SOI-FET and FIN-FET-ABU SYED KUET for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkpipkf6:" popovertarget=":R1dkpipkf6:" style="anchor-name:--popover-R1dkpipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkpipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkpipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/syedsumon">A. S. M. Jannatul Islam</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document provides an overview of the history and scaling of transistors and integrated circuits. It discusses how vacuum tubes were replaced by transistors, with the first transistor invented in 1947 and the first integrated circuit in 1958. It describes how continuous scaling and improvements in silicon manufacturing have led to billions of transistors being integrated onto a single chip today. The document then discusses different transistor technologies, including MOSFETs, and how scaling to smaller sizes introduced challenges like short channel effects that new transistor designs like FinFETs help address.</span></div></div><div class="" id=":R4pipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4pipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-6" aria-haspopup="dialog" aria-controls=":R4tipkf6:" popovertarget=":R4tipkf6:" style="anchor-name:--popover-R4tipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/second-order-effects/89683801"><span class="sr-only">Second order effects</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:6" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Second order effects" src="https://cdn.slidesharecdn.com/ss_thumbnails/secondordereffects-180305173314-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Second order effects" src="https://cdn.slidesharecdn.com/ss_thumbnails/secondordereffects-180305173314-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Second order effects</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Second order effects for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dktipkf6:" popovertarget=":R1dktipkf6:" style="anchor-name:--popover-R1dktipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dktipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dktipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/rppvch">PRAVEEN KUMAR CHITLURI</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses four topics related to transistors: 1. Threshold voltage is the minimum gate voltage needed to create a conducting path between source and drain, and depends on oxide thickness, temperature, and random dopant fluctuations. 2. Latchup refers to a short circuit formed between power and ground rails in an integrated circuit, caused by interaction between parasitic bipolar transistors. 3. Electromigration is the forced movement of metal ions due to an electric field, with atoms traveling toward the positive conductor end and vacancies toward the negative end. 4. Mobility degradation occurs due to lateral and vertical electric fields scattering carriers, reducing surface mobility as channel lengths shrink.</span></div></div><div class="" id=":R4tipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4tipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-7" aria-haspopup="dialog" aria-controls=":R51ipkf6:" popovertarget=":R51ipkf6:" style="anchor-name:--popover-R51ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/lightly-doped-drain/79861534"><span class="sr-only">Lightly Doped Drain</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:7" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Lightly Doped Drain" src="https://cdn.slidesharecdn.com/ss_thumbnails/ldd-170917150611-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Lightly Doped Drain" src="https://cdn.slidesharecdn.com/ss_thumbnails/ldd-170917150611-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Lightly Doped Drain</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Lightly Doped Drain for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl1ipkf6:" popovertarget=":R1dl1ipkf6:" style="anchor-name:--popover-R1dl1ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl1ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl1ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/shudhanshu29">Sudhanshu Janwadkar</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This presentation discusses about the need for Lightly Doped Drain. Also, why are LDD implants required in nMOS but not in pMOS</span></div></div><div class="" id=":R51ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R51ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-8" aria-haspopup="dialog" aria-controls=":R55ipkf6:" popovertarget=":R55ipkf6:" style="anchor-name:--popover-R55ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/subhradeeptoton/crosstalk-minimisation-using-vlsi-26184039"><span class="sr-only">crosstalk minimisation using vlsi</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:8" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="crosstalk minimisation using vlsi" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsialmostfinal-130913214006-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="crosstalk minimisation using vlsi" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsialmostfinal-130913214006-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">crosstalk minimisation using vlsi</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save crosstalk minimisation using vlsi for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl5ipkf6:" popovertarget=":R1dl5ipkf6:" style="anchor-name:--popover-R1dl5ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl5ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl5ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/subhradeeptoton">subhradeep mitra</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document summarizes techniques for minimizing crosstalk in VLSI designs. It discusses the VLSI design cycle and physical design cycle. Routing is a key stage that involves global and detailed routing. Crosstalk occurs due to mutual inductance and capacitance between wires and can affect signal integrity, delay, and timing. Basic approaches to reduce crosstalk include segregating wires, increasing spacing between wires, using ground shields, optimizing the net ordering and layer assignments. Specific techniques mentioned are widening spacing, minimizing wire heights and lengths of parallel runs, using differential routing, and routing orthogonal layers.</span></div></div><div class="" id=":R55ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R55ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-9" aria-haspopup="dialog" aria-controls=":R59ipkf6:" popovertarget=":R59ipkf6:" style="anchor-name:--popover-R59ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/mosfet-124149811/124149811"><span class="sr-only">Mosfet</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:9" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Mosfet" src="https://cdn.slidesharecdn.com/ss_thumbnails/mosfet-181127115058-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Mosfet" src="https://cdn.slidesharecdn.com/ss_thumbnails/mosfet-181127115058-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Mosfet</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Mosfet for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl9ipkf6:" popovertarget=":R1dl9ipkf6:" style="anchor-name:--popover-R1dl9ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl9ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl9ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/sarunkutti">sarunkutti</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses the I-V characteristics of MOSFETs, which occur in three regions: cutoff, linear, and saturation. In cutoff region (VGS < VT), no channel is formed and IDS = 0. In linear region (VGS > VT, VDS < VGS - VT), IDS varies linearly with VDS. In saturation region (VGS > VT, VDS > VGS - VT), further increases in VDS do not increase IDS due to channel pinch-off. Equations are provided to describe IDS in each region.</span></div></div><div class="" id=":R59ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R59ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-10" aria-haspopup="dialog" aria-controls=":R5dipkf6:" popovertarget=":R5dipkf6:" style="anchor-name:--popover-R5dipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/bandgap-ppt/57274756"><span class="sr-only">bandgap ppt</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:10" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="bandgap ppt" src="https://cdn.slidesharecdn.com/ss_thumbnails/79768869-c307-4439-87aa-81b230495570-160120124422-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="bandgap ppt" src="https://cdn.slidesharecdn.com/ss_thumbnails/79768869-c307-4439-87aa-81b230495570-160120124422-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">bandgap ppt</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save bandgap ppt for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dldipkf6:" popovertarget=":R1dldipkf6:" style="anchor-name:--popover-R1dldipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dldipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dldipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/lingadharreddy">lingadhar reddy</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document describes the implementation of a bandgap reference circuit. It was designed by M. Lingadhar Reddy under the guidance of Mr. G. Shiva Kumar at GITAM University in Hyderabad, India from 2013-2015. The document outlines the basic operation of a bandgap reference circuit, which produces a reference voltage that is stable over changes in temperature, supply voltage, and process parameters. It discusses the tool and technology used, different approaches to bandgap references, and details the design and simulation results of a two-stage CMOS operational amplifier and final bandgap reference circuit implemented in a 90nm CMOS technology using Cadence Virtuoso.</span></div></div><div class="" id=":R5dipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5dipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-11" aria-haspopup="dialog" aria-controls=":R5hipkf6:" popovertarget=":R5hipkf6:" style="anchor-name:--popover-R5hipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-design-and-fabrication-ppt/47160694"><span class="sr-only">Vlsi design and fabrication ppt</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:11" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Vlsi design and fabrication ppt" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsidesignandfabricationppt-150419062609-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Vlsi design and fabrication ppt" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsidesignandfabricationppt-150419062609-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Vlsi design and fabrication ppt</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Vlsi design and fabrication ppt for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dlhipkf6:" popovertarget=":R1dlhipkf6:" style="anchor-name:--popover-R1dlhipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dlhipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dlhipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/manjushreemm">Manjushree Mashal</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document provides information about a paper presentation on VLSI design and fabrication by two students. It includes an outline of topics to be covered such as introduction to VLSI, MOS transistors, CMOS circuits, and fabrication. The presentation aims to provide an introduction to VLSI design including how MOS transistors work and are used to build logic gates, as well as the process of designing masks and layouts for chips. It also gives an overview of the fabrication process used to manufacture chips.</span></div></div><div class="" id=":R5hipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5hipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-12" aria-haspopup="dialog" aria-controls=":R5lipkf6:" popovertarget=":R5lipkf6:" style="anchor-name:--popover-R5lipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/introduction-to-finfet-89025450/89025450"><span class="sr-only">Introduction to FinFET</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:12" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Introduction to FinFET" src="https://cdn.slidesharecdn.com/ss_thumbnails/introductiontofinfet-180227020253-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Introduction to FinFET" src="https://cdn.slidesharecdn.com/ss_thumbnails/introductiontofinfet-180227020253-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Introduction to FinFET</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Introduction to FinFET for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dllipkf6:" popovertarget=":R1dllipkf6:" style="anchor-name:--popover-R1dllipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dllipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dllipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ManishKenchi">ManishKenchi</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">For more information regarding the "Construction of finFET" you can contact through mail (manishkenchi111296@gmail.com)</span></div></div><div class="" id=":R5lipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5lipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-13" aria-haspopup="dialog" aria-controls=":R5pipkf6:" popovertarget=":R5pipkf6:" style="anchor-name:--popover-R5pipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/bgr-57274715/57274715"><span class="sr-only">BGR</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:13" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="BGR" src="https://cdn.slidesharecdn.com/ss_thumbnails/fe67e1bd-c993-4e70-9b81-ab711473d201-160120124327-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="BGR" src="https://cdn.slidesharecdn.com/ss_thumbnails/fe67e1bd-c993-4e70-9b81-ab711473d201-160120124327-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">BGR</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save BGR for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dlpipkf6:" popovertarget=":R1dlpipkf6:" style="anchor-name:--popover-R1dlpipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dlpipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dlpipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/lingadharreddy">lingadhar reddy</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document describes the implementation of a bandgap reference circuit. It begins by acknowledging those who supported the project. It then provides an abstract stating that bandgap reference circuits are used to generate stable reference voltages and currents on integrated circuits. The main goal of the project was to understand bandgap reference design and limitations, and implement a bandgap reference circuit in a 90nm CMOS technology using CADENCE.</span></div></div><div class="" id=":R5pipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5pipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-14" aria-haspopup="dialog" aria-controls=":R5tipkf6:" popovertarget=":R5tipkf6:" style="anchor-name:--popover-R5tipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-designfabrication/49132602"><span class="sr-only">VLSI Design(Fabrication)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:14" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="VLSI Design(Fabrication)" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsi2-150608165741-lva1-app6891-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="VLSI Design(Fabrication)" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsi2-150608165741-lva1-app6891-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">VLSI Design(Fabrication)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save VLSI Design(Fabrication) for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dltipkf6:" popovertarget=":R1dltipkf6:" style="anchor-name:--popover-R1dltipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dltipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dltipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/TrijitMallick">Trijit Mallick</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">this ppt provides fabrication on SI wafer, CMOS fabrication process, basic CMOS inverter, future, application, advantage, disadvantage etc.</span></div></div><div class="" id=":R5tipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5tipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-15" aria-haspopup="dialog" aria-controls=":R61ipkf6:" popovertarget=":R61ipkf6:" style="anchor-name:--popover-R61ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/short-channel-effects-115332110/115332110"><span class="sr-only">Short channel effects</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:15" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Short channel effects" src="https://cdn.slidesharecdn.com/ss_thumbnails/shortchanneleffects-180919050414-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Short channel effects" src="https://cdn.slidesharecdn.com/ss_thumbnails/shortchanneleffects-180919050414-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Short channel effects</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Short channel effects for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dm1ipkf6:" popovertarget=":R1dm1ipkf6:" style="anchor-name:--popover-R1dm1ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dm1ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dm1ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/aditiagrawal97">aditiagrawal97</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses short channel effects that occur in MOSFET devices when the channel length decreases to the same order of magnitude as the source/drain junction depth. It describes five main short channel effects: drain induced barrier lowering, drain punch through, velocity saturation, impact ionization, and hot electron effects. For each effect, it provides an explanation of the physical phenomenon and how it impacts device performance as the channel length decreases. It concludes by listing three references for further reading on leakage current mechanisms and MOSFET modeling.</span></div></div><div class="" id=":R61ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R61ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-16" aria-haspopup="dialog" aria-controls=":R65ipkf6:" popovertarget=":R65ipkf6:" style="anchor-name:--popover-R65ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/finfet-technology/227466347"><span class="sr-only">Finfet Technology</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:16" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Finfet Technology" src="https://cdn.slidesharecdn.com/ss_thumbnails/17304013-navya-200209170047-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Finfet Technology" src="https://cdn.slidesharecdn.com/ss_thumbnails/17304013-navya-200209170047-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Finfet Technology</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Finfet Technology for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dm5ipkf6:" popovertarget=":R1dm5ipkf6:" style="anchor-name:--popover-R1dm5ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dm5ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dm5ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/SrinivasVasamsetti2">Srinivas Vasamsetti </a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses FinFET technology. It begins with an introduction to FinFETs, explaining that they are a type of double-gate CMOS that offers advantages over traditional CMOS for scaling to short gate lengths. It then discusses why FinFET technology is needed as traditional CMOS scaling faces challenges from subthreshold and gate leakage. It provides details on double-gate FET structure and operation, including how it controls short-channel effects better than single-gate FETs. It also covers FinFET features, applications, challenges and concludes that FinFETs can help continue CMOS scaling if key issues like fin patterning and gate work functions are addressed.</span></div></div><div class="" id=":R65ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R65ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-17" aria-haspopup="dialog" aria-controls=":R69ipkf6:" popovertarget=":R69ipkf6:" style="anchor-name:--popover-R69ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-2/11350708"><span class="sr-only">Vlsi 2</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:17" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Vlsi 2" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsi2-120131080155-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Vlsi 2" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsi2-120131080155-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Vlsi 2</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Vlsi 2 for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dm9ipkf6:" popovertarget=":R1dm9ipkf6:" style="anchor-name:--popover-R1dm9ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dm9ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dm9ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/idris01111">idris01111</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document describes the key steps in CMOS fabrication: 1. A p-type substrate is used, and n-well regions are defined through implantation to create isolation for p-MOSFETs. 2. Active device regions and field oxide isolation are then patterned, followed by gate oxide growth and polysilicon deposition. 3. Self-aligned implantation creates n-type and p-type source/drain regions. Additional metallization layers connect the transistors.</span></div></div><div class="" id=":R69ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R69ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-18" aria-haspopup="dialog" aria-controls=":R6dipkf6:" popovertarget=":R6dipkf6:" style="anchor-name:--popover-R6dipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/powerplanning/16883536"><span class="sr-only">Powerplanning</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:18" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Powerplanning" src="https://cdn.slidesharecdn.com/ss_thumbnails/powerplanning-130302112400-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Powerplanning" src="https://cdn.slidesharecdn.com/ss_thumbnails/powerplanning-130302112400-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Powerplanning</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Powerplanning for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dmdipkf6:" popovertarget=":R1dmdipkf6:" style="anchor-name:--popover-R1dmdipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dmdipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dmdipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/vlsisyst">VLSI SYSTEM Design</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">https://www.udemy.com/vlsi-academy Usually, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. But on a chip, it becomes necessary to have a grid structure of power, with more than one 'vdd' and 'vss'. The concept of power grid structure would be uploaded soon. It is actually the scaling trend that drives chip designers for power grid structure. </span></div></div><div class="" id=":R6dipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R6dipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-19" aria-haspopup="dialog" aria-controls=":R6hipkf6:" popovertarget=":R6hipkf6:" style="anchor-name:--popover-R6hipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/cmos-fabrication-71314286/71314286"><span class="sr-only">Cmos fabrication</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:19" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Cmos fabrication" src="https://cdn.slidesharecdn.com/ss_thumbnails/cmosfabrication-170124042413-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Cmos fabrication" src="https://cdn.slidesharecdn.com/ss_thumbnails/cmosfabrication-170124042413-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Cmos fabrication</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Cmos fabrication for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dmhipkf6:" popovertarget=":R1dmhipkf6:" style="anchor-name:--popover-R1dmhipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dmhipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dmhipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/KANAGARAJT4">KANAGARAJ T</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document summarizes the basic steps in CMOS fabrication: (1) dopants are diffused or implanted into a silicon wafer to form n-well and p-substrate regions; (2) a gate oxide and polysilicon layer are deposited and patterned to form transistors; (3) n+ and p+ diffusion regions are implanted or diffused to form sources, drains and contacts; (4) a metallization process deposits aluminum wires to connect the transistors together into circuits. The process involves repeatedly depositing materials and using lithography to pattern layers from the bottom up on the silicon wafer.</span></div></div><div class="" id=":R6hipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R6hipkf6"></div></div><div class="desktop-recs"><div class="Slider_root__c0Jo8"><div class="Slider_scroller__KHjw4"><div class="BottomRecommendationCard_root__gffTk SlideshowCard_root__pD8t4 slideshow-card"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/matching-concept-in-microelectronics/237111064"><span class="sr-only">Matching concept in Microelectronics</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:16 / 9;--index:0" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Matching concept in 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data-cy="slideshow-title">Brand Profile 2016_email2</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Brand Profile 2016_email2 for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkpj9kf6:" popovertarget=":R1dkpj9kf6:" style="anchor-name:--popover-R1dkpj9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkpj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkpj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/LyleJulius">Lyle Julius</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Africology is a leading natural skincare company based in South Africa that offers luxury natural and eco-friendly products. The brand is committed to using only 100% natural and biodegradable ingredients in its products and sustainable practices. It offers a full range of skincare products and spa treatments inspired by African wisdom and traditions. The company was founded by Renchia Droganis and has grown successfully both in South Africa and internationally while staying true to its holistic and ethical philosophy.</span></div></div><div class="" id=":R4pj9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4pj9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-6" aria-haspopup="dialog" aria-controls=":R4tj9kf6:" popovertarget=":R4tj9kf6:" style="anchor-name:--popover-R4tj9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://es.slideshare.net/slideshow/fisiopatologia-megacolon/64737578"><span class="sr-only">Fisiopatologia megacolon</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:6" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Fisiopatologia megacolon" src="https://cdn.slidesharecdn.com/ss_thumbnails/fisiopatologiamegacolon-160805154644-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Fisiopatologia megacolon" src="https://cdn.slidesharecdn.com/ss_thumbnails/fisiopatologiamegacolon-160805154644-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Fisiopatologia megacolon</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Fisiopatologia megacolon for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dktj9kf6:" popovertarget=":R1dktj9kf6:" style="anchor-name:--popover-R1dktj9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dktj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dktj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/SharonQuimis">Sharon Quimis</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">La enfermedad de Hirschsprung causa que los neuroblastos primitivos no migren correctamente durante el desarrollo fetal, dejando un segmento del intestino sin ganglios nerviosos. Esto altera la motilidad intestinal y causa obstrucción, afectando comúnmente el colon sigmoides en un 75% de los casos. Las anomalías anatómicas en la inervación producen diversos grados de obstrucción funcional intestinal debido a la pérdida de la motilidad coordinada y la relajación eficiente del intestino.</span></div></div><div class="" id=":R4tj9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4tj9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-7" aria-haspopup="dialog" aria-controls=":R51j9kf6:" popovertarget=":R51j9kf6:" style="anchor-name:--popover-R51j9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/eu-rtbf-criteria/42224251"><span class="sr-only">Eu rtbf criteria</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:7" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Eu rtbf criteria" src="https://cdn.slidesharecdn.com/ss_thumbnails/eurtbfcriteria-141201111411-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Eu rtbf criteria" src="https://cdn.slidesharecdn.com/ss_thumbnails/eurtbfcriteria-141201111411-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Eu rtbf criteria</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Eu rtbf criteria for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl1j9kf6:" popovertarget=":R1dl1j9kf6:" style="anchor-name:--popover-R1dl1j9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl1j9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl1j9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/gesterling">Greg Sterling</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document provides guidelines for implementing a European Court of Justice ruling regarding a person's right to request removal of search engine links to personal information. It summarizes that search engines are data controllers subject to EU data protection law. When a search is done by name, the search engine processing can significantly affect privacy rights by enabling users to compile an extensive profile about a person. The rights of the data subject generally take priority over the economic interests of the search engine or public's interest in the information. National data protection authorities will consider various criteria on a case-by-case basis when evaluating removal requests.</span></div></div><div class="" id=":R51j9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R51j9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-8" aria-haspopup="dialog" aria-controls=":R55j9kf6:" popovertarget=":R55j9kf6:" style="anchor-name:--popover-R55j9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/torontomagazinefooddrinkissue-62917413/62917413"><span class="sr-only">toronto-magazine-food-drink-issue</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:8" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="toronto-magazine-food-drink-issue" src="https://cdn.slidesharecdn.com/ss_thumbnails/0a00ef9f-e82a-4d91-9bc8-5f0d0488e793-160610031806-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="toronto-magazine-food-drink-issue" src="https://cdn.slidesharecdn.com/ss_thumbnails/0a00ef9f-e82a-4d91-9bc8-5f0d0488e793-160610031806-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">toronto-magazine-food-drink-issue</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save toronto-magazine-food-drink-issue for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl5j9kf6:" popovertarget=":R1dl5j9kf6:" style="anchor-name:--popover-R1dl5j9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl5j9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl5j9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/YukiHayashi5">Yuki Hayashi</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document is a magazine article promoting Toronto's food and drink scene. It provides information on various culinary festivals in Toronto including Taste of Toronto, Toronto Food & Wine Festival, Summerlicious, Toronto Beer Week, and the Gourmet Food & Wine Expo. It also profiles the city's thriving brunch culture and provides recommendations for top brunch spots such as Mildred's Temple Kitchen, Rose and Sons, Saving Grace, and Lady Marmalade. The article highlights Toronto's growing maple water trend and includes a recipe for maple coffee. It concludes by sharing chef Christina Tosi's favorite Toronto restaurants - Dumpling House and Buca.</span></div></div><div class="" id=":R55j9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R55j9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-9" aria-haspopup="dialog" aria-controls=":R59j9kf6:" popovertarget=":R59j9kf6:" style="anchor-name:--popover-R59j9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/p2-colem/9856858"><span class="sr-only">P2 colem</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:9" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="P2 colem" src="https://cdn.slidesharecdn.com/ss_thumbnails/p2colem-111024080924-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="P2 colem" src="https://cdn.slidesharecdn.com/ss_thumbnails/p2colem-111024080924-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">P2 colem</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save P2 colem for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl9j9kf6:" popovertarget=":R1dl9j9kf6:" style="anchor-name:--popover-R1dl9j9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl9j9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl9j9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/worldcultures6">worldcultures6</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document describes various Mayan-themed products for sale, including a luxury bed modeled after those of Mayan kings, a shower faucet inspired by the rain god Chac, herbal medicine based on the goddess Ix Chel, and a toy bird that mimics the real quetzal. Prices range from $13.99 for a pocket calendar to $5,000 for a jewelry-encrusted good luck charm. The products are aimed at commemorating Mayan culture and mythology.</span></div></div><div class="" id=":R59j9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R59j9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-10"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/2016-sfu-pregame/66818865"><span class="sr-only">2016 SFU Pre-Game</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:10" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="2016 SFU Pre-Game" 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style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dlhj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dlhj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ShaneCasey3">Shane Casey</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document is a collection of photos with attribution credits. Most of the photos are credited to various photographers on Flickr and have Creative Commons licenses attached. There are also a few photos credited to Shane Casey without additional details provided. The document also includes one quote from Shigeru Miyamoto about players being artists within games.</span></div></div><div class="" id=":R5hj9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5hj9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-12" aria-haspopup="dialog" aria-controls=":R5lj9kf6:" popovertarget=":R5lj9kf6:" style="anchor-name:--popover-R5lj9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/affordable-care-act-presentation-for-state-library-of-ohio/25716080"><span class="sr-only">Affordable Care Act Presentation for State Library of Ohio</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:12" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Affordable Care Act Presentation for State Library of Ohio" src="https://cdn.slidesharecdn.com/ss_thumbnails/acapresentationforstatelibrarywaudio-130829073823-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Affordable Care Act Presentation for State Library of Ohio" src="https://cdn.slidesharecdn.com/ss_thumbnails/acapresentationforstatelibrarywaudio-130829073823-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Affordable Care Act Presentation for State Library of Ohio</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Affordable Care Act Presentation for State Library of Ohio for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dllj9kf6:" popovertarget=":R1dllj9kf6:" style="anchor-name:--popover-R1dllj9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dllj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dllj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/DonBoozer">Don Boozer</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses considerations for librarians assisting patrons with implementation of the Affordable Care Act. It emphasizes the importance of protecting patron privacy, having difficult yet tactful conversations, and knowing where to draw the line in terms of advice. Librarians should familiarize themselves with ACA resources, maintain patron confidentiality, and approach questions with common sense, discretion and sensitivity. The goal is to provide authoritative information to patrons while observing ethical standards of privacy and neutrality.</span></div></div><div class="" id=":R5lj9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5lj9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-13" aria-haspopup="dialog" aria-controls=":R5pj9kf6:" popovertarget=":R5pj9kf6:" style="anchor-name:--popover-R5pj9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/empire-marquee-catalog/66850424"><span class="sr-only">Empire marquee catalog</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:13" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Empire marquee catalog" src="https://cdn.slidesharecdn.com/ss_thumbnails/db539721-5810-417f-b89b-379b4386f9fa-161007094721-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Empire marquee catalog" src="https://cdn.slidesharecdn.com/ss_thumbnails/db539721-5810-417f-b89b-379b4386f9fa-161007094721-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Empire marquee catalog</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Empire marquee catalog for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dlpj9kf6:" popovertarget=":R1dlpj9kf6:" style="anchor-name:--popover-R1dlpj9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dlpj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dlpj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/EmpireMarqueePvtLtd">Empire Marquee Pvt Ltd</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document provides contact information for Empire Marquee, a company that rents out tents and event equipment. It lists the company's address, phone numbers, emails, and social media links. It then summarizes the types of tents and equipment available, including party tents, wedding tents, pagoda tents, gazebo tents, car parking shades, and event design and management services. The document emphasizes that Empire Marquee can provide the right size tent or equipment for events of any size.</span></div></div><div class="" id=":R5pj9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5pj9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-14" aria-haspopup="dialog" aria-controls=":R5tj9kf6:" popovertarget=":R5tj9kf6:" style="anchor-name:--popover-R5tj9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/abortion-quick-facts/5760112"><span class="sr-only">Abortion quick facts</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:14" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Abortion quick facts" src="https://cdn.slidesharecdn.com/ss_thumbnails/abortionquickfacts-101112171507-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Abortion quick facts" src="https://cdn.slidesharecdn.com/ss_thumbnails/abortionquickfacts-101112171507-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Abortion quick facts</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Abortion quick facts for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dltj9kf6:" popovertarget=":R1dltj9kf6:" style="anchor-name:--popover-R1dltj9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dltj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dltj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ahmedbashu">Fakru Bashu</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">1. The document discusses several topics related to pregnancies resulting from rape and incest, including reliable estimates of such pregnancies, reasons why they result in lower rates of pregnancy, perspectives on allowing abortion in these cases, and testimony from victims. 2. Statistics on the percentage of abortions performed for rape and incest are provided, estimated to be 1.5% and 0.5% respectively. However, these numbers are disputed by some as not being based on reliable evidence. 3. Arguments presented against allowing abortion for rape and incest include that the unborn child is innocent and does not deserve to die for the crimes of the father, and that abortion can harm the emotional and psychological health of the woman. Vict</span></div></div><div class="" id=":R5tj9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5tj9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-15" aria-haspopup="dialog" aria-controls=":R61j9kf6:" popovertarget=":R61j9kf6:" style="anchor-name:--popover-R61j9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/1e-cp-house-refurbishment/5758924"><span class="sr-only">1E - CP House Refurbishment</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:15" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="1E - CP House Refurbishment" src="https://cdn.slidesharecdn.com/ss_thumbnails/1e-cphouserefurbishment-101112141706-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="1E - CP House Refurbishment" src="https://cdn.slidesharecdn.com/ss_thumbnails/1e-cphouserefurbishment-101112141706-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">1E - CP House Refurbishment</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save 1E - CP House Refurbishment for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dm1j9kf6:" popovertarget=":R1dm1j9kf6:" style="anchor-name:--popover-R1dm1j9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dm1j9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dm1j9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/1eNews">1E: Software Lifecycle Automation</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Our UK offices have been in disarray for far too long while we’ve made adjustments, changes, and improvements to compliment our growing company! Our refurbishment is finally complete and we’re loving the improved space. We hope you love it, too!</span></div></div><div class="" id=":R61j9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R61j9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-16"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/pr-3013/16840385"><span class="sr-only">Pr агентства аиа 3013</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:16" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Pr агентства аиа 3013" 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slideshow-card" aria-describedby="alsoLiked-card-description-17" aria-haspopup="dialog" aria-controls=":R69j9kf6:" popovertarget=":R69j9kf6:" style="anchor-name:--popover-R69j9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/adameva/biblioteca-din-alexandria"><span class="sr-only">Biblioteca Din Alexandria</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:17" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Biblioteca Din Alexandria" src="https://cdn.slidesharecdn.com/ss_thumbnails/bibliotecadinalexandria-091226172732-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Biblioteca Din Alexandria" src="https://cdn.slidesharecdn.com/ss_thumbnails/bibliotecadinalexandria-091226172732-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Biblioteca Din Alexandria</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Biblioteca Din Alexandria for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dm9j9kf6:" popovertarget=":R1dm9j9kf6:" style="anchor-name:--popover-R1dm9j9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dm9j9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dm9j9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/adameva">adam eva</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses the new senior vice president of the Alexandria Library. It instructs readers to turn on their speakers but provides no additional details about the new SVP or their responsibilities. The document contains repetitive blank lines that do not convey meaningful information.</span></div></div><div class="" id=":R69j9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R69j9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-18" aria-haspopup="dialog" aria-controls=":R6dj9kf6:" popovertarget=":R6dj9kf6:" style="anchor-name:--popover-R6dj9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/combicut-djnc-accessories/2029810"><span class="sr-only">Combicut DJ/NC Accessories</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:18" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Combicut DJ/NC Accessories" src="https://cdn.slidesharecdn.com/ss_thumbnails/djnccombicutaccessories-090921071606-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Combicut DJ/NC Accessories" src="https://cdn.slidesharecdn.com/ss_thumbnails/djnccombicutaccessories-090921071606-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Combicut DJ/NC Accessories</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Combicut DJ/NC Accessories for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dmdj9kf6:" popovertarget=":R1dmdj9kf6:" style="anchor-name:--popover-R1dmdj9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dmdj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dmdj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/Breton_machines">Breton SpA</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">1. 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href="https://www.slideshare.net/slideshow/b-mos-transistor-fabrication-problem/16994087"><span class="sr-only">B )mos transistor fabrication problem</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:0" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="B )mos transistor fabrication problem" src="https://cdn.slidesharecdn.com/ss_thumbnails/bmostransistorfabricationproblem-130306231358-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="B )mos transistor fabrication problem" src="https://cdn.slidesharecdn.com/ss_thumbnails/bmostransistorfabricationproblem-130306231358-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">B )mos transistor fabrication problem</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save B )mos transistor fabrication problem for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dk5jpkf6:" popovertarget=":R1dk5jpkf6:" style="anchor-name:--popover-R1dk5jpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dk5jpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dk5jpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/virussalona">Viruss Alona</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses CMOS transistor fabrication and scaling. It addresses two key problems with CMOS operation: latch-up and parasitic capacitance. Latch-up can permanently damage transistors, while parasitic capacitance limits high frequency performance. Methods to overcome these issues include latch-up protection circuits, increasing distances between wells/junctions, and partially disconnecting parasitic devices from ground terminals. CMOS technologies like P-well, N-well, and SOI were compared in terms of mitigating latch-up and parasitic capacitance. The document also covers MOS scaling theory and its impacts on circuit performance and power consumption over time as feature sizes decreased from submicron to deep submicron to nanotechnology levels.</span></div></div><div class="" id=":R45jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R45jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-1" aria-haspopup="dialog" aria-controls=":R49jpkf6:" popovertarget=":R49jpkf6:" style="anchor-name:--popover-R49jpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-interview-questions1/25943220"><span class="sr-only">Vlsi interview questions1</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:1" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Vlsi interview questions1" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsiinterviewquestions1-130905223534--thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Vlsi interview questions1" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsiinterviewquestions1-130905223534--thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Vlsi interview questions1</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Vlsi interview questions1 for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dk9jpkf6:" popovertarget=":R1dk9jpkf6:" style="anchor-name:--popover-R1dk9jpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dk9jpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dk9jpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/sukeshprathap">SUKESH Prathap</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document contains interview questions and answers related to CMOS design. Some key topics covered include: 1. Latch-up and how it can permanently damage a device due to excessive current flow. 2. NAND gates are preferred over NOR gates in fabrication due to higher electron mobility and lower gate leakage in NAND structures. 3. Noise margin is the minimum amount of noise that can be allowed on the input without affecting the output.</span></div></div><div class="" id=":R49jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R49jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-2" aria-haspopup="dialog" aria-controls=":R4djpkf6:" popovertarget=":R4djpkf6:" style="anchor-name:--popover-R4djpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/cmos-vlsi-design/5328783"><span class="sr-only">CMOS VLSI design</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:2" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="CMOS VLSI design" src="https://cdn.slidesharecdn.com/ss_thumbnails/piyush-100930205645-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="CMOS VLSI design" src="https://cdn.slidesharecdn.com/ss_thumbnails/piyush-100930205645-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">CMOS VLSI design</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save CMOS VLSI design for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkdjpkf6:" popovertarget=":R1dkdjpkf6:" style="anchor-name:--popover-R1dkdjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkdjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkdjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/RajanKumar1">Rajan Kumar</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses CMOS VLSI design technology and future trends. It provides an overview of CMOS technology and basic MOSFET operation. It then discusses how nanotechnology and integrated tri-gate transistors can help address limitations of CMOS scaling by reducing feature sizes and parasitic leakage. The document concludes that continued CMOS scaling will eventually be limited and alternatives like nanotechnology may be needed to retain device characteristics at smaller sizes.</span></div></div><div class="" id=":R4djpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4djpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-3" aria-haspopup="dialog" aria-controls=":R4hjpkf6:" popovertarget=":R4hjpkf6:" style="anchor-name:--popover-R4hjpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/proximity-effect/47337922"><span class="sr-only">Proximity effect</span></a><div class="slideshow-thumbnail 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class="seo-only">theory about Facility Electrical Losses: Proximity Effect, Skin Effect, and Eddy Current Losses and calculations with full illustrations</span></div></div><div class="" id=":R4hjpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4hjpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-4" aria-haspopup="dialog" aria-controls=":R4ljpkf6:" popovertarget=":R4ljpkf6:" style="anchor-name:--popover-R4ljpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/my-vlsipptx/255536378"><span class="sr-only">My VLSI.pptx</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:4" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="My VLSI.pptx" src="https://cdn.slidesharecdn.com/ss_thumbnails/myvlsi-230126132649-ea1decc1-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="My VLSI.pptx" src="https://cdn.slidesharecdn.com/ss_thumbnails/myvlsi-230126132649-ea1decc1-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">My VLSI.pptx</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save My VLSI.pptx for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkljpkf6:" popovertarget=":R1dkljpkf6:" style="anchor-name:--popover-R1dkljpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkljpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkljpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/chiranjeevimuppala2">chiranjeevimuppala2</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document provides an overview of VLSI design and MOS transistors. It discusses the basic steps of IC fabrication for PMOS, NMOS, CMOS, and BiCMOS processes. It also covers MOS transistor switches, including the MOSFET, transmission gate, and pass transistor logic. The document then examines the basic electrical properties of MOS and BiCMOS circuits, such as threshold voltage, body effect, and Ids-Vds relationships. It provides details on SOI fabrication processes and compares CMOS to bipolar technologies.</span></div></div><div class="" id=":R4ljpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4ljpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-5" aria-haspopup="dialog" aria-controls=":R4pjpkf6:" popovertarget=":R4pjpkf6:" style="anchor-name:--popover-R4pjpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/analog-and-digital-circuit-design-in-65-nm-cmos-end-of-the-roaddocx/267038511"><span class="sr-only">Analog and digital circuit design in 65 nm CMOS end of the road.docx</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:5" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Analog and digital circuit design in 65 nm CMOS end of the road.docx" src="https://cdn.slidesharecdn.com/ss_thumbnails/analoganddigitalcircuitdesignin65nmcmosendoftheroad-240331104703-89c6aae7-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Analog and digital circuit design in 65 nm CMOS end of the road.docx" src="https://cdn.slidesharecdn.com/ss_thumbnails/analoganddigitalcircuitdesignin65nmcmosendoftheroad-240331104703-89c6aae7-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Analog and digital circuit design in 65 nm CMOS end of the road.docx</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Analog and digital circuit design in 65 nm CMOS end of the road.docx for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkpjpkf6:" popovertarget=":R1dkpjpkf6:" style="anchor-name:--popover-R1dkpjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkpjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkpjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ZHKhan15">ZHKhan15</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document summarizes challenges in analog and digital circuit design for 65nm CMOS technology. It discusses how leakage currents, process variability, and interconnect delays increase as technologies scale down, posing new problems. A panel of experts will discuss whether 65nm marks the "end of the road" for continued design benefits from technology scaling or if issues can be addressed.</span></div></div><div class="" id=":R4pjpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4pjpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-6" aria-haspopup="dialog" aria-controls=":R4tjpkf6:" popovertarget=":R4tjpkf6:" style="anchor-name:--popover-R4tjpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/w04406104107/35249814"><span class="sr-only">W04406104107</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K 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open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.</span></div></div><div class="" id=":R4tjpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4tjpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-7" aria-haspopup="dialog" aria-controls=":R51jpkf6:" popovertarget=":R51jpkf6:" style="anchor-name:--popover-R51jpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/a0810105/34424416"><span class="sr-only">Design of Nanoscale 3-T DRAM using FinFET</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:7" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Design of Nanoscale 3-T DRAM using FinFET" src="https://cdn.slidesharecdn.com/ss_thumbnails/a0810105-140508014508-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Design of Nanoscale 3-T DRAM using FinFET" src="https://cdn.slidesharecdn.com/ss_thumbnails/a0810105-140508014508-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Design of Nanoscale 3-T DRAM using FinFET</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Design of Nanoscale 3-T DRAM using FinFET for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl1jpkf6:" popovertarget=":R1dl1jpkf6:" style="anchor-name:--popover-R1dl1jpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl1jpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl1jpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/IOSR">IOSR Journals</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document describes the design of a 3-transistor (3T) dynamic random access memory (DRAM) cell using both CMOS and FinFET technologies at the 32nm node. Simulation results show that the FinFET-based DRAM cell has lower average power (9.5136uW vs 10.869uW), lower power dissipation (144.7353uW vs 235.2313uW), and much lower leakage power (2.4303nW vs 1.8781uW) compared to the CMOS-based cell. FinFET devices are able to better control short channel effects at small scales compared to planar CMOS, enabling lower power DRAM designs. The document provides</span></div></div><div class="" id=":R51jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R51jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-8" aria-haspopup="dialog" aria-controls=":R55jpkf6:" popovertarget=":R55jpkf6:" style="anchor-name:--popover-R55jpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/printed-circuit-board-design-techniques-for-emc-compliance202402201451050000pdf/266873472"><span class="sr-only">Printed Circuit Board Design Techniques for EMC Compliance_20240220_145105_00...</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:8" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Printed Circuit Board Design Techniques for EMC Compliance_20240220_145105_00..." src="https://cdn.slidesharecdn.com/ss_thumbnails/printedcircuitboarddesigntechniquesforemccompliance202402201451050000-240319221459-0c65d3f0-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Printed Circuit Board Design Techniques for EMC Compliance_20240220_145105_00..." src="https://cdn.slidesharecdn.com/ss_thumbnails/printedcircuitboarddesigntechniquesforemccompliance202402201451050000-240319221459-0c65d3f0-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Printed Circuit Board Design Techniques for EMC Compliance_20240220_145105_00...</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Printed Circuit Board Design Techniques for EMC Compliance_20240220_145105_00... for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl5jpkf6:" popovertarget=":R1dl5jpkf6:" style="anchor-name:--popover-R1dl5jpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl5jpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl5jpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/AlanGustavo13">AlanGustavo13</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Key ways to ensure the purity of the power distribution system in a PCB design include: 1. Controlling the impedance and capacitive loading of each trace path to maintain signal integrity and minimize interference. 2. Maintaining the purity of the power and ground planes by preventing switching noise, externally induced RF fields, surge events, and other interference. 3. Using board materials with low dielectric constants to allow for faster signal propagation speeds and reduced capacitance in trace paths. 4. Minimizing crosstalk and interference through strategic design of signal and power paths.</span></div></div><div class="" id=":R55jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R55jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-9" aria-haspopup="dialog" aria-controls=":R59jpkf6:" popovertarget=":R59jpkf6:" style="anchor-name:--popover-R59jpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/04inter-phase-spacers/47062091"><span class="sr-only">INTER PHASE SPACERS </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:9" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="INTER PHASE SPACERS " src="https://cdn.slidesharecdn.com/ss_thumbnails/04-150416041802-conversion-gate02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="INTER PHASE SPACERS " src="https://cdn.slidesharecdn.com/ss_thumbnails/04-150416041802-conversion-gate02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">INTER PHASE SPACERS </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save INTER PHASE SPACERS for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl9jpkf6:" popovertarget=":R1dl9jpkf6:" style="anchor-name:--popover-R1dl9jpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl9jpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl9jpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/HarishAgarwal3">Harish Agarwal</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Composite inter phase separators have a great role to play to compact the lines and avoid flash-overs & short circuits resulting from conductor swing and galloping.</span></div></div><div class="" id=":R59jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R59jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-10" aria-haspopup="dialog" aria-controls=":R5djpkf6:" popovertarget=":R5djpkf6:" style="anchor-name:--popover-R5djpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/i501045562/44375591"><span class="sr-only">IR Drop Analysis and Its Reduction Techniques in Deep Submicron Technology</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:10" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="IR Drop Analysis and Its Reduction Techniques in Deep Submicron Technology" src="https://cdn.slidesharecdn.com/ss_thumbnails/i501045562-150207004243-conversion-gate02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="IR Drop Analysis and Its Reduction Techniques in Deep Submicron Technology" src="https://cdn.slidesharecdn.com/ss_thumbnails/i501045562-150207004243-conversion-gate02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">IR Drop Analysis and Its Reduction Techniques in Deep Submicron Technology</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save IR Drop Analysis and Its Reduction Techniques in Deep Submicron Technology for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dldjpkf6:" popovertarget=":R1dldjpkf6:" style="anchor-name:--popover-R1dldjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dldjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dldjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ijeraeditor">IJERA Editor</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This paper presents a detailed conceptual analysis of IR Drop effect in deep submicron technologies and its reduction techniques. The IR Drop effect in power/ground network increases rapidly with technology scaling. This affects the timing of the design and hence the desired speed. It is shown that in present day designs, using well known reduction techniques such as wire sizing and decoupling capacitor insertion, may not be sufficient to limit the voltage fluctuations and hence, two more important methods such as selective glitch reduction technique and IR Drop reduction through combinational circuit partitioning are discussed and the issues related to all the techniques are revised.</span></div></div><div class="" id=":R5djpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5djpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-11" aria-haspopup="dialog" aria-controls=":R5hjpkf6:" popovertarget=":R5hjpkf6:" style="anchor-name:--popover-R5hjpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/d503051619/46972470"><span class="sr-only">Structural and Electrical Analysis of Various MOSFET Designs</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:11" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Structural and Electrical Analysis of Various MOSFET Designs" src="https://cdn.slidesharecdn.com/ss_thumbnails/d503051619-150414043856-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Structural and Electrical Analysis of Various MOSFET Designs" src="https://cdn.slidesharecdn.com/ss_thumbnails/d503051619-150414043856-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Structural and Electrical Analysis of Various MOSFET Designs</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Structural and Electrical Analysis of Various MOSFET Designs for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dlhjpkf6:" popovertarget=":R1dlhjpkf6:" style="anchor-name:--popover-R1dlhjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dlhjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dlhjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ijeraeditor">IJERA Editor</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Invention of Transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key to the development of nano electronics technology. This paper offers a brief review of some of the most popular MOSFET structure designs. The scaling down of planar bulk MOSFET proposed by the Moore’s Law has been saturated due to short channel effects and DIBL. Due to this alternative approaches has been considered to overcome the problems at lower node technology. SOI and FinFET technologies are promising candidates in this area.</span></div></div><div class="" id=":R5hjpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5hjpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-12" aria-haspopup="dialog" aria-controls=":R5ljpkf6:" popovertarget=":R5ljpkf6:" style="anchor-name:--popover-R5ljpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/JazzSameer/18ec655module1pptx"><span class="sr-only">18EC655_Module-1.pptx</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:12" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="18EC655_Module-1.pptx" src="https://cdn.slidesharecdn.com/ss_thumbnails/18ec655module-1-230708131457-5c822193-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="18EC655_Module-1.pptx" src="https://cdn.slidesharecdn.com/ss_thumbnails/18ec655module-1-230708131457-5c822193-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">18EC655_Module-1.pptx</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save 18EC655_Module-1.pptx for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dlljpkf6:" popovertarget=":R1dlljpkf6:" style="anchor-name:--popover-R1dlljpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dlljpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dlljpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/JazzSameer">JazzSameer</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses basic concepts in VLSI design including: - The history and progression of integrated circuit generations from SSI to VLSI to ULSI. - The basic operation and types (enhancement vs depletion, NMOS vs PMOS) of MOS transistors. - Fabrication processes for CMOS, including masks, diffusion, deposition of oxide and polysilicon layers. - Threshold voltage and factors that determine it such as oxide thickness and charges at interfaces.</span></div></div><div class="" id=":R5ljpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5ljpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-13" aria-haspopup="dialog" aria-controls=":R5pjpkf6:" popovertarget=":R5pjpkf6:" style="anchor-name:--popover-R5pjpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/RoslinaShariff/pvc-cmos-finale"><span class="sr-only">Pvc cmos finale </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:13" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Pvc cmos finale " src="https://cdn.slidesharecdn.com/ss_thumbnails/pvccmosfinale190415paklahfinale-180305040729-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Pvc cmos finale " src="https://cdn.slidesharecdn.com/ss_thumbnails/pvccmosfinale190415paklahfinale-180305040729-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Pvc cmos finale </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Pvc cmos finale for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dlpjpkf6:" popovertarget=":R1dlpjpkf6:" style="anchor-name:--popover-R1dlpjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dlpjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dlpjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/RoslinaShariff">Roslina Shariff</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document provides an introduction and background on Complementary Metal Oxide Semiconductor (CMOS) technology. It discusses key components of a CMOS circuit including NMOS, PMOS, photolithography, etching, chemical mechanical planarization, shallow trench isolation, contacts, vias, and interlayer dielectrics. The objectives of the project are to identify defects in a defective CMOS sample using electrical testing, scanning laser optical microscopy, passive voltage contrast under SEM, and focused ion beam with EDX to determine the root cause of the defect.</span></div></div><div class="" id=":R5pjpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5pjpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-14" aria-haspopup="dialog" aria-controls=":R5tjpkf6:" popovertarget=":R5tjpkf6:" style="anchor-name:--popover-R5tjpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/nanometer-layout-handbook-at-high-speed-design/76971943"><span class="sr-only">Nanometer layout handbook at high speed design</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:14" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Nanometer layout handbook at high speed design" src="https://cdn.slidesharecdn.com/ss_thumbnails/nanometerlayouthandbookathighspeeddesign-170615123243-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Nanometer layout handbook at high speed design" src="https://cdn.slidesharecdn.com/ss_thumbnails/nanometerlayouthandbookathighspeeddesign-170615123243-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Nanometer layout handbook at high speed design</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Nanometer layout handbook at high speed design for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dltjpkf6:" popovertarget=":R1dltjpkf6:" style="anchor-name:--popover-R1dltjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dltjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dltjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/MinhoPark25">Minho Park</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">I made this contents for whom is about to layout own's IC design. I think it would be helpful to consider layouts about high speed Rx / Tx. Specially it was aimed giga hertz bandwidth I/O with its ESD protection (I am still working on that items to rearrange with my knowledge to my experiences) I showed up all references and all images (except originals) are belong to own's copy rights.</span></div></div><div class="" id=":R5tjpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5tjpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-15" aria-haspopup="dialog" aria-controls=":R61jpkf6:" popovertarget=":R61jpkf6:" style="anchor-name:--popover-R61jpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/extended-abstract-adam-moreau/64819483"><span class="sr-only">Extended Abstract - Adam Moreau</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:15" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Extended Abstract - Adam Moreau" src="https://cdn.slidesharecdn.com/ss_thumbnails/df5d5815-28f5-4228-bc14-42825c98e02f-160809025337-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Extended Abstract - Adam Moreau" src="https://cdn.slidesharecdn.com/ss_thumbnails/df5d5815-28f5-4228-bc14-42825c98e02f-160809025337-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Extended Abstract - Adam Moreau</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Extended Abstract - Adam Moreau for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dm1jpkf6:" popovertarget=":R1dm1jpkf6:" style="anchor-name:--popover-R1dm1jpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dm1jpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dm1jpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/AdamMoreau">Adam Moreau</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document summarizes research into designing a piezoelectric-actuated mirror mount with a servo bandwidth greater than 380kHz. Four different mount designs were tested: a cylindrical control mount and three designs intended to dampen mechanical resonances - a solid center of mass design, a design with a 0.125" tungsten-carbide core, and a design with a 0.25" tungsten-carbide core. Testing showed the thickness of the adhesive layer and mount material most affected resonance frequency. The optimal design was found to be a 0.25" tungsten-carbide filled brass mount, achieving a 392kHz servo bandwidth.</span></div></div><div class="" id=":R61jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R61jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-16" aria-haspopup="dialog" aria-controls=":R65jpkf6:" popovertarget=":R65jpkf6:" style="anchor-name:--popover-R65jpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/wirelesspages0414/37688587"><span class="sr-only">PIM: Components, Materials, Handling & Testing</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K 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RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This issue of AWT Global's Wireless Pages describes How to measure PIM, treating low PIM components and offers information about low PIM materials.</span></div></div><div class="" id=":R65jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R65jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-17" aria-haspopup="dialog" aria-controls=":R69jpkf6:" popovertarget=":R69jpkf6:" style="anchor-name:--popover-R69jpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/nc342352340/26092580"><span class="sr-only">Nc342352340</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:17" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Nc342352340" src="https://cdn.slidesharecdn.com/ss_thumbnails/nc342352340-130911055219-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Nc342352340" src="https://cdn.slidesharecdn.com/ss_thumbnails/nc342352340-130911055219-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Nc342352340</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi 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class="seo-only">This document summarizes research on scaling limits of CMOS devices and proposed structures to overcome these limits. It first discusses how quantum mechanical effects and short channel effects become problematic as devices are scaled down, limiting further scaling. It then reviews various structures proposed by other researchers, including fully depleted SOI MOSFETs with strained silicon channels, dual material gates, and gate-all-around structures. Finally, it proposes a new structure combining these elements: a fully depleted SOI gate-all-around MOSFET using a strained silicon channel and dual material gate to address scaling challenges while improving performance.</span></div></div><div class="" id=":R69jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R69jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-18" aria-haspopup="dialog" aria-controls=":R6djpkf6:" popovertarget=":R6djpkf6:" style="anchor-name:--popover-R6djpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/b02041118/14129205"><span class="sr-only">IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:18" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="IJERD (www.ijerd.com) International Journal of Engineering Research and Devel..." src="https://cdn.slidesharecdn.com/ss_thumbnails/b02041118-120831080415-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="IJERD (www.ijerd.com) International Journal of Engineering Research and Devel..." src="https://cdn.slidesharecdn.com/ss_thumbnails/b02041118-120831080415-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save IJERD (www.ijerd.com) International Journal of Engineering Research and Devel... for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dmdjpkf6:" popovertarget=":R1dmdjpkf6:" style="anchor-name:--popover-R1dmdjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dmdjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dmdjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ijerd_editor">IJERD Editor</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document summarizes a research paper that proposes low-leakage 1-bit full adder cell designs for reducing power consumption in nanometer technologies. It introduces two modified full adder circuit designs (Design1 and Design2) that apply transistor resizing and power gating techniques. Simulation results show that the proposed designs reduce standby leakage power and active power compared to a conventional 28-transistor CMOS full adder. Design1 sizes transistors with a 3.17x PMOS-to-NMOS ratio while Design2 uses a 1.5x ratio. Both aim to minimize area and leakage through optimized transistor widths and lengths.</span></div></div><div class="" id=":R6djpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R6djpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="similarTo-card-description-19" aria-haspopup="dialog" aria-controls=":R6hjpkf6:" popovertarget=":R6hjpkf6:" style="anchor-name:--popover-R6hjpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/ultra-high-speed-factorial-design-in-subnanometer-technology/86508427"><span class="sr-only">ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:19" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY" src="https://cdn.slidesharecdn.com/ss_thumbnails/csit3229-180122091617-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY" src="https://cdn.slidesharecdn.com/ss_thumbnails/csit3229-180122091617-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dmhjpkf6:" popovertarget=":R1dmhjpkf6:" style="anchor-name:--popover-R1dmhjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dmhjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dmhjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/cscpconf">cscpconf</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This work proposes a high speed and low power factorial design in 22nm technology and also it counts the effect of sub nano-meter constraints on this circuit. A comparative study for this design has been done for 90nm, 45nm and 22nm technology. The rise in circuit complexity and speed is accompanied by the scaling of MOSFET’s. The transistor saturation current Idsat is an important parameter because the transistor current determines the time needed to charge and discharge the capacitive loads on chip, and thus impacts the product speed more than any other transistor parameter. The efficient implementation of a factorial number is carried out by using a decremented and multipliers which has been lucidly discussed in this paper. Normally in a factorial module a number is calculated as the iterative multiplication of the given number to the decremented value of the given number. A Parallel adder based decremented has been proposed for calculating the factorial of any number that also includes 0 and 1. The performances are calculated by using the existing 90-nm CMOS technology and scaling down the existing technology to 45-nm and 22-nm. </span></div></div><div class="" id=":R6hjpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R6hjpkf6"></div></div><div class="desktop-recs"><div class="Slider_root__c0Jo8"><div class="Slider_scroller__KHjw4"><div class="BottomRecommendationCard_root__gffTk SlideshowCard_root__pD8t4 slideshow-card"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/b-mos-transistor-fabrication-problem/16994087"><span class="sr-only">B )mos transistor fabrication problem</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:16 / 9;--index:0" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="B )mos transistor fabrication problem" src="https://cdn.slidesharecdn.com/ss_thumbnails/bmostransistorfabricationproblem-130306231358-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="B )mos transistor fabrication problem" src="https://cdn.slidesharecdn.com/ss_thumbnails/bmostransistorfabricationproblem-130306231358-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">B )mos transistor fabrication problem</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save B )mos transistor fabrication problem for later" role="switch" aria-haspopup="dialog" aria-controls=":R5gmjpkf6:" popovertarget=":R5gmjpkf6:" style="anchor-name:--popover-R5gmjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5gmjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5gmjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/virussalona">Viruss Alona</a><div class="slideshow-stats SlideshowStats_root__EQOR1"> </div></div></div><div class="BottomRecommendationCard_root__gffTk SlideshowCard_root__pD8t4 slideshow-card"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" 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type="button" class="Slider_arrow__8LCca Slider_next__fa9IO"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/chevron-right.9b30ad08.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button></div></div></div></div><div id="between-recs-ad-2-container" class="freestar-ad-container FreestarAdContainer_root__qPPC_" style="--fallback-aspect-ratio:undefined / undefined" data-testid="freestar-ad-container"><div><div class="" id="between-recs-ad-2"></div></div></div></div></div><div class="Transcript_root__Vrf6Q"><h2 class="Transcript_title__YgAka"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/file.5db1ba24.svg);background-color:currentColor"></span><span class="sr-only"></span></span>Nmi Presentation Sept 2007</h2><div><ul class="Transcript_list__faItj"><div><li>1. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/AdrianOShaughnessy/nmi-presentation-sept-2007#1">NMI Presentation Notes </a> 12th September 2007 IC Mask Design Limited Unit 12G Maynooth Business Campus Maynooth, Co. Kildare, Ireland. Topics: 1. Analog Layout at 90 nanometer 2. RF Layout at 90 nanometer Analog Layout at 90 nanometer There are various challages in Analog layout at 90 nanometer.The topics for discussion are:  Shallow Trench Isolation Stress (STI)  Well Proximity Effect (WPE) RF Layout at 90 nanometer As frequencies increase, with some CMOS circuits operating in the RF range, layout quality has a larger influence on circuit perfomance. The topics for discussion are:  Interconnect  Interconnect Parasitics  Device Parasitics  Understanding and optimising device parasitics ICMaskDesign Adrian O'Shaughnessy </li></div><div><li>2. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/AdrianOShaughnessy/nmi-presentation-sept-2007#2">STI So what exactly </a> is it? STI is a technique to electrically isolate mos transistors from each other. LOCUS (local oxidation of silicon) was the technique used previous to this. Basically this involved growing a thick pad of oxide between adjacent devices. The problem with it really was scalability. As geometries were getting smaller it wasn't really an option, so Shallow Trench Isolation was introduced. This involved etching out a shallow trench into the substrate between devices and then filling with an oxide. So why is it so important that we understand it? Basically if STI isn't taking into account it can lead to circuit failure. So the designer has to be aware of it and most importantly the layout engineer has to understand and know how to deal with it. So what problems does it introduce? The STI process stresses the mos transistors which can lead to a degradation or variation in performance. So this can affect things like matching. If your current mirror is experiencing a variation across it's transistors then they won't be matched and offsets could be introduced. Worse still will be that the current output will be much less than expected so things like biasing currents could be affected. So how does it stress the mos transistors? First of all when the trench is etched into the substrate this will cause some mechanical stress. In other words the silicon itself will experience stress and the degree of stress that the transistor experiences is related to the distance of the gate to the closest STI region, that is the distance of the channel to the closest oxide. So how can we as layout engineers fix it? 1. Well we could match it. If for example in a current mirror we ensure that each transistor experiences the same STI stress then they are matched. The problem with this though is the designer has to be aware that this is the technique that we are using because this technique could result in a degradation in current output and so the designer has to allow for this in their simulations. 2. Another technique is to share regions. Here we have utilised area and we have eliminated the STI stress. The important thing to note is we that must extend the poly to active distance on the outer mos transistors. We can do this by simply drawing in the extra diffusion area or by adding in dummy devices ICMaskDesign Adrian O'Shaughnessy </li></div><div><li>3. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/AdrianOShaughnessy/nmi-presentation-sept-2007#3">WPE The Well Proximity </a> Effect is another effect that if not understood has the potential to cause circuit failure. So what is it? Basically this involves the scattering of ions (ion scattering) during the implantation of the wells. So what does this cause? The result is a well surface concentration that changes with lateral distance from the mask edge over the range of 1 micron or more. This later non-uniformity in well doping causes the MOS threshold voltages and other electrical characteristics to vary with the distance of the transistor to the well edge. In some instances Vt has been found to increase by as much as 50mV as the device moves closer to the edge. If this isn't taken into account such things as current mirrors can be shifted out of saturation leading to circuit failure. So how is it fixed? The layout engineer must insure that the mos devices either experience the same WPE effect or must ensure that there is enough of a distance from the well edge so as to negate the effects of WPE. Characterisation tests reveal that 2-5 microns should be sufficient. ICMaskDesign Adrian O'Shaughnessy </li></div><div><li>4. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/AdrianOShaughnessy/nmi-presentation-sept-2007#4">RF Layout at </a> 90 Nanometres INTRO Good layout practice at high frequencies is extremely important because bad layout can and will introduce parasitics that may result in extra current needed to drive these parasitic loads. It could also of course stop your circuit from working at all as it may limit it's frequency response. Interconnect Lets look at the parasitics that's introduced by interconnect. Every single piece of interconnect we put down will have an associated parasitic resistance. This resistance is calculated by multiplying it's sheet resistance by it's length over width – Rs * (L/W) Interconnect will also introduce different types of parasitic capacitance such as parallel plate, Fringe and cross coupling which will all have a combinational affect and create one overall parasitic capacitance. So have can we improve on the parasitic resistance? 1. Reduce Length. If we properly floorplan our blocks it should be possible to minimise the interconnect between them. 2. Increase Width. Increasing the width will reduce the number of squares. It is common for differential signals to be wider than the minimum width. 3. Use Higher Layers. Higher metals have a lower sheet resistance than lower ones therefore reducing its overall resistance. This will also have the added advantage of decreasing the capacitance to substrate. ICMaskDesign Adrian O'Shaughnessy </li></div><div><li>5. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/AdrianOShaughnessy/nmi-presentation-sept-2007#5">Device Parasitics INTRO When we </a> put down a device in layout we introduce parasitics. Simple as that. So what happens when we put down a mos device? Simple MOS Parasitics We introduce a whole host of resistive and capacitive parasitics and as a layout engineer there are some on these parasitics that can be optimised and there's some that can't. Parasitics that we can't optimise are directly related to the length of the device which we can't change. We can optimise the gate resistance by tying both ends of the poly in metal thereby connecting another resistor, in this case metal1, in parallel with in. Connecting the gate in metal will improve the resistance by 200% - 400%. We can improve the drain and source parasitic capacitance by folding the device. But which one do we optimise? This is particularly done on differential pairs. If we optimise the source area then we're optimising a region that is going to ground if it's an NMOS device. Any good? If we optimise the drain area then we're optimising the output node which in RF circuits is highly sensitive to capacitance. So it's best to optimise this. We can also improve the substrate resistance by putting in lots of well contacts. This will help prevent against latch-up and also serve as noise protection. ICMaskDesign Adrian O'Shaughnessy </li></div></ul></div></div><dialog class="Modal_root__TYkzh FullscreenModal_root__efM9m" id=":R2kf6:"><div class="Modal_wrapper__4UTGq"><div class="modal-content Modal_content__R1F4d FullscreenModal_content__bQ6mt"></div></div></dialog><div class="ad textads banner-ads banner_ads ad-unit ad-zone ad-space adsbox ads prebid" style="position:absolute;height:1px"></div><footer class="Footer_footer__N3WmV"><div class="Footer_top__y0vfl" data-testid="footer-top"><div class="Footer_links__F2xFZ"><a class="Link_root__vn3ab Link_light__mcUPh Link_size-medium__ZLo12 Link_weight-bold__me4nt" style="order:0" href="/about">About</a><a class="Link_root__vn3ab Link_light__mcUPh Link_size-medium__ZLo12 Link_weight-bold__me4nt" style="order:1" href="https://support.scribd.com/hc/en/categories/360004792932-SlideShare?userType=SlideShare">Support</a><a class="Link_root__vn3ab Link_light__mcUPh Link_size-medium__ZLo12 Link_weight-bold__me4nt" style="order:2" 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09:27:04 UTC","description":"The document discusses layout challenges at the 90nm technology node. It covers analog layout challenges including shallow trench isolation (STI) stress and well proximity effects that can degrade transistor performance. For RF layout, it discusses the importance of minimizing interconnect and device parasitics. Interconnect parasitics like resistance and capacitance can be reduced by shorter lengths, wider widths, and using higher metal layers. Device parasitics are also discussed and how optimizing the drain area of differential pairs by folding can help minimize parasitic capacitance effects.","downloadKey":"09930d3b1d52f413440f35901d2d791cdfc0925f05179a68e0205ccd02362312","editorsNotes":[],"emailShareUrl":"mailto:?subject=Check out this SlideShare document\u0026body=https://www.slideshare.net/AdrianOShaughnessy/nmi-presentation-sept-2007","extension":"pdf","facebookShareUrl":"https://facebook.com/sharer.php?u=https%3A%2F%2Fwww.slideshare.net%2FAdrianOShaughnessy%2Fnmi-presentation-sept-2007\u0026t=Nmi+Presentation+Sept+2007","genaiDescriptionCreatedAt":"2023-12-25","genaiTest":"description","id":"5443659","iframeEmbed":{"url":"https://www.slideshare.net/slideshow/embed_code/key/B5pZ1xX2MxDbN9","height":715,"width":670},"isIndexable":true,"isLikedByCurrentUser":false,"isPrivate":false,"isViewable":true,"language":"en","likes":0,"linkedinShareUrl":"https://www.linkedin.com/cws/share?url=https%3A%2F%2Fwww.slideshare.net%2FAdrianOShaughnessy%2Fnmi-presentation-sept-2007\u0026trk=SLIDESHARE","downloadCount":24,"secretUrl":"B5pZ1xX2MxDbN9","shouldShowAds":true,"slides":{"host":"https://image.slidesharecdn.com","title":"Nmi-Presentation-Sept-2007","imageLocation":"nmipresentationsept2007-12870663346649-phpapp01","imageSizes":[{"quality":85,"width":320,"format":"jpg"},{"quality":85,"width":638,"format":"jpg"},{"quality":75,"width":2048,"format":"webp"}]},"smsShareUrl":"sms:?body=Check out this SlideShare : https://www.slideshare.net/AdrianOShaughnessy/nmi-presentation-sept-2007","strippedTitle":"nmi-presentation-sept-2007","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/nmipresentationsept2007-12870663346649-phpapp01-thumbnail.jpg?width=640\u0026height=640\u0026fit=bounds","title":"Nmi Presentation Sept 2007","totalSlides":5,"transcript":["NMI Presentation Notes\n 12th September 2007\nIC Mask Design Limited\nUnit 12G Maynooth Business Campus\nMaynooth, Co. Kildare, Ireland.\n\n\nTopics:\n 1. Analog Layout at 90 nanometer\n 2. RF Layout at 90 nanometer\n\n\nAnalog Layout at 90 nanometer\nThere are various challages in Analog layout at 90 nanometer.The topics for discussion are:\n  Shallow Trench Isolation Stress (STI)\n  Well Proximity Effect (WPE)\n\n\nRF Layout at 90 nanometer\nAs frequencies increase, with some CMOS circuits operating in the RF range, layout quality has a\nlarger influence on circuit perfomance. The topics for discussion are:\n  Interconnect\n  Interconnect Parasitics\n\n  Device Parasitics\n  Understanding and optimising device parasitics\n\n\n\n\nICMaskDesign Adrian O'Shaughnessy\n ","STI\nSo what exactly is it?\n\nSTI is a technique to electrically isolate mos transistors from each other. LOCUS (local oxidation\nof silicon) was the technique used previous to this. Basically this involved growing a thick pad of\noxide between adjacent devices. The problem with it really was scalability. As geometries were\ngetting smaller it wasn't really an option, so Shallow Trench Isolation was introduced.\n\nThis involved etching out a shallow trench into the substrate between devices and then filling\nwith an oxide.\n\nSo why is it so important that we understand it?\n\nBasically if STI isn't taking into account it can lead to circuit failure. So the designer has to be\naware of it and most importantly the layout engineer has to understand and know how to deal with\nit.\n\nSo what problems does it introduce?\n\nThe STI process stresses the mos transistors which can lead to a degradation or variation in\nperformance. So this can affect things like matching. If your current mirror is experiencing a\nvariation across it's transistors then they won't be matched and offsets could be introduced.\n\nWorse still will be that the current output will be much less than expected so things like biasing\ncurrents could be affected.\n\nSo how does it stress the mos transistors?\n\nFirst of all when the trench is etched into the substrate this will cause some mechanical stress. In\nother words the silicon itself will experience stress and the degree of stress that the transistor\nexperiences is related to the distance of the gate to the closest STI region, that is the distance of the\nchannel to the closest oxide.\n\nSo how can we as layout engineers fix it?\n\n 1. Well we could match it. If for example in a current mirror we ensure that each transistor\n experiences the same STI stress then they are matched. The problem with this though is the\n designer has to be aware that this is the technique that we are using because this technique\n could result in a degradation in current output and so the designer has to allow for this in\n their simulations.\n 2. Another technique is to share regions. Here we have utilised area and we have eliminated\n the STI stress. The important thing to note is we that must extend the poly to active distance\n on the outer mos transistors. We can do this by simply drawing in the extra diffusion area or\n by adding in dummy devices\n\nICMaskDesign Adrian O'Shaughnessy\n ","WPE\n\nThe Well Proximity Effect is another effect that if not understood has the potential to cause circuit\nfailure.\n\nSo what is it?\n\nBasically this involves the scattering of ions (ion scattering) during the implantation of the wells.\n\nSo what does this cause?\n\nThe result is a well surface concentration that changes with lateral distance from the mask edge\nover the range of 1 micron or more.\n\nThis later non-uniformity in well doping causes the MOS threshold voltages and other electrical\ncharacteristics to vary with the distance of the transistor to the well edge.\n\nIn some instances Vt has been found to increase by as much as 50mV as the device moves closer to\nthe edge.\n\nIf this isn't taken into account such things as current mirrors can be shifted out of saturation leading\nto circuit failure.\n\nSo how is it fixed?\n\nThe layout engineer must insure that the mos devices either experience the same WPE effect or\nmust ensure that there is enough of a distance from the well edge so as to negate the effects of\nWPE. Characterisation tests reveal that 2-5 microns should be sufficient.\n\n\n\n\nICMaskDesign Adrian O'Shaughnessy\n ","RF Layout at 90 Nanometres\nINTRO\nGood layout practice at high frequencies is extremely important because bad layout can and will\nintroduce parasitics that may result in extra current needed to drive these parasitic loads.\n\nIt could also of course stop your circuit from working at all as it may limit it's frequency response.\n\nInterconnect\n\nLets look at the parasitics that's introduced by interconnect.\n\nEvery single piece of interconnect we put down will have an associated parasitic resistance. This\nresistance is calculated by multiplying it's sheet resistance by it's length over width – Rs * (L/W)\n\nInterconnect will also introduce different types of parasitic capacitance such as parallel plate,\nFringe and cross coupling which will all have a combinational affect and create one overall parasitic\ncapacitance.\n\nSo have can we improve on the parasitic resistance?\n\n 1. Reduce Length. If we properly floorplan our blocks it should be possible to minimise the\n interconnect between them.\n\n 2. Increase Width. Increasing the width will reduce the number of squares. It is common for\n differential signals to be wider than the minimum width.\n\n 3. Use Higher Layers. Higher metals have a lower sheet resistance than lower ones therefore\n reducing its overall resistance. This will also have the added advantage of decreasing the\n capacitance to substrate.\n\n\n\n\nICMaskDesign Adrian O'Shaughnessy\n ","Device Parasitics\n\nINTRO\n\nWhen we put down a device in layout we introduce parasitics. Simple as that. So what happens\nwhen we put down a mos device?\n\nSimple MOS Parasitics\n\nWe introduce a whole host of resistive and capacitive parasitics and as a layout engineer there\nare some on these parasitics that can be optimised and there's some that can't.\n\nParasitics that we can't optimise are directly related to the length of the device which we can't\nchange.\n\nWe can optimise the gate resistance by tying both ends of the poly in metal thereby connecting\nanother resistor, in this case metal1, in parallel with in.\n\nConnecting the gate in metal will improve the resistance by 200% - 400%.\n\nWe can improve the drain and source parasitic capacitance by folding the device. But which one do\nwe optimise? This is particularly done on differential pairs. If we optimise the source area then\nwe're optimising a region that is going to ground if it's an NMOS device. Any good?\n\nIf we optimise the drain area then we're optimising the output node which in RF circuits is highly\nsensitive to capacitance. So it's best to optimise this.\n\nWe can also improve the substrate resistance by putting in lots of well contacts. This will help\nprevent against latch-up and also serve as noise protection.\n\n\n\n\nICMaskDesign Adrian O'Shaughnessy\n "],"twitterShareUrl":"https://twitter.com/intent/tweet?via=SlideShare\u0026text=Nmi+Presentation+Sept+2007+%23analog+%23layout+https%3A%2F%2Fwww.slideshare.net%2FAdrianOShaughnessy%2Fnmi-presentation-sept-2007","type":"document","viewStats":{"views":867,"viewsFromEmbeds":105,"topEmbeds":[]},"recommendationsByLocation":{"rightRail":[{"algorithmId":"5","displayTitle":"NT_N Guard Ring Noise Analysis","isSavedByCurrentUser":false,"pageCount":13,"score":0.850235,"slideshowId":"33214012","sourceName":"cm_interact","strippedTitle":"ntn-moat-noiseanalysis","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/linkedinmoatnoiseanalysis-signed-140407045535-phpapp01-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"The purpose of this report is to provide a detailed example and analysis of a N_TN guard ring structure. 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It discusses the basic steps of IC fabrication for PMOS, NMOS, CMOS, and BiCMOS processes. It also covers MOS transistor switches, including the MOSFET, transmission gate, and pass transistor logic. The document then examines the basic electrical properties of MOS and BiCMOS circuits, such as threshold voltage, body effect, and Ids-Vds relationships. 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It discusses how leakage currents, process variability, and interconnect delays increase as technologies scale down, posing new problems. A panel of experts will discuss whether 65nm marks the \"end of the road\" for continued design benefits from technology scaling or if issues can be addressed.","tags":[],"url":"https://www.slideshare.net/slideshow/analog-and-digital-circuit-design-in-65-nm-cmos-end-of-the-roaddocx/267038511","userLogin":"ZHKhan15","userName":"ZHKhan15","viewCount":50},{"algorithmId":"3","displayTitle":"W04406104107","isSavedByCurrentUser":false,"pageCount":4,"score":0.5005,"slideshowId":"35249814","sourceName":"cm_text","strippedTitle":"w04406104107","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/w04406104107-140529023127-phpapp01-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology \u0026 science, Power Electronics, Electronics \u0026 Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing \u0026 Low Power VLSI Design etc.","tags":["ijera(www.ijera.com)international journal of engin"],"url":"https://www.slideshare.net/slideshow/w04406104107/35249814","userLogin":"ijeraeditor","userName":"IJERA Editor","viewCount":408},{"algorithmId":"3","displayTitle":"Design of Nanoscale 3-T DRAM using FinFET","isSavedByCurrentUser":false,"pageCount":5,"score":0.4998,"slideshowId":"34424416","sourceName":"cm_text","strippedTitle":"a0810105","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/a0810105-140508014508-phpapp01-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"This document describes the design of a 3-transistor (3T) dynamic random access memory (DRAM) cell using both CMOS and FinFET technologies at the 32nm node. Simulation results show that the FinFET-based DRAM cell has lower average power (9.5136uW vs 10.869uW), lower power dissipation (144.7353uW vs 235.2313uW), and much lower leakage power (2.4303nW vs 1.8781uW) compared to the CMOS-based cell. FinFET devices are able to better control short channel effects at small scales compared to planar CMOS, enabling lower power DRAM designs. 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Maintaining the purity of the power and ground planes by preventing switching noise, externally induced RF fields, surge events, and other interference. \n\n3. Using board materials with low dielectric constants to allow for faster signal propagation speeds and reduced capacitance in trace paths.\n\n4. Minimizing crosstalk and interference through strategic design of signal and power paths.","tags":["libros"],"url":"https://www.slideshare.net/slideshow/printed-circuit-board-design-techniques-for-emc-compliance202402201451050000pdf/266873472","userLogin":"AlanGustavo13","userName":"AlanGustavo13","viewCount":165},{"algorithmId":"3","displayTitle":"INTER PHASE SPACERS ","isSavedByCurrentUser":false,"pageCount":17,"score":0.4986,"slideshowId":"47062091","sourceName":"cm_text","strippedTitle":"04inter-phase-spacers","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/04-150416041802-conversion-gate02-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"Composite inter phase separators have a great role to play to compact the lines and avoid flash-overs \u0026 short circuits resulting from conductor swing and galloping.","tags":["inter phase spacers","transmission or distribution","cable connector"],"url":"https://www.slideshare.net/slideshow/04inter-phase-spacers/47062091","userLogin":"HarishAgarwal3","userName":"Harish Agarwal","viewCount":1704},{"algorithmId":"3","displayTitle":"IR Drop Analysis and Its Reduction Techniques in Deep Submicron Technology","isSavedByCurrentUser":false,"pageCount":8,"score":0.4977,"slideshowId":"44375591","sourceName":"cm_text","strippedTitle":"i501045562","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/i501045562-150207004243-conversion-gate02-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"This paper presents a detailed conceptual analysis of IR Drop effect in deep submicron technologies and its reduction techniques. The IR Drop effect in power/ground network increases rapidly with technology scaling. This affects the timing of the design and hence the desired speed. It is shown that in present day designs, using well known reduction techniques such as wire sizing and decoupling capacitor insertion, may not be sufficient to limit the voltage fluctuations and hence, two more important methods such as selective glitch reduction technique and IR Drop reduction through combinational circuit partitioning are discussed and the issues related to all the techniques are revised.","tags":["switching activity","decoupling capacitance","ir drop"],"url":"https://www.slideshare.net/slideshow/i501045562/44375591","userLogin":"ijeraeditor","userName":"IJERA Editor","viewCount":3001},{"algorithmId":"3","displayTitle":"Structural and Electrical Analysis of Various MOSFET Designs","isSavedByCurrentUser":false,"pageCount":4,"score":0.4908,"slideshowId":"46972470","sourceName":"cm_text","strippedTitle":"d503051619","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/d503051619-150414043856-conversion-gate01-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"Invention of Transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key to the development of nano electronics technology. This paper offers a brief review of some of the most popular MOSFET structure designs. The scaling down of planar bulk MOSFET proposed by the Moore’s Law has been saturated due to short channel effects and DIBL. Due to this alternative approaches has been considered to overcome the problems at lower node technology. SOI and FinFET technologies are promising candidates in this area.","tags":["soi.","pd mosfet","finfet"],"url":"https://www.slideshare.net/slideshow/d503051619/46972470","userLogin":"ijeraeditor","userName":"IJERA Editor","viewCount":335},{"algorithmId":"3","displayTitle":"18EC655_Module-1.pptx","isSavedByCurrentUser":false,"pageCount":55,"score":0.489,"slideshowId":"259061709","sourceName":"cm_text","strippedTitle":"18ec655module1pptx","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/18ec655module-1-230708131457-5c822193-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"The document discusses basic concepts in VLSI design including:\n- The history and progression of integrated circuit generations from SSI to VLSI to ULSI. \n- The basic operation and types (enhancement vs depletion, NMOS vs PMOS) of MOS transistors. \n- Fabrication processes for CMOS, including masks, diffusion, deposition of oxide and polysilicon layers.\n- Threshold voltage and factors that determine it such as oxide thickness and charges at interfaces.","tags":[],"url":"https://www.slideshare.net/JazzSameer/18ec655module1pptx","userLogin":"JazzSameer","userName":"JazzSameer","viewCount":21},{"algorithmId":"3","displayTitle":"Pvc cmos finale ","isSavedByCurrentUser":false,"pageCount":78,"score":0.4883,"slideshowId":"89609039","sourceName":"cm_text","strippedTitle":"pvc-cmos-finale","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/pvccmosfinale190415paklahfinale-180305040729-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"This document provides an introduction and background on Complementary Metal Oxide Semiconductor (CMOS) technology. It discusses key components of a CMOS circuit including NMOS, PMOS, photolithography, etching, chemical mechanical planarization, shallow trench isolation, contacts, vias, and interlayer dielectrics. The objectives of the project are to identify defects in a defective CMOS sample using electrical testing, scanning laser optical microscopy, passive voltage contrast under SEM, and focused ion beam with EDX to determine the root cause of the defect.","tags":[],"url":"https://www.slideshare.net/RoslinaShariff/pvc-cmos-finale","userLogin":"RoslinaShariff","userName":"Roslina Shariff","viewCount":993},{"algorithmId":"3","displayTitle":"Nanometer layout handbook at high speed design","isSavedByCurrentUser":false,"pageCount":39,"score":0.4875,"slideshowId":"76971943","sourceName":"cm_text","strippedTitle":"nanometer-layout-handbook-at-high-speed-design","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/nanometerlayouthandbookathighspeeddesign-170615123243-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"I made this contents for whom is about to layout own's IC design. I think it would be helpful to consider layouts about high speed Rx / Tx.\r\nSpecially it was aimed giga hertz bandwidth I/O with its ESD protection (I am still working on that items to rearrange with my knowledge to my experiences)\r\nI showed up all references and all images (except originals) are belong to own's copy rights.","tags":["high speed cmos ic layout","matching","offset"],"url":"https://www.slideshare.net/slideshow/nanometer-layout-handbook-at-high-speed-design/76971943","userLogin":"MinhoPark25","userName":"Minho Park","viewCount":2092},{"algorithmId":"3","displayTitle":"Extended Abstract - Adam Moreau","isSavedByCurrentUser":false,"pageCount":7,"score":0.4874,"slideshowId":"64819483","sourceName":"cm_text","strippedTitle":"extended-abstract-adam-moreau","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/df5d5815-28f5-4228-bc14-42825c98e02f-160809025337-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"This document summarizes research into designing a piezoelectric-actuated mirror mount with a servo bandwidth greater than 380kHz. Four different mount designs were tested: a cylindrical control mount and three designs intended to dampen mechanical resonances - a solid center of mass design, a design with a 0.125\" tungsten-carbide core, and a design with a 0.25\" tungsten-carbide core. Testing showed the thickness of the adhesive layer and mount material most affected resonance frequency. The optimal design was found to be a 0.25\" tungsten-carbide filled brass mount, achieving a 392kHz servo bandwidth.","tags":[],"url":"https://www.slideshare.net/slideshow/extended-abstract-adam-moreau/64819483","userLogin":"AdamMoreau","userName":"Adam Moreau","viewCount":131},{"algorithmId":"3","displayTitle":"PIM: Components, Materials, Handling \u0026 Testing","isSavedByCurrentUser":false,"pageCount":4,"score":0.4863,"slideshowId":"37688587","sourceName":"cm_text","strippedTitle":"wirelesspages0414","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/wirelesspages0414-140805115723-phpapp01-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"This issue of AWT Global's Wireless Pages describes How to measure PIM, treating low PIM components and offers information about low PIM materials.","tags":["pim","rf","skin effect"],"url":"https://www.slideshare.net/slideshow/wirelesspages0414/37688587","userLogin":"AWT-Global","userName":"AWT Global","viewCount":328},{"algorithmId":"3","displayTitle":"Nc342352340","isSavedByCurrentUser":false,"pageCount":6,"score":0.4846,"slideshowId":"26092580","sourceName":"cm_text","strippedTitle":"nc342352340","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/nc342352340-130911055219-phpapp01-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"This document summarizes research on scaling limits of CMOS devices and proposed structures to overcome these limits. It first discusses how quantum mechanical effects and short channel effects become problematic as devices are scaled down, limiting further scaling. It then reviews various structures proposed by other researchers, including fully depleted SOI MOSFETs with strained silicon channels, dual material gates, and gate-all-around structures. Finally, it proposes a new structure combining these elements: a fully depleted SOI gate-all-around MOSFET using a strained silicon channel and dual material gate to address scaling challenges while improving performance.","tags":[],"url":"https://www.slideshare.net/slideshow/nc342352340/26092580","userLogin":"ijeraeditor","userName":"IJERA Editor","viewCount":280},{"algorithmId":"3","displayTitle":"IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...","isSavedByCurrentUser":false,"pageCount":8,"score":0.4833,"slideshowId":"14129205","sourceName":"cm_text","strippedTitle":"b02041118","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/b02041118-120831080415-phpapp01-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"This document summarizes a research paper that proposes low-leakage 1-bit full adder cell designs for reducing power consumption in nanometer technologies. It introduces two modified full adder circuit designs (Design1 and Design2) that apply transistor resizing and power gating techniques. Simulation results show that the proposed designs reduce standby leakage power and active power compared to a conventional 28-transistor CMOS full adder. Design1 sizes transistors with a 3.17x PMOS-to-NMOS ratio while Design2 uses a 1.5x ratio. Both aim to minimize area and leakage through optimized transistor widths and lengths.","tags":[],"url":"https://www.slideshare.net/slideshow/b02041118/14129205","userLogin":"ijerd_editor","userName":"IJERD Editor","viewCount":737},{"algorithmId":"3","displayTitle":"ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY","isSavedByCurrentUser":false,"pageCount":11,"score":0.4824,"slideshowId":"86508427","sourceName":"cm_text","strippedTitle":"ultra-high-speed-factorial-design-in-subnanometer-technology","thumbnail":"https://cdn.slidesharecdn.com/ss_thumbnails/csit3229-180122091617-thumbnail.jpg?width=600\u0026height=600\u0026fit=bounds","description":"This work proposes a high speed and low power factorial design in 22nm technology and also it counts the effect of sub nano-meter constraints on this circuit. A comparative study for this\r\ndesign has been done for 90nm, 45nm and 22nm technology. The rise in circuit complexity and speed is accompanied by the scaling of MOSFET’s. The transistor saturation current Idsat is an important parameter because the transistor current determines the time needed to charge and discharge the capacitive loads on chip, and thus impacts the product speed more than any other transistor parameter. The efficient implementation of a factorial number is carried out by using\r\na decremented and multipliers which has been lucidly discussed in this paper. Normally in a factorial module a number is calculated as the iterative multiplication of the given number to\r\nthe decremented value of the given number. A Parallel adder based decremented has been proposed for calculating the factorial of any number that also includes 0 and 1. The\r\nperformances are calculated by using the existing 90-nm CMOS technology and scaling down the existing technology to 45-nm and 22-nm. \r\n","tags":["mosfet scaling","decremented","multiplier"],"url":"https://www.slideshare.net/slideshow/ultra-high-speed-factorial-design-in-subnanometer-technology/86508427","userLogin":"cscpconf","userName":"cscpconf","viewCount":84}],"moreFromUser":[],"featured":null,"latest":[]},"slideDimensions":{"height":842,"width":595},"sectionSummaries":[{"summaryList":"[\n {\n \"slides\": [\n 1\n ],\n \"topic\": \"Challenges in Analog Layout at 90nm\",\n \"cover\": \"Discusses Shallow Trench Isolation (STI) and Well Proximity Effect (WPE) challenges in analog layouts.\"\n },\n {\n \"slides\": [\n 2\n ],\n \"topic\": \"Shallow Trench Isolation (STI)\",\n \"cover\": \"Explains the STI technique, its importance, introduction of stress in MOS transistors, and methods to mitigate it.\"\n },\n {\n \"slides\": [\n 3\n ],\n \"topic\": \"Well Proximity Effect (WPE)\",\n \"cover\": \"Describes WPE, its effect on MOS threshold voltage variation, and layout considerations to mitigate this issue.\"\n },\n {\n \"slides\": [\n 4\n ],\n \"topic\": \"Importance of RF Layout at 90nm\",\n \"cover\": \"Emphasizes the significance of layout quality at high frequencies regarding parasitics and circuit performance.\"\n },\n {\n \"slides\": [\n 5\n ],\n \"topic\": \"Device Parasitics in RF Layout\",\n \"cover\": \"Discusses MOS parasitics, optimization techniques for gate resistance, and improving substrate resistance.\"\n }\n]"}],"topReadSlides":[],"user":{"id":"15900460","isFollowing":false,"login":"AdrianOShaughnessy","name":"AdrianOShaughnessy","occupation":null,"organization":null,"photo":"https://public.slidesharecdn.com/v2/images/profile-picture.png","photoExists":false,"shortName":"AdrianOShaughnessy"},"views":972},"_nextI18Next":{"initialI18nStore":{"en":{"common":{"ad":{"fallbackText":"Ad for Scribd subscription","label":"Ad","close":"Close Ad","dismiss_in":"Dismiss in","ad_info_title":"Why are you seeing this?","ad_info_description":"We use ads to keep content free and accessible for everyone. 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