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id="toc-History-sublist" class="vector-toc-list"> <li id="toc-Early_history" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Early_history"> <div class="vector-toc-text"> 2.1 Early history </div> </a> <ul id="toc-Early_history-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Expansion" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Expansion"> <div class="vector-toc-text"> 2.2 Expansion </div> </a> <ul id="toc-Expansion-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Recent_history" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Recent_history"> <div class="vector-toc-text"> 2.3 Recent history </div> </a> <ul id="toc-Recent_history-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Technology" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Technology"> <div class="vector-toc-text"> 3 Technology </div> </a> <ul id="toc-Technology-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Family_lines_of_products" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Family_lines_of_products"> <div class="vector-toc-text"> 4 Family lines of products </div> </a> <button aria-controls="toc-Family_lines_of_products-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Family lines of products subsection </button> <ul id="toc-Family_lines_of_products-sublist" class="vector-toc-list"> <li id="toc-Virtex_family" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Virtex_family"> <div class="vector-toc-text"> 4.1 Virtex family </div> </a> <ul id="toc-Virtex_family-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Kintex" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Kintex"> <div class="vector-toc-text"> 4.2 Kintex </div> </a> <ul id="toc-Kintex-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Artix" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Artix"> <div class="vector-toc-text"> 4.3 Artix </div> </a> <ul id="toc-Artix-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Zynq" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Zynq"> <div class="vector-toc-text"> 4.4 Zynq </div> </a> <ul id="toc-Zynq-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Spartan_family" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Spartan_family"> <div class="vector-toc-text"> 4.5 Spartan family </div> </a> <ul id="toc-Spartan_family-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-EasyPath" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#EasyPath"> <div class="vector-toc-text"> 4.6 EasyPath </div> </a> <ul id="toc-EasyPath-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Versal" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Versal"> <div class="vector-toc-text"> 4.7 Versal </div> </a> <ul id="toc-Versal-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> 5 See also </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> 6 References </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> 7 External links </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" > Toggle the table of contents </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading">Xilinx</h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 30 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-30" aria-hidden="true" > 30 languages </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%B2%D8%A7%D9%8A%D9%84%D9%86%D9%8A%D9%83%D8%B3" title="زايلنيكس – Arabic" lang="ar" hreflang="ar" data-title="زايلنيكس" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target">العربية</a></li><li class="interlanguage-link interwiki-azb mw-list-item"><a href="https://azb.wikipedia.org/wiki/%D8%B2%D8%A7%DB%8C%D9%84%DB%8C%D9%86%DA%A9%D8%B3" title="زایلینکس – South Azerbaijani" lang="azb" hreflang="azb" data-title="زایلینکس" data-language-autonym="تۆرکجه" data-language-local-name="South Azerbaijani" class="interlanguage-link-target">تۆرکجه</a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Xilinx" title="Xilinx – Catalan" lang="ca" hreflang="ca" data-title="Xilinx" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target">Català</a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/Xilinx" title="Xilinx – Czech" lang="cs" hreflang="cs" data-title="Xilinx" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target">Čeština</a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Xilinx" title="Xilinx – German" lang="de" hreflang="de" data-title="Xilinx" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target">Deutsch</a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Xilinx" title="Xilinx – Spanish" lang="es" hreflang="es" data-title="Xilinx" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target">Español</a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%B2%D8%A7%DB%8C%D9%84%DB%8C%D9%86%DA%A9%D8%B3" title="زایلینکس – Persian" lang="fa" hreflang="fa" data-title="زایلینکس" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target">فارسی</a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Xilinx" title="Xilinx – French" lang="fr" hreflang="fr" data-title="Xilinx" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target">Français</a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%9E%90%EC%9D%BC%EB%A7%81%EC%8A%A4" title="자일링스 – Korean" lang="ko" hreflang="ko" data-title="자일링스" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target">한국어</a></li><li class="interlanguage-link interwiki-ig mw-list-item"><a href="https://ig.wikipedia.org/wiki/Xilinx" title="Xilinx – Igbo" lang="ig" hreflang="ig" data-title="Xilinx" data-language-autonym="Igbo" data-language-local-name="Igbo" class="interlanguage-link-target">Igbo</a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Xilinx" title="Xilinx – Indonesian" lang="id" hreflang="id" data-title="Xilinx" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target">Bahasa Indonesia</a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Xilinx" title="Xilinx – Italian" lang="it" hreflang="it" data-title="Xilinx" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target">Italiano</a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/%D7%96%D7%99%D7%99%D7%9C%D7%99%D7%A0%D7%A7%D7%A1" title="זיילינקס – Hebrew" lang="he" hreflang="he" data-title="זיילינקס" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target">עברית</a></li><li class="interlanguage-link interwiki-ms mw-list-item"><a href="https://ms.wikipedia.org/wiki/Xilinx" title="Xilinx – Malay" lang="ms" hreflang="ms" data-title="Xilinx" data-language-autonym="Bahasa Melayu" data-language-local-name="Malay" class="interlanguage-link-target">Bahasa Melayu</a></li><li class="interlanguage-link interwiki-my mw-list-item"><a href="https://my.wikipedia.org/wiki/%E1%80%87%E1%80%AD%E1%80%AF%E1%80%84%E1%80%BA%E1%80%9C%E1%80%84%E1%80%BA%E1%80%B8%E1%80%80%E1%80%BA%E1%80%85%E1%80%BA" title="ဇိုင်လင်းက်စ် – Burmese" lang="my" hreflang="my" data-title="ဇိုင်လင်းက်စ်" data-language-autonym="မြန်မာဘာသာ" data-language-local-name="Burmese" class="interlanguage-link-target">မြန်မာဘာသာ</a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Xilinx" title="Xilinx – Dutch" lang="nl" hreflang="nl" data-title="Xilinx" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target">Nederlands</a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/%E3%82%B6%E3%82%A4%E3%83%AA%E3%83%B3%E3%82%AF%E3%82%B9" title="ザイリンクス – Japanese" lang="ja" hreflang="ja" data-title="ザイリンクス" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target">日本語</a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/Xilinx" title="Xilinx – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="Xilinx" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target">Norsk bokmål</a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Xilinx" title="Xilinx – Polish" lang="pl" hreflang="pl" data-title="Xilinx" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target">Polski</a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Xilinx" title="Xilinx – Portuguese" lang="pt" hreflang="pt" data-title="Xilinx" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target">Português</a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Xilinx" title="Xilinx – Romanian" lang="ro" hreflang="ro" data-title="Xilinx" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target">Română</a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/Xilinx" title="Xilinx – Russian" lang="ru" hreflang="ru" data-title="Xilinx" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target">Русский</a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/Xilinx" title="Xilinx – Serbian" lang="sr" hreflang="sr" data-title="Xilinx" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target">Српски / srpski</a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/Xilinx" title="Xilinx – Finnish" lang="fi" hreflang="fi" data-title="Xilinx" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target">Suomi</a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/Xilinx" title="Xilinx – Swedish" lang="sv" hreflang="sv" data-title="Xilinx" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target">Svenska</a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/Xilinx" title="Xilinx – Turkish" lang="tr" hreflang="tr" data-title="Xilinx" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target">Türkçe</a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/Xilinx" title="Xilinx – Ukrainian" lang="uk" hreflang="uk" data-title="Xilinx" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target">Українська</a></li><li class="interlanguage-link interwiki-ur mw-list-item"><a href="https://ur.wikipedia.org/wiki/%D8%B2%DB%8C%D9%84%DB%8C%D9%86%DA%A9%D8%B3" title="زیلینکس – Urdu" lang="ur" hreflang="ur" data-title="زیلینکس" data-language-autonym="اردو" data-language-local-name="Urdu" class="interlanguage-link-target">اردو</a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/Xilinx" title="Xilinx – Vietnamese" lang="vi" hreflang="vi" data-title="Xilinx" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target">Tiếng Việt</a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/%E8%B5%9B%E7%81%B5%E6%80%9D" title="赛灵思 – Chinese" lang="zh" hreflang="zh" data-title="赛灵思" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target">中文</a></li> </ul> <div class="after-portlet after-portlet-lang"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q1046482#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></div> </div> </div> </div> </header> <div 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<div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">American technology company</div> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><style data-mw-deduplicate="TemplateStyles:r1242257876">.mw-parser-output .ib-company .infobox-label{padding-right:0.5em}.mw-parser-output .ib-company .infobox-data,.mw-parser-output .ib-company .infobox-below{line-height:1.35em}.mw-parser-output .ib-company-logo img{background-color:#f8f9fa}.mw-parser-output .ib-company-locality,.mw-parser-output .ib-company-country{display:inline}</style><table class="infobox ib-company vcard"><caption class="infobox-title fn org">Xilinx, Inc.</caption><tbody><tr><td colspan="2" class="infobox-image ib-company-logo logo"><a href="/wiki/File:AMD_Xilinx_logo.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a9/AMD_Xilinx_logo.svg/220px-AMD_Xilinx_logo.svg.png" decoding="async" width="220" height="101" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a9/AMD_Xilinx_logo.svg/330px-AMD_Xilinx_logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a9/AMD_Xilinx_logo.svg/440px-AMD_Xilinx_logo.svg.png 2x" data-file-width="512" data-file-height="236" /></a></td></tr><tr><td colspan="2" class="infobox-image ib-company-logo logo"><a href="/wiki/File:XilinxInc-lobby.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/d9/XilinxInc-lobby.jpg/250px-XilinxInc-lobby.jpg" decoding="async" width="250" height="141" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/d/d9/XilinxInc-lobby.jpg 1.5x" data-file-width="268" data-file-height="151" /></a><div class="infobox-caption">Headquarters in the United States</div></td></tr><tr><th scope="row" class="infobox-label">Company type</th><td class="infobox-data category"><a href="/wiki/Subsidiary" title="Subsidiary">Subsidiary</a></td></tr><tr><th scope="row" class="infobox-label"><div style="display: inline-block; line-height: 1.2em; padding: .1em 0;"><a href="/wiki/Ticker_symbol" title="Ticker symbol">Traded as</a></div></th><td class="infobox-data"><a href="/wiki/Nasdaq" title="Nasdaq">Nasdaq</a>: XLNX</td></tr><tr><th scope="row" class="infobox-label">Industry</th><td class="infobox-data category"><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuits</a></td></tr><tr><th scope="row" class="infobox-label">Founded</th><td class="infobox-data">1984; 40 years ago (1984)<a href="#cite_note-Xilinx-Inc-Jun-1996-10-K-1">[1]</a></td></tr><tr><th scope="row" class="infobox-label">Founders</th><td class="infobox-data agent"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li><a href="/wiki/James_V._Barnett_II" title="James V. Barnett II">James V. Barnett II</a></li><li><a href="/wiki/Ross_Freeman" title="Ross Freeman">Ross Freeman</a></li><li><a href="/wiki/Bernie_Vonderschmitt" class="mw-redirect" title="Bernie Vonderschmitt">Bernie Vonderschmitt</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Defunct</th><td class="infobox-data">June 6, 2023; 17 months ago (2023-06-06)</td></tr><tr><th scope="row" class="infobox-label">Fate</th><td class="infobox-data">Acquired by <a href="/wiki/AMD" title="AMD">AMD</a> in 2022 and Xilinx's generic branding phased out in 2023</td></tr><tr><th scope="row" class="infobox-label">Headquarters</th><td class="infobox-data label"><a href="/wiki/San_Jose,_California" title="San Jose, California">San Jose</a>, <a href="/wiki/California" title="California">California</a>, U.S.</td></tr><tr><th scope="row" class="infobox-label"><div style="display: inline-block; line-height: 1.2em; padding: .1em 0;">Area served</div></th><td class="infobox-data">Worldwide</td></tr><tr><th scope="row" class="infobox-label"><div style="display: inline-block; line-height: 1.2em; padding: .1em 0;">Key people</div></th><td class="infobox-data agent"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist nowrap"><ul><li>Dennis Segers (<a href="/wiki/Chairman" class="mw-redirect" title="Chairman">chairman</a>)</li><li><a href="/wiki/Victor_Peng" title="Victor Peng">Victor Peng</a> (<a href="/wiki/President_(corporate_title)" title="President (corporate title)">president</a>, <a href="/wiki/Chief_Executive_Officer" class="mw-redirect" title="Chief Executive Officer">CEO</a>)</li><li>Brice Hill (<a href="/wiki/Chief_Financial_Officer" class="mw-redirect" title="Chief Financial Officer">CFO</a>)<a href="#cite_note-2">[2]</a></li><li>Ivo Bolsens (<a href="/wiki/Chief_Technology_Officer" class="mw-redirect" title="Chief Technology Officer">CTO</a>)</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Products</th><td class="infobox-data"><a href="/wiki/FPGA" class="mw-redirect" title="FPGA">FPGAs</a>, <a href="/wiki/CPLD" class="mw-redirect" title="CPLD">CPLDs</a></td></tr><tr><th scope="row" class="infobox-label">Revenue</th><td class="infobox-data"><img alt="Decrease" src="//upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Decrease2.svg/11px-Decrease2.svg.png" decoding="async" width="11" height="11" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Decrease2.svg/17px-Decrease2.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Decrease2.svg/22px-Decrease2.svg.png 2x" data-file-width="300" data-file-height="300" /> <a href="/wiki/United_States_dollar" title="United States dollar">US$</a>3.15 billion (2021)<a href="#cite_note-2021_10-K-3">[3]</a></td></tr><tr><th scope="row" class="infobox-label"><div style="display: inline-block; line-height: 1.2em; padding: .1em 0;"><a href="/wiki/Earnings_before_interest_and_taxes" title="Earnings before interest and taxes">Operating income</a></div></th><td class="infobox-data"><img alt="Decrease" src="//upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Decrease2.svg/11px-Decrease2.svg.png" decoding="async" width="11" height="11" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Decrease2.svg/17px-Decrease2.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Decrease2.svg/22px-Decrease2.svg.png 2x" data-file-width="300" data-file-height="300" /> US$753 million (2021)<a href="#cite_note-2021_10-K-3">[3]</a></td></tr><tr><th scope="row" class="infobox-label"><div style="display: inline-block; line-height: 1.2em; padding: .1em 0;"><a href="/wiki/Net_income" title="Net income">Net income</a></div></th><td class="infobox-data"><img alt="Decrease" src="//upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Decrease2.svg/11px-Decrease2.svg.png" decoding="async" width="11" height="11" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Decrease2.svg/17px-Decrease2.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/ed/Decrease2.svg/22px-Decrease2.svg.png 2x" data-file-width="300" data-file-height="300" /> US$646 million (2021)<a href="#cite_note-2021_10-K-3">[3]</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Asset" title="Asset">Total assets</a></th><td class="infobox-data"><img alt="Increase" src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b0/Increase2.svg/11px-Increase2.svg.png" decoding="async" width="11" height="11" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b0/Increase2.svg/17px-Increase2.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b0/Increase2.svg/22px-Increase2.svg.png 2x" data-file-width="300" data-file-height="300" /> US$5.52 billion (2021)<a href="#cite_note-2021_10-K-3">[3]</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Equity_(finance)" title="Equity (finance)">Total equity</a></th><td class="infobox-data"><img alt="Increase" src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b0/Increase2.svg/11px-Increase2.svg.png" decoding="async" width="11" height="11" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b0/Increase2.svg/17px-Increase2.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b0/Increase2.svg/22px-Increase2.svg.png 2x" data-file-width="300" data-file-height="300" /> US$2.89 billion (2021)<a href="#cite_note-2021_10-K-3">[3]</a></td></tr><tr><th scope="row" class="infobox-label"><div style="display: inline-block; line-height: 1.2em; padding: .1em 0;">Number of employees</div></th><td class="infobox-data">4,890 (April 2021)<a href="#cite_note-2021_10-K-3">[3]</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Parent_company" class="mw-redirect" title="Parent company">Parent</a></th><td class="infobox-data"><a href="/wiki/AMD" title="AMD">AMD</a></td></tr><tr><th scope="row" class="infobox-label">Website</th><td class="infobox-data"><a rel="nofollow" class="external text" href="http://www.xilinx.com/">www.xilinx.com</a> <a href="https://www.wikidata.org/wiki/Q1046482#P856" title="Edit this at Wikidata"><img alt="Edit this at Wikidata" src="//upload.wikimedia.org/wikipedia/en/thumb/8/8a/OOjs_UI_icon_edit-ltr-progressive.svg/10px-OOjs_UI_icon_edit-ltr-progressive.svg.png" decoding="async" width="10" height="10" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/8/8a/OOjs_UI_icon_edit-ltr-progressive.svg/15px-OOjs_UI_icon_edit-ltr-progressive.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/8/8a/OOjs_UI_icon_edit-ltr-progressive.svg/20px-OOjs_UI_icon_edit-ltr-progressive.svg.png 2x" data-file-width="20" data-file-height="20" /></a></td></tr></tbody></table> Xilinx, Inc. (<a href="/wiki/Help:IPA/English" title="Help:IPA/English">/ˈzaɪlɪŋks/</a> <a href="/wiki/Help:Pronunciation_respelling_key" title="Help:Pronunciation respelling key">ZY-links</a>) was an American technology and <a href="/wiki/Semiconductor" title="Semiconductor">semiconductor</a> company that primarily supplied <a href="/wiki/Programmable_logic_device" title="Programmable logic device">programmable logic devices</a>. The company is renowned for inventing the first commercially viable <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate array</a> (FPGA). It also pioneered the first <a href="/wiki/Fabless_manufacturing" title="Fabless manufacturing">fabless manufacturing</a> model.<a href="#cite_note-:0b-4">[4]</a><a href="#cite_note-six-5">[5]</a><a href="#cite_note-eleven-6">[6]</a> Xilinx was co-founded by <a href="/wiki/Ross_Freeman" title="Ross Freeman">Ross Freeman</a>, <a href="/wiki/Bernard_Vonderschmitt" class="mw-redirect" title="Bernard Vonderschmitt">Bernard Vonderschmitt</a>, and <a href="/wiki/James_V._Barnett_II" title="James V. Barnett II">James V Barnett II</a> in 1984. The company went public on the <a href="/wiki/Nasdaq" title="Nasdaq">Nasdaq</a> in 1990.<a href="#cite_note-7">[7]</a><a href="#cite_note-8">[8]</a> In October 2020, <a href="/wiki/AMD" title="AMD">AMD</a> announced its acquisition of Xilinx, which was completed on February 14, 2022, through an all-stock transaction valued at approximately $60 billion.<a href="#cite_note-9">[9]</a><a href="#cite_note-10">[10]</a> Xilinx remained a wholly owned <a href="/wiki/Subsidiary" title="Subsidiary">subsidiary</a> of AMD until the <a href="/wiki/Brand" title="Brand">brand</a> was phased out in June 2023, with Xilinx's product lines now branded under AMD.<a href="#cite_note-11">[11]</a> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Company_overview">Company overview</h2>[<a href="/w/index.php?title=Xilinx&action=edit&section=1" title="Edit section: Company overview">edit</a>]</div> Xilinx was founded in <a href="/wiki/Silicon_Valley" title="Silicon Valley">Silicon Valley</a> in 1984 and is headquartered in <a href="/wiki/San_Jose,_California" title="San Jose, California">San Jose</a>, United States. The company also has offices in <a href="/wiki/Longmont" class="mw-redirect" title="Longmont">Longmont</a>, United States; <a href="/wiki/Dublin" title="Dublin">Dublin</a>, Ireland; <a href="/wiki/Singapore" title="Singapore">Singapore</a>; <a href="/wiki/Hyderabad" title="Hyderabad">Hyderabad</a>, India; <a href="/wiki/Beijing" title="Beijing">Beijing</a>, China; <a href="/wiki/Shanghai" title="Shanghai">Shanghai</a>, China; <a href="/wiki/Brisbane" title="Brisbane">Brisbane</a>, Australia, <a href="/wiki/Tokyo" title="Tokyo">Tokyo</a>, Japan and <a href="/wiki/Yerevan" title="Yerevan">Yerevan</a>, Armenia.<a href="#cite_note-four-12">[12]</a><a href="#cite_note-13">[13]</a> According to Bill Carter, former <a href="/wiki/Chief_technology_officer" title="Chief technology officer">CTO</a> and current[<a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers">when?</a>] fellow at Xilinx, the choice of the name Xilinx refers to the <a href="/wiki/Chemical_symbol" title="Chemical symbol">chemical symbol</a> for <a href="/wiki/Silicon" title="Silicon">silicon</a> Si.<a href="#cite_note-:6-14">[14]</a>[<a href="/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify">how?</a>][<a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">failed verification</a>] The "linx" represents programmable links that connect programmable logic blocks together. The 'X's at each end represent the programmable logic blocks.<a href="#cite_note-three-15">[15]</a>[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] Xilinx sold a broad range of <a href="/wiki/Field_programmable_gate_array" class="mw-redirect" title="Field programmable gate array">field programmable gate arrays</a> (FPGAs), and <a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">complex programmable logic devices</a> (CPLDs), design tools, <a href="/wiki/Intellectual_property" title="Intellectual property">intellectual property</a>, and reference designs.<a href="#cite_note-two-16">[16]</a> Xilinx customers represent just over half of the entire programmable logic market, at 51%.<a href="#cite_note-two-16">[16]</a><a href="#cite_note-six-5">[5]</a><a href="#cite_note-twentythree-17">[17]</a> <a href="/wiki/Altera" title="Altera">Altera</a> (now subsidiary of <a href="/wiki/Intel" title="Intel">Intel</a>) is Xilinx's strongest competitor with 34% of the market. Other key players in this market are <a href="/wiki/Actel" title="Actel">Actel</a> (now subsidiary of <a href="/wiki/Microchip_Technology" title="Microchip Technology">Microsemi</a>) and <a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice Semiconductor</a>.<a href="#cite_note-eleven-6">[6]</a> <div class="mw-heading mw-heading2"><h2 id="History">History</h2>[<a href="/w/index.php?title=Xilinx&action=edit&section=2" title="Edit section: History">edit</a>]</div> <div class="mw-heading mw-heading3"><h3 id="Early_history">Early history</h3>[<a href="/w/index.php?title=Xilinx&action=edit&section=3" title="Edit section: Early history">edit</a>]</div> <a href="/wiki/Ross_Freeman" title="Ross Freeman">Ross Freeman</a>, <a href="/wiki/Bernard_Vonderschmitt" class="mw-redirect" title="Bernard Vonderschmitt">Bernard Vonderschmitt</a>, and <a href="/wiki/James_V_Barnett_II" class="mw-redirect" title="James V Barnett II">James V Barnett II</a>—all former employees of <a href="/wiki/Zilog" title="Zilog">Zilog</a>, an <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> and solid-state device manufacturer—co-founded Xilinx in 1984 with headquarters in <a href="/wiki/San_Jose,_California" title="San Jose, California">San Jose</a>, USA.<a href="#cite_note-four-12">[12]</a><a href="#cite_note-three-15">[15]</a> While working for Zilog, Freeman wanted to create chips that acted like a blank tape, allowing users to program the technology themselves.<a href="#cite_note-three-15">[15]</a> "The concept required lots of <a href="/wiki/Transistors" class="mw-redirect" title="Transistors">transistors</a> and, at that time, transistors were considered extremely precious—people thought that Ross's idea was pretty far out", said Xilinx Fellow Bill Carter, hired in 1984 to design ICs as Xilinx's eighth employee.<a href="#cite_note-three-15">[15]</a> It was at the time more profitable to manufacture generic circuits in massive volumes<a href="#cite_note-four-12">[12]</a> than specialized circuits for specific markets.<a href="#cite_note-four-12">[12]</a> <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGAs</a> promised to make specialized circuits profitable. Freeman could not convince Zilog to invest in FPGAs to chase a market then estimated at $100 million,<a href="#cite_note-four-12">[12]</a> so he and Barnett left to team up with Vonderschmitt, a former colleague. Together, they raised $4.5 million in <a href="/wiki/Venture_capital" title="Venture capital">venture</a> <a href="/wiki/Funding" title="Funding">funding</a> to design the first commercially viable FPGA.<a href="#cite_note-four-12">[12]</a> They incorporated the company in 1984 and began selling its first product by 1985.<a href="#cite_note-four-12">[12]</a> By late 1987, the company had raised more than $18 million in <a href="/wiki/Venture_capital" title="Venture capital">venture capital</a> (equivalent to $48.27 million in 2023) and was making nearly $14 million a year.<a href="#cite_note-four-12">[12]</a><a href="#cite_note-twelve-18">[18]</a> <div class="mw-heading mw-heading3"><h3 id="Expansion">Expansion</h3>[<a href="/w/index.php?title=Xilinx&action=edit&section=4" title="Edit section: Expansion">edit</a>]</div> From 1988 to 1990, the company's <a href="/wiki/Revenue" title="Revenue">revenue</a> grew each year, from $30 million to $100 million.<a href="#cite_note-four-12">[12]</a> During this time, Monolithic Memories Inc. (MMI), the company which had been providing funding to Xilinx, was purchased by <a href="/wiki/AMD" title="AMD">AMD</a>.<a href="#cite_note-four-12">[12]</a> As a result, Xilinx dissolved the deal with MMI and went public on the Nasdaq in 1989.<a href="#cite_note-four-12">[12]</a> The company also moved to a 144,000-square-foot (13,400 m2) plant in San Jose, California, to handle increasingly large orders from <a href="/wiki/Hewlett-Packard" title="Hewlett-Packard">HP</a>, <a href="/wiki/Apple_Inc." title="Apple Inc.">Apple Inc.</a>, <a href="/wiki/IBM" title="IBM">IBM</a> and <a href="/wiki/Sun_Microsystems" title="Sun Microsystems">Sun Microsystems</a>.<a href="#cite_note-four-12">[12]</a> Other FPGA makers emerged in the mid-1990s.<a href="#cite_note-four-12">[12]</a> By 1995, the company reached $550 million in revenue.<a href="#cite_note-four-12">[12]</a> Over the years, Xilinx expanded operations to <a href="/wiki/India" title="India">India</a>, <a href="/wiki/Asia" title="Asia">Asia</a> and <a href="/wiki/Europe" title="Europe">Europe</a>.<a href="#cite_note-five-19">[19]</a><a href="#cite_note-eight-20">[20]</a><a href="#cite_note-nine-21">[21]</a><a href="#cite_note-ten-22">[22]</a> Xilinx's sales rose to $2.53 billion by the end of its fiscal year 2018.<a href="#cite_note-23">[23]</a> Moshe Gavrielov – an <a href="/wiki/Electronic_design_automation" title="Electronic design automation">EDA</a> and <a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a> industry veteran who was appointed president and CEO in early 2008 – introduced targeted design platforms that combine FPGAs with <a href="/wiki/Software" title="Software">software</a>, IP cores, boards and kits to address focused target applications.<a href="#cite_note-embedded-24">[24]</a> These platforms provide an alternative to costly application-specific integrated circuits (<a href="/wiki/ASICs" class="mw-redirect" title="ASICs">ASICs</a>) and application-specific standard products (ASSPs).<a href="#cite_note-twentyeight-25">[25]</a><a href="#cite_note-twentynine-26">[26]</a><a href="#cite_note-:0-27">[27]</a> On January 4, 2018, Victor Peng, the company's COO, replaced Gavrielov as CEO.<a href="#cite_note-XilinxPressRelease08Jan2018-28">[28]</a> <div class="mw-heading mw-heading3"><h3 id="Recent_history">Recent history</h3>[<a href="/w/index.php?title=Xilinx&action=edit&section=5" title="Edit section: Recent history">edit</a>]</div> <figure typeof="mw:File/Thumb"><a href="/wiki/File:Xilinx_logo.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/cb/Xilinx_logo.svg/200px-Xilinx_logo.svg.png" decoding="async" width="200" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/cb/Xilinx_logo.svg/300px-Xilinx_logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/cb/Xilinx_logo.svg/400px-Xilinx_logo.svg.png 2x" data-file-width="173" data-file-height="35" /></a><figcaption>Logo of Xilinx until AMD acquisition</figcaption></figure> In 2011, the company introduced the <a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex-7</a> 2000T, the first product based on 2.5D stacked silicon (based on <a href="/wiki/Interposer" title="Interposer">silicon interposer</a> technology) to deliver larger FPGAs than could be built using standard monolithic silicon.<a href="#cite_note-:6-14">[14]</a> Xilinx then adapted the technology to combine formerly separate components in a single chip, first combining an FPGA with <a href="/wiki/Transceiver" title="Transceiver">transceivers</a> based on heterogeneous process technology to boost bandwidth capacity while using less power.<a href="#cite_note-29">[29]</a> According to former Xilinx <a href="/wiki/Chief_executive_officer" title="Chief executive officer">CEO</a> Moshe Gavrielov, the addition of a heterogeneous communications device, combined with the introduction of new <a href="/wiki/Software" title="Software">software</a> tools and the Zynq-7000 line of 28nm <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a> devices that combine an <a href="/wiki/ARM_core" class="mw-redirect" title="ARM core">ARM core</a> with an <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a>, are part of shifting its position from a programmable logic device supplier to one delivering “all things programmable”.<a href="#cite_note-ElectronicProductNews15May2012-30">[30]</a> In addition to Zynq-7000, Xilinx product lines include the <a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a>, Kintex and Artix series, each including configurations and models optimized for different applications.<a href="#cite_note-thirtythree-31">[31]</a> In April 2012, the company introduced the <a href="/wiki/Xilinx_Vivado" class="mw-redirect" title="Xilinx Vivado">Vivado Design Suite</a> - a next-generation <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>-strength design environment for advanced electronic system designs.<a href="#cite_note-EETimes25Apr2012-32">[32]</a> In May, 2014, the company shipped the first of the next generation FPGAs: the 20<a href="/wiki/Nanometre" title="Nanometre">nm</a> UltraScale.<a href="#cite_note-XCellDaily-33">[33]</a> In September 2017, <a href="/wiki/Amazon_(company)" title="Amazon (company)">Amazon</a> and Xilinx started a campaign for FPGA adoption. This campaign enables <a href="/wiki/Amazon_Web_Services" title="Amazon Web Services">AWS</a> Marketplace's <a href="/wiki/Amazon_Machine_Image" title="Amazon Machine Image">Amazon Machine Images</a> (AMIs) with associated Amazon FPGA Instances created by partners. The two companies released software development tools to simplify the creation of FPGA technology. The tools create and manage the machine images created and sold by partners.<a href="#cite_note-FBS13Dec2016-34">[34]</a><a href="#cite_note-FBS27Sep2017-35">[35]</a> In July 2018, Xilinx acquired DeepPhi Technology, a <a href="/wiki/China" title="China">Chinese</a> <a href="/wiki/Machine_learning" title="Machine learning">machine learning</a> <a href="/wiki/Startup_company" title="Startup company">startup</a> founded in 2016.<a href="#cite_note-:4-36">[36]</a><a href="#cite_note-37">[37]</a> In October 2018, the Xilinx Virtex UltraScale+ FPGAs and NGCodec's H.265 video encoder were used in a cloud-based video coding service using the <a href="/wiki/High_Efficiency_Video_Coding" title="High Efficiency Video Coding">High Efficiency Video Coding</a> (HEVC).<a href="#cite_note-38">[38]</a> The combination enables video streaming with the same visual quality as that using GPUs, but at 35%-45% lower bitrate.<a href="#cite_note-39">[39]</a> In November 2018, the company's Zynq UltraScale+ family of multiprocessor system-on-chips was certified to <a href="/wiki/Safety_integrity_level" title="Safety integrity level">safety integrity level</a> (SIL) 3 HFT1 of the <a href="/wiki/IEC_61508" title="IEC 61508">IEC 61508</a> specification.<a href="#cite_note-:2-40">[40]</a><a href="#cite_note-41">[41]</a> With this certification, developers are able to use the <a href="/wiki/Multi-processor_system-on-chip" class="mw-redirect" title="Multi-processor system-on-chip">MPSoC</a> platform in <a href="/wiki/Artificial_intelligence" title="Artificial intelligence">AI</a>-based safety applications of up to SIL 3, in industrial 4.0 platforms of automotive, aerospace, and AI systems.<a href="#cite_note-42">[42]</a><a href="#cite_note-43">[43]</a> In January 2019, ZF Friedrichshafen AG (ZF) worked with Xilinx's Zynq to power its ProAI automotive control unit, which is used to enable automated driving applications.<a href="#cite_note-44">[44]</a><a href="#cite_note-45">[45]</a><a href="#cite_note-46">[46]</a> Xilinx's platform overlooks the aggregation, pre-processing, and distribution of real-time data, and accelerates the AI processing of the unit.<a href="#cite_note-:2-40">[40]</a><a href="#cite_note-47">[47]</a> In November 2018, Xilinx migrated its defense-grade XQ UltraScale+ products to TSMC's 16nm <a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a> process.<a href="#cite_note-48">[48]</a><a href="#cite_note-49">[49]</a><a href="#cite_note-50">[50]</a> The products included the industry's first defense-grade heterogeneous <a href="/wiki/Multi-processor" class="mw-redirect" title="Multi-processor">multi-processor</a> SoC devices and encompassed the XQ Zynq UltraScale+ <a href="/wiki/MPSoC" class="mw-redirect" title="MPSoC">MPSoCs</a> and RFSoCs as well as XQ UltraScale+ Kintex and Virtex FPGAs.<a href="#cite_note-51">[51]</a><a href="#cite_note-52">[52]</a> That same month the company expanded its Alveo data center accelerator cards portfolio with the Alveo U280.<a href="#cite_note-53">[53]</a> The initial Alveo line included the U200 and U250, which featured 16 nm UltraScale+ Virtex FPGAs and <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a>.<a href="#cite_note-54">[54]</a> Those two cards were launched in October 2018 at the Xilinx Developer Forum.<a href="#cite_note-:3-55">[55]</a> At the Forum, Victor Peng, CEO of semiconductor design at Xilinx, and AMD CTO <a href="/wiki/Mark_Papermaster" title="Mark Papermaster">Mark Papermaster</a>, used eight Alveo U250 cards and two <a href="/wiki/Epyc" title="Epyc">AMD Epyc</a> 7551 server CPUs to set a new world record for inference throughput at 30,000 images per second.<a href="#cite_note-:3-55">[55]</a> Also in November 2018, Xilinx announced that <a href="/wiki/Dell_EMC" title="Dell EMC">Dell EMC</a> was the first server vendor to qualify its Alveo U200 accelerator card, used to accelerate key HPC and other workloads with select Dell EMC PowerEdge servers.<a href="#cite_note-56">[56]</a> The U280 included support for <a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">high-bandwidth memory</a> (HBM2) and high-performance server interconnect.<a href="#cite_note-57">[57]</a> In August 2019, Xilinx launched the Alveo U50, a low-profile adaptable accelerator with PCIe Gen4 support.<a href="#cite_note-58">[58]</a><a href="#cite_note-59">[59]</a> The U55C accelerator card was launched in November 2021, designed for <a href="/wiki/HPCC" title="HPCC">HPCC</a> and big data workloads by incorporating the <a href="/wiki/RDMA_over_Converged_Ethernet" title="RDMA over Converged Ethernet">RoCE v2</a>-based clustering solution, allowing for FPGA-based HPCC clustering to be integrated into existing data center infrastructures.<a href="#cite_note-U55C-60">[60]</a> In January 2019 <a href="/wiki/K%26L_Gates" title="K&L Gates">K&L Gates</a>, a law firm representing Xilinx sent a <a href="/wiki/DMCA" class="mw-redirect" title="DMCA">DMCA</a> <a href="/wiki/Cease_and_desist" title="Cease and desist">cease and desist</a> letter to an <a href="/wiki/Electrical_engineering" title="Electrical engineering">EE</a> <a href="/wiki/YouTube" title="YouTube">YouTuber</a> claiming <a href="/wiki/Trademark_infringement" title="Trademark infringement">trademark infringement</a> for featuring the Xilinx logo next to <a href="/wiki/Altera" title="Altera">Altera</a>'s in an educational video.<a href="#cite_note-61">[61]</a><a href="#cite_note-62">[62]</a> Xilinx refused to reply until a video outlining the legal threat was published, after which they sent an apology e-mail.<a href="#cite_note-63">[63]</a> In January 2019, <a href="/wiki/Baidu" title="Baidu">Baidu</a> announced that its new <a href="/wiki/Edge_computing" title="Edge computing">edge</a> acceleration computing product, EdgeBoard, was powered by Xilinx.<a href="#cite_note-64">[64]</a><a href="#cite_note-65">[65]</a> Edgeboard is a part of the Baidu Brain AI Hardware Platform Initiative, which encompasses Baidu's open computing services, and hardware and software products for its edge <a href="/wiki/Artificial_intelligence" title="Artificial intelligence">AI</a> applications.<a href="#cite_note-66">[66]</a> Edgeboard is based on the Xilinx Zynq UltraScale+ MPSoC, which uses real-time processors together with programmable logic.<a href="#cite_note-67">[67]</a><a href="#cite_note-68">[68]</a> The Xilinx-based Edgeboard can be used to develop products like smart-video security surveillance solutions, advanced-driver-assistance systems, and next-generation robots.<a href="#cite_note-69">[69]</a><a href="#cite_note-70">[70]</a> In February 2019, the company announced two new generations of its Zynq UltraScale+ RF system on chip (RFSoC) portfolio.<a href="#cite_note-71">[71]</a> The device covers the entire sub-6 GHz spectrum, which is necessary for <a href="/wiki/5G" title="5G">5G</a>, and the updates included: an extended millimeter wave interface, up to 20% power reduction in the RF data converter subsystem compared to the base portfolio, and support of <a href="/wiki/5G_NR" title="5G NR">5G New Radio</a>.<a href="#cite_note-72">[72]</a> The second generation release covered up to 5 GHz, while the third went up to 6 GHz.<a href="#cite_note-73">[73]</a> As of February, the portfolio was the only adaptable radio platform single chip that had been designed to address the industry's 5G network needs.<a href="#cite_note-74">[74]</a> The second announcement revealed that Xilinx and <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a> performed the world's first <a href="/wiki/5G_NR" title="5G NR">5G New Radio</a> (NR) commercial deployment in <a href="/wiki/South_Korea" title="South Korea">South Korea</a>.<a href="#cite_note-:0a-75">[75]</a><a href="#cite_note-:1-76">[76]</a> The two companies developed and deployed 5G massive multiple-input, multiple-output (m-MIMO) and millimeter wave (mmWave) products using Xilinx's UltraScale+ platform.<a href="#cite_note-:0a-75">[75]</a> The capabilities are essential for 5G commercialization.<a href="#cite_note-:1-76">[76]</a> The companies also announced collaboration on Xilinx's Versal adaptable compute acceleration platform (ACAP) products that will deliver 5G services.<a href="#cite_note-77">[77]</a> In February 2019, Xilinx introduced an HDMI 2.1 IP subsystem core, which enabled the company's devices to transmit, receive, and process up to <a href="/wiki/8K_resolution" title="8K resolution">8K</a> (7680 x 4320 pixels) UHD video in media players, cameras, monitors, LED walls, projectors, and <a href="/wiki/Kernel_(operating_system)" title="Kernel (operating system)">kernel</a>-based <a href="/wiki/Virtual_machine" title="Virtual machine">virtual machines</a>.<a href="#cite_note-78">[78]</a><a href="#cite_note-79">[79]</a> In April 2019, Xilinx entered into a definitive agreement to acquire Solarflare Communications, Inc.<a href="#cite_note-electronics360.globalspec.com-80">[80]</a><a href="#cite_note-Xilinx_to_Acquire_Solarflare-81">[81]</a> Xilinx became a strategic investor in Solarflare in 2017.<a href="#cite_note-Xilinx_to_Acquire_Solarflare-81">[81]</a><a href="#cite_note-82">[82]</a> The companies have been collaborating since then on advanced networking technology, and in March 2019 demonstrated their first joint solution: a single-chip FPGA-based 100G <a href="/wiki/Network_interface_controller" title="Network interface controller">NIC</a>. The acquisition enables Xilinx to combine its FPGA, MPSoC and ACAP solutions[<a href="/wiki/Wikipedia:Use_plain_English#Buzzwords" title="Wikipedia:Use plain English">buzzword</a>] with Solarflare's NIC technology.<a href="#cite_note-83">[83]</a><a href="#cite_note-electronics360.globalspec.com-80">[80]</a><a href="#cite_note-84">[84]</a> In August 2019, Xilinx announced that the company would be adding the world's largest FPGA - the Virtex Ultrascale+ VU19P, to the 16nm Virtex Ultrascale+ family. The VU19P contains 35 billion transistors.<a href="#cite_note-85">[85]</a><a href="#cite_note-86">[86]</a><a href="#cite_note-87">[87]</a> In June 2019, Xilinx announced that it was shipping its first Versal chips.<a href="#cite_note-88">[88]</a> Using ACAP, the chips’ hardware and software can be programmed to run almost any kind of AI software.<a href="#cite_note-89">[89]</a><a href="#cite_note-90">[90]</a> On October 1, 2019, Xilinx announced the launch of Vitis, a unified <a href="/wiki/Free_and_open-source_software" title="Free and open-source software">free and open source software</a> platform that helps developers take advantage of hardware adaptability.<a href="#cite_note-91">[91]</a><a href="#cite_note-92">[92]</a><a href="#cite_note-93">[93]</a> In 2019, Xilinx exceeded $3 billion in annual revenues for the first time, announcing revenues of $3.06 billion, up 24% from the prior fiscal year.<a href="#cite_note-94">[94]</a><a href="#cite_note-95">[95]</a> Revenues were $828 million for the fourth quarter of the fiscal year 2019, up 4% from the prior quarter and up 30% year over year.<a href="#cite_note-96">[96]</a> Xilinx's communications sector represented 41% of the revenue; the industrial, aerospace and defense sectors represented 27%; the data center and test, measurement & emulation (TME) sectors accounted for 18%; and the automotive, broadcast and consumer markets contributed 14%.<a href="#cite_note-97">[97]</a> In August 2020, <a href="/wiki/Subaru" title="Subaru">Subaru</a> announced the use of one of Xilinx's chips as processing power for camera images in its <a href="/wiki/Advanced_driver-assistance_systems" class="mw-redirect" title="Advanced driver-assistance systems">driver-assistance system</a>.<a href="#cite_note-98">[98]</a> In September 2020, Xilinx announced its new <a href="/wiki/Chipset" title="Chipset">chipset</a>, the T1 Telco Accelerator card, that can be used for units running on an open RAN 5G network.<a href="#cite_note-99">[99]</a> On October 27, 2020, <a href="/wiki/AMD" title="AMD">AMD</a> reached an agreement to acquire Xilinx in a <a href="/wiki/Stock_swap" title="Stock swap">stock-swap</a> deal, valuing the company at $35 billion. The deal was expected to close by the end of 2021.<a href="#cite_note-100">[100]</a> Their stockholders approved the acquisition on April 7, 2021.<a href="#cite_note-101">[101]</a> The deal was completed on February 14, 2022.<a href="#cite_note-102">[102]</a> Since the acquisition was completed, all Xilinx products are co-branded as AMD Xilinx; started in June 2023, all Xilinx's products are now being consolidated under AMD's branding. In December 2020, Xilinx announced they were acquiring the assets of Falcon Computing Systems to enhance the <a href="/wiki/Free_and_open-source_software" title="Free and open-source software">free and open source</a> Vitis platform, a design software for adaptable processing engines to enable highly optimized domain specific accelerators.<a href="#cite_note-103">[103]</a> In April 2021, Xilinx announced a collaboration with <a href="/wiki/Mavenir" title="Mavenir">Mavenir</a> to boost cell phone tower capacity for open <a href="/wiki/5G" title="5G">5G</a> networks.<a href="#cite_note-104">[104]</a> That same month, the company unveiled the Kria portfolio, a line of small form factor <a href="/wiki/System_on_module" title="System on module">system-on-modules</a> (SOMs) that come with a pre-built software stack to simplify development.<a href="#cite_note-105">[105]</a> In June, Xilinx announced it was acquiring German software developer Silexica, for an undisclosed amount.<a href="#cite_note-106">[106]</a> <div class="mw-heading mw-heading2"><h2 id="Technology">Technology</h2>[<a href="/w/index.php?title=Xilinx&action=edit&section=6" title="Edit section: Technology">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Xilinx_Spartan-3E_(XC3S500E).jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/4e/Xilinx_Spartan-3E_%28XC3S500E%29.jpg/220px-Xilinx_Spartan-3E_%28XC3S500E%29.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/4e/Xilinx_Spartan-3E_%28XC3S500E%29.jpg/330px-Xilinx_Spartan-3E_%28XC3S500E%29.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/4e/Xilinx_Spartan-3E_%28XC3S500E%29.jpg/440px-Xilinx_Spartan-3E_%28XC3S500E%29.jpg 2x" data-file-width="600" data-file-height="600" /></a><figcaption>The Spartan-3 platform was the industry's first 90nm FPGA, delivering more functionality and bandwidth per dollar than was previously possible.</figcaption></figure> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid 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(June 2020) (<a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a>)</div></td></tr></tbody></table> </div> </div> (<a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a>)</div></td></tr></tbody></table> Xilinx designs and develops programmable logic products, including integrated circuits (ICs), software design tools, predefined system functions delivered as intellectual property (IP) cores, design services, customer training, field engineering and technical support.<a href="#cite_note-two-16">[16]</a> Xilinx sells both FPGAs and CPLDs for electronic equipment manufacturers in end markets such as <a href="/wiki/Communications" class="mw-redirect" title="Communications">communications</a>, industrial, <a href="/wiki/Consumer" title="Consumer">consumer</a>, <a href="/wiki/Automotive" class="mw-redirect" title="Automotive">automotive</a> and <a href="/wiki/Data_processing" title="Data processing">data processing</a>.<a href="#cite_note-107">[107]</a><a href="#cite_note-108">[108]</a><a href="#cite_note-109">[109]</a><a href="#cite_note-110">[110]</a><a href="#cite_note-111">[111]</a><a href="#cite_note-112">[112]</a><a href="#cite_note-113">[113]</a> Xilinx's FPGAs have been used for the <a href="/wiki/A_Large_Ion_Collider_Experiment" class="mw-redirect" title="A Large Ion Collider Experiment">ALICE</a> (A Large Ion Collider Experiment) at the <a href="/wiki/CERN" title="CERN">CERN</a> European laboratory on the <a href="/wiki/France" title="France">French</a>-<a href="/wiki/Switzerland" title="Switzerland">Swiss</a> border to map and disentangle the trajectories of thousands of <a href="/wiki/Subatomic_particles" class="mw-redirect" title="Subatomic particles">subatomic particles</a>.<a href="#cite_note-114">[114]</a> Xilinx has also engaged in a partnership with the <a href="/wiki/United_States_Air_Force" title="United States Air Force">United States Air Force</a> Research Laboratory's Space Vehicles Directorate to develop FPGAs to withstand the damaging effects of <a href="/wiki/Space_radiation" class="mw-redirect" title="Space radiation">radiation in space</a>, which are 1,000 times less sensitive to space radiation than the commercial equivalent, for deployment in new satellites.<a href="#cite_note-Kleiman-115">[115]</a> Xilinx FPGAs can run a regular embedded OS (such as <a href="/wiki/Linux" title="Linux">Linux</a> or <a href="/wiki/VxWorks" title="VxWorks">vxWorks</a>) and can implement processor peripherals in programmable logic.<a href="#cite_note-two-16">[16]</a> The Virtex-II Pro, Virtex-4, Virtex-5, and Virtex-6 FPGA families, which include up to two embedded <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> cores, are targeted to the needs of <a href="/wiki/System-on-chip" class="mw-redirect" title="System-on-chip">system-on-chip</a> (SoC) designers.<a href="#cite_note-116">[116]</a><a href="#cite_note-eweekly-117">[117]</a><a href="#cite_note-118">[118]</a> Xilinx's IP cores include IP for simple functions (<a href="/wiki/Binary-coded_decimal" title="Binary-coded decimal">BCD</a> encoders, counters, etc.), for domain specific cores (<a href="/wiki/Digital_signal_processing" title="Digital signal processing">digital signal processing</a>, <a href="/wiki/Fast_Fourier_transform" title="Fast Fourier transform">FFT</a> and <a href="/wiki/Free_ideal_ring" title="Free ideal ring">FIR</a> cores) to complex systems (multi-gigabit networking cores, the MicroBlaze soft microprocessor and the compact Picoblaze <a href="/wiki/Microcontroller" title="Microcontroller">microcontroller</a>).<a href="#cite_note-two-16">[16]</a> Xilinx also creates custom cores for a fee.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] The main design toolkit Xilinx provides engineers is the <a href="/wiki/Xilinx_Vivado" class="mw-redirect" title="Xilinx Vivado">Vivado Design Suite</a>, an <a href="/wiki/Integrated_development_environment" title="Integrated development environment">integrated design environment</a> (IDE) with a system-to-IC level tools built on a shared scalable data model and a common debug environment. Vivado includes electronic system level (ESL) design tools for synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems.<a href="#cite_note-119">[119]</a> A free version WebPACK Edition of Vivado provides designers with a limited version of the design environment.<a href="#cite_note-120">[120]</a> Xilinx's Embedded Developer's Kit (EDK) supports the embedded <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> 405 and 440 cores (in Virtex-II Pro and some Virtex-4 and -5 chips) and the <a href="/wiki/Microblaze" class="mw-redirect" title="Microblaze">Microblaze</a> core. Xilinx's System Generator for DSP implements DSP designs on Xilinx FPGAs. A freeware version of its EDA software called ISE WebPACK is used with some of its non-high-performance chips. Xilinx is the only (as of 2007) FPGA vendor to distribute a native Linux freeware synthesis toolchain.<a href="#cite_note-cheung-121">[121]</a> Xilinx announced the architecture for a new <a href="/wiki/ARM_Cortex-A9" title="ARM Cortex-A9">ARM Cortex-A9</a>-based platform for embedded systems designers, that combines the software programmability of an embedded processor with the hardware flexibility of an FPGA.<a href="#cite_note-EETimesApril27-122">[122]</a><a href="#cite_note-DesignReuseMay3-123">[123]</a> The new architecture abstracts much of the hardware burden away from the <a href="/wiki/Embedded_software" title="Embedded software">embedded software</a> developers' point of view, giving them an unprecedented level of control in the development process.<a href="#cite_note-EETimesApril28-124">[124]</a><a href="#cite_note-FPGABlogApril27-125">[125]</a><a href="#cite_note-EETimesApril27-122">[122]</a><a href="#cite_note-DesignReuseMay3-123">[123]</a> With this platform, software developers can leverage their existing system code based on ARM technology and utilize vast off-the-shelf open-source and commercially available software component libraries.<a href="#cite_note-EETimesApril28-124">[124]</a><a href="#cite_note-FPGABlogApril27-125">[125]</a><a href="#cite_note-EETimesApril27-122">[122]</a><a href="#cite_note-DesignReuseMay3-123">[123]</a> Because the system boots an <a href="/wiki/Operating_system" title="Operating system">OS</a> at reset, software development can get under way quickly within familiar development and debug environments using tools such as <a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a>'s RealView development suite and related third-party tools, Eclipse-based IDEs, GNU, the Xilinx Software Development Kit and others.<a href="#cite_note-EETimesApril28-124">[124]</a><a href="#cite_note-FPGABlogApril27-125">[125]</a><a href="#cite_note-EETimesApril27-122">[122]</a><a href="#cite_note-DesignReuseMay3-123">[123]</a> In early 2011, Xilinx began shipping the Zynq-7000 SoC platform immerses ARM multi-cores, programmable logic fabric, DSP data paths, memories and <a href="/wiki/Input/output" title="Input/output">I/O</a> functions in a dense and configurable mesh of interconnect.<a href="#cite_note-EETimesMarch1-126">[126]</a><a href="#cite_note-EmbeddedWorldMarch1-127">[127]</a> The platform targets embedded designers working on market applications that require multi-functionality and real-time responsiveness, such as automotive driver assistance, intelligent video surveillance, industrial automation, aerospace and defense, and next-generation wireless.<a href="#cite_note-EETimesApril28-124">[124]</a><a href="#cite_note-FPGABlogApril27-125">[125]</a><a href="#cite_note-EETimesApril27-122">[122]</a><a href="#cite_note-DesignReuseMay3-123">[123]</a> Following the introduction of its 28nm 7-series FPGAs, Xilinx revealed that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies in one package, employing technology developed for 3D construction and stacked-die assemblies.<a href="#cite_note-ednEurope-128">[128]</a><a href="#cite_note-lawrence-129">[129]</a> The company's stacked silicon interconnect (SSI) technology stacks several (three or four) active FPGA dies side by side on a silicon <a href="/wiki/Interposer" title="Interposer">interposer</a> – a single piece of silicon that carries passive interconnect. The individual FPGA dies are conventional, and are flip-chip mounted by microbumps on to the interposer. The interposer provides direct interconnect between the FPGA dies, with no need for transceiver technologies such as high-speed <a href="/wiki/SerDes" title="SerDes">SerDes</a>.<a href="#cite_note-ednEurope-128">[128]</a><a href="#cite_note-lawrence-129">[129]</a><a href="#cite_note-130">[130]</a> In October 2011, Xilinx shipped the first FPGA to use the new technology, the Virtex-7 2000T FPGA, which includes 6.8 billion transistors and 20 million ASIC gates.<a href="#cite_note-don1025-131">[131]</a><a href="#cite_note-clive1025-132">[132]</a><a href="#cite_note-david1025-133">[133]</a><a href="#cite_note-scieng1026-134">[134]</a> The following spring, Xilinx used 3D technology to ship the Virtex-7 HT, the industry's first heterogeneous FPGAs, which combine high bandwidth FPGAs with a maximum of sixteen 28 Gbit/s and seventy-two 13.1 Gbit/s transceivers to reduce power and size requirements for key Nx100G and 400G line card applications and functions.<a href="#cite_note-135">[135]</a><a href="#cite_note-136">[136]</a> In January 2011, Xilinx acquired design tool firm AutoESL Design Technologies and added System C high-level design for its 6- and 7-series FPGA families.<a href="#cite_note-EETimesJan31-137">[137]</a> The addition of AutoESL tools extended the design community for FPGAs to designers more accustomed to designing at a higher level of abstraction using <a href="/wiki/C_(programming_language)" title="C (programming language)">C</a>, <a href="/wiki/C%2B%2B" title="C++">C++</a> and System C.<a href="#cite_note-ElectronicsWeelyJan31-138">[138]</a> In April 2012, Xilinx introduced a revised version of its toolset for programmable systems, called <a href="/wiki/Xilinx_Vivado" class="mw-redirect" title="Xilinx Vivado">Vivado Design Suite</a>. This IP and system-centric design software supports newer high capacity devices, and speeds the design of programmable logic and I/O.<a href="#cite_note-139">[139]</a> Vivado provides faster integration and implementation for programmable systems into devices with 3D stacked silicon interconnect technology, ARM processing systems, analog mixed signal (AMS), and many <a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">semiconductor intellectual property</a> (IP) cores.<a href="#cite_note-EDN15Jun2012-140">[140]</a> In July 2019, Xilinx acquired NGCodec, developers of <a href="/wiki/FPGA" class="mw-redirect" title="FPGA">FPGA</a> <a href="/wiki/Hardware_acceleration" title="Hardware acceleration">accelerated</a> video encoders for <a href="/wiki/Video_hosting_service" class="mw-redirect" title="Video hosting service">video streaming</a>, <a href="/wiki/Cloud_gaming" title="Cloud gaming">cloud gaming</a> and cloud <a href="/wiki/Mixed_reality" title="Mixed reality">mixed reality</a> services. NGCodec video encoders include support for <a href="/wiki/H.264/MPEG-4_AVC" class="mw-redirect" title="H.264/MPEG-4 AVC">H.264/AVC</a>, <a href="/wiki/HEVC" class="mw-redirect" title="HEVC">H.265/HEVC</a>, <a href="/wiki/VP9" title="VP9">VP9</a> and <a href="/wiki/AV1" title="AV1">AV1</a>, with planned future support for <a href="/wiki/Versatile_Video_Coding" title="Versatile Video Coding">H.266/VVC</a> and AV2.<a href="#cite_note-141">[141]</a><a href="#cite_note-142">[142]</a> In May 2020, Xilinx installed its first Adaptive Compute Cluster (XACC) at ETH Zurich in Switzerland.<a href="#cite_note-:5-143">[143]</a> The XACCs provide infrastructure and funding to support research in adaptive compute acceleration for high performance computing (HPC).<a href="#cite_note-:5-143">[143]</a> The clusters include high-end servers, Xilinx Alveo accelerator cards, and high speed networking.<a href="#cite_note-144">[144]</a> Three other XACCs will be installed at the <a href="/wiki/University_of_California,_Los_Angeles" title="University of California, Los Angeles">University of California, Los Angeles</a> (UCLA); the <a href="/wiki/University_of_Illinois_at_Urbana_Champaign" class="mw-redirect" title="University of Illinois at Urbana Champaign">University of Illinois at Urbana Champaign</a> (UIUC); and the <a href="/wiki/National_University_of_Singapore" title="National University of Singapore">National University of Singapore</a> (NUS).<a href="#cite_note-:5-143">[143]</a><a href="#cite_note-145">[145]</a> <div class="mw-heading mw-heading2"><h2 id="Family_lines_of_products">Family lines of products</h2>[<a href="/w/index.php?title=Xilinx&action=edit&section=7" title="Edit section: Family lines of products">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:ZyXEL_ZyAIR_B-2000_-_Xilinx_XC9536XL-8842.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/bc/ZyXEL_ZyAIR_B-2000_-_Xilinx_XC9536XL-8842.jpg/220px-ZyXEL_ZyAIR_B-2000_-_Xilinx_XC9536XL-8842.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/bc/ZyXEL_ZyAIR_B-2000_-_Xilinx_XC9536XL-8842.jpg/330px-ZyXEL_ZyAIR_B-2000_-_Xilinx_XC9536XL-8842.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/bc/ZyXEL_ZyAIR_B-2000_-_Xilinx_XC9536XL-8842.jpg/440px-ZyXEL_ZyAIR_B-2000_-_Xilinx_XC9536XL-8842.jpg 2x" data-file-width="2824" data-file-height="2824" /></a><figcaption>CPLD Xilinx XC9536XL</figcaption></figure> Before 2010, Xilinx offered two main FPGA families: the high-performance <a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a> series and the high-volume Spartan series, with a cheaper EasyPath option for ramping to volume production.<a href="#cite_note-thirtythree-31">[31]</a> The company also provides two <a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a> lines: the CoolRunner and the 9500 series. Each model series has been released in multiple generations since its launch.<a href="#cite_note-Brown-146">[146]</a> With the introduction of its 28nm FPGAs in June 2010, Xilinx replaced the high-volume Spartan family with the Kintex family and the low-cost Artix family.<a href="#cite_note-EET-147">[147]</a><a href="#cite_note-Morris-148">[148]</a> Xilinx's newer FPGA products use a <a href="/wiki/High-%CE%BA_dielectric" title="High-κ dielectric">High-K Metal Gate</a> (HKMG) process, which reduces static power consumption while increasing logic capacity.<a href="#cite_note-harris-149">[149]</a> In 28nm devices, static power accounts for much and sometimes most of the total power dissipation. Virtex-6 and Spartan-6 FPGA families are said to consume 50 percent less power, and have up to twice the logic capacity compared to the previous generation of Xilinx FPGAs.<a href="#cite_note-eweekly-117">[117]</a><a href="#cite_note-eetimes-150">[150]</a><a href="#cite_note-EDN-151">[151]</a> In June 2010, Xilinx introduced the Xilinx 7 series: the Virtex-7, Kintex-7, and Artix-7 families, promising improvements in system power, performance, capacity, and price. These new FPGA families are manufactured using <a href="/wiki/TSMC" title="TSMC">TSMC</a>'s 28nm HKMG process.<a href="#cite_note-xilinx7-152">[152]</a> The 28nm series 7 devices feature a 50 percent power reduction compared to the company's 40nm devices and offer capacity of up to 2 million logic cells.<a href="#cite_note-EET-147">[147]</a> Less than one year after announcing the 7 series 28nm FPGAs, Xilinx shipped the world's first 28nm FPGA device, the Kintex-7.<a href="#cite_note-153">[153]</a><a href="#cite_note-154">[154]</a> In March 2011, Xilinx introduced the Zynq-7000 family, which integrates a complete <a href="/wiki/ARM_Cortex-A9" title="ARM Cortex-A9">ARM Cortex-A9</a> MPCore processor-based system on a 28nm FPGA for system architects and embedded software developers.<a href="#cite_note-EETimesMarch1-126">[126]</a><a href="#cite_note-EmbeddedWorldMarch1-127">[127]</a> In May 2017, Xilinx expanded the 7 Series with the production of the Spartan-7 family.<a href="#cite_note-spartan7announce-155">[155]</a><a href="#cite_note-spartan7prod-156">[156]</a> In Dec, 2013, Xilinx introduced the UltraScale series: Virtex UltraScale and Kintex UltraScale families. These new FPGA families are manufactured by <a href="/wiki/TSMC" title="TSMC">TSMC</a> in its 20nm planar process.<a href="#cite_note-TSMC-157">[157]</a> At the same time it announced an UltraScale SoC architecture, called Zynq UltraScale+ <a href="/wiki/MPSoC" class="mw-redirect" title="MPSoC">MPSoC</a>, in TSMC 16nm FinFET process.<a href="#cite_note-TSMC_16-158">[158]</a> In March 2021, Xilinx announced a new cost-optimized portfolio with Artix and Zynq UltraScale+ devices, fabricated on TSMC's 16nm process.<a href="#cite_note-159">[159]</a> <div class="mw-heading mw-heading3"><h3 id="Virtex_family">Virtex family</h3>[<a href="/w/index.php?title=Xilinx&action=edit&section=8" title="Edit section: Virtex family">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex (FPGA)</a></div> The <a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a> series of FPGAs have integrated features that include <a href="/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a> and ECC logic, DSP blocks, <a href="/wiki/PCI-Express" class="mw-redirect" title="PCI-Express">PCI-Express</a> controllers, <a href="/wiki/Ethernet" title="Ethernet">Ethernet</a> <a href="/wiki/MAC_address" title="MAC address">MAC</a> blocks, and high-speed transceivers. In addition to FPGA logic, the Virtex series includes embedded fixed function hardware for commonly used functions such as multipliers, memories, serial transceivers and microprocessor cores.<a href="#cite_note-Virtex1-160">[160]</a> These capabilities are used in applications such as wired and wireless infrastructure equipment, advanced medical equipment, test and measurement, and defense systems.<a href="#cite_note-Virtex2-161">[161]</a> The Virtex 7 family, is based on a 28nm design and is reported to deliver a two-fold system performance improvement at 50 percent lower power compared to previous generation Virtex-6 devices. In addition, Virtex-7 doubles the memory bandwidth compared to previous generation Virtex FPGAs with 1866 Mbit/s memory interfacing performance and over two million logic cells.<a href="#cite_note-EET-147">[147]</a><a href="#cite_note-Morris-148">[148]</a> In 2011, Xilinx began shipping sample quantities of the Virtex-7 2000T "3D FPGA", which combines four smaller FPGAs into a single package by placing them on a special silicon interconnection pad (called an <a href="/wiki/Interposer" title="Interposer">interposer</a>) to deliver 6.8 billion transistors in a single large chip. The interposer provides 10,000 data pathways between the individual FPGAs — roughly 10 to 100 times more than would usually be available on a board – to create a single FPGA.<a href="#cite_note-don1025-131">[131]</a><a href="#cite_note-clive1025-132">[132]</a><a href="#cite_note-david1025-133">[133]</a> In 2012, using the same 3D technology, Xilinx introduced initial shipments of their Virtex-7 H580T FPGA, a heterogeneous device, so called because it comprises two FPGA dies and one 8-channel 28 Gbit/s transceiver die in the same package.<a href="#cite_note-ElectronicProductNews15May2012-30">[30]</a> The Virtex-6 family is built on a 40nm process for compute-intensive electronic systems, and the company claims it consumes 15 percent less power and has 15 percent improved performance over competing 40nm FPGAs.<a href="#cite_note-162">[162]</a> The Virtex-5 LX and the LXT are intended for logic-intensive applications, and the Virtex-5 SXT is for DSP applications.<a href="#cite_note-163">[163]</a> With the Virtex-5, Xilinx changed the logic fabric from four-input LUTs to six-input LUTs. With the increasing complexity of combinational logic functions required by SoC designs, the percentage of combinational paths requiring multiple four-input LUTs had become a performance and routing bottleneck. The six-input LUT represented a tradeoff between better handling of increasingly complex combinational functions, at the expense of a reduction in the absolute number of LUTs per device. The Virtex-5 series is a 65nm design <a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">fabricated</a> in 1.0V, triple-oxide process technology.<a href="#cite_note-Virtex3-164">[164]</a> Legacy Virtex devices (Virtex, Virtex-II, Virtex-II Pro, Virtex 4) are still available, but are not recommended for use in new designs. <div class="mw-heading mw-heading3"><h3 id="Kintex">Kintex</h3>[<a href="/w/index.php?title=Xilinx&action=edit&section=9" title="Edit section: Kintex">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Xilinx_Kintex7_XCKU025_on_matrox_grabber.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/62/Xilinx_Kintex7_XCKU025_on_matrox_grabber.jpg/220px-Xilinx_Kintex7_XCKU025_on_matrox_grabber.jpg" decoding="async" width="220" height="154" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/62/Xilinx_Kintex7_XCKU025_on_matrox_grabber.jpg/330px-Xilinx_Kintex7_XCKU025_on_matrox_grabber.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/62/Xilinx_Kintex7_XCKU025_on_matrox_grabber.jpg/440px-Xilinx_Kintex7_XCKU025_on_matrox_grabber.jpg 2x" data-file-width="3901" data-file-height="2731" /></a><figcaption>A Xilinx Kintex UltraScale FPGA (XCKU025-FFVA1156) on a <a href="/wiki/Matrox" title="Matrox">Matrox</a> <a href="/wiki/Frame_grabber" title="Frame grabber">frame grabber</a></figcaption></figure> The Kintex-7 family is the first Xilinx mid-range FPGA family that the company claims delivers Virtex-6 family performance at less than half the price while consuming 50 percent less power. The Kintex family includes high-performance 12.5 Gbit/s or lower-cost optimized 6.5 Gbit/s serial connectivity, memory, and logic performance required for applications such as high volume <a href="/wiki/10G" title="10G">10G</a> optical wired communication equipment, and provides a balance of signal processing performance, power consumption and cost to support the deployment of <a href="/wiki/Long_Term_Evolution" class="mw-redirect" title="Long Term Evolution">Long Term Evolution</a> (LTE) wireless networks.<a href="#cite_note-EET-147">[147]</a><a href="#cite_note-Morris-148">[148]</a> In August 2018, SK Telecom deployed Xilinx Kintex UltraScale FPGAs as their artificial intelligence accelerators at their data centers in South Korea.<a href="#cite_note-kintex-165">[165]</a> The FPGAs run SKT's automatic speech-recognition application to accelerate Nugu, SKT's voice-activated assistant.<a href="#cite_note-kintex-165">[165]</a><a href="#cite_note-166">[166]</a> In July, 2020 Xilinx made the latest addition to their Kintex family, 'KU19P FPGA' which delivers more logic fabric and embedded memory<a href="#cite_note-167">[167]</a> <div class="mw-heading mw-heading3"><h3 id="Artix">Artix</h3>[<a href="/w/index.php?title=Xilinx&action=edit&section=10" title="Edit section: Artix">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Xilinx_XC7A35T.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/af/Xilinx_XC7A35T.jpg/220px-Xilinx_XC7A35T.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/af/Xilinx_XC7A35T.jpg/330px-Xilinx_XC7A35T.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/af/Xilinx_XC7A35T.jpg/440px-Xilinx_XC7A35T.jpg 2x" data-file-width="1024" data-file-height="768" /></a><figcaption>A Artix-7 FPGA (XC7A35T-CSG325)</figcaption></figure> The Artix-7 family delivers 50 percent lower power and 35 percent lower cost compared to the Spartan-6 family and is based on the unified Virtex-series architecture. The Artix family is designed to address the small form factor and low-power performance requirements of battery-powered portable <a href="/wiki/Ultrasound" title="Ultrasound">ultrasound</a> equipment, commercial digital camera lens control, and military <a href="/wiki/Avionics" title="Avionics">avionics</a> and communications equipment.<a href="#cite_note-EET-147">[147]</a><a href="#cite_note-Morris-148">[148]</a> With the introduction of the Spartan-7 family in 2017, which lack high-bandwidth transceivers, the Artix-7's was clarified as being the "transceiver optimized" member.<a href="#cite_note-costOptimizedPortfolio2017-168">[168]</a> <div class="mw-heading mw-heading3"><h3 id="Zynq">Zynq</h3>[<a href="/w/index.php?title=Xilinx&action=edit&section=11" title="Edit section: Zynq">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Adapteva_Parallella_DK02_-_Zynq_(15455173526).png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/ce/Adapteva_Parallella_DK02_-_Zynq_%2815455173526%29.png/220px-Adapteva_Parallella_DK02_-_Zynq_%2815455173526%29.png" decoding="async" width="220" height="146" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/ce/Adapteva_Parallella_DK02_-_Zynq_%2815455173526%29.png/330px-Adapteva_Parallella_DK02_-_Zynq_%2815455173526%29.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/ce/Adapteva_Parallella_DK02_-_Zynq_%2815455173526%29.png/440px-Adapteva_Parallella_DK02_-_Zynq_%2815455173526%29.png 2x" data-file-width="4000" data-file-height="2660" /></a><figcaption>A Zynq-7000 (XC7Z010-CLG400) on a <a href="/wiki/Adapteva" class="mw-redirect" title="Adapteva">Adapteva</a> Parallella <a href="/wiki/Single-board_computer" title="Single-board computer">single-board computer</a></figcaption></figure> The Zynq-7000 family of <a href="/wiki/System_on_a_chip" title="System on a chip">SoCs</a> addresses high-end embedded-system applications, such as video surveillance, automotive-driver assistance, next-generation wireless, and factory automation.<a href="#cite_note-EETimesMarch1-126">[126]</a><a href="#cite_note-EmbeddedWorldMarch1-127">[127]</a><a href="#cite_note-EDNMarch1-169">[169]</a> Zynq-7000 integrate a complete <a href="/wiki/ARM_Cortex-A9" title="ARM Cortex-A9">ARM Cortex-A9</a> MPCore-processor-based 28nm system. The Zynq architecture differs from previous marriages of programmable logic and embedded processors by moving from an FPGA-centric platform to a processor-centric model.<a href="#cite_note-EETimesMarch1-126">[126]</a><a href="#cite_note-EmbeddedWorldMarch1-127">[127]</a><a href="#cite_note-EDNMarch1-169">[169]</a> For software developers, Zynq-7000 appear the same as a standard, fully featured <a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a> processor-based <a href="/wiki/System_on_a_chip" title="System on a chip">system-on-chip (SoC)</a>, booting immediately at power-up and capable of running a variety of operating systems independently of the programmable logic.<a href="#cite_note-EETimesMarch1-126">[126]</a><a href="#cite_note-EmbeddedWorldMarch1-127">[127]</a><a href="#cite_note-EDNMarch1-169">[169]</a> In 2013, Xilinx introduced the Zynq-7100, which integrates <a href="/wiki/Digital_signal_processing" title="Digital signal processing">digital signal processing</a> (DSP) to meet emerging programmable systems integration requirements of wireless, broadcast, medical and military applications.<a href="#cite_note-170">[170]</a> The new Zynq-7000 product family posed a key challenge for system designers, because Xilinx ISE design software had not been developed to handle the capacity and complexity of designing with an FPGA with an ARM core.<a href="#cite_note-EETimes25Apr2012-32">[32]</a><a href="#cite_note-EDN15Jun2012-140">[140]</a> Xilinx's new <a href="/wiki/Xilinx_Vivado" class="mw-redirect" title="Xilinx Vivado">Vivado Design Suite</a> addressed this issue, because the software was developed for higher capacity FPGAs, and it included <a href="/wiki/High_level_synthesis" class="mw-redirect" title="High level synthesis">high level synthesis</a> (HLS) functionality that allows engineers to compile the co-processors from a <a href="/wiki/C_(programming_language)" title="C (programming language)">C</a>-based description.<a href="#cite_note-EETimes25Apr2012-32">[32]</a><a href="#cite_note-EDN15Jun2012-140">[140]</a> The <a href="/wiki/AXIOM_(camera)" title="AXIOM (camera)">AXIOM</a>,<a href="#cite_note-171">[171]</a> the world's first <a href="/wiki/Digital_cinema_camera" class="mw-redirect" title="Digital cinema camera">digital cinema camera</a> that is <a href="/wiki/Open_source_hardware" class="mw-redirect" title="Open source hardware">open source hardware</a>, contains a Zynq-7000.<a href="#cite_note-172">[172]</a> <div class="mw-heading mw-heading3"><h3 id="Spartan_family">Spartan family</h3>[<a href="/w/index.php?title=Xilinx&action=edit&section=12" title="Edit section: Spartan family">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Fritz!Box_Fon_WLAN_7270_-_Xilinx_3S250E-3338.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/79/Fritz%21Box_Fon_WLAN_7270_-_Xilinx_3S250E-3338.jpg/220px-Fritz%21Box_Fon_WLAN_7270_-_Xilinx_3S250E-3338.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/79/Fritz%21Box_Fon_WLAN_7270_-_Xilinx_3S250E-3338.jpg/330px-Fritz%21Box_Fon_WLAN_7270_-_Xilinx_3S250E-3338.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/79/Fritz%21Box_Fon_WLAN_7270_-_Xilinx_3S250E-3338.jpg/440px-Fritz%21Box_Fon_WLAN_7270_-_Xilinx_3S250E-3338.jpg 2x" data-file-width="1804" data-file-height="1804" /></a><figcaption>Xilinx 3S250, Spartan-3E FPGA family</figcaption></figure> The Spartan series targets low cost, high-volume applications with a low-power footprint e.g. <a href="/wiki/Displays" class="mw-redirect" title="Displays">displays</a>, <a href="/wiki/Set-top_boxes" class="mw-redirect" title="Set-top boxes">set-top boxes</a>, <a href="/wiki/Wireless_router" title="Wireless router">wireless routers</a> and other applications.<a href="#cite_note-spartan-173">[173]</a> The Spartan-6 family is built on a 45nm, 9-metal layer, dual-oxide process technology.<a href="#cite_note-eetimes-150">[150]</a><a href="#cite_note-spartanrelease-174">[174]</a> The Spartan-6 was marketed in 2009 as a low-cost option for automotive, wireless communications, flat-panel display and video surveillance applications.<a href="#cite_note-spartanrelease-174">[174]</a> The Spartan-7 family, built on the same 28<a href="/wiki/Nanometer" class="mw-redirect" title="Nanometer">nm</a> process used in the other 7-Series FPGAs, was announced in 2015,<a href="#cite_note-spartan7announce-155">[155]</a> and became available in 2017.<a href="#cite_note-spartan7prod-156">[156]</a> Unlike the Artix-7 family and the "LXT" members of the Spartan-6 family, the Spartan-7 FPGAs lack high-bandwidth transceivers.<a href="#cite_note-costOptimizedPortfolio2017-168">[168]</a> <div class="mw-heading mw-heading3"><h3 id="EasyPath">EasyPath</h3>[<a href="/w/index.php?title=Xilinx&action=edit&section=13" title="Edit section: EasyPath">edit</a>]</div> Because EasyPath devices are identical to the FPGAs that customers are already using the parts can be produced faster and more reliably from the time they are ordered compared to similar competing programs.<a href="#cite_note-thirtyone-175">[175]</a> <div class="mw-heading mw-heading3"><h3 id="Versal">Versal</h3>[<a href="/w/index.php?title=Xilinx&action=edit&section=14" title="Edit section: Versal">edit</a>]</div> Versal is Xilinx's 7nm architecture that targets <a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">heterogeneous computing</a> needs in datacenter acceleration applications, in <a href="/wiki/Artificial_intelligence" title="Artificial intelligence">artificial intelligence</a> acceleration at the <a href="/wiki/Edge_computing" title="Edge computing">edge</a>, <a href="/wiki/Internet_of_things" title="Internet of things">Internet of things</a> (IoT) applications and <a href="/wiki/Embedded_computing" class="mw-redirect" title="Embedded computing">embedded computing</a>. The Everest program focuses on the Versal Adaptive Compute Acceleration Platform (ACAP), a product category combining a traditional FPGA fabric with an <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a> <a href="/wiki/System_on_chip" class="mw-redirect" title="System on chip">system on chip</a> and a set of <a href="/wiki/Coprocessor" title="Coprocessor">coprocessors</a>, connected through a <a href="/wiki/Network_on_a_chip" title="Network on a chip">network on a chip</a>.<a href="#cite_note-VB20190618-176">[176]</a> Xilinx's goal was to reduce the barriers to adoption of FPGAs for accelerated compute-intensive datacenter workloads.<a href="#cite_note-FBS26Mar2018-177">[177]</a> They are designed for a wide range of applications in the fields of <a href="/wiki/Big_data" title="Big data">big data</a> and <a href="/wiki/Machine_learning" title="Machine learning">machine learning</a>, including video transcoding, database querying, data compression, search, <a href="/wiki/Inference#Inference_engines" title="Inference">AI inferencing</a>, <a href="/wiki/Machine_vision" title="Machine vision">machine vision</a>, <a href="/wiki/Computer_vision" title="Computer vision">computer vision</a>, <a href="/wiki/Vehicular_automation" title="Vehicular automation">autonomous vehicles</a>, <a href="/wiki/Genomics" title="Genomics">genomics</a>, computational storage and network acceleration.<a href="#cite_note-VB20190618-176">[176]</a> On April 15, 2020, it was announced that Xilinx would supply its Versal chips to <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a> for 5G networking equipment.<a href="#cite_note-178">[178]</a> In July 2021, Xilinx debuted the Versal HBM, which combines the network interface of the platform with <a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM2e</a> memory to alleviate data bottlenecking.<a href="#cite_note-179">[179]</a> <div class="mw-heading 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Retrieved 2019-05-29.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Electronics+360&rft.atitle=Xilinx+to+buy+network+interface+card+vendor+Solarflare&rft_id=https%3A%2F%2Felectronics360.globalspec.com%2Farticle%2F13677%2Fxilinx-to-buy-network-interface-card-vendor-solarflare&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXilinx" class="Z3988"> </li> <li id="cite_note-Xilinx_to_Acquire_Solarflare-81">^ <a href="#cite_ref-Xilinx_to_Acquire_Solarflare_81-0">a</a> <a href="#cite_ref-Xilinx_to_Acquire_Solarflare_81-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.hpcwire.com/off-the-wire/xilinx-to-acquire-solarflare/">"Xilinx to Acquire Solarflare"</a>. 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EE Times. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190802185804/https://www.eetimes.com/document.asp?doc_id=1334613">Archived</a> from the original on 2019-08-02. Retrieved 2019-06-04.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=EE+Times&rft.atitle=Xilinx+to+Buy+Networking+Technology+Firm+Solarflare&rft.aulast=McGrath&rft.aufirst=Dylan&rft_id=https%3A%2F%2Fwww.eetimes.com%2Fdocument.asp%3Fdoc_id%3D1334613%23&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXilinx" class="Z3988"> </li> <li id="cite_note-85"><a href="#cite_ref-85">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFManners2019" class="citation web cs1">Manners, David (2019-08-22). <a rel="nofollow" class="external text" href="https://www.electronicsweekly.com/news/business/xilinx-claims-worlds-largest-fpga-2019-08/">"Xilinx claims world's largest FPGA"</a>. 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Retrieved 2019-09-20.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=Xilinx+Announces+World+Largest+FPGA%3A+Virtex+Ultrascale%2B+VU19P+with+9m+Cells&rft.aulast=Cutress&rft.aufirst=Dr+Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F14798%2Fxilinx-announces-world-largest-fpga-virtex-ultrascale-vu19p-with-9m-cells&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXilinx" class="Z3988"> </li> <li id="cite_note-87"><a href="#cite_ref-87">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.allaboutcircuits.com/news/xilinx-claims-title-of-worlds-largest-fpga-with-new-vu19p/">"Xilinx Claims Title of "World's Largest FPGA" with New VU19P"</a>. www.allaboutcircuits.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190920135958/https://www.allaboutcircuits.com/news/xilinx-claims-title-of-worlds-largest-fpga-with-new-vu19p/">Archived</a> from the original on 2019-09-20. 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Retrieved 2020-03-09.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=VentureBeat&rft.atitle=Xilinx+ships+first+Versal+ACAP+chips+that+adapt+to+AI+programs&rft.date=2019-06-18&rft_id=https%3A%2F%2Fventurebeat.com%2F2019%2F06%2F18%2Fxilinx-ships-first-versal-acap-chips-that-adapt-to-ai-programs%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXilinx" class="Z3988"> </li> <li id="cite_note-90"><a href="#cite_ref-90">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDignan" class="citation web cs1">Dignan, Larry. <a rel="nofollow" class="external text" href="https://www.zdnet.com/article/xilinx-ships-its-versal-ai-core-versal-prime-key-parts-of-its-adaptive-compute-acceleration-platform/">"Xilinx ships its Versal AI Core, Versal Prime, key parts of its adaptive compute acceleration platform"</a>. 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Retrieved 2020-03-09.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ZDNet&rft.atitle=Xilinx+ships+its+Versal+AI+Core%2C+Versal+Prime%2C+key+parts+of+its+adaptive+compute+acceleration+platform&rft.aulast=Dignan&rft.aufirst=Larry&rft_id=https%3A%2F%2Fwww.zdnet.com%2Farticle%2Fxilinx-ships-its-versal-ai-core-versal-prime-key-parts-of-its-adaptive-compute-acceleration-platform%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXilinx" class="Z3988"> </li> <li id="cite_note-91"><a href="#cite_ref-91">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAltavilla" class="citation web cs1">Altavilla, Dave. <a rel="nofollow" class="external text" href="https://www.forbes.com/sites/davealtavilla/2019/10/01/xilinx-unveils-vitis-disruptive-open-source-design-software-tools-for-adaptable-processing-engines/">"Xilinx Unveils Vitis, Breakthrough Open-Source Design Software For Adaptable Processing Engines"</a>. Forbes. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20191029175220/https://www.forbes.com/sites/davealtavilla/2019/10/01/xilinx-unveils-vitis-disruptive-open-source-design-software-tools-for-adaptable-processing-engines/">Archived</a> from the original on 2019-10-29. Retrieved 2019-10-29.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Forbes&rft.atitle=Xilinx+Unveils+Vitis%2C+Breakthrough+Open-Source+Design+Software+For+Adaptable+Processing+Engines&rft.aulast=Altavilla&rft.aufirst=Dave&rft_id=https%3A%2F%2Fwww.forbes.com%2Fsites%2Fdavealtavilla%2F2019%2F10%2F01%2Fxilinx-unveils-vitis-disruptive-open-source-design-software-tools-for-adaptable-processing-engines%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXilinx" class="Z3988"> </li> <li id="cite_note-92"><a href="#cite_ref-92">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.semiaccurate.com/2019/10/07/xilinx-updates-their-tool-suite-with-vitis/">"Xilinx updates their tool suite with Vitis"</a>. SemiAccurate. 2019-10-07. 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Retrieved 2014-06-20.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Axiom+Alpha&rft_id=https%3A%2F%2Fwww.apertus.org%2Falpha_prototype&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXilinx" class="Z3988"> </li> <li id="cite_note-172"><a href="#cite_ref-172">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://forums.xilinx.com/t5/Xcell-Daily-Blog/Zynq-based-Axiom-Alpha-open-4K-cine-camera-proto-debuts-in/ba-p/430066">"Zynq-based Axiom Alpha open 4K cine camera proto debuts in Vienna hackerspace"</a>. 2014-03-20. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20140813105309/http://forums.xilinx.com/t5/Xcell-Daily-Blog/Zynq-based-Axiom-Alpha-open-4K-cine-camera-proto-debuts-in/ba-p/430066">Archived</a> from the original on 2014-08-13. Retrieved 2014-06-20.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Zynq-based+Axiom+Alpha+open+4K+cine+camera+proto+debuts+in+Vienna+hackerspace&rft.date=2014-03-20&rft_id=http%3A%2F%2Fforums.xilinx.com%2Ft5%2FXcell-Daily-Blog%2FZynq-based-Axiom-Alpha-open-4K-cine-camera-proto-debuts-in%2Fba-p%2F430066&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXilinx" class="Z3988"> </li> <li id="cite_note-spartan-173"><a href="#cite_ref-spartan_173-0">^</a> Daniel Harris, Electronic Design. "<a rel="nofollow" class="external text" href="http://electronicdesign.com/Articles/Index.cfm?AD=1&ArticleID=18342">If only the original spartans could have thrived on so little power</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090302010210/http://electronicdesign.com/Articles/Index.cfm?AD=1&ArticleID=18342">Archived</a> 2009-03-02 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>." February 27, 2008. Retrieved January 20, 2008. </li> <li id="cite_note-spartanrelease-174">^ <a href="#cite_ref-spartanrelease_174-0">a</a> <a href="#cite_ref-spartanrelease_174-1">b</a> Company Release. "<a rel="nofollow" class="external text" href="http://news.prnewswire.com/ViewContent.aspx?ACCT=109&STORY=/www/story/02-02-2009/0004964201&EDATE">The low-cost Spartan-6 FPGA family delivers an optimal balance of low risk, low cost, low power, and high performance</a> [<a href="/wiki/Wikipedia:Link_rot" title="Wikipedia:Link rot">dead link</a>‍]." February 2, 2009. </li> <li id="cite_note-thirtyone-175"><a href="#cite_ref-thirtyone_175-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMorris" class="citation web cs1">Morris, Kevin. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090327150947/http://www.fpgajournal.com/articles_2008/pdf/20080527_easypath.pdf">"Not Bad Die: Xilinx EasyPath Explained"</a> (PDF). FPGA Journal. Archived from <a rel="nofollow" class="external text" href="http://www.fpgajournal.com/articles_2008/pdf/20080527_easypath.pdf">the original</a> (PDF) on 27 March 2009. Retrieved 20 January 2008.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=FPGA+Journal&rft.atitle=Not+Bad+Die%3A+Xilinx+EasyPath+Explained&rft.aulast=Morris&rft.aufirst=Kevin&rft_id=http%3A%2F%2Fwww.fpgajournal.com%2Farticles_2008%2Fpdf%2F20080527_easypath.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXilinx" class="Z3988"> </li> <li id="cite_note-VB20190618-176">^ <a href="#cite_ref-VB20190618_176-0">a</a> <a href="#cite_ref-VB20190618_176-1">b</a> "<a rel="nofollow" class="external text" href="https://venturebeat.com/2019/06/18/xilinx-ships-first-versal-acap-chips-that-adapt-to-ai-programs/">Xilinx ships first Versal ACAP chips that adapt to AI programs</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200521204130/https://venturebeat.com/2019/06/18/xilinx-ships-first-versal-acap-chips-that-adapt-to-ai-programs/">Archived</a> 2020-05-21 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>." June 18, 2019. Retrieved Feb 26, 2020. </li> <li id="cite_note-FBS26Mar2018-177"><a href="#cite_ref-FBS26Mar2018_177-0">^</a> Karl Freund, <a href="/wiki/Forbes_(magazine)" class="mw-redirect" title="Forbes (magazine)">Forbes (magazine)</a>. "<a rel="nofollow" class="external text" href="https://www.forbes.com/sites/moorinsights/2018/03/26/xilinx-everest-enabling-fpga-acceleration-with-acap/#5b2a9b6b342e">Xilinx Everest: Enabling FPGA Acceleration With ACAP</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180612144257/https://www.forbes.com/sites/moorinsights/2018/03/26/xilinx-everest-enabling-fpga-acceleration-with-acap/#5b2a9b6b342e">Archived</a> 2018-06-12 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>." March 26, 2018. Retrieved April 26, 2018. </li> <li id="cite_note-178"><a href="#cite_ref-178">^</a> "<a rel="nofollow" class="external text" href="https://www.platformexecutive.com/news/mobile-telecoms-infrastructure/samsung-to-tap-xilinx-chips-for-5g-network-equipment/">Samsung to tap Xilinx chips for 5G network equipment</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20201011022347/https://www.platformexecutive.com/news/mobile-telecoms-infrastructure/samsung-to-tap-xilinx-chips-for-5g-network-equipment/">Archived</a> 2020-10-11 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>." Apr 16, 2020. Retrieved April 16, 2020. </li> <li id="cite_note-179"><a href="#cite_ref-179">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMcGregor" class="citation web cs1">McGregor, Jim. <a rel="nofollow" class="external text" href="https://www.forbes.com/sites/tiriasresearch/2021/07/15/xilinx-ups-the-ante-in-high-performance-processing-with-versal-hbm/?sh=4d3955f455e1">"Xilinx Ups The Ante In High-Performance Processing With Versal HBM"</a>. Forbes. Retrieved 28 September 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Forbes&rft.atitle=Xilinx+Ups+The+Ante+In+High-Performance+Processing+With+Versal+HBM&rft.aulast=McGregor&rft.aufirst=Jim&rft_id=https%3A%2F%2Fwww.forbes.com%2Fsites%2Ftiriasresearch%2F2021%2F07%2F15%2Fxilinx-ups-the-ante-in-high-performance-processing-with-versal-hbm%2F%3Fsh%3D4d3955f455e1&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXilinx" class="Z3988"> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2>[<a href="/w/index.php?title=Xilinx&action=edit&section=17" title="Edit section: External links">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1235681985">.mw-parser-output .side-box{margin:4px 0;box-sizing:border-box;border:1px solid #aaa;font-size:88%;line-height:1.25em;background-color:var(--background-color-interactive-subtle,#f8f9fa);display:flow-root}.mw-parser-output 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PowerTune">AMD PowerTune</a></li> <li><a href="/wiki/AMD_CrossFire" title="AMD CrossFire">CrossFire</a></li> <li><a href="/wiki/AMD_Eyefinity" title="AMD Eyefinity">Eyefinity</a></li> <li><a href="/wiki/FreeSync" title="FreeSync">FreeSync</a></li> <li><a href="/wiki/Mantle_(API)" title="Mantle (API)">Mantle</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Processor</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AGESA" title="AGESA">AGESA</a></li> <li><a href="/wiki/AMD_Turbo_Core" title="AMD Turbo Core">AMD Turbo Core</a></li> <li><a href="/wiki/Cool%27n%27Quiet" title="Cool'n'Quiet">Cool'n'Quiet</a></li> <li><a href="/wiki/AMD_Platform_Security_Processor" title="AMD Platform Security Processor">AMD Platform Security Processor</a></li> <li><a href="/wiki/Ryzen_AI" class="mw-redirect" title="Ryzen AI">Ryzen AI</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Memory</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a> (HBM)</li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Sockets</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><td class="navbox-abovebelow" colspan="2"><div id="Sockets_without_existing_articles_(e.g._FP4)_are_omitted_from_this_section.">Sockets without existing articles (e.g. FP4) are omitted from this section.</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Desktop</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Pin_grid_array" title="Pin grid array">Pin grid array</a> (PGA)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Super_Socket_7" title="Super Socket 7">Super Socket 7</a> (Super 7)</li> <li><a href="/wiki/Socket_939" title="Socket 939">939</a></li> <li><a href="/wiki/Socket_AM2" title="Socket AM2">AM2</a></li> <li><a href="/wiki/Socket_AM2%2B" title="Socket AM2+">AM2+</a></li> <li><a href="/wiki/Socket_AM3" title="Socket AM3">AM3</a></li> <li><a href="/wiki/Socket_AM3%2B" title="Socket AM3+">AM3+</a></li> <li><a href="/wiki/Socket_FM1" title="Socket FM1">FM1</a></li> <li><a href="/wiki/Socket_FM2" title="Socket FM2">FM2</a></li> <li><a href="/wiki/Socket_FM2%2B" title="Socket FM2+">FM2+</a></li> <li><a href="/wiki/Socket_AM1" title="Socket AM1">AM1</a></li> <li><a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Land_grid_array" title="Land grid array">Land grid array</a> (LGA)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_TR4" title="Socket TR4">TR4</a></li> <li><a href="/wiki/Socket_sTRX4" title="Socket sTRX4">sTRX4</a></li> <li><a href="/wiki/Socket_AM5" title="Socket AM5">AM5</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Slot_A" title="Slot A">Slot A</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Mobile</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Pin grid array (PGA)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_563" title="Socket 563">563</a></li> <li><a href="/wiki/Socket_S1" title="Socket S1">S1</a></li> <li><a href="/wiki/Socket_FS1" title="Socket FS1">FS1</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Ball_grid_array" title="Ball grid array">Ball grid array</a> (BGA)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_FT1" title="Socket FT1">FT1</a></li> <li><a href="/wiki/Socket_FP2" title="Socket FP2">FP2</a></li> <li><a href="/wiki/Socket_FT3" title="Socket FT3">FT3</a></li> <li><a href="/wiki/Socket_FP3" title="Socket FP3">FP3</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Server</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Pin grid array (PGA)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_940" title="Socket 940">940</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Land grid array (LGA)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_F" title="Socket F">F</a></li> <li><a href="/wiki/Socket_F%2B" title="Socket F+">F+</a></li> <li><s><a href="/wiki/AMD_Socket_G3" title="AMD Socket G3">G3</a></s></li> <li><a href="/wiki/Socket_G34" title="Socket G34">G34</a></li> <li><a href="/wiki/Socket_C32" title="Socket C32">C32</a></li> <li><a href="/wiki/Socket_SP3" title="Socket SP3">SP3</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Mixed</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="Pin_grid_array_(PGA)" scope="row" class="navbox-group" style="width:1%">Pin grid array (PGA)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_A" title="Socket A">Socket A</a> (Socket 462)</li> <li><a href="/wiki/Socket_754" title="Socket 754">754</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Product lists</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_AMD_microprocessors" class="mw-redirect" title="List of AMD microprocessors">List of AMD microprocessors</a></li> <li><a href="/wiki/List_of_AMD_graphics_processing_units" title="List of AMD graphics processing units">List of AMD graphics processing units</a></li> <li><a href="/wiki/List_of_AMD_accelerated_processing_units" class="mw-redirect" title="List of AMD accelerated processing units">List of AMD accelerated processing units</a></li> <li><a href="/wiki/List_of_AMD_CPU_microarchitectures" title="List of AMD CPU microarchitectures">List of AMD CPU microarchitectures</a></li> <li><a href="/wiki/List_of_AMD_chipsets" title="List of AMD chipsets">List of AMD chipsets</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Category:AMD_people" title="Category:AMD people">People</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Founders</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Jerry_Sanders_(businessman)" title="Jerry Sanders (businessman)">Jerry Sanders</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">CEOs</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Jerry Sanders (1969–2002)</li> <li><a href="/wiki/Hector_Ruiz" title="Hector Ruiz">Hector Ruiz</a> (2002–2008)</li> <li><a href="/wiki/Dirk_Meyer" title="Dirk Meyer">Dirk Meyer</a> (2008–2011)</li> <li><a href="/wiki/Rory_Read" title="Rory Read">Rory Read</a> (2011–2014)</li> <li><a href="/wiki/Lisa_Su" title="Lisa Su">Lisa Su</a> (2014–present)</li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Acquisitions</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ATI_Technologies" title="ATI Technologies">ATI Technologies</a></li> <li><a href="/wiki/SeaMicro" title="SeaMicro">SeaMicro</a></li> <li><a class="mw-selflink selflink">Xilinx</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Joint ventures</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD%E2%80%93Chinese_joint_venture" title="AMD–Chinese joint venture">AMD–Chinese joint venture</a> <ul><li><a href="/wiki/Hygon_Information_Technology" title="Hygon Information Technology">Hygon Information Technology</a></li></ul></li> <li>TF-AMD <ul><li><a href="/wiki/Tongfu_Microelectronics" title="Tongfu Microelectronics">Tongfu Microelectronics</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Litigation</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Corp._v._Advanced_Micro_Devices,_Inc." title="Intel Corp. v. Advanced Micro Devices, Inc.">Intel Corp. v. Advanced Micro Devices, Inc.</a> (2004)</li> <li><a href="/wiki/Advanced_Micro_Devices,_Inc._v._Intel_Corp." title="Advanced Micro Devices, Inc. v. Intel Corp.">Advanced Micro Devices, Inc. v. Intel Corp.</a> (2005)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Vulkan_(API)" class="mw-redirect" title="Vulkan (API)">Vulkan (API)</a></li> <li><a href="/wiki/NexGen" title="NexGen">NexGen</a></li> <li><a href="/wiki/Spansion" title="Spansion">Spansion</a></li> <li><a href="/wiki/AMD_Live!" title="AMD Live!">AMD Live!</a></li> <li><a href="/wiki/Performance_Rating" title="Performance Rating">Performance Rating</a></li> <li><a href="/wiki/Torrenza" title="Torrenza">Torrenza</a></li> <li><a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div> <ul><li>Italics indicates an unreleased product (e.g. socket)</li> <li><s>Strikethrough</s> indicates a product that was never released.</li> <li>Mixed indicates sockets that are designed for or integrated with one or more platforms.</li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Programmable_logic" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Programmable_logic" title="Template:Programmable logic"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Programmable_logic" title="Template talk:Programmable logic"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Programmable_logic" title="Special:EditPage/Template:Programmable logic"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Programmable_logic" style="font-size:114%;margin:0 4em"><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Concepts</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a> <ul><li><a href="/wiki/Logic_block" title="Logic block">Logic block</a></li></ul></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Programmable_logic_device#EPLDs" title="Programmable logic device">EPLD</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">PLA</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Generic_array_logic" class="mw-redirect" title="Generic array logic">GAL</a></li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">PSoC</a></li> <li><a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a> <ul><li><a href="/wiki/Xputer" title="Xputer">Xputer</a></li></ul></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li> <li><a href="/wiki/Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Verilog" title="Verilog">Verilog</a> <ul><li><a href="/wiki/Verilog-A" title="Verilog-A">A</a></li> <li><a href="/wiki/Verilog-AMS" title="Verilog-AMS">AMS</a></li></ul></li> <li><a href="/wiki/VHDL" title="VHDL">VHDL</a> <ul><li><a href="/wiki/VHDL-AMS" title="VHDL-AMS">AMS</a></li> <li><a href="/wiki/VHDL-VITAL" title="VHDL-VITAL">VITAL</a></li></ul></li> <li><a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a> <ul><li><a href="/wiki/SystemVerilog_DPI" title="SystemVerilog DPI">DPI</a></li></ul></li> <li><a href="/wiki/SystemC" title="SystemC">SystemC</a></li> <li><a href="/wiki/Altera_Hardware_Description_Language" title="Altera Hardware Description Language">AHDL</a></li> <li><a href="/wiki/Handel-C" title="Handel-C">Handel-C</a></li> <li><a href="/wiki/Lola_(computing)" title="Lola (computing)">Lola</a></li> <li><a href="/wiki/Property_Specification_Language" title="Property Specification Language">PSL</a></li> <li><a href="/wiki/Unified_Power_Format" title="Unified Power Format">UPF</a></li> <li><a href="/wiki/PALASM" title="PALASM">PALASM</a></li> <li><a href="/wiki/Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a></li> <li><a href="/wiki/Programmable_Array_Logic#CUPL" title="Programmable Array Logic">CUPL</a></li> <li><a href="/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li> <li><a href="/wiki/Flow_to_HDL" title="Flow to HDL">Flow to HDL</a></li> <li><a href="/wiki/MyHDL" title="MyHDL">MyHDL</a></li> <li><a href="/wiki/ELLA_(programming_language)" title="ELLA (programming language)">ELLA</a></li> <li><a href="/wiki/Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Accellera" title="Accellera">Accellera</a></li> <li><a href="/wiki/Achronix" title="Achronix">Achronix</a></li> <li><a href="/wiki/AMD" title="AMD">AMD</a></li> <li><a href="/wiki/Aldec" title="Aldec">Aldec</a></li> <li><a href="/wiki/Arm_Holdings" title="Arm Holdings">Arm</a></li> <li><a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li> <li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a></li> <li><a href="/wiki/Intel" title="Intel">Intel</a></li> <li><a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li> <li><a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a></li> <li><a href="/wiki/Siemens" title="Siemens">Siemens</a></li> <li><a href="/wiki/Synopsys" title="Synopsys">Synopsys</a></li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ICE_(FPGA)" title="ICE (FPGA)">iCE</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Quartus_Prime" title="Intel Quartus Prime">Intel Quartus Prime</a></li> <li><a href="/wiki/Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li> <li><a href="/wiki/Vivado" title="Vivado">Vivado</a></li> <li><a href="/wiki/ModelSim" title="ModelSim">ModelSim</a></li> <li><a href="/wiki/Verilog-to-Routing" title="Verilog-to-Routing">VTR</a></li> <li><a href="/wiki/List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Intellectual_property" title="Intellectual property">Intellectual property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li> <li><a href="/wiki/LEON" title="LEON">LEON</a></li> <li><a href="/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a></li> <li><a href="/wiki/Nios_embedded_processor" title="Nios embedded processor">Nios</a></li> <li><a href="/wiki/Nios_II" title="Nios II">Nios II</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Java_Optimized_Processor" title="Java Optimized Processor">JOP</a></li> <li><a href="/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a></li> <li><a href="/wiki/OpenCores" title="OpenCores">OpenCores</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a> <ul><li><a href="/wiki/OpenRISC_1200" title="OpenRISC 1200">1200</a></li></ul></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <ul><li><a href="/wiki/Libre-SOC" title="Libre-SOC">Libre-SOC</a></li> <li><a href="/wiki/OpenPOWER_Microwatt" title="OpenPOWER Microwatt">Microwatt</a></li></ul></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/Zet_(hardware)" title="Zet (hardware)">Zet</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox authority-control" aria-labelledby="Authority_control_databases_frameless&#124;text-top&#124;10px&#124;alt=Edit_this_at_Wikidata&#124;link=https&#58;//www.wikidata.org/wiki/Q1046482#identifiers&#124;class=noprint&#124;Edit_this_at_Wikidata" style="padding:3px"><table class="nowraplinks hlist mw-collapsible expanded navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Authority_control_databases_frameless&#124;text-top&#124;10px&#124;alt=Edit_this_at_Wikidata&#124;link=https&#58;//www.wikidata.org/wiki/Q1046482#identifiers&#124;class=noprint&#124;Edit_this_at_Wikidata" style="font-size:114%;margin:0 4em"><a href="/wiki/Help:Authority_control" title="Help:Authority control">Authority control databases</a> <a href="https://www.wikidata.org/wiki/Q1046482#identifiers" title="Edit this at Wikidata"><img alt="Edit this at Wikidata" src="//upload.wikimedia.org/wikipedia/en/thumb/8/8a/OOjs_UI_icon_edit-ltr-progressive.svg/10px-OOjs_UI_icon_edit-ltr-progressive.svg.png" decoding="async" width="10" height="10" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/8/8a/OOjs_UI_icon_edit-ltr-progressive.svg/15px-OOjs_UI_icon_edit-ltr-progressive.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/8/8a/OOjs_UI_icon_edit-ltr-progressive.svg/20px-OOjs_UI_icon_edit-ltr-progressive.svg.png 2x" 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