<?xml version="1.0" encoding="UTF-8"?> <article key="pdf/8858" mdate="2009-06-22 00:00:00"> <author>Haruo Shimada and Akinori Kanasugi</author> <title>A Dynamically Reconfigurable Arithmetic Circuit for Complex Number and Double Precision Number</title> <pages>1325 - 1331</pages> <year>2009</year> <volume>3</volume> <number>6</number> <journal>International Journal of Electrical and Computer Engineering</journal> <ee>https://publications.waset.org/pdf/8858</ee> <url>https://publications.waset.org/vol/30</url> <publisher>World Academy of Science, Engineering and Technology</publisher> <abstract>This paper proposes an architecture of dynamically reconfigurable arithmetic circuit. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operations. The proposed circuit is based on a complex number multiplyaccumulation circuit which is used frequently in the field of digital signal processing. In addition, the proposed circuit performs real number double precision arithmetic operations. The data formats are single and double precision floating point number based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.</abstract> <index>Open Science Index 30, 2009</index> </article>