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<span>Physical</span> </div> </a> <ul id="toc-Physical-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Electrical" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Electrical"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.5</span> <span>Electrical</span> </div> </a> <ul id="toc-Electrical-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-SPARC64_V+" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#SPARC64_V+"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>SPARC64 V+</span> </div> </a> <ul id="toc-SPARC64_V+-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SPARC64_VI" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#SPARC64_VI"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>SPARC64 VI</span> </div> </a> <ul id="toc-SPARC64_VI-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SPARC64_VII" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#SPARC64_VII"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>SPARC64 VII</span> </div> </a> <ul id="toc-SPARC64_VII-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SPARC64_VII+" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#SPARC64_VII+"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>SPARC64 VII+</span> </div> </a> <ul id="toc-SPARC64_VII+-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SPARC64_VIIIfx" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#SPARC64_VIIIfx"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>SPARC64 VIIIfx</span> </div> </a> <button aria-controls="toc-SPARC64_VIIIfx-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle SPARC64 VIIIfx subsection</span> </button> <ul id="toc-SPARC64_VIIIfx-sublist" class="vector-toc-list"> <li id="toc-History_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#History_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.1</span> <span>History</span> </div> </a> <ul id="toc-History_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Description_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Description_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.2</span> <span>Description</span> </div> </a> <ul id="toc-Description_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Miscellaneous_specifications" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Miscellaneous_specifications"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.3</span> <span>Miscellaneous specifications</span> </div> </a> <ul id="toc-Miscellaneous_specifications-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-SPARC64_IXfx" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#SPARC64_IXfx"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>SPARC64 IXfx</span> </div> </a> <ul id="toc-SPARC64_IXfx-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SPARC64_X" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#SPARC64_X"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>SPARC64 X</span> </div> </a> <ul id="toc-SPARC64_X-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SPARC64_X+" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#SPARC64_X+"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>SPARC64 X+</span> </div> </a> <ul id="toc-SPARC64_X+-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SPARC64_XIfx" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#SPARC64_XIfx"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>SPARC64 XIfx</span> </div> </a> <button aria-controls="toc-SPARC64_XIfx-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle SPARC64 XIfx subsection</span> </button> <ul id="toc-SPARC64_XIfx-sublist" class="vector-toc-list"> <li id="toc-Future" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Future"> <div class="vector-toc-text"> <span class="vector-toc-numb">11.1</span> <span>Future</span> </div> </a> <ul id="toc-Future-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-SPARC64_XII" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#SPARC64_XII"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>SPARC64 XII</span> </div> </a> <ul id="toc-SPARC64_XII-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">13</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Sources" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Sources"> <div class="vector-toc-text"> <span class="vector-toc-numb">14</span> <span>Sources</span> </div> </a> <ul id="toc-Sources-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">15</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">16</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav 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class="firstHeading mw-first-heading"><span class="mw-page-title-main">SPARC64 V</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. 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interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/SPARC64_V" title="SPARC64 V – Catalan" lang="ca" hreflang="ca" data-title="SPARC64 V" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/SPARC64_V" title="SPARC64 V – German" lang="de" hreflang="de" data-title="SPARC64 V" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/SPARC64_V" title="SPARC64 V – Hungarian" lang="hu" hreflang="hu" data-title="SPARC64 V" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/SPARC64_V" title="SPARC64 V – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="SPARC64 V" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/SPARC64_V" title="SPARC64 V – Russian" lang="ru" hreflang="ru" data-title="SPARC64 V" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q669497#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> 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</div> </div> <div id="bodyContent" class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"><span class="mw-redirectedfrom">(Redirected from <a href="/w/index.php?title=SPARC64_VI&redirect=no" class="mw-redirect" title="SPARC64 VI">SPARC64 VI</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Microprocessor designed by Fujitsu</div> <p class="mw-empty-elt"> </p> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">SPARC64 V</caption><tbody><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:SPARC64_logo.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/en/thumb/0/0b/SPARC64_logo.svg/220px-SPARC64_logo.svg.png" decoding="async" width="220" height="82" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/0/0b/SPARC64_logo.svg/330px-SPARC64_logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/0/0b/SPARC64_logo.svg/440px-SPARC64_logo.svg.png 2x" data-file-width="126" data-file-height="47" /></a></span></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2001</td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data"><a href="/wiki/Fujitsu" title="Fujitsu">Fujitsu</a></td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.10 GHz to 1.35 GHz</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/SPARC_V9" class="mw-redirect" title="SPARC V9">SPARC V9</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li>1</li></ul></div></td></tr></tbody></table> <p>The <b>SPARC64 V</b> (<i>Zeus</i>) is a <a href="/wiki/SPARC" title="SPARC">SPARC V9</a> <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a> designed by <a href="/wiki/Fujitsu" title="Fujitsu">Fujitsu</a>.<sup id="cite_ref-ReferenceA_1-0" class="reference"><a href="#cite_note-ReferenceA-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> The SPARC64 V was the basis for a series of successive processors designed for servers, and later, supercomputers. </p><p>The servers series are the SPARC64 V+, VI, VI+, VII, VII+, X, X+ and XII. The SPARC64 VI and its successors up to the VII+ were used in the Fujitsu and Sun (later <a href="/wiki/Oracle_Corporation" title="Oracle Corporation">Oracle</a>) <a href="/wiki/SPARC_Enterprise" title="SPARC Enterprise">SPARC Enterprise M-Series</a> servers. In addition to servers, a version of the SPARC64 VII was also used in the commercially available Fujitsu FX1 supercomputer. As of October 2017, the SPARC64 XII is the latest server processor, and it is used in the Fujitsu and Oracle M12 servers. </p><p>The supercomputer series was based on the SPARC64 VII, and are the SPARC64 VIIfx, IXfx, and XIfx. The SPARC64 VIIIfx was used in the <a href="/wiki/K_computer" title="K computer">K computer</a>, and the SPARC64 IXfx in the commercially available <a href="/wiki/PRIMEHPC_FX10" title="PRIMEHPC FX10">PRIMEHPC FX10</a>. As of July 2016, the SPARC64 XIfx is the latest supercomputer processor, and it is used in the Fujitsu PRIMEHPC FX100 supercomputer. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In the late 1990s, <a href="/wiki/HAL_Computer_Systems" title="HAL Computer Systems">HAL Computer Systems</a>, a subsidiary of Fujitsu, was designing a successor to the <a href="/wiki/HAL_SPARC64#SPARC64_GP" title="HAL SPARC64">SPARC64 GP</a> as the SPARC64 V. First announced at Microprocessor Forum 1999, the HAL SPARC64 V would have operated 1 GHz and had a wide <a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> organization with <a href="/wiki/Speculative_execution" title="Speculative execution">superspeculation</a>, an L1 instruction <a href="/wiki/Trace_cache" title="Trace cache">trace cache</a>, a small but very fast 8 KB L1 data cache, and separate L2 caches for instructions and data. It was designed in Fujitsu's CS85 process, a 0.17 μm CMOS process with six levels of copper interconnect; and would have consisted of 65 million transistors on a 380 mm<sup>2</sup> die. Originally scheduled for a late 2001 release in Fujitsu GranPower servers, it was canceled in mid-2001 when HAL was closed by Fujitsu, and replaced by a Fujitsu design.<sup id="cite_ref-Diefendorff:1999-11-15_2-0" class="reference"><a href="#cite_note-Diefendorff:1999-11-15-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p>The first Fujitsu SPARC64 Vs were fabricated in December 2001.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> They operated at 1.1 to 1.35 GHz. Fujitsu's 2003 SPARC64 roadmap showed that the company planned a 1.62 GHz version for release in late 2003 or early 2004, but it was canceled in favor of the SPARC64 V+.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> The SPARC64 V was used by Fujitsu in their PRIMEPOWER servers. </p><p>The SPARC64 V was first presented at Microprocessor Forum 2002.<sup id="cite_ref-MPR-2002-10-21-P1_5-0" class="reference"><a href="#cite_note-MPR-2002-10-21-P1-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> At introduction, it had the highest clock frequency of both SPARC and 64-bit server processors in production; and the highest <a href="/wiki/SPEC" class="mw-redirect" title="SPEC">SPEC</a> rating of any SPARC processor.<sup id="cite_ref-MPR-2002-10-21-P1_5-1" class="reference"><a href="#cite_note-MPR-2002-10-21-P1-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Description">Description</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=2" title="Edit section: Description"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The SPARC64 V is a four-issue <a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> microprocessor with <a href="/wiki/Out-of-order_execution" title="Out-of-order execution">out-of-order execution</a>. It was based on the Fujitsu GS8900 <a href="/wiki/Mainframe_computer" title="Mainframe computer">mainframe</a> microprocessor.<sup id="cite_ref-ReferenceB_6-0" class="reference"><a href="#cite_note-ReferenceB-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Pipeline">Pipeline</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=3" title="Edit section: Pipeline"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The SPARC64 V fetches up to eight instructions from the instruction cache during the first stage and places them into a 48-entry instruction buffer. In the next stage, four instructions are taken from this buffer, decoded and issued to the appropriate reserve stations. The SPARC64 V has six reserve stations, two that serve the integer units, one for the address generators, two for the floating-point units, and one for branch instructions. Each integer, address generator and floating-point unit has an eight-entry reserve station. Each reserve station can dispatch an instruction to its execution unit. Which instruction is dispatched firstly depends on operand availability and then its age. Older instructions are given higher priority than newer ones. The reserve stations can dispatch instructions speculatively (speculative dispatch). That is, instructions can be dispatched to the execution units even when their operands are not yet available but will be when execution begins. During stage six, up to six instructions are dispatched. </p> <div class="mw-heading mw-heading4"><h4 id="Register_read">Register read</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=4" title="Edit section: Register read"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The register files are read during stage seven. The SPARC architecture has separate register files for integer and floating-point instructions. The integer register file has eight register windows. The JWR (Joint Work Register) contains 64 entries and has eight read ports and two write ports. The JWR contains a subset of the eight register windows, the previous, current and next register windows. Its purpose is reduce the size of register file so that the microprocessor can operate at higher clock frequencies. The floating-point register file contains 64 entries and has six read ports and two write ports. </p> <div class="mw-heading mw-heading4"><h4 id="Execution">Execution</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=5" title="Edit section: Execution"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Execution begins during stage nine. There are six execution units, two for integer, two for loads and stores, and two for floating-point.<sup id="cite_ref-MPR-2002-10-21-P2_7-0" class="reference"><a href="#cite_note-MPR-2002-10-21-P2-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> The two integer execution units are designated EXA and EXB. Both have an <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">arithmetic logic unit</a> (ALU) and a shift unit, but only EXA has multiply and divide units. Loads and stores are executed by two address generators (AGs) designated AGA and AGB. These are simple ALUs used to calculate virtual addresses. </p><p>The two floating-point units (FPUs) are designated FLA and FLB. Each FPU contains an adder and a multiplier, but only FLA has a graphics unit attached. They execute add, subtract, multiply, divide, square root and <a href="/wiki/Multiply%E2%80%93add" class="mw-redirect" title="Multiply–add">multiply–add</a> instructions. Unlike its successor <a href="/wiki/SPARC64_VI" class="mw-redirect" title="SPARC64 VI">SPARC64 VI</a>, the SPARC64 V performs the <a href="/wiki/Multiply%E2%80%93add" class="mw-redirect" title="Multiply–add">multiply–add</a> with separate multiplication and addition operations, thus with up to two rounding errors.<sup id="cite_ref-SPARC64_VI_Extensions_8-0" class="reference"><a href="#cite_note-SPARC64_VI_Extensions-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> The graphics unit executes <a href="/wiki/Visual_Instruction_Set" title="Visual Instruction Set">Visual Instruction Set</a> (VIS) instructions, a set of <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">single instruction, multiple data</a> (SIMD) instructions. All instructions are pipelined except for divide and square root, which are executed using iterative algorithms. The FMA instruction is implemented by reading three operands from the operand register, multiplying two of the operands, forwarding the result and the third operand to the adder, and adding them to produce the final result. </p><p>Results from the execution units and loads are not written to the register file. To maintain program order, they are written to update buffers, where they reside until committed. The SPARC64 V has separate update buffers for integer and floating-point units. Both have 32 entries each. The integer register has eight read ports and four write ports. Half of the write ports are used for results from the integer execution units and the other half by data returned by loads. The floating-point update buffer has six read ports and four write ports. </p><p>Commit takes place during stage ten at the earliest. The SPARC64 V can commit up to four instructions per cycle. During stage eleven, results are written to the register file, where it becomes visible to software.<sup id="cite_ref-HPCA-P4_9-0" class="reference"><a href="#cite_note-HPCA-P4-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Cache">Cache</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=6" title="Edit section: Cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The SPARC64 V has two-level cache hierarchy. The first level consists of two caches, an instruction cache and a data cache. The second level consists of an on-die unified cache. </p><p>The level 1 (L1) caches each have a capacity of 128 KB. They are both two-way set associative and have 64-byte line size. They are virtually indexed and physically tagged. The instruction cache is accessed via a 256-bit bus. The data cache is accessed with two 128-bit buses. The data cache consists of eight banks separated by 32-bit boundaries. It uses a write-back policy. The data cache writes to the L2 cache with its own 128-bit unidirectional bus. </p><p>The second level cache has a capacity of 1 or 2 MB and the set associativity depends on the capacity. </p> <div class="mw-heading mw-heading3"><h3 id="System_bus">System bus</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=7" title="Edit section: System bus"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The microprocessor has a 128-bit system bus that operates at 260 MHz. The bus can operate in two modes, single-data rate (SDR) or double-data (DDR) rate, yielding a peak bandwidth of 4.16 or 8.32 GB/s, respectively. </p> <div class="mw-heading mw-heading3"><h3 id="Physical">Physical</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=8" title="Edit section: Physical"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The SPARC64 V consisted of 191 million transistors, of which 19 million are contained in logic circuits.<sup id="cite_ref-ReferenceC_10-0" class="reference"><a href="#cite_note-ReferenceC-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> It was <a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">fabricated</a> in a <a href="/wiki/130_nanometer" class="mw-redirect" title="130 nanometer">0.13 μm</a>,<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> eight-layer copper metallization, <a href="/wiki/Complementary_metal%E2%80%93oxide%E2%80%93semiconductor" class="mw-redirect" title="Complementary metal–oxide–semiconductor">complementary metal–oxide–semiconductor</a> (CMOS) <a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">silicon on insulator</a> (SOI) process. The die measured 18.14 mm by 15.99 mm for a die area of 290 mm<sup>2</sup>.<sup id="cite_ref-ReferenceC_10-1" class="reference"><a href="#cite_note-ReferenceC-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Electrical">Electrical</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=9" title="Edit section: Electrical"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>At 1.3 GHz, the SPARC64 V has a power dissipation of 34.7 W.<sup id="cite_ref-ReferenceC_10-2" class="reference"><a href="#cite_note-ReferenceC-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> The Fujitsu PrimePower servers that use the SPARC64 V supply a slightly higher voltage the microprocessor to enable it to operate at 1.35 GHz. The increased power supply voltage and operating frequency increased the power dissipation to ~45 W.<sup id="cite_ref-FOOTNOTEAndo2003705_12-0" class="reference"><a href="#cite_note-FOOTNOTEAndo2003705-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="SPARC64_V+"><span id="SPARC64_V.2B"></span>SPARC64 V+</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=10" title="Edit section: SPARC64 V+"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">SPARC64 V+</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2004</td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data"><a href="/wiki/Fujitsu" title="Fujitsu">Fujitsu</a></td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.65 GHz to 2.16 GHz</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/SPARC_V9" class="mw-redirect" title="SPARC V9">SPARC V9</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>1</li></ul></div></td></tr></tbody></table> <p>The <b>SPARC64 V+</b>, code-named "Olympus-B", is a further development of the SPARC64 V. Improvements over the SPARC64 V included higher clock frequencies of 1.82–2.16 GHz and a larger 3 or 4 MB L2 cache.<sup id="cite_ref-ReferenceA_1-1" class="reference"><a href="#cite_note-ReferenceA-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p><p>The first SPARC64 V+, a 1.89 GHz version, was shipped in September 2004 in the Fujitsu PrimePower 650 and 850. In December 2004, a 1.82 GHz version was shipped in the PrimePower 2500. These versions have a 3 MB L2 cache.<sup id="cite_ref-Morgan:2004-06-24_13-0" class="reference"><a href="#cite_note-Morgan:2004-06-24-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> In February 2006, four versions were introduced: 1.65 and 1.98 GHz versions with 3 MB L2 caches shipped in the PrimePower 250 and 450; and 2.08 and 2.16 GHz versions with 4 MB L2 caches shipped in mid-range and high-end models.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> </p><p>It contained approximately 400 million transistors on an 18.46 mm by 15.94 mm die for an area of 294.25 mm<sup>2</sup>. It was fabricated in a <a href="/wiki/90_nanometer" class="mw-redirect" title="90 nanometer">90 nm</a> CMOS process with ten levels of <a href="/wiki/Copper_interconnect" class="mw-redirect" title="Copper interconnect">copper interconnect</a>.<sup id="cite_ref-ReferenceB_6-1" class="reference"><a href="#cite_note-ReferenceB-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="SPARC64_VI">SPARC64 VI</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=11" title="Edit section: SPARC64 VI"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">SPARC64 VI</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2007</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">2150 - 2400</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a></th><td class="infobox-data">128 <a href="/wiki/Kibibyte" class="mw-redirect" title="Kibibyte">KB</a> per core</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">4–6 MB per core</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/SPARC" title="SPARC">SPARC V9</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Transistor_count" title="Transistor count">Transistors</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/90_nanometer" class="mw-redirect" title="90 nanometer">90 nm</a> transistors</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>2</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">History</th></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data">SPARC64 V+</td></tr><tr><th scope="row" class="infobox-label">Successor</th><td class="infobox-data"><a href="/wiki/SPARC64_VII" class="mw-redirect" title="SPARC64 VII">SPARC64 VII</a></td></tr></tbody></table> <p>The <b>SPARC64 VI</b>, code-named Olympus-C, is a two-core processor (the first multi-core SPARC64 processor) which succeeded the <a href="/wiki/SPARC64_V%2B" class="mw-redirect" title="SPARC64 V+">SPARC64 V+</a>. It is fabricated by Fujitsu in a 90 nm, 10-layer copper, CMOS <a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">silicon on insulator</a> (SOI) process, which enabled two cores and an L2 cache to be integrated on a die. Each core is a modified <a class="mw-selflink-fragment" href="#SPARC64_V+">SPARC64 V+</a> processor. One of the main improvements is the addition of two-way <a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">coarse-grained multi-threading</a> (CMT), which Fujitsu called <i>vertical multi-threading</i> (VMT). In CMT, which thread is executed is determined by time-sharing, or if the thread is executing a long-latency operation, then execution is switched to the other thread.<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> The addition of CMT required duplication of the program counter and the control, integer, and floating-point registers so there is one set of each for every thread. A floating-point <a href="/wiki/Fused_multiply-add" class="mw-redirect" title="Fused multiply-add">fused multiply-add</a> (FMA) instruction was also added, the first SPARC processor to do so.<sup id="cite_ref-SPARC64_VI_Extensions_8-1" class="reference"><a href="#cite_note-SPARC64_VI_Extensions-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p><p>The cores share a 6 MB on-die unified L2 cache. The L2 cache is 12-way set associative and has 256-byte lines. The cache is accessed via two unidirectional buses, a 256-bit read bus and a 128-bit write bus. The SPARC64 VI has a new system bus, the Jupiter Bus. The SPARC64 VI consisted of 540 million transistors. The die measures 20.38 mm by 20.67 mm (421.25 mm<sup>2</sup>). </p><p>The SPARC64 VI was originally to have been introduced in mid-2004 in Fujitsu's PrimePower servers. Development of the PrimerPowers were canceled after Fujitsu and Sun Microsystems announced in June 2004 that they would collaborate on new servers called the Advanced Product Line (APL). These servers were scheduled to be introduced in mid-2006, but were delayed until April 2007, when they were introduced as the <a href="/wiki/SPARC_Enterprise" title="SPARC Enterprise">SPARC Enterprise</a>. The SPARC64 VI processors featured in the SPARC Enterprise at its announcement were a 2.15 GHz version with a 5 MB L2 cache, and 2.28 and 2.4 GHz versions with 6 MB L2 caches.<sup id="cite_ref-Morgan:2007-04-19_16-0" class="reference"><a href="#cite_note-Morgan:2007-04-19-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="SPARC64_VII">SPARC64 VII</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=12" title="Edit section: SPARC64 VII"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <b>SPARC64 VII</b> (previously called the SPARC64 VI+),<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> code-named <i>Jupiter</i>,<sup id="cite_ref-Morgan2008-07-17_18-0" class="reference"><a href="#cite_note-Morgan2008-07-17-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> is a further development of the SPARC64 VI announced in July 2008.<sup id="cite_ref-Morgan2008-07-17_18-1" class="reference"><a href="#cite_note-Morgan2008-07-17-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> It is a quad-core microprocessor. Each core is capable of two-way <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">simultaneous multithreading</a> (SMT), which replaces two-way <a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">coarse-grained multithreading</a>, termed <i>vertical multithreading</i> (VMT) by Fujitsu. Thus, it can execute eight threads simultaneously.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> Other changes include more <a href="/wiki/Reliability,_availability_and_serviceability_(computer_hardware)" class="mw-redirect" title="Reliability, availability and serviceability (computer hardware)">RAS</a> features; the integer register file is now protected by ECC, and the number of error checkers has been increased to around 3,400. It consists of 600 million transistors, is 21.31 mm × 20.86 mm (444.63 mm<sup>2</sup>) large, and is fabricated by Fujitsu in its <a href="/wiki/65_nanometer" class="mw-redirect" title="65 nanometer">65 nm</a> CMOS, copper interconnect process. </p><p>The SPARC64 VII was featured in the <a href="/wiki/SPARC_Enterprise" title="SPARC Enterprise">SPARC Enterprise</a>. It is socket-compatible with its predecessor, the SPARC64 VI, and is field-upgradeable. SPARC64 VIIs could coexist, whilst operating at their native clock frequency, alongside SPARC64 VIs.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> The first versions of the SPARC64 VII were a 2.4 GHz version with a 5 MB L2 cache used in the SPARC Enterprise M4000 and M5000, and a 2.52 GHz version with a 6 MB L2 cache.<sup id="cite_ref-Morgan2008-07-17_18-2" class="reference"><a href="#cite_note-Morgan2008-07-17-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> On 28 October 2008, a 2.52 GHz version with a 5 MB L2 cache was introduced in the SPARC Enterprise M3000.<sup id="cite_ref-Morgan:2008-10-28_21-0" class="reference"><a href="#cite_note-Morgan:2008-10-28-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> On 13 October 2009, Fujitsu and Sun introduced new versions of the SPARC64 VII (code-named <i>Jupiter+</i>),<sup id="cite_ref-Morgan:2009-09-11_22-0" class="reference"><a href="#cite_note-Morgan:2009-09-11-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> a 2.53 GHz version with a 5.5 MB L2 cache for the M4000 and M5000, and a 2.88 GHz version with a 6 MB L2 cache for the M8000 and M9000.<sup id="cite_ref-Morgan:2009-10-13_23-0" class="reference"><a href="#cite_note-Morgan:2009-10-13-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> On 12 January 2010, a 2.75 GHz version with a 5 MB L2 cache was introduced in the M3000.<sup id="cite_ref-Morgan:2010-01-12_24-0" class="reference"><a href="#cite_note-Morgan:2010-01-12-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="SPARC64_VII+"><span id="SPARC64_VII.2B"></span>SPARC64 VII+</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=13" title="Edit section: SPARC64 VII+"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <b>SPARC64 VII+</b> (<i>Jupiter-E</i>),<sup id="cite_ref-Morgan:2011-04-12_25-0" class="reference"><a href="#cite_note-Morgan:2011-04-12-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> referred to as the <b>M3</b> by Oracle,<sup id="cite_ref-Morgan:2011-04-12_25-1" class="reference"><a href="#cite_note-Morgan:2011-04-12-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> is a further development of the SPARC64 VII. The clock frequency was increased up to 3 GHz and the L2 cache size was doubled to 12 MB. This version was announced on 2 December 2010 for the high-end SPARC Enterprise M8000 and M9000 servers.<sup id="cite_ref-Fujitsu:2010-12-02_26-0" class="reference"><a href="#cite_note-Fujitsu:2010-12-02-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> These improvements resulted in an approximately 20% increase to overall performance. A 2.66 GHz version was for mid-range M4000 and M5000 models.<sup id="cite_ref-Morgan:2011-04-12_25-2" class="reference"><a href="#cite_note-Morgan:2011-04-12-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> On 12 April 2011, a 2.86 GHz version with two or four cores and a 5.5 MB L2 cache was announced for the low-end M3000.<sup id="cite_ref-Fujitsu:2011-04-12_27-0" class="reference"><a href="#cite_note-Fujitsu:2011-04-12-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Morgan:2011-04-12_25-3" class="reference"><a href="#cite_note-Morgan:2011-04-12-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> The VII+ is socket-compatible with its predecessor, the VII. Existing high-end SPARC Enterprise M-Series servers are able to upgrade to the VII+ processors in the field.<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="SPARC64_VIIIfx">SPARC64 VIIIfx</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=14" title="Edit section: SPARC64 VIIIfx"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c8/Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG/220px-Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG" decoding="async" width="220" height="293" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c8/Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG/330px-Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c8/Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG/440px-Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG 2x" data-file-width="3448" data-file-height="4592" /></a><figcaption>A <a href="/wiki/K_computer" title="K computer">K computer</a> <a href="/wiki/Blade_server" title="Blade server">blade</a> featuring four SPARC64 VIIIfx processors (under the larger <a href="/wiki/Heat_exchanger" title="Heat exchanger">heat exchangers</a>)</figcaption></figure> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:SPARC64_VIIIfx_2.00GHz.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a6/SPARC64_VIIIfx_2.00GHz.jpg/200px-SPARC64_VIIIfx_2.00GHz.jpg" decoding="async" width="200" height="200" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a6/SPARC64_VIIIfx_2.00GHz.jpg/300px-SPARC64_VIIIfx_2.00GHz.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a6/SPARC64_VIIIfx_2.00GHz.jpg/400px-SPARC64_VIIIfx_2.00GHz.jpg 2x" data-file-width="900" data-file-height="900" /></a><figcaption></figcaption></figure> <p>The <b>SPARC64 VIIIfx</b> (<i>Venus</i>) is an eight-core processor based on the SPARC64 VII designed for <a href="/wiki/High-performance_computing" title="High-performance computing">high-performance computing</a> (HPC).<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> As a result, the VIIIfx did not succeed the VII, but existed concurrently with it. It consists of 760 million transistors, measures 22.7 mm by 22.6  (513.02 mm<sup>2</sup>;), is fabricated in Fujitu's <a href="/wiki/45_nm" class="mw-redirect" title="45 nm">45 nm</a> CMOS process with copper interconnects, and has 1,271 I/O pins. The VIIIfx has a peak performance at 2 GHz of 128 <a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a> and a typical power consumption of 58 W at 30 °C for an efficiency of 2.2 GFLOPS/W. The VIIIfx has four integrated <a href="/wiki/Memory_controller" title="Memory controller">memory controllers</a> for a total of eight <a href="/wiki/Multi-channel_memory_architecture" title="Multi-channel memory architecture">memory channels</a>. It connects to 64 GB of <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a> and has a peak memory bandwidth of 64 GB/s.<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="History_2">History</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=15" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The VIIIfx was developed for the Next-Generation Supercomputer Project (also called <i>Kei Soku Keisenki</i> and Project Keisoku) initiated by Japan's <a href="/wiki/Ministry_of_Education,_Culture,_Sports,_Science_and_Technology" title="Ministry of Education, Culture, Sports, Science and Technology">Ministry of Education, Culture, Sports, Science and Technology</a> in January 2006. The project aimed to produce the world's fastest supercomputer with performance of over 10 PFLOPS by March 2011. The companies contracted to develop the supercomputer were Fujitsu, <a href="/wiki/Hitachi" title="Hitachi">Hitachi</a>, and <a href="/wiki/NEC" title="NEC">NEC</a>. The supercomputer was originally envisioned to have a hybrid architecture containing <a href="/wiki/Scalar_processor" title="Scalar processor">scalar</a> and <a href="/wiki/Vector_processor" title="Vector processor">vector processors</a>. The Fujitsu-designed VIIIfx was to have been the scalar processor, with the vector processor to have been jointly designed by Hitachi and NEC. However, due to the <a href="/wiki/Financial_crisis_of_2007%E2%80%932008" class="mw-redirect" title="Financial crisis of 2007–2008">Financial crisis of 2007–2008</a>, Hitachi and NEC announced in May 2009 that they would leave the project because manufacturing the hardware they were responsible for would result in financial losses for them. Afterwards, Fujitsu redesigned the supercomputer to use the VIIIfx as its only processor type. </p><p>By 2010, the supercomputer that would be built by the project was named the <a href="/wiki/K_computer" title="K computer">K computer</a>. Located at the <a href="/wiki/RIKEN" class="mw-redirect" title="RIKEN">RIKEN</a>'s Advanced Institute for Computational Science (AICS) in <a href="/wiki/Kobe" title="Kobe">Kobe</a>, Japan;<sup id="cite_ref-tele20611_31-0" class="reference"><a href="#cite_note-tele20611-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-nyt20611_32-0" class="reference"><a href="#cite_note-nyt20611-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-fujnr_33-0" class="reference"><a href="#cite_note-fujnr-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> it obtains its performance from 88,128 VIIIfx processors. In June 2011, the <a href="/wiki/TOP500" title="TOP500">TOP500</a> Project Committee announced that the K computer (still incomplete with only 68,544 processors) topped the <a href="/wiki/LINPACK_benchmark" class="mw-redirect" title="LINPACK benchmark">LINPACK benchmark</a> at 8.162 <a href="/wiki/PFLOPS" class="mw-redirect" title="PFLOPS">PFLOPS</a>, realizing 93% of its peak performance, making it the fastest supercomputer in the world at that time.<sup id="cite_ref-nyt20611_32-1" class="reference"><a href="#cite_note-nyt20611-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-riken_34-0" class="reference"><a href="#cite_note-riken-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-top500_35-0" class="reference"><a href="#cite_note-top500-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Description_2">Description</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=16" title="Edit section: Description"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The VIIIfx core is based on that of the SPARC64 VII with numerous modifications for HPC, namely High Performance Computing-Arithmetic Computational Extensions (HPC-ACE) a Fujitsu-designed extension to the SPARC V9 architecture. The front-end had coarse-grained multi-threading removed, the L1 instruction cache halved in size to 32 KB; and the number of branch target address cache (BTAC) entries reduced to 1,024 from 8,192, and its <a href="/wiki/CPU_cache#Associativity" title="CPU cache">associativity</a> reduced to two from eight; and an extra pipeline stage was inserted before the instruction decoder. This stage accommodated the greater number of integer and floating-point registers defined by HPC-ACE. The SPARC V9 architecture was designed to have only 32 integer and 32 floating-point number registers. The SPARC V9 instruction encoding limited the number of registers specifiable to 32. To specify the extra registers, HPC-ACE has a "prefix" instruction that would immediately follow one or two SPARC V9 instructions. The prefix instruction contained (primarily) the portions of the register numbers that could not fit within a SPARC V9 instruction. This extra pipeline stage was where up to four SPARC V9 instructions were combined with up to two prefix instructions in the preceding stage. The combined instructions were then decoded in the next pipeline stage. </p><p>The back-end was also heavily modified. The number of reservation station entries for branch and integer instructions were reduced to six and ten, respectively. Both the integer and floating-point register files had registers added to them: the integer register file gained 32, and there were a total of 256 floating-point registers. The extra integer registers are not part of the <a href="/wiki/Register_window" title="Register window">register windows</a> defined by SPARC V9, but are always accessible via the prefix instruction; and the 256 floating-point registers could be used by both scalar floating-point instructions and by both integer and floating-point SIMD instructions. An extra pipeline stage was added to the beginning of the floating-point execution pipeline to access the larger floating-point register file. The 128-bit SIMD instructions from HPC-ACE were implemented by adding two extra floating-point units for a total of four. SIMD execution can perform up four single- or double-precision fused-multiply-add operations (eight FLOPs) per cycle. The number of load queue entries was increased to 20 from 16, and the L1 data cache was halved in size to 32 KB. The number of commit stack entries, which determined the number of instructions that could be in-flight in the back-end, was reduced to 48 from 64. </p> <div class="mw-heading mw-heading3"><h3 id="Miscellaneous_specifications">Miscellaneous specifications</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=17" title="Edit section: Miscellaneous specifications"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Physical address range: 41 bits</li> <li>Cache:</li></ul> <dl><dd><ul><li>L1: 32 <a href="/wiki/Kibibyte" class="mw-redirect" title="Kibibyte">KB</a> two-way <a href="/wiki/Set-associative" class="mw-redirect" title="Set-associative">set-associative</a> data, 32 KB two-way set-associative instruction (128-byte cache line), sectored</li> <li>L2: 6 <a href="/wiki/Mebibyte" class="mw-redirect" title="Mebibyte">MB</a> 12-way set-associative (128-byte line), index-hashed, sectored</li></ul></dd></dl> <ul><li><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB):</li></ul> <dl><dd><ul><li>A 16-entry micro-TLB; and 256-entry, four-way set-associative TLB for instructions</li> <li>A 512-entry, four-way set-associative TLB for data, no victim cache</li></ul></dd></dl> <ul><li>Page sizes: 8 KB, 64 KB, 512 KB, 4 MB, 32 MB, 256 MB, 2 GB</li></ul> <div class="mw-heading mw-heading2"><h2 id="SPARC64_IXfx">SPARC64 IXfx</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=18" title="Edit section: SPARC64 IXfx"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <b>SPARC64 IXfx</b> is an improved version of the SPARC64 VIIIfx designed by Fujitsu and <a href="/wiki/LSI_Corporation" title="LSI Corporation">LSI</a><sup id="cite_ref-Byrne:2011-12-05_37-0" class="reference"><a href="#cite_note-Byrne:2011-12-05-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> first revealed in the announcement of the <a href="/wiki/PRIMEHPC_FX10" title="PRIMEHPC FX10">PRIMEHPC FX10</a> supercomputer on 7 November 2011.<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> It, along with the PRIMEHPC FX10, is a commercialization of the technologies that first appeared in the VIIIfx and K computer. Compared to the VIIIfx, organizational improvements included doubling the number of cores was to 16, doubling the amount of shared L2 cache to 12 MB, and increasing peak DDR3 SDRAM memory bandwidth to 85 GB/s. The IXfx operates at 1.848 GHz, has a peak performance of 236.5 GFLOPS, and consumes 110 W for a power efficiency of more than 2 GFLOPS per watt.<sup id="cite_ref-Morgan:2011-11-07_39-0" class="reference"><a href="#cite_note-Morgan:2011-11-07-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Byrne:2011-12-05_37-1" class="reference"><a href="#cite_note-Byrne:2011-12-05-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> It consisted of 1 billion transistors and was implemented in a 40 nm CMOS process with copper interconnects.<sup id="cite_ref-Maruyama:2012-08-29_40-0" class="reference"><a href="#cite_note-Maruyama:2012-08-29-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="SPARC64_X">SPARC64 X</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=19" title="Edit section: SPARC64 X"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <b>SPARC64 X</b> is a 16-core server microprocessor announced in 2012 and used in Fujitsu's M10 servers (which are also marketed by Oracle). The SPARC64 X is based on the SPARC64 VII+ with significant enhancements to its core and chip organization. The cores were improved by the inclusion of a pattern history table for <a href="/wiki/Branch_predictor" title="Branch predictor">branch prediction</a>, <a href="/wiki/Memory_disambiguation" title="Memory disambiguation">speculative execution of loads</a>, more execution units, support for the HPC-ACE extension (originally from the SPARC64 VIIIfx), deeper pipeline for a 3.0 GHz clock frequency, and accelerators for <a href="/wiki/Cryptography" title="Cryptography">cryptography</a>, <a href="/wiki/Database" title="Database">database</a>, and decimal floating-point number arithmetic and conversion functions. The 16 cores share a unified, 24 MB, 24-way set-associative L2 cache. Chip organization improvements include four integrated <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a> memory controllers, <a href="/wiki/Glue_logic" title="Glue logic">glueless</a> four-way symmetrical multiprocessing, ten SERDES channels for symmetrical multiprocessing scalability to 64 sockets, and two integrated <a href="/wiki/PCI_Express_3.0" class="mw-redirect" title="PCI Express 3.0">PCI Express 3.0</a> controllers. The SPARC64 X contains 2.95 billion transistors, measures 23.5 mm by 25 mm (587.5 mm<sup>2</sup>), and is fabricated in a 28 nm CMOS process with copper interconnects.<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Maruyama:2012-08-29_40-1" class="reference"><a href="#cite_note-Maruyama:2012-08-29-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="SPARC64_X+"><span id="SPARC64_X.2B"></span>SPARC64 X+</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=20" title="Edit section: SPARC64 X+"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <b>SPARC64 X+</b> is an enhanced SPARC64 X processor announced in 2013. It features minor improvements to the core organization, and a higher 3.5 GHz clock frequency obtained through better circuit design and layout. It contained 2.99 billion transistors, measured 24 mm by 25 mm (600 mm<sup>2</sup>), and is fabricated in the same process as the SPARC64 X.<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> On 8 April 2014, 3.7 GHz <a href="/wiki/Product_binning" title="Product binning">speed-binned</a> parts became available in response to the introduction of new <a href="/wiki/Xeon" title="Xeon">Xeon</a> E5 and E7 models by <a href="/wiki/Intel" title="Intel">Intel</a>; and the impending introduction of the <a href="/wiki/POWER8" title="POWER8">POWER8</a> by <a href="/wiki/IBM" title="IBM">IBM</a>.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="SPARC64_XIfx">SPARC64 XIfx</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=21" title="Edit section: SPARC64 XIfx"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Fujitsu introduced the <b>SPARC64 XIfx</b> in August 2014 at the <a href="/wiki/Hot_Chips" class="mw-redirect" title="Hot Chips">Hot Chips</a> symposium.<sup id="cite_ref-Halfhill:2014-09-22_45-0" class="reference"><a href="#cite_note-Halfhill:2014-09-22-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> It is used in the Fujitsu PRIMEHPC FX100 supercomputer, which succeeded the <a href="/wiki/PRIMEHPC_FX10" title="PRIMEHPC FX10">PRIMEHPC FX10</a>.<sup id="cite_ref-Heise20140812_46-0" class="reference"><a href="#cite_note-Heise20140812-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Fujitsu201408_47-0" class="reference"><a href="#cite_note-Fujitsu201408-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> The XIfx operates at 2.2 GHz and has a peak performance of 1.1 TFLOPS.<sup id="cite_ref-PCWorld20140812_48-0" class="reference"><a href="#cite_note-PCWorld20140812-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> It consists of 3.75 billion transistors and is fabricated by the <a href="/wiki/Taiwan_Semiconductor_Manufacturing_Company" class="mw-redirect" title="Taiwan Semiconductor Manufacturing Company">Taiwan Semiconductor Manufacturing Company</a> in its <a href="/w/index.php?title=20_nm&action=edit&redlink=1" class="new" title="20 nm (page does not exist)">20 nm</a> <a href="/wiki/High-%CE%BA_dielectric" title="High-κ dielectric">high-κ metal gate</a> (HKMG) process. The <i>Microprocessor Report</i> estimated the die to have an area of 500 mm<sup>2</sup>; and a typical power consumption of 200 W.<sup id="cite_ref-Halfhill:2014-09-22_45-1" class="reference"><a href="#cite_note-Halfhill:2014-09-22-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> </p><p>The XIfx has 34 cores, 32 of which are <i>compute cores</i> used to run user applications, and 2 <i>assistant cores</i> used to run the operating system and other system services. The delegation of user applications and operating system to dedicated cores improves performance by ensuring that the private caches of the compute cores are not shared with or disrupted by non-application instructions and data. The 34 cores are further organized into two <i>Core Memory Groups</i> (<i>CMGs</i>), each consisting of 16 compute cores and 1 assistant core sharing a 12 MB L2 unified cache. The division of the cores into CMGs enabled 34 cores to be integrated on a single die by easing the implementation of cache coherence and avoiding the need for the L2 cache to be shared between 34 cores. The two CMGs share the memory through a <a href="/wiki/CcNUMA" class="mw-redirect" title="CcNUMA">ccNUMA</a> organization. </p><p>The XIfx core was based on the SPARC64 X+ with organizational improvements. The XIfx implements an improved version of the HPC-ACE extensions (HPC-ACE2), which doubled the width of the <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> units to 256 bits and added new SIMD instructions. Compared to the SPARC64 IXfx, the XIfx has an improvement of a factor of 3.2 for double precision and 6.1 for single precision. To complement the increased width of the SIMD units, the L1 cache bandwidth was increased to 4.4 TB/s. </p><p>Improvements to the SoC organization were to the memory and interconnect interfaces. The integrated <a href="/wiki/Memory_controller" title="Memory controller">memory controllers</a> were replaced with four <a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a> (HMC) interfaces for decreased memory latency and improved memory bandwidth. According to the <i>Microprocessor Report</i>, the IXfx was the first processor to use HMCs.<sup id="cite_ref-Halfhill:2014-09-22_45-2" class="reference"><a href="#cite_note-Halfhill:2014-09-22-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> The XIfx is connected to 32 GB of memory provided by eight 4 GB HMCs. The HMCs are 16-lane versions, with each lane operating at 15 Gbit/s. Each CMG has two HMC interfaces, and each HMC interface is connected to two HMCs via its own ports. Each CMG has 240 GB/s (120 GB/s in and 120 GB/s out) of memory bandwidth. </p><p>The XIfx replaced the ten SERDES channels to an external Tofu interconnect controller with a ten-port integrated controller for the second-generation Tofu2 interconnect. Tofu2 is a 6D mesh/torus network with a 25 GB/s full-duplex bandwidth (12.5 GB/s per direction, 125 GB/s for ten ports) and an improved routing architecture. </p> <div class="mw-heading mw-heading3"><h3 id="Future">Future</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=22" title="Edit section: Future"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Fujitsu announced at the <a href="/wiki/International_Supercomputing_Conference" class="mw-redirect" title="International Supercomputing Conference">International Supercomputing Conference</a> in June 2016 that its future <a href="/wiki/Exascale_computing" title="Exascale computing">exascale</a> supercomputer will feature processors of its own design that implement the <a href="/wiki/ARMv8" class="mw-redirect" title="ARMv8">ARMv8</a> architecture. The <a href="/wiki/Fujitsu_A64FX" title="Fujitsu A64FX">A64FX</a> will implement extensions to the ARMv8 architecture, equivalent to HPC-ACE2, that Fujitsu is developing with <a href="/wiki/ARM_Holdings" class="mw-redirect" title="ARM Holdings">ARM Holdings</a>.<sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="SPARC64_XII">SPARC64 XII</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=23" title="Edit section: SPARC64 XII"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=SPARC64_V&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">January 2018</span>)</i></span></div></td></tr></tbody></table> <p><b>SPARC64 XII</b> was launched in 2017 with Fujitsu's SPARC M12 servers. It nominally features 12 cores, but just like IBM's <a href="/wiki/POWER9" title="POWER9">POWER9</a> that was launched the same year, each of the twelve cores consists of two separate pipelines, and the only resources shared between SPARC64 XII core's pipelines are the <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">TLB</a>, L1 instruction cache and L2 cache, and as a result the single-threaded performance is almost unchanged from SPARC64 X. SPARC64 XII operates at up to 4.25 GHz base frequency and 4.35 GHz boost frequency. The size of the chip is 25.8mm × 30.8mm (795mm<sup>2</sup>), containing 5.45 billion transistors made on <a href="/wiki/TSMC" title="TSMC">TSMC</a>'s <a href="/wiki/20_nm_process" class="mw-redirect" title="20 nm process">20 nm process</a>. Each of the two pipelines of a core can fetch 8 instructions, decode 4 instructions and execute 6 instructions per cycle, and supports 4 SMT threads (for 96 threads per CPU). Each pipeline has an own 32 MB 4-way L1 data cache, and two pipelines share a 64 MB 4-way associative L1 instruction cache and a 512 MB 16-way L2 cache. SPARC64 XII is Fujitsu's first SPARC CPU with L3 cache (32 MB 16-way). The number of 8-lane PCIe 3.0 ports has been doubled to 4 per chip. Memory speed has been increased by 50% to 2400 MT/s, bringing the theoretical combined bandwidth of the 8 DDR4 channels of the chip to 153 GB/s, and the capacity per CPU is up to 1.5 TB across 24 slots. Two CPUs can be connected in a Building Block, and up to 16 Building Blocks can be connected to create a 32-CPU server with up to 48 TB of memory.<sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=24" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-ReferenceA-1"><span class="mw-cite-backlink">^ <a href="#cite_ref-ReferenceA_1-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-ReferenceA_1-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFMorgan2006" class="citation web cs1">Morgan, Timothy Prickett (23 February 2006). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20060312154311/http://www.itjungle.com/tug/tug022306-story01.html">"Fujitsu Draws Sparc64 Roadmap Past 2010"</a>. <i>The Unix Guardian</i>. Archived from <a rel="nofollow" class="external text" href="http://www.itjungle.com/tug/tug022306-story01.html">the original</a> on 12 March 2006.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Unix+Guardian&rft.atitle=Fujitsu+Draws+Sparc64+Roadmap+Past+2010&rft.date=2006-02-23&rft.aulast=Morgan&rft.aufirst=Timothy+Prickett&rft_id=http%3A%2F%2Fwww.itjungle.com%2Ftug%2Ftug022306-story01.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-Diefendorff:1999-11-15-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-Diefendorff:1999-11-15_2-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDiefendorff1999" class="citation journal cs1"><a href="/wiki/Keith_Diefendorff" title="Keith Diefendorff">Diefendorff, Keith</a> (15 November 1999). "Hal Makes Sparcs Fly". <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>. <b>13</b> (5).</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Microprocessor+Report&rft.atitle=Hal+Makes+Sparcs+Fly&rft.volume=13&rft.issue=5&rft.date=1999-11-15&rft.aulast=Diefendorff&rft.aufirst=Keith&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation conference cs1"><i>Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems</i>. Ninth International Symposium on High-Performance Computer Architecture, 2003 (HPCA-9 2003). <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FHPCA.2003.1183533">10.1109/HPCA.2003.1183533</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=Microarchitecture+and+Performance+Analysis+of+a+SPARC-V9+Microprocessor+for+Enterprise+Server+Systems&rft_id=info%3Adoi%2F10.1109%2FHPCA.2003.1183533&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMorgan2006" class="citation news cs1">Morgan, Timothy Prickett (9 February 2006). <a rel="nofollow" class="external text" href="http://www.itjungle.com/tug/tug020906-story07.html">"Fujitsu-Siemens Cranks the Clock on Sparc V Chips for PrimePowers"</a>. <i>The Unix Guardian</i>. Vol. 3, no. 5.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=The+Unix+Guardian&rft.atitle=Fujitsu-Siemens+Cranks+the+Clock+on+Sparc+V+Chips+for+PrimePowers&rft.volume=3&rft.issue=5&rft.date=2006-02-09&rft.aulast=Morgan&rft.aufirst=Timothy+Prickett&rft_id=http%3A%2F%2Fwww.itjungle.com%2Ftug%2Ftug020906-story07.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-MPR-2002-10-21-P1-5"><span class="mw-cite-backlink">^ <a href="#cite_ref-MPR-2002-10-21-P1_5-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-MPR-2002-10-21-P1_5-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKrewell2002" class="citation journal cs1">Krewell, Kevin (21 October 2002). <a rel="nofollow" class="external text" href="https://www.eecg.toronto.edu/~moshovos/ACA07/lecturenotes/ultrasparc5%2520(mpr).pdf">"Fujitsu's SPARC64 V Is Real Deal"</a> <span class="cs1-format">(PDF)</span>. <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>: 1.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Microprocessor+Report&rft.atitle=Fujitsu%27s+SPARC64+V+Is+Real+Deal&rft.pages=1&rft.date=2002-10-21&rft.aulast=Krewell&rft.aufirst=Kevin&rft_id=https%3A%2F%2Fwww.eecg.toronto.edu%2F~moshovos%2FACA07%2Flecturenotes%2Fultrasparc5%252520%28mpr%29.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-ReferenceB-6"><span class="mw-cite-backlink">^ <a href="#cite_ref-ReferenceB_6-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-ReferenceB_6-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">"SPARC64 V Processor For UNIX Server"</span> </li> <li id="cite_note-MPR-2002-10-21-P2-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-MPR-2002-10-21-P2_7-0">^</a></b></span> <span class="reference-text"><a href="#CITEREFKrewell2002">Krewell 2002</a>, p. 2</span> </li> <li id="cite_note-SPARC64_VI_Extensions-8"><span class="mw-cite-backlink">^ <a href="#cite_ref-SPARC64_VI_Extensions_8-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-SPARC64_VI_Extensions_8-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.fujitsu.com/downloads/SPARCE/others/sparc64vi-extensions.pdf">"SPARC64 VI Extensions"</a> page 56, Fujitsu Limited, Release 1.3, 27 March 2007</span> </li> <li id="cite_note-HPCA-P4-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-HPCA-P4_9-0">^</a></b></span> <span class="reference-text">"Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems", p. 4.</span> </li> <li id="cite_note-ReferenceC-10"><span class="mw-cite-backlink">^ <a href="#cite_ref-ReferenceC_10-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-ReferenceC_10-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-ReferenceC_10-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAndo2003" class="citation conference cs1">Ando, Hisashige; et al. (June 2003). "A 1.3GHz fifth generation SPARC64 microprocessor". <i>Proceedings of the 40th annual Design Automation Conference</i>. pp. 702–705. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F775832.776010">10.1145/775832.776010</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/1581136889" title="Special:BookSources/1581136889"><bdi>1581136889</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:7005187">7005187</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.atitle=A+1.3GHz+fifth+generation+SPARC64+microprocessor&rft.btitle=Proceedings+of+the+40th+annual+Design+Automation+Conference&rft.pages=702-705&rft.date=2003-06&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A7005187%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1145%2F775832.776010&rft.isbn=1581136889&rft.aulast=Ando&rft.aufirst=Hisashige&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span>p. 702.</span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><a href="#CITEREFKrewell2002">Krewell 2002</a>, p. 3</span> </li> <li id="cite_note-FOOTNOTEAndo2003705-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-FOOTNOTEAndo2003705_12-0">^</a></b></span> <span class="reference-text"><a href="#CITEREFAndo2003">Ando 2003</a>, p. 705.</span> </li> <li id="cite_note-Morgan:2004-06-24-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-Morgan:2004-06-24_13-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMorgan2004" class="citation web cs1">Morgan, Timothy Prickett (24 June 2004). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20041021221739/http://www.itjungle.com/tug/tug062404-story01.html">"Fujitsu-Siemens Upgrades PrimePower Unix Servers"</a>. <i>The Unix Guardian</i>. Archived from <a rel="nofollow" class="external text" href="http://www.itjungle.com/tug/tug062404-story01.html">the original</a> on 21 October 2004.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Unix+Guardian&rft.atitle=Fujitsu-Siemens+Upgrades+PrimePower+Unix+Servers&rft.date=2004-06-24&rft.aulast=Morgan&rft.aufirst=Timothy+Prickett&rft_id=http%3A%2F%2Fwww.itjungle.com%2Ftug%2Ftug062404-story01.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-14">^</a></b></span> <span class="reference-text">"Fujitsu-Siemens Cranks the Clock on Sparc V Chips for PrimePowers"</span> </li> <li id="cite_note-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-15">^</a></b></span> <span class="reference-text">Fujitsu Limited (27 March 2007). "<i>SPARC64 VI Extensions</i>, Release 1.3". pp. 45–46.</span> </li> <li id="cite_note-Morgan:2007-04-19-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-Morgan:2007-04-19_16-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMorgan2007" class="citation web cs1">Morgan, Timothy Prickett (19 April 2007). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20081203235248/http://www.itjungle.com/tug/tug041907-story01.html">"Fujitsu, Sun Deliver Joint Sparc Enterprise Server Line"</a>. <i>The Unix Guardian</i>. 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Archived from <a rel="nofollow" class="external text" href="http://www.itjungle.com/tug/tug071708-story01.html">the original</a> on 20 November 2008.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Unix+Guardian&rft.atitle=Fujitsu+and+Sun+Flex+Their+Quads+with+New+Sparc+Server+Lineup&rft.date=2008-07-17&rft.aulast=Morgan&rft.aufirst=Timothy+Prickett&rft_id=http%3A%2F%2Fwww.itjungle.com%2Ftug%2Ftug071708-story01.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-19"><span class="mw-cite-backlink"><b><a href="#cite_ref-19">^</a></b></span> <span class="reference-text">"Hot Chips: Fujitsu shows off SPARC64 VII"</span> </li> <li id="cite_note-20"><span class="mw-cite-backlink"><b><a href="#cite_ref-20">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.sun.com/servers/sparcenterprise/SPARCEnt-Arch-Final.pdf">"Sun SPARC Enterprise Server Family Architecture: Flexible, Mainframe-Class Compute Power for the Datacenter"</a> <span class="cs1-format">(PDF)</span>. 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"Sparc64 IXfx Burns Through FP Code". <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Microprocessor+Report&rft.atitle=Sparc64+IXfx+Burns+Through+FP+Code&rft.date=2011-12-05&rft.aulast=Byrne&rft.aufirst=Joseph&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-38"><span class="mw-cite-backlink"><b><a href="#cite_ref-38">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.Fujitsu.com/global/news/pr/archives/month/2011/20111107-01.html">Fujitsu Launches PRIMEHPC FX10 Supercomputer</a></span> </li> <li id="cite_note-Morgan:2011-11-07-39"><span class="mw-cite-backlink"><b><a href="#cite_ref-Morgan:2011-11-07_39-0">^</a></b></span> <span class="reference-text">Morgan, Timothy Prickett (7 November 2011). <a rel="nofollow" class="external text" href="https://www.theregister.co.uk/2011/11/07/fujitsu_sparc64_ixfx_fx10_supercomputer/">"Fujitsu readies 23 petaflops Sparc FX10 super beast"</a>. <i><a href="/wiki/The_Register" title="The Register">The Register</a></i>.</span> </li> <li id="cite_note-Maruyama:2012-08-29-40"><span class="mw-cite-backlink">^ <a href="#cite_ref-Maruyama:2012-08-29_40-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Maruyama:2012-08-29_40-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMaruyama2012" class="citation conference cs1">Maruyama, Takumi (29 August 2012). <i>SPARC64™ X: Fujitsu's new generation 16 core processor for the next generation UNIX servers</i>. 2012 IEEE Hot Chips 24 Symposium (HCS). pp. 1–20. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FHOTCHIPS.2012.7476503">10.1109/HOTCHIPS.2012.7476503</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4673-8879-5" title="Special:BookSources/978-1-4673-8879-5"><bdi>978-1-4673-8879-5</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:34868980">34868980</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=SPARC64%E2%84%A2+X%3A+Fujitsu%27s+new+generation+16+core+processor+for+the+next+generation+UNIX+servers&rft.pages=1-20&rft.date=2012-08-29&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A34868980%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FHOTCHIPS.2012.7476503&rft.isbn=978-1-4673-8879-5&rft.aulast=Maruyama&rft.aufirst=Takumi&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-41"><span class="mw-cite-backlink"><b><a href="#cite_ref-41">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHalfhill2012" class="citation journal cs1">Halfhill, Tom R. (17 September 2012). "Fujitsu and Oracle Ignite SPARCs". <i>Microprocessor Report</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Microprocessor+Report&rft.atitle=Fujitsu+and+Oracle+Ignite+SPARCs&rft.date=2012-09-17&rft.aulast=Halfhill&rft.aufirst=Tom+R.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-42"><span class="mw-cite-backlink"><b><a href="#cite_ref-42">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGwennap2013" class="citation journal cs1">Gwennap, Linley (7 October 2013). "Fujitsu, Oracle Processors Evolve". <i>Microprocessor Report</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Microprocessor+Report&rft.atitle=Fujitsu%2C+Oracle+Processors+Evolve&rft.date=2013-10-07&rft.aulast=Gwennap&rft.aufirst=Linley&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-43"><span class="mw-cite-backlink"><b><a href="#cite_ref-43">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFYoshida2013" class="citation news cs1">Yoshida, Toshio (27 August 2013). "SPARC64 X+: Fujitsu's Next Generation Processor for UNIX servers".</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=SPARC64+X%2B%3A+Fujitsu%27s+Next+Generation+Processor+for+UNIX+servers&rft.date=2013-08-27&rft.aulast=Yoshida&rft.aufirst=Toshio&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-44"><span class="mw-cite-backlink"><b><a href="#cite_ref-44">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFPrickett2014" class="citation news cs1">Prickett, Timothy Morgan (8 April 2014). "Oracle Unfolds Sparc Roadmap, Fujitsu boosts SPARC64 X Clocks". <i>EnterpriseTech</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=EnterpriseTech&rft.atitle=Oracle+Unfolds+Sparc+Roadmap%2C+Fujitsu+boosts+SPARC64+X+Clocks&rft.date=2014-04-08&rft.aulast=Prickett&rft.aufirst=Timothy+Morgan&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-Halfhill:2014-09-22-45"><span class="mw-cite-backlink">^ <a href="#cite_ref-Halfhill:2014-09-22_45-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Halfhill:2014-09-22_45-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Halfhill:2014-09-22_45-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHalfhill2014" class="citation journal cs1">Halfhill, Tom R. (22 September 2014). "Sparc64 XIfx Uses Memory Cubes". <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Microprocessor+Report&rft.atitle=Sparc64+XIfx+Uses+Memory+Cubes&rft.date=2014-09-22&rft.aulast=Halfhill&rft.aufirst=Tom+R.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-Heise20140812-46"><span class="mw-cite-backlink"><b><a href="#cite_ref-Heise20140812_46-0">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.heise.de/newsticker/meldung/Sparc-Prozessor-fuer-100-Petaflop-Rechner-2290438.html"><i>Sparc-Prozessor für 100-Petaflop-Rechner</i></a> Heise Newsticker, 6 August 2014</span> </li> <li id="cite_note-Fujitsu201408-47"><span class="mw-cite-backlink"><b><a href="#cite_ref-Fujitsu201408_47-0">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.fujitsu.com/global/Images/next-generaton-primehpc_tcm100-1050349.pdf"><i>Next Generation PRIMEHPC</i></a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160304200814/http://www.fujitsu.com/global/Images/next-generaton-primehpc_tcm100-1050349.pdf">Archived</a> 4 March 2016 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> Fujitsu Ltd., 2014</span> </li> <li id="cite_note-PCWorld20140812-48"><span class="mw-cite-backlink"><b><a href="#cite_ref-PCWorld20140812_48-0">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.pcworld.com/article/2462380/fujitsu-guns-for-faster-supercomputers-with-new-chip.html"><i>Fujitsu guns for faster supercomputers with new chip</i></a> Agam Shah, PC World, 6 August 2014</span> </li> <li id="cite_note-49"><span class="mw-cite-backlink"><b><a href="#cite_ref-49">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMorgan2016" class="citation web cs1">Morgan, Timothy Prickett (23 June 2016). <a rel="nofollow" class="external text" href="https://www.nextplatform.com/2016/06/23/inside-japans-future-exaflops-arm-supercomputer/">"Inside Japan's Future Exascale ARM Supercomputer"</a>. <i>The Next Platform</i><span class="reference-accessdate">. Retrieved <span class="nowrap">13 July</span> 2016</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Next+Platform&rft.atitle=Inside+Japan%27s+Future+Exascale+ARM+Supercomputer&rft.date=2016-06-23&rft.aulast=Morgan&rft.aufirst=Timothy+Prickett&rft_id=https%3A%2F%2Fwww.nextplatform.com%2F2016%2F06%2F23%2Finside-japans-future-exaflops-arm-supercomputer%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-50"><span class="mw-cite-backlink"><b><a href="#cite_ref-50">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20170829121542/https://www.fujitsu.com/jp/documents/products/computing/servers/unix/sparc/events/2017/coolchips20/CoolChips20-rev8.pdf">"SPARC64™ XII: Fujitsu's latest 12 Core Processor for Mission Critical Servers"</a> <span class="cs1-format">(PDF)</span>. 20 April 2017. Archived from <a rel="nofollow" class="external text" href="https://www.fujitsu.com/jp/documents/products/computing/servers/unix/sparc/events/2017/coolchips20/CoolChips20-rev8.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 29 August 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=SPARC64%E2%84%A2+XII%3A+Fujitsu%27s+latest+12+Core+Processor+for+Mission+Critical+Servers&rft.date=2017-04-20&rft_id=https%3A%2F%2Fwww.fujitsu.com%2Fjp%2Fdocuments%2Fproducts%2Fcomputing%2Fservers%2Funix%2Fsparc%2Fevents%2F2017%2Fcoolchips20%2FCoolChips20-rev8.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> <li id="cite_note-51"><span class="mw-cite-backlink"><b><a href="#cite_ref-51">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.fujitsu.com/global/documents/products/computing/servers/unix/sparc/downloads/manuals/en/c120-e690-14en.pdf">"Fujitsu SPARC M12 and Fujitsu M10 Server Architecture White Paper"</a> <span class="cs1-format">(PDF)</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Fujitsu+SPARC+M12+and+Fujitsu+M10+Server+Architecture+White+Paper&rft_id=https%3A%2F%2Fwww.fujitsu.com%2Fglobal%2Fdocuments%2Fproducts%2Fcomputing%2Fservers%2Funix%2Fsparc%2Fdownloads%2Fmanuals%2Fen%2Fc120-e690-14en.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="Sources">Sources</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=25" title="Edit section: Sources"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Fujitsu_Limited" class="mw-redirect" title="Fujitsu Limited">Fujitsu Limited</a> (August 2004). <i>SPARC64 V Processor For UNIX Server</i>.</li> <li>Krewell, Kevin (24 November 2003). "Fujitsu Makes SPARC See Double". <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>.</li> <li>Krewell, Kevin (24 June 2004). "SPARC's New Roadmap. <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>.</li> <li>Krewell, Kevin (25 October 2004). "SPARC Turns 90nm". <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>.</li> <li>Krewell, Kevin (14 November 2005). "SPARC's Still Going Strong". <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>.</li> <li>McGhan, Harlan (25 September 2006). "The Sun-Fujitsu APL Alliance". <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>.</li> <li>McGhan, Harlan (23 October 2006). "SPARC64 VI Ready for PrimeTime". <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>.</li> <li>Morgan, Timothy Prickett (4 September 2012). <a rel="nofollow" class="external text" href="https://www.theregister.co.uk/2012/09/04/fujitsu_sparc64_x_processor/">"Fujitsu to embiggen iron bigtime with Sparc64-X"</a>. <i><a href="/wiki/The_Register" title="The Register">The Register</a></i>.</li> <li>Morgan, Timothy Prickett (1 October 2012). <a rel="nofollow" class="external text" href="https://www.theregister.co.uk/2012/10/01/fujitsu_oracle_athena_chip_server/">"Fujitsu, Oracle pair up on future 'Athena' Sparc64 chips"</a>. <i><a href="/wiki/The_Register" title="The Register">The Register</a></i>.</li> <li>Morgan, Timothy Prickett (25 January 2013). <a rel="nofollow" class="external text" href="https://www.theregister.co.uk/2013/01/25/fujitsu_racle_athena_sparc64_x_servers/">"Fujitsu launches 'Athena' Sparc64-X servers in Japan"</a>. <i><a href="/wiki/The_Register" title="The Register">The Register</a></i>.</li> <li>Sakamoto, Mariko et al. (2003). "Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems". <i>Proceedings of the 9th International Symposium on High-Performance Computer Architecture</i>. pp. 141–152.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=26" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <dl><dt>SPARC64 V</dt></dl> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAndoYoshidaInoueSugiyama2003" class="citation conference cs1">Ando, H.; Yoshida, Y.; Inoue, A.; Sugiyama, I.; Asakawa, T.; Morita, K.; Muta, T.; Motokurumada, T.; Okada, S.; Yamashita, H.; Satsukawa, Y.; Konmoto, A.; Yamashita, R.; Sugiyama, H. (13 February 2003). <i>A 1.3 GHz fifth generation SPARC64 microprocessor</i>. 2003 IEEE International Solid-State Circuits Conference. <i>Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International</i>. pp. 246, 491. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FISSCC.2003.1234286">10.1109/ISSCC.2003.1234286</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-7803-7707-9" title="Special:BookSources/0-7803-7707-9"><bdi>0-7803-7707-9</bdi></a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0193-6530">0193-6530</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=conference&rft.jtitle=Solid-State+Circuits+Conference%2C+1997.+Digest+of+Technical+Papers.+43rd+ISSCC.%2C+1997+IEEE+International&rft.atitle=A+1.3+GHz+fifth+generation+SPARC64+microprocessor&rft.pages=246%2C+491&rft.date=2003-02-13&rft.issn=0193-6530&rft_id=info%3Adoi%2F10.1109%2FISSCC.2003.1234286&rft.isbn=0-7803-7707-9&rft.aulast=Ando&rft.aufirst=H.&rft.au=Yoshida%2C+Y.&rft.au=Inoue%2C+A.&rft.au=Sugiyama%2C+I.&rft.au=Asakawa%2C+T.&rft.au=Morita%2C+K.&rft.au=Muta%2C+T.&rft.au=Motokurumada%2C+T.&rft.au=Okada%2C+S.&rft.au=Yamashita%2C+H.&rft.au=Satsukawa%2C+Y.&rft.au=Konmoto%2C+A.&rft.au=Yamashita%2C+R.&rft.au=Sugiyama%2C+H.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAndoYoshidaInoueSugiyama2003" class="citation conference cs1">Ando, H.; Yoshida, Y.; Inoue, A.; Sugiyama, I.; Asakawa, T.; Morita, K.; Muta, T.; Motokurumada, T.; Okada, S.; Yamashita, H.; Satsukawa, Y.; Konmoto, A.; Yamashita, R.; Sugiyama, H. (2003). <i>A 1.3GHz fifth generation SPARC64 microprocessor</i>. Design Automation Conference. pp. 702–705. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F775832.776010">10.1145/775832.776010</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/1-58113-688-9" title="Special:BookSources/1-58113-688-9"><bdi>1-58113-688-9</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=A+1.3GHz+fifth+generation+SPARC64+microprocessor&rft.pages=702-705&rft.date=2003&rft_id=info%3Adoi%2F10.1145%2F775832.776010&rft.isbn=1-58113-688-9&rft.aulast=Ando&rft.aufirst=H.&rft.au=Yoshida%2C+Y.&rft.au=Inoue%2C+A.&rft.au=Sugiyama%2C+I.&rft.au=Asakawa%2C+T.&rft.au=Morita%2C+K.&rft.au=Muta%2C+T.&rft.au=Motokurumada%2C+T.&rft.au=Okada%2C+S.&rft.au=Yamashita%2C+H.&rft.au=Satsukawa%2C+Y.&rft.au=Konmoto%2C+A.&rft.au=Yamashita%2C+R.&rft.au=Sugiyama%2C+H.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFItoKomatsuTanamuraYamashita2003" class="citation conference cs1">Ito, N.; Komatsu, H.; Tanamura, Y.; Yamashita, R.; Sugiyama, H.; Sugiyama, Y.; Hamamura, H. (2003). <i>A physical design methodology for 1.3 GHz SPARC 64 microprocessor</i>. 21st International Conference on Computer Design. pp. 204–210. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FICCD.2003.1240896">10.1109/ICCD.2003.1240896</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-7695-2025-1" title="Special:BookSources/0-7695-2025-1"><bdi>0-7695-2025-1</bdi></a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/1063-6404">1063-6404</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=A+physical+design+methodology+for+1.3+GHz+SPARC+64+microprocessor&rft.pages=204-210&rft.date=2003&rft.issn=1063-6404&rft_id=info%3Adoi%2F10.1109%2FICCD.2003.1240896&rft.isbn=0-7695-2025-1&rft.aulast=Ito&rft.aufirst=N.&rft.au=Komatsu%2C+H.&rft.au=Tanamura%2C+Y.&rft.au=Yamashita%2C+R.&rft.au=Sugiyama%2C+H.&rft.au=Sugiyama%2C+Y.&rft.au=Hamamura%2C+H.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAndoKanTosakaTakahisa2008" class="citation conference cs1">Ando, Hisashige; Kan, Ryuji; Tosaka, Yoshiharu; Takahisa, Keiji; Hatanaka, Kichiji (24–27 June 2008). <i>Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor</i>. 2008 IEEE International Conference on Dependable Systems and Networks. pp. 62–69. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FDSN.2008.4630071">10.1109/DSN.2008.4630071</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4244-2397-2" title="Special:BookSources/978-1-4244-2397-2"><bdi>978-1-4244-2397-2</bdi></a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/1530-0889">1530-0889</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=Validation+of+hardware+error+recovery+mechanisms+for+the+SPARC64+V+microprocessor&rft.pages=62-69&rft.date=2008-06-24%2F2008-06-27&rft.issn=1530-0889&rft_id=info%3Adoi%2F10.1109%2FDSN.2008.4630071&rft.isbn=978-1-4244-2397-2&rft.aulast=Ando&rft.aufirst=Hisashige&rft.au=Kan%2C+Ryuji&rft.au=Tosaka%2C+Yoshiharu&rft.au=Takahisa%2C+Keiji&rft.au=Hatanaka%2C+Kichiji&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></li></ul> <dl><dt>SPARC64 VIIIfx</dt></dl> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMaruyamaYoshidaKanYamazaki2010" class="citation journal cs1">Maruyama, Takumi; Yoshida, Toshio; Kan, Ryuji; Yamazaki, Iwao; Yamamura, Shuji; Takahashi, Noriyuki; Hondou, Mikio; Okano, Hiroshi (March–April 2010). "Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing". <i>IEEE Micro</i>. <b>30</b> (2): 30–40. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FMM.2010.40">10.1109/MM.2010.40</a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0272-1732">0272-1732</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:206472881">206472881</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Micro&rft.atitle=Sparc64+VIIIfx%3A+A+New-Generation+Octocore+Processor+for+Petascale+Computing&rft.volume=30&rft.issue=2&rft.pages=30-40&rft.date=2010-03%2F2010-04&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A206472881%23id-name%3DS2CID&rft.issn=0272-1732&rft_id=info%3Adoi%2F10.1109%2FMM.2010.40&rft.aulast=Maruyama&rft.aufirst=Takumi&rft.au=Yoshida%2C+Toshio&rft.au=Kan%2C+Ryuji&rft.au=Yamazaki%2C+Iwao&rft.au=Yamamura%2C+Shuji&rft.au=Takahashi%2C+Noriyuki&rft.au=Hondou%2C+Mikio&rft.au=Okano%2C+Hiroshi&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFOkanoKawabeKanYoshida2010" class="citation conference cs1">Okano, Hiroshi; Kawabe, Yukihito; Kan, Ryuji; Yoshida, Toshio; Yamazaki, Iwao; Sakurai, Hitoshi; Hondou, Mikio; Matsui, Nobuyki; Yamashita, Hideo; Nakada, Tatsumi; Maruyama, Takumi; Asakawa, Takeo (2010). <i>Fine grained power analysis and low-power techniques of a 128GFLOPS/58W SPARC64 VIIIfx processor for peta-scale computing</i>. Symposium on VLSI Circuits. pp. 167–168. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FVLSIC.2010.5560313">10.1109/VLSIC.2010.5560313</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4244-5454-9" title="Special:BookSources/978-1-4244-5454-9"><bdi>978-1-4244-5454-9</bdi></a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/2158-5601">2158-5601</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=Fine+grained+power+analysis+and+low-power+techniques+of+a+128GFLOPS%2F58W+SPARC64+VIIIfx+processor+for+peta-scale+computing&rft.pages=167-168&rft.date=2010&rft.issn=2158-5601&rft_id=info%3Adoi%2F10.1109%2FVLSIC.2010.5560313&rft.isbn=978-1-4244-5454-9&rft.aulast=Okano&rft.aufirst=Hiroshi&rft.au=Kawabe%2C+Yukihito&rft.au=Kan%2C+Ryuji&rft.au=Yoshida%2C+Toshio&rft.au=Yamazaki%2C+Iwao&rft.au=Sakurai%2C+Hitoshi&rft.au=Hondou%2C+Mikio&rft.au=Matsui%2C+Nobuyki&rft.au=Yamashita%2C+Hideo&rft.au=Nakada%2C+Tatsumi&rft.au=Maruyama%2C+Takumi&rft.au=Asakawa%2C+Takeo&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></li></ul> <dl><dt>SPARC64 X</dt></dl> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKanTanakaSugizakiNishiyama2013" class="citation conference cs1">Kan, Ryuji; Tanaka, Tomohiro; Sugizaki, Go; Nishiyama, Ryuichi; Sakabayashi, Sota; Koyanagi, Yoichi; Iwatsuki, Ryuji; Hayasaka, Kazumi; Uemura, Taiki; Ito, Gaku; Ozeki, Yoshitomo; Adachi, Hiroyuki; Furuya, Kazuhiro; Motokurumada, Tsuyoshi (2013). <i>A 10th generation 16-core SPARC64 processor for mission-critical UNIX server</i>. IEEE International Solid-State Circuits Conference. pp. 60–61. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FISSCC.2013.6487637">10.1109/ISSCC.2013.6487637</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4673-4515-6" title="Special:BookSources/978-1-4673-4515-6"><bdi>978-1-4673-4515-6</bdi></a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0193-6530">0193-6530</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=A+10th+generation+16-core+SPARC64+processor+for+mission-critical+UNIX+server&rft.pages=60-61&rft.date=2013&rft.issn=0193-6530&rft_id=info%3Adoi%2F10.1109%2FISSCC.2013.6487637&rft.isbn=978-1-4673-4515-6&rft.aulast=Kan&rft.aufirst=Ryuji&rft.au=Tanaka%2C+Tomohiro&rft.au=Sugizaki%2C+Go&rft.au=Nishiyama%2C+Ryuichi&rft.au=Sakabayashi%2C+Sota&rft.au=Koyanagi%2C+Yoichi&rft.au=Iwatsuki%2C+Ryuji&rft.au=Hayasaka%2C+Kazumi&rft.au=Uemura%2C+Taiki&rft.au=Ito%2C+Gaku&rft.au=Ozeki%2C+Yoshitomo&rft.au=Adachi%2C+Hiroyuki&rft.au=Furuya%2C+Kazuhiro&rft.au=Motokurumada%2C+Tsuyoshi&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKanTanakaSugizakiIshizaka2014" class="citation journal cs1">Kan, Ryuji; Tanaka, Tomohiro; Sugizaki, Go; Ishizaka, Kinya; Nishiyama, Ryuichi; Sakabayashi, Sota; Koyanagi, Yoichi (January 2014). "The 10th Generation 16-Core SPARC64 Processor for Mission Critical UNIX Server". <i>IEEE Journal of Solid-State Circuits</i>. <b>49</b> (1): 32–40. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FJSSC.2013.2284650">10.1109/JSSC.2013.2284650</a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0018-9200">0018-9200</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:32362191">32362191</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Journal+of+Solid-State+Circuits&rft.atitle=The+10th+Generation+16-Core+SPARC64+Processor+for+Mission+Critical+UNIX+Server&rft.volume=49&rft.issue=1&rft.pages=32-40&rft.date=2014-01&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A32362191%23id-name%3DS2CID&rft.issn=0018-9200&rft_id=info%3Adoi%2F10.1109%2FJSSC.2013.2284650&rft.aulast=Kan&rft.aufirst=Ryuji&rft.au=Tanaka%2C+Tomohiro&rft.au=Sugizaki%2C+Go&rft.au=Ishizaka%2C+Kinya&rft.au=Nishiyama%2C+Ryuichi&rft.au=Sakabayashi%2C+Sota&rft.au=Koyanagi%2C+Yoichi&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFYoshidaMaruyamaAkizukiKan2013" class="citation journal cs1">Yoshida, Toshio; Maruyama, Takumi; Akizuki, Yasunobu; Kan, Ryuji; Kiyota, Naohiro; Ikenishi, Kiyoshi; Itou, Shigeki; Watahiki, Tomoyuki; Okano, Hiroshi (November–December 2013). "Sparc64 X: Fujitsu's New-Generation 16-Core Processor for Unix Servers". <i>IEEE Micro</i>. <b>33</b> (6): 16–24. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FMM.2013.126">10.1109/MM.2013.126</a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0272-1732">0272-1732</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:8056145">8056145</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Micro&rft.atitle=Sparc64+X%3A+Fujitsu%27s+New-Generation+16-Core+Processor+for+Unix+Servers&rft.volume=33&rft.issue=6&rft.pages=16-24&rft.date=2013-11%2F2013-12&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A8056145%23id-name%3DS2CID&rft.issn=0272-1732&rft_id=info%3Adoi%2F10.1109%2FMM.2013.126&rft.aulast=Yoshida&rft.aufirst=Toshio&rft.au=Maruyama%2C+Takumi&rft.au=Akizuki%2C+Yasunobu&rft.au=Kan%2C+Ryuji&rft.au=Kiyota%2C+Naohiro&rft.au=Ikenishi%2C+Kiyoshi&rft.au=Itou%2C+Shigeki&rft.au=Watahiki%2C+Tomoyuki&rft.au=Okano%2C+Hiroshi&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></li></ul> <dl><dt>SPARC64 XIfx</dt></dl> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFYoshidaHondouTabataKan2015" class="citation journal cs1">Yoshida, Toshio; Hondou, Mikio; Tabata, Takekazu; Kan, Ryuji; Kiyota, Naohiro; Kojima, Hiroyuki; Hosoe, Koji; Okano, Hiroshi (March–April 2015). "Sparc64 XIfx: Fujitsu's Next-Generation Processor for High-Performance Computing". <i>IEEE Micro</i>. <b>35</b> (2): 32–40. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FMM.2015.11">10.1109/MM.2015.11</a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0272-1732">0272-1732</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:206473367">206473367</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Micro&rft.atitle=Sparc64+XIfx%3A+Fujitsu%27s+Next-Generation+Processor+for+High-Performance+Computing&rft.volume=35&rft.issue=2&rft.pages=32-40&rft.date=2015-03%2F2015-04&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A206473367%23id-name%3DS2CID&rft.issn=0272-1732&rft_id=info%3Adoi%2F10.1109%2FMM.2015.11&rft.aulast=Yoshida&rft.aufirst=Toshio&rft.au=Hondou%2C+Mikio&rft.au=Tabata%2C+Takekazu&rft.au=Kan%2C+Ryuji&rft.au=Kiyota%2C+Naohiro&rft.au=Kojima%2C+Hiroyuki&rft.au=Hosoe%2C+Koji&rft.au=Okano%2C+Hiroshi&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASPARC64+V" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=SPARC64_V&action=edit&section=27" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="https://www.fujitsu.com/global/products/computing/servers/unix/sparc/key-reports/roadmap/">Fujitsu SPARC Servers Roadmap</a></li> <li><a rel="nofollow" class="external text" href="https://www.fujitsu.com/global/products/computing/servers/supercomputer/archives/">Fujitsu PRIMEHPC FX100/FX10 Supercomputers</a></li> <li><a rel="nofollow" class="external text" href="https://www.fujitsu.com/global/products/computing/servers/unix/">Fujitsu SPARC Servers</a></li> <li>Fujitsu SPARC64 <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190403225509/http://www.fujitsu.com/global/solutions/business-technology/tc/catalog/">V, VI, VII, VIIIfx, IXfx Extensions</a> at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> (archived April 3, 2019), and <a rel="nofollow" class="external text" href="https://www.fujitsu.com/global/products/computing/servers/unix/sparc/downloads/documents/">X / X+ Specification</a></li> <li><a rel="nofollow" class="external text" href="https://www.fujitsu.com/global/products/computing/servers/unix/sparc/technology/performance/processor.html">High Performance Processor SPARC64 X</a></li> <li><a rel="nofollow" class="external text" href="https://www.fujitsu.com/global/products/computing/servers/unix/sparc-enterprise/technology/performance/processor.html">Multi Core Processor SPARC64 Series</a></li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output 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"}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Fujitsu" title="Template:Fujitsu"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Fujitsu" title="Template talk:Fujitsu"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Fujitsu" title="Special:EditPage/Template:Fujitsu"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Fujitsu" style="font-size:114%;margin:0 4em"><a href="/wiki/Fujitsu" title="Fujitsu">Fujitsu</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;">Divisions and<br />subsidiaries</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left; background-color: #eee;">Current</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Amdahl_Corporation" title="Amdahl Corporation">Amdahl Corporation</a></li> <li>Fujitsu Client Computing</li> <li><a href="/wiki/Fujitsu_Computer_Products_of_America" title="Fujitsu Computer Products of America">Fujitsu Computer Products of America</a></li> <li><a href="/wiki/Fujitsu#Fujitsu_Consulting" title="Fujitsu">Fujitsu Consulting</a> <ul><li><span style="font-size:85%;"><a href="/wiki/Fujitsu_Consulting_India" class="mw-redirect" title="Fujitsu Consulting India">Fujitsu Consulting India</a></span></li></ul></li> <li><a href="/wiki/Fujitsu#Fujitsu_Laboratories_Ltd." title="Fujitsu">Fujitsu Laboratories</a></li> <li>Fujitsu Semiconductor</li> <li><a href="/wiki/Fujitsu_Technology_Solutions" title="Fujitsu Technology Solutions">Fujitsu Technology Solutions</a></li> <li><a href="/wiki/Glovia_Services_Inc" class="mw-redirect" title="Glovia Services Inc"> Glovia Services</a></li> <li><a href="/wiki/Nifty_Corporation" title="Nifty Corporation">Nifty Corporation</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left; background-color: #eee;">Former and defunct</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/FANUC" title="FANUC">FANUC</a><sup>4</sup></li> <li><a href="/wiki/HAL_Computer_Systems" title="HAL Computer Systems">HAL Computer Systems</a><sup>1</sup></li> <li><a href="/wiki/International_Computers_Limited" title="International Computers Limited">International Computers Limited</a><sup>1</sup></li> <li><a href="/wiki/Tongfu_Microelectronics" title="Tongfu Microelectronics">Nantong Fujitsu Microelectronics</a><sup>3</sup></li> <li><a href="/wiki/Ross_Technology" title="Ross Technology">Ross Technology</a><sup>1</sup></li></ul> </div></td></tr></tbody></table><div></div></td><td class="noviewer navbox-image" rowspan="6" style="width:1px;padding:0 0 0 2px"><div><span typeof="mw:File"><a href="/wiki/File:Shiodome_City_Center_2012.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e3/Shiodome_City_Center_2012.JPG/140px-Shiodome_City_Center_2012.JPG" decoding="async" width="140" height="230" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e3/Shiodome_City_Center_2012.JPG/210px-Shiodome_City_Center_2012.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e3/Shiodome_City_Center_2012.JPG/280px-Shiodome_City_Center_2012.JPG 2x" data-file-width="2075" data-file-height="3413" /></a></span></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;">Joint ventures and<br />shareholdings</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;background-color: #eee;">Current</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/General_Airconditioners" class="mw-redirect" title="General Airconditioners">General Airconditioners</a></li> <li><a href="/wiki/TranSys" title="TranSys">TranSys</a> <span style="font-size:85%;">(20%)</span></li> <li><a href="/wiki/PFU_Limited" title="PFU Limited">PFU</a> <span style="font-size:85%;">(20%)</span></li> <li><a href="/wiki/Denso_Ten" title="Denso Ten">Denso Ten</a> <span style="font-size:85%;">(14%)</span></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;background-color: #eee;">Former and defunct</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Fujitsu_Siemens_Computers" title="Fujitsu Siemens Computers">Fujitsu Siemens Computers</a><sup>2</sup></li> <li><a href="/wiki/Spansion" title="Spansion">Spansion</a><sup>3</sup></li> <li><a href="/wiki/Socionext" title="Socionext">Socionext</a><sup>4</sup></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;"><a href="/wiki/List_of_Fujitsu_products" title="List of Fujitsu products">Products, services<br />and standards</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;background-color: #eee;">Current</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Alternate_lighting_of_surfaces" title="Alternate lighting of surfaces"> ALiS</a></li> <li><a href="/wiki/BCeSIS" title="BCeSIS">BCeSIS</a></li> <li><a href="/wiki/BS2000" title="BS2000">BS2000</a></li> <li><a href="/wiki/Enon_(robot)" title="Enon (robot)"> Enon</a></li> <li><a href="/wiki/Fujitsu_Global_Cloud_Platform" class="mw-redirect" title="Fujitsu Global Cloud Platform">Global Cloud Platform</a></li> <li><a href="/wiki/HOAP" title="HOAP">HOAP</a></li> <li><a href="/wiki/Macroscope_(methodology_suite)" title="Macroscope (methodology suite)">Macroscope</a></li> <li><a href="/w/index.php?title=OpenFT_(Fujitsu)&action=edit&redlink=1" class="new" title="OpenFT (Fujitsu) (page does not exist)">OpenFT</a></li> <li><a href="/wiki/SESAM_(database)" title="SESAM (database)">SESAM</a></li> <li><a href="/wiki/VM2000" title="VM2000">VM2000</a></li></ul> <ul><li>Processors: <ul><li><a href="/wiki/Fujitsu_A64FX" title="Fujitsu A64FX">A64FX</a></li> <li><a href="/wiki/Fujitsu_FR" title="Fujitsu FR">FR</a></li> <li><a href="/wiki/FR-V_(microprocessor)" title="FR-V (microprocessor)">FR-V</a></li> <li><a class="mw-selflink-fragment" href="#SPARC64_X+">SPARC64 X+</a></li> <li><a class="mw-selflink-fragment" href="#SPARC64_XIfx">SPARC64 XIfx</a></li></ul></li></ul> <ul><li>Supercomputers and servers: <ul><li><a href="/wiki/Fugaku_(supercomputer)" title="Fugaku (supercomputer)">Fugaku</a></li> <li><a href="/wiki/K_computer" title="K computer">K computer</a></li> <li><a href="/wiki/Primergy" title="Primergy">Primergy</a></li> <li>Primequest</li></ul></li></ul> <ul><li>Business computers: <ul><li><a href="/wiki/Fujitsu_Celsius" title="Fujitsu Celsius">Celsius</a></li> <li><a href="/wiki/Fujitsu_Lifebook" title="Fujitsu Lifebook">Lifebook</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;background-color: #eee;">Defunct</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Corporate_Headquarters_Office_Technology_System" title="Corporate Headquarters Office Technology System">Corporate Headquarters Office Technology System</a></li> <li><a href="/wiki/DC/OSx" title="DC/OSx">DC/OSx</a></li> <li><a href="/wiki/Fujitsu_Eagle" title="Fujitsu Eagle">Eagle</a></li> <li><a href="/wiki/FLEPia" title="FLEPia">FLEPia</a></li> <li><a href="/wiki/FM_Towns" title="FM Towns">FM Towns</a></li> <li><a href="/wiki/FM_Towns_Marty" title="FM Towns Marty">FM Towns Marty</a> <ul><li><span style="font-size:85%;"><a href="/wiki/List_of_FM_Towns_games" title="List of FM Towns games">FM Towns games</a></span></li></ul></li> <li><a href="/wiki/FM-7" title="FM-7">FM-7</a></li> <li><a href="/wiki/FM-8" title="FM-8">FM-8</a></li> <li><a href="/wiki/FM-11" title="FM-11">FM-11</a></li> <li><a href="/wiki/Fujitsu_iPAD" title="Fujitsu iPAD">iPAD</a></li> <li><a href="/wiki/Fujitsu_Micro_16s" title="Fujitsu Micro 16s">Micro 16s</a></li> <li><a href="/wiki/Pocket_LOOX" title="Pocket LOOX">Pocket LOOX</a></li> <li><a href="/wiki/SINIX" title="SINIX">SINIX</a></li> <li><a href="/wiki/SPARC_Enterprise" title="SPARC Enterprise">SPARC Enterprise</a></li> <li><a href="/wiki/HAL_SPARC64" title="HAL SPARC64">SPARC64</a></li> <li><a href="/wiki/TurboSPARC" title="TurboSPARC">TurboSPARC</a></li> <li><a href="/wiki/Fujitsu_VP" title="Fujitsu VP">VP</a></li> <li><a href="/wiki/Fujitsu_VP2000" title="Fujitsu VP2000">VP2000</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;"><a href="/wiki/Category:Fujitsu_people" title="Category:Fujitsu people">People</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/David_Courtley" title="David Courtley">David Courtley</a></li> <li><a href="/wiki/Toshio_Ikeda" title="Toshio Ikeda">Toshio Ikeda</a></li> <li><a href="/wiki/Naoki_Yokoyama" title="Naoki Yokoyama">Naoki Yokoyama</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;">Places</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Shiodome_City_Center" title="Shiodome City Center">Shiodome City Center</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align: left;">Other</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Atlas_Consortium" title="Atlas Consortium">Atlas Consortium</a></li> <li><a href="/wiki/Fujitsu%27s_Application" title="Fujitsu's Application">Fujitsu's Application</a></li> <li><a href="/wiki/Fujitsu_Cup" title="Fujitsu Cup">Fujitsu Cup</a></li> <li><a href="/wiki/Fujitsu_Ladies" title="Fujitsu Ladies">Fujitsu Ladies</a></li> <li><a href="/wiki/Furukawa_Group" title="Furukawa Group">Furukawa Group</a></li> <li><a href="/wiki/Kawasaki_Frontale" title="Kawasaki Frontale">Kawasaki Frontale</a></li> <li><a href="/wiki/Fujitsu_Frontiers" title="Fujitsu Frontiers">Fujitsu Frontiers</a></li> <li><a href="/wiki/Fujitsu_Red_Wave" title="Fujitsu Red Wave">Fujitsu Red Wave</a></li> <li><a href="/wiki/PFU_BlueCats" title="PFU BlueCats">PFU BlueCats</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="3"><div> <ul><li><sup>1</sup><i>Now integrated into other Fujitsu divisions or business groupings</i></li> <li><sup>2</sup><i>Now wholly owned</i></li> <li><sup>3</sup><i>Sold</i></li> <li><sup>4</sup><i>Spun off</i></li></ul> <ul><li><span class="noviewer" typeof="mw:File"><span title="Category"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/16px-Symbol_category_class.svg.png" decoding="async" width="16" height="16" class="mw-file-element" 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