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class="entry-author-link" rel="author"><span class="entry-author-name">Nicolas Lozada-Smith, Power Application Engineer, Wolfspeed</span></a></span> <span class="entry-comments-link"><a href="https://www.powerelectronictips.com/mitigate-reverse-recovery-overshoot-in-mosfet-body-diode/#respond">Leave a Comment</a></span> </p></header><div class="entry-content"><div class="addtoany_share_save_container addtoany_content addtoany_content_top"><div class="a2a_kit a2a_kit_size_16 addtoany_list" data-a2a-url="https://www.powerelectronictips.com/mitigate-reverse-recovery-overshoot-in-mosfet-body-diode/" data-a2a-title="Mitigate reverse recovery overshoot in MOSFET body diodes"><a class="a2a_button_facebook" href="https://www.addtoany.com/add_to/facebook?linkurl=https%3A%2F%2Fwww.powerelectronictips.com%2Fmitigate-reverse-recovery-overshoot-in-mosfet-body-diode%2F&linkname=Mitigate%20reverse%20recovery%20overshoot%20in%20MOSFET%20body%20diodes" title="Facebook" rel="nofollow noopener" target="_blank"></a><a class="a2a_button_x" href="https://www.addtoany.com/add_to/x?linkurl=https%3A%2F%2Fwww.powerelectronictips.com%2Fmitigate-reverse-recovery-overshoot-in-mosfet-body-diode%2F&linkname=Mitigate%20reverse%20recovery%20overshoot%20in%20MOSFET%20body%20diodes" title="X" rel="nofollow noopener" target="_blank"></a><a class="a2a_button_linkedin" href="https://www.addtoany.com/add_to/linkedin?linkurl=https%3A%2F%2Fwww.powerelectronictips.com%2Fmitigate-reverse-recovery-overshoot-in-mosfet-body-diode%2F&linkname=Mitigate%20reverse%20recovery%20overshoot%20in%20MOSFET%20body%20diodes" title="LinkedIn" rel="nofollow noopener" target="_blank"></a><a class="a2a_dd addtoany_share_save addtoany_share" href="https://www.addtoany.com/share"></a></div></div><p>Because of their compact size, higher efficiency, and superior performance in high-power applications, SiC MOSFETs are now replacing Si devices in switching applications. SiC devices enable faster switching times, significantly reducing switching losses. These advantages stem from the unique electrical and material properties of SiC-based devices — snappy reverse recovery inherent to the structure of the MOSFET body diode, which tempers SiC MOSFET benefits. During a snappy reverse recovery event, devices can experience large voltage spikes, posing risks to both the device and the overall system. Additional design challenges include increased electromagnetic interference (EMI) and unintended faults, such as false gate events or parasitic turn-on [3] [4]. Fortunately, you can mitigate these effects, which optimizes system performance.</p> <h3>Reverse recovery at the system Level:</h3> <p>A SiC MOSFET integrated with a soft-body diode increases a converter circuit’s operating frequency and efficiency while decreasing the number of components.</p> <p><strong>Figure 1</strong> shows a full bridge topology of a single-phase two-level converter and a pulse pattern that will cause a reverse recovery event. At t<sub>0</sub>, all switches start in the off state. S<sub>1</sub> and S<sub>4</sub> are initially turned on during t<sub>1,</sub> letting the current pass through the load. During t<sub>2</sub>, S<sub>4</sub> returns to the off-state. The current must then change to the freewheeling path, which utilizes the body diode in S<sub>2</sub>. This time is known as dead time, and the current will decay due to the path resistance. During the transition period between t<sub>2</sub> and t<sub>3</sub>, S<sub>4</sub> turns back on, causing a shoot-through scenario that forces the body diode of S<sub>2</sub> to undergo reverse recovery. After the recovery instant, the parasitic inductance in the current path results in a voltage overshoot to maintain the current in the path.</p> <figure id="attachment_23524" aria-describedby="caption-attachment-23524" style="width: 1024px" class="wp-caption aligncenter"><a href="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure1_300dpi.png"><img decoding="async" class="wp-image-23524 size-large" src="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure1_300dpi-1024x647.png" alt="" width="1024" height="647" srcset="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure1_300dpi-1024x647.png 1024w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure1_300dpi-300x189.png 300w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure1_300dpi-768x485.png 768w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure1_300dpi-1536x970.png 1536w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure1_300dpi-2048x1293.png 2048w" sizes="(max-width: 1024px) 100vw, 1024px" /></a><figcaption id="caption-attachment-23524" class="wp-caption-text">Figure 1. The schematic of a single-phase, two-level converter shows the path of the freewheeling current (blue arrow) prior to the reverse recovery event. The pulse pattern shows the freewheeling path and reverse recovery event.</figcaption></figure> <h3>Reverse recovery and softness factor</h3> <p>A snappy or reverse recovery occurs when a SiC diode transitions from “forward-conduction” to an “off-state.” To simplify the reverse recovery event, <strong>Figure 2</strong> shows a diode’s ideal recovery current and voltage waveform (Fig. 2a) and a non-ideal current waveform for a MOSFET (Fig. 2b).</p> <figure id="attachment_23525" aria-describedby="caption-attachment-23525" style="width: 1024px" class="wp-caption aligncenter"><a href="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure2_300dpi.png"><img decoding="async" class="wp-image-23525 size-large" src="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure2_300dpi-1024x418.png" alt="" width="1024" height="418" srcset="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure2_300dpi-1024x418.png 1024w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure2_300dpi-300x122.png 300w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure2_300dpi-768x313.png 768w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure2_300dpi-1536x627.png 1536w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure2_300dpi-2048x836.png 2048w" sizes="(max-width: 1024px) 100vw, 1024px" /></a><figcaption id="caption-attachment-23525" class="wp-caption-text">Figure 2. This comparison of (a) the ideal reverse recovery current (solid line) and voltage (dashed line) of a diode and (b) a measured MOSFET body diode current recovery waveform shows that the measured waveform contains ringing caused by parasitic inductance in the circuit.</figcaption></figure> <p>Fig. 2a shows two regions of time based on I<sub>diode</sub>. From t<sub>0</sub> to t<sub>1, the reverse voltage VR (dashed line) application</sub> forces the current to drop at a constant rate, d<em>I</em>/d<em>t</em>. During this period, the rate at which d<em>I</em>/d<em>t</em> changes is determined mainly by the applied V<sub>R</sub>, circuit elements such as the complementary device’s external R<sub>G</sub>, and parasitic circuit inductance. At the start of t<sub>1, excess carriers are removed from the drift region, and a depletion region begins to form, which build</sub>s the voltage across the diode. The voltage reaches its target value V<sub>R</sub> when I<sub>rrm</sub> is met at t<sub>2, and there is no additional bias from the voltage source VR that increases</sub> the current magnitude further. From t<sub>2 </sub>to t<sub>3, </sub>the voltage overshoots its target value as the parasitic inductance opposes the decreasing loop current, eventually settling at V<sub>R</sub>. The voltage overshoot peak depends on the circuit’s parasitic inductance and rate of change of recovery current dI<sub>r</sub>/dt<sub>(max)</sub>.</p> <p>Typically, we use two formulas to evaluate the softness factor of a recovery event. Below is S1, a single-parameter ratio:</p> <p><a href="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_eq1.png"><img loading="lazy" decoding="async" class="aligncenter wp-image-23526 " src="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_eq1.png" alt="" width="87" height="62" /></a></p> <p>where t<sub>a</sub> = t<sub>2</sub>– t<sub>1</sub> and t<sub>b</sub> = t<sub>3 </sub>– t<sub>2</sub>.</p> <p>When S<sub>1</sub> = 1, the time it takes for the current to reach Irrm equals the time it takes to return to 0 A or leakage values.</p> <p>A second method of measuring the softness of a reverse recovery event is defined in the equation below:</p> <p><a href="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_eq2.png"><img loading="lazy" decoding="async" class="aligncenter wp-image-23527" src="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_eq2.png" alt="" width="127" height="82" /></a></p> <p>Where: dI/dt is the current at the initial zero-crossing of the commuting current, and dI<sub>r</sub>/dt<sub>(max)</sub> is the max return current during t<sub>b</sub>.</p> <p>When S<sub>2</sub> = 1, the current flow rate into and out of the body diode is equivalent. Most devices never achieve an ideal S<sub>1</sub> and S<sub>2</sub> value. A snappy recovery will occur when S1 and S2 are less than 1, while a value greater than 1 is considered a soft recovery.</p> <p><strong>Figure 3</strong> shows a half-bridge test circuit used to perform reverse recovery characterization. Like the pulse pattern described in Figure 1, the high-side device will initially switch on and off to allow a controlled amount of current to conduct through the body diode of the low-side MOSFET. The high-side device then turns back on, forcing the freewheeling current to commutate, overshoot, and eventually settle, completing the reverse recovery event. Test boards and other external circuitry should limit the influence on body diode characterization. Do your best to minimize the test board’s stray inductance in accordance with good PCB layout practice and ensure that the external circuitry is not limiting the switching capabilities of the MOSFET. Minimizing the area of the power and gate loops will reduce inductance and achieve greater switching control.</p> <figure id="attachment_23528" aria-describedby="caption-attachment-23528" style="width: 1024px" class="wp-caption aligncenter"><a href="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure3_300dpi.png"><img loading="lazy" decoding="async" class="size-large wp-image-23528" src="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure3_300dpi-1024x678.png" alt="" width="1024" height="678" srcset="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure3_300dpi-1024x678.png 1024w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure3_300dpi-300x199.png 300w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure3_300dpi-768x509.png 768w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure3_300dpi.png 1054w" sizes="auto, (max-width: 1024px) 100vw, 1024px" /></a><figcaption id="caption-attachment-23528" class="wp-caption-text">Figure 3. This test circuit of a half-bridge configuration lets you characterize reverse recovery parameters in a MOSFET</figcaption></figure> <h3>Managing reverse recovery and EMI</h3> <p>Temperature dependence is the major factor for V<sub>DS</sub> overshoot and peak I<sub>DS</sub> values during the reverse recovery event. Tests performed at high temperatures will provide “worst-case scenario” results. The free-wheeling current through the body diode slowly dissipates over time as heat. This heat causes a temperature change in the junction, decreasing the conductive path’s resistance and thus increasing the initial d<em>I</em>/d<em>t</em>.</p> <p><strong>Figure 4a</strong> shows the temperature dependence of the reverse recovery current. The test parameters include an R<sub>G(ext)</sub> = 5 Ω, V<sub>DS</sub> = 800 V, and I<sub>D</sub> = 40 A. Increasing external gate resistance is recommended to achieve softer recovery characteristics such as reduced Q<sub>rr</sub>, I<sub>rrm</sub>, and dampened ringing. Improvements in reverse recovery obtained from increasing R<sub>G(ext)</sub> are shown in Figure 4b). Higher gate resistance reduces the risk of snappy reverse recovery and can increase switching losses due to increased t<sub>rr</sub> if overly dampened. Figure 4b) shows the reverse recovery current plotted versus time for various external R<sub>G</sub> values. The reduced ringing effect in the current waveform will reduce unwanted EMI.</p> <figure id="attachment_23529" aria-describedby="caption-attachment-23529" style="width: 1017px" class="wp-caption aligncenter"><a href="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure4_300dpi.png"><img loading="lazy" decoding="async" class="wp-image-23529 size-full" src="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure4_300dpi.png" alt="body diodes" width="1017" height="359" srcset="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure4_300dpi.png 1017w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure4_300dpi-300x106.png 300w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure4_300dpi-768x271.png 768w" sizes="auto, (max-width: 1017px) 100vw, 1017px" /></a><figcaption id="caption-attachment-23529" class="wp-caption-text">Figure 4. ID vs. t (a) at 25°C and 175°C and (b) for various RG(ext) values shows the effects of temperature and external gate resistance on reverse recovery.</figcaption></figure> <p><strong>Table 1</strong> demonstrates that increasing R<sub>G</sub> will decrease d<em>I</em>/d<em>t</em> and Q<sub>rr</sub> and dampen the initial oscillatory peak current level. In contrast, increasing R<sub>G</sub> also increases t<sub>rr</sub>, creating a tradeoff between overshoot and switching times. Always visually inspect the waveform after measuring it.</p> <figure id="attachment_23530" aria-describedby="caption-attachment-23530" style="width: 1020px" class="wp-caption aligncenter"><a href="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Table1.png"><img loading="lazy" decoding="async" class="wp-image-23530 size-full" src="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Table1.png" alt="body diodes" width="1020" height="279" srcset="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Table1.png 1020w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Table1-300x82.png 300w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Table1-768x210.png 768w" sizes="auto, (max-width: 1020px) 100vw, 1020px" /></a><figcaption id="caption-attachment-23530" class="wp-caption-text">Table 1. Reverse diode characteristics for various RG(ext) values.</figcaption></figure> <h3>Impact of reverse recovery on voltage and energy</h3> <p>You must also consider reverse recovery effects on voltage to ensure a power circuit won’t exceed the device’s safe operating area (SOA). Parasitic inductance in the commutating current path causes an overshoot in the voltage waveform. If ignored, you will violate SOAs and reduce the system efficiency and lifetime of the semiconductor device.</p> <p><strong>Figure 5a</strong> shows the I<sub>SD</sub> recovery waveform of the low-side device as a function of time at T = 125°C and V<sub>DS</sub> = 800 V. <strong>Figure 5b</strong> shows the V<sub>DS</sub> recovery waveform as a function of time and <strong>Figure 5c</strong> shows the peak V<sub>DS</sub> value as a function of external gate resistance. The devices tested are in a half-bridge configuration with 4 dies in parallel per switch position. As expected, the V<sub>DS</sub> peak decreases as R<sub>G(ext)</sub> increases. An R<sub>G(ext)</sub> >3 Ω is required to remain within the device’s SOA.</p> <figure id="attachment_23531" aria-describedby="caption-attachment-23531" style="width: 1024px" class="wp-caption aligncenter"><a href="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure5_300dpi.png"><img loading="lazy" decoding="async" class="wp-image-23531 size-large" src="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure5_300dpi-1024x847.png" alt="body diodes" width="1024" height="847" srcset="https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure5_300dpi-1024x847.png 1024w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure5_300dpi-300x248.png 300w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure5_300dpi-768x635.png 768w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure5_300dpi-1536x1270.png 1536w, https://www.powerelectronictips.com/wp-content/uploads/2024/11/Wolfspeed_Figure5_300dpi.png 2000w" sizes="auto, (max-width: 1024px) 100vw, 1024px" /></a><figcaption id="caption-attachment-23531" class="wp-caption-text">Figure 5. Shows the (a) IDS vs t (b) VDS vs t (c) and VDS peak vs. RG(ext) results using four die in parallel in a half-bridge configuration. Peak VDS can be easily managed by increasing the external gate resistance to a module.</figcaption></figure> <h3>Conclusion</h3> <p>The circuits shown help you mitigate overshoot voltage and unwanted EMI during the reverse recovery of a SiC MOSFET body diode. Reverse recovery is an inherent occurrence in MOSFET body diodes, and negative effects are amplified by increased junction temperature. Board or module circuit parasitics create oscillatory voltage spikes that can break device SOA limitations. You should accurately characterize the softness factor of a MOSFET body diode to understand the benefits gained from mitigation techniques fully. Increasing external gate resistance is the most common method for softening recovery characteristics and managing V<sub>DS</sub> overshoot.</p> <h3><strong>References</strong></h3> <p>1993. J. B. Mohit Bhatnagar, “<a href="https://ieeexplore.ieee.org/document/199372" target="_blank" rel="noopener">Comparison of 6H-SiC, 3C-SiC, and Si for Power Devices</a>,” IEEE Transactions on Electronic Devices, vol. 40, no. 3, pp. 645-655, 1993.Singh R., S. Ryu, J.W. Palmour, A.R. Hefner. J. Lai, “<a href="https://ieeexplore.ieee.org/document/856782" target="_blank" rel="noopener">1500 V, 4 Amp 4H-Sic JBS Diodes</a>,” in International Symposium on Power Semiconductor Devices, Toulouse, 2000.<br /> Romero, A., “<a href="https://assets.wolfspeed.com/uploads/dlm_uploads/2023/07/Wolfspeed_PRD-06933_Capacitance_Ratio_and_Parasitic_Turn-On.pdf" target="_blank" rel="noopener">Capacitance Ratio and Parasitic Turn-on</a>,” Wolfspeed Inc., Durham, 2023.<br /> Yuan, X., S. Walder and N. Oswald, “<a href="https://ieeexplore.ieee.org/abstract/document/6860245" target="_blank" rel="noopener">EMI Generation Characteristics of SiC and Si Diodes: Influence of Reverse-Recovery Characteristics</a>,” IEEE Transactions of Power Electronics, vol. 30, no. 3, pp. 1131-1136, 2015.</p> <div class="bawmrp"> <h3>You may also like:</h3> <ul> <li style="float:left;width:120px;height:auto;overflow:hidden;list-style:none;border-right: 1px solid #ccc;text-align:center;padding:0px 5px;" class="bawmrp_manual"><a href="https://www.powerelectronictips.com/bipolar-junction-transistors-show-their-muscle/"><img loading="lazy" decoding="async" width="100" height="100" src="https://www.powerelectronictips.com/wp-content/uploads/2024/10/Nexperia_Fig7-1-150x150.png" class="attachment-100x100 size-100x100 wp-post-image" alt="" /><br />Bipolar junction transistors show their muscle</a></li> <li style="float:left;width:120px;height:auto;overflow:hidden;list-style:none;border-right: 1px solid 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