{"title":"Charge-Pump with a Regulated Cascode Circuit for Reducing Current Mismatch in PLLs","authors":"Jae Hyung Noh, Hang Geun Jeong","volume":7,"journal":"International Journal of Electrical and Computer Engineering","pagesStart":1002,"pagesEnd":1005,"ISSN":"1307-6892","URL":"https:\/\/publications.waset.org\/pdf\/3951","abstract":"<p>The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase\/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-&mu;m 1.8-V CMOS technology.<\/p>\r\n","references":"[1] M. Mansuri, D. Liu, and C. K. Yang, \"Fast Frequency Acquisition\r\nPhase-Frequency Detectors for Gsamples\/s Phase-Locked Loops\", IEEE\r\nJournal of Solid-State Circuits, vol. 37, pp. 1331-4, Oct. 2002.\r\n[2] S. Cheng, H. Tong, J. Silva-Martinez, and A. I. Karsilayan, \"Design and\r\nAnalysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge\r\nPump With Minimum Output Current Variation and Accurate Matching\",\r\n[3] J. Maneatis, \"Low-Jitter and Process-Independent DLL and PLL Based\r\non Self-Biased Techniques,\" ISSCC Digest of Technical Papers, 1996.\r\n[4] David A. Johns, Ken Martin, Analog Integrated Circuit Design, New\r\nYork: John Willey & Sons, 1997.","publisher":"World Academy of Science, Engineering and Technology","index":"Open Science Index 7, 2007"}