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class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Use_of_FPGAs"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4</span> <span>Use of FPGAs</span> </div> </a> <ul id="toc-Use_of_FPGAs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Use_of_NPUs" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Use_of_NPUs"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.5</span> <span>Use of NPUs</span> </div> </a> <ul id="toc-Use_of_NPUs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Emergence_of_dedicated_AI_accelerator_ASICs" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Emergence_of_dedicated_AI_accelerator_ASICs"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.6</span> <span>Emergence of dedicated AI accelerator ASICs</span> </div> </a> <ul id="toc-Emergence_of_dedicated_AI_accelerator_ASICs-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Ongoing_research" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Ongoing_research"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Ongoing research</span> </div> </a> <button aria-controls="toc-Ongoing_research-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Ongoing research subsection</span> </button> <ul id="toc-Ongoing_research-sublist" class="vector-toc-list"> <li id="toc-In-memory_computing_architectures" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#In-memory_computing_architectures"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>In-memory computing architectures</span> </div> </a> <ul id="toc-In-memory_computing_architectures-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-In-memory_computing_with_analog_resistive_memories" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#In-memory_computing_with_analog_resistive_memories"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>In-memory computing with analog resistive memories</span> </div> </a> <ul id="toc-In-memory_computing_with_analog_resistive_memories-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Atomically_thin_semiconductors" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Atomically_thin_semiconductors"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Atomically thin semiconductors</span> </div> </a> <ul id="toc-Atomically_thin_semiconductors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Integrated_photonic_tensor_core" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Integrated_photonic_tensor_core"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>Integrated photonic tensor core</span> </div> </a> <ul id="toc-Integrated_photonic_tensor_core-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Nomenclature" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Nomenclature"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Nomenclature</span> </div> </a> <ul id="toc-Nomenclature-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Deep_learning_processors_(DLPs)" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Deep_learning_processors_(DLPs)"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Deep learning processors (DLPs)</span> </div> </a> <button aria-controls="toc-Deep_learning_processors_(DLPs)-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Deep learning processors (DLPs) subsection</span> </button> <ul id="toc-Deep_learning_processors_(DLPs)-sublist" class="vector-toc-list"> <li id="toc-Digital_DLPs" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Digital_DLPs"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1</span> <span>Digital DLPs</span> </div> </a> <ul id="toc-Digital_DLPs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Hybrid_DLPs" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Hybrid_DLPs"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.2</span> <span>Hybrid DLPs</span> </div> </a> <ul id="toc-Hybrid_DLPs-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Benchmarks" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Benchmarks"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Benchmarks</span> </div> </a> <ul id="toc-Benchmarks-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Potential_applications" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Potential_applications"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Potential applications</span> </div> </a> <ul id="toc-Potential_applications-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" title="Table of Contents" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" 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Available in 19 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-19" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">19 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%85%D8%B3%D8%B1%D8%B9_%D8%A7%D9%84%D8%B0%D9%83%D8%A7%D8%A1_%D8%A7%D9%84%D8%A7%D8%B5%D8%B7%D9%86%D8%A7%D8%B9%D9%8A" title="مسرع الذكاء الاصطناعي – Arabic" lang="ar" hreflang="ar" data-title="مسرع الذكاء الاصطناعي" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-be mw-list-item"><a href="https://be.wikipedia.org/wiki/%D0%9D%D0%B5%D0%B9%D1%80%D0%BE%D0%BD%D0%BD%D1%8B_%D0%BF%D1%80%D0%B0%D1%86%D1%8D%D1%81%D0%B0%D1%80" title="Нейронны працэсар – Belarusian" lang="be" hreflang="be" data-title="Нейронны працэсар" data-language-autonym="Беларуская" data-language-local-name="Belarusian" class="interlanguage-link-target"><span>Беларуская</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Accelerador_d%27IA" title="Accelerador d'IA – Catalan" lang="ca" hreflang="ca" data-title="Accelerador d'IA" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/AI_akceler%C3%A1tor" title="AI akcelerátor – Czech" lang="cs" hreflang="cs" data-title="AI akcelerátor" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/KI-Beschleuniger" title="KI-Beschleuniger – German" lang="de" hreflang="de" data-title="KI-Beschleuniger" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/AI_kiirendi" title="AI kiirendi – Estonian" lang="et" hreflang="et" data-title="AI kiirendi" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Acelerador_de_IA" title="Acelerador de IA – Spanish" lang="es" hreflang="es" data-title="Acelerador de IA" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%B4%D8%AA%D8%A7%D8%A8%E2%80%8C%D8%AF%D9%87%D9%86%D8%AF%D9%87_%D9%87%D9%88%D8%B4_%D9%85%D8%B5%D9%86%D9%88%D8%B9%DB%8C" title="شتاب‌دهنده هوش مصنوعی – Persian" lang="fa" hreflang="fa" data-title="شتاب‌دهنده هوش مصنوعی" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Puce_d%27acc%C3%A9l%C3%A9ration_de_r%C3%A9seaux_de_neurones" title="Puce d'accélération de réseaux de neurones – French" lang="fr" hreflang="fr" data-title="Puce d'accélération de réseaux de neurones" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/AI_%EA%B0%80%EC%86%8D%EA%B8%B0" title="AI 가속기 – Korean" lang="ko" hreflang="ko" data-title="AI 가속기" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Akselerator_kecerdasan_buatan" title="Akselerator kecerdasan buatan – Indonesian" lang="id" hreflang="id" data-title="Akselerator kecerdasan buatan" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Acceleratore_di_Intelligenza_Artificiale" title="Acceleratore di Intelligenza Artificiale – Italian" lang="it" hreflang="it" data-title="Acceleratore di Intelligenza Artificiale" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/AI%E3%82%A2%E3%82%AF%E3%82%BB%E3%83%A9%E3%83%AC%E3%83%BC%E3%82%BF" title="AIアクセラレータ – Japanese" lang="ja" hreflang="ja" data-title="AIアクセラレータ" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Acelerador_de_IA" title="Acelerador de IA – Portuguese" lang="pt" hreflang="pt" data-title="Acelerador de IA" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Unitate_de_procesare_neural%C4%83" title="Unitate de procesare neurală – Romanian" lang="ro" hreflang="ro" data-title="Unitate de procesare neurală" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/%D0%9D%D0%B5%D0%B9%D1%80%D0%BE%D0%BD%D0%BD%D1%8B%D0%B9_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D1%81%D0%BE%D1%80" title="Нейронный процессор – Russian" lang="ru" hreflang="ru" data-title="Нейронный процессор" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/Teko%C3%A4lykiihdytin" title="Tekoälykiihdytin – Finnish" lang="fi" hreflang="fi" data-title="Tekoälykiihdytin" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/%D0%A8%D0%86-%D0%BF%D1%80%D0%B8%D1%81%D0%BA%D0%BE%D1%80%D1%8E%D0%B2%D0%B0%D1%87" title="ШІ-прискорювач – Ukrainian" lang="uk" hreflang="uk" data-title="ШІ-прискорювач" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/%E4%BA%BA%E5%B7%A5%E6%99%BA%E8%83%BD%E5%8A%A0%E9%80%9F%E5%99%A8" title="人工智能加速器 – Chinese" lang="zh" hreflang="zh" data-title="人工智能加速器" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a 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class="mw-redirectedfrom">(Redirected from <a href="/w/index.php?title=AI_accelerator&redirect=no" class="mw-redirect" title="AI accelerator">AI accelerator</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Hardware acceleration unit for artificial intelligence tasks</div> <p class="mw-empty-elt"> </p><p>A <b>neural processing unit</b> (<b>NPU</b>), also known as <b>AI accelerator</b> or <b>deep learning processor,</b> is a class of specialized <a href="/wiki/Hardware_acceleration" title="Hardware acceleration">hardware accelerator</a><sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> or computer system<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> designed to accelerate <a href="/wiki/Artificial_intelligence" title="Artificial intelligence">artificial intelligence</a> (AI) and <a href="/wiki/Machine_learning" title="Machine learning">machine learning</a> applications, including <a href="/wiki/Artificial_neural_network" class="mw-redirect" title="Artificial neural network">artificial neural networks</a> and <a href="/wiki/Computer_vision" title="Computer vision">computer vision</a>. Typical applications include algorithms for <a href="/wiki/Robotics" title="Robotics">robotics</a>, <a href="/wiki/Internet_of_Things" class="mw-redirect" title="Internet of Things">Internet of Things</a>, and other <a href="/wiki/Data_(computing)" class="mw-redirect" title="Data (computing)">data</a>-intensive or sensor-driven tasks.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> They are often <a href="/wiki/Manycore_processor" title="Manycore processor">manycore</a> designs and generally focus on <a href="/wiki/Precision_(computer_science)" title="Precision (computer science)">low-precision</a> arithmetic, novel <a href="/wiki/Dataflow_architecture" title="Dataflow architecture">dataflow architectures</a> or <a href="/wiki/In-memory_computing" class="mw-redirect" title="In-memory computing">in-memory computing</a> capability. As of 2024<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=Neural_processing_unit&action=edit">[update]</a></sup>, a typical AI <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> chip <a href="/wiki/Transistor_count" title="Transistor count">contains tens of billions</a> of <a href="/wiki/MOSFET" title="MOSFET">MOSFETs</a>.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p><p>AI accelerators are used in mobile devices such as Apple <a href="/wiki/IPhone" title="IPhone">iPhones</a> and <a href="/wiki/Huawei" title="Huawei">Huawei</a> cellphones,<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> and personal computers such as <a href="/wiki/Intel" title="Intel">Intel</a> laptops,<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> <a href="/wiki/AMD" title="AMD">AMD</a> laptops<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> and <a href="/wiki/Apple_silicon" title="Apple silicon">Apple silicon</a> <a href="/wiki/Mac_(computer)" title="Mac (computer)">Macs</a>.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> Accelerators are used in <a href="/wiki/Cloud_computing" title="Cloud computing">cloud computing</a> servers, including <a href="/wiki/Tensor_processing_unit" class="mw-redirect" title="Tensor processing unit">tensor processing units</a> (TPU) in <a href="/wiki/Google_Cloud_Platform" title="Google Cloud Platform">Google Cloud Platform</a><sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> and <a href="/wiki/Trainium" class="mw-redirect" title="Trainium">Trainium</a> and <a href="/wiki/Inferentia" class="mw-redirect" title="Inferentia">Inferentia</a> chips in <a href="/wiki/Amazon_Web_Services" title="Amazon Web Services">Amazon Web Services</a>.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> A number of vendor-specific terms exist for devices in this category, and it is an <a href="/wiki/Emerging_technologies" title="Emerging technologies">emerging technology</a> without a <a href="/wiki/Dominant_design" title="Dominant design">dominant design</a>. </p><p><a href="/wiki/Graphics_processing_units" class="mw-redirect" title="Graphics processing units">Graphics processing units</a> designed by companies such as <a href="/wiki/Nvidia" title="Nvidia">Nvidia</a> and <a href="/wiki/AMD" title="AMD">AMD</a> often include AI-specific hardware, and are commonly used as AI accelerators, both for <a href="/wiki/Machine_learning" title="Machine learning">training</a> and <a href="/wiki/Inference_engine" title="Inference engine">inference</a>.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Computer systems have frequently complemented the <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> with special-purpose accelerators for specialized tasks, known as <a href="/wiki/Coprocessor" title="Coprocessor">coprocessors</a>. Notable <a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific</a> <a href="/wiki/Expansion_card" title="Expansion card">hardware units</a> include <a href="/wiki/Video_card" class="mw-redirect" title="Video card">video cards</a> for <a href="/wiki/Computer_graphics" title="Computer graphics">graphics</a>, <a href="/wiki/Sound_card" title="Sound card">sound cards</a>, <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">graphics processing units</a> and <a href="/wiki/Digital_signal_processor" title="Digital signal processor">digital signal processors</a>. As <a href="/wiki/Deep_learning" title="Deep learning">deep learning</a> and <a href="/wiki/Artificial_intelligence" title="Artificial intelligence">artificial intelligence</a> workloads rose in prominence in the 2010s, specialized hardware units were developed or adapted from existing products to <a href="/wiki/Hardware_acceleration" title="Hardware acceleration">accelerate</a> these tasks. </p> <div class="mw-heading mw-heading3"><h3 id="Early_attempts">Early attempts</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=2" title="Edit section: Early attempts"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>First attempts like <a href="/wiki/Intel" title="Intel">Intel</a>'s ETANN 80170NX incorporated analog circuits to compute neural functions.<sup id="cite_ref-ICH_1_13-0" class="reference"><a href="#cite_note-ICH_1-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p><p>Later all-digital chips like the Nestor/Intel <a href="/wiki/Ni1000" title="Ni1000">Ni1000</a> followed. As early as 1993, <a href="/wiki/Digital_signal_processor" title="Digital signal processor">digital signal processors</a> were used as neural network accelerators to accelerate <a href="/wiki/Optical_character_recognition" title="Optical character recognition">optical character recognition</a> software.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> </p><p>By 1988, Wei Zhang et al. had discussed fast optical implementations of convolutional neural networks for alphabet recognition.<sup id="cite_ref-wz1988_15-0" class="reference"><a href="#cite_note-wz1988-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-wz1990_16-0" class="reference"><a href="#cite_note-wz1990-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </p><p>In the 1990s, there were also attempts to create parallel high-throughput systems for workstations aimed at various applications, including neural network simulations.<sup id="cite_ref-DCS_1_17-0" class="reference"><a href="#cite_note-DCS_1-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-krste_general_purpose_18-0" class="reference"><a href="#cite_note-krste_general_purpose-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a>-based accelerators were also first explored in the 1990s for both inference and training.<sup id="cite_ref-fpga-inference_19-0" class="reference"><a href="#cite_note-fpga-inference-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-fpga-training_20-0" class="reference"><a href="#cite_note-fpga-training-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> </p><p>In 2014, Chen et al. proposed DianNao (Chinese for "electric brain"),<sup id="cite_ref-:1_21-0" class="reference"><a href="#cite_note-:1-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> to accelerate deep neural networks especially. DianNao provides 452 Gop/s peak performance (of key operations in deep neural networks) in a footprint of 3.02 mm<sup>2</sup> and 485 mW. Later, the successors (DaDianNao,<sup id="cite_ref-:2_22-0" class="reference"><a href="#cite_note-:2-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> ShiDianNao,<sup id="cite_ref-:3_23-0" class="reference"><a href="#cite_note-:3-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> PuDianNao<sup id="cite_ref-:4_24-0" class="reference"><a href="#cite_note-:4-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup>) were proposed by the same group, forming the DianNao Family<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Smartphone" title="Smartphone">Smartphones</a> began incorporating AI accelerators starting with the <a href="/wiki/Qualcomm_Snapdragon_820" class="mw-redirect" title="Qualcomm Snapdragon 820">Qualcomm Snapdragon 820</a> in 2015.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Heterogeneous_computing">Heterogeneous computing</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=3" title="Edit section: Heterogeneous computing"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous computing</a></div> <p>Heterogeneous computing incorporates many specialized processors in a single system, or a single chip, each optimized for a specific type of task. Architectures such as the <a href="/wiki/Cell_(microprocessor)" class="mw-redirect" title="Cell (microprocessor)">Cell microprocessor</a><sup id="cite_ref-cell_28-0" class="reference"><a href="#cite_note-cell-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> have features significantly overlapping with AI accelerators including: support for packed low precision arithmetic, <a href="/wiki/Dataflow_architecture" title="Dataflow architecture">dataflow architecture</a>, and prioritizing throughput over latency. The Cell microprocessor has been applied to a number of tasks<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> including AI.<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> </p><p>In the 2000s, <a href="/wiki/Central_processing_unit" title="Central processing unit">CPUs</a> also gained increasingly wide <a href="/wiki/SIMD" class="mw-redirect" title="SIMD">SIMD</a> units, driven by video and gaming workloads; as well as support for packed low-precision <a href="/wiki/Data_type" title="Data type">data types</a>.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> Due to the increasing performance of CPUs, they are also used for running AI workloads. CPUs are superior for <a href="/wiki/Deep_neural_network" class="mw-redirect" title="Deep neural network">DNNs</a> with small or medium-scale parallelism, for sparse DNNs and in low-batch-size scenarios. </p> <div class="mw-heading mw-heading3"><h3 id="Use_of_GPUs">Use of GPUs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=4" title="Edit section: Use of GPUs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing units</a> or GPUs are specialized hardware for the manipulation of images and calculation of local image properties. The mathematical basis of neural networks and <a href="/wiki/Graphics_pipeline" title="Graphics pipeline">image manipulation</a> are similar, <a href="/wiki/Embarrassingly_parallel" title="Embarrassingly parallel">embarrassingly parallel</a> tasks involving matrices, leading GPUs to become increasingly used for machine learning tasks.<sup id="cite_ref-HPC_36-0" class="reference"><a href="#cite_note-HPC-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-INC_1_37-0" class="reference"><a href="#cite_note-INC_1-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> </p><p>In 2012, Alex Krizhevsky adopted two GPUs to train a deep learning network, i.e., AlexNet,<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> which won the champion of the ISLVRC-2012 competition. During the 2010s, GPU manufacturers such as <a href="/wiki/Nvidia" title="Nvidia">Nvidia</a> added deep learning related features in both hardware (e.g., INT8 operators) and software (e.g., cuDNN Library). </p><p>Over the 2010s GPUs continued to evolve in a direction to facilitate deep learning, both for training and inference in devices such as <a href="/wiki/Self-driving_car" title="Self-driving car">self-driving cars</a>.<sup id="cite_ref-ND_1_39-0" class="reference"><a href="#cite_note-ND_1-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-NIS_1_40-0" class="reference"><a href="#cite_note-NIS_1-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> GPU developers such as Nvidia <a href="/wiki/NVLink" title="NVLink">NVLink</a> are developing additional connective capability for the kind of dataflow workloads AI benefits from. As GPUs have been increasingly applied to AI acceleration, GPU manufacturers have incorporated <a href="/wiki/Neural_network" title="Neural network">neural network</a>-<a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">specific</a> hardware to further accelerate these tasks.<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-CUDA9_42-0" class="reference"><a href="#cite_note-CUDA9-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Tensor_core" class="mw-redirect" title="Tensor core">Tensor cores</a> are intended to speed up the training of neural networks.<sup id="cite_ref-CUDA9_42-1" class="reference"><a href="#cite_note-CUDA9-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> </p><p>GPUs continue to be used in large-scale AI applications. For example, <a href="/wiki/Summit_(supercomputer)" title="Summit (supercomputer)">Summit</a>, a supercomputer from IBM for <a href="/wiki/Oak_Ridge_National_Laboratory" title="Oak Ridge National Laboratory">Oak Ridge National Laboratory</a>,<sup id="cite_ref-SOR_1_43-0" class="reference"><a href="#cite_note-SOR_1-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> contains 27,648 <a href="/wiki/Nvidia_Tesla" title="Nvidia Tesla">Nvidia Tesla</a> V100 cards, which can be used to accelerate deep learning algorithms. </p> <div class="mw-heading mw-heading3"><h3 id="Use_of_FPGAs">Use of FPGAs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=5" title="Edit section: Use of FPGAs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Deep learning frameworks are still evolving, making it hard to design custom hardware. <a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable</a> devices such as <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate arrays</a> (FPGA) make it easier to evolve hardware, frameworks, and software <a href="/wiki/Integrated_design" title="Integrated design">alongside each other</a>.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-fpga-inference_19-1" class="reference"><a href="#cite_note-fpga-inference-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-fpga-training_20-1" class="reference"><a href="#cite_note-fpga-training-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> </p><p>Microsoft has used FPGA chips to accelerate inference for real-time deep learning services.<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Use_of_NPUs">Use of NPUs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=6" title="Edit section: Use of NPUs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Neural Processing Units (NPU) are another more native approach. Since 2017, several CPUs and SoCs have on-die NPUs: for example, <a href="/wiki/Meteor_Lake_(microarchitecture)" class="mw-redirect" title="Meteor Lake (microarchitecture)">Intel Meteor Lake</a>, <a href="/wiki/Apple_A11" title="Apple A11">Apple A11</a>. </p> <div class="mw-heading mw-heading3"><h3 id="Emergence_of_dedicated_AI_accelerator_ASICs">Emergence of dedicated AI accelerator ASICs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=7" title="Edit section: Emergence of dedicated AI accelerator ASICs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>While GPUs and FPGAs perform far better than CPUs for AI-related tasks, a factor of up to 10 in efficiency<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> may be gained with a more specific design, via an <a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuit</a> (ASIC).<sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> These accelerators employ strategies such as optimized <a href="/wiki/Cache-aware_model" class="mw-redirect" title="Cache-aware model">memory use</a><sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (November 2017)">citation needed</span></a></i>]</sup> and the use of <a href="/wiki/Minifloat" title="Minifloat">lower precision arithmetic</a> to accelerate calculation and increase <a href="/wiki/Throughput" class="mw-redirect" title="Throughput">throughput</a> of computation.<sup id="cite_ref-lowprecision_50-0" class="reference"><a href="#cite_note-lowprecision-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> Some low-precision <a href="/wiki/Floating-point_format" class="mw-redirect" title="Floating-point format">floating-point formats</a> used for AI acceleration are <a href="/wiki/Half-precision_floating-point_format" title="Half-precision floating-point format">half-precision</a> and the <a href="/wiki/Bfloat16_floating-point_format" title="Bfloat16 floating-point format">bfloat16 floating-point format</a>.<sup id="cite_ref-toms_Inte_52-0" class="reference"><a href="#cite_note-toms_Inte-52"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-arxiv_1711.10604_53-0" class="reference"><a href="#cite_note-arxiv_1711.10604-53"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Cerebras" title="Cerebras">Cerebras Systems</a> has built a dedicated AI accelerator based on the largest processor in the industry, the second-generation Wafer Scale Engine (WSE-2), to support deep learning workloads.<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup><a href="/wiki/Amazon_Web_Services" title="Amazon Web Services">Amazon Web Services</a> NeuronCores are heterogenous compute-units that power Tranium, Tranium2, Inferentia, and Inferentia2 chips consisting of 4 main engines: Tensor, Vector, Scalar, and GPSIMD, with on-chip software-managed SRAM memory to manage data locality and data prefetch.<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Ongoing_research">Ongoing research</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=8" title="Edit section: Ongoing research"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="In-memory_computing_architectures">In-memory computing architectures</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=9" title="Edit section: In-memory computing architectures"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Neural_processing_unit&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">October 2018</span>)</i></span></div></td></tr></tbody></table> <p>In June 2017, <a href="/wiki/IBM" title="IBM">IBM</a> researchers announced an architecture in contrast to the <a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann architecture</a> based on <a href="/wiki/In-memory_processing" title="In-memory processing">in-memory computing</a> and <a href="/wiki/Phase-change_memory" title="Phase-change memory">phase-change memory</a> arrays applied to temporal <a href="/wiki/Correlation_(statistics)" class="mw-redirect" title="Correlation (statistics)">correlation</a> detection, intending to generalize the approach to <a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">heterogeneous computing</a> and <a href="/wiki/Massively_parallel" title="Massively parallel">massively parallel</a> systems.<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup> In October 2018, IBM researchers announced an architecture based on in-memory processing and <a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">modeled on the human brain's synaptic network</a> to accelerate <a href="/wiki/Deep_neural_network" class="mw-redirect" title="Deep neural network">deep neural networks</a>.<sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup> The system is based on phase-change memory arrays.<sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="In-memory_computing_with_analog_resistive_memories">In-memory computing with analog resistive memories</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=10" title="Edit section: In-memory computing with analog resistive memories"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 2019, researchers from Politecnico di Milano found a way to solve systems of linear equations in a few tens of nanoseconds via a single operation. Their algorithm is based on <a href="/wiki/In-memory_computing" class="mw-redirect" title="In-memory computing">in-memory computing</a> with analog resistive memories which performs with high efficiencies of time and energy, via conducting <a href="/wiki/Matrix%E2%80%93vector_multiplication" class="mw-redirect" title="Matrix–vector multiplication">matrix–vector multiplication</a> in one step using Ohm's law and Kirchhoff's law. The researchers showed that a feedback circuit with cross-point resistive memories can solve algebraic problems such as systems of linear equations, matrix eigenvectors, and differential equations in just one step. Such an approach improves computational times drastically in comparison with digital algorithms.<sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Atomically_thin_semiconductors">Atomically thin semiconductors</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=11" title="Edit section: Atomically thin semiconductors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 2020, Marega et al. published experiments with a large-area active channel material for developing logic-in-memory devices and circuits based on <a href="/wiki/Floating-gate" class="mw-redirect" title="Floating-gate">floating-gate</a> <a href="/wiki/Field-effect_transistor" title="Field-effect transistor">field-effect transistors</a> (FGFETs).<sup id="cite_ref-atomthin_61-0" class="reference"><a href="#cite_note-atomthin-61"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup> Such atomically thin <a href="/wiki/Semiconductor" title="Semiconductor">semiconductors</a> are considered promising for energy-efficient <a href="/wiki/Machine_learning" title="Machine learning">machine learning</a> applications, where the same basic device structure is used for both logic operations and data storage. The authors used two-dimensional materials such as semiconducting <a href="/wiki/Molybdenum_disulphide" class="mw-redirect" title="Molybdenum disulphide">molybdenum disulphide</a> to precisely tune FGFETs as building blocks in which logic operations can be performed with the memory elements.<sup id="cite_ref-atomthin_61-1" class="reference"><a href="#cite_note-atomthin-61"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Integrated_photonic_tensor_core">Integrated photonic tensor core</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=12" title="Edit section: Integrated photonic tensor core"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 1988, Wei Zhang et al. discussed fast optical implementations of <a href="/wiki/Convolutional_neural_networks" class="mw-redirect" title="Convolutional neural networks">convolutional neural networks</a> for alphabet recognition.<sup id="cite_ref-wz1988_15-1" class="reference"><a href="#cite_note-wz1988-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-wz1990_16-1" class="reference"><a href="#cite_note-wz1990-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> In 2021, J. Feldmann et al. proposed an integrated <a href="/wiki/Photonic" class="mw-redirect" title="Photonic">photonic</a> <a href="/wiki/Hardware_accelerator" class="mw-redirect" title="Hardware accelerator">hardware accelerator</a> for parallel convolutional processing.<sup id="cite_ref-photonic_62-0" class="reference"><a href="#cite_note-photonic-62"><span class="cite-bracket">[</span>62<span class="cite-bracket">]</span></a></sup> The authors identify two key advantages of integrated photonics over its electronic counterparts: (1) massively parallel data transfer through <a href="/wiki/Wavelength" title="Wavelength">wavelength</a> division <a href="/wiki/Multiplexing" title="Multiplexing">multiplexing</a> in conjunction with <a href="/wiki/Frequency_comb" title="Frequency comb">frequency combs</a>, and (2) extremely high data modulation speeds.<sup id="cite_ref-photonic_62-1" class="reference"><a href="#cite_note-photonic-62"><span class="cite-bracket">[</span>62<span class="cite-bracket">]</span></a></sup> Their system can execute trillions of multiply-accumulate operations per second, indicating the potential of <a href="/wiki/Photonic_integrated_circuit" title="Photonic integrated circuit">integrated</a> <a href="/wiki/Photonics" title="Photonics">photonics</a> in data-heavy AI applications.<sup id="cite_ref-photonic_62-2" class="reference"><a href="#cite_note-photonic-62"><span class="cite-bracket">[</span>62<span class="cite-bracket">]</span></a></sup> Optical processors that can also perform backpropagation for artificial neural networks have been experimentally developed.<sup id="cite_ref-63" class="reference"><a href="#cite_note-63"><span class="cite-bracket">[</span>63<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Nomenclature">Nomenclature</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=13" title="Edit section: Nomenclature"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>As of 2016, the field is still in flux and vendors are pushing their own marketing term for what amounts to an "AI accelerator", in the hope that their designs and <a href="/wiki/Application_programming_interface" class="mw-redirect" title="Application programming interface">APIs</a> will become the <a href="/wiki/Dominant_design" title="Dominant design">dominant design</a>. There is no consensus on the boundary between these devices, nor the exact form they will take; however several examples clearly aim to fill this new space, with a fair amount of overlap in capabilities. </p><p>In the past when consumer <a href="/wiki/Graphics_accelerator" class="mw-redirect" title="Graphics accelerator">graphics accelerators</a> emerged, the industry eventually adopted <a href="/wiki/Nvidia" title="Nvidia">Nvidia</a>'s self-assigned term, "the GPU",<sup id="cite_ref-64" class="reference"><a href="#cite_note-64"><span class="cite-bracket">[</span>64<span class="cite-bracket">]</span></a></sup> as the collective noun for "graphics accelerators", which had taken many forms before <span class="cleanup-needed-content" style="padding-left:0.1em; padding-right:0.1em; color:var(--color-subtle, #54595d); border:1px solid var(--border-color-subtle, #c8ccd1);">settling on an overall <a href="/wiki/Graphics_pipeline" title="Graphics pipeline">pipeline</a> implementing a model presented by <a href="/wiki/Direct3D" title="Direct3D">Direct3D</a></span><sup class="noprint Inline-Template" style="margin-left:0.1em; white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify"><span title="The text near this tag may need clarification or removal of jargon. (July 2024)">clarification needed</span></a></i>]</sup>. </p><p>All models of Intel <a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a> processors have a <i>Versatile Processor Unit</i> (<i>VPU</i>) built-in for accelerating <a href="/wiki/Statistical_inference" title="Statistical inference">inference</a> for computer vision and deep learning.<sup id="cite_ref-65" class="reference"><a href="#cite_note-65"><span class="cite-bracket">[</span>65<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Deep_learning_processors_(DLPs)"><span id="Deep_learning_processors_.28DLPs.29"></span>Deep learning processors (DLPs)</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=14" title="Edit section: Deep learning processors (DLPs)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Inspired from the pioneer work of DianNao Family, many DLPs are proposed in both academia and industry with design optimized to leverage the features of deep neural networks for high efficiency. At ISCA 2016, three sessions (15%) of the accepted papers, focused on architecture designs about deep learning. Such efforts include Eyeriss (MIT),<sup id="cite_ref-:5_66-0" class="reference"><a href="#cite_note-:5-66"><span class="cite-bracket">[</span>66<span class="cite-bracket">]</span></a></sup> EIE (Stanford),<sup id="cite_ref-:6_67-0" class="reference"><a href="#cite_note-:6-67"><span class="cite-bracket">[</span>67<span class="cite-bracket">]</span></a></sup> Minerva (Harvard),<sup id="cite_ref-68" class="reference"><a href="#cite_note-68"><span class="cite-bracket">[</span>68<span class="cite-bracket">]</span></a></sup> Stripes (University of Toronto) in academia,<sup id="cite_ref-69" class="reference"><a href="#cite_note-69"><span class="cite-bracket">[</span>69<span class="cite-bracket">]</span></a></sup> TPU (Google),<sup id="cite_ref-:0_70-0" class="reference"><a href="#cite_note-:0-70"><span class="cite-bracket">[</span>70<span class="cite-bracket">]</span></a></sup> and MLU (<a href="/wiki/Cambricon" class="mw-redirect" title="Cambricon">Cambricon</a>) in industry.<sup id="cite_ref-71" class="reference"><a href="#cite_note-71"><span class="cite-bracket">[</span>71<span class="cite-bracket">]</span></a></sup> We listed several representative works in Table 1. </p> <table class="wikitable"> <tbody><tr> <th colspan="8">Table 1. Typical DLPs </th></tr> <tr> <th>Year </th> <th>DLPs </th> <th>Institution </th> <th>Type </th> <th>Computation </th> <th>Memory Hierarchy </th> <th>Control </th> <th>Peak Performance </th></tr> <tr> <td rowspan="2">2014 </td> <td>DianNao<sup id="cite_ref-:1_21-1" class="reference"><a href="#cite_note-:1-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> </td> <td>ICT, CAS </td> <td>digital </td> <td>vector <a href="/wiki/Multiply%E2%80%93accumulate_operation" title="Multiply–accumulate operation">MACs</a> </td> <td>scratchpad </td> <td><a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> </td> <td>452 Gops (16-bit) </td></tr> <tr> <td>DaDianNao<sup id="cite_ref-:2_22-1" class="reference"><a href="#cite_note-:2-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> </td> <td>ICT, CAS </td> <td>digital </td> <td>vector MACs </td> <td>scratchpad </td> <td>VLIW </td> <td>5.58 Tops (16-bit) </td></tr> <tr> <td rowspan="2">2015 </td> <td>ShiDianNao<sup id="cite_ref-:3_23-1" class="reference"><a href="#cite_note-:3-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> </td> <td>ICT, CAS </td> <td>digital </td> <td>scalar MACs </td> <td>scratchpad </td> <td>VLIW </td> <td>194 Gops (16-bit) </td></tr> <tr> <td>PuDianNao<sup id="cite_ref-:4_24-1" class="reference"><a href="#cite_note-:4-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> </td> <td>ICT, CAS </td> <td>digital </td> <td>vector MACs </td> <td>scratchpad </td> <td>VLIW </td> <td>1,056 Gops (16-bit) </td></tr> <tr> <td rowspan="4">2016 </td> <td>DnnWeaver </td> <td>Georgia Tech </td> <td>digital </td> <td>Vector MACs </td> <td>scratchpad </td> <td>- </td> <td>- </td></tr> <tr> <td>EIE<sup id="cite_ref-:6_67-1" class="reference"><a href="#cite_note-:6-67"><span class="cite-bracket">[</span>67<span class="cite-bracket">]</span></a></sup> </td> <td>Stanford </td> <td>digital </td> <td>scalar MACs </td> <td>scratchpad </td> <td>- </td> <td>102 Gops (16-bit) </td></tr> <tr> <td>Eyeriss<sup id="cite_ref-:5_66-1" class="reference"><a href="#cite_note-:5-66"><span class="cite-bracket">[</span>66<span class="cite-bracket">]</span></a></sup> </td> <td>MIT </td> <td>digital </td> <td>scalar MACs </td> <td>scratchpad </td> <td>- </td> <td>67.2 Gops (16-bit) </td></tr> <tr> <td>Prime<sup id="cite_ref-:7_72-0" class="reference"><a href="#cite_note-:7-72"><span class="cite-bracket">[</span>72<span class="cite-bracket">]</span></a></sup> </td> <td>UCSB </td> <td>hybrid </td> <td><a href="/wiki/In-memory_processing" title="In-memory processing">Process-in-Memory</a> </td> <td>ReRAM </td> <td>- </td> <td>- </td></tr> <tr> <td rowspan="4">2017 </td> <td>TPU<sup id="cite_ref-:0_70-1" class="reference"><a href="#cite_note-:0-70"><span class="cite-bracket">[</span>70<span class="cite-bracket">]</span></a></sup> </td> <td>Google </td> <td>digital </td> <td>scalar MACs </td> <td>scratchpad </td> <td><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a> </td> <td>92 Tops (8-bit) </td></tr> <tr> <td>PipeLayer<sup id="cite_ref-:8_73-0" class="reference"><a href="#cite_note-:8-73"><span class="cite-bracket">[</span>73<span class="cite-bracket">]</span></a></sup> </td> <td>U of Pittsburgh </td> <td>hybrid </td> <td>Process-in-Memory </td> <td>ReRAM </td> <td>- </td> <td> </td></tr> <tr> <td>FlexFlow </td> <td>ICT, CAS </td> <td>digital </td> <td>scalar MACs </td> <td>scratchpad </td> <td>- </td> <td>420 Gops () </td></tr> <tr> <td>DNPU<sup id="cite_ref-74" class="reference"><a href="#cite_note-74"><span class="cite-bracket">[</span>74<span class="cite-bracket">]</span></a></sup> </td> <td>KAIST </td> <td>digital </td> <td>scalar MACS </td> <td>scratchpad </td> <td>- </td> <td>300 Gops(16bit) <p>1200 Gops(4bit) </p> </td></tr> <tr> <td rowspan="3">2018 </td> <td>MAERI </td> <td>Georgia Tech </td> <td>digital </td> <td>scalar MACs </td> <td>scratchpad </td> <td>- </td> <td> </td></tr> <tr> <td>PermDNN </td> <td>City University of New York </td> <td>digital </td> <td>vector MACs </td> <td>scratchpad </td> <td>- </td> <td>614.4 Gops (16-bit) </td></tr> <tr> <td>UNPU<sup id="cite_ref-75" class="reference"><a href="#cite_note-75"><span class="cite-bracket">[</span>75<span class="cite-bracket">]</span></a></sup> </td> <td>KAIST </td> <td>digital </td> <td>scalar MACs </td> <td>scratchpad </td> <td>- </td> <td>345.6 Gops(16bit) <p>691.2 Gops(8b) 1382 Gops(4bit) 7372 Gops(1bit) </p> </td></tr> <tr> <td rowspan="2">2019 </td> <td>FPSA </td> <td>Tsinghua </td> <td>hybrid </td> <td>Process-in-Memory </td> <td>ReRAM </td> <td>- </td> <td> </td></tr> <tr> <td>Cambricon-F </td> <td>ICT, CAS </td> <td>digital </td> <td>vector MACs </td> <td>scratchpad </td> <td>FISA </td> <td>14.9 Tops (F1, 16-bit) <p>956 Tops (F100, 16-bit) </p> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Digital_DLPs">Digital DLPs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=15" title="Edit section: Digital DLPs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The major components of DLPs architecture usually include a computation component, the on-chip memory hierarchy, and the control logic that manages the data communication and computing flows. </p><p>Regarding the computation component, as most operations in deep learning can be aggregated into vector operations, the most common ways for building computation components in digital DLPs are the <a href="/wiki/Multiply%E2%80%93accumulate_operation" title="Multiply–accumulate operation">MAC</a>-based (multiplier-accumulation) organization, either with vector MACs<sup id="cite_ref-:1_21-2" class="reference"><a href="#cite_note-:1-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:2_22-2" class="reference"><a href="#cite_note-:2-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:4_24-2" class="reference"><a href="#cite_note-:4-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> or scalar MACs.<sup id="cite_ref-:0_70-2" class="reference"><a href="#cite_note-:0-70"><span class="cite-bracket">[</span>70<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:3_23-2" class="reference"><a href="#cite_note-:3-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:5_66-2" class="reference"><a href="#cite_note-:5-66"><span class="cite-bracket">[</span>66<span class="cite-bracket">]</span></a></sup> Rather than <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> or <a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">SIMT</a> in general processing devices, deep learning domain-specific parallelism is better explored on these MAC-based organizations. Regarding the memory hierarchy, as deep learning algorithms require high bandwidth to provide the computation component with sufficient data, DLPs usually employ a relatively larger size (tens of kilobytes or several megabytes) on-chip buffer but with dedicated on-chip data reuse strategy and data exchange strategy to alleviate the burden for memory bandwidth. For example, DianNao, 16 16-in vector MAC, requires 16 × 16 × 2 = 512 16-bit data, i.e., almost 1024 GB/s bandwidth requirements between computation components and buffers. With on-chip reuse, such bandwidth requirements are reduced drastically.<sup id="cite_ref-:1_21-3" class="reference"><a href="#cite_note-:1-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> Instead of the widely used cache in general processing devices, DLPs always use scratchpad memory as it could provide higher data reuse opportunities by leveraging the relatively regular data access pattern in deep learning algorithms. Regarding the control logic, as the deep learning algorithms keep evolving at a dramatic speed, DLPs start to leverage dedicated ISA (instruction set architecture) to support the deep learning domain flexibly. At first, DianNao used a VLIW-style instruction set where each instruction could finish a layer in a DNN. Cambricon<sup id="cite_ref-76" class="reference"><a href="#cite_note-76"><span class="cite-bracket">[</span>76<span class="cite-bracket">]</span></a></sup> introduces the first deep learning domain-specific ISA, which could support more than ten different deep learning algorithms. TPU also reveals five key instructions from the CISC-style ISA. </p> <div class="mw-heading mw-heading3"><h3 id="Hybrid_DLPs">Hybrid DLPs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=16" title="Edit section: Hybrid DLPs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Hybrid DLPs emerge for DNN inference and training acceleration because of their high efficiency. Processing-in-memory (PIM) architectures are one most important type of hybrid DLP. The key design concept of PIM is to bridge the gap between computing and memory, with the following manners: 1) Moving computation components into memory cells, controllers, or memory chips to alleviate the memory wall issue.<sup id="cite_ref-:8_73-1" class="reference"><a href="#cite_note-:8-73"><span class="cite-bracket">[</span>73<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:9_77-0" class="reference"><a href="#cite_note-:9-77"><span class="cite-bracket">[</span>77<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-78" class="reference"><a href="#cite_note-78"><span class="cite-bracket">[</span>78<span class="cite-bracket">]</span></a></sup> Such architectures significantly shorten data paths and leverage much higher internal bandwidth, hence resulting in attractive performance improvement. 2) Build high efficient DNN engines by adopting computational devices. In 2013, HP Lab demonstrated the astonishing capability of adopting ReRAM crossbar structure for computing.<sup id="cite_ref-79" class="reference"><a href="#cite_note-79"><span class="cite-bracket">[</span>79<span class="cite-bracket">]</span></a></sup> Inspiring by this work, tremendous work are proposed to explore the new architecture and system design based on ReRAM,<sup id="cite_ref-:7_72-1" class="reference"><a href="#cite_note-:7-72"><span class="cite-bracket">[</span>72<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-80" class="reference"><a href="#cite_note-80"><span class="cite-bracket">[</span>80<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-81" class="reference"><a href="#cite_note-81"><span class="cite-bracket">[</span>81<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:8_73-2" class="reference"><a href="#cite_note-:8-73"><span class="cite-bracket">[</span>73<span class="cite-bracket">]</span></a></sup> phase change memory,<sup id="cite_ref-:9_77-1" class="reference"><a href="#cite_note-:9-77"><span class="cite-bracket">[</span>77<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-82" class="reference"><a href="#cite_note-82"><span class="cite-bracket">[</span>82<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-83" class="reference"><a href="#cite_note-83"><span class="cite-bracket">[</span>83<span class="cite-bracket">]</span></a></sup> etc. </p> <div class="mw-heading mw-heading2"><h2 id="Benchmarks">Benchmarks</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=17" title="Edit section: Benchmarks"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Benchmarks such as MLPerf and others may be used to evaluate the performance of AI accelerators.<sup id="cite_ref-84" class="reference"><a href="#cite_note-84"><span class="cite-bracket">[</span>84<span class="cite-bracket">]</span></a></sup> Table 2 lists several typical benchmarks for AI accelerators. </p> <table class="wikitable"> <caption>Table 2. Benchmarks. </caption> <tbody><tr> <th>Year </th> <th>NN Benchmark </th> <th>Affiliations </th> <th># of microbenchmarks </th> <th># of component benchmarks </th> <th># of application benchmarks </th></tr> <tr> <td>2012 </td> <td>BenchNN </td> <td>ICT, CAS </td> <td>N/A </td> <td>12 </td> <td>N/A </td></tr> <tr> <td>2016 </td> <td>Fathom </td> <td>Harvard </td> <td>N/A </td> <td>8 </td> <td>N/A </td></tr> <tr> <td>2017 </td> <td>BenchIP </td> <td>ICT, CAS </td> <td>12 </td> <td>11 </td> <td>N/A </td></tr> <tr> <td>2017 </td> <td>DAWNBench </td> <td>Stanford </td> <td>8 </td> <td>N/A </td> <td>N/A </td></tr> <tr> <td>2017 </td> <td>DeepBench </td> <td>Baidu </td> <td>4 </td> <td>N/A </td> <td>N/A </td></tr> <tr> <td>2018 </td> <td>AI Benchmark </td> <td>ETH Zurich </td> <td>N/A </td> <td>26 </td> <td>N/A </td></tr> <tr> <td>2018 </td> <td>MLPerf </td> <td>Harvard, Intel, and Google, etc. </td> <td>N/A </td> <td>7 </td> <td>N/A </td></tr> <tr> <td>2019 </td> <td>AIBench </td> <td>ICT, CAS and Alibaba, etc. </td> <td>12 </td> <td>16 </td> <td>2 </td></tr> <tr> <td>2019 </td> <td>NNBench-X </td> <td>UCSB </td> <td>N/A </td> <td>10 </td> <td>N/A </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Potential_applications">Potential applications</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=18" title="Edit section: Potential applications"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Agricultural_robot" title="Agricultural robot">Agricultural robots</a>, for example, herbicide-free weed control.<sup id="cite_ref-85" class="reference"><a href="#cite_note-85"><span class="cite-bracket">[</span>85<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Vehicular_automation" title="Vehicular automation">Autonomous vehicles</a>: Nvidia has targeted their <a href="/wiki/Drive_PX-series" class="mw-redirect" title="Drive PX-series">Drive PX-series</a> boards at this application.<sup id="cite_ref-86" class="reference"><a href="#cite_note-86"><span class="cite-bracket">[</span>86<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Computer-aided_diagnosis" title="Computer-aided diagnosis">Computer-aided diagnosis</a></li> <li><a href="/wiki/Industrial_robot" title="Industrial robot">Industrial robots</a>, increasing the range of tasks that can be automated, by adding adaptability to variable situations.</li> <li><a href="/wiki/Machine_translation" title="Machine translation">Machine translation</a></li> <li><a href="/wiki/Military_robot" title="Military robot">Military robots</a></li> <li><a href="/wiki/Natural_language_processing" title="Natural language processing">Natural language processing</a></li> <li><a href="/wiki/Search_engine" title="Search engine">Search engines</a>, increasing the <a href="/wiki/Energy_efficiency_in_computing" class="mw-redirect" title="Energy efficiency in computing">energy efficiency</a> of <a href="/wiki/Data_center" title="Data center">data centers</a> and the ability to use increasingly advanced <a href="/wiki/Information_retrieval" title="Information retrieval">queries</a>.</li> <li><a href="/wiki/Unmanned_aerial_vehicle" title="Unmanned aerial vehicle">Unmanned aerial vehicles</a>, e.g. navigation systems, e.g. the <a href="/wiki/Movidius_Myriad_2" class="mw-redirect" title="Movidius Myriad 2">Movidius Myriad 2</a> has been demonstrated successfully guiding autonomous drones.<sup id="cite_ref-87" class="reference"><a href="#cite_note-87"><span class="cite-bracket">[</span>87<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Voice_user_interface" title="Voice user interface">Voice user interface</a>, e.g. in mobile phones, a target for Qualcomm <a href="/wiki/Zeroth_(software)" title="Zeroth (software)">Zeroth</a>.<sup id="cite_ref-88" class="reference"><a href="#cite_note-88"><span class="cite-bracket">[</span>88<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=19" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Cognitive_computer" title="Cognitive computer">Cognitive computer</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic engineering</a></li> <li><a href="/wiki/Optical_neural_network" title="Optical neural network">Optical neural network</a></li> <li><a href="/wiki/Physical_neural_network" title="Physical neural network">Physical neural network</a></li> <li><a href="/wiki/UALink" title="UALink">UALink</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Neural_processing_unit&action=edit&section=20" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 32em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20170811193632/https://www.v3.co.uk/v3-uk/news/3014293/intel-unveils-movidius-compute-stick-usb-ai-accelerator">"Intel unveils Movidius Compute Stick USB AI Accelerator"</a>. July 21, 2017. Archived from <a rel="nofollow" class="external text" href="https://www.v3.co.uk/v3-uk/news/3014293/intel-unveils-movidius-compute-stick-usb-ai-accelerator">the original</a> on August 11, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">August 11,</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+unveils+Movidius+Compute+Stick+USB+AI+Accelerator&rft.date=2017-07-21&rft_id=https%3A%2F%2Fwww.v3.co.uk%2Fv3-uk%2Fnews%2F3014293%2Fintel-unveils-movidius-compute-stick-usb-ai-accelerator&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://insidehpc.com/2017/06/inspurs-unveils-gx4-ai-accelerator/">"Inspurs unveils GX4 AI Accelerator"</a>. June 21, 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Inspurs+unveils+GX4+AI+Accelerator&rft.date=2017-06-21&rft_id=https%3A%2F%2Finsidehpc.com%2F2017%2F06%2Finspurs-unveils-gx4-ai-accelerator%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWiggers2019" class="citation cs2">Wiggers, Kyle (November 6, 2019) [2019], <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200306120524/https://venturebeat.com/2019/11/06/neural-magic-raises-15-million-to-boost-ai-training-speed-on-off-the-shelf-processors/"><i>Neural Magic raises $15 million to boost AI inferencing speed on off-the-shelf processors</i></a>, archived from <a rel="nofollow" class="external text" href="https://venturebeat.com/2019/11/06/neural-magic-raises-15-million-to-boost-ai-training-speed-on-off-the-shelf-processors/">the original</a> on March 6, 2020<span class="reference-accessdate">, retrieved <span class="nowrap">March 14,</span> 2020</span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Neural+Magic+raises+%2415+million+to+boost+AI+inferencing+speed+on+off-the-shelf+processors&rft.date=2019-11-06&rft.aulast=Wiggers&rft.aufirst=Kyle&rft_id=https%3A%2F%2Fventurebeat.com%2F2019%2F11%2F06%2Fneural-magic-raises-15-million-to-boost-ai-training-speed-on-off-the-shelf-processors%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.eetimes.com/google-designing-ai-processors/">"Google Designing AI Processors"</a>. May 18, 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Google+Designing+AI+Processors&rft.date=2016-05-18&rft_id=https%3A%2F%2Fwww.eetimes.com%2Fgoogle-designing-ai-processors%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span> Google using its own AI accelerators.</span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMoss2022" class="citation web cs1">Moss, Sebastian (March 23, 2022). <a rel="nofollow" class="external text" href="https://www.datacenterdynamics.com/en/news/nvidia-reveals-new-hopper-h100-gpu-with-80-billion-transistors/">"Nvidia reveals new Hopper H100 GPU, with 80 billion transistors"</a>. <i>Data Center Dynamics</i><span class="reference-accessdate">. Retrieved <span class="nowrap">January 30,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Data+Center+Dynamics&rft.atitle=Nvidia+reveals+new+Hopper+H100+GPU%2C+with+80+billion+transistors&rft.date=2022-03-23&rft.aulast=Moss&rft.aufirst=Sebastian&rft_id=https%3A%2F%2Fwww.datacenterdynamics.com%2Fen%2Fnews%2Fnvidia-reveals-new-hopper-h100-gpu-with-80-billion-transistors%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://consumer.huawei.com/en/press/news/2017/ifa2017-kirin970">"HUAWEI Reveals the Future of Mobile AI at IFA"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=HUAWEI+Reveals+the+Future+of+Mobile+AI+at+IFA&rft_id=https%3A%2F%2Fconsumer.huawei.com%2Fen%2Fpress%2Fnews%2F2017%2Fifa2017-kirin970&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/newsroom/news/intels-lunar-lake-processors-arriving-q3-2024.html">"Intel's Lunar Lake Processors Arriving Q3 2024"</a>. <i>Intel</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=Intel%27s+Lunar+Lake+Processors+Arriving+Q3+2024&rft_id=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fnewsroom%2Fnews%2Fintels-lunar-lake-processors-arriving-q3-2024.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/technologies/xdna.html">"AMD XDNA Architecture"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+XDNA+Architecture&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Ftechnologies%2Fxdna.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://machinelearning.apple.com/research/neural-engine-transformers">"Deploying Transformers on the Apple Neural Engine"</a>. <i>Apple Machine Learning Research</i><span class="reference-accessdate">. Retrieved <span class="nowrap">August 24,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Apple+Machine+Learning+Research&rft.atitle=Deploying+Transformers+on+the+Apple+Neural+Engine&rft_id=https%3A%2F%2Fmachinelearning.apple.com%2Fresearch%2Fneural-engine-transformers&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJouppiYoungPatilPatterson2017" class="citation journal cs1">Jouppi, Norman P.; et al. (June 24, 2017). <a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F3140659.3080246">"In-Datacenter Performance Analysis of a Tensor Processing Unit"</a>. <i>ACM SIGARCH Computer Architecture News</i>. <b>45</b> (2): <span class="nowrap">1–</span>12. <a href="/wiki/ArXiv_(identifier)" class="mw-redirect" title="ArXiv (identifier)">arXiv</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://arxiv.org/abs/1704.04760">1704.04760</a></span>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F3140659.3080246">10.1145/3140659.3080246</a></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=ACM+SIGARCH+Computer+Architecture+News&rft.atitle=In-Datacenter+Performance+Analysis+of+a+Tensor+Processing+Unit&rft.volume=45&rft.issue=2&rft.pages=%3Cspan+class%3D%22nowrap%22%3E1-%3C%2Fspan%3E12&rft.date=2017-06-24&rft_id=info%3Aarxiv%2F1704.04760&rft_id=info%3Adoi%2F10.1145%2F3140659.3080246&rft.aulast=Jouppi&rft.aufirst=Norman+P.&rft.au=Young%2C+Cliff&rft.au=Patil%2C+Nishant&rft.au=Patterson%2C+David&rft.au=Agrawal%2C+Gaurav&rft.au=Bajwa%2C+Raminder&rft.au=Bates%2C+Sarah&rft.au=Bhatia%2C+Suresh&rft.au=Boden%2C+Nan&rft.au=Borchers%2C+Al&rft.au=Boyle%2C+Rick&rft.au=Cantin%2C+Pierre-luc&rft.au=Chao%2C+Clifford&rft.au=Clark%2C+Chris&rft.au=Coriell%2C+Jeremy&rft.au=Daley%2C+Mike&rft.au=Dau%2C+Matt&rft.au=Dean%2C+Jeffrey&rft.au=Gelb%2C+Ben&rft.au=Ghaemmaghami%2C+Tara+Vazir&rft.au=Gottipati%2C+Rajendra&rft.au=Gulland%2C+William&rft.au=Hagmann%2C+Robert&rft.au=Ho%2C+C.+Richard&rft.au=Hogberg%2C+Doug&rft.au=Hu%2C+John&rft.au=Hundt%2C+Robert&rft.au=Hurt%2C+Dan&rft.au=Ibarz%2C+Julian&rft.au=Jaffey%2C+Aaron&rft_id=https%3A%2F%2Fdoi.org%2F10.1145%252F3140659.3080246&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amazon.science/how-silicon-innovation-became-the-secret-sauce-behind-awss-success">"How silicon innovation became the 'secret sauce' behind AWS's success"</a>. <i>Amazon Science</i>. July 27, 2022<span class="reference-accessdate">. Retrieved <span class="nowrap">July 19,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Amazon+Science&rft.atitle=How+silicon+innovation+became+the+%27secret+sauce%27+behind+AWS%27s+success&rft.date=2022-07-27&rft_id=https%3A%2F%2Fwww.amazon.science%2Fhow-silicon-innovation-became-the-secret-sauce-behind-awss-success&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFPatelNishballXie2023" class="citation web cs1">Patel, Dylan; Nishball, Daniel; Xie, Myron (November 9, 2023). <a rel="nofollow" class="external text" href="https://www.semianalysis.com/p/nvidias-new-china-ai-chips-circumvent">"Nvidia's New China AI Chips Circumvent US Restrictions"</a>. <i>SemiAnalysis</i><span class="reference-accessdate">. Retrieved <span class="nowrap">February 7,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=SemiAnalysis&rft.atitle=Nvidia%27s+New+China+AI+Chips+Circumvent+US+Restrictions&rft.date=2023-11-09&rft.aulast=Patel&rft.aufirst=Dylan&rft.au=Nishball%2C+Daniel&rft.au=Xie%2C+Myron&rft_id=https%3A%2F%2Fwww.semianalysis.com%2Fp%2Fnvidias-new-china-ai-chips-circumvent&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-ICH_1-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-ICH_1_13-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDvorak,_J.C.1990" class="citation web cs1">Dvorak, J.C. (May 29, 1990). <a rel="nofollow" class="external text" href="https://archive.org/details/PC_Magazine_1990_05_29_v9n10/page/n83/mode/2up">"Inside Track"</a>. PC Magazine<span class="reference-accessdate">. Retrieved <span class="nowrap">December 26,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Inside+Track&rft.pub=PC+Magazine&rft.date=1990-05-29&rft.au=Dvorak%2C+J.C.&rft_id=https%3A%2F%2Farchive.org%2Fdetails%2FPC_Magazine_1990_05_29_v9n10%2Fpage%2Fn83%2Fmode%2F2up&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-14">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=FwFduRA_L6Q">"convolutional neural network demo from 1993 featuring DSP32 accelerator"</a>. <i><a href="/wiki/YouTube" title="YouTube">YouTube</a></i>. June 2, 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=YouTube&rft.atitle=convolutional+neural+network+demo+from+1993+featuring+DSP32+accelerator&rft.date=2014-06-02&rft_id=https%3A%2F%2Fwww.youtube.com%2Fwatch%3Fv%3DFwFduRA_L6Q&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-wz1988-15"><span class="mw-cite-backlink">^ <a href="#cite_ref-wz1988_15-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-wz1988_15-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFZhang1988" class="citation journal cs1">Zhang, Wei (1988). "Shift-invariant pattern recognition neural network and its optical architecture". <i>Proceedings of Annual Conference of the Japan Society of Applied Physics</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Proceedings+of+Annual+Conference+of+the+Japan+Society+of+Applied+Physics&rft.atitle=Shift-invariant+pattern+recognition+neural+network+and+its+optical+architecture&rft.date=1988&rft.aulast=Zhang&rft.aufirst=Wei&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-wz1990-16"><span class="mw-cite-backlink">^ <a href="#cite_ref-wz1990_16-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-wz1990_16-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFZhang1990" class="citation journal cs1">Zhang, Wei (1990). "Parallel distributed processing model with local space-invariant interconnections and its optical architecture". <i>Applied Optics</i>. <b>29</b> (32): <span class="nowrap">4790–</span>7. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/1990ApOpt..29.4790Z">1990ApOpt..29.4790Z</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1364%2FAO.29.004790">10.1364/AO.29.004790</a>. <a href="/wiki/PMID_(identifier)" class="mw-redirect" title="PMID (identifier)">PMID</a> <a rel="nofollow" class="external text" href="https://pubmed.ncbi.nlm.nih.gov/20577468">20577468</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Applied+Optics&rft.atitle=Parallel+distributed+processing+model+with+local+space-invariant+interconnections+and+its+optical+architecture&rft.volume=29&rft.issue=32&rft.pages=%3Cspan+class%3D%22nowrap%22%3E4790-%3C%2Fspan%3E7&rft.date=1990&rft_id=info%3Apmid%2F20577468&rft_id=info%3Adoi%2F10.1364%2FAO.29.004790&rft_id=info%3Abibcode%2F1990ApOpt..29.4790Z&rft.aulast=Zhang&rft.aufirst=Wei&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-DCS_1-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-DCS_1_17-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAsanović,_K.Beck,_J.Feldman,_J.Morgan,_N.1994" class="citation journal cs1">Asanović, K.; Beck, J.; Feldman, J.; Morgan, N.; Wawrzynek, J. (January 1994). <a rel="nofollow" class="external text" href="https://www.researchgate.net/publication/15149042">"Designing a connectionist network supercomputer"</a>. <i><a href="/wiki/International_Journal_of_Neural_Systems" title="International Journal of Neural Systems">International Journal of Neural Systems</a></i>. <b>4</b> (4). ResearchGate: <span class="nowrap">317–</span>26. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1142%2FS0129065793000250">10.1142/S0129065793000250</a>. <a href="/wiki/PMID_(identifier)" class="mw-redirect" title="PMID (identifier)">PMID</a> <a rel="nofollow" class="external text" href="https://pubmed.ncbi.nlm.nih.gov/8049794">8049794</a><span class="reference-accessdate">. Retrieved <span class="nowrap">December 26,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=International+Journal+of+Neural+Systems&rft.atitle=Designing+a+connectionist+network+supercomputer&rft.volume=4&rft.issue=4&rft.pages=%3Cspan+class%3D%22nowrap%22%3E317-%3C%2Fspan%3E26&rft.date=1994-01&rft_id=info%3Adoi%2F10.1142%2FS0129065793000250&rft_id=info%3Apmid%2F8049794&rft.au=Asanovi%C4%87%2C+K.&rft.au=Beck%2C+J.&rft.au=Feldman%2C+J.&rft.au=Morgan%2C+N.&rft.au=Wawrzynek%2C+J.&rft_id=https%3A%2F%2Fwww.researchgate.net%2Fpublication%2F15149042&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-krste_general_purpose-18"><span class="mw-cite-backlink"><b><a href="#cite_ref-krste_general_purpose_18-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=VtJthbiiTBQ">"The end of general purpose computers (not)"</a>. <i><a href="/wiki/YouTube" title="YouTube">YouTube</a></i>. April 17, 2015.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=YouTube&rft.atitle=The+end+of+general+purpose+computers+%28not%29&rft.date=2015-04-17&rft_id=https%3A%2F%2Fwww.youtube.com%2Fwatch%3Fv%3DVtJthbiiTBQ&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-fpga-inference-19"><span class="mw-cite-backlink">^ <a href="#cite_ref-fpga-inference_19-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-fpga-inference_19-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGschwind,_M.Salapura,_V.Maischberger,_O.1995" class="citation web cs1">Gschwind, M.; Salapura, V.; Maischberger, O. (February 1995). <a rel="nofollow" class="external text" href="https://www.researchgate.net/publication/2318589">"Space Efficient Neural Net Implementation"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">December 26,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Space+Efficient+Neural+Net+Implementation&rft.date=1995-02&rft.au=Gschwind%2C+M.&rft.au=Salapura%2C+V.&rft.au=Maischberger%2C+O.&rft_id=https%3A%2F%2Fwww.researchgate.net%2Fpublication%2F2318589&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-fpga-training-20"><span class="mw-cite-backlink">^ <a href="#cite_ref-fpga-training_20-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-fpga-training_20-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGschwindSalapuraMaischberger1996" class="citation book cs1">Gschwind, M.; Salapura, V.; Maischberger, O. (1996). "A Generic Building Block for Hopfield Neural Networks with On-Chip Learning". <i>1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96</i>. pp. <span class="nowrap">49–</span>52. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FISCAS.1996.598474">10.1109/ISCAS.1996.598474</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-7803-3073-0" title="Special:BookSources/0-7803-3073-0"><bdi>0-7803-3073-0</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:17630664">17630664</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=A+Generic+Building+Block+for+Hopfield+Neural+Networks+with+On-Chip+Learning&rft.btitle=1996+IEEE+International+Symposium+on+Circuits+and+Systems.+Circuits+and+Systems+Connecting+the+World.+ISCAS+96&rft.pages=%3Cspan+class%3D%22nowrap%22%3E49-%3C%2Fspan%3E52&rft.date=1996&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A17630664%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FISCAS.1996.598474&rft.isbn=0-7803-3073-0&rft.aulast=Gschwind&rft.aufirst=M.&rft.au=Salapura%2C+V.&rft.au=Maischberger%2C+O.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-:1-21"><span class="mw-cite-backlink">^ <a href="#cite_ref-:1_21-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:1_21-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-:1_21-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-:1_21-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFChenDuSunWang2014" class="citation journal cs1">Chen, Tianshi; Du, Zidong; Sun, Ninghui; Wang, Jia; Wu, Chengyong; Chen, Yunji; Temam, Olivier (April 5, 2014). <a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F2654822.2541967">"DianNao"</a>. <i>ACM SIGARCH Computer Architecture News</i>. <b>42</b> (1): <span class="nowrap">269–</span>284. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F2654822.2541967">10.1145/2654822.2541967</a></span>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0163-5964">0163-5964</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=ACM+SIGARCH+Computer+Architecture+News&rft.atitle=DianNao&rft.volume=42&rft.issue=1&rft.pages=%3Cspan+class%3D%22nowrap%22%3E269-%3C%2Fspan%3E284&rft.date=2014-04-05&rft_id=info%3Adoi%2F10.1145%2F2654822.2541967&rft.issn=0163-5964&rft.aulast=Chen&rft.aufirst=Tianshi&rft.au=Du%2C+Zidong&rft.au=Sun%2C+Ninghui&rft.au=Wang%2C+Jia&rft.au=Wu%2C+Chengyong&rft.au=Chen%2C+Yunji&rft.au=Temam%2C+Olivier&rft_id=https%3A%2F%2Fdoi.org%2F10.1145%252F2654822.2541967&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-:2-22"><span class="mw-cite-backlink">^ <a href="#cite_ref-:2_22-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:2_22-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-:2_22-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFChenLuoLiuZhang2014" class="citation book cs1">Chen, Yunji; Luo, Tao; Liu, Shaoli; Zhang, Shijin; He, Liqiang; Wang, Jia; Li, Ling; Chen, Tianshi; Xu, Zhiwei; Sun, Ninghui; Temam, Olivier (December 2014). "DaDianNao: A Machine-Learning Supercomputer". <i>2014 47th Annual IEEE/ACM International Symposium on Microarchitecture</i>. IEEE. pp. <span class="nowrap">609–</span>622. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2Fmicro.2014.58">10.1109/micro.2014.58</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4799-6998-2" title="Special:BookSources/978-1-4799-6998-2"><bdi>978-1-4799-6998-2</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:6838992">6838992</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=DaDianNao%3A+A+Machine-Learning+Supercomputer&rft.btitle=2014+47th+Annual+IEEE%2FACM+International+Symposium+on+Microarchitecture&rft.pages=%3Cspan+class%3D%22nowrap%22%3E609-%3C%2Fspan%3E622&rft.pub=IEEE&rft.date=2014-12&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A6838992%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2Fmicro.2014.58&rft.isbn=978-1-4799-6998-2&rft.aulast=Chen&rft.aufirst=Yunji&rft.au=Luo%2C+Tao&rft.au=Liu%2C+Shaoli&rft.au=Zhang%2C+Shijin&rft.au=He%2C+Liqiang&rft.au=Wang%2C+Jia&rft.au=Li%2C+Ling&rft.au=Chen%2C+Tianshi&rft.au=Xu%2C+Zhiwei&rft.au=Sun%2C+Ninghui&rft.au=Temam%2C+Olivier&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-:3-23"><span class="mw-cite-backlink">^ <a href="#cite_ref-:3_23-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:3_23-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-:3_23-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDuFasthuberChenIenne2016" class="citation journal cs1">Du, Zidong; Fasthuber, Robert; Chen, Tianshi; Ienne, Paolo; Li, Ling; Luo, Tao; Feng, Xiaobing; Chen, Yunji; Temam, Olivier (January 4, 2016). "ShiDianNao". <i>ACM SIGARCH Computer Architecture News</i>. <b>43</b> (3S): <span class="nowrap">92–</span>104. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F2872887.2750389">10.1145/2872887.2750389</a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0163-5964">0163-5964</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=ACM+SIGARCH+Computer+Architecture+News&rft.atitle=ShiDianNao&rft.volume=43&rft.issue=3S&rft.pages=%3Cspan+class%3D%22nowrap%22%3E92-%3C%2Fspan%3E104&rft.date=2016-01-04&rft_id=info%3Adoi%2F10.1145%2F2872887.2750389&rft.issn=0163-5964&rft.aulast=Du&rft.aufirst=Zidong&rft.au=Fasthuber%2C+Robert&rft.au=Chen%2C+Tianshi&rft.au=Ienne%2C+Paolo&rft.au=Li%2C+Ling&rft.au=Luo%2C+Tao&rft.au=Feng%2C+Xiaobing&rft.au=Chen%2C+Yunji&rft.au=Temam%2C+Olivier&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-:4-24"><span class="mw-cite-backlink">^ <a href="#cite_ref-:4_24-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:4_24-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-:4_24-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLiuChenLiuZhou2015" class="citation journal cs1">Liu, Daofu; Chen, Tianshi; Liu, Shaoli; Zhou, Jinhong; Zhou, Shengyuan; Teman, Olivier; Feng, Xiaobing; Zhou, Xuehai; Chen, Yunji (May 29, 2015). "PuDianNao". <i>ACM SIGARCH Computer Architecture News</i>. <b>43</b> (1): <span class="nowrap">369–</span>381. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F2786763.2694358">10.1145/2786763.2694358</a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0163-5964">0163-5964</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=ACM+SIGARCH+Computer+Architecture+News&rft.atitle=PuDianNao&rft.volume=43&rft.issue=1&rft.pages=%3Cspan+class%3D%22nowrap%22%3E369-%3C%2Fspan%3E381&rft.date=2015-05-29&rft_id=info%3Adoi%2F10.1145%2F2786763.2694358&rft.issn=0163-5964&rft.aulast=Liu&rft.aufirst=Daofu&rft.au=Chen%2C+Tianshi&rft.au=Liu%2C+Shaoli&rft.au=Zhou%2C+Jinhong&rft.au=Zhou%2C+Shengyuan&rft.au=Teman%2C+Olivier&rft.au=Feng%2C+Xiaobing&rft.au=Zhou%2C+Xuehai&rft.au=Chen%2C+Yunji&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFChenChenXuSun2016" class="citation journal cs1">Chen, Yunji; Chen, Tianshi; Xu, Zhiwei; Sun, Ninghui; Temam, Olivier (October 28, 2016). "DianNao family". <i>Communications of the ACM</i>. <b>59</b> (11): <span class="nowrap">105–</span>112. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F2996864">10.1145/2996864</a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0001-0782">0001-0782</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:207243998">207243998</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Communications+of+the+ACM&rft.atitle=DianNao+family&rft.volume=59&rft.issue=11&rft.pages=%3Cspan+class%3D%22nowrap%22%3E105-%3C%2Fspan%3E112&rft.date=2016-10-28&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A207243998%23id-name%3DS2CID&rft.issn=0001-0782&rft_id=info%3Adoi%2F10.1145%2F2996864&rft.aulast=Chen&rft.aufirst=Yunji&rft.au=Chen%2C+Tianshi&rft.au=Xu%2C+Zhiwei&rft.au=Sun%2C+Ninghui&rft.au=Temam%2C+Olivier&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.qualcomm.com/news/releases/2016/05/02/qualcomm-helps-make-your-mobile-devices-smarter-new-snapdragon-machine">"Qualcomm Helps Make Your Mobile Devices Smarter With New Snapdragon Machine Learning Software Development Kit"</a>. <i>Qualcomm</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Qualcomm&rft.atitle=Qualcomm+Helps+Make+Your+Mobile+Devices+Smarter+With+New+Snapdragon+Machine+Learning+Software+Development+Kit&rft_id=https%3A%2F%2Fwww.qualcomm.com%2Fnews%2Freleases%2F2016%2F05%2F02%2Fqualcomm-helps-make-your-mobile-devices-smarter-new-snapdragon-machine&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-27"><span class="mw-cite-backlink"><b><a href="#cite_ref-27">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRubin" class="citation web cs1">Rubin, Ben Fox. <a rel="nofollow" class="external text" href="https://www.cnet.com/tech/mobile/qualcomms-zeroth-platform-could-make-your-smartphone-much-smarter/">"Qualcomm's Zeroth platform could make your smartphone much smarter"</a>. <i>CNET</i><span class="reference-accessdate">. Retrieved <span class="nowrap">September 28,</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CNET&rft.atitle=Qualcomm%27s+Zeroth+platform+could+make+your+smartphone+much+smarter&rft.aulast=Rubin&rft.aufirst=Ben+Fox&rft_id=https%3A%2F%2Fwww.cnet.com%2Ftech%2Fmobile%2Fqualcomms-zeroth-platform-could-make-your-smartphone-much-smarter%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-cell-28"><span class="mw-cite-backlink"><b><a href="#cite_ref-cell_28-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGschwindHofsteeFlachsHopkins2006" class="citation journal cs1">Gschwind, Michael; Hofstee, H. Peter; Flachs, Brian; Hopkins, Martin; Watanabe, Yukio; Yamazaki, Takeshi (2006). "Synergistic Processing in Cell's Multicore Architecture". <i>IEEE Micro</i>. <b>26</b> (2): <span class="nowrap">10–</span>24. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FMM.2006.41">10.1109/MM.2006.41</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:17834015">17834015</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Micro&rft.atitle=Synergistic+Processing+in+Cell%27s+Multicore+Architecture&rft.volume=26&rft.issue=2&rft.pages=%3Cspan+class%3D%22nowrap%22%3E10-%3C%2Fspan%3E24&rft.date=2006&rft_id=info%3Adoi%2F10.1109%2FMM.2006.41&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A17834015%23id-name%3DS2CID&rft.aulast=Gschwind&rft.aufirst=Michael&rft.au=Hofstee%2C+H.+Peter&rft.au=Flachs%2C+Brian&rft.au=Hopkins%2C+Martin&rft.au=Watanabe%2C+Yukio&rft.au=Yamazaki%2C+Takeshi&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-29"><span class="mw-cite-backlink"><b><a href="#cite_ref-29">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDe_Fabritiis2007" class="citation journal cs1">De Fabritiis, G. (2007). "Performance of Cell processor for biomolecular simulations". <i>Computer Physics Communications</i>. <b>176</b> (<span class="nowrap">11–</span>12): <span class="nowrap">660–</span>664. <a href="/wiki/ArXiv_(identifier)" class="mw-redirect" title="ArXiv (identifier)">arXiv</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://arxiv.org/abs/physics/0611201">physics/0611201</a></span>. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2007CoPhC.176..660D">2007CoPhC.176..660D</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1016%2Fj.cpc.2007.02.107">10.1016/j.cpc.2007.02.107</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:13871063">13871063</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Computer+Physics+Communications&rft.atitle=Performance+of+Cell+processor+for+biomolecular+simulations&rft.volume=176&rft.issue=%3Cspan+class%3D%22nowrap%22%3E11%E2%80%93%3C%2Fspan%3E12&rft.pages=%3Cspan+class%3D%22nowrap%22%3E660-%3C%2Fspan%3E664&rft.date=2007&rft_id=info%3Aarxiv%2Fphysics%2F0611201&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A13871063%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1016%2Fj.cpc.2007.02.107&rft_id=info%3Abibcode%2F2007CoPhC.176..660D&rft.aulast=De+Fabritiis&rft.aufirst=G.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-30"><span class="mw-cite-backlink"><b><a href="#cite_ref-30">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><i>Video Processing and Retrieval on Cell architecture</i>. <a href="/wiki/CiteSeerX_(identifier)" class="mw-redirect" title="CiteSeerX (identifier)">CiteSeerX</a> <span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.138.5133">10.1.1.138.5133</a></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Video+Processing+and+Retrieval+on+Cell+architecture&rft_id=https%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fsummary%3Fdoi%3D10.1.1.138.5133%23id-name%3DCiteSeerX&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-31">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBenthinWaldScherbaumFriedrich2006" class="citation book cs1">Benthin, Carsten; Wald, Ingo; Scherbaum, Michael; Friedrich, Heiko (2006). <i>2006 IEEE Symposium on Interactive Ray Tracing</i>. pp. <span class="nowrap">15–</span>23. <a href="/wiki/CiteSeerX_(identifier)" class="mw-redirect" title="CiteSeerX (identifier)">CiteSeerX</a> <span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.67.8982">10.1.1.67.8982</a></span>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FRT.2006.280210">10.1109/RT.2006.280210</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4244-0693-7" title="Special:BookSources/978-1-4244-0693-7"><bdi>978-1-4244-0693-7</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:1198101">1198101</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=2006+IEEE+Symposium+on+Interactive+Ray+Tracing&rft.pages=%3Cspan+class%3D%22nowrap%22%3E15-%3C%2Fspan%3E23&rft.date=2006&rft_id=https%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fsummary%3Fdoi%3D10.1.1.67.8982%23id-name%3DCiteSeerX&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A1198101%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FRT.2006.280210&rft.isbn=978-1-4244-0693-7&rft.aulast=Benthin&rft.aufirst=Carsten&rft.au=Wald%2C+Ingo&rft.au=Scherbaum%2C+Michael&rft.au=Friedrich%2C+Heiko&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-32"><span class="mw-cite-backlink"><b><a href="#cite_ref-32">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20170830041003/http://www.teco.edu/~scholz/papers/ScholzDiploma.pdf">"Development of an artificial neural network on a heterogeneous multicore architecture to predict a successful weight loss in obese individuals"</a> <span class="cs1-format">(PDF)</span>. Archived from <a rel="nofollow" class="external text" href="https://www.teco.edu/~scholz/papers/ScholzDiploma.pdf">the original</a> <span class="cs1-format">(PDF)</span> on August 30, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">November 14,</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Development+of+an+artificial+neural+network+on+a+heterogeneous+multicore+architecture+to+predict+a+successful+weight+loss+in+obese+individuals&rft_id=https%3A%2F%2Fwww.teco.edu%2F~scholz%2Fpapers%2FScholzDiploma.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-33"><span class="mw-cite-backlink"><b><a href="#cite_ref-33">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKwonChoiChungKim2008" class="citation book cs1">Kwon, Bomjun; Choi, Taiho; Chung, Heejin; Kim, Geonho (2008). <i>2008 5th IEEE Consumer Communications and Networking Conference</i>. pp. <span class="nowrap">1030–</span>1034. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2Fccnc08.2007.235">10.1109/ccnc08.2007.235</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4244-1457-4" title="Special:BookSources/978-1-4244-1457-4"><bdi>978-1-4244-1457-4</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:14429828">14429828</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=2008+5th+IEEE+Consumer+Communications+and+Networking+Conference&rft.pages=%3Cspan+class%3D%22nowrap%22%3E1030-%3C%2Fspan%3E1034&rft.date=2008&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A14429828%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2Fccnc08.2007.235&rft.isbn=978-1-4244-1457-4&rft.aulast=Kwon&rft.aufirst=Bomjun&rft.au=Choi%2C+Taiho&rft.au=Chung%2C+Heejin&rft.au=Kim%2C+Geonho&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-34"><span class="mw-cite-backlink"><b><a href="#cite_ref-34">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDuanStrey2008" class="citation book cs1">Duan, Rubing; Strey, Alfred (2008). <i>Euro-Par 2008 – Parallel Processing</i>. Lecture Notes in Computer Science. Vol. 5168. pp. <span class="nowrap">665–</span>675. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1007%2F978-3-540-85451-7_71">10.1007/978-3-540-85451-7_71</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-3-540-85450-0" title="Special:BookSources/978-3-540-85450-0"><bdi>978-3-540-85450-0</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Euro-Par+2008+%E2%80%93+Parallel+Processing&rft.series=Lecture+Notes+in+Computer+Science&rft.pages=%3Cspan+class%3D%22nowrap%22%3E665-%3C%2Fspan%3E675&rft.date=2008&rft_id=info%3Adoi%2F10.1007%2F978-3-540-85451-7_71&rft.isbn=978-3-540-85450-0&rft.aulast=Duan&rft.aufirst=Rubing&rft.au=Strey%2C+Alfred&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-35"><span class="mw-cite-backlink"><b><a href="#cite_ref-35">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://software.intel.com/content/www/us/en/develop/articles/improving-the-compute-performance-of-video-processing-software-using-avx-advanced-vector-extensions-instructions.html">"Improving the performance of video with AVX"</a>. February 8, 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Improving+the+performance+of+video+with+AVX&rft.date=2012-02-08&rft_id=https%3A%2F%2Fsoftware.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fdevelop%2Farticles%2Fimproving-the-compute-performance-of-video-processing-software-using-avx-advanced-vector-extensions-instructions.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-HPC-36"><span class="mw-cite-backlink"><b><a href="#cite_ref-HPC_36-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFChellapilla,_K.Sidd_PuriSimard,_P.2006" class="citation web cs1">Chellapilla, K.; Sidd Puri; Simard, P. (October 23, 2006). <a rel="nofollow" class="external text" href="https://inria.hal.science/inria-00112631/document">"High Performance Convolutional Neural Networks for Document Processing"</a>. 10th International Workshop on Frontiers in Handwriting Recognition<span class="reference-accessdate">. Retrieved <span class="nowrap">December 23,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=High+Performance+Convolutional+Neural+Networks+for+Document+Processing&rft.pub=10th+International+Workshop+on+Frontiers+in+Handwriting+Recognition&rft.date=2006-10-23&rft.au=Chellapilla%2C+K.&rft.au=Sidd+Puri&rft.au=Simard%2C+P.&rft_id=https%3A%2F%2Finria.hal.science%2Finria-00112631%2Fdocument&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-INC_1-37"><span class="mw-cite-backlink"><b><a href="#cite_ref-INC_1_37-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKrizhevsky,_A.Sutskever,_I.Hinton,_G.E.2017" class="citation journal cs1">Krizhevsky, A.; Sutskever, I.; Hinton, G.E. (May 24, 2017). <a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F3065386">"ImageNet Classification with Deep Convolutional Neural Networks"</a>. <i>Communications of the ACM</i>. <b>60</b> (6): <span class="nowrap">84–</span>90. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F3065386">10.1145/3065386</a></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Communications+of+the+ACM&rft.atitle=ImageNet+Classification+with+Deep+Convolutional+Neural+Networks&rft.volume=60&rft.issue=6&rft.pages=%3Cspan+class%3D%22nowrap%22%3E84-%3C%2Fspan%3E90&rft.date=2017-05-24&rft_id=info%3Adoi%2F10.1145%2F3065386&rft.au=Krizhevsky%2C+A.&rft.au=Sutskever%2C+I.&rft.au=Hinton%2C+G.E.&rft_id=https%3A%2F%2Fdoi.org%2F10.1145%252F3065386&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-38"><span class="mw-cite-backlink"><b><a href="#cite_ref-38">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKrizhevskySutskeverHinton2017" class="citation journal cs1">Krizhevsky, Alex; Sutskever, Ilya; Hinton, Geoffrey E (May 24, 2017). <a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F3065386">"ImageNet classification with deep convolutional neural networks"</a>. <i>Communications of the ACM</i>. <b>60</b> (6): <span class="nowrap">84–</span>90. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F3065386">10.1145/3065386</a></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Communications+of+the+ACM&rft.atitle=ImageNet+classification+with+deep+convolutional+neural+networks&rft.volume=60&rft.issue=6&rft.pages=%3Cspan+class%3D%22nowrap%22%3E84-%3C%2Fspan%3E90&rft.date=2017-05-24&rft_id=info%3Adoi%2F10.1145%2F3065386&rft.aulast=Krizhevsky&rft.aufirst=Alex&rft.au=Sutskever%2C+Ilya&rft.au=Hinton%2C+Geoffrey+E&rft_id=https%3A%2F%2Fdoi.org%2F10.1145%252F3065386&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-ND_1-39"><span class="mw-cite-backlink"><b><a href="#cite_ref-ND_1_39-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRoe,_R.2023" class="citation web cs1">Roe, R. (May 17, 2023). <a rel="nofollow" class="external text" href="https://insidehpc.com/2016/05/nvidia-driving-the-development-of-deep-learning">"Nvidia in the Driver's Seat for Deep Learning"</a>. insideHPC<span class="reference-accessdate">. Retrieved <span class="nowrap">December 23,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Nvidia+in+the+Driver%27s+Seat+for+Deep+Learning&rft.pub=insideHPC&rft.date=2023-05-17&rft.au=Roe%2C+R.&rft_id=https%3A%2F%2Finsidehpc.com%2F2016%2F05%2Fnvidia-driving-the-development-of-deep-learning&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-NIS_1-40"><span class="mw-cite-backlink"><b><a href="#cite_ref-NIS_1_40-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBohn,_D.2016" class="citation web cs1">Bohn, D. (January 5, 2016). <a rel="nofollow" class="external text" href="https://www.theverge.com/2016/1/4/10712634/nvidia-drive-px2-self-driving-car-supercomputer-announces-ces-2016">"Nvidia announces 'supercomputer' for self-driving cars at CES 2016"</a>. Vox Media<span class="reference-accessdate">. Retrieved <span class="nowrap">December 23,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Nvidia+announces+%27supercomputer%27+for+self-driving+cars+at+CES+2016&rft.pub=Vox+Media&rft.date=2016-01-05&rft.au=Bohn%2C+D.&rft_id=https%3A%2F%2Fwww.theverge.com%2F2016%2F1%2F4%2F10712634%2Fnvidia-drive-px2-self-driving-car-supercomputer-announces-ces-2016&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-41"><span class="mw-cite-backlink"><b><a href="#cite_ref-41">^</a></b></span> <span class="reference-text">"<a rel="nofollow" class="external text" href="https://www.researchgate.net/publication/329802520_A_Survey_on_Optimized_Implementation_of_Deep_Learning_Models_on_the_NVIDIA_Jetson_Platform">A Survey on Optimized Implementation of Deep Learning Models on the NVIDIA Jetson Platform</a>", 2019</span> </li> <li id="cite_note-CUDA9-42"><span class="mw-cite-backlink">^ <a href="#cite_ref-CUDA9_42-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-CUDA9_42-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHarris2017" class="citation web cs1">Harris, Mark (May 11, 2017). <a rel="nofollow" class="external text" href="https://developer.nvidia.com/blog/cuda-9-features-revealed/">"CUDA 9 Features Revealed: Volta, Cooperative Groups and More"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">August 12,</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=CUDA+9+Features+Revealed%3A+Volta%2C+Cooperative+Groups+and+More&rft.date=2017-05-11&rft.aulast=Harris&rft.aufirst=Mark&rft_id=https%3A%2F%2Fdeveloper.nvidia.com%2Fblog%2Fcuda-9-features-revealed%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-SOR_1-43"><span class="mw-cite-backlink"><b><a href="#cite_ref-SOR_1_43-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.olcf.ornl.gov/olcf-resources/compute-systems/summit">"Summit: Oak Ridge National Laboratory's 200 petaflop supercomputer"</a>. <a href="/wiki/United_States_Department_of_Energy" title="United States Department of Energy">United States Department of Energy</a>. 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">January 8,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Summit%3A+Oak+Ridge+National+Laboratory%27s+200+petaflop+supercomputer&rft.pub=United+States+Department+of+Energy&rft.date=2024&rft_id=https%3A%2F%2Fwww.olcf.ornl.gov%2Folcf-resources%2Fcompute-systems%2Fsummit&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-44"><span class="mw-cite-backlink"><b><a href="#cite_ref-44">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSefatAslanKellingtonQasem2019" class="citation book cs1">Sefat, Md Syadus; Aslan, Semih; Kellington, Jeffrey W; Qasem, Apan (August 2019). <a rel="nofollow" class="external text" href="https://ieeexplore.ieee.org/document/8855410">"Accelerating HotSpots in Deep Neural Networks on a CAPI-Based FPGA"</a>. <i>2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)</i>. pp. <span class="nowrap">248–</span>256. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FHPCC%2FSmartCity%2FDSS.2019.00048">10.1109/HPCC/SmartCity/DSS.2019.00048</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-7281-2058-4" title="Special:BookSources/978-1-7281-2058-4"><bdi>978-1-7281-2058-4</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:203656070">203656070</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Accelerating+HotSpots+in+Deep+Neural+Networks+on+a+CAPI-Based+FPGA&rft.btitle=2019+IEEE+21st+International+Conference+on+High+Performance+Computing+and+Communications%3B+IEEE+17th+International+Conference+on+Smart+City%3B+IEEE+5th+International+Conference+on+Data+Science+and+Systems+%28HPCC%2FSmartCity%2FDSS%29&rft.pages=%3Cspan+class%3D%22nowrap%22%3E248-%3C%2Fspan%3E256&rft.date=2019-08&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A203656070%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FHPCC%2FSmartCity%2FDSS.2019.00048&rft.isbn=978-1-7281-2058-4&rft.aulast=Sefat&rft.aufirst=Md+Syadus&rft.au=Aslan%2C+Semih&rft.au=Kellington%2C+Jeffrey+W&rft.au=Qasem%2C+Apan&rft_id=https%3A%2F%2Fieeexplore.ieee.org%2Fdocument%2F8855410&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-45"><span class="mw-cite-backlink"><b><a href="#cite_ref-45">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.nextplatform.com/2016/08/23/fpga-based-deep-learning-accelerators-take-asics/">"FPGA Based Deep Learning Accelerators Take on ASICs"</a>. <i>The Next Platform</i>. August 23, 2016<span class="reference-accessdate">. Retrieved <span class="nowrap">September 7,</span> 2016</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Next+Platform&rft.atitle=FPGA+Based+Deep+Learning+Accelerators+Take+on+ASICs&rft.date=2016-08-23&rft_id=http%3A%2F%2Fwww.nextplatform.com%2F2016%2F08%2F23%2Ffpga-based-deep-learning-accelerators-take-asics%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-46"><span class="mw-cite-backlink"><b><a href="#cite_ref-46">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.microsoft.com/en-us/research/blog/microsoft-unveils-project-brainwave/">"Microsoft unveils Project Brainwave for real-time AI"</a>. <i><a href="/wiki/Microsoft" title="Microsoft">Microsoft</a></i>. August 22, 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Microsoft&rft.atitle=Microsoft+unveils+Project+Brainwave+for+real-time+AI&rft.date=2017-08-22&rft_id=https%3A%2F%2Fwww.microsoft.com%2Fen-us%2Fresearch%2Fblog%2Fmicrosoft-unveils-project-brainwave%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-47"><span class="mw-cite-backlink"><b><a href="#cite_ref-47">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://techreport.com/news/30155/google-boosts-machine-learning-with-its-tensor-processing-unit/">"Google boosts machine learning with its Tensor Processing Unit"</a>. May 19, 2016<span class="reference-accessdate">. Retrieved <span class="nowrap">September 13,</span> 2016</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Google+boosts+machine+learning+with+its+Tensor+Processing+Unit&rft.date=2016-05-19&rft_id=https%3A%2F%2Ftechreport.com%2Fnews%2F30155%2Fgoogle-boosts-machine-learning-with-its-tensor-processing-unit%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-48"><span class="mw-cite-backlink"><b><a href="#cite_ref-48">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.sciencedaily.com/releases/2016/02/160203134840.htm">"Chip could bring deep learning to mobile devices"</a>. <i>www.sciencedaily.com</i>. February 3, 2016<span class="reference-accessdate">. Retrieved <span class="nowrap">September 13,</span> 2016</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.sciencedaily.com&rft.atitle=Chip+could+bring+deep+learning+to+mobile+devices&rft.date=2016-02-03&rft_id=https%3A%2F%2Fwww.sciencedaily.com%2Freleases%2F2016%2F02%2F160203134840.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-49"><span class="mw-cite-backlink"><b><a href="#cite_ref-49">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://techcrunch.com/2023/08/29/google-cloud-announces-the-5th-generation-of-its-custom-tpus/">"Google Cloud announces the 5th generation of its custom TPUs"</a>. August 29, 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Google+Cloud+announces+the+5th+generation+of+its+custom+TPUs&rft.date=2023-08-29&rft_id=https%3A%2F%2Ftechcrunch.com%2F2023%2F08%2F29%2Fgoogle-cloud-announces-the-5th-generation-of-its-custom-tpus%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-lowprecision-50"><span class="mw-cite-backlink"><b><a href="#cite_ref-lowprecision_50-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://proceedings.mlr.press/v37/gupta15.pdf">"Deep Learning with Limited Numerical Precision"</a> <span class="cs1-format">(PDF)</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Deep+Learning+with+Limited+Numerical+Precision&rft_id=http%3A%2F%2Fproceedings.mlr.press%2Fv37%2Fgupta15.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-51"><span class="mw-cite-backlink"><b><a href="#cite_ref-51">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRastegariOrdonezRedmonFarhadi2016" class="citation arxiv cs1">Rastegari, Mohammad; Ordonez, Vicente; Redmon, Joseph; Farhadi, Ali (2016). "XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks". <a href="/wiki/ArXiv_(identifier)" class="mw-redirect" title="ArXiv (identifier)">arXiv</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://arxiv.org/abs/1603.05279">1603.05279</a></span> [<a rel="nofollow" class="external text" href="https://arxiv.org/archive/cs.CV">cs.CV</a>].</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=preprint&rft.jtitle=arXiv&rft.atitle=XNOR-Net%3A+ImageNet+Classification+Using+Binary+Convolutional+Neural+Networks&rft.date=2016&rft_id=info%3Aarxiv%2F1603.05279&rft.aulast=Rastegari&rft.aufirst=Mohammad&rft.au=Ordonez%2C+Vicente&rft.au=Redmon%2C+Joseph&rft.au=Farhadi%2C+Ali&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-toms_Inte-52"><span class="mw-cite-backlink"><b><a href="#cite_ref-toms_Inte_52-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLucian_Armasu2018" class="citation web cs1">Lucian Armasu (May 23, 2018). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/intel-neural-network-processor-lake-crest,37105.html">"Intel To Launch Spring Crest, Its First Neural Network Processor, In 2019"</a>. <i>Tom's Hardware</i><span class="reference-accessdate">. Retrieved <span class="nowrap">May 23,</span> 2018</span>. <q>Intel said that the NNP-L1000 would also support bfloat16, a numerical format that's being adopted by all the ML industry players for neural networks. The company will also support bfloat16 in its FPGAs, Xeons, and other ML products. The Nervana NNP-L1000 is scheduled for release in 2019.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=Intel+To+Launch+Spring+Crest%2C+Its+First+Neural+Network+Processor%2C+In+2019&rft.date=2018-05-23&rft.au=Lucian+Armasu&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Fintel-neural-network-processor-lake-crest%2C37105.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-arxiv_1711.10604-53"><span class="mw-cite-backlink"><b><a href="#cite_ref-arxiv_1711.10604_53-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJoshua_V._DillonIan_LangmoreDustin_TranEugene_Brevdo2017" class="citation report cs1">Joshua V. Dillon; Ian Langmore; Dustin Tran; Eugene Brevdo; Srinivas Vasudevan; Dave Moore; Brian Patton; Alex Alemi; Matt Hoffman; Rif A. Saurous (November 28, 2017). TensorFlow Distributions (Report). <a href="/wiki/ArXiv_(identifier)" class="mw-redirect" title="ArXiv (identifier)">arXiv</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://arxiv.org/abs/1711.10604">1711.10604</a></span>. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2017arXiv171110604D">2017arXiv171110604D</a>. Accessed May 23, 2018. <q>All operations in TensorFlow Distributions are numerically stable across half, single, and double floating-point precisions (as TensorFlow dtypes: tf.bfloat16 (truncated floating point), tf.float16, tf.float32, tf.float64). Class constructors have a validate_args flag for numerical asserts</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=report&rft.btitle=TensorFlow+Distributions&rft.date=2017-11-28&rft_id=info%3Aarxiv%2F1711.10604&rft_id=info%3Abibcode%2F2017arXiv171110604D&rft.au=Joshua+V.+Dillon&rft.au=Ian+Langmore&rft.au=Dustin+Tran&rft.au=Eugene+Brevdo&rft.au=Srinivas+Vasudevan&rft.au=Dave+Moore&rft.au=Brian+Patton&rft.au=Alex+Alemi&rft.au=Matt+Hoffman&rft.au=Rif+A.+Saurous&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-54"><span class="mw-cite-backlink"><b><a href="#cite_ref-54">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWoodie2021" class="citation web cs1">Woodie, Alex (November 1, 2021). <a rel="nofollow" class="external text" href="https://www.datanami.com/2021/11/01/cerebras-hits-the-accelerator-for-deep-learning-workloads/">"Cerebras Hits the Accelerator for Deep Learning Workloads"</a>. <i>Datanami</i><span class="reference-accessdate">. Retrieved <span class="nowrap">August 3,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Datanami&rft.atitle=Cerebras+Hits+the+Accelerator+for+Deep+Learning+Workloads&rft.date=2021-11-01&rft.aulast=Woodie&rft.aufirst=Alex&rft_id=https%3A%2F%2Fwww.datanami.com%2F2021%2F11%2F01%2Fcerebras-hits-the-accelerator-for-deep-learning-workloads%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-55"><span class="mw-cite-backlink"><b><a href="#cite_ref-55">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://venturebeat.com/2021/04/20/cerebras-systems-launches-new-ai-supercomputing-processor-with-2-6-trillion-transistors/">"Cerebras launches new AI supercomputing processor with 2.6 trillion transistors"</a>. <i>VentureBeat</i>. April 20, 2021<span class="reference-accessdate">. Retrieved <span class="nowrap">August 3,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=VentureBeat&rft.atitle=Cerebras+launches+new+AI+supercomputing+processor+with+2.6+trillion+transistors&rft.date=2021-04-20&rft_id=https%3A%2F%2Fventurebeat.com%2F2021%2F04%2F20%2Fcerebras-systems-launches-new-ai-supercomputing-processor-with-2-6-trillion-transistors%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-56"><span class="mw-cite-backlink"><b><a href="#cite_ref-56">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://awsdocs-neuron.readthedocs-hosted.com/en/latest/general/arch/neuron-hardware/neuroncores-arch.html">"AWS NeuronCore Architecture"</a>. <i>readthedocs-hosted</i>. December 27, 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">December 27,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=readthedocs-hosted&rft.atitle=AWS+NeuronCore+Architecture&rft.date=2024-12-27&rft_id=https%3A%2F%2Fawsdocs-neuron.readthedocs-hosted.com%2Fen%2Flatest%2Fgeneral%2Farch%2Fneuron-hardware%2Fneuroncores-arch.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-57"><span class="mw-cite-backlink"><b><a href="#cite_ref-57">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAbu_SebastianTomas_TumaNikolaos_PapandreouManuel_Le_Gallo2017" class="citation journal cs1">Abu Sebastian; Tomas Tuma; Nikolaos Papandreou; Manuel Le Gallo; Lukas Kull; Thomas Parnell; Evangelos Eleftheriou (2017). <a rel="nofollow" class="external text" href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5653661">"Temporal correlation detection using computational phase-change memory"</a>. <i>Nature Communications</i>. <b>8</b> (1): 1115. <a href="/wiki/ArXiv_(identifier)" class="mw-redirect" title="ArXiv (identifier)">arXiv</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://arxiv.org/abs/1706.00511">1706.00511</a></span>. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2017NatCo...8.1115S">2017NatCo...8.1115S</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1038%2Fs41467-017-01481-9">10.1038/s41467-017-01481-9</a>. <a href="/wiki/PMC_(identifier)" class="mw-redirect" title="PMC (identifier)">PMC</a> <span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5653661">5653661</a></span>. <a href="/wiki/PMID_(identifier)" class="mw-redirect" title="PMID (identifier)">PMID</a> <a rel="nofollow" class="external text" href="https://pubmed.ncbi.nlm.nih.gov/29062022">29062022</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Nature+Communications&rft.atitle=Temporal+correlation+detection+using+computational+phase-change+memory&rft.volume=8&rft.issue=1&rft.pages=1115&rft.date=2017&rft_id=https%3A%2F%2Fwww.ncbi.nlm.nih.gov%2Fpmc%2Farticles%2FPMC5653661%23id-name%3DPMC&rft_id=info%3Abibcode%2F2017NatCo...8.1115S&rft_id=info%3Aarxiv%2F1706.00511&rft_id=info%3Apmid%2F29062022&rft_id=info%3Adoi%2F10.1038%2Fs41467-017-01481-9&rft.au=Abu+Sebastian&rft.au=Tomas+Tuma&rft.au=Nikolaos+Papandreou&rft.au=Manuel+Le+Gallo&rft.au=Lukas+Kull&rft.au=Thomas+Parnell&rft.au=Evangelos+Eleftheriou&rft_id=https%3A%2F%2Fwww.ncbi.nlm.nih.gov%2Fpmc%2Farticles%2FPMC5653661&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-58"><span class="mw-cite-backlink"><b><a href="#cite_ref-58">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://phys.org/news/2018-10-brain-inspired-architecture-advance-ai.html">"A new brain-inspired architecture could improve how computers handle data and advance AI"</a>. <i>American Institute of Physics</i>. October 3, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">October 5,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=American+Institute+of+Physics&rft.atitle=A+new+brain-inspired+architecture+could+improve+how+computers+handle+data+and+advance+AI&rft.date=2018-10-03&rft_id=https%3A%2F%2Fphys.org%2Fnews%2F2018-10-brain-inspired-architecture-advance-ai.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-59"><span class="mw-cite-backlink"><b><a href="#cite_ref-59">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCarlos_RíosNathan_YoungbloodZengguang_ChengManuel_Le_Gallo2018" class="citation journal cs1">Carlos Ríos; Nathan Youngblood; Zengguang Cheng; Manuel Le Gallo; Wolfram H.P. Pernice; C. David Wright; Abu Sebastian; Harish Bhaskaran (2018). <a rel="nofollow" class="external text" href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6377270">"In-memory computing on a photonic platform"</a>. <i>Science Advances</i>. <b>5</b> (2): eaau5759. <a href="/wiki/ArXiv_(identifier)" class="mw-redirect" title="ArXiv (identifier)">arXiv</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://arxiv.org/abs/1801.06228">1801.06228</a></span>. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2019SciA....5.5759R">2019SciA....5.5759R</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1126%2Fsciadv.aau5759">10.1126/sciadv.aau5759</a>. <a href="/wiki/PMC_(identifier)" class="mw-redirect" title="PMC (identifier)">PMC</a> <span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6377270">6377270</a></span>. <a href="/wiki/PMID_(identifier)" class="mw-redirect" title="PMID (identifier)">PMID</a> <a rel="nofollow" class="external text" href="https://pubmed.ncbi.nlm.nih.gov/30793028">30793028</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:7637801">7637801</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Science+Advances&rft.atitle=In-memory+computing+on+a+photonic+platform&rft.volume=5&rft.issue=2&rft.pages=eaau5759&rft.date=2018&rft_id=https%3A%2F%2Fwww.ncbi.nlm.nih.gov%2Fpmc%2Farticles%2FPMC6377270%23id-name%3DPMC&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A7637801%23id-name%3DS2CID&rft_id=info%3Abibcode%2F2019SciA....5.5759R&rft_id=info%3Aarxiv%2F1801.06228&rft_id=info%3Apmid%2F30793028&rft_id=info%3Adoi%2F10.1126%2Fsciadv.aau5759&rft.au=Carlos+R%C3%ADos&rft.au=Nathan+Youngblood&rft.au=Zengguang+Cheng&rft.au=Manuel+Le+Gallo&rft.au=Wolfram+H.P.+Pernice&rft.au=C.+David+Wright&rft.au=Abu+Sebastian&rft.au=Harish+Bhaskaran&rft_id=https%3A%2F%2Fwww.ncbi.nlm.nih.gov%2Fpmc%2Farticles%2FPMC6377270&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-60"><span class="mw-cite-backlink"><b><a href="#cite_ref-60">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFZhong_SunGiacomo_PedrettiElia_AmbrosiAlessandro_Bricalli2019" class="citation journal cs1">Zhong Sun; Giacomo Pedretti; Elia Ambrosi; Alessandro Bricalli; Wei Wang; Daniele Ielmini (2019). <a rel="nofollow" class="external text" href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6410822">"Solving matrix equations in one step with cross-point resistive arrays"</a>. <i>Proceedings of the National Academy of Sciences</i>. <b>116</b> (10): <span class="nowrap">4123–</span>4128. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2019PNAS..116.4123S">2019PNAS..116.4123S</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://doi.org/10.1073%2Fpnas.1815682116">10.1073/pnas.1815682116</a></span>. <a href="/wiki/PMC_(identifier)" class="mw-redirect" title="PMC (identifier)">PMC</a> <span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6410822">6410822</a></span>. <a href="/wiki/PMID_(identifier)" class="mw-redirect" title="PMID (identifier)">PMID</a> <a rel="nofollow" class="external text" href="https://pubmed.ncbi.nlm.nih.gov/30782810">30782810</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Proceedings+of+the+National+Academy+of+Sciences&rft.atitle=Solving+matrix+equations+in+one+step+with+cross-point+resistive+arrays&rft.volume=116&rft.issue=10&rft.pages=%3Cspan+class%3D%22nowrap%22%3E4123-%3C%2Fspan%3E4128&rft.date=2019&rft_id=https%3A%2F%2Fwww.ncbi.nlm.nih.gov%2Fpmc%2Farticles%2FPMC6410822%23id-name%3DPMC&rft_id=info%3Apmid%2F30782810&rft_id=info%3Adoi%2F10.1073%2Fpnas.1815682116&rft_id=info%3Abibcode%2F2019PNAS..116.4123S&rft.au=Zhong+Sun&rft.au=Giacomo+Pedretti&rft.au=Elia+Ambrosi&rft.au=Alessandro+Bricalli&rft.au=Wei+Wang&rft.au=Daniele+Ielmini&rft_id=https%3A%2F%2Fwww.ncbi.nlm.nih.gov%2Fpmc%2Farticles%2FPMC6410822&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-atomthin-61"><span class="mw-cite-backlink">^ <a href="#cite_ref-atomthin_61-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-atomthin_61-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMaregaZhaoAvsarWang2020" class="citation journal cs1">Marega, Guilherme Migliato; Zhao, Yanfei; Avsar, Ahmet; Wang, Zhenyu; Tripati, Mukesh; Radenovic, Aleksandra; Kis, Anras (2020). <a rel="nofollow" class="external text" href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7116757">"Logic-in-memory based on an atomically thin semiconductor"</a>. <i>Nature</i>. <b>587</b> (2): <span class="nowrap">72–</span>77. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2020Natur.587...72M">2020Natur.587...72M</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1038%2Fs41586-020-2861-0">10.1038/s41586-020-2861-0</a>. <a href="/wiki/PMC_(identifier)" class="mw-redirect" title="PMC (identifier)">PMC</a> <span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7116757">7116757</a></span>. <a href="/wiki/PMID_(identifier)" class="mw-redirect" title="PMID (identifier)">PMID</a> <a rel="nofollow" class="external text" href="https://pubmed.ncbi.nlm.nih.gov/33149289">33149289</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Nature&rft.atitle=Logic-in-memory+based+on+an+atomically+thin+semiconductor&rft.volume=587&rft.issue=2&rft.pages=%3Cspan+class%3D%22nowrap%22%3E72-%3C%2Fspan%3E77&rft.date=2020&rft_id=https%3A%2F%2Fwww.ncbi.nlm.nih.gov%2Fpmc%2Farticles%2FPMC7116757%23id-name%3DPMC&rft_id=info%3Apmid%2F33149289&rft_id=info%3Adoi%2F10.1038%2Fs41586-020-2861-0&rft_id=info%3Abibcode%2F2020Natur.587...72M&rft.aulast=Marega&rft.aufirst=Guilherme+Migliato&rft.au=Zhao%2C+Yanfei&rft.au=Avsar%2C+Ahmet&rft.au=Wang%2C+Zhenyu&rft.au=Tripati%2C+Mukesh&rft.au=Radenovic%2C+Aleksandra&rft.au=Kis%2C+Anras&rft_id=https%3A%2F%2Fwww.ncbi.nlm.nih.gov%2Fpmc%2Farticles%2FPMC7116757&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-photonic-62"><span class="mw-cite-backlink">^ <a href="#cite_ref-photonic_62-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-photonic_62-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-photonic_62-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFFeldmannYoungbloodKarpovGehring2021" class="citation journal cs1">Feldmann, J.; Youngblood, N.; Karpov, M.; et al. (2021). "Parallel convolutional processing using an integrated photonic tensor". <i>Nature</i>. <b>589</b> (2): <span class="nowrap">52–</span>58. <a href="/wiki/ArXiv_(identifier)" class="mw-redirect" title="ArXiv (identifier)">arXiv</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://arxiv.org/abs/2002.00281">2002.00281</a></span>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1038%2Fs41586-020-03070-1">10.1038/s41586-020-03070-1</a>. <a href="/wiki/PMID_(identifier)" class="mw-redirect" title="PMID (identifier)">PMID</a> <a rel="nofollow" class="external text" href="https://pubmed.ncbi.nlm.nih.gov/33408373">33408373</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:211010976">211010976</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Nature&rft.atitle=Parallel+convolutional+processing+using+an+integrated+photonic+tensor&rft.volume=589&rft.issue=2&rft.pages=%3Cspan+class%3D%22nowrap%22%3E52-%3C%2Fspan%3E58&rft.date=2021&rft_id=info%3Aarxiv%2F2002.00281&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A211010976%23id-name%3DS2CID&rft_id=info%3Apmid%2F33408373&rft_id=info%3Adoi%2F10.1038%2Fs41586-020-03070-1&rft.aulast=Feldmann&rft.aufirst=J.&rft.au=Youngblood%2C+N.&rft.au=Karpov%2C+M.&rft.au=Gehring%2C+H.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-63"><span class="mw-cite-backlink"><b><a href="#cite_ref-63">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://spectrum.ieee.org/backpropagation-optical-ai">"Photonic Chips Curb AI Training's Energy Appetite - IEEE Spectrum"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Photonic+Chips+Curb+AI+Training%27s+Energy+Appetite+-+IEEE+Spectrum&rft_id=https%3A%2F%2Fspectrum.ieee.org%2Fbackpropagation-optical-ai&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-64"><span class="mw-cite-backlink"><b><a href="#cite_ref-64">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160227145622/http://www.nvidia.com/object/IO_20020111_5424.html">"NVIDIA launches the World's First Graphics Processing Unit, the GeForce 256"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.nvidia.com/object/IO_20020111_5424.html">the original</a> on February 27, 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=NVIDIA+launches+the+World%27s+First+Graphics+Processing+Unit%2C+the+GeForce+256&rft_id=http%3A%2F%2Fwww.nvidia.com%2Fobject%2FIO_20020111_5424.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-65"><span class="mw-cite-backlink"><b><a href="#cite_ref-65">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.pcmag.com/news/intel-to-bring-a-vpu-processor-unit-to-14th-gen-meteor-lake-chips">"Intel to Bring a 'VPU' Processor Unit to 14th Gen Meteor Lake Chips"</a>. <i>PCMAG</i>. August 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=PCMAG&rft.atitle=Intel+to+Bring+a+%27VPU%27+Processor+Unit+to+14th+Gen+Meteor+Lake+Chips&rft.date=2022-08&rft_id=https%3A%2F%2Fwww.pcmag.com%2Fnews%2Fintel-to-bring-a-vpu-processor-unit-to-14th-gen-meteor-lake-chips&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-:5-66"><span class="mw-cite-backlink">^ <a href="#cite_ref-:5_66-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:5_66-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-:5_66-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFChenEmerSze2017" class="citation journal cs1">Chen, Yu-Hsin; Emer, Joel; <a href="/wiki/Vivienne_Sze" title="Vivienne Sze">Sze, Vivienne</a> (2017). "Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks". <i>IEEE Micro</i>: 1. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2Fmm.2017.265085944">10.1109/mm.2017.265085944</a>. <a href="/wiki/Hdl_(identifier)" class="mw-redirect" title="Hdl (identifier)">hdl</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://hdl.handle.net/1721.1%2F102369">1721.1/102369</a></span>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0272-1732">0272-1732</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Micro&rft.atitle=Eyeriss%3A+A+Spatial+Architecture+for+Energy-Efficient+Dataflow+for+Convolutional+Neural+Networks&rft.pages=1&rft.date=2017&rft_id=info%3Ahdl%2F1721.1%2F102369&rft.issn=0272-1732&rft_id=info%3Adoi%2F10.1109%2Fmm.2017.265085944&rft.aulast=Chen&rft.aufirst=Yu-Hsin&rft.au=Emer%2C+Joel&rft.au=Sze%2C+Vivienne&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-:6-67"><span class="mw-cite-backlink">^ <a href="#cite_ref-:6_67-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:6_67-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHanLiuMaoPu2016" class="citation book cs1">Han, Song; Liu, Xingyu; Mao, Huizi; Pu, Jing; Pedram, Ardavan; Horowitz, Mark A.; Dally, William J. (February 3, 2016). <i>EIE: Efficient Inference Engine on Compressed Deep Neural Network</i>. <a href="/wiki/OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/oclc/1106232247">1106232247</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=EIE%3A+Efficient+Inference+Engine+on+Compressed+Deep+Neural+Network&rft.date=2016-02-03&rft_id=info%3Aoclcnum%2F1106232247&rft.aulast=Han&rft.aufirst=Song&rft.au=Liu%2C+Xingyu&rft.au=Mao%2C+Huizi&rft.au=Pu%2C+Jing&rft.au=Pedram%2C+Ardavan&rft.au=Horowitz%2C+Mark+A.&rft.au=Dally%2C+William+J.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-68"><span class="mw-cite-backlink"><b><a href="#cite_ref-68">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFReagenWhatmoughAdolfRama2016" class="citation book cs1">Reagen, Brandon; Whatmough, Paul; Adolf, Robert; Rama, Saketh; Lee, Hyunkwang; Lee, Sae Kyu; Hernandez-Lobato, Jose Miguel; Wei, Gu-Yeon; Brooks, David (June 2016). "Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators". <i>2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)</i>. Seoul: IEEE. pp. <span class="nowrap">267–</span>278. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FISCA.2016.32">10.1109/ISCA.2016.32</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4673-8947-1" title="Special:BookSources/978-1-4673-8947-1"><bdi>978-1-4673-8947-1</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Minerva%3A+Enabling+Low-Power%2C+Highly-Accurate+Deep+Neural+Network+Accelerators&rft.btitle=2016+ACM%2FIEEE+43rd+Annual+International+Symposium+on+Computer+Architecture+%28ISCA%29&rft.place=Seoul&rft.pages=%3Cspan+class%3D%22nowrap%22%3E267-%3C%2Fspan%3E278&rft.pub=IEEE&rft.date=2016-06&rft_id=info%3Adoi%2F10.1109%2FISCA.2016.32&rft.isbn=978-1-4673-8947-1&rft.aulast=Reagen&rft.aufirst=Brandon&rft.au=Whatmough%2C+Paul&rft.au=Adolf%2C+Robert&rft.au=Rama%2C+Saketh&rft.au=Lee%2C+Hyunkwang&rft.au=Lee%2C+Sae+Kyu&rft.au=Hernandez-Lobato%2C+Jose+Miguel&rft.au=Wei%2C+Gu-Yeon&rft.au=Brooks%2C+David&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-69"><span class="mw-cite-backlink"><b><a href="#cite_ref-69">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJuddAlbericioMoshovos2017" class="citation journal cs1">Judd, Patrick; Albericio, Jorge; Moshovos, Andreas (January 1, 2017). "Stripes: Bit-Serial Deep Neural Network Computing". <i>IEEE Computer Architecture Letters</i>. <b>16</b> (1): <span class="nowrap">80–</span>83. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2Flca.2016.2597140">10.1109/lca.2016.2597140</a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/1556-6056">1556-6056</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:3784424">3784424</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Computer+Architecture+Letters&rft.atitle=Stripes%3A+Bit-Serial+Deep+Neural+Network+Computing&rft.volume=16&rft.issue=1&rft.pages=%3Cspan+class%3D%22nowrap%22%3E80-%3C%2Fspan%3E83&rft.date=2017-01-01&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A3784424%23id-name%3DS2CID&rft.issn=1556-6056&rft_id=info%3Adoi%2F10.1109%2Flca.2016.2597140&rft.aulast=Judd&rft.aufirst=Patrick&rft.au=Albericio%2C+Jorge&rft.au=Moshovos%2C+Andreas&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-:0-70"><span class="mw-cite-backlink">^ <a href="#cite_ref-:0_70-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:0_70-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-:0_70-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJouppi,_N.Young,_C.Patil,_N.Patterson,_D.2017" class="citation book cs1">Jouppi, N.; Young, C.; Patil, N.; Patterson, D. (June 24, 2017). <i>In-Datacenter Performance Analysis of a Tensor Processing Unit</i>. <a href="/wiki/Association_for_Computing_Machinery" title="Association for Computing Machinery">Association for Computing Machinery</a>. pp. <span class="nowrap">1–</span>12. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F3079856.3080246">10.1145/3079856.3080246</a></span>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9781450348928" title="Special:BookSources/9781450348928"><bdi>9781450348928</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:4202768">4202768</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=In-Datacenter+Performance+Analysis+of+a+Tensor+Processing+Unit&rft.pages=%3Cspan+class%3D%22nowrap%22%3E1-%3C%2Fspan%3E12&rft.pub=Association+for+Computing+Machinery&rft.date=2017-06-24&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A4202768%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1145%2F3079856.3080246&rft.isbn=9781450348928&rft.au=Jouppi%2C+N.&rft.au=Young%2C+C.&rft.au=Patil%2C+N.&rft.au=Patterson%2C+D.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-71"><span class="mw-cite-backlink"><b><a href="#cite_ref-71">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1 cs1-prop-foreign-lang-source"><a rel="nofollow" class="external text" href="https://www.cambricon.com/index.php?m=content&c=index&a=lists&catid=21">"MLU 100 intelligence accelerator card"</a> (in Japanese). Cambricon. 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">January 8,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=MLU+100+intelligence+accelerator+card&rft.pub=Cambricon&rft.date=2024&rft_id=https%3A%2F%2Fwww.cambricon.com%2Findex.php%3Fm%3Dcontent%26c%3Dindex%26a%3Dlists%26catid%3D21&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-:7-72"><span class="mw-cite-backlink">^ <a href="#cite_ref-:7_72-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:7_72-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFChiLiXuZhang2016" class="citation book cs1">Chi, Ping; Li, Shuangchen; Xu, Cong; Zhang, Tao; Zhao, Jishen; Liu, Yongpan; Wang, Yu; Xie, Yuan (June 2016). "PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory". <i>2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)</i>. IEEE. pp. <span class="nowrap">27–</span>39. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2Fisca.2016.13">10.1109/isca.2016.13</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4673-8947-1" title="Special:BookSources/978-1-4673-8947-1"><bdi>978-1-4673-8947-1</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=PRIME%3A+A+Novel+Processing-in-Memory+Architecture+for+Neural+Network+Computation+in+ReRAM-Based+Main+Memory&rft.btitle=2016+ACM%2FIEEE+43rd+Annual+International+Symposium+on+Computer+Architecture+%28ISCA%29&rft.pages=%3Cspan+class%3D%22nowrap%22%3E27-%3C%2Fspan%3E39&rft.pub=IEEE&rft.date=2016-06&rft_id=info%3Adoi%2F10.1109%2Fisca.2016.13&rft.isbn=978-1-4673-8947-1&rft.aulast=Chi&rft.aufirst=Ping&rft.au=Li%2C+Shuangchen&rft.au=Xu%2C+Cong&rft.au=Zhang%2C+Tao&rft.au=Zhao%2C+Jishen&rft.au=Liu%2C+Yongpan&rft.au=Wang%2C+Yu&rft.au=Xie%2C+Yuan&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-:8-73"><span class="mw-cite-backlink">^ <a href="#cite_ref-:8_73-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:8_73-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-:8_73-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSongQianLiChen2017" class="citation book cs1">Song, Linghao; Qian, Xuehai; <a href="/wiki/Hai_Li" title="Hai Li">Li, Hai</a>; Chen, Yiran (February 2017). "PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning". <i>2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)</i>. IEEE. pp. <span class="nowrap">541–</span>552. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2Fhpca.2017.55">10.1109/hpca.2017.55</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-5090-4985-1" title="Special:BookSources/978-1-5090-4985-1"><bdi>978-1-5090-4985-1</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:15281419">15281419</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=PipeLayer%3A+A+Pipelined+ReRAM-Based+Accelerator+for+Deep+Learning&rft.btitle=2017+IEEE+International+Symposium+on+High+Performance+Computer+Architecture+%28HPCA%29&rft.pages=%3Cspan+class%3D%22nowrap%22%3E541-%3C%2Fspan%3E552&rft.pub=IEEE&rft.date=2017-02&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A15281419%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2Fhpca.2017.55&rft.isbn=978-1-5090-4985-1&rft.aulast=Song&rft.aufirst=Linghao&rft.au=Qian%2C+Xuehai&rft.au=Li%2C+Hai&rft.au=Chen%2C+Yiran&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-74"><span class="mw-cite-backlink"><b><a href="#cite_ref-74">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShinLeeLeeYoo2017" class="citation book cs1">Shin, Dongjoo; Lee, Jinmook; Lee, Jinsu; Yoo, Hoi-Jun (2017). <a rel="nofollow" class="external text" href="https://ieeexplore.ieee.org/document/7870350">"14.2 DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks"</a>. <i>2017 IEEE International Solid-State Circuits Conference (ISSCC)</i>. pp. <span class="nowrap">240–</span>241. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FISSCC.2017.7870350">10.1109/ISSCC.2017.7870350</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-5090-3758-2" title="Special:BookSources/978-1-5090-3758-2"><bdi>978-1-5090-3758-2</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:206998709">206998709</a><span class="reference-accessdate">. Retrieved <span class="nowrap">August 24,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=14.2+DNPU%3A+An+8.1TOPS%2FW+reconfigurable+CNN-RNN+processor+for+general-purpose+deep+neural+networks&rft.btitle=2017+IEEE+International+Solid-State+Circuits+Conference+%28ISSCC%29&rft.pages=%3Cspan+class%3D%22nowrap%22%3E240-%3C%2Fspan%3E241&rft.date=2017&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A206998709%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FISSCC.2017.7870350&rft.isbn=978-1-5090-3758-2&rft.aulast=Shin&rft.aufirst=Dongjoo&rft.au=Lee%2C+Jinmook&rft.au=Lee%2C+Jinsu&rft.au=Yoo%2C+Hoi-Jun&rft_id=https%3A%2F%2Fieeexplore.ieee.org%2Fdocument%2F7870350&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-75"><span class="mw-cite-backlink"><b><a href="#cite_ref-75">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLeeKimKangShin2018" class="citation book cs1">Lee, Jinmook; Kim, Changhyeon; Kang, Sanghoon; Shin, Dongjoo; Kim, Sangyeob; Yoo, Hoi-Jun (2018). <a rel="nofollow" class="external text" href="https://ieeexplore.ieee.org/document/8310262">"UNPU: A 50.6TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision"</a>. <i>2018 IEEE International Solid - State Circuits Conference - (ISSCC)</i>. pp. <span class="nowrap">218–</span>220. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FISSCC.2018.8310262">10.1109/ISSCC.2018.8310262</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-5090-4940-0" title="Special:BookSources/978-1-5090-4940-0"><bdi>978-1-5090-4940-0</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:3861747">3861747</a><span class="reference-accessdate">. Retrieved <span class="nowrap">November 30,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=UNPU%3A+A+50.6TOPS%2FW+unified+deep+neural+network+accelerator+with+1b-to-16b+fully-variable+weight+bit-precision&rft.btitle=2018+IEEE+International+Solid+-+State+Circuits+Conference+-+%28ISSCC%29&rft.pages=%3Cspan+class%3D%22nowrap%22%3E218-%3C%2Fspan%3E220&rft.date=2018&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A3861747%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FISSCC.2018.8310262&rft.isbn=978-1-5090-4940-0&rft.aulast=Lee&rft.aufirst=Jinmook&rft.au=Kim%2C+Changhyeon&rft.au=Kang%2C+Sanghoon&rft.au=Shin%2C+Dongjoo&rft.au=Kim%2C+Sangyeob&rft.au=Yoo%2C+Hoi-Jun&rft_id=https%3A%2F%2Fieeexplore.ieee.org%2Fdocument%2F8310262&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-76"><span class="mw-cite-backlink"><b><a href="#cite_ref-76">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLiuDuTaoHan2016" class="citation book cs1">Liu, Shaoli; Du, Zidong; Tao, Jinhua; Han, Dong; Luo, Tao; Xie, Yuan; Chen, Yunji; Chen, Tianshi (June 2016). "Cambricon: An Instruction Set Architecture for Neural Networks". <i>2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)</i>. IEEE. pp. <span class="nowrap">393–</span>405. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2Fisca.2016.42">10.1109/isca.2016.42</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4673-8947-1" title="Special:BookSources/978-1-4673-8947-1"><bdi>978-1-4673-8947-1</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Cambricon%3A+An+Instruction+Set+Architecture+for+Neural+Networks&rft.btitle=2016+ACM%2FIEEE+43rd+Annual+International+Symposium+on+Computer+Architecture+%28ISCA%29&rft.pages=%3Cspan+class%3D%22nowrap%22%3E393-%3C%2Fspan%3E405&rft.pub=IEEE&rft.date=2016-06&rft_id=info%3Adoi%2F10.1109%2Fisca.2016.42&rft.isbn=978-1-4673-8947-1&rft.aulast=Liu&rft.aufirst=Shaoli&rft.au=Du%2C+Zidong&rft.au=Tao%2C+Jinhua&rft.au=Han%2C+Dong&rft.au=Luo%2C+Tao&rft.au=Xie%2C+Yuan&rft.au=Chen%2C+Yunji&rft.au=Chen%2C+Tianshi&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-:9-77"><span class="mw-cite-backlink">^ <a href="#cite_ref-:9_77-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:9_77-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAmbrogioNarayananTsaiShelby2018" class="citation journal cs1">Ambrogio, Stefano; Narayanan, Pritish; Tsai, Hsinyu; Shelby, Robert M.; Boybat, Irem; di Nolfo, Carmelo; Sidler, Severin; Giordano, Massimo; Bodini, Martina; Farinha, Nathan C. P.; Killeen, Benjamin (June 2018). "Equivalent-accuracy accelerated neural-network training using analogue memory". <i>Nature</i>. <b>558</b> (7708): <span class="nowrap">60–</span>67. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2018Natur.558...60A">2018Natur.558...60A</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1038%2Fs41586-018-0180-5">10.1038/s41586-018-0180-5</a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0028-0836">0028-0836</a>. <a href="/wiki/PMID_(identifier)" class="mw-redirect" title="PMID (identifier)">PMID</a> <a rel="nofollow" class="external text" href="https://pubmed.ncbi.nlm.nih.gov/29875487">29875487</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:46956938">46956938</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Nature&rft.atitle=Equivalent-accuracy+accelerated+neural-network+training+using+analogue+memory&rft.volume=558&rft.issue=7708&rft.pages=%3Cspan+class%3D%22nowrap%22%3E60-%3C%2Fspan%3E67&rft.date=2018-06&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A46956938%23id-name%3DS2CID&rft_id=info%3Abibcode%2F2018Natur.558...60A&rft.issn=0028-0836&rft_id=info%3Adoi%2F10.1038%2Fs41586-018-0180-5&rft_id=info%3Apmid%2F29875487&rft.aulast=Ambrogio&rft.aufirst=Stefano&rft.au=Narayanan%2C+Pritish&rft.au=Tsai%2C+Hsinyu&rft.au=Shelby%2C+Robert+M.&rft.au=Boybat%2C+Irem&rft.au=di+Nolfo%2C+Carmelo&rft.au=Sidler%2C+Severin&rft.au=Giordano%2C+Massimo&rft.au=Bodini%2C+Martina&rft.au=Farinha%2C+Nathan+C.+P.&rft.au=Killeen%2C+Benjamin&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-78"><span class="mw-cite-backlink"><b><a href="#cite_ref-78">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFChenLinLaiLi2017" class="citation book cs1">Chen, Wei-Hao; Lin, Wen-Jang; Lai, Li-Ya; Li, Shuangchen; Hsu, Chien-Hua; Lin, Huan-Ting; Lee, Heng-Yuan; Su, Jian-Wei; Xie, Yuan; Sheu, Shyh-Shyuan; Chang, Meng-Fan (December 2017). "A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme". <i>2017 IEEE International Electron Devices Meeting (IEDM)</i>. IEEE. pp. 28.2.1–28.2.4. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2Fiedm.2017.8268468">10.1109/iedm.2017.8268468</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-5386-3559-9" title="Special:BookSources/978-1-5386-3559-9"><bdi>978-1-5386-3559-9</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:19556846">19556846</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=A+16Mb+dual-mode+ReRAM+macro+with+sub-14ns+computing-in-memory+and+memory+functions+enabled+by+self-write+termination+scheme&rft.btitle=2017+IEEE+International+Electron+Devices+Meeting+%28IEDM%29&rft.pages=28.2.1-28.2.4&rft.pub=IEEE&rft.date=2017-12&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A19556846%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2Fiedm.2017.8268468&rft.isbn=978-1-5386-3559-9&rft.aulast=Chen&rft.aufirst=Wei-Hao&rft.au=Lin%2C+Wen-Jang&rft.au=Lai%2C+Li-Ya&rft.au=Li%2C+Shuangchen&rft.au=Hsu%2C+Chien-Hua&rft.au=Lin%2C+Huan-Ting&rft.au=Lee%2C+Heng-Yuan&rft.au=Su%2C+Jian-Wei&rft.au=Xie%2C+Yuan&rft.au=Sheu%2C+Shyh-Shyuan&rft.au=Chang%2C+Meng-Fan&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-79"><span class="mw-cite-backlink"><b><a href="#cite_ref-79">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFYangStrukovStewart2013" class="citation journal cs1">Yang, J. Joshua; Strukov, Dmitri B.; Stewart, Duncan R. (January 2013). <a rel="nofollow" class="external text" href="https://www.nature.com/articles/nnano.2012.240">"Memristive devices for computing"</a>. <i>Nature Nanotechnology</i>. <b>8</b> (1): <span class="nowrap">13–</span>24. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2013NatNa...8...13Y">2013NatNa...8...13Y</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1038%2Fnnano.2012.240">10.1038/nnano.2012.240</a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/1748-3395">1748-3395</a>. <a href="/wiki/PMID_(identifier)" class="mw-redirect" title="PMID (identifier)">PMID</a> <a rel="nofollow" class="external text" href="https://pubmed.ncbi.nlm.nih.gov/23269430">23269430</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Nature+Nanotechnology&rft.atitle=Memristive+devices+for+computing&rft.volume=8&rft.issue=1&rft.pages=%3Cspan+class%3D%22nowrap%22%3E13-%3C%2Fspan%3E24&rft.date=2013-01&rft_id=info%3Adoi%2F10.1038%2Fnnano.2012.240&rft.issn=1748-3395&rft_id=info%3Apmid%2F23269430&rft_id=info%3Abibcode%2F2013NatNa...8...13Y&rft.aulast=Yang&rft.aufirst=J.+Joshua&rft.au=Strukov%2C+Dmitri+B.&rft.au=Stewart%2C+Duncan+R.&rft_id=https%3A%2F%2Fwww.nature.com%2Farticles%2Fnnano.2012.240&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-80"><span class="mw-cite-backlink"><b><a href="#cite_ref-80">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShafieeNagMuralimanoharBalasubramonian2016" class="citation journal cs1">Shafiee, Ali; Nag, Anirban; Muralimanohar, Naveen; Balasubramonian, Rajeev; Strachan, John Paul; Hu, Miao; Williams, R. Stanley; Srikumar, Vivek (October 12, 2016). "ISAAC". <i>ACM SIGARCH Computer Architecture News</i>. <b>44</b> (3): <span class="nowrap">14–</span>26. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F3007787.3001139">10.1145/3007787.3001139</a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0163-5964">0163-5964</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:6329628">6329628</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=ACM+SIGARCH+Computer+Architecture+News&rft.atitle=ISAAC&rft.volume=44&rft.issue=3&rft.pages=%3Cspan+class%3D%22nowrap%22%3E14-%3C%2Fspan%3E26&rft.date=2016-10-12&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A6329628%23id-name%3DS2CID&rft.issn=0163-5964&rft_id=info%3Adoi%2F10.1145%2F3007787.3001139&rft.aulast=Shafiee&rft.aufirst=Ali&rft.au=Nag%2C+Anirban&rft.au=Muralimanohar%2C+Naveen&rft.au=Balasubramonian%2C+Rajeev&rft.au=Strachan%2C+John+Paul&rft.au=Hu%2C+Miao&rft.au=Williams%2C+R.+Stanley&rft.au=Srikumar%2C+Vivek&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-81"><span class="mw-cite-backlink"><b><a href="#cite_ref-81">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJi,_Yu_Zhang,_Youyang_Xie,_Xinfeng_Li,_Shuangchen_Wang,_Peiqi_Hu,_Xing_Zhang,_Youhui_Xie,_Yuan2019" class="citation book cs1">Ji, Yu Zhang, Youyang Xie, Xinfeng Li, Shuangchen Wang, Peiqi Hu, Xing Zhang, Youhui Xie, Yuan (January 27, 2019). <i>FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture</i>. <a href="/wiki/OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/oclc/1106329050">1106329050</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=FPSA%3A+A+Full+System+Stack+Solution+for+Reconfigurable+ReRAM-based+NN+Accelerator+Architecture&rft.date=2019-01-27&rft_id=info%3Aoclcnum%2F1106329050&rft.au=Ji%2C+Yu+Zhang%2C+Youyang+Xie%2C+Xinfeng+Li%2C+Shuangchen+Wang%2C+Peiqi+Hu%2C+Xing+Zhang%2C+Youhui+Xie%2C+Yuan&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_book" title="Template:Cite book">cite book</a>}}</code>: CS1 maint: multiple names: authors list (<a href="/wiki/Category:CS1_maint:_multiple_names:_authors_list" title="Category:CS1 maint: multiple names: authors list">link</a>)</span></span> </li> <li id="cite_note-82"><span class="mw-cite-backlink"><b><a href="#cite_ref-82">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFNandakumarBoybatJoshiPiveteau2019" class="citation book cs1">Nandakumar, S. R.; Boybat, Irem; Joshi, Vinay; Piveteau, Christophe; Le Gallo, Manuel; Rajendran, Bipin; Sebastian, Abu; Eleftheriou, Evangelos (November 2019). "Phase-Change Memory Models for Deep Learning Training and Inference". <i>2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)</i>. IEEE. pp. <span class="nowrap">727–</span>730. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2Ficecs46596.2019.8964852">10.1109/icecs46596.2019.8964852</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-7281-0996-1" title="Special:BookSources/978-1-7281-0996-1"><bdi>978-1-7281-0996-1</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:210930121">210930121</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Phase-Change+Memory+Models+for+Deep+Learning+Training+and+Inference&rft.btitle=2019+26th+IEEE+International+Conference+on+Electronics%2C+Circuits+and+Systems+%28ICECS%29&rft.pages=%3Cspan+class%3D%22nowrap%22%3E727-%3C%2Fspan%3E730&rft.pub=IEEE&rft.date=2019-11&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A210930121%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2Ficecs46596.2019.8964852&rft.isbn=978-1-7281-0996-1&rft.aulast=Nandakumar&rft.aufirst=S.+R.&rft.au=Boybat%2C+Irem&rft.au=Joshi%2C+Vinay&rft.au=Piveteau%2C+Christophe&rft.au=Le+Gallo%2C+Manuel&rft.au=Rajendran%2C+Bipin&rft.au=Sebastian%2C+Abu&rft.au=Eleftheriou%2C+Evangelos&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-83"><span class="mw-cite-backlink"><b><a href="#cite_ref-83">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJoshiLe_GalloHaefeliBoybat2020" class="citation journal cs1">Joshi, Vinay; Le Gallo, Manuel; Haefeli, Simon; Boybat, Irem; Nandakumar, S. R.; Piveteau, Christophe; Dazzi, Martino; Rajendran, Bipin; Sebastian, Abu; Eleftheriou, Evangelos (May 18, 2020). <a rel="nofollow" class="external text" href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7235046">"Accurate deep neural network inference using computational phase-change memory"</a>. <i>Nature Communications</i>. <b>11</b> (1): 2473. <a href="/wiki/ArXiv_(identifier)" class="mw-redirect" title="ArXiv (identifier)">arXiv</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://arxiv.org/abs/1906.03138">1906.03138</a></span>. <a href="/wiki/Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2020NatCo..11.2473J">2020NatCo..11.2473J</a>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://doi.org/10.1038%2Fs41467-020-16108-9">10.1038/s41467-020-16108-9</a></span>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/2041-1723">2041-1723</a>. <a href="/wiki/PMC_(identifier)" class="mw-redirect" title="PMC (identifier)">PMC</a> <span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7235046">7235046</a></span>. <a href="/wiki/PMID_(identifier)" class="mw-redirect" title="PMID (identifier)">PMID</a> <a rel="nofollow" class="external text" href="https://pubmed.ncbi.nlm.nih.gov/32424184">32424184</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Nature+Communications&rft.atitle=Accurate+deep+neural+network+inference+using+computational+phase-change+memory&rft.volume=11&rft.issue=1&rft.pages=2473&rft.date=2020-05-18&rft_id=https%3A%2F%2Fwww.ncbi.nlm.nih.gov%2Fpmc%2Farticles%2FPMC7235046%23id-name%3DPMC&rft_id=info%3Abibcode%2F2020NatCo..11.2473J&rft_id=info%3Aarxiv%2F1906.03138&rft.issn=2041-1723&rft_id=info%3Adoi%2F10.1038%2Fs41467-020-16108-9&rft_id=info%3Apmid%2F32424184&rft.aulast=Joshi&rft.aufirst=Vinay&rft.au=Le+Gallo%2C+Manuel&rft.au=Haefeli%2C+Simon&rft.au=Boybat%2C+Irem&rft.au=Nandakumar%2C+S.+R.&rft.au=Piveteau%2C+Christophe&rft.au=Dazzi%2C+Martino&rft.au=Rajendran%2C+Bipin&rft.au=Sebastian%2C+Abu&rft.au=Eleftheriou%2C+Evangelos&rft_id=https%3A%2F%2Fwww.ncbi.nlm.nih.gov%2Fpmc%2Farticles%2FPMC7235046&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-84"><span class="mw-cite-backlink"><b><a href="#cite_ref-84">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.theregister.com/2022/09/09/nvidia_hopper_mlperf/">"Nvidia claims 'record performance' for Hopper MLPerf debut"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Nvidia+claims+%27record+performance%27+for+Hopper+MLPerf+debut&rft_id=https%3A%2F%2Fwww.theregister.com%2F2022%2F09%2F09%2Fnvidia_hopper_mlperf%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ANeural+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-85"><span class="mw-cite-backlink"><b><a href="#cite_ref-85">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20100623062608/http://www.abe.ufl.edu/wlee/Publications/ICAME96.pdf">"Development of a machine vision system for weed control using precision chemical application"</a> <span class="cs1-format">(PDF)</span>. <i>University of Florida</i>. <a href="/wiki/CiteSeerX_(identifier)" class="mw-redirect" title="CiteSeerX (identifier)">CiteSeerX</a> <span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.7.342">10.1.1.7.342</a></span>. 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title="Cryptographic accelerator">Cryptography</a> <ul><li><a href="/wiki/TLS_acceleration" title="TLS acceleration">TLS</a></li></ul></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Machine vision</a></li> <li><a href="/wiki/Custom_hardware_attack" title="Custom hardware attack">Custom hardware attack</a> <ul><li><a href="/wiki/Scrypt" title="Scrypt">scrypt</a></li></ul></li> <li><a href="/wiki/Network_processor" title="Network processor">Networking</a></li> <li><a href="/wiki/Data_processing_unit" title="Data processing unit">Data</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Implementations</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a> <ul><li><a href="/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li></ul></li> <li><a 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architecture">Transport triggered</a></li> <li><a href="/wiki/Multicore" class="mw-redirect" title="Multicore">Multicore</a></li> <li><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous</a></li> <li><a href="/wiki/In-memory_processing" title="In-memory processing">In-memory computing</a></li> <li><a href="/wiki/Systolic_array" title="Systolic array">Systolic array</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Programmable_logic" class="mw-redirect" title="Programmable logic">Programmable logic</a></li> <li><a href="/wiki/Processor_(computing)" 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