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GitHub - stnolting/neorv32: :desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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6.2525 5.55125C6.2525 5.55125 7.17375 5.2625 9.2775 6.67875C10.1575 6.43125 11.0925 6.3075 12.0275 6.3075C12.9625 6.3075 13.8975 6.43125 14.7775 6.67875C16.8813 5.24875 17.8025 5.55125 17.8025 5.55125C18.4075 7.06375 18.0225 8.19125 17.9125 8.46625C18.6138 9.23625 19.04 10.2125 19.04 11.4225C19.04 15.6437 16.4688 16.5787 14.0213 16.8537C14.42 17.1975 14.7638 17.8575 14.7638 18.8887C14.7638 20.36 14.75 21.5425 14.75 21.9137C14.75 22.2025 14.9563 22.5462 15.5063 22.4362C19.8513 20.9787 23 16.8537 23 12C23 5.9225 18.0775 1 12 1Z"></path> </svg> </a> <div class="flex-1 flex-order-2 text-right"> <a href="/login?return_to=https%3A%2F%2Fgithub.com%2Fstnolting%2Fneorv32" class="HeaderMenu-link HeaderMenu-button d-inline-flex d-lg-none flex-order-1 f5 no-underline border color-border-default rounded-2 px-2 py-1 color-fg-inherit js-prevent-focus-on-mobile-nav" data-hydro-click="{"event_type":"authentication.click","payload":{"location_in_page":"site header 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class="color-fg-default h4">GitHub Copilot</div> Write better code with AI </div> </a></li> <li> <a class="HeaderMenu-dropdown-link d-block no-underline position-relative py-2 Link--secondary d-flex flex-items-center Link--has-description pb-lg-3" data-analytics-event="{"location":"navbar","action":"github_advanced_security","context":"product","tag":"link","label":"github_advanced_security_link_product_navbar"}" href="https://github.com/security/advanced-security"> <svg aria-hidden="true" height="24" viewBox="0 0 24 24" version="1.1" width="24" data-view-component="true" class="octicon octicon-shield-check color-fg-subtle mr-3"> <path d="M16.53 9.78a.75.75 0 0 0-1.06-1.06L11 13.19l-1.97-1.97a.75.75 0 0 0-1.06 1.06l2.5 2.5a.75.75 0 0 0 1.06 0l5-5Z"></path><path d="m12.54.637 8.25 2.675A1.75 1.75 0 0 1 22 4.976V10c0 6.19-3.771 10.704-9.401 12.83a1.704 1.704 0 0 1-1.198 0C5.77 20.705 2 16.19 2 10V4.976c0-.758.489-1.43 1.21-1.664L11.46.637a1.748 1.748 0 0 1 1.08 0Zm-.617 1.426-8.25 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2.7 2.908 2.7a.75.75 0 1 1-1.02 1.1l-3.5-3.25a.75.75 0 0 1 0-1.1l3.5-3.25a.75.75 0 0 1 1.06.04Zm3.44 1.06a.75.75 0 1 1 1.02-1.1l3.5 3.25a.75.75 0 0 1 0 1.1l-3.5 3.25a.75.75 0 1 1-1.02-1.1l2.908-2.7-2.908-2.7Z"></path><path d="M1.5 4.25c0-.966.784-1.75 1.75-1.75h17.5c.966 0 1.75.784 1.75 1.75v12.5a1.75 1.75 0 0 1-1.75 1.75h-9.69l-3.573 3.573A1.458 1.458 0 0 1 5 21.043V18.5H3.25a1.75 1.75 0 0 1-1.75-1.75ZM3.25 4a.25.25 0 0 0-.25.25v12.5c0 .138.112.25.25.25h2.5a.75.75 0 0 1 .75.75v3.19l3.72-3.72a.749.749 0 0 1 .53-.22h10a.25.25 0 0 0 .25-.25V4.25a.25.25 0 0 0-.25-.25Z"></path> </svg> <div> <div class="color-fg-default h4">Code Review</div> Manage code changes </div> </a></li> <li> <a class="HeaderMenu-dropdown-link d-block no-underline position-relative py-2 Link--secondary d-flex flex-items-center Link--has-description pb-lg-3" data-analytics-event="{"location":"navbar","action":"discussions","context":"product","tag":"link","label":"discussions_link_product_navbar"}" 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src=\"/stnolting/neorv32/raw/main/docs/figures/neorv32_logo_riscv.png\" alt=\"NEORV32\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/p\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch1 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003eThe NEORV32 RISC-V Processor\u003c/h1\u003e\u003ca id=\"user-content-the-neorv32-risc-v-processor\" class=\"anchor\" aria-label=\"Permalink: The NEORV32 RISC-V Processor\" href=\"#the-neorv32-risc-v-processor\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 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href=\"#2-features\"\u003eFeatures\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"#3-fpga-implementation-results\"\u003eFPGA Implementation Results\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"#4-performance\"\u003ePerformance\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"#5-getting-started\"\u003e\u003cstrong\u003eGetting Started\u003c/strong\u003e\u003c/a\u003e 🚀\u003c/li\u003e\n\u003c/ol\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch2 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003e1. Overview\u003c/h2\u003e\u003ca id=\"user-content-1-overview\" class=\"anchor\" aria-label=\"Permalink: 1. Overview\" href=\"#1-overview\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cp dir=\"auto\"\u003e\u003ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"/stnolting/neorv32/blob/main/docs/figures/neorv32_processor.png\"\u003e\u003cimg src=\"/stnolting/neorv32/raw/main/docs/figures/neorv32_processor.png\" alt=\"neorv32 Overview\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/p\u003e\n\u003cp dir=\"auto\"\u003eThe NEORV32 Processor is a \u003cstrong\u003ecustomizable microcontroller-like system on chip (SoC)\u003c/strong\u003e built around the NEORV32\n\u003ca href=\"https://riscv.org/\" rel=\"nofollow\"\u003eRISC-V\u003c/a\u003e CPU that is written in \u003cstrong\u003eplatform-independent VHDL\u003c/strong\u003e. The processor is intended as auxiliary\ncontroller in larger SoC designs or as tiny and customized microcontroller that even fits into a\nLattice iCE40 UltraPlus low-power \u0026amp; low-density FPGA. The project is intended to work \u003cem\u003eout of the box\u003c/em\u003e and targets\nFPGA / RISC-V beginners as well as advanced users.\u003c/p\u003e\n\u003cp dir=\"auto\"\u003eSpecial focus is paid on \u003cstrong\u003eexecution safety\u003c/strong\u003e to provide defined and predictable behavior at any time.\nFor example, the CPU ensures \u003cem\u003eall\u003c/em\u003e memory accesses are properly acknowledged and \u003cem\u003eall\u003c/em\u003e invalid/malformed\ninstructions are always detected as such. Whenever an unexpected state occurs the application software is\ninformed via \u003cem\u003eprecise\u003c/em\u003e and resumable hardware exceptions.\u003c/p\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003e♻️ Looking for an \u003cstrong\u003eall-Verilog\u003c/strong\u003e version? Have a look at \u003ca href=\"https://github.com/stnolting/neorv32-verilog\"\u003eneorv32-verilog\u003c/a\u003e.\u003c/li\u003e\n\u003cli\u003e✔️ \u003ca href=\"#project-status\"\u003eContinuous integration\u003c/a\u003e to check for regressions (including RISC-V ISA compatibility check using \u003cstrong\u003eRISCOF\u003c/strong\u003e).\u003c/li\u003e\n\u003cli\u003e📂 \u003ca href=\"https://github.com/stnolting/neorv32-setups\"\u003eExemplary setups\u003c/a\u003e and\n\u003ca href=\"https://github.com/stnolting/neorv32-setups/blob/main/README.md#Community-Projects\"\u003ecommunity projects\u003c/a\u003e\ntargeting various FPGA boards and toolchains to get started.\u003c/li\u003e\n\u003cli\u003e📦 The entire processor is also available as \u003ca href=\"https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block\" rel=\"nofollow\"\u003eVivado IP Block\u003c/a\u003e.\u003c/li\u003e\n\u003cli\u003e🪁 Support for \u003ca href=\"https://github.com/stnolting/neorv32-freertos\"\u003eFreeRTOS\u003c/a\u003e,\n\u003ca href=\"https://docs.zephyrproject.org/latest/boards/others/neorv32/doc/index.html\" rel=\"nofollow\"\u003eZephyr OS\u003c/a\u003e and\n\u003ca href=\"https://github.com/enjoy-digital/litex/wiki/CPUs#risc-v---neorv32\"\u003eLiteX\u003c/a\u003e SoC Builder Framework.\u003c/li\u003e\n\u003cli\u003e🖥️ Pre-configured \u003ca href=\"https://stnolting.github.io/neorv32/ug/#_eclipse_ide\" rel=\"nofollow\"\u003eEclipse project\u003c/a\u003e for developing and debugging code using an IDE.\u003c/li\u003e\n\u003cli\u003e🏷️ The project's change log is available in \u003ca href=\"https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md\"\u003eCHANGELOG.md\u003c/a\u003e.\u003c/li\u003e\n\u003cli\u003e🚀 Check out the \u003ca href=\"#5-getting-started\"\u003equick links below\u003c/a\u003e and the\n\u003ca href=\"https://stnolting.github.io/neorv32/ug/\" rel=\"nofollow\"\u003eUser Guide\u003c/a\u003e to get started setting up \u003cem\u003eyour\u003c/em\u003e NEORV32 processor!\u003c/li\u003e\n\u003cli\u003e📚 For detailed information see the \u003ca href=\"https://stnolting.github.io/neorv32/\" rel=\"nofollow\"\u003eNEORV32 online documentation\u003c/a\u003e.\u003c/li\u003e\n\u003cli\u003e\u003cg-emoji class=\"g-emoji\" alias=\"interrobang\"\u003e⁉️\u003c/g-emoji\u003e Want to know more? Check out the \u003ca href=\"https://stnolting.github.io/neorv32/#_rationale\" rel=\"nofollow\"\u003eproject's rationale\u003c/a\u003e.\u003c/li\u003e\n\u003cli\u003e📋 File an \u003ca href=\"https://github.com/stnolting/neorv32/issues\"\u003eissue\u003c/a\u003e/\u003ca href=\"https://github.com/stnolting/neorv32/discussions\"\u003ediscussion\u003c/a\u003e/\n\u003ca href=\"https://github.com/stnolting/neorv32/pulls\"\u003ePR\u003c/a\u003e for questions, comments, ideas, feedback or if something isn't working as expected.\u003c/li\u003e\n\u003cli\u003e🤝 Find out how to \u003ca href=\"https://github.com/stnolting/neorv32/blob/main/CONTRIBUTING.md\"\u003econtribute\u003c/a\u003e.\u003c/li\u003e\n\u003c/ul\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch3 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003eKey Features\u003c/h3\u003e\u003ca id=\"user-content-key-features\" class=\"anchor\" aria-label=\"Permalink: Key Features\" href=\"#key-features\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cul class=\"contains-task-list\"\u003e\n\u003cli class=\"task-list-item\"\u003e\u003cinput type=\"checkbox\" id=\"\" disabled=\"\" class=\"task-list-item-checkbox\" checked=\"\"\u003e all-in-one package: \u003cstrong\u003eCPU\u003c/strong\u003e + \u003cstrong\u003eSoC\u003c/strong\u003e + \u003cstrong\u003eSoftware Framework\u003c/strong\u003e + \u003cstrong\u003eTooling\u003c/strong\u003e\u003c/li\u003e\n\u003cli class=\"task-list-item\"\u003e\u003cinput type=\"checkbox\" id=\"\" disabled=\"\" class=\"task-list-item-checkbox\" checked=\"\"\u003e completely described in behavioral, platform-independent VHDL - \u003cstrong\u003eno\u003c/strong\u003e platform-specific primitives, macros, attributes, etc.; an all-Verilog \"version\" is also \u003ca href=\"https://github.com/stnolting/neorv32-verilog\"\u003eavailable\u003c/a\u003e\u003c/li\u003e\n\u003cli class=\"task-list-item\"\u003e\u003cinput type=\"checkbox\" id=\"\" disabled=\"\" class=\"task-list-item-checkbox\" checked=\"\"\u003e extensive configuration options for adapting the processor to the requirements of the application (on CPU, processor and system level)\u003c/li\u003e\n\u003cli class=\"task-list-item\"\u003e\u003cinput type=\"checkbox\" id=\"\" disabled=\"\" class=\"task-list-item-checkbox\" checked=\"\"\u003e aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off\u003c/li\u003e\n\u003cli class=\"task-list-item\"\u003e\u003cinput type=\"checkbox\" id=\"\" disabled=\"\" class=\"task-list-item-checkbox\" checked=\"\"\u003e FPGA friendly (e.g. \u003cem\u003eall\u003c/em\u003e internal memories can be mapped to block RAM - including the CPU's register file)\u003c/li\u003e\n\u003cli class=\"task-list-item\"\u003e\u003cinput type=\"checkbox\" id=\"\" disabled=\"\" class=\"task-list-item-checkbox\" checked=\"\"\u003e optimized for high clock frequencies to ease integration / timing closure\u003c/li\u003e\n\u003cli class=\"task-list-item\"\u003e\u003cinput type=\"checkbox\" id=\"\" disabled=\"\" class=\"task-list-item-checkbox\" checked=\"\"\u003e from zero to \u003cem\u003e\"hello world!\"\u003c/em\u003e - completely open source and documented (on software and hardware side)\u003c/li\u003e\n\u003cli class=\"task-list-item\"\u003e\u003cinput type=\"checkbox\" id=\"\" disabled=\"\" class=\"task-list-item-checkbox\" checked=\"\"\u003e easy to use even for digital logic / FPGA / RISC-V newcomers – intended to work \u003cem\u003eout of the box\u003c/em\u003e\u003c/li\u003e\n\u003c/ul\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch3 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003eProject Status\u003c/h3\u003e\u003ca id=\"user-content-project-status\" class=\"anchor\" aria-label=\"Permalink: Project Status\" href=\"#project-status\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cp dir=\"auto\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32/releases\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/30dfe29f1ffd6bd303c1bc5861743785a9333baa166f3341ae7521bdf544706a/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f762f72656c656173652f73746e6f6c74696e672f6e656f727633323f6c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6f676f3d476974487562\" alt=\"release\" data-canonical-src=\"https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true\u0026amp;style=flat-square\u0026amp;logo=GitHub\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\n\u003ca href=\"https://github.com/stnolting/neorv32/activity\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/d2b7f39be440167bb30f662816079f3d0d9b519c0228843b315b87f81a5d66ae/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f636f6d6d6974732d73696e63652f73746e6f6c74696e672f6e656f727633322f6c61746573743f6c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6f676f3d476974487562\" alt=\"commits-since-latest-release\" data-canonical-src=\"https://img.shields.io/github/commits-since/stnolting/neorv32/latest?longCache=true\u0026amp;style=flat-square\u0026amp;logo=GitHub\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/p\u003e\n\u003cmarkdown-accessiblity-table\u003e\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth align=\"left\"\u003eTask / Subproject\u003c/th\u003e\n\u003cth align=\"left\"\u003eRepository\u003c/th\u003e\n\u003cth align=\"left\"\u003eCI Status\u003c/th\u003e\n\u003c/tr\u003e\n\u003c/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003eGitHub pages (docs)\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32\"\u003eneorv32\u003c/a\u003e\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://stnolting.github.io/neorv32\" rel=\"nofollow\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/c971a0b2b322db0ef7d3ee1a3f4e109e0b759899d43173dc66fceba849c49ff4/68747470733a2f2f696d672e736869656c64732e696f2f776562736974652e7376673f6c6162656c3d73746e6f6c74696e672e6769746875622e696f2532466e656f72763332266c6f6e6743616368653d74727565267374796c653d666c61742d7371756172652675726c3d6874747025334125324625324673746e6f6c74696e672e6769746875622e696f2532466e656f72763332253246696e6465782e68746d6c266c6f676f3d476974487562\" alt=\"GitHub Pages\" data-canonical-src=\"https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32\u0026amp;longCache=true\u0026amp;style=flat-square\u0026amp;url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html\u0026amp;logo=GitHub\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003eBuild documentation\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32\"\u003eneorv32\u003c/a\u003e\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/b3826041a97c94eacb434eefe8551450fc2b709e5c8f3d39c1fbfb323627310d/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322f446f63756d656e746174696f6e2e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d446f63756d656e746174696f6e266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666\" alt=\"Documentation\" data-canonical-src=\"https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Documentation.yml?branch=main\u0026amp;longCache=true\u0026amp;style=flat-square\u0026amp;label=Documentation\u0026amp;logo=Github%20Actions\u0026amp;logoColor=fff\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003eProcessor verification\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32\"\u003eneorv32\u003c/a\u003e\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/033a61c4e0ce2b2abd7054568c2b93f4c486867e2ddddf4e44fc44efb4c649af/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322f50726f636573736f722e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d50726f636573736f72253230436865636b266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666\" alt=\"Processor\" data-canonical-src=\"https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Processor.yml?branch=main\u0026amp;longCache=true\u0026amp;style=flat-square\u0026amp;label=Processor%20Check\u0026amp;logo=Github%20Actions\u0026amp;logoColor=fff\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003eRISCOF core verification\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32-riscof\"\u003eneorv32-riscof\u003c/a\u003e\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32-riscof/actions/workflows/main.yml\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/4d9ab47b6009c0a9d11ef6c6ff5e33c6dfdc3d7c74a3352e0834dbce6a0bada4/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322d726973636f662f6d61696e2e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d6e656f727633322d726973636f66266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666\" alt=\"neorv32-riscof\" data-canonical-src=\"https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-riscof/main.yml?branch=main\u0026amp;longCache=true\u0026amp;style=flat-square\u0026amp;label=neorv32-riscof\u0026amp;logo=Github%20Actions\u0026amp;logoColor=fff\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003eFPGA implementations\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32-setups\"\u003eneorv32-setups\u003c/a\u003e\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32-setups/actions?query=workflow%3AImplementation\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/215aae1e97503b118315bf2bb29ad863f01274ee850f4f9a11851446c50907b8/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322d7365747570732f496d706c656d656e746174696f6e2e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d496d706c656d656e746174696f6e266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666\" alt=\"Implementation\" data-canonical-src=\"https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-setups/Implementation.yml?branch=main\u0026amp;longCache=true\u0026amp;style=flat-square\u0026amp;label=Implementation\u0026amp;logo=Github%20Actions\u0026amp;logoColor=fff\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003eAll-Verilog version\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32-verilog\"\u003eneorv32-verilog\u003c/a\u003e\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32-verilog/actions/workflows/main.yml\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/37b56f9c05374de5cf7f377d4ebf0882a3132e1481b1a53346698b7910c6eb19/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322d766572696c6f672f6d61696e2e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d6e656f727633322d766572696c6f67266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666\" alt=\"neorv32-verilog\" data-canonical-src=\"https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-verilog/main.yml?branch=main\u0026amp;longCache=true\u0026amp;style=flat-square\u0026amp;label=neorv32-verilog\u0026amp;logo=Github%20Actions\u0026amp;logoColor=fff\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003eFreeRTOS port\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32-freertos\"\u003eneorv32-freertos\u003c/a\u003e\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32-freertos/actions/workflows/main.yml\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/17920bea7b2f4183aabaf2429387fbf2d382750f108cbf807cdde130229d1933/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322d6672656572746f732f6d61696e2e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d6e656f727633322d6672656572746f7325323073696d266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666\" alt=\"neorv32-freertos\" data-canonical-src=\"https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-freertos/main.yml?branch=main\u0026amp;longCache=true\u0026amp;style=flat-square\u0026amp;label=neorv32-freertos%20sim\u0026amp;logo=Github%20Actions\u0026amp;logoColor=fff\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\u003c/markdown-accessiblity-table\u003e\n\u003cp dir=\"auto\"\u003eThe processor passes the official RISC-V architecture tests to ensure compatibility with the RISC-V ISA specs., which is checked by the\n\u003ca href=\"https://github.com/stnolting/neorv32-riscof\"\u003eneorv32-riscof\u003c/a\u003e repository. It can successfully run \u003cem\u003eany\u003c/em\u003e C program\n(for example from the \u003ca href=\"https://github.com/stnolting/neorv32/tree/main/sw/example\"\u003e\u003ccode\u003esw/example\u003c/code\u003e\u003c/a\u003e folder) including CoreMark\nand FreeRTOS and can be synthesized for \u003cem\u003eany\u003c/em\u003e target technology - \u003ca href=\"https://github.com/stnolting/neorv32-setups\"\u003etested\u003c/a\u003e\non AMD, Intel, Lattice, Gowin and Colong Chip FPGAs. The conversion into a single, plain-Verilog module file is automatically\nchecked by the \u003ca href=\"https://github.com/stnolting/neorv32-verilog\"\u003eneorv32-verilog\u003c/a\u003e repository.\u003c/p\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch2 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003e2. Features\u003c/h2\u003e\u003ca id=\"user-content-2-features\" class=\"anchor\" aria-label=\"Permalink: 2. Features\" href=\"#2-features\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cp dir=\"auto\"\u003eThe NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU.\nBy using generics the design is highly configurable and allows a flexible customization to tailor the\nsetup according to your needs. Note that all of the following SoC modules are entirely \u003cem\u003eoptional\u003c/em\u003e.\u003c/p\u003e\n\u003cp dir=\"auto\"\u003e\u003cstrong\u003eCPU Core\u003c/strong\u003e\u003c/p\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003e\u003ca href=\"https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/7a36f85b6d6806e6925f4e6bd714d78db7e76cafab7e178aa7a66a86d7f1f4a0/68747470733a2f2f696d672e736869656c64732e696f2f62616467652f524953432d2d5625323041726368697465637475726525323049442d31392d3030303030302e7376673f6c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6f676f3d726973637626636f6c6f72413d32373332373426636f6c6f72423d666262353137\" alt=\"RISCV-ARCHID\" data-canonical-src=\"https://img.shields.io/badge/RISC--V%20Architecture%20ID-19-000000.svg?longCache=true\u0026amp;style=flat-square\u0026amp;logo=riscv\u0026amp;colorA=273274\u0026amp;colorB=fbb517\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003eRISC-V 32-bit little-endian pipelined/multi-cycle modified Harvard architecture\u003c/li\u003e\n\u003cli\u003eSingle-core or SMP dual-core configuration (including low-latency inter-core communication)\u003c/li\u003e\n\u003cli\u003econfigurable \u003ca href=\"https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions\" rel=\"nofollow\"\u003einstruction sets and extensions\u003c/a\u003e:\n\u003cbr\u003e\n\u003ccode\u003eRV32\u003c/code\u003e\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_i_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eI\u003c/code\u003e\u003c/a\u003e/\u003ca href=\"https://stnolting.github.io/neorv32/#_e_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eE\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_m_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eM\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_a_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eA\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_c_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eC\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_b_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eB\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_u_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eU\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_x_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eX\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zaamo_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZaamo\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zalrsc_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZalrsc\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zba_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZba\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zbb_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZbb\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zbkb_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZbkb\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zbkc_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZbkc\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zbkx_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZbkx\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zbs_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZbs\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zicntr_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZicntr\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zicond_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZicond\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zicsr_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZicsr\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zifencei_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZifencei\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zihpm_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZihpm\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zfinx_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZfinx\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zkn_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZkn\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zknd_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZknd\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zkne_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZkne\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zknh_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZknh\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zkt_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZkt\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zks_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZks\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zksed_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZksed\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zksh_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZksh\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zmmul_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZmmul\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_zxcfu_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eZxcfu\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_sdext_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eSdext\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_sdtrig_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eSdtrig\u003c/code\u003e\u003c/a\u003e]\n[\u003ca href=\"https://stnolting.github.io/neorv32/#_smpmp_isa_extension\" rel=\"nofollow\"\u003e\u003ccode\u003eSmpmp\u003c/code\u003e\u003c/a\u003e]\u003c/li\u003e\n\u003cli\u003ecompatible to subsets of the RISC-V\n\u003cem\u003eUnprivileged ISA Specification\u003c/em\u003e (\u003ca href=\"https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-spec.pdf\"\u003epdf\u003c/a\u003e)\nand \u003cem\u003ePrivileged Architecture Specification\u003c/em\u003e (\u003ca href=\"https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-privileged.pdf\"\u003epdf\u003c/a\u003e).\u003c/li\u003e\n\u003cli\u003e\u003ccode\u003emachine\u003c/code\u003e and \u003ccode\u003euser\u003c/code\u003e privilege modes\u003c/li\u003e\n\u003cli\u003eimplements \u003cstrong\u003eall\u003c/strong\u003e standard RISC-V exceptions and interrupts + 16 fast interrupt request channels as NEORV32-specific extension\u003c/li\u003e\n\u003cli\u003ecustom functions unit (\u003ca href=\"https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu\" rel=\"nofollow\"\u003eCFU\u003c/a\u003e as \u003ccode\u003eZxcfu\u003c/code\u003e ISA extension)\nfor \u003cstrong\u003ecustom RISC-V instructions\u003c/strong\u003e;\u003c/li\u003e\n\u003cli\u003e\u003cem\u003eintrinsic\u003c/em\u003e libraries for CPU extensions that are not yet supported by GCC\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp dir=\"auto\"\u003e\u003cstrong\u003eMemories\u003c/strong\u003e\u003c/p\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003eprocessor-internal data and instruction memories (\u003ca href=\"https://stnolting.github.io/neorv32/#_data_memory_dmem\" rel=\"nofollow\"\u003eDMEM\u003c/a\u003e /\n\u003ca href=\"https://stnolting.github.io/neorv32/#_instruction_memory_imem\" rel=\"nofollow\"\u003eIMEM\u003c/a\u003e) \u0026amp;\ncaches (\u003ca href=\"https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache\" rel=\"nofollow\"\u003eiCACHE\u003c/a\u003e and\n\u003ca href=\"https://stnolting.github.io/neorv32/#_processor_internal_data_cache_dcache\" rel=\"nofollow\"\u003edCACHE\u003c/a\u003e)\u003c/li\u003e\n\u003cli\u003epre-installed bootloader (\u003ca href=\"https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom\" rel=\"nofollow\"\u003eBOOTLDROM\u003c/a\u003e) with serial user interface;\nallows booting application code via UART, TWI or from external SPI flash\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp dir=\"auto\"\u003e\u003cstrong\u003eTimers and Counters\u003c/strong\u003e\u003c/p\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003ecore local interruptor (\u003ca href=\"https://stnolting.github.io/neorv32/#_core_local_interruptor_clint\" rel=\"nofollow\"\u003eCLINT\u003c/a\u003e), RISC-V-compatible\u003c/li\u003e\n\u003cli\u003e32-bit general purpose timer (\u003ca href=\"https://stnolting.github.io/neorv32/#_general_purpose_timer_gptmr\" rel=\"nofollow\"\u003eGPTMR\u003c/a\u003e)\u003c/li\u003e\n\u003cli\u003ewatchdog timer (\u003ca href=\"https://stnolting.github.io/neorv32/#_watchdog_timer_wdt\" rel=\"nofollow\"\u003eWDT\u003c/a\u003e)\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp dir=\"auto\"\u003e\u003cstrong\u003eInput / Output\u003c/strong\u003e\u003c/p\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003estandard serial interfaces\n(\u003ca href=\"https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0\" rel=\"nofollow\"\u003eUART\u003c/a\u003e,\n\u003ca href=\"https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi\" rel=\"nofollow\"\u003eSPI\u003c/a\u003e (SPI host),\n\u003ca href=\"https://stnolting.github.io/neorv32/#_serial_data_interface_controller_sdi\" rel=\"nofollow\"\u003eSDI\u003c/a\u003e (SPI device),\n\u003ca href=\"https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi\" rel=\"nofollow\"\u003eTWI\u003c/a\u003e (I²C host),\n\u003ca href=\"https://stnolting.github.io/neorv32/#_two_wire_serial_device_controller_twd\" rel=\"nofollow\"\u003eTWD\u003c/a\u003e (I²C device),\n\u003ca href=\"https://stnolting.github.io/neorv32/#_one_wire_serial_interface_controller_onewire\" rel=\"nofollow\"\u003eONEWIRE/1-Wire\u003c/a\u003e)\u003c/li\u003e\n\u003cli\u003einterrupt-capable general purpose IOs (\u003ca href=\"https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio\" rel=\"nofollow\"\u003eGPIO\u003c/a\u003e) and\n\u003ca href=\"https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm\" rel=\"nofollow\"\u003ePWM\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003esmart LED interface (\u003ca href=\"https://stnolting.github.io/neorv32/#_smart_led_interface_neoled\" rel=\"nofollow\"\u003eNEOLED\u003c/a\u003e) to directly control NeoPixel(TM) LEDs\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp dir=\"auto\"\u003e\u003cstrong\u003eSoC Connectivity\u003c/strong\u003e\u003c/p\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003e32-bit external bus interface - Wishbone b4 compatible\n(\u003ca href=\"https://stnolting.github.io/neorv32/#_processor_external_bus_interface_xbus\" rel=\"nofollow\"\u003eXBUS\u003c/a\u003e) with optional cache (XCACHE);\n\u003ca href=\"https://github.com/stnolting/neorv32/blob/main/rtl/system_integration\"\u003ewrappers\u003c/a\u003e for AXI4-Lite and Avalon-MM host interfaces\u003c/li\u003e\n\u003cli\u003estream link interface with independent RX and TX channels - AXI4-Stream compatible\n(\u003ca href=\"https://stnolting.github.io/neorv32/#_stream_link_interface_slink\" rel=\"nofollow\"\u003eSLINK\u003c/a\u003e)\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp dir=\"auto\"\u003e\u003cstrong\u003eAdvanced\u003c/strong\u003e\u003c/p\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003etrue-random number generator (\u003ca href=\"https://stnolting.github.io/neorv32/#_true_random_number_generator_trng\" rel=\"nofollow\"\u003eTRNG\u003c/a\u003e) based\non the \u003ca href=\"https://github.com/stnolting/neoTRNG\"\u003eneoTRNG\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003ecustom functions subsystem (\u003ca href=\"https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs\" rel=\"nofollow\"\u003eCFS\u003c/a\u003e)\nfor custom tightly-coupled co-processors, accelerators or interfaces\u003c/li\u003e\n\u003cli\u003edirect memory access controller (\u003ca href=\"https://stnolting.github.io/neorv32/#_direct_memory_access_controller_dma\" rel=\"nofollow\"\u003eDMA\u003c/a\u003e) for CPU-independent\ndata transfers and conversions\u003c/li\u003e\n\u003cli\u003ecyclic redundancy check unit (\u003ca href=\"https://stnolting.github.io/neorv32/#_cyclic_redundancy_check_crc\" rel=\"nofollow\"\u003eCRC\u003c/a\u003e) to test\ndata integrity (CRC8/16/32)\u003c/li\u003e\n\u003cli\u003e32 dedicated hardware spinlocks (\u003ca href=\"https://stnolting.github.io/neorv32/#_hardware_spinlocks_hwspinlock\" rel=\"nofollow\"\u003eHWSPINLOCK\u003c/a\u003e)\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp dir=\"auto\"\u003e\u003cstrong\u003eDebugging\u003c/strong\u003e\u003c/p\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003eon-chip debugger (\u003ca href=\"https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd\" rel=\"nofollow\"\u003eOCD\u003c/a\u003e) accessible via standard JTAG interface\u003c/li\u003e\n\u003cli\u003ecompatible to the \"Minimal RISC-V Debug Specification Version 1.0\"\u003c/li\u003e\n\u003cli\u003ecompatible with \u003cstrong\u003eOpenOCD\u003c/strong\u003e, \u003cstrong\u003eGDB\u003c/strong\u003e and \u003cstrong\u003eSegger Embedded Studio\u003c/strong\u003e\u003c/li\u003e\n\u003cli\u003eRISC-V \u003ca href=\"https://stnolting.github.io/neorv32/#_trigger_module\" rel=\"nofollow\"\u003etrigger module\u003c/a\u003e for hardware-assisted breakpoints\u003c/li\u003e\n\u003cli\u003eoptional authentication module to implement custom security mechanisms\u003c/li\u003e\n\u003c/ul\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch2 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003e3. FPGA Implementation Results\u003c/h2\u003e\u003ca id=\"user-content-3-fpga-implementation-results\" class=\"anchor\" aria-label=\"Permalink: 3. FPGA Implementation Results\" href=\"#3-fpga-implementation-results\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cp dir=\"auto\"\u003eImplementation results for \u003cstrong\u003eexemplary CPU configurations\u003c/strong\u003e generated for an Intel Cyclone IV \u003ccode\u003eEP4CE22F17C6\u003c/code\u003e FPGA\nusing Intel Quartus Prime Lite 21.1 (no timing constrains, \u003cem\u003ebalanced optimization\u003c/em\u003e, f_max from \u003cem\u003eSlow 1200mV 0C Model\u003c/em\u003e).\u003c/p\u003e\n\u003cmarkdown-accessiblity-table\u003e\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth align=\"left\"\u003eCPU Configuration (version \u003ca href=\"https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md\"\u003e1.7.8.5\u003c/a\u003e)\u003c/th\u003e\n\u003cth align=\"center\"\u003eLEs\u003c/th\u003e\n\u003cth align=\"center\"\u003eFFs\u003c/th\u003e\n\u003cth align=\"center\"\u003eMemory bits\u003c/th\u003e\n\u003cth align=\"center\"\u003eDSPs\u003c/th\u003e\n\u003cth align=\"center\"\u003ef_max\u003c/th\u003e\n\u003c/tr\u003e\n\u003c/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003e\u003ccode\u003erv32i_Zicsr\u003c/code\u003e\u003c/td\u003e\n\u003ctd align=\"center\"\u003e1223\u003c/td\u003e\n\u003ctd align=\"center\"\u003e607\u003c/td\u003e\n\u003ctd align=\"center\"\u003e1024\u003c/td\u003e\n\u003ctd align=\"center\"\u003e0\u003c/td\u003e\n\u003ctd align=\"center\"\u003e130 MHz\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003e\u003ccode\u003erv32i_Zicsr_Zicntr\u003c/code\u003e\u003c/td\u003e\n\u003ctd align=\"center\"\u003e1578\u003c/td\u003e\n\u003ctd align=\"center\"\u003e773\u003c/td\u003e\n\u003ctd align=\"center\"\u003e1024\u003c/td\u003e\n\u003ctd align=\"center\"\u003e0\u003c/td\u003e\n\u003ctd align=\"center\"\u003e130 MHz\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003e\u003ccode\u003erv32imc_Zicsr_Zicntr\u003c/code\u003e\u003c/td\u003e\n\u003ctd align=\"center\"\u003e2338\u003c/td\u003e\n\u003ctd align=\"center\"\u003e992\u003c/td\u003e\n\u003ctd align=\"center\"\u003e1024\u003c/td\u003e\n\u003ctd align=\"center\"\u003e0\u003c/td\u003e\n\u003ctd align=\"center\"\u003e130 MHz\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\u003c/markdown-accessiblity-table\u003e\n\u003cp dir=\"auto\"\u003eAn incremental list of CPU extensions and processor modules can be found in the \u003ca href=\"https://stnolting.github.io/neorv32/#_fpga_implementation_results\" rel=\"nofollow\"\u003eData Sheet: FPGA Implementation Results\u003c/a\u003e.\u003c/p\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch2 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003e4. Performance\u003c/h2\u003e\u003ca id=\"user-content-4-performance\" class=\"anchor\" aria-label=\"Permalink: 4. Performance\" href=\"#4-performance\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cp dir=\"auto\"\u003eThe NEORV32 CPU is based on a two-stages pipelined/multi-cycle architecture (fetch and execute).\nThe following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing\n2000 iterations of the \u003ca href=\"https://github.com/stnolting/neorv32/blob/main/sw/example/coremark\"\u003eCoreMark\u003c/a\u003e CPU benchmark\n(using plain GCC10 rv32i built-in libraries only!).\u003c/p\u003e\n\u003cmarkdown-accessiblity-table\u003e\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth align=\"left\"\u003eCPU Configuration (version \u003ca href=\"https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md\"\u003e1.5.7.10\u003c/a\u003e)\u003c/th\u003e\n\u003cth align=\"center\"\u003eCoreMark Score\u003c/th\u003e\n\u003c/tr\u003e\n\u003c/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003e\u003cem\u003esmall\u003c/em\u003e (\u003ccode\u003erv32i_Zicsr_Zifencei\u003c/code\u003e)\u003c/td\u003e\n\u003ctd align=\"center\"\u003e33.89\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003e\u003cem\u003emedium\u003c/em\u003e (\u003ccode\u003erv32imc_Zicsr_Zifencei\u003c/code\u003e)\u003c/td\u003e\n\u003ctd align=\"center\"\u003e62.50\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003e\u003cem\u003eperformance\u003c/em\u003e (\u003ccode\u003erv32imc_Zicsr_Zifencei\u003c/code\u003e + perf. options)\u003c/td\u003e\n\u003ctd align=\"center\"\u003e95.23\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\u003c/markdown-accessiblity-table\u003e\n\u003cp dir=\"auto\"\u003eMore information regarding the CPU performance can be found in the\n\u003ca href=\"https://stnolting.github.io/neorv32/#_cpu_performance\" rel=\"nofollow\"\u003eData Sheet: CPU Performance\u003c/a\u003e.\nThe CPU \u0026amp; SoC provide further \"tuning\" options to optimize the design for maximum performance,\nmaximum clock speed, minimal area or minimal power consumption:\n\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration\" rel=\"nofollow\"\u003eUser Guide: Application-Specific Processor Configuration\u003c/a\u003e\u003c/p\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch2 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003e5. Getting Started\u003c/h2\u003e\u003ca id=\"user-content-5-getting-started\" class=\"anchor\" aria-label=\"Permalink: 5. Getting Started\" href=\"#5-getting-started\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cp dir=\"auto\"\u003eThis overview provides some \u003cem\u003equick links\u003c/em\u003e to the most important sections of the\n\u003ca href=\"https://stnolting.github.io/neorv32\" rel=\"nofollow\"\u003eonline Data Sheet\u003c/a\u003e and the \u003ca href=\"https://stnolting.github.io/neorv32/ug\" rel=\"nofollow\"\u003eonline User Guide\u003c/a\u003e.\u003c/p\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch3 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003e🔍 \u003ca href=\"https://stnolting.github.io/neorv32/#_overview\" rel=\"nofollow\"\u003eNEORV32 Project\u003c/a\u003e - An Introduction\u003c/h3\u003e\u003ca id=\"user-content-mag-neorv32-project---an-introduction\" class=\"anchor\" aria-label=\"Permalink: :mag: NEORV32 Project - An Introduction\" href=\"#mag-neorv32-project---an-introduction\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_rationale\" rel=\"nofollow\"\u003eRationale\u003c/a\u003e - why? how come? what for?\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_project_key_features\" rel=\"nofollow\"\u003eKey Features\u003c/a\u003e - what makes it special\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_project_folder_structure\" rel=\"nofollow\"\u003eStructure\u003c/a\u003e - folders, RTL files and compile order\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_file_list_files\" rel=\"nofollow\"\u003eFile-List Files\u003c/a\u003e - to simplify HDL setup\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_fpga_implementation_results\" rel=\"nofollow\"\u003eMetrics\u003c/a\u003e - FPGA implementation and performance evaluation\u003c/li\u003e\n\u003c/ul\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch3 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003e🖥️ \u003ca href=\"https://stnolting.github.io/neorv32/#_neorv32_processor_soc\" rel=\"nofollow\"\u003eNEORV32 Processor\u003c/a\u003e - The SoC\u003c/h3\u003e\u003ca id=\"user-content-desktop_computer-neorv32-processor---the-soc\" class=\"anchor\" aria-label=\"Permalink: :desktop_computer: NEORV32 Processor - The SoC\" href=\"#desktop_computer-neorv32-processor---the-soc\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_processor_top_entity_signals\" rel=\"nofollow\"\u003eTop Entity - Signals\u003c/a\u003e - how to connect to the processor\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_processor_top_entity_generics\" rel=\"nofollow\"\u003eTop Entity - Generics\u003c/a\u003e - processor/CPU configuration options\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_address_space\" rel=\"nofollow\"\u003eAddress Space\u003c/a\u003e - memory layout and address mapping\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_boot_configuration\" rel=\"nofollow\"\u003eBoot Configuration\u003c/a\u003e - how to make the processor start executing\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_processor_internal_modules\" rel=\"nofollow\"\u003eSoC Modules\u003c/a\u003e - IO/peripheral modules and memories\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd\" rel=\"nofollow\"\u003eOn-Chip Debugger\u003c/a\u003e - in-system debugging of the processor via JTAG\u003c/li\u003e\n\u003c/ul\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch3 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003e🧮 \u003ca href=\"https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu\" rel=\"nofollow\"\u003eNEORV32 CPU\u003c/a\u003e - The Core\u003c/h3\u003e\u003ca id=\"user-content-abacus-neorv32-cpu---the-core\" class=\"anchor\" aria-label=\"Permalink: :abacus: NEORV32 CPU - The Core\" href=\"#abacus-neorv32-cpu---the-core\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_risc_v_compatibility\" rel=\"nofollow\"\u003eRISC-V Compatibility\u003c/a\u003e - what is compatible to the specs and what is not\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_architecture\" rel=\"nofollow\"\u003eArchitecture\u003c/a\u003e - a look under the hood\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_full_virtualization\" rel=\"nofollow\"\u003eFull Virtualization\u003c/a\u003e - execution safety\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions\" rel=\"nofollow\"\u003eISA and Extensions\u003c/a\u003e - available (RISC-V) ISA extensions\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs\" rel=\"nofollow\"\u003eCSRs\u003c/a\u003e - control and status registers\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts\" rel=\"nofollow\"\u003eTraps\u003c/a\u003e - interrupts and exceptions\u003c/li\u003e\n\u003c/ul\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch3 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003e💾 \u003ca href=\"https://stnolting.github.io/neorv32/#_software_framework\" rel=\"nofollow\"\u003eSoftware Framework\u003c/a\u003e - The Software Ecosystem\u003c/h3\u003e\u003ca id=\"user-content-floppy_disk-software-framework---the-software-ecosystem\" class=\"anchor\" aria-label=\"Permalink: :floppy_disk: Software Framework - The Software Ecosystem\" href=\"#floppy_disk-software-framework---the-software-ecosystem\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003e\u003ca href=\"https://github.com/stnolting/neorv32/tree/main/sw/example\"\u003eExample Programs\u003c/a\u003e - examples how to use the processor's IO/peripheral modules\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_core_libraries\" rel=\"nofollow\"\u003eCore Libraries\u003c/a\u003e - high-level functions for accessing the processor's peripherals\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/sw/files.html\" rel=\"nofollow\"\u003eSoftware Framework Documentation\u003c/a\u003e - \u003cem\u003edoxygen\u003c/em\u003e-based\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_application_makefile\" rel=\"nofollow\"\u003eApplication Makefile\u003c/a\u003e - turning \u003cem\u003eyour\u003c/em\u003e application into an executable\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_bootloader\" rel=\"nofollow\"\u003eBootloader\u003c/a\u003e - the build-in NEORV32 bootloader\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_executable_image_format\" rel=\"nofollow\"\u003eImage Generator\u003c/a\u003e - create (FPGA) memory initialization files from your application\u003c/li\u003e\n\u003c/ul\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch3 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003e🚀 \u003ca href=\"https://stnolting.github.io/neorv32/ug/\" rel=\"nofollow\"\u003eUser Guide\u003c/a\u003e - Let's Get It Started\u003c/h3\u003e\u003ca id=\"user-content-rocket-user-guide---lets-get-it-started\" class=\"anchor\" aria-label=\"Permalink: :rocket: User Guide - Let's Get It Started\" href=\"#rocket-user-guide---lets-get-it-started\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup\" rel=\"nofollow\"\u003eToolchain Setup\u003c/a\u003e - install and set up the RISC-V GCC toolchain\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_general_hardware_setup\" rel=\"nofollow\"\u003eGeneral Hardware Setup\u003c/a\u003e - set up a new NEORV32 FPGA project\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup\" rel=\"nofollow\"\u003eGeneral Software Setup\u003c/a\u003e - configure the software framework\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_application_program_compilation\" rel=\"nofollow\"\u003eApplication Compilation\u003c/a\u003e - compile an application using \u003cem\u003emake\u003c/em\u003e\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart\" rel=\"nofollow\"\u003eUpload via Bootloader\u003c/a\u003e - upload and execute executables\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration\" rel=\"nofollow\"\u003eApplication-Specific Processor Configuration\u003c/a\u003e - tailor the processor to your needs\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules\" rel=\"nofollow\"\u003eAdding Custom Hardware Modules\u003c/a\u003e - add \u003cem\u003eyour\u003c/em\u003e custom hardware\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger\" rel=\"nofollow\"\u003eDebugging via the On-Chip Debugger\u003c/a\u003e - step through code \u003cem\u003eonline\u003c/em\u003e and \u003cem\u003ein-system\u003c/em\u003e\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_simulating_the_processor\" rel=\"nofollow\"\u003eSimulation\u003c/a\u003e - simulate the whole SoC\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_litex_soc_builder_support\" rel=\"nofollow\"\u003eLiteX Integration\u003c/a\u003e - build a SoC using NEORV32 + \u003ca href=\"https://github.com/enjoy-digital/litex\"\u003eLiteX\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_neorv32_in_verilog\" rel=\"nofollow\"\u003eConvert to Verilog\u003c/a\u003e - turn the NEORV32 into an all-Verilog design\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block\" rel=\"nofollow\"\u003ePackage as Vivado IP block\u003c/a\u003e - turn the entire processor into an interactive AMD Vivado IP block\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/ug/#_eclipse_ide\" rel=\"nofollow\"\u003eUsing Eclipse\u003c/a\u003e - use the Eclipse IDE for developing and debugging\u003c/li\u003e\n\u003c/ul\u003e\n\u003cdiv class=\"markdown-heading\" dir=\"auto\"\u003e\u003ch3 tabindex=\"-1\" class=\"heading-element\" dir=\"auto\"\u003e©️ Legal\u003c/h3\u003e\u003ca id=\"user-content-copyright-legal\" class=\"anchor\" aria-label=\"Permalink: :copyright: Legal\" href=\"#copyright-legal\"\u003e\u003csvg class=\"octicon octicon-link\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" height=\"16\" aria-hidden=\"true\"\u003e\u003cpath d=\"m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z\"\u003e\u003c/path\u003e\u003c/svg\u003e\u003c/a\u003e\u003c/div\u003e\n\u003cp dir=\"auto\"\u003e\u003ca href=\"https://github.com/stnolting/neorv32/blob/main/LICENSE\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/4edfc017e04cec3e3d6a4d980d66702213a495d21dca18fc113ad5080f1d623b/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f6c6963656e73652f73746e6f6c74696e672f6e656f727633323f6c6f6e6743616368653d74727565267374796c653d666c6174\" alt=\"license\" data-canonical-src=\"https://img.shields.io/github/license/stnolting/neorv32?longCache=true\u0026amp;style=flat\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\n\u003ca href=\"https://doi.org/10.5281/zenodo.5018888\" rel=\"nofollow\"\u003e\u003cimg src=\"https://camo.githubusercontent.com/f67e5e364442b780fd6dc827d4cc8b3d942a5140bdb0c6e943c09516d57bdb97/68747470733a2f2f7a656e6f646f2e6f72672f62616467652f444f492f31302e353238312f7a656e6f646f2e353031383838382e737667\" alt=\"DOI\" data-canonical-src=\"https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg\" style=\"max-width: 100%;\"\u003e\u003c/a\u003e\u003c/p\u003e\n\u003cul dir=\"auto\"\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_legal\" rel=\"nofollow\"\u003eOverview\u003c/a\u003e - license, disclaimer, limitation of liability for external links, proprietary notice, etc.\u003c/li\u003e\n\u003cli\u003e\u003ca href=\"https://stnolting.github.io/neorv32/#_citing\" rel=\"nofollow\"\u003eCiting\u003c/a\u003e - citing information\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp dir=\"auto\"\u003eThis is an open-source project that is free of charge. Use this project in any way you like\n(as long as it complies to the permissive \u003ca href=\"https://github.com/stnolting/neorv32/blob/main/LICENSE\"\u003elicense\u003c/a\u003e).\nPlease cite it appropriately. 👍\u003c/p\u003e\n\u003chr\u003e\n\u003cp dir=\"auto\"\u003e\u003cstrong\u003e❤️ A big shout-out to the community and all the \u003ca href=\"https://github.com/stnolting/neorv32/graphs/contributors\"\u003econtributors\u003c/a\u003e -\nthis project would not be where it is without them!\u003c/strong\u003e\u003c/p\u003e\n\u003c/article\u003e","loaded":true,"timedOut":false,"errorMessage":null,"headerInfo":{"toc":[{"level":1,"text":"The NEORV32 RISC-V Processor","anchor":"the-neorv32-risc-v-processor","htmlText":"The NEORV32 RISC-V Processor"},{"level":2,"text":"1. Overview","anchor":"1-overview","htmlText":"1. Overview"},{"level":3,"text":"Key Features","anchor":"key-features","htmlText":"Key Features"},{"level":3,"text":"Project Status","anchor":"project-status","htmlText":"Project Status"},{"level":2,"text":"2. Features","anchor":"2-features","htmlText":"2. Features"},{"level":2,"text":"3. FPGA Implementation Results","anchor":"3-fpga-implementation-results","htmlText":"3. FPGA Implementation Results"},{"level":2,"text":"4. Performance","anchor":"4-performance","htmlText":"4. Performance"},{"level":2,"text":"5. Getting Started","anchor":"5-getting-started","htmlText":"5. Getting Started"},{"level":3,"text":":mag: NEORV32 Project - An Introduction","anchor":"mag-neorv32-project---an-introduction","htmlText":"🔍 NEORV32 Project - An Introduction"},{"level":3,"text":":desktop_computer: NEORV32 Processor - The SoC","anchor":"desktop_computer-neorv32-processor---the-soc","htmlText":"🖥️ NEORV32 Processor - The SoC"},{"level":3,"text":":abacus: NEORV32 CPU - The Core","anchor":"abacus-neorv32-cpu---the-core","htmlText":"🧮 NEORV32 CPU - The Core"},{"level":3,"text":":floppy_disk: Software Framework - The Software Ecosystem","anchor":"floppy_disk-software-framework---the-software-ecosystem","htmlText":"💾 Software Framework - The Software Ecosystem"},{"level":3,"text":":rocket: User Guide - Let's Get It Started","anchor":"rocket-user-guide---lets-get-it-started","htmlText":"🚀 User Guide - Let's Get It Started"},{"level":3,"text":":copyright: Legal","anchor":"copyright-legal","htmlText":"©️ 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src="/stnolting/neorv32/raw/main/docs/figures/neorv32_logo_riscv.png" alt="NEORV32" style="max-width: 100%;"></a></p> <div class="markdown-heading" dir="auto"><h1 tabindex="-1" class="heading-element" dir="auto">The NEORV32 RISC-V Processor</h1><a id="user-content-the-neorv32-risc-v-processor" class="anchor" aria-label="Permalink: The NEORV32 RISC-V Processor" href="#the-neorv32-risc-v-processor"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <p dir="auto"><a href="https://github.com/stnolting/neorv32/releases/tag/nightly"><img src="https://camo.githubusercontent.com/bef4b71e8fe61bd4e17af6e7d8e295bafcc8b27b1c6c51437b0517fe6c2f5ca9/68747470733a2f2f696d672e736869656c64732e696f2f62616467652f6461746125323073686565742d5044462d6666626430303f6c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6f676f3d6173636969646f63746f7226636f6c6f72413d323733323734" alt="datasheet (pdf)" data-canonical-src="https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor&colorA=273274" style="max-width: 100%;"></a> <a href="https://stnolting.github.io/neorv32" rel="nofollow"><img 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data-canonical-src="https://img.shields.io/badge/doxygen-HTML-ffbd00?longCache=true&style=flat-square&logo=Doxygen&colorA=273274" style="max-width: 100%;"></a></p> <ol dir="auto"> <li><a href="#1-overview">Overview</a> <ul dir="auto"> <li><a href="#key-features">Key Features</a></li> <li><a href="#project-status">Project Status</a></li> </ul> </li> <li><a href="#2-features">Features</a></li> <li><a href="#3-fpga-implementation-results">FPGA Implementation Results</a></li> <li><a href="#4-performance">Performance</a></li> <li><a href="#5-getting-started"><strong>Getting Started</strong></a> 🚀</li> </ol> <div class="markdown-heading" dir="auto"><h2 tabindex="-1" class="heading-element" dir="auto">1. Overview</h2><a id="user-content-1-overview" class="anchor" aria-label="Permalink: 1. Overview" href="#1-overview"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <p dir="auto"><a target="_blank" rel="noopener noreferrer" href="/stnolting/neorv32/blob/main/docs/figures/neorv32_processor.png"><img src="/stnolting/neorv32/raw/main/docs/figures/neorv32_processor.png" alt="neorv32 Overview" style="max-width: 100%;"></a></p> <p dir="auto">The NEORV32 Processor is a <strong>customizable microcontroller-like system on chip (SoC)</strong> built around the NEORV32 <a href="https://riscv.org/" rel="nofollow">RISC-V</a> CPU that is written in <strong>platform-independent VHDL</strong>. The processor is intended as auxiliary controller in larger SoC designs or as tiny and customized microcontroller that even fits into a Lattice iCE40 UltraPlus low-power & low-density FPGA. The project is intended to work <em>out of the box</em> and targets FPGA / RISC-V beginners as well as advanced users.</p> <p dir="auto">Special focus is paid on <strong>execution safety</strong> to provide defined and predictable behavior at any time. For example, the CPU ensures <em>all</em> memory accesses are properly acknowledged and <em>all</em> invalid/malformed instructions are always detected as such. Whenever an unexpected state occurs the application software is informed via <em>precise</em> and resumable hardware exceptions.</p> <ul dir="auto"> <li>♻️ Looking for an <strong>all-Verilog</strong> version? Have a look at <a href="https://github.com/stnolting/neorv32-verilog">neorv32-verilog</a>.</li> <li>✔️ <a href="#project-status">Continuous integration</a> to check for regressions (including RISC-V ISA compatibility check using <strong>RISCOF</strong>).</li> <li>📂 <a href="https://github.com/stnolting/neorv32-setups">Exemplary setups</a> and <a href="https://github.com/stnolting/neorv32-setups/blob/main/README.md#Community-Projects">community projects</a> targeting various FPGA boards and toolchains to get started.</li> <li>📦 The entire processor is also available as <a href="https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block" rel="nofollow">Vivado IP Block</a>.</li> <li>🪁 Support for <a href="https://github.com/stnolting/neorv32-freertos">FreeRTOS</a>, <a href="https://docs.zephyrproject.org/latest/boards/others/neorv32/doc/index.html" rel="nofollow">Zephyr OS</a> and <a href="https://github.com/enjoy-digital/litex/wiki/CPUs#risc-v---neorv32">LiteX</a> SoC Builder Framework.</li> <li>🖥️ Pre-configured <a href="https://stnolting.github.io/neorv32/ug/#_eclipse_ide" rel="nofollow">Eclipse project</a> for developing and debugging code using an IDE.</li> <li>🏷️ The project's change log is available in <a href="https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md">CHANGELOG.md</a>.</li> <li>🚀 Check out the <a href="#5-getting-started">quick links below</a> and the <a href="https://stnolting.github.io/neorv32/ug/" rel="nofollow">User Guide</a> to get started setting up <em>your</em> NEORV32 processor!</li> <li>📚 For detailed information see the <a href="https://stnolting.github.io/neorv32/" rel="nofollow">NEORV32 online documentation</a>.</li> <li><g-emoji class="g-emoji" alias="interrobang">⁉️</g-emoji> Want to know more? Check out the <a href="https://stnolting.github.io/neorv32/#_rationale" rel="nofollow">project's rationale</a>.</li> <li>📋 File an <a href="https://github.com/stnolting/neorv32/issues">issue</a>/<a href="https://github.com/stnolting/neorv32/discussions">discussion</a>/ <a href="https://github.com/stnolting/neorv32/pulls">PR</a> for questions, comments, ideas, feedback or if something isn't working as expected.</li> <li>🤝 Find out how to <a href="https://github.com/stnolting/neorv32/blob/main/CONTRIBUTING.md">contribute</a>.</li> </ul> <div class="markdown-heading" dir="auto"><h3 tabindex="-1" class="heading-element" dir="auto">Key Features</h3><a id="user-content-key-features" class="anchor" aria-label="Permalink: Key Features" href="#key-features"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <ul class="contains-task-list"> <li class="task-list-item"><input type="checkbox" id="" disabled="" class="task-list-item-checkbox" checked=""> all-in-one package: <strong>CPU</strong> + <strong>SoC</strong> + <strong>Software Framework</strong> + <strong>Tooling</strong></li> <li class="task-list-item"><input type="checkbox" id="" disabled="" class="task-list-item-checkbox" checked=""> completely described in behavioral, platform-independent VHDL - <strong>no</strong> platform-specific primitives, macros, attributes, etc.; an all-Verilog "version" is also <a href="https://github.com/stnolting/neorv32-verilog">available</a></li> <li class="task-list-item"><input type="checkbox" id="" disabled="" class="task-list-item-checkbox" checked=""> extensive configuration options for adapting the processor to the requirements of the application (on CPU, processor and system level)</li> <li class="task-list-item"><input type="checkbox" id="" disabled="" class="task-list-item-checkbox" checked=""> aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off</li> <li class="task-list-item"><input type="checkbox" id="" disabled="" class="task-list-item-checkbox" checked=""> FPGA friendly (e.g. <em>all</em> internal memories can be mapped to block RAM - including the CPU's register file)</li> <li class="task-list-item"><input type="checkbox" id="" disabled="" class="task-list-item-checkbox" checked=""> optimized for high clock frequencies to ease integration / timing closure</li> <li class="task-list-item"><input type="checkbox" id="" disabled="" class="task-list-item-checkbox" checked=""> from zero to <em>"hello world!"</em> - completely open source and documented (on software and hardware side)</li> <li class="task-list-item"><input type="checkbox" id="" disabled="" class="task-list-item-checkbox" checked=""> easy to use even for digital logic / FPGA / RISC-V newcomers – intended to work <em>out of the box</em></li> </ul> <div class="markdown-heading" dir="auto"><h3 tabindex="-1" class="heading-element" dir="auto">Project Status</h3><a id="user-content-project-status" class="anchor" aria-label="Permalink: Project Status" href="#project-status"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <p dir="auto"><a href="https://github.com/stnolting/neorv32/releases"><img src="https://camo.githubusercontent.com/30dfe29f1ffd6bd303c1bc5861743785a9333baa166f3341ae7521bdf544706a/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f762f72656c656173652f73746e6f6c74696e672f6e656f727633323f6c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6f676f3d476974487562" alt="release" data-canonical-src="https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&style=flat-square&logo=GitHub" style="max-width: 100%;"></a> <a href="https://github.com/stnolting/neorv32/activity"><img src="https://camo.githubusercontent.com/d2b7f39be440167bb30f662816079f3d0d9b519c0228843b315b87f81a5d66ae/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f636f6d6d6974732d73696e63652f73746e6f6c74696e672f6e656f727633322f6c61746573743f6c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6f676f3d476974487562" alt="commits-since-latest-release" data-canonical-src="https://img.shields.io/github/commits-since/stnolting/neorv32/latest?longCache=true&style=flat-square&logo=GitHub" style="max-width: 100%;"></a></p> <markdown-accessiblity-table><table> <thead> <tr> <th align="left">Task / Subproject</th> <th align="left">Repository</th> <th align="left">CI Status</th> </tr> </thead> <tbody> <tr> <td align="left">GitHub pages (docs)</td> <td align="left"><a href="https://github.com/stnolting/neorv32">neorv32</a></td> <td align="left"><a href="https://stnolting.github.io/neorv32" rel="nofollow"><img src="https://camo.githubusercontent.com/c971a0b2b322db0ef7d3ee1a3f4e109e0b759899d43173dc66fceba849c49ff4/68747470733a2f2f696d672e736869656c64732e696f2f776562736974652e7376673f6c6162656c3d73746e6f6c74696e672e6769746875622e696f2532466e656f72763332266c6f6e6743616368653d74727565267374796c653d666c61742d7371756172652675726c3d6874747025334125324625324673746e6f6c74696e672e6769746875622e696f2532466e656f72763332253246696e6465782e68746d6c266c6f676f3d476974487562" alt="GitHub Pages" data-canonical-src="https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&longCache=true&style=flat-square&url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&logo=GitHub" style="max-width: 100%;"></a></td> </tr> <tr> <td align="left">Build documentation</td> <td align="left"><a href="https://github.com/stnolting/neorv32">neorv32</a></td> <td align="left"><a href="https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation"><img src="https://camo.githubusercontent.com/b3826041a97c94eacb434eefe8551450fc2b709e5c8f3d39c1fbfb323627310d/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322f446f63756d656e746174696f6e2e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d446f63756d656e746174696f6e266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666" alt="Documentation" data-canonical-src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Documentation.yml?branch=main&longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff" style="max-width: 100%;"></a></td> </tr> <tr> <td align="left">Processor verification</td> <td align="left"><a href="https://github.com/stnolting/neorv32">neorv32</a></td> <td align="left"><a href="https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor"><img src="https://camo.githubusercontent.com/033a61c4e0ce2b2abd7054568c2b93f4c486867e2ddddf4e44fc44efb4c649af/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322f50726f636573736f722e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d50726f636573736f72253230436865636b266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666" alt="Processor" data-canonical-src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Processor.yml?branch=main&longCache=true&style=flat-square&label=Processor%20Check&logo=Github%20Actions&logoColor=fff" style="max-width: 100%;"></a></td> </tr> <tr> <td align="left">RISCOF core verification</td> <td align="left"><a href="https://github.com/stnolting/neorv32-riscof">neorv32-riscof</a></td> <td align="left"><a href="https://github.com/stnolting/neorv32-riscof/actions/workflows/main.yml"><img src="https://camo.githubusercontent.com/4d9ab47b6009c0a9d11ef6c6ff5e33c6dfdc3d7c74a3352e0834dbce6a0bada4/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322d726973636f662f6d61696e2e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d6e656f727633322d726973636f66266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666" alt="neorv32-riscof" data-canonical-src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-riscof/main.yml?branch=main&longCache=true&style=flat-square&label=neorv32-riscof&logo=Github%20Actions&logoColor=fff" style="max-width: 100%;"></a></td> </tr> <tr> <td align="left">FPGA implementations</td> <td align="left"><a href="https://github.com/stnolting/neorv32-setups">neorv32-setups</a></td> <td align="left"><a href="https://github.com/stnolting/neorv32-setups/actions?query=workflow%3AImplementation"><img src="https://camo.githubusercontent.com/215aae1e97503b118315bf2bb29ad863f01274ee850f4f9a11851446c50907b8/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322d7365747570732f496d706c656d656e746174696f6e2e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d496d706c656d656e746174696f6e266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666" alt="Implementation" data-canonical-src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-setups/Implementation.yml?branch=main&longCache=true&style=flat-square&label=Implementation&logo=Github%20Actions&logoColor=fff" style="max-width: 100%;"></a></td> </tr> <tr> <td align="left">All-Verilog version</td> <td align="left"><a href="https://github.com/stnolting/neorv32-verilog">neorv32-verilog</a></td> <td align="left"><a href="https://github.com/stnolting/neorv32-verilog/actions/workflows/main.yml"><img src="https://camo.githubusercontent.com/37b56f9c05374de5cf7f377d4ebf0882a3132e1481b1a53346698b7910c6eb19/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322d766572696c6f672f6d61696e2e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d6e656f727633322d766572696c6f67266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666" alt="neorv32-verilog" data-canonical-src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-verilog/main.yml?branch=main&longCache=true&style=flat-square&label=neorv32-verilog&logo=Github%20Actions&logoColor=fff" style="max-width: 100%;"></a></td> </tr> <tr> <td align="left">FreeRTOS port</td> <td align="left"><a href="https://github.com/stnolting/neorv32-freertos">neorv32-freertos</a></td> <td align="left"><a href="https://github.com/stnolting/neorv32-freertos/actions/workflows/main.yml"><img src="https://camo.githubusercontent.com/17920bea7b2f4183aabaf2429387fbf2d382750f108cbf807cdde130229d1933/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f616374696f6e732f776f726b666c6f772f7374617475732f73746e6f6c74696e672f6e656f727633322d6672656572746f732f6d61696e2e796d6c3f6272616e63683d6d61696e266c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6162656c3d6e656f727633322d6672656572746f7325323073696d266c6f676f3d476974687562253230416374696f6e73266c6f676f436f6c6f723d666666" alt="neorv32-freertos" data-canonical-src="https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-freertos/main.yml?branch=main&longCache=true&style=flat-square&label=neorv32-freertos%20sim&logo=Github%20Actions&logoColor=fff" style="max-width: 100%;"></a></td> </tr> </tbody> </table></markdown-accessiblity-table> <p dir="auto">The processor passes the official RISC-V architecture tests to ensure compatibility with the RISC-V ISA specs., which is checked by the <a href="https://github.com/stnolting/neorv32-riscof">neorv32-riscof</a> repository. It can successfully run <em>any</em> C program (for example from the <a href="https://github.com/stnolting/neorv32/tree/main/sw/example"><code>sw/example</code></a> folder) including CoreMark and FreeRTOS and can be synthesized for <em>any</em> target technology - <a href="https://github.com/stnolting/neorv32-setups">tested</a> on AMD, Intel, Lattice, Gowin and Colong Chip FPGAs. The conversion into a single, plain-Verilog module file is automatically checked by the <a href="https://github.com/stnolting/neorv32-verilog">neorv32-verilog</a> repository.</p> <div class="markdown-heading" dir="auto"><h2 tabindex="-1" class="heading-element" dir="auto">2. Features</h2><a id="user-content-2-features" class="anchor" aria-label="Permalink: 2. Features" href="#2-features"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <p dir="auto">The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU. By using generics the design is highly configurable and allows a flexible customization to tailor the setup according to your needs. Note that all of the following SoC modules are entirely <em>optional</em>.</p> <p dir="auto"><strong>CPU Core</strong></p> <ul dir="auto"> <li><a href="https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md"><img src="https://camo.githubusercontent.com/7a36f85b6d6806e6925f4e6bd714d78db7e76cafab7e178aa7a66a86d7f1f4a0/68747470733a2f2f696d672e736869656c64732e696f2f62616467652f524953432d2d5625323041726368697465637475726525323049442d31392d3030303030302e7376673f6c6f6e6743616368653d74727565267374796c653d666c61742d737175617265266c6f676f3d726973637626636f6c6f72413d32373332373426636f6c6f72423d666262353137" alt="RISCV-ARCHID" data-canonical-src="https://img.shields.io/badge/RISC--V%20Architecture%20ID-19-000000.svg?longCache=true&style=flat-square&logo=riscv&colorA=273274&colorB=fbb517" style="max-width: 100%;"></a></li> <li>RISC-V 32-bit little-endian pipelined/multi-cycle modified Harvard architecture</li> <li>Single-core or SMP dual-core configuration (including low-latency inter-core communication)</li> <li>configurable <a href="https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions" rel="nofollow">instruction sets and extensions</a>: <br> <code>RV32</code> [<a href="https://stnolting.github.io/neorv32/#_i_isa_extension" rel="nofollow"><code>I</code></a>/<a href="https://stnolting.github.io/neorv32/#_e_isa_extension" rel="nofollow"><code>E</code></a>] [<a href="https://stnolting.github.io/neorv32/#_m_isa_extension" rel="nofollow"><code>M</code></a>] [<a href="https://stnolting.github.io/neorv32/#_a_isa_extension" rel="nofollow"><code>A</code></a>] [<a href="https://stnolting.github.io/neorv32/#_c_isa_extension" rel="nofollow"><code>C</code></a>] [<a href="https://stnolting.github.io/neorv32/#_b_isa_extension" rel="nofollow"><code>B</code></a>] [<a href="https://stnolting.github.io/neorv32/#_u_isa_extension" rel="nofollow"><code>U</code></a>] [<a href="https://stnolting.github.io/neorv32/#_x_isa_extension" rel="nofollow"><code>X</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zaamo_isa_extension" rel="nofollow"><code>Zaamo</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zalrsc_isa_extension" rel="nofollow"><code>Zalrsc</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zba_isa_extension" rel="nofollow"><code>Zba</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zbb_isa_extension" rel="nofollow"><code>Zbb</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zbkb_isa_extension" rel="nofollow"><code>Zbkb</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zbkc_isa_extension" rel="nofollow"><code>Zbkc</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zbkx_isa_extension" rel="nofollow"><code>Zbkx</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zbs_isa_extension" rel="nofollow"><code>Zbs</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zicntr_isa_extension" rel="nofollow"><code>Zicntr</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zicond_isa_extension" rel="nofollow"><code>Zicond</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zicsr_isa_extension" rel="nofollow"><code>Zicsr</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zifencei_isa_extension" rel="nofollow"><code>Zifencei</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zihpm_isa_extension" rel="nofollow"><code>Zihpm</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zfinx_isa_extension" rel="nofollow"><code>Zfinx</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zkn_isa_extension" rel="nofollow"><code>Zkn</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zknd_isa_extension" rel="nofollow"><code>Zknd</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zkne_isa_extension" rel="nofollow"><code>Zkne</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zknh_isa_extension" rel="nofollow"><code>Zknh</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zkt_isa_extension" rel="nofollow"><code>Zkt</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zks_isa_extension" rel="nofollow"><code>Zks</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zksed_isa_extension" rel="nofollow"><code>Zksed</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zksh_isa_extension" rel="nofollow"><code>Zksh</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zmmul_isa_extension" rel="nofollow"><code>Zmmul</code></a>] [<a href="https://stnolting.github.io/neorv32/#_zxcfu_isa_extension" rel="nofollow"><code>Zxcfu</code></a>] [<a href="https://stnolting.github.io/neorv32/#_sdext_isa_extension" rel="nofollow"><code>Sdext</code></a>] [<a href="https://stnolting.github.io/neorv32/#_sdtrig_isa_extension" rel="nofollow"><code>Sdtrig</code></a>] [<a href="https://stnolting.github.io/neorv32/#_smpmp_isa_extension" rel="nofollow"><code>Smpmp</code></a>]</li> <li>compatible to subsets of the RISC-V <em>Unprivileged ISA Specification</em> (<a href="https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-spec.pdf">pdf</a>) and <em>Privileged Architecture Specification</em> (<a href="https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-privileged.pdf">pdf</a>).</li> <li><code>machine</code> and <code>user</code> privilege modes</li> <li>implements <strong>all</strong> standard RISC-V exceptions and interrupts + 16 fast interrupt request channels as NEORV32-specific extension</li> <li>custom functions unit (<a href="https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu" rel="nofollow">CFU</a> as <code>Zxcfu</code> ISA extension) for <strong>custom RISC-V instructions</strong>;</li> <li><em>intrinsic</em> libraries for CPU extensions that are not yet supported by GCC</li> </ul> <p dir="auto"><strong>Memories</strong></p> <ul dir="auto"> <li>processor-internal data and instruction memories (<a href="https://stnolting.github.io/neorv32/#_data_memory_dmem" rel="nofollow">DMEM</a> / <a href="https://stnolting.github.io/neorv32/#_instruction_memory_imem" rel="nofollow">IMEM</a>) & caches (<a href="https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache" rel="nofollow">iCACHE</a> and <a href="https://stnolting.github.io/neorv32/#_processor_internal_data_cache_dcache" rel="nofollow">dCACHE</a>)</li> <li>pre-installed bootloader (<a href="https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom" rel="nofollow">BOOTLDROM</a>) with serial user interface; allows booting application code via UART, TWI or from external SPI flash</li> </ul> <p dir="auto"><strong>Timers and Counters</strong></p> <ul dir="auto"> <li>core local interruptor (<a href="https://stnolting.github.io/neorv32/#_core_local_interruptor_clint" rel="nofollow">CLINT</a>), RISC-V-compatible</li> <li>32-bit general purpose timer (<a href="https://stnolting.github.io/neorv32/#_general_purpose_timer_gptmr" rel="nofollow">GPTMR</a>)</li> <li>watchdog timer (<a href="https://stnolting.github.io/neorv32/#_watchdog_timer_wdt" rel="nofollow">WDT</a>)</li> </ul> <p dir="auto"><strong>Input / Output</strong></p> <ul dir="auto"> <li>standard serial interfaces (<a href="https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0" rel="nofollow">UART</a>, <a href="https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi" rel="nofollow">SPI</a> (SPI host), <a href="https://stnolting.github.io/neorv32/#_serial_data_interface_controller_sdi" rel="nofollow">SDI</a> (SPI device), <a href="https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi" rel="nofollow">TWI</a> (I²C host), <a href="https://stnolting.github.io/neorv32/#_two_wire_serial_device_controller_twd" rel="nofollow">TWD</a> (I²C device), <a href="https://stnolting.github.io/neorv32/#_one_wire_serial_interface_controller_onewire" rel="nofollow">ONEWIRE/1-Wire</a>)</li> <li>interrupt-capable general purpose IOs (<a href="https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio" rel="nofollow">GPIO</a>) and <a href="https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm" rel="nofollow">PWM</a></li> <li>smart LED interface (<a href="https://stnolting.github.io/neorv32/#_smart_led_interface_neoled" rel="nofollow">NEOLED</a>) to directly control NeoPixel(TM) LEDs</li> </ul> <p dir="auto"><strong>SoC Connectivity</strong></p> <ul dir="auto"> <li>32-bit external bus interface - Wishbone b4 compatible (<a href="https://stnolting.github.io/neorv32/#_processor_external_bus_interface_xbus" rel="nofollow">XBUS</a>) with optional cache (XCACHE); <a href="https://github.com/stnolting/neorv32/blob/main/rtl/system_integration">wrappers</a> for AXI4-Lite and Avalon-MM host interfaces</li> <li>stream link interface with independent RX and TX channels - AXI4-Stream compatible (<a href="https://stnolting.github.io/neorv32/#_stream_link_interface_slink" rel="nofollow">SLINK</a>)</li> </ul> <p dir="auto"><strong>Advanced</strong></p> <ul dir="auto"> <li>true-random number generator (<a href="https://stnolting.github.io/neorv32/#_true_random_number_generator_trng" rel="nofollow">TRNG</a>) based on the <a href="https://github.com/stnolting/neoTRNG">neoTRNG</a></li> <li>custom functions subsystem (<a href="https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs" rel="nofollow">CFS</a>) for custom tightly-coupled co-processors, accelerators or interfaces</li> <li>direct memory access controller (<a href="https://stnolting.github.io/neorv32/#_direct_memory_access_controller_dma" rel="nofollow">DMA</a>) for CPU-independent data transfers and conversions</li> <li>cyclic redundancy check unit (<a href="https://stnolting.github.io/neorv32/#_cyclic_redundancy_check_crc" rel="nofollow">CRC</a>) to test data integrity (CRC8/16/32)</li> <li>32 dedicated hardware spinlocks (<a href="https://stnolting.github.io/neorv32/#_hardware_spinlocks_hwspinlock" rel="nofollow">HWSPINLOCK</a>)</li> </ul> <p dir="auto"><strong>Debugging</strong></p> <ul dir="auto"> <li>on-chip debugger (<a href="https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd" rel="nofollow">OCD</a>) accessible via standard JTAG interface</li> <li>compatible to the "Minimal RISC-V Debug Specification Version 1.0"</li> <li>compatible with <strong>OpenOCD</strong>, <strong>GDB</strong> and <strong>Segger Embedded Studio</strong></li> <li>RISC-V <a href="https://stnolting.github.io/neorv32/#_trigger_module" rel="nofollow">trigger module</a> for hardware-assisted breakpoints</li> <li>optional authentication module to implement custom security mechanisms</li> </ul> <div class="markdown-heading" dir="auto"><h2 tabindex="-1" class="heading-element" dir="auto">3. FPGA Implementation Results</h2><a id="user-content-3-fpga-implementation-results" class="anchor" aria-label="Permalink: 3. FPGA Implementation Results" href="#3-fpga-implementation-results"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <p dir="auto">Implementation results for <strong>exemplary CPU configurations</strong> generated for an Intel Cyclone IV <code>EP4CE22F17C6</code> FPGA using Intel Quartus Prime Lite 21.1 (no timing constrains, <em>balanced optimization</em>, f_max from <em>Slow 1200mV 0C Model</em>).</p> <markdown-accessiblity-table><table> <thead> <tr> <th align="left">CPU Configuration (version <a href="https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md">1.7.8.5</a>)</th> <th align="center">LEs</th> <th align="center">FFs</th> <th align="center">Memory bits</th> <th align="center">DSPs</th> <th align="center">f_max</th> </tr> </thead> <tbody> <tr> <td align="left"><code>rv32i_Zicsr</code></td> <td align="center">1223</td> <td align="center">607</td> <td align="center">1024</td> <td align="center">0</td> <td align="center">130 MHz</td> </tr> <tr> <td align="left"><code>rv32i_Zicsr_Zicntr</code></td> <td align="center">1578</td> <td align="center">773</td> <td align="center">1024</td> <td align="center">0</td> <td align="center">130 MHz</td> </tr> <tr> <td align="left"><code>rv32imc_Zicsr_Zicntr</code></td> <td align="center">2338</td> <td align="center">992</td> <td align="center">1024</td> <td align="center">0</td> <td align="center">130 MHz</td> </tr> </tbody> </table></markdown-accessiblity-table> <p dir="auto">An incremental list of CPU extensions and processor modules can be found in the <a href="https://stnolting.github.io/neorv32/#_fpga_implementation_results" rel="nofollow">Data Sheet: FPGA Implementation Results</a>.</p> <div class="markdown-heading" dir="auto"><h2 tabindex="-1" class="heading-element" dir="auto">4. Performance</h2><a id="user-content-4-performance" class="anchor" aria-label="Permalink: 4. Performance" href="#4-performance"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <p dir="auto">The NEORV32 CPU is based on a two-stages pipelined/multi-cycle architecture (fetch and execute). The following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing 2000 iterations of the <a href="https://github.com/stnolting/neorv32/blob/main/sw/example/coremark">CoreMark</a> CPU benchmark (using plain GCC10 rv32i built-in libraries only!).</p> <markdown-accessiblity-table><table> <thead> <tr> <th align="left">CPU Configuration (version <a href="https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md">1.5.7.10</a>)</th> <th align="center">CoreMark Score</th> </tr> </thead> <tbody> <tr> <td align="left"><em>small</em> (<code>rv32i_Zicsr_Zifencei</code>)</td> <td align="center">33.89</td> </tr> <tr> <td align="left"><em>medium</em> (<code>rv32imc_Zicsr_Zifencei</code>)</td> <td align="center">62.50</td> </tr> <tr> <td align="left"><em>performance</em> (<code>rv32imc_Zicsr_Zifencei</code> + perf. options)</td> <td align="center">95.23</td> </tr> </tbody> </table></markdown-accessiblity-table> <p dir="auto">More information regarding the CPU performance can be found in the <a href="https://stnolting.github.io/neorv32/#_cpu_performance" rel="nofollow">Data Sheet: CPU Performance</a>. The CPU & SoC provide further "tuning" options to optimize the design for maximum performance, maximum clock speed, minimal area or minimal power consumption: <a href="https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration" rel="nofollow">User Guide: Application-Specific Processor Configuration</a></p> <div class="markdown-heading" dir="auto"><h2 tabindex="-1" class="heading-element" dir="auto">5. Getting Started</h2><a id="user-content-5-getting-started" class="anchor" aria-label="Permalink: 5. Getting Started" href="#5-getting-started"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <p dir="auto">This overview provides some <em>quick links</em> to the most important sections of the <a href="https://stnolting.github.io/neorv32" rel="nofollow">online Data Sheet</a> and the <a href="https://stnolting.github.io/neorv32/ug" rel="nofollow">online User Guide</a>.</p> <div class="markdown-heading" dir="auto"><h3 tabindex="-1" class="heading-element" dir="auto">🔍 <a href="https://stnolting.github.io/neorv32/#_overview" rel="nofollow">NEORV32 Project</a> - An Introduction</h3><a id="user-content-mag-neorv32-project---an-introduction" class="anchor" aria-label="Permalink: :mag: NEORV32 Project - An Introduction" href="#mag-neorv32-project---an-introduction"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <ul dir="auto"> <li><a href="https://stnolting.github.io/neorv32/#_rationale" rel="nofollow">Rationale</a> - why? how come? what for?</li> <li><a href="https://stnolting.github.io/neorv32/#_project_key_features" rel="nofollow">Key Features</a> - what makes it special</li> <li><a href="https://stnolting.github.io/neorv32/#_project_folder_structure" rel="nofollow">Structure</a> - folders, RTL files and compile order</li> <li><a href="https://stnolting.github.io/neorv32/#_file_list_files" rel="nofollow">File-List Files</a> - to simplify HDL setup</li> <li><a href="https://stnolting.github.io/neorv32/#_fpga_implementation_results" rel="nofollow">Metrics</a> - FPGA implementation and performance evaluation</li> </ul> <div class="markdown-heading" dir="auto"><h3 tabindex="-1" class="heading-element" dir="auto">🖥️ <a href="https://stnolting.github.io/neorv32/#_neorv32_processor_soc" rel="nofollow">NEORV32 Processor</a> - The SoC</h3><a id="user-content-desktop_computer-neorv32-processor---the-soc" class="anchor" aria-label="Permalink: :desktop_computer: NEORV32 Processor - The SoC" href="#desktop_computer-neorv32-processor---the-soc"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <ul dir="auto"> <li><a href="https://stnolting.github.io/neorv32/#_processor_top_entity_signals" rel="nofollow">Top Entity - Signals</a> - how to connect to the processor</li> <li><a href="https://stnolting.github.io/neorv32/#_processor_top_entity_generics" rel="nofollow">Top Entity - Generics</a> - processor/CPU configuration options</li> <li><a href="https://stnolting.github.io/neorv32/#_address_space" rel="nofollow">Address Space</a> - memory layout and address mapping</li> <li><a href="https://stnolting.github.io/neorv32/#_boot_configuration" rel="nofollow">Boot Configuration</a> - how to make the processor start executing</li> <li><a href="https://stnolting.github.io/neorv32/#_processor_internal_modules" rel="nofollow">SoC Modules</a> - IO/peripheral modules and memories</li> <li><a href="https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd" rel="nofollow">On-Chip Debugger</a> - in-system debugging of the processor via JTAG</li> </ul> <div class="markdown-heading" dir="auto"><h3 tabindex="-1" class="heading-element" dir="auto">🧮 <a href="https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu" rel="nofollow">NEORV32 CPU</a> - The Core</h3><a id="user-content-abacus-neorv32-cpu---the-core" class="anchor" aria-label="Permalink: :abacus: NEORV32 CPU - The Core" href="#abacus-neorv32-cpu---the-core"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <ul dir="auto"> <li><a href="https://stnolting.github.io/neorv32/#_risc_v_compatibility" rel="nofollow">RISC-V Compatibility</a> - what is compatible to the specs and what is not</li> <li><a href="https://stnolting.github.io/neorv32/#_architecture" rel="nofollow">Architecture</a> - a look under the hood</li> <li><a href="https://stnolting.github.io/neorv32/#_full_virtualization" rel="nofollow">Full Virtualization</a> - execution safety</li> <li><a href="https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions" rel="nofollow">ISA and Extensions</a> - available (RISC-V) ISA extensions</li> <li><a href="https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs" rel="nofollow">CSRs</a> - control and status registers</li> <li><a href="https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts" rel="nofollow">Traps</a> - interrupts and exceptions</li> </ul> <div class="markdown-heading" dir="auto"><h3 tabindex="-1" class="heading-element" dir="auto">💾 <a href="https://stnolting.github.io/neorv32/#_software_framework" rel="nofollow">Software Framework</a> - The Software Ecosystem</h3><a id="user-content-floppy_disk-software-framework---the-software-ecosystem" class="anchor" aria-label="Permalink: :floppy_disk: Software Framework - The Software Ecosystem" href="#floppy_disk-software-framework---the-software-ecosystem"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <ul dir="auto"> <li><a href="https://github.com/stnolting/neorv32/tree/main/sw/example">Example Programs</a> - examples how to use the processor's IO/peripheral modules</li> <li><a href="https://stnolting.github.io/neorv32/#_core_libraries" rel="nofollow">Core Libraries</a> - high-level functions for accessing the processor's peripherals</li> <li><a href="https://stnolting.github.io/neorv32/sw/files.html" rel="nofollow">Software Framework Documentation</a> - <em>doxygen</em>-based</li> <li><a href="https://stnolting.github.io/neorv32/#_application_makefile" rel="nofollow">Application Makefile</a> - turning <em>your</em> application into an executable</li> <li><a href="https://stnolting.github.io/neorv32/#_bootloader" rel="nofollow">Bootloader</a> - the build-in NEORV32 bootloader</li> <li><a href="https://stnolting.github.io/neorv32/#_executable_image_format" rel="nofollow">Image Generator</a> - create (FPGA) memory initialization files from your application</li> </ul> <div class="markdown-heading" dir="auto"><h3 tabindex="-1" class="heading-element" dir="auto">🚀 <a href="https://stnolting.github.io/neorv32/ug/" rel="nofollow">User Guide</a> - Let's Get It Started</h3><a id="user-content-rocket-user-guide---lets-get-it-started" class="anchor" aria-label="Permalink: :rocket: User Guide - Let's Get It Started" href="#rocket-user-guide---lets-get-it-started"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <ul dir="auto"> <li><a href="https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup" rel="nofollow">Toolchain Setup</a> - install and set up the RISC-V GCC toolchain</li> <li><a href="https://stnolting.github.io/neorv32/ug/#_general_hardware_setup" rel="nofollow">General Hardware Setup</a> - set up a new NEORV32 FPGA project</li> <li><a href="https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup" rel="nofollow">General Software Setup</a> - configure the software framework</li> <li><a href="https://stnolting.github.io/neorv32/ug/#_application_program_compilation" rel="nofollow">Application Compilation</a> - compile an application using <em>make</em></li> <li><a href="https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart" rel="nofollow">Upload via Bootloader</a> - upload and execute executables</li> <li><a href="https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration" rel="nofollow">Application-Specific Processor Configuration</a> - tailor the processor to your needs</li> <li><a href="https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules" rel="nofollow">Adding Custom Hardware Modules</a> - add <em>your</em> custom hardware</li> <li><a href="https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger" rel="nofollow">Debugging via the On-Chip Debugger</a> - step through code <em>online</em> and <em>in-system</em></li> <li><a href="https://stnolting.github.io/neorv32/ug/#_simulating_the_processor" rel="nofollow">Simulation</a> - simulate the whole SoC</li> <li><a href="https://stnolting.github.io/neorv32/ug/#_litex_soc_builder_support" rel="nofollow">LiteX Integration</a> - build a SoC using NEORV32 + <a href="https://github.com/enjoy-digital/litex">LiteX</a></li> <li><a href="https://stnolting.github.io/neorv32/ug/#_neorv32_in_verilog" rel="nofollow">Convert to Verilog</a> - turn the NEORV32 into an all-Verilog design</li> <li><a href="https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block" rel="nofollow">Package as Vivado IP block</a> - turn the entire processor into an interactive AMD Vivado IP block</li> <li><a href="https://stnolting.github.io/neorv32/ug/#_eclipse_ide" rel="nofollow">Using Eclipse</a> - use the Eclipse IDE for developing and debugging</li> </ul> <div class="markdown-heading" dir="auto"><h3 tabindex="-1" class="heading-element" dir="auto">©️ Legal</h3><a id="user-content-copyright-legal" class="anchor" aria-label="Permalink: :copyright: Legal" href="#copyright-legal"><svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div> <p dir="auto"><a href="https://github.com/stnolting/neorv32/blob/main/LICENSE"><img src="https://camo.githubusercontent.com/4edfc017e04cec3e3d6a4d980d66702213a495d21dca18fc113ad5080f1d623b/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f6c6963656e73652f73746e6f6c74696e672f6e656f727633323f6c6f6e6743616368653d74727565267374796c653d666c6174" alt="license" data-canonical-src="https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat" style="max-width: 100%;"></a> <a href="https://doi.org/10.5281/zenodo.5018888" rel="nofollow"><img src="https://camo.githubusercontent.com/f67e5e364442b780fd6dc827d4cc8b3d942a5140bdb0c6e943c09516d57bdb97/68747470733a2f2f7a656e6f646f2e6f72672f62616467652f444f492f31302e353238312f7a656e6f646f2e353031383838382e737667" alt="DOI" data-canonical-src="https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg" style="max-width: 100%;"></a></p> <ul dir="auto"> <li><a href="https://stnolting.github.io/neorv32/#_legal" rel="nofollow">Overview</a> - license, disclaimer, limitation of liability for external links, proprietary notice, etc.</li> <li><a href="https://stnolting.github.io/neorv32/#_citing" rel="nofollow">Citing</a> - citing information</li> </ul> <p dir="auto">This is an open-source project that is free of charge. Use this project in any way you like (as long as it complies to the permissive <a href="https://github.com/stnolting/neorv32/blob/main/LICENSE">license</a>). Please cite it appropriately. 👍</p> <hr> <p dir="auto"><strong>❤️ A big shout-out to the community and all the <a href="https://github.com/stnolting/neorv32/graphs/contributors">contributors</a> - this project would not be where it is without them!</strong></p> </article></div></div></div></div></div> <!-- --> <!-- --> <script type="application/json" id="__PRIMER_DATA_:R0:__">{"resolvedServerColorMode":"day"}</script></div> </react-partial> <input type="hidden" data-csrf="true" value="2q3j0BvQDd5A2EZgr6I6ejSgvhHvzyqJZOqWQr+Nz9XMLI3Jv2cLrDWj1v7b7Tu9zdc3x2CbxDccNfdC8R4qQA==" /> </div> <div data-view-component="true" class="Layout-sidebar"> <div class="BorderGrid about-margin" data-pjax> <div class="BorderGrid-row"> <div class="BorderGrid-cell"> <div class="hide-sm hide-md"> <h2 class="mb-3 h4">About</h2> <p class="f4 my-3"> 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. </p> <div class="my-3 d-flex flex-items-center"> <svg aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-link flex-shrink-0 mr-2"> <path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path> </svg> <span class="flex-auto min-width-0 css-truncate css-truncate-target width-fit"> <a title="https://neorv32.org" role="link" target="_blank" rel="noopener noreferrer nofollow" class="text-bold" href="https://neorv32.org">neorv32.org</a> </span> </div> <h3 class="sr-only">Topics</h3> <div class="my-3"> <div class="f6"> <a href="/topics/microcontroller" title="Topic: microcontroller" data-view-component="true" class="topic-tag topic-tag-link"> microcontroller </a> <a href="/topics/embedded" title="Topic: embedded" data-view-component="true" class="topic-tag topic-tag-link"> embedded </a> <a href="/topics/cpu" title="Topic: cpu" data-view-component="true" class="topic-tag topic-tag-link"> cpu </a> <a href="/topics/fpga" title="Topic: fpga" data-view-component="true" class="topic-tag topic-tag-link"> fpga </a> <a href="/topics/processor" title="Topic: processor" data-view-component="true" class="topic-tag topic-tag-link"> processor </a> <a href="/topics/vhdl" title="Topic: vhdl" data-view-component="true" class="topic-tag topic-tag-link"> vhdl </a> <a href="/topics/riscv" title="Topic: riscv" data-view-component="true" class="topic-tag topic-tag-link"> riscv </a> <a href="/topics/rtl" title="Topic: rtl" data-view-component="true" class="topic-tag topic-tag-link"> rtl </a> <a href="/topics/smp" title="Topic: smp" data-view-component="true" class="topic-tag topic-tag-link"> smp </a> <a href="/topics/multi-core" title="Topic: multi-core" data-view-component="true" class="topic-tag topic-tag-link"> multi-core </a> <a href="/topics/rtos" title="Topic: rtos" data-view-component="true" class="topic-tag topic-tag-link"> rtos </a> <a href="/topics/soc" title="Topic: soc" data-view-component="true" class="topic-tag topic-tag-link"> soc </a> <a href="/topics/risc-v" title="Topic: risc-v" data-view-component="true" class="topic-tag topic-tag-link"> risc-v </a> <a href="/topics/soft-core" title="Topic: soft-core" data-view-component="true" class="topic-tag topic-tag-link"> soft-core </a> <a href="/topics/system-on-chip" title="Topic: system-on-chip" data-view-component="true" class="topic-tag topic-tag-link"> system-on-chip </a> <a href="/topics/rv32" title="Topic: rv32" data-view-component="true" class="topic-tag topic-tag-link"> rv32 </a> <a href="/topics/asip" title="Topic: asip" data-view-component="true" class="topic-tag topic-tag-link"> asip </a> <a href="/topics/neorv32" title="Topic: neorv32" data-view-component="true" class="topic-tag topic-tag-link"> neorv32 </a> <a href="/topics/on-chip-debbuger" title="Topic: on-chip-debbuger" data-view-component="true" class="topic-tag topic-tag-link"> on-chip-debbuger </a> </div> </div> <h3 class="sr-only">Resources</h3> <div class="mt-2"> <a class="Link--muted" data-analytics-event="{"category":"Repository Overview","action":"click","label":"location:sidebar;file:readme"}" href="#readme-ov-file"> <svg aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-book mr-2"> <path d="M0 1.75A.75.75 0 0 1 .75 1h4.253c1.227 0 2.317.59 3 1.501A3.743 3.743 0 0 1 11.006 1h4.245a.75.75 0 0 1 .75.75v10.5a.75.75 0 0 1-.75.75h-4.507a2.25 2.25 0 0 0-1.591.659l-.622.621a.75.75 0 0 1-1.06 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8.7l-1.167-1.168c-.674-.671-1.78-.664-2.474.03-.268.269-.538.537-.802.797-.893.882-2.319.843-3.185-.032-.346-.35-.693-.697-1.043-1.047a.75.75 0 0 1-.04-1.016c.162-.191.336-.401.52-.623.62-.748 1.356-1.637 2.166-2.417Zm7.112 4.442c.313-.65.491-1.293.491-1.916v-.001c0-.614-.088-1.045-.23-1.385-.143-.339-.357-.633-.673-.949a3.111 3.111 0 0 0-2.218-.915c-1.092.003-2.165.627-3.226 1.602-.823.755-1.554 1.637-2.228 2.45l-.127.154.562.566a.755.755 0 0 0 1.066.02l.794-.79c1.258-1.258 3.312-1.31 4.594-.032.396.394.792.791 1.173 1.173Z"></path> </svg> Code of conduct </a> </div> <include-fragment src="/stnolting/neorv32/hovercards/citation/sidebar_partial?tree_name=main"> </include-fragment> <div class="mt-2"> <a href="/stnolting/neorv32/activity" data-view-component="true" class="Link Link--muted"><svg text="gray" aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-pulse mr-2"> <path d="M6 2c.306 0 .582.187.696.471L10 10.731l1.304-3.26A.751.751 0 0 1 12 7h3.25a.75.75 0 0 1 0 1.5h-2.742l-1.812 4.528a.751.751 0 0 1-1.392 0L6 4.77 4.696 8.03A.75.75 0 0 1 4 8.5H.75a.75.75 0 0 1 0-1.5h2.742l1.812-4.529A.751.751 0 0 1 6 2Z"></path> </svg> <span class="color-fg-muted">Activity</span></a> </div> <h3 class="sr-only">Stars</h3> <div class="mt-2"> <a href="/stnolting/neorv32/stargazers" data-view-component="true" class="Link Link--muted"><svg aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-star mr-2"> <path d="M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z"></path> </svg> <strong>1.7k</strong> stars</a> </div> <h3 class="sr-only">Watchers</h3> <div class="mt-2"> <a href="/stnolting/neorv32/watchers" data-view-component="true" class="Link Link--muted"><svg aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-eye mr-2"> <path d="M8 2c1.981 0 3.671.992 4.933 2.078 1.27 1.091 2.187 2.345 2.637 3.023a1.62 1.62 0 0 1 0 1.798c-.45.678-1.367 1.932-2.637 3.023C11.67 13.008 9.981 14 8 14c-1.981 0-3.671-.992-4.933-2.078C1.797 10.83.88 9.576.43 8.898a1.62 1.62 0 0 1 0-1.798c.45-.677 1.367-1.931 2.637-3.022C4.33 2.992 6.019 2 8 2ZM1.679 7.932a.12.12 0 0 0 0 .136c.411.622 1.241 1.75 2.366 2.717C5.176 11.758 6.527 12.5 8 12.5c1.473 0 2.825-.742 3.955-1.715 1.124-.967 1.954-2.096 2.366-2.717a.12.12 0 0 0 0-.136c-.412-.621-1.242-1.75-2.366-2.717C10.824 4.242 9.473 3.5 8 3.5c-1.473 0-2.825.742-3.955 1.715-1.124.967-1.954 2.096-2.366 2.717ZM8 10a2 2 0 1 1-.001-3.999A2 2 0 0 1 8 10Z"></path> </svg> <strong>51</strong> watching</a> </div> <h3 class="sr-only">Forks</h3> <div class="mt-2"> <a href="/stnolting/neorv32/forks" data-view-component="true" class="Link Link--muted"><svg aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-repo-forked mr-2"> <path d="M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z"></path> </svg> <strong>249</strong> forks</a> </div> <div class="mt-2"> <a class="Link--muted" href="/contact/report-content?content_url=https%3A%2F%2Fgithub.com%2Fstnolting%2Fneorv32&report=stnolting+%28user%29"> Report repository </a> </div> </div> </div> </div> <div class="BorderGrid-row"> <div class="BorderGrid-cell"> <h2 class="h4 mb-3" data-pjax="#repo-content-pjax-container" data-turbo-frame="repo-content-turbo-frame"> <a href="/stnolting/neorv32/releases" data-view-component="true" class="Link--primary no-underline Link">Releases <span title="44" data-view-component="true" class="Counter">44</span></a></h2> <a class="Link--primary d-flex no-underline" data-pjax="#repo-content-pjax-container" data-turbo-frame="repo-content-turbo-frame" href="/stnolting/neorv32/releases/tag/v1.11.2"> <svg aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-tag flex-shrink-0 mt-1 color-fg-success"> <path d="M1 7.775V2.75C1 1.784 1.784 1 2.75 1h5.025c.464 0 .91.184 1.238.513l6.25 6.25a1.75 1.75 0 0 1 0 2.474l-5.026 5.026a1.75 1.75 0 0 1-2.474 0l-6.25-6.25A1.752 1.752 0 0 1 1 7.775Zm1.5 0c0 .066.026.13.073.177l6.25 6.25a.25.25 0 0 0 .354 0l5.025-5.025a.25.25 0 0 0 0-.354l-6.25-6.25a.25.25 0 0 0-.177-.073H2.75a.25.25 0 0 0-.25.25ZM6 5a1 1 0 1 1 0 2 1 1 0 0 1 0-2Z"></path> </svg> <div class="ml-2 min-width-0"> <div class="d-flex"> <span class="css-truncate css-truncate-target text-bold mr-2" style="max-width: none;">v1.11.2</span> <span title="Label: Latest" data-view-component="true" class="Label Label--success flex-shrink-0"> Latest </span> </div> <div class="text-small color-fg-muted"><relative-time datetime="2025-03-15T20:59:39Z" class="no-wrap">Mar 15, 2025</relative-time></div> </div> </a> <div data-view-component="true" class="mt-3"> <a text="small" data-pjax="#repo-content-pjax-container" data-turbo-frame="repo-content-turbo-frame" href="/stnolting/neorv32/releases" data-view-component="true" class="Link">+ 43 releases</a></div> </div> </div> <div class="BorderGrid-row" hidden> <div class="BorderGrid-cell"> <include-fragment src="/stnolting/neorv32/used_by_list" accept="text/fragment+html"> </include-fragment> </div> </div> <div class="BorderGrid-row"> <div class="BorderGrid-cell"> <h2 class="h4 mb-3"> <a href="/stnolting/neorv32/graphs/contributors" data-view-component="true" class="Link--primary no-underline Link d-flex flex-items-center">Contributors <span title="49" data-view-component="true" class="Counter ml-1">49</span></a></h2> <ul class="list-style-none d-flex flex-wrap mb-n2"> <li class="mb-2 mr-2" > <a href="https://github.com/stnolting" class="" data-hovercard-type="user" data-hovercard-url="/users/stnolting/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/22944758?s=64&v=4" alt="@stnolting" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/umarcor" class="" data-hovercard-type="user" data-hovercard-url="/users/umarcor/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/38422348?s=64&v=4" alt="@umarcor" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/akaeba" class="" data-hovercard-type="user" data-hovercard-url="/users/akaeba/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/29815957?s=64&v=4" alt="@akaeba" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/LukasP46" class="" data-hovercard-type="user" data-hovercard-url="/users/LukasP46/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/9783727?s=64&v=4" alt="@LukasP46" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/zipotron" class="" data-hovercard-type="user" data-hovercard-url="/users/zipotron/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/6671137?s=64&v=4" alt="@zipotron" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/emb4fun" class="" data-hovercard-type="user" data-hovercard-url="/users/emb4fun/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/10170906?s=64&v=4" alt="@emb4fun" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/mikaelsky" class="" data-hovercard-type="user" data-hovercard-url="/users/mikaelsky/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/119539842?s=64&v=4" alt="@mikaelsky" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/NikLeberg" class="" data-hovercard-type="user" data-hovercard-url="/users/NikLeberg/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/39563554?s=64&v=4" alt="@NikLeberg" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/LarsAsplund" class="" data-hovercard-type="user" data-hovercard-url="/users/LarsAsplund/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/6681689?s=64&v=4" alt="@LarsAsplund" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/henrikbrixandersen" class="" data-hovercard-type="user" data-hovercard-url="/users/henrikbrixandersen/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/1076226?s=64&v=4" alt="@henrikbrixandersen" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/tmeissner" class="" data-hovercard-type="user" data-hovercard-url="/users/tmeissner/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/1034175?s=64&v=4" alt="@tmeissner" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/pepijndevos" class="" data-hovercard-type="user" data-hovercard-url="/users/pepijndevos/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/168609?s=64&v=4" alt="@pepijndevos" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/vivi202" class="" data-hovercard-type="user" data-hovercard-url="/users/vivi202/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/35976157?s=64&v=4" alt="@vivi202" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> <li class="mb-2 mr-2" > <a href="https://github.com/matty0005" class="" data-hovercard-type="user" data-hovercard-url="/users/matty0005/hovercard" data-octo-click="hovercard-link-click" data-octo-dimensions="link_type:self" > <img src="https://avatars.githubusercontent.com/u/24428467?s=64&v=4" alt="@matty0005" size="32" height="32" width="32" data-view-component="true" class="avatar circle" /> </a> </li> </ul> <div data-view-component="true" class="mt-3"> <a text="small" href="/stnolting/neorv32/graphs/contributors" data-view-component="true" class="Link--inTextBlock Link">+ 35 contributors</a></div> </div> </div> <div class="BorderGrid-row"> <div class="BorderGrid-cell"> <h2 class="h4 mb-3">Languages</h2> <div class="mb-2"> <span data-view-component="true" class="Progress"> <span style="background-color:#adb2cb !important;;width: 49.8%;" itemprop="keywords" data-view-component="true" class="Progress-item color-bg-success-emphasis"></span> <span style="background-color:#555555 !important;;width: 45.2%;" itemprop="keywords" data-view-component="true" class="Progress-item color-bg-success-emphasis"></span> <span style="background-color:#427819 !important;;width: 2.3%;" itemprop="keywords" data-view-component="true" class="Progress-item color-bg-success-emphasis"></span> <span style="background-color:#e4cc98 !important;;width: 1.0%;" itemprop="keywords" data-view-component="true" class="Progress-item color-bg-success-emphasis"></span> <span style="background-color:#ccc !important;;width: 0.6%;" itemprop="keywords" data-view-component="true" class="Progress-item color-bg-success-emphasis"></span> <span style="background-color:#6E4C13 !important;;width: 0.6%;" itemprop="keywords" data-view-component="true" class="Progress-item color-bg-success-emphasis"></span> <span style="background-color:#ededed !important;;width: 0.5%;" itemprop="keywords" data-view-component="true" class="Progress-item color-bg-success-emphasis"></span> </span></div> <ul class="list-style-none"> <li class="d-inline"> <a class="d-inline-flex flex-items-center flex-nowrap Link--secondary no-underline text-small mr-3" href="/stnolting/neorv32/search?l=vhdl" data-ga-click="Repository, language stats search click, location:repo overview"> <svg style="color:#adb2cb;" aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-dot-fill mr-2"> <path d="M8 4a4 4 0 1 1 0 8 4 4 0 0 1 0-8Z"></path> </svg> <span class="color-fg-default text-bold mr-1">VHDL</span> <span>49.8%</span> </a> </li> <li class="d-inline"> <a class="d-inline-flex flex-items-center flex-nowrap Link--secondary no-underline text-small mr-3" href="/stnolting/neorv32/search?l=c" data-ga-click="Repository, language stats search click, location:repo overview"> <svg style="color:#555555;" aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-dot-fill mr-2"> <path d="M8 4a4 4 0 1 1 0 8 4 4 0 0 1 0-8Z"></path> </svg> <span class="color-fg-default text-bold mr-1">C</span> <span>45.2%</span> </a> </li> <li class="d-inline"> <a class="d-inline-flex flex-items-center flex-nowrap Link--secondary no-underline text-small mr-3" href="/stnolting/neorv32/search?l=makefile" data-ga-click="Repository, language stats search click, location:repo overview"> <svg style="color:#427819;" aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-dot-fill mr-2"> <path d="M8 4a4 4 0 1 1 0 8 4 4 0 0 1 0-8Z"></path> </svg> <span class="color-fg-default text-bold mr-1">Makefile</span> <span>2.3%</span> </a> </li> <li class="d-inline"> <a class="d-inline-flex flex-items-center flex-nowrap Link--secondary no-underline text-small mr-3" href="/stnolting/neorv32/search?l=tcl" data-ga-click="Repository, language stats search click, location:repo overview"> <svg style="color:#e4cc98;" aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-dot-fill mr-2"> <path d="M8 4a4 4 0 1 1 0 8 4 4 0 0 1 0-8Z"></path> </svg> <span class="color-fg-default text-bold mr-1">Tcl</span> <span>1.0%</span> </a> </li> <li class="d-inline"> <a class="d-inline-flex flex-items-center flex-nowrap Link--secondary no-underline text-small mr-3" href="/stnolting/neorv32/search?l=linker-script" data-ga-click="Repository, language stats search click, location:repo overview"> <svg style="color:#ccc;" aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-dot-fill mr-2"> <path d="M8 4a4 4 0 1 1 0 8 4 4 0 0 1 0-8Z"></path> </svg> <span class="color-fg-default text-bold mr-1">Linker Script</span> <span>0.6%</span> </a> </li> <li class="d-inline"> <a class="d-inline-flex flex-items-center flex-nowrap Link--secondary no-underline text-small mr-3" href="/stnolting/neorv32/search?l=assembly" data-ga-click="Repository, language stats search click, location:repo overview"> <svg style="color:#6E4C13;" aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-dot-fill mr-2"> <path d="M8 4a4 4 0 1 1 0 8 4 4 0 0 1 0-8Z"></path> </svg> <span class="color-fg-default text-bold mr-1">Assembly</span> <span>0.6%</span> </a> </li> <li class="d-inline"> <span class="d-inline-flex flex-items-center flex-nowrap text-small mr-3"> <svg style="color:#ededed;" aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-dot-fill mr-2"> <path d="M8 4a4 4 0 1 1 0 8 4 4 0 0 1 0-8Z"></path> </svg> <span class="color-fg-default text-bold mr-1">Other</span> <span>0.5%</span> </span> </li> </ul> </div> </div> </div> </div> </div></div> </div> </div> </turbo-frame> </main> </div> </div> <footer class="footer pt-8 pb-6 f6 color-fg-muted p-responsive" role="contentinfo" > <h2 class='sr-only'>Footer</h2> <div class="d-flex flex-justify-center flex-items-center flex-column-reverse flex-lg-row flex-wrap flex-lg-nowrap"> <div class="d-flex flex-items-center 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