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class="clearfix "><div class="grve-content-wrapper"><div id="grve-main-content"><div class="grve-main-content-wrapper clearfix"><div id="page-569" class="post-569 page type-page status-publish hentry"><div class="grve-section grve-row-section grve-fullwidth-background grve-padding-top-1x grve-bg-none"><div class="grve-container"><div class="grve-row grve-bookmark grve-columns-gap-30"><div class="grve-column wpb_column grve-column-1" ><div class="grve-column-wrapper" ><div class="grve-row-inner grve-bookmark reverse-col-dsktp grve-padding-bottom-1x"><div class="grve-column-inner wpb_column grve-column-1-3 img-column right"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-image mw-270 grve-hover-item grve-hover-style-1 grve-full-image" style=""><div class="grve-image-wrapper"><figure class="grve-image-hover grve-media grve-zoom-none"><div class="grve-bg-dark grve-hover-overlay grve-opacity-0"></div><img fetchpriority="high" decoding="async" width="270" height="300" src="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-boris-murmann.jpg" class="" alt="Boris Murmann" srcset="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-boris-murmann.jpg 1x,https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-boris-murmann2x.jpg 2x" /><figcaption></figcaption></figure><div class="grve-content grve-align-center"><h4 class="grve-title grve-h5 grve-text-inherit">Boris Murmann</h4><span class="grve-description grve-link-text grve-text-content">Chair<br /> TC-OSE</span></div></div></div></div></div><div class="grve-column-inner wpb_column grve-column-2-3 txt-column left"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-text"><p><strong>Boris Murmann</strong> is a Professor of Electrical Engineering at Stanford University. He joined Stanford in 2004 after completing his Ph.D. degree in electrical engineering at the University of California, Berkeley in 2003. From 1994 to 1997, he was with Neutron Microelectronics, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. Since 2004, he has worked as a consultant with numerous Silicon Valley companies. Dr. Murmann’s research interests are in mixed-signal integrated circuit design, with special emphasis on sensor interfaces, data converters and custom circuits for embedded machine learning. In 2008, he was a co-recipient of the Best Student Paper Award at the VLSI Circuits Symposium and a recipient of the Best Invited Paper Award at the IEEE Custom Integrated Circuits Conference (CICC). He received the Agilent Early Career Professor Award in 2009 and the Friedrich Wilhelm Bessel Research Award in 2012. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits, an AdCom member and Distinguished Lecturer of the IEEE Solid-State Circuits Society, as well as the Data Converter Subcommittee Chair and the Technical Program Chair of the IEEE International Solid-State Circuits Conference (ISSCC). He is the founding faculty co-director of the Stanford SystemX Alliance and the faculty director of Stanford’s System Prototyping Facility (SPF). He is a Fellow of the IEEE.</p></div></div></div></div><div class="grve-row-inner grve-bookmark reverse-col-dsktp grve-padding-bottom-1x"><div class="grve-column-inner wpb_column grve-column-1-3 img-column right"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-image mw-270 grve-hover-item grve-hover-style-1 grve-full-image" style=""><div class="grve-image-wrapper"><figure class="grve-image-hover grve-media grve-zoom-none"><div class="grve-bg-dark grve-hover-overlay grve-opacity-0"></div><img decoding="async" width="2560" height="1707" src="https://sscs.ieee.org/wp-content/uploads/Matt-Venn-1-scaled.jpg" class="" alt="" srcset="https://sscs.ieee.org/wp-content/uploads/Matt-Venn-1-scaled.jpg 1x,https://sscs.ieee.org/wp-content/uploads/Matt-Venn-1-scaled.jpg 2x" /><figcaption></figcaption></figure><div class="grve-content grve-align-center"><h4 class="grve-title grve-h5 grve-text-inherit">Matthew Venn</h4></div></div></div></div></div><div class="grve-column-inner wpb_column grve-column-2-3 txt-column left"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-text"><div><strong>Matthew Venn</strong> is a science & technology communicator and electronic engineer. He received a degree in Electronic Engineering from Leeds, UK in 1999. He has had a varied career in industry with a combination of engineering and teaching jobs. He has been a central figure in the open source silicon movement over the last 3 years with his Zero to ASIC course and Tiny Tapeout initiative.</div><div class="gmail_default"><div class="gmail_default"><a href="https://www.zerotoasiccourse.com/" target="_blank" rel="noopener" data-saferedirecturl="https://www.google.com/url?q=https://www.zerotoasiccourse.com/&source=gmail&ust=1720797692211000&usg=AOvVaw2frXMq60dNyFLLdOyZprtn">https://www.zerotoasiccourse.<wbr />com/</a></div><div class="gmail_default"><a href="https://tinytapeout.com/" target="_blank" rel="noopener" data-saferedirecturl="https://www.google.com/url?q=https://tinytapeout.com/&source=gmail&ust=1720797692211000&usg=AOvVaw3mPj9i6dvJJ5G1cu1QTrII">https://tinytapeout.com/</a></div></div></div></div></div></div><div class="grve-row-inner grve-bookmark reverse-col-dsktp grve-padding-bottom-1x"><div class="grve-column-inner wpb_column grve-column-1-3 img-column right"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-image mw-270 grve-hover-item grve-hover-style-1 grve-full-image" style=""><div class="grve-image-wrapper"><figure class="grve-image-hover grve-media grve-zoom-none"><div class="grve-bg-dark grve-hover-overlay grve-opacity-0"></div><img decoding="async" width="270" height="300" src="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-ali-sabir.jpg" class="" alt="Ali Sabir" srcset="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-ali-sabir.jpg 1x,https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-ali-sabir2x.jpg 2x" /><figcaption></figcaption></figure><div class="grve-content grve-align-center"><h4 class="grve-title grve-h5 grve-text-inherit">Ali Sabir</h4></div></div></div></div></div><div class="grve-column-inner wpb_column grve-column-2-3 txt-column left"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-text"><p><strong>Ali Sabir</strong> received his BS degree in Electronics Engineering from University of Engineering and Technology, Pakistan in 2021 with highest distinction. Currently, he is pursuing his Master’s degree in Electrical Engineering (Specialization in Chip Design) from FAST-NUCES, Pakistan.</p><p>In 2021, he joined the ICD Lab at FAST-NUCES, Pakistan as an IC Design Engineer. He took part in the 2022 SSCS “PICO” Open-Source Chipathon where three of his projects were selected for tapeout. He also led the top-level integration team in one of the chips. He is also a member of TC-OSE Committee for 2023 SSCS “PICO” Open-Source Chipathon, his interest in the Digital and Mixed Signal IC Design.</p></div></div></div></div><div class="grve-row-inner grve-bookmark reverse-col-dsktp grve-padding-bottom-1x"><div class="grve-column-inner wpb_column grve-column-1-3 img-column right"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-image mw-270 grve-hover-item grve-hover-style-1 grve-full-image" style=""><div class="grve-image-wrapper"><figure class="grve-image-hover grve-media grve-zoom-none"><div class="grve-bg-dark grve-hover-overlay grve-opacity-0"></div><img loading="lazy" decoding="async" width="270" height="300" src="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-sadayuki-yoshitomi.jpg" class="" alt="Sadayuki Yoshitomi" srcset="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-sadayuki-yoshitomi.jpg 1x,https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-sadayuki-yoshitomi2x.jpg 2x" /><figcaption></figcaption></figure><div class="grve-content grve-align-center"><h4 class="grve-title grve-h5 grve-text-inherit">Sadayuki Yoshitomi</h4></div></div></div></div></div><div class="grve-column-inner wpb_column grve-column-2-3 txt-column left"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-text"><p><strong>Sadayuki Yoshitomi</strong>, Ph.D (IEEE member), joined TOSHIBA Research and Development Center, Kawasaki Kanagawa pref. Japan in 1993, where he is engaged in characterization and modeling of SiGe BiCMOS devices for RF applications. In 1999, he moved to the RF LSI design team of System LSI Division of TOSHIBA Corp, where he worked with the system design for GSM, Bluetooth applications. Since 2015, he is managing PDK development team for RF-CMOS application. He contributed PDK developments from 130nm to 40nm RF-CMOS as both manager and SPICE model engineer. From 2017 to 2022, he belonged to the memory division of TOSHIBA Corporation (currently named as KIOXIA corporation) as a chief specialist with the same role, where he contributed to the PDK developments of 3D Nand-Flash memory (BiCS) products. In 2022, he moved the ASIC design team of MegaChips corporation, Tokyo Japan, working with the highspeed ASIC design and next 5G system design. Dr.Sadayuki Yoshitomi is a subcommittee chair of BCICTS conference, TPC member of ESSDERC (EU), Mixdes (Poland) and IrPhe(Armenia) conferences, and working member of 79GHz license strategy working group of Japanese Interior Ministry.</p></div></div></div></div><div class="grve-row-inner grve-bookmark reverse-col-dsktp grve-padding-bottom-1x"><div class="grve-column-inner wpb_column grve-column-1-3 img-column right"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-image mw-270 grve-hover-item grve-hover-style-1 grve-full-image" style=""><div class="grve-image-wrapper"><figure class="grve-image-hover grve-media grve-zoom-none"><div class="grve-bg-dark grve-hover-overlay grve-opacity-0"></div><img loading="lazy" decoding="async" width="270" height="300" src="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-kwantae-kim.jpg" class="" alt="Kwantae Kim" srcset="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-kwantae-kim.jpg 1x,https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-kwantae-kim2x.jpg 2x" /><figcaption></figcaption></figure><div class="grve-content grve-align-center"><h4 class="grve-title grve-h5 grve-text-inherit">Kwantae Kim</h4></div></div></div></div></div><div class="grve-column-inner wpb_column grve-column-2-3 txt-column left"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-text"><p><strong>Kwantae Kim</strong> received the B.S., M.S., and Ph.D. degrees from the School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2015, 2017, and 2021, respectively. From 2015 to 2017, he was with the Healthrian R&D Center, Daejeon, where he designed bio-potential readout IC for mobile healthcare solutions. In 2020, he was a Visiting Student with the Institute of Neuroinformatics, University of Zürich and ETH Zürich, Zürich, Switzerland, where he has been a Post-Doctoral Researcher since 2021. His research interests include analog/mixed-signal ICs for time-domain processing, in-memory computing, bio-impedance sensor, and neuromorphic audio sensor.</p></div></div></div></div><div class="grve-row-inner grve-bookmark reverse-col-dsktp grve-padding-bottom-1x"><div class="grve-column-inner wpb_column grve-column-1-3 img-column right"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-image mw-270 grve-hover-item grve-hover-style-1 grve-full-image" style=""><div class="grve-image-wrapper"><figure class="grve-image-hover grve-media grve-zoom-none"><div class="grve-bg-dark grve-hover-overlay grve-opacity-0"></div><img loading="lazy" decoding="async" width="1280" height="720" src="https://sscs.ieee.org/wp-content/uploads/Mitch-Bailey.jpg" class="" alt="" srcset="https://sscs.ieee.org/wp-content/uploads/Mitch-Bailey.jpg 1x,https://sscs.ieee.org/wp-content/uploads/Mitch-Bailey.jpg 2x" /><figcaption></figcaption></figure><div class="grve-content grve-align-center"><h4 class="grve-title grve-h5 grve-text-inherit">Mitch Bailey</h4></div></div></div></div></div><div class="grve-column-inner wpb_column grve-column-2-3 txt-column left"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-text"><div class="gmail_default"><strong>David Mitchell</strong> “Mitch” Bailey graduated from The Ohio State University in 1988 with a BS degree in Computer and Information Science from the College of Engineering. Joining Hitachi ULSI Systems in 1991, he developed netlist format conversion programs while maintaining backend verification rule files. In 2000, he initiated the development of a groundbreaking reliability verification tool, which successfully flagged errors commonly missed by other tool flows. This tool was used on over 500 SOC and DRAM chips and eliminated the need for respins due to reliability errors.</div><p>In 2013, Mitch left Hitachi and rewrote the system, now known as CVC-RV (Circuit Validity Check – Reliability Verification), as open-source. As a consultant, he currently leverages CVC-RV for full-chip verification of SOC and DRAM designs. Additionally, Mitch collaborates with Efabless to facilitate full-chip device-level LVS verification using open source tools.</p><p>Mitch’s career has been marked by a commitment to advancing reliability verification methodologies and contributing to the open-source community.</p></div></div></div></div><div class="grve-row-inner grve-bookmark reverse-col-dsktp grve-padding-bottom-1x"><div class="grve-column-inner wpb_column grve-column-1-3 img-column right"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-image mw-270 grve-hover-item grve-hover-style-1 grve-full-image" style=""><div class="grve-image-wrapper"><figure class="grve-image-hover grve-media grve-zoom-none"><div class="grve-bg-dark grve-hover-overlay grve-opacity-0"></div><img loading="lazy" decoding="async" width="413" height="579" src="https://sscs.ieee.org/wp-content/uploads/Tim-Edwards.jpg" class="" alt="" srcset="https://sscs.ieee.org/wp-content/uploads/Tim-Edwards.jpg 1x,https://sscs.ieee.org/wp-content/uploads/Tim-Edwards.jpg 2x" /><figcaption></figcaption></figure><div class="grve-content grve-align-center"><h4 class="grve-title grve-h5 grve-text-inherit">Tim Edwards</h4></div></div></div></div></div><div class="grve-column-inner wpb_column grve-column-2-3 txt-column left"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-text"><p><strong>Tim Edwards</strong> is director of analog at Efabless corporation. He has been an advocate of open source hardware and the open source tools to create it since the early 1990s. He developes and maintains the EDA software magic, netgen, xcircuit, IRSIM, qflow, CACE, and others, and regularly contributes to open source EDA tool and open PDK development. He helped develop the first open-source PDK from SkyWater, the Efabless open MPW shuttle run, and the Efabless Caravel harness chip. He spends much of his time on Slack helping designers get their open source chip designs done.</p></div></div></div></div><div class="grve-row-inner grve-bookmark reverse-col-dsktp grve-padding-bottom-1x"><div class="grve-column-inner wpb_column grve-column-1-3 img-column right"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-image mw-270 grve-hover-item grve-hover-style-1 grve-full-image" style=""><div class="grve-image-wrapper"><figure class="grve-image-hover grve-media grve-zoom-none"><div class="grve-bg-dark grve-hover-overlay grve-opacity-0"></div><img loading="lazy" decoding="async" width="270" height="300" src="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-harald-pretl.jpg" class="" alt="Harald Pretl" srcset="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-harald-pretl.jpg 1x,https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-harald-pretl2x.jpg 2x" /><figcaption></figcaption></figure><div class="grve-content grve-align-center"><h4 class="grve-title grve-h5 grve-text-inherit">Harald Pretl</h4></div></div></div></div></div><div class="grve-column-inner wpb_column grve-column-2-3 txt-column left"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-text"><p style="font-weight: 400;"><strong>Harald Pretl</strong> (S’97-M’01-SM’08) was born in Linz, Austria, in 1972. He received a Dipl.-Ing. degree in electrical engineering from the Graz University of Technology, Austria, in 1997, and the Dr.techn. degree from the Johannes Kepler University (JKU) in Linz, Austria, in 2001, for his work on first-generation direct-conversion transceivers for 3G.</p><p style="font-weight: 400;">From 2000 to 2011, he worked at Infineon Technologies as Director and Senior Principal Engineer, and from 2011 to 2019 at Intel as Senior Principal Engineer and Chief RF Technologist, contributing to several generations of cellular RF transceivers and mobile communications platforms, spanning from 2G to 5G, as analog circuit designer, project lead and RF systems architect. Since 2015 he has been a full professor heading the Institute for Integrated Circuits (IIC) at the JKU, Linz, where he is leading the Energy-Efficient Analog Circuits & Systems Group. Harald is a co-lead of the LIT/SAL mmWave Lab and the lead developer of the IIC-OSIC-TOOLS, an open-source IC design environment.</p><p style="font-weight: 400;">Harald Pretl was a member of the technical program committee of the ISSCC in 2010-2012 and has published more than 80 papers at international conferences and journals in the area of RF transceivers and analog circuits, in addition to more than 25 issued or filed patents. His current research interests are focused on cellular transceivers, wireless sensor networks, micro-power RF SoC for medical applications, and mm-wave circuits for 6G and advanced radar, as well as open-source IC design. He is a co-recipient of first place in the 2015 MTT-S PAWR student paper competition, the 2019 ReSMiQ best paper award at the IEEE NEWCAS conference, the 2019 APMC student prize, and a 2021 ISCAS best paper award. He is also a co-recipient of the Intel Achievement Award in 2019. He is a member of the Austrian Electrotechnical Association (OVE), the Association for Electrical, Electronic & Information Technologies (VDE), and the Silicon Austria Labs Advisory Board.</p></div></div></div></div><div class="grve-row-inner grve-bookmark reverse-col-dsktp grve-padding-bottom-1x"><div class="grve-column-inner wpb_column grve-column-1-3 img-column right"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-image mw-270 grve-hover-item grve-hover-style-1 grve-full-image" style=""><div class="grve-image-wrapper"><figure class="grve-image-hover grve-media grve-zoom-none"><div class="grve-bg-dark grve-hover-overlay grve-opacity-0"></div><img loading="lazy" decoding="async" width="270" height="300" src="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-mehdi-saligane.jpg" class="" alt="Mehdi Saligane" srcset="https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-mehdi-saligane.jpg 1x,https://sscs.ieee.org/wp-content/uploads/tc-ose-committee-members-mehdi-saligane2x.jpg 2x" /><figcaption></figcaption></figure><div class="grve-content grve-align-center"><h4 class="grve-title grve-h5 grve-text-inherit">Mehdi Saligane</h4></div></div></div></div></div><div class="grve-column-inner wpb_column grve-column-2-3 txt-column left"><div class="grve-column-wrapper-inner grve-padding-top-2x"><div class="grve-element grve-text"><p style="font-weight: 400;"><strong>Mehdi Saligane</strong> is a Research Scientist in the Department of Electrical Engineering and Computer Science at the University of Michigan. He received his M.Sc. and Ph.D. degrees in electrical and computer engineering from the University of Grenoble and Aix-Marseille in 2011 and 2016, respectively. He worked at STMicroelectronics, in France, as a Research Engineer from 2010 to 2015, and after completing his Ph.D., he joined the Michigan Integrated Circuits Lab at the University of Michigan. Dr. Saligane’s current research interests are in low-power and energy-efficient IC design, with a focus on open-source EDA and analog and mixed-signal IC design automation. He currently serves as chair of the Analog Working Group, as a member of the Technical Steering Committee at CHIPS Alliance, and as a technical member of SSCS’ open source ecosystem.</p></div></div></div></div><div class="grve-row-inner grve-bookmark reverse-col-dsktp grve-padding-bottom-1x"><div class="grve-column-inner wpb_column grve-column-1-3 img-column right"><div class="grve-column-wrapper-inner grve-padding-top-2x"></div></div><div class="grve-column-inner wpb_column grve-column-2-3 txt-column left"><div class="grve-column-wrapper-inner grve-padding-top-2x"></div></div></div><div class="grve-row-inner grve-bookmark reverse-col-dsktp grve-padding-bottom-1x"><div class="grve-column-inner wpb_column grve-column-1-3 img-column right"><div class="grve-column-wrapper-inner grve-padding-top-2x"></div></div><div class="grve-column-inner wpb_column grve-column-2-3 txt-column left"><div class="grve-column-wrapper-inner grve-padding-top-2x"></div></div></div></div></div></div></div><div class="grve-background-wrapper"></div></div></div></div></div></div></div><footer id="grve-footer" data-sticky-footer="no" class="grve-border grve-bookmark"><div id="grve-bottom-bar" class="grve-bookmark"><div class="grve-section grve-row-section grve-fullwidth-background grve-padding-top-3x grve-padding-bottom-3x grve-bg-none bg-red-gradient" id="join-sscs"><div class="grve-container"><div class="grve-row grve-bookmark grve-columns-gap-30"><div class="grve-column wpb_column grve-column-1 grve-align-center" ><div class="grve-column-wrapper mw-770" ><h2 class="grve-element grve-title grve-align-center grve-subtitle-text" style=""><span>Join IEEE Solid-State Circuits Society</span></h2><div class="grve-element grve-text"><p>As a member of the IEEE SSCS Society, you will receive communications about networking opportunities, conferences, meetings, special events, exclusive content, and so much more.</p></div><div class="grve-element grve-align-center ieee-btn"><a href="https://www.ieee.org/membership-catalog/productdetail/showProductDetailPage.html?product=MEMSSC037" title="Learn More" class="grve-btn grve-btn-medium grve-extra-round grve-bg-white grve-bg-hover-primary-2"><span>Learn More</span></a></div></div></div></div></div><div class="grve-background-wrapper"></div></div></div><div class="grve-footer-wrapper"><div class="grve-widget-area"><div class="grve-container grve-padding-top-2x grve-padding-bottom-1x "><div class="grve-row grve-columns-gap-30"><div class="wpb_column grve-column grve-column-1-2 grve-tablet-column-1-2"><div class="grve-column-wrapper"><div id="media_image-2" class="grve-widget widget widget_media_image"><a href="/"><img width="476" height="128" src="https://sscs.ieee.org/wp-content/uploads/ieee-sscs-sm-ko-logo2x.png" class="image wp-image-1260 attachment-full size-full" alt="IEEE Solid-State Circuits Society logo" style="max-width: 100%; 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menu-item-type-post_type menu-item-object-page menu-item-3356"><a href="https://sscs.ieee.org/publications/ieee-journal-on-exploratory-solid-state-computational-devices-and-circuits-jcdc/jxcdc-submission/"><span class="grve-item">JXCDC Submission</span></a></li><li class="menu-item menu-item-type-post_type menu-item-object-page menu-item-3357"><a href="https://sscs.ieee.org/publications/ieee-journal-on-exploratory-solid-state-computational-devices-and-circuits-jcdc/jxcdc-associate-editors/"><span class="grve-item">JXCDC Associate Editors</span></a></li><li class="menu-item menu-item-type-post_type menu-item-object-page menu-item-3363"><a href="https://sscs.ieee.org/publications/ieee-journal-on-exploratory-solid-state-computational-devices-and-circuits-jcdc/jxcdc-steering-committee/"><span class="grve-item">JXCDC Steering Committee</span></a></li><li class="menu-item menu-item-type-post_type menu-item-object-page menu-item-3364"><a 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