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<li id="toc-Background_and_motivation" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Background_and_motivation"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>Background and motivation</span> </div> </a> <ul id="toc-Background_and_motivation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-PCI-X_1.0" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI-X_1.0"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2</span> <span>PCI-X 1.0</span> </div> </a> <ul id="toc-PCI-X_1.0-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-PCI-X_2.0" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#PCI-X_2.0"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.3</span> <span>PCI-X 2.0</span> </div> </a> <ul id="toc-PCI-X_2.0-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Technical_description" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Technical_description"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Technical description</span> </div> </a> <ul id="toc-Technical_description-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Versions" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Versions"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Versions</span> </div> </a> <ul id="toc-Versions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Mixing_of_32-bit_and_64-bit_PCI_cards_in_different_width_slots" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Mixing_of_32-bit_and_64-bit_PCI_cards_in_different_width_slots"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Mixing of 32-bit and 64-bit PCI cards in different width slots</span> </div> </a> <ul id="toc-Mixing_of_32-bit_and_64-bit_PCI_cards_in_different_width_slots-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Comparison_with_PCI-Express" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Comparison_with_PCI-Express"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Comparison with PCI-Express</span> </div> </a> <ul id="toc-Comparison_with_PCI-Express-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" 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class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">PCI-X</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 20 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-20" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">20 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/PCI-X" title="PCI-X – Czech" lang="cs" hreflang="cs" data-title="PCI-X" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/PCI-X" title="PCI-X – Estonian" lang="et" hreflang="et" data-title="PCI-X" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/PCI-X" title="PCI-X – Spanish" lang="es" hreflang="es" data-title="PCI-X" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eo mw-list-item"><a href="https://eo.wikipedia.org/wiki/PCI-X" title="PCI-X – Esperanto" lang="eo" hreflang="eo" data-title="PCI-X" data-language-autonym="Esperanto" data-language-local-name="Esperanto" class="interlanguage-link-target"><span>Esperanto</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/PCI-X" title="PCI-X – French" lang="fr" hreflang="fr" data-title="PCI-X" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/PCI-X" title="PCI-X – Korean" lang="ko" hreflang="ko" data-title="PCI-X" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/PCI-X" title="PCI-X – Croatian" lang="hr" hreflang="hr" data-title="PCI-X" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target"><span>Hrvatski</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/PCI-X" title="PCI-X – Italian" lang="it" hreflang="it" data-title="PCI-X" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/PCI-X" title="PCI-X – Dutch" lang="nl" hreflang="nl" data-title="PCI-X" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/PCI-X" title="PCI-X – Japanese" lang="ja" hreflang="ja" data-title="PCI-X" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/PCI-X" title="PCI-X – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="PCI-X" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-nn mw-list-item"><a href="https://nn.wikipedia.org/wiki/PCI-X" title="PCI-X – Norwegian Nynorsk" lang="nn" hreflang="nn" data-title="PCI-X" data-language-autonym="Norsk nynorsk" data-language-local-name="Norwegian Nynorsk" class="interlanguage-link-target"><span>Norsk nynorsk</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/PCI-X" title="PCI-X – Polish" lang="pl" hreflang="pl" data-title="PCI-X" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt badge-Q70893996 mw-list-item" title=""><a href="https://pt.wikipedia.org/wiki/PCI-X" title="PCI-X – Portuguese" lang="pt" hreflang="pt" data-title="PCI-X" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/PCI-X" title="PCI-X – Russian" lang="ru" hreflang="ru" data-title="PCI-X" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/PCI-X" title="PCI-X – Slovak" lang="sk" hreflang="sk" data-title="PCI-X" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/PCI-X" title="PCI-X – Finnish" lang="fi" hreflang="fi" data-title="PCI-X" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/PCI-X" title="PCI-X – Turkish" lang="tr" hreflang="tr" data-title="PCI-X" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/PCI-X" title="PCI-X – Ukrainian" lang="uk" hreflang="uk" data-title="PCI-X" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/PCI-X" title="PCI-X – Chinese" lang="zh" hreflang="zh" data-title="PCI-X" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q868561#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit 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div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> (PCI-E or PCIe).</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">"PCIX" redirects here. For the PC Unix port, see <a href="/wiki/Interactive_Systems_Corporation#PC/IX" title="Interactive Systems Corporation">Interactive Systems Corporation § PC/IX</a>.</div> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">PCI-X</caption><tbody><tr><td colspan="2" class="infobox-subheader">PCI Local Bus</td></tr><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:ZRAID_at_PCI-X_at_FSC_Primtrgy_TX200_S2.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/66/ZRAID_at_PCI-X_at_FSC_Primtrgy_TX200_S2.JPG/220px-ZRAID_at_PCI-X_at_FSC_Primtrgy_TX200_S2.JPG" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/66/ZRAID_at_PCI-X_at_FSC_Primtrgy_TX200_S2.JPG/330px-ZRAID_at_PCI-X_at_FSC_Primtrgy_TX200_S2.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/66/ZRAID_at_PCI-X_at_FSC_Primtrgy_TX200_S2.JPG/440px-ZRAID_at_PCI-X_at_FSC_Primtrgy_TX200_S2.JPG 2x" data-file-width="2816" data-file-height="2112" /></a></span><div class="infobox-caption">PCI-X motherboard, with one card installed.</div></td></tr><tr><th scope="row" class="infobox-label">Year created</th><td class="infobox-data">1998<span class="noprint">; 26 years ago</span><span style="display:none"> (<span class="bday dtstart published updated">1998</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Created by</th><td class="infobox-data"><a href="/wiki/IBM" title="IBM">IBM</a>, <a href="/wiki/Hewlett-Packard" title="Hewlett-Packard">HP</a>, and <a href="/wiki/Compaq" title="Compaq">Compaq</a></td></tr><tr><th scope="row" class="infobox-label">Superseded by</th><td class="infobox-data"><a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> (2004)</td></tr><tr><th scope="row" class="infobox-label">Width in bits</th><td class="infobox-data">64</td></tr><tr><th scope="row" class="infobox-label">Speed</th><td class="infobox-data">Half-duplex<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> 266–4266 MB/s</td></tr><tr><th scope="row" class="infobox-label">Style</th><td class="infobox-data"><a href="/wiki/Parallel_communication" title="Parallel communication">Parallel</a></td></tr><tr><th scope="row" class="infobox-label">Hotplugging interface</th><td class="infobox-data">Optional</td></tr></tbody></table> <p><b>PCI-X</b>, short for <b>Peripheral Component Interconnect eXtended</b>, is a <a href="/wiki/Computer_bus" class="mw-redirect" title="Computer bus">computer bus</a> and <a href="/wiki/Expansion_card" title="Expansion card">expansion card</a> standard that enhances the 32-bit <a href="/wiki/Conventional_PCI" class="mw-redirect" title="Conventional PCI">PCI</a> <a href="/wiki/Local_bus" title="Local bus">local bus</a> for higher <a href="/wiki/Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a> demanded mostly by <a href="/wiki/Server_(computing)" title="Server (computing)">servers</a> and <a href="/wiki/Workstations" class="mw-redirect" title="Workstations">workstations</a>. It uses a modified protocol to support higher <a href="/wiki/Clock_rate" title="Clock rate">clock speeds</a> (up to 133 MHz), but is otherwise similar in electrical implementation. PCI-X 2.0 added speeds up to 533 MHz,<sup id="cite_ref-PCIX2.0_2-0" class="reference"><a href="#cite_note-PCIX2.0-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 23">: 23 </span></sup> with a reduction in electrical signal levels. </p><p>The slot is physically a 3.3 V PCI slot, with the same size, location and pin assignments. The electrical specifications are compatible, but stricter. However, while most conventional PCI slots are the 85 mm long 32-bit version, most PCI-X devices use the 130 mm long 64-bit slot, to the point that 64-bit PCI connectors and PCI-X support are seen as synonymous. </p><p>PCI-X is specified for both <a href="/wiki/32-bit_computing" title="32-bit computing">32-</a> and <a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a> PCI connectors,<sup id="cite_ref-PCIX1.0a_3-0" class="reference"><a href="#cite_note-PCIX1.0a-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 14">: 14 </span></sup> and PCI-X 2.0 added a <a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a> variant for embedded applications.<sup id="cite_ref-PCIX2.0_2-1" class="reference"><a href="#cite_note-PCIX2.0-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 22">: 22 </span></sup> </p><p>PCI-X has been replaced in modern designs by the similar-sounding <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> (PCIe),<sup id="cite_ref-Andrews2010_4-0" class="reference"><a href="#cite_note-Andrews2010-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> with a different physical connector and a different electrical design, having one or more <a href="/wiki/Serial_communication" title="Serial communication">serial</a> lanes instead of a number of slower <a href="/wiki/Parallel_communication" title="Parallel communication">parallel</a> connections. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Background_and_motivation">Background and motivation</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=2" title="Edit section: Background and motivation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Dualportintelmtpro1000mtserveradapterspc.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/61/Dualportintelmtpro1000mtserveradapterspc.jpg/220px-Dualportintelmtpro1000mtserveradapterspc.jpg" decoding="async" width="220" height="147" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/61/Dualportintelmtpro1000mtserveradapterspc.jpg/330px-Dualportintelmtpro1000mtserveradapterspc.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/61/Dualportintelmtpro1000mtserveradapterspc.jpg/440px-Dualportintelmtpro1000mtserveradapterspc.jpg 2x" data-file-width="3493" data-file-height="2329" /></a><figcaption>A Dual Port <a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">Gigabit Ethernet</a> <a href="/wiki/Network_Card" class="mw-redirect" title="Network Card">Network Card</a> for single PCI-X slot to save on PCI-X slots and use the full potential of the PCI-X <a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a> bus.</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:LSI_Logic_MegaRAID_SATA_300-8X_SATA_RAID_controller.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/2a/LSI_Logic_MegaRAID_SATA_300-8X_SATA_RAID_controller.jpg/220px-LSI_Logic_MegaRAID_SATA_300-8X_SATA_RAID_controller.jpg" decoding="async" width="220" height="145" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/2a/LSI_Logic_MegaRAID_SATA_300-8X_SATA_RAID_controller.jpg/330px-LSI_Logic_MegaRAID_SATA_300-8X_SATA_RAID_controller.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/2a/LSI_Logic_MegaRAID_SATA_300-8X_SATA_RAID_controller.jpg/440px-LSI_Logic_MegaRAID_SATA_300-8X_SATA_RAID_controller.jpg 2x" data-file-width="3000" data-file-height="1982" /></a><figcaption>A 8 port <a href="/wiki/SATA" title="SATA">SATA</a> <a href="/wiki/Host_bus_adapter" class="mw-redirect" title="Host bus adapter">host bus adapter</a> for PCI-X from <a href="/wiki/Lsi_logic" class="mw-redirect" title="Lsi logic">Lsi logic</a>.</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:HP_VISUALIZE_fx10_Pro_(A1299-6503)_front.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/4f/HP_VISUALIZE_fx10_Pro_%28A1299-6503%29_front.jpg/220px-HP_VISUALIZE_fx10_Pro_%28A1299-6503%29_front.jpg" decoding="async" width="220" height="91" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/4f/HP_VISUALIZE_fx10_Pro_%28A1299-6503%29_front.jpg/330px-HP_VISUALIZE_fx10_Pro_%28A1299-6503%29_front.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/4f/HP_VISUALIZE_fx10_Pro_%28A1299-6503%29_front.jpg/440px-HP_VISUALIZE_fx10_Pro_%28A1299-6503%29_front.jpg 2x" data-file-width="12379" data-file-height="5140" /></a><figcaption>HP VISUALIZE fx10 Pro <a href="/wiki/Video_card" class="mw-redirect" title="Video card">video card</a> for PCI-X</figcaption></figure> <p>In PCI, a transaction that cannot be completed immediately is postponed by either the target or the initiator issuing retry-cycles, during which no other agents can use the PCI bus. Since PCI lacks a split-response mechanism to permit the target to return data at a later time, the bus remains occupied by the target issuing retry-cycles until the read data is ready. In PCI-X, after the master issues the request, it disconnects from the PCI bus, allowing other agents to use the bus. The split-response containing the requested data is generated only when the target is ready to return all of the requested data. Split-responses increase bus efficiency by eliminating retry-cycles, during which no data can be transferred across the bus. </p><p>PCI also suffered from the relative scarcity of unique interrupt lines. With only 4 interrupt pins (INT A/B/C/D), systems with many PCI devices require multiple functions to share an interrupt line, complicating host-side interrupt-handling. PCI-X added <a href="/wiki/Message_Signaled_Interrupts" title="Message Signaled Interrupts">Message Signaled Interrupts</a>, an interrupt system using writes to host-memory. In MSI-mode, the function's interrupt is not signaled by asserting an INTx line. Instead, the function performs a memory-write to a system-configured region in host-memory. Since the content and address are configured on a per-function basis, MSI-mode interrupts are dedicated instead of shared. A PCI-X system allows both MSI-mode interrupts and legacy INTx interrupts to be used simultaneously (though not by the same function). </p><p>The lack of registered I/Os limited PCI to a maximum frequency of 66 MHz. PCI-X I/Os are registered to the PCI clock, usually through means of a PLL to actively control I/O delay the bus pins. The improvement in setup time allows an increase in frequency to 133 MHz. </p><p>Some devices, most notably Gigabit Ethernet cards, SCSI controllers (Fibre Channel and Ultra320), and cluster interconnects could by themselves saturate the PCI bus's 133 MB/s bandwidth. Ports using a bus speed doubled to 66 MHz and a bus width doubled to 64 bits (with the pin count increased to 184 from 124), in combination or not, have been implemented. These extensions were loosely supported as optional parts of the PCI 2.x standards, but device compatibility beyond the basic 133 MB/s continued to be difficult. </p><p>Developers eventually used the combined 64-bit and 66-MHz extension as a foundation, and, anticipating future needs, established 66-MHz and 133-MHz variants with a maximum bandwidth of 532 MB/s and 1064 MB/s respectively. The joint result was submitted as PCI-X to the <a href="/wiki/PCI-SIG" title="PCI-SIG">PCI Special Interest Group</a> (<a href="/wiki/Special_Interest_Group" class="mw-redirect" title="Special Interest Group">Special Interest Group</a> of the <a href="/wiki/Association_for_Computing_Machinery" title="Association for Computing Machinery">Association for Computing Machinery</a>). Subsequent approval made it an <a href="/wiki/Open_standard" title="Open standard">open standard</a> adoptable by all computer developers. The PCI SIG controls technical support, training, and compliance testing for PCI-X. IBM, Intel, Microelectronics, and <a href="/wiki/Mylex" title="Mylex">Mylex</a> were to develop supporting chipsets. <a href="/wiki/3Com" title="3Com">3Com</a> and <a href="/wiki/Adaptec" title="Adaptec">Adaptec</a> were to develop compatible peripherals. To accelerate PCI-X adoption by the industry, Compaq offered PCI-X development tools at their Web site. </p> <div class="mw-heading mw-heading3"><h3 id="PCI-X_1.0">PCI-X 1.0</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=3" title="Edit section: PCI-X 1.0"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The PCI-X standard was developed jointly by <a href="/wiki/IBM" title="IBM">IBM</a>, <a href="/wiki/Hewlett-Packard" title="Hewlett-Packard">HP</a>, and <a href="/wiki/Compaq" title="Compaq">Compaq</a> and submitted for approval in 1998. It was an effort to codify proprietary <a href="/wiki/Server_(computing)" title="Server (computing)">server</a> extensions to the <a href="/wiki/PCI_local_bus" class="mw-redirect" title="PCI local bus">PCI local bus</a> to address several shortcomings in PCI, and increase performance of high bandwidth devices, such as Gigabit Ethernet, <a href="/wiki/Fibre_Channel" title="Fibre Channel">Fibre Channel</a>, and <a href="/wiki/SCSI" title="SCSI">Ultra3 SCSI</a> cards, and allow processors to be interconnected in <a href="/wiki/Computer_cluster" title="Computer cluster">clusters</a>. </p><p>Intel gave only a qualified welcome to PCI-X, stressing that the next generation bus would have to be a "fundamentally new architecture".<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> Without Intel's support, PCI-X failed to be adopted in PCs. According to Rick Merritt of the EE Times, "A falling-out between the PCI SIG and a key Intel interconnect designer who spearheaded development on the <a href="/wiki/Accelerated_Graphics_Port" title="Accelerated Graphics Port">Accelerated Graphics Port</a> caused Intel to pull out of the initial PCI-X effort".<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> The PCI-X interface was however briefly adopted by Apple, for the first few generations of the <a href="/wiki/Power_Macintosh_G5" class="mw-redirect" title="Power Macintosh G5">Power Macintosh G5</a>. </p><p>The first PCI-X products were manufactured in 1998, such as the Adaptec AHA-3950U2B dual Ultra2 Wide SCSI controller, however at that point the PCI-X connector was merely referred to as "64-bit ready PCI" on packaging, hinting at future <a href="/wiki/Forward_compatibility" title="Forward compatibility">forward compatibility</a>. Actual PCI-X branding only became standard later, likely coinciding with widespread availability of PCI-X equipped motherboards. When more details of PCI Express were released in August 2001, PCI SIG chairman Roger Tipley expressed his belief that "PCI-X is going to be in servers forever because it serves a certain level of functionality, and it may not be compelling to switch to 3GIO [PCI Express] for that functionality. We learned that from not being able to get rid of ISA. ISA hung around because of all of these systems that weren't high-volume parts." Tipley also announced that (at the time) the PCI SIG was planning to fold PCI Express and PCI-X 2.0 into a single work tentatively called PCI 3.0,<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> but that name was eventually used for a relatively minor revision of conventional PCI.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="PCI-X_2.0">PCI-X 2.0</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=4" title="Edit section: PCI-X 2.0"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 2003, the PCI SIG ratified PCI-X 2.0. It adds 266-MHz and 533-MHz variants, yielding roughly 2,132 MB/s and 4,266 MB/s throughput, respectively. PCI-X 2.0 makes additional protocol revisions that are designed to help system reliability and add <a href="/wiki/Error-correcting_code" class="mw-redirect" title="Error-correcting code">Error-correcting codes</a> to the bus to avoid re-sends.<sup id="cite_ref-PCI-SIG_9-0" class="reference"><a href="#cite_note-PCI-SIG-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> To deal with one of the most common complaints of the PCI-X form factor, the 184-pin connector, 16-bit ports were developed to allow PCI-X to be used in devices with tight space constraints. Similar to PCI-Express, PtP functions were added to allow for devices on the bus to talk to each other without burdening the <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> or bus controller. </p><p>Despite the various theoretical advantages of PCI-X 2.0 and its backward compatibility with PCI-X and PCI devices, it has not been implemented on a large scale (as of 2008<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=PCI-X&action=edit">[update]</a></sup>). This lack of implementation primarily is because hardware vendors have chosen to integrate <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> instead. </p><p><a href="/wiki/IBM" title="IBM">IBM</a> was one of the (few) vendors which provided PCI-X 2.0 (266 MHz) support in their <a href="/wiki/IBM_AS/400" title="IBM AS/400">System i5</a> Model 515, 520 and 525; IBM advertised these slots as suitable for <a href="/wiki/10_Gigabit_Ethernet" title="10 Gigabit Ethernet">10 Gigabit Ethernet</a> adapters, which they also provided.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Hewlett-Packard" title="Hewlett-Packard">HP</a> offered PCI-X 2.0 in some <a href="/wiki/ProLiant" title="ProLiant">ProLiant</a> and <a href="/wiki/HPE_Integrity_Servers" title="HPE Integrity Servers">Integrity</a> servers and offered dual-port 4 Gbit/s <a href="/wiki/Fibre_Channel" title="Fibre Channel">Fibre Channel</a> adapters, also operating at 266 MHz.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> <a href="/wiki/AMD" title="AMD">AMD</a> supported PCI-X 2.0 (266 MHz) via its 8132 <a href="/wiki/Hypertransport" class="mw-redirect" title="Hypertransport">Hypertransport</a> to PCI-X 2.0 tunnel chip.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-MuellerSoper2006_13-0" class="reference"><a href="#cite_note-MuellerSoper2006-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> <a href="/wiki/ServerWorks" title="ServerWorks">ServerWorks</a> was a vocal supporter of PCI-X 2.0<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> (to the detriment of the first generation PCI Express) particularly through its chief <a href="/w/index.php?title=Raju_Vegesna&action=edit&redlink=1" class="new" title="Raju Vegesna (page does not exist)">Raju Vegesna</a>,<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> who was however fired soon thereafter for roadmap disagreements with the Broadcom leadership.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </p><p>In 2003, <a href="/wiki/Dell" title="Dell">Dell</a> announced it would skip PCI-X 2.0 in favor of more rapid adoption of PCI Express solutions.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> As reported by <a href="/wiki/PC_Magazine" class="mw-redirect" title="PC Magazine">PC Magazine</a>, Intel began to sideline PCI-X in their 2004 roadmap, in favor of PCI Express, arguing that the latter had substantial advantages in terms of system latency and power consumption, more dramatically stated as avoiding "the 1,000-pin apocalypse" for their <a href="/wiki/Intel_Xeon_chipsets#NetBurst-based_Xeon_chipsets" class="mw-redirect" title="Intel Xeon chipsets">Tumwater</a> chipset.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Technical_description">Technical description</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=5" title="Edit section: Technical description"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>PCI-X revised the <a href="/wiki/Conventional_PCI" class="mw-redirect" title="Conventional PCI">conventional PCI</a> standard by doubling the maximum clock speed (from 66 MHz to 133 MHz)<sup id="cite_ref-PCI-SIG_9-1" class="reference"><a href="#cite_note-PCI-SIG-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> and hence the amount of data exchanged between the computer processor and peripherals. Conventional PCI supports up to <a href="/wiki/64-bit_computing" title="64-bit computing">64 bits</a> at 66 MHz (though anything above 32 bits at 33 MHz is seen only in high-end systems). The theoretical maximum amount of data exchanged between the processor and peripherals with PCI-X is 1.06 GB/s, compared to 133 MB/s with standard PCI. PCI-X also improves the fault tolerance of PCI, allowing, for example, faulty cards to be reinitialized or taken offline. </p><p>PCI-X is backward compatible to PCI in the sense that the entire bus falls back to PCI if any card on the bus does not support PCI-X. </p><p>The two most fundamental changes are: </p> <ul><li>The shortest time between a signal appearing on the PCI bus and a response to that signal occurring on the bus has been extended to 2 cycles, rather than 1. This allows much faster clock rates, but causes many protocol changes: <ul><li>The ability of the conventional PCI bus protocol to insert wait states on any cycle based on the IRDY# and TRDY# signals has been deleted; PCI-X only allows bursts to be interrupted at 128-byte boundaries.</li> <li>The initiator must deassert FRAME# <i>two</i> cycles before the end of the transaction.</li> <li>The initiator may not insert wait states. The target may, but only before any data is transferred, and wait states for writes are limited to multiples of 2 clock cycles.</li> <li>Likewise, the length of a burst is decided before it begins; it may not be halted on an arbitrary cycle using the FRAME# and STOP# signals.</li> <li>Subtractive decode DEVSEL# takes place two cycles after the "slow DEVSEL#" cycle rather than on the next cycle.</li></ul></li> <li>After the address phase (and before any device has responded with DEVSEL#), there is an additional 1-cycle "attribute phase", during which 36 additional bits (both AD and C/BE# lines are used) of information about the operation are transmitted. These include 16 bits of requester identification (PCI bus, device and function number), 12 bits of burst length, 5 bits of tag (for associating split transactions), and 3 bits of additional status.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Versions">Versions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=6" title="Edit section: Versions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure typeof="mw:File/Thumb"><a href="/wiki/File:PCI_Keying.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/15/PCI_Keying.svg/500px-PCI_Keying.svg.png" decoding="async" width="500" height="304" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/15/PCI_Keying.svg/750px-PCI_Keying.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/15/PCI_Keying.svg/1000px-PCI_Keying.svg.png 2x" data-file-width="1706" data-file-height="1037" /></a><figcaption>3.3 V and 5 V keying of 64-bit PCI cards (both PCI and PCI-X). While most 64-bit PCI-X cards are universal and are backward compatible with common 32-bit 5 V PCI slots, PCI-X slots are 3.3 V and will not accept 5 V-only PCI cards.</figcaption></figure> <p>Essentially all PCI-X cards or slots have a 64-bit implementation and vary as follows: </p> <ul><li>Cards <ul><li>66 MHz (added in Rev. 1.0)<sup id="cite_ref-PCI-SIG_9-2" class="reference"><a href="#cite_note-PCI-SIG-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup></li> <li>100 MHz (works in 133 MHz slots by forcing a downclock of the bus to 100 MHz)<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup></li> <li>133 MHz (added in Rev. 1.0)<sup id="cite_ref-PCI-SIG_9-3" class="reference"><a href="#cite_note-PCI-SIG-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup></li> <li>266 MHz (added in Rev. 2.0)<sup id="cite_ref-PCI-SIG_9-4" class="reference"><a href="#cite_note-PCI-SIG-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup></li> <li>533 MHz (added in Rev. 2.0)<sup id="cite_ref-PCI-SIG_9-5" class="reference"><a href="#cite_note-PCI-SIG-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup></li></ul></li> <li>Slots <ul><li>66 MHz (speed as 66 MHz 64-bit PCI, can be found on older servers)</li> <li>133 MHz (most common)</li> <li>266 MHz (rare on x86, main bus on IBM <a href="/wiki/IBM_System_p" title="IBM System p">pSeries</a> from the era)</li> <li>533 MHz (rare)</li></ul></li></ul> <div class="mw-heading mw-heading2"><h2 id="Mixing_of_32-bit_and_64-bit_PCI_cards_in_different_width_slots">Mixing of 32-bit and 64-bit PCI cards in different width slots</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=7" title="Edit section: Mixing of 32-bit and 64-bit PCI cards in different width slots"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCI-X_in_a_32-bit_slot.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/64/PCI-X_in_a_32-bit_slot.jpg/220px-PCI-X_in_a_32-bit_slot.jpg" decoding="async" width="220" height="69" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/64/PCI-X_in_a_32-bit_slot.jpg/330px-PCI-X_in_a_32-bit_slot.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/64/PCI-X_in_a_32-bit_slot.jpg/440px-PCI-X_in_a_32-bit_slot.jpg 2x" data-file-width="2816" data-file-height="885" /></a><figcaption>64-bit PCI-X card partially inserted in 32-bit PCI slot, showing compatibility</figcaption></figure> <p>Most 32-bit PCI cards will function properly in 64-bit PCI-X slots, but the bus speed will be limited to the clock frequency of the slowest card, an inherent limitation of PCI's shared bus topology. For example, when a PCI 2.3 66-MHz card is installed into a PCI-X bus capable of 133 MHz, the entire bus backplane will be limited to 66 MHz. To get around this limitation, many motherboards have multiple PCI/PCI-X buses, with one bus intended for use with high-speed PCI-X peripherals, and the other bus intended for general-purpose peripherals. </p><p>Many 64-bit PCI-X cards are designed to work in 32-bit mode if inserted in shorter 32-bit connectors, with some loss of speed.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> An example of this is the Adaptec 29160 64-bit <a href="/wiki/SCSI" title="SCSI">SCSI</a> interface card.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> However some 64-bit PCI-X cards do not work in standard 32-bit PCI slots.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup><sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Reliable_sources" title="Wikipedia:Reliable sources"><span title="The material near this tag may rely on an unreliable source. (July 2012)">unreliable source?</span></a></i>]</sup> Even if it would work, installing a 64-bit PCI-X card in a 32-bit slot will leave the 64-bit portion of the card edge connector not connected and overhanging, which requires that there be no motherboard components positioned so as to mechanically obstruct the overhanging portion of the card edge connector. </p> <div class="mw-heading mw-heading2"><h2 id="Comparison_with_PCI-Express">Comparison with PCI-Express</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=8" title="Edit section: Comparison with PCI-Express"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:MOTU_PCIX-424_7825.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e0/MOTU_PCIX-424_7825.jpg/220px-MOTU_PCIX-424_7825.jpg" decoding="async" width="220" height="169" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e0/MOTU_PCIX-424_7825.jpg/330px-MOTU_PCIX-424_7825.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e0/MOTU_PCIX-424_7825.jpg/440px-MOTU_PCIX-424_7825.jpg 2x" data-file-width="3000" data-file-height="2305" /></a><figcaption>A MOTU PCIX-424 audio interface card, which was also released in standard PCI and PCIe variations.</figcaption></figure> <p>PCI-X should not be confused with the similar-sounding but incompatible <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a>, commonly abbreviated as PCI-E or PCIe. While both are high-speed computer buses for internal peripherals, they differ in looks and technology. PCI-X is a 64-bit parallel interface, backward compatible with 32-bit PCI. PCIe is a serial point-to-point connection with a different physical interface that was designed to supersede both PCI and PCI-X. </p><p>PCI-X and standard PCI buses may run on a PCIe bridge, similar to the way <a href="/wiki/Industry_Standard_Architecture" title="Industry Standard Architecture">ISA</a> buses ran on standard PCI buses in some computers. PCIe also matches PCI-X and even PCI-X 2.0 in maximum bandwidth. PCIe 1.0 x1 offers 250 MB/s in each direction (lane), and up to 16 lanes (x16) are currently supported each direction, in <a href="/wiki/Full-duplex#Full-duplex" class="mw-redirect" title="Full-duplex">full-duplex</a>, giving a maximum of 4 GB/s bandwidth in each direction. PCI-X 2.0 offers (at its maximum 64-bit 533-MHz variant) a maximum bandwidth of 4,266 MB/s (≈4.3 GB/s), although only in <a href="/wiki/Half-duplex" class="mw-redirect" title="Half-duplex">half-duplex</a>. </p><p>PCI-X has technological and economical disadvantages compared to PCI Express. The 64-bit parallel interface requires difficult trace routing, because, as with all parallel interfaces, the signals from the bus must arrive simultaneously or within a very short window, and noise from adjacent slots may cause interference. The serial interface of PCIe suffers fewer such problems and therefore does not require such complex and expensive designs. PCI-X buses, like standard PCI, are <a href="/wiki/Half-duplex" class="mw-redirect" title="Half-duplex">half-duplex</a> bidirectional, whereas PCIe buses are <a href="/wiki/Full-duplex" class="mw-redirect" title="Full-duplex">full-duplex</a> bidirectional. PCI-X buses run only as fast as the slowest device, whereas PCIe devices are able to independently negotiate the bus speed. Also, PCI-X slots are longer than PCIe 1x through PCIe 16x, which makes it impossible to make short cards for PCI-X. PCI-X slots take quite a bit of space on motherboards, which can be a problem for <a href="/wiki/ATX" title="ATX">ATX</a> and smaller <a href="/wiki/Motherboard_form_factor" title="Motherboard form factor">form factors</a>. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=9" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239009302">.mw-parser-output .portalbox{padding:0;margin:0.5em 0;display:table;box-sizing:border-box;max-width:175px;list-style:none}.mw-parser-output .portalborder{border:1px solid var(--border-color-base,#a2a9b1);padding:0.1em;background:var(--background-color-neutral-subtle,#f8f9fa)}.mw-parser-output .portalbox-entry{display:table-row;font-size:85%;line-height:110%;height:1.9em;font-style:italic;font-weight:bold}.mw-parser-output .portalbox-image{display:table-cell;padding:0.2em;vertical-align:middle;text-align:center}.mw-parser-output .portalbox-link{display:table-cell;padding:0.2em 0.2em 0.2em 0.3em;vertical-align:middle}@media(min-width:720px){.mw-parser-output .portalleft{clear:left;float:left;margin:0.5em 1em 0.5em 0}.mw-parser-output .portalright{clear:right;float:right;margin:0.5em 0 0.5em 1em}}</style><ul role="navigation" aria-label="Portals" class="noprint portalbox portalborder portalright"> <li class="portalbox-entry"><span class="portalbox-image"><span class="noviewer" typeof="mw:File"><a href="/wiki/File:Nuvola_apps_ksim.png" class="mw-file-description"><img alt="icon" src="//upload.wikimedia.org/wikipedia/commons/thumb/8/8d/Nuvola_apps_ksim.png/28px-Nuvola_apps_ksim.png" decoding="async" width="28" height="28" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/8d/Nuvola_apps_ksim.png/42px-Nuvola_apps_ksim.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/8d/Nuvola_apps_ksim.png/56px-Nuvola_apps_ksim.png 2x" data-file-width="128" data-file-height="128" /></a></span></span><span class="portalbox-link"><a href="/wiki/Portal:Electronics" title="Portal:Electronics">Electronics portal</a></span></li></ul> <ul><li><a href="/wiki/PCI_configuration_space" title="PCI configuration space">PCI configuration space</a></li> <li><a href="/wiki/List_of_interface_bit_rates" title="List of interface bit rates">List of interface bit rates</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=10" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.pearsonitcertification.com/articles/article.aspx?p=2731934&seqNum=24">"PCIe (Peripheral Component Interconnect Express) | On the Motherboard | Pearson IT Certification"</a>. <i>www.pearsonitcertification.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2020-09-25</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.pearsonitcertification.com&rft.atitle=PCIe+%28Peripheral+Component+Interconnect+Express%29+%7C+On+the+Motherboard+%7C+Pearson+IT+Certification&rft_id=https%3A%2F%2Fwww.pearsonitcertification.com%2Farticles%2Farticle.aspx%3Fp%3D2731934%26seqNum%3D24&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-PCIX2.0-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-PCIX2.0_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-PCIX2.0_2-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs1"><i>PCI-X Protocol Addendum to the PCI Local Bus Specification</i>. Revision 2.0. PCI Special Interest Group. 29 July 2002.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=PCI-X+Protocol+Addendum+to+the+PCI+Local+Bus+Specification&rft.series=Revision+2.0&rft.pub=PCI+Special+Interest+Group&rft.date=2002-07-29&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-PCIX1.0a-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-PCIX1.0a_3-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs1"><i>PCI-X Addendum to the PCI Local Bus Specification</i>. Revision 1.0a. PCI Special Interest Group. 24 July 2000.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=PCI-X+Addendum+to+the+PCI+Local+Bus+Specification&rft.series=Revision+1.0a&rft.pub=PCI+Special+Interest+Group&rft.date=2000-07-24&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-Andrews2010-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-Andrews2010_4-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJean_Andrews2010" class="citation book cs1">Jean Andrews (2010). <span class="id-lock-registration" title="Free registration required"><a rel="nofollow" class="external text" href="https://archive.org/details/labmanualtoaccom07edandr"><i>A+ Guide to Managing and Maintaining Your PC</i></a></span>. Cengage Learning. p. <a rel="nofollow" class="external text" href="https://archive.org/details/labmanualtoaccom07edandr/page/187">187</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4354-9778-8" title="Special:BookSources/978-1-4354-9778-8"><bdi>978-1-4354-9778-8</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=A%2B+Guide+to+Managing+and+Maintaining+Your+PC&rft.pages=187&rft.pub=Cengage+Learning&rft.date=2010&rft.isbn=978-1-4354-9778-8&rft.au=Jean+Andrews&rft_id=https%3A%2F%2Farchive.org%2Fdetails%2Flabmanualtoaccom07edandr&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLettice1999" class="citation news cs1">Lettice, John (1999-01-13). <a rel="nofollow" class="external text" href="https://www.theregister.co.uk/1999/01/13/pcix_gang_of_three_challenges/">"PCI-X Gang of Three challenges Intel with Future I/O"</a>. <i>The Register</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=The+Register&rft.atitle=PCI-X+Gang+of+Three+challenges+Intel+with+Future+I%2FO&rft.date=1999-01-13&rft.aulast=Lettice&rft.aufirst=John&rft_id=https%3A%2F%2Fwww.theregister.co.uk%2F1999%2F01%2F13%2Fpcix_gang_of_three_challenges%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMerritt2001" class="citation news cs1">Merritt, Rick (2001-11-21). <a rel="nofollow" class="external text" href="http://www.eetimes.com/document.asp?doc_id=1204479">"Servers gas up with 4-Gbyte/s PCI-X 2.0 spec"</a>. <i>EE Times</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=EE+Times&rft.atitle=Servers+gas+up+with+4-Gbyte%2Fs+PCI-X+2.0+spec&rft.date=2001-11-21&rft.aulast=Merritt&rft.aufirst=Rick&rft_id=http%3A%2F%2Fwww.eetimes.com%2Fdocument.asp%3Fdoc_id%3D1204479&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text">Jerry Ascierto (8/30/2001) "<a rel="nofollow" class="external text" href="http://www.eetimes.com/document.asp?doc_id=1228264">Intel details next-generation I/O spec</a>", <i>EE Times</i></span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140211033021/http://www.pcisig.com/news_room/faqs/faq_pci30/pci30_faq.pdf">"Archived copy"</a> <span class="cs1-format">(PDF)</span>. Archived from <a rel="nofollow" class="external text" href="http://www.pcisig.com/news_room/faqs/faq_pci30/pci30_faq.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2014-02-11<span class="reference-accessdate">. Retrieved <span class="nowrap">2013-12-16</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Archived+copy&rft_id=http%3A%2F%2Fwww.pcisig.com%2Fnews_room%2Ffaqs%2Ffaq_pci30%2Fpci30_faq.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: archived copy as title (<a href="/wiki/Category:CS1_maint:_archived_copy_as_title" title="Category:CS1 maint: archived copy as title">link</a>)</span></span> </li> <li id="cite_note-PCI-SIG-9"><span class="mw-cite-backlink">^ <a href="#cite_ref-PCI-SIG_9-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-PCI-SIG_9-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-PCI-SIG_9-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-PCI-SIG_9-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-PCI-SIG_9-4"><sup><i><b>e</b></i></sup></a> <a href="#cite_ref-PCI-SIG_9-5"><sup><i><b>f</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20080215215940/http://www.pcisig.com/news_room/faqs/faq_20/">"PCI-SIG — FAQ — PCI-X 2.0"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.pcisig.com/news_room/faqs/faq_20/">the original</a> on 2008-02-15<span class="reference-accessdate">. Retrieved <span class="nowrap">2008-02-17</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI-SIG+%E2%80%94+FAQ+%E2%80%94+PCI-X+2.0&rft_id=http%3A%2F%2Fwww.pcisig.com%2Fnews_room%2Ffaqs%2Ffaq_20%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.redbooks.ibm.com/redpapers/pdfs/redp4011.pdf">"PCI, PCI-X, PCI-X DDR, and PCIe Placement Rules for IBM System i Models"</a> <span class="cs1-format">(PDF)</span>. p. 7. <q>A third generation of PCI is now offered with the introduction of the 1.9 GHz System i5 Models 515, 520, and 525. These models have a PCI-X DDR (PCI-X 2.0) slot that runs at a maximum of 266 MHz and supports only adapters that can run without an IOP. This slot is ideally suited for ultra-high bandwidth adapters such as the new 266 MHz (DDR) #5721/#5722 10 Gb Ethernet adapters.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI%2C+PCI-X%2C+PCI-X+DDR%2C+and+PCIe+Placement+Rules+for+IBM+System+i+Models&rft.pages=7&rft_id=http%3A%2F%2Fwww.redbooks.ibm.com%2Fredpapers%2Fpdfs%2Fredp4011.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131216060927/http://h18004.www1.hp.com/products/quickspecs/12481_na/12481_na.PDF">"HP FC2243 Dual Channel 4Gb PCI-X 2.0 HBA"</a> <span class="cs1-format">(PDF)</span>. Archived from <a rel="nofollow" class="external text" href="http://h18004.www1.hp.com/products/quickspecs/12481_na/12481_na.PDF">the original</a> <span class="cs1-format">(PDF)</span> on 2013-12-16<span class="reference-accessdate">. Retrieved <span class="nowrap">2013-12-16</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=HP+FC2243+Dual+Channel+4Gb+PCI-X+2.0+HBA&rft_id=http%3A%2F%2Fh18004.www1.hp.com%2Fproducts%2Fquickspecs%2F12481_na%2F12481_na.PDF&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131216104651/http://www.theinquirer.net/inquirer/news/1016137/amd-rolls-out-8132-pci-x-tunnel-part">"AMD rolls out 8132 PCI-X tunnel part"</a>. The Inquirer. 2004-06-14. Archived from the original on December 16, 2013<span class="reference-accessdate">. Retrieved <span class="nowrap">2014-02-13</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+rolls+out+8132+PCI-X+tunnel+part&rft.pub=The+Inquirer&rft.date=2004-06-14&rft_id=http%3A%2F%2Fwww.theinquirer.net%2Finquirer%2Fnews%2F1016137%2Famd-rolls-out-8132-pci-x-tunnel-part&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: unfit URL (<a href="/wiki/Category:CS1_maint:_unfit_URL" title="Category:CS1 maint: unfit URL">link</a>)</span></span> </li> <li id="cite_note-MuellerSoper2006-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-MuellerSoper2006_13-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFScott_M._MuellerMark_Edward_SoperBarrie_Sosinsky2006" class="citation book cs1">Scott M. Mueller; Mark Edward Soper; Barrie Sosinsky (2006). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=9cLFf_1PBnkC&pg=PT366"><i>Upgrading and Repairing Servers</i></a>. Pearson Education. p. 366. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-13-279698-9" title="Special:BookSources/978-0-13-279698-9"><bdi>978-0-13-279698-9</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Upgrading+and+Repairing+Servers&rft.pages=366&rft.pub=Pearson+Education&rft.date=2006&rft.isbn=978-0-13-279698-9&rft.au=Scott+M.+Mueller&rft.au=Mark+Edward+Soper&rft.au=Barrie+Sosinsky&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3D9cLFf_1PBnkC%26pg%3DPT366&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-14">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20030718015904/http://serverworks.com/technology/pdf/PCI-X_2-0_WhitePaper.pdf">"Archived copy"</a> <span class="cs1-format">(PDF)</span>. <i>serverworks.com</i>. Archived from <a rel="nofollow" class="external text" href="http://serverworks.com/technology/pdf/PCI-X_2-0_WhitePaper.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 18 July 2003<span class="reference-accessdate">. Retrieved <span class="nowrap">12 January</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=serverworks.com&rft.atitle=Archived+copy&rft_id=http%3A%2F%2Fserverworks.com%2Ftechnology%2Fpdf%2FPCI-X_2-0_WhitePaper.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: archived copy as title (<a href="/wiki/Category:CS1_maint:_archived_copy_as_title" title="Category:CS1 maint: archived copy as title">link</a>)</span></span> </li> <li id="cite_note-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-15">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.eetimes.com/document.asp?doc_id=1144859">ServerWorks chief spurns first-generation PCI Express</a></span> </li> <li id="cite_note-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-16">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://news.cnet.com/Broadcom-ousts-ServerWorks-chief/2100-1006_3-994245.html">Broadcom ousts ServerWorks chief</a></span> </li> <li id="cite_note-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-17">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://news.cnet.com/2100-1010-992769.html">PCI-X marks the spot for IBM, HP</a></span> </li> <li id="cite_note-18"><span class="mw-cite-backlink"><b><a href="#cite_ref-18">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160304075654/https://www.pcmag.com/article2/0,2817,909447,00.asp">Intel Begins Making Its Case Against PCI-X</a></span> </li> <li id="cite_note-19"><span class="mw-cite-backlink"><b><a href="#cite_ref-19">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20050225092337/http://www.it-enquirer.com/main/ite/more/pci_xpci_express/">"PCI-X vs. PCI-Express"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.it-enquirer.com/main/ite/more/pci_xpci_express/">the original</a> on February 25, 2005<span class="reference-accessdate">. Retrieved <span class="nowrap">September 2,</span> 2016</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PCI-X+vs.+PCI-Express&rft_id=http%3A%2F%2Fwww.it-enquirer.com%2Fmain%2Fite%2Fmore%2Fpci_xpci_express%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-20"><span class="mw-cite-backlink"><b><a href="#cite_ref-20">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFZNYX_Networks2009" class="citation web cs1">ZNYX Networks (June 16, 2009). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110502042329/http://docs.znyx.com/products/hardware/zx370.htm">"ZX370 Series"</a>. Archived from <a rel="nofollow" class="external text" href="http://docs.znyx.com/products/hardware/zx370.htm">the original</a> on May 2, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">July 13,</span> 2012</span>. <q>The ZX370 Series is a true 64-bit adapter, widening the network pipeline to achieve higher throughput, while offering backward compatibility with standard 32-bit PCI slots.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=ZX370+Series&rft.date=2009-06-16&rft.au=ZNYX+Networks&rft_id=http%3A%2F%2Fdocs.znyx.com%2Fproducts%2Fhardware%2Fzx370.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-21">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFZNYX_Networks" class="citation web cs1">ZNYX Networks. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130720174917/http://docs.znyx.com/products/pdf/ZX370_Datasheet_02_web.pdf">"ZX370 Series Multi-Channel PCI Fast Ethernet Adapter"</a> <span class="cs1-format">(PDF)</span>. Archived from <a rel="nofollow" class="external text" href="http://docs.znyx.com/products/pdf/ZX370_Datasheet_02_web.pdf">the original</a> <span class="cs1-format">(PDF)</span> on July 20, 2013<span class="reference-accessdate">. Retrieved <span class="nowrap">July 13,</span> 2012</span>. <q>Backward compatible with 32 bit, 33 MHz PCI slots</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=ZX370+Series+Multi-Channel+PCI+Fast+Ethernet+Adapter&rft.au=ZNYX+Networks&rft_id=http%3A%2F%2Fdocs.znyx.com%2Fproducts%2Fpdf%2FZX370_Datasheet_02_web.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-22"><span class="mw-cite-backlink"><b><a href="#cite_ref-22">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAdaptec2000" class="citation web cs1">Adaptec (January 2000). <a rel="nofollow" class="external text" href="http://www.adaptec.com/en-us/support/scsi/u160/asc-29160/_docs/29160_users_reference_pdf.htm?nc=/en-us/support/scsi/u160/asc-29160/_docs/29160_users_reference_pdf.htm">"Adaptec SCSI Card 29160 Ultra160 SCSI Controller User's Reference"</a> <span class="cs1-format">(PDF)</span>. p. 1<span class="reference-accessdate">. Retrieved <span class="nowrap">July 13,</span> 2012</span>. <q>Although the Adaptec SCSI Card 29160 is a 64-bit PCI card, it also works in a 32-bit PCI slot. When installed in a 32-bit PCI slot, the card automatically runs in the slower 32-bit mode.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Adaptec+SCSI+Card+29160+Ultra160+SCSI+Controller+User%27s+Reference&rft.pages=1&rft.date=2000-01&rft.au=Adaptec&rft_id=http%3A%2F%2Fwww.adaptec.com%2Fen-us%2Fsupport%2Fscsi%2Fu160%2Fasc-29160%2F_docs%2F29160_users_reference_pdf.htm%3Fnc%3D%2Fen-us%2Fsupport%2Fscsi%2Fu160%2Fasc-29160%2F_docs%2F29160_users_reference_pdf.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> <li id="cite_note-23"><span class="mw-cite-backlink"><b><a href="#cite_ref-23">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLaCie" class="citation web cs1">LaCie. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120404080344/http://www.lacie.com/support/support_manifest.htm?id=10525&article=1164">"LaCie support: Identify a variety of PCI slots"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.lacie.com/support/support_manifest.htm?id=10525&article=1164">the original</a> on April 4, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">July 13,</span> 2012</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=LaCie+support%3A+Identify+a+variety+of+PCI+slots&rft.au=LaCie&rft_id=http%3A%2F%2Fwww.lacie.com%2Fsupport%2Fsupport_manifest.htm%3Fid%3D10525%26article%3D1164&rfr_id=info%3Asid%2Fen.wikipedia.org%3APCI-X" class="Z3988"></span></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=11" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><i>PCI Bus Demystified</i>; 2nd Ed; Doug Abbott; 250 pages; 2004; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-7506-7739-4" title="Special:BookSources/978-0-7506-7739-4">978-0-7506-7739-4</a>.</li> <li><i>PCI-X System Architecture</i>; 1st Ed; Tom Shanley; 752 pages; 2000; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-201-72682-4" title="Special:BookSources/978-0-201-72682-4">978-0-201-72682-4</a>.</li> <li><i>PCI & PCI-X Hardware and Software Architecture & Design</i>; 5th Ed; Ed Solari; 1140 pages; 2001; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-929392-63-9" title="Special:BookSources/978-0-929392-63-9">978-0-929392-63-9</a>.</li> <li>Ray Weiss, (6/9/2000) "<a rel="nofollow" class="external text" href="http://www.eetimes.com/document.asp?doc_id=1255127">PCI-X Exposed</a>", <i><a href="/wiki/EE_Times" title="EE Times">EE Times</a></i></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=PCI-X&action=edit&section=12" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://hsi.web.cern.ch/HSI/s-link/devices/s32pci64/slottypes.html">Good diagrams and text on how to recognize the difference between 5 volt and 3.3 volt PCI (and PCI-X) slots.</a></li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist 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navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Computer_bus" title="Template:Computer bus"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Computer_bus" title="Template talk:Computer bus"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Computer_bus" title="Special:EditPage/Template:Computer bus"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Technical_and_de_facto_standards_for_wired_computer_buses" style="font-size:114%;margin:0 4em"><a href="/wiki/Technical_standard" title="Technical standard">Technical</a> and <a href="/wiki/De_facto_standard" title="De facto standard"><i>de facto</i> standards</a> for <a href="/wiki/Wired_communication" title="Wired communication">wired</a> <a href="/wiki/Bus_(computing)" title="Bus (computing)">computer buses</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">General</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_bus" title="System bus">System bus</a></li> <li><a href="/wiki/Front-side_bus" title="Front-side bus">Front-side bus</a></li> <li><a href="/wiki/Back-side_bus" title="Back-side bus">Back-side bus</a></li> <li><a href="/wiki/Daisy_chain_(electrical_engineering)" title="Daisy chain (electrical engineering)">Daisy chain</a></li> <li><a href="/wiki/Control_bus" title="Control bus">Control bus</a></li> <li><a href="/wiki/Address_bus" class="mw-redirect" title="Address bus">Address bus</a></li> <li><a href="/wiki/Bus_contention" title="Bus contention">Bus contention</a></li> <li><a href="/wiki/Bus_mastering" title="Bus mastering">Bus mastering</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a></li> <li><a href="/wiki/Plug_and_play" title="Plug and play">Plug and play</a></li> <li><a href="/wiki/List_of_interface_bit_rates#Computer_buses" title="List of interface bit rates">List of bus bandwidths</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Standards</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/SS-50_bus" title="SS-50 bus">SS-50 bus</a></li> <li><a href="/wiki/S-100_bus" title="S-100 bus">S-100 bus</a></li> <li><a href="/wiki/Multibus" title="Multibus">Multibus</a></li> <li><a href="/wiki/Unibus" title="Unibus">Unibus</a></li> <li><a href="/wiki/VAXBI_bus" title="VAXBI bus">VAXBI</a></li> <li><a href="/wiki/MBus_(SPARC)" title="MBus (SPARC)">MBus</a></li> <li><a href="/wiki/STD_Bus" title="STD Bus">STD Bus</a></li> <li><a href="/wiki/System_Management_Bus" title="System Management Bus">SMBus</a></li> <li><a href="/wiki/Q-Bus" title="Q-Bus">Q-Bus</a></li> <li><a href="/wiki/Europe_Card_Bus" title="Europe Card Bus">Europe Card Bus</a></li> <li><a href="/wiki/Industry_Standard_Architecture" title="Industry Standard Architecture">ISA</a></li> <li><a href="/wiki/STEbus" title="STEbus">STEbus</a></li> <li><a href="/wiki/Amiga_Zorro_II" title="Amiga Zorro II">Zorro II</a></li> <li><a href="/wiki/Amiga_Zorro_III" title="Amiga Zorro III">Zorro III</a></li> <li><a href="/wiki/Computer_Automated_Measurement_and_Control" title="Computer Automated Measurement and Control">CAMAC</a></li> <li><a href="/wiki/FASTBUS" title="FASTBUS">FASTBUS</a></li> <li><a href="/wiki/Low_Pin_Count" title="Low Pin Count">LPC</a></li> <li><a href="/wiki/HP_Precision_Bus" title="HP Precision Bus">HP Precision Bus</a></li> <li><a href="/wiki/Extended_Industry_Standard_Architecture" title="Extended Industry Standard Architecture">EISA</a></li> <li><a href="/wiki/VMEbus" title="VMEbus">VME</a></li> <li><a href="/wiki/VME_eXtensions_for_Instrumentation" title="VME eXtensions for Instrumentation">VXI</a></li> <li><a href="/wiki/VXS" title="VXS">VXS</a></li> <li><a href="/wiki/VPX" title="VPX">VPX</a></li> <li><a href="/wiki/NuBus" title="NuBus">NuBus</a></li> <li><a href="/wiki/TURBOchannel" title="TURBOchannel">TURBOchannel</a></li> <li><a href="/wiki/Micro_Channel_architecture" title="Micro Channel architecture">MCA</a></li> <li><a href="/wiki/SBus" title="SBus">SBus</a></li> <li><a href="/wiki/VESA_Local_Bus" title="VESA Local Bus">VLB</a></li> <li><a href="/wiki/GSC_bus" title="GSC bus">HP GSC bus</a></li> <li><a href="/wiki/InfiniBand" title="InfiniBand">InfiniBand</a></li> <li><a href="/wiki/Ethernet" title="Ethernet">Ethernet</a></li> <li><a href="/wiki/Ultra_Port_Architecture" title="Ultra Port Architecture">UPA</a></li> <li><a href="/wiki/Peripheral_Component_Interconnect" title="Peripheral Component Interconnect">PCI</a></li> <li><a class="mw-selflink selflink">PCI Extended (PCI-X)</a></li> <li><a href="/wiki/PCI_eXtensions_for_Instrumentation" title="PCI eXtensions for Instrumentation">PXI</a></li> <li><a href="/wiki/PCI_Express" title="PCI Express">PCI Express (PCIe)</a></li> <li><a href="/wiki/Accelerated_Graphics_Port" title="Accelerated Graphics Port">AGP</a></li> <li><a href="/wiki/Compute_Express_Link" title="Compute Express Link">Compute Express Link (CXL)</a></li> <li><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface (DMI)</a></li> <li><a href="/wiki/RapidIO" title="RapidIO">RapidIO</a></li> <li><a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">Intel QuickPath Interconnect</a></li> <li><a href="/wiki/NVLink" title="NVLink">NVLink</a></li> <li><a href="/wiki/HyperTransport" title="HyperTransport">HyperTransport</a> <ul><li><a href="/wiki/Infinity_Fabric" class="mw-redirect" title="Infinity Fabric">Infinity Fabric</a></li></ul></li> <li><a href="/wiki/Intel_Ultra_Path_Interconnect" title="Intel Ultra Path Interconnect">Intel Ultra Path Interconnect</a></li> <li><a href="/wiki/Coherent_Accelerator_Processor_Interface" title="Coherent Accelerator Processor Interface">Coherent Accelerator Processor Interface (CAPI)</a></li> <li><a href="/wiki/SpaceWire" title="SpaceWire">SpaceWire</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Storage</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ST-506/ST-412" title="ST-506/ST-412">ST-506</a></li> <li><a href="/wiki/Enhanced_Small_Disk_Interface" title="Enhanced Small Disk Interface">ESDI</a></li> <li><a href="/wiki/Intelligent_Peripheral_Interface" title="Intelligent Peripheral Interface">IPI</a></li> <li><a href="/wiki/Storage_Module_Device" title="Storage Module Device">SMD</a></li> <li><a href="/wiki/Parallel_ATA" title="Parallel ATA">Parallel ATA (PATA)</a></li> <li><a href="/wiki/Bus_and_Tag" title="Bus and Tag">Bus and Tag</a></li> <li><a href="/wiki/Digital_Storage_Systems_Interconnect" title="Digital Storage Systems Interconnect">DSSI</a></li> <li><a href="/wiki/HIPPI" title="HIPPI">HIPPI</a></li> <li><a href="/wiki/SATA" title="SATA">Serial ATA (SATA)</a></li> <li><a href="/wiki/SCSI" title="SCSI">SCSI</a> <ul><li><a href="/wiki/Parallel_SCSI" title="Parallel SCSI">Parallel</a></li> <li><a href="/wiki/Serial_Attached_SCSI" title="Serial Attached SCSI">SAS</a></li></ul></li> <li><a href="/wiki/ESCON" title="ESCON">ESCON</a></li> <li><a href="/wiki/Fibre_Channel" title="Fibre Channel">Fibre Channel</a></li> <li><a href="/wiki/Serial_Storage_Architecture" title="Serial Storage Architecture">SSA</a></li> <li><a href="/wiki/SATA_Express" title="SATA Express">SATAe</a></li> <li>PCI Express (via <a href="/wiki/Advanced_Host_Controller_Interface" title="Advanced Host Controller Interface">AHCI</a> or <a href="/wiki/NVM_Express" title="NVM Express">NVMe</a> logical device interface)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Peripheral</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Apple_Desktop_Bus" title="Apple Desktop Bus">Apple Desktop Bus</a></li> <li><a href="/wiki/Atari_SIO" title="Atari SIO">Atari SIO</a></li> <li><a href="/wiki/Digital_Control_Bus" title="Digital Control Bus">DCB</a></li> <li><a href="/wiki/Commodore_bus" title="Commodore bus">Commodore bus</a></li> <li><a href="/wiki/HP-IL" title="HP-IL">HP-IL</a></li> <li><a href="/wiki/HIL_bus" title="HIL bus">HIL</a></li> <li><a href="/wiki/MIDI" title="MIDI">MIDI</a></li> <li><a href="/wiki/RS-232" title="RS-232">RS-232</a></li> <li><a href="/wiki/RS-422" title="RS-422">RS-422</a></li> <li><a href="/wiki/RS-423" title="RS-423">RS-423</a></li> <li><a href="/wiki/RS-485" title="RS-485">RS-485</a></li> <li><a href="/wiki/Lightning_(connector)" title="Lightning (connector)">Lightning</a></li> <li><a href="/wiki/DMX512#DMX512-A" title="DMX512">DMX512-A</a></li> <li><a href="/wiki/IEEE-488" class="mw-redirect" title="IEEE-488">IEEE-488 (GPIB)</a></li> <li><a href="/wiki/IEEE_1284" title="IEEE 1284">IEEE-1284 (parallel port)</a></li> <li><a href="/wiki/IEEE_1394" title="IEEE 1394">IEEE-1394 (FireWire)</a></li> <li><a href="/wiki/UNI/O" title="UNI/O">UNI/O</a></li> <li><a href="/wiki/1-Wire" title="1-Wire">1-Wire</a></li> <li><a href="/wiki/I%C2%B2C" title="I²C">I²C</a> (<a href="/wiki/ACCESS.bus" title="ACCESS.bus">ACCESS.bus</a>, <a href="/wiki/Power_Management_Bus" title="Power Management Bus">PMBus</a>, <a href="/wiki/System_Management_Bus" title="System Management Bus">SMBus</a>)</li> <li><a href="/wiki/I3C_(bus)" title="I3C (bus)">I3C</a></li> <li><a href="/wiki/Serial_Peripheral_Interface" title="Serial Peripheral Interface">SPI</a></li> <li><a href="/wiki/IEC_61030" title="IEC 61030">D²B</a></li> <li><a href="/wiki/Parallel_SCSI" title="Parallel SCSI">Parallel SCSI</a></li> <li><a href="/wiki/Profibus" title="Profibus">Profibus</a></li> <li><a href="/wiki/USB" title="USB">USB</a></li> <li><a href="/wiki/Camera_Link" title="Camera Link">Camera Link</a></li> <li><a href="/wiki/PCI_Express#PCI_Express_External_Cabling" title="PCI Express">External PCIe</a></li> <li><a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Audio</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ADAT_Lightpipe" title="ADAT Lightpipe">ADAT Lightpipe</a></li> <li><a href="/wiki/AES3" title="AES3">AES3</a></li> <li><a href="/wiki/Intel_High_Definition_Audio" title="Intel High Definition Audio">Intel HD Audio</a></li> <li><a href="/wiki/I%C2%B2S" title="I²S">I²S</a></li> <li><a href="/wiki/MADI" title="MADI">MADI</a></li> <li><a href="/wiki/McASP" title="McASP">McASP</a></li> <li><a href="/wiki/S/PDIF" title="S/PDIF">S/PDIF</a></li> <li><a href="/wiki/TOSLINK" title="TOSLINK">TOSLINK</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Portable</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/PC_Card" title="PC Card">PC Card</a></li> <li><a href="/wiki/ExpressCard" title="ExpressCard">ExpressCard</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Embedded</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multidrop_bus" title="Multidrop bus">Multidrop bus</a></li> <li><a href="/wiki/CoreConnect" title="CoreConnect">CoreConnect</a></li> <li><a href="/wiki/Advanced_Microcontroller_Bus_Architecture" title="Advanced Microcontroller Bus Architecture">AMBA</a> (<a href="/wiki/Advanced_eXtensible_Interface" title="Advanced eXtensible Interface">AXI</a>)</li> <li><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a></li> <li><a href="/wiki/SLIMbus" title="SLIMbus">SLIMbus</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div><small>Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.</small><br /><span class="noviewer" typeof="mw:File"><span title="Category"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/16px-Symbol_category_class.svg.png" decoding="async" width="16" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/23px-Symbol_category_class.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/31px-Symbol_category_class.svg.png 2x" data-file-width="180" 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