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class="vector-toc-link" href="#Cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4</span> <span>Cache</span> </div> </a> <ul id="toc-Cache-sublist" class="vector-toc-list"> <li id="toc-Primary_caches" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Primary_caches"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4.1</span> <span>Primary caches</span> </div> </a> <ul id="toc-Primary_caches-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-B-cache" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#B-cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4.2</span> <span>B-cache</span> </div> </a> <ul id="toc-B-cache-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Branch_prediction" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Branch_prediction"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.5</span> <span>Branch prediction</span> </div> </a> <ul id="toc-Branch_prediction-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_interface" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#External_interface"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.6</span> <span>External interface</span> </div> </a> <ul id="toc-External_interface-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Memory_addressing" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Memory_addressing"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Memory addressing</span> </div> </a> <ul id="toc-Memory_addressing-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Fabrication" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Fabrication"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Fabrication</span> </div> </a> <ul id="toc-Fabrication-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Packaging" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Packaging"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Packaging</span> </div> </a> <ul id="toc-Packaging-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Derivatives" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Derivatives"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Derivatives</span> </div> </a> <button aria-controls="toc-Derivatives-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Derivatives subsection</span> </button> <ul id="toc-Derivatives-sublist" class="vector-toc-list"> <li id="toc-Alpha_21264A" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Alpha_21264A"> <div class="vector-toc-text"> <span class="vector-toc-numb">5.1</span> <span>Alpha 21264A</span> </div> </a> <ul id="toc-Alpha_21264A-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alpha_21264B" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Alpha_21264B"> <div class="vector-toc-text"> <span class="vector-toc-numb">5.2</span> <span>Alpha 21264B</span> </div> </a> <ul id="toc-Alpha_21264B-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alpha_21264C" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Alpha_21264C"> <div class="vector-toc-text"> <span class="vector-toc-numb">5.3</span> <span>Alpha 21264C</span> </div> </a> <ul id="toc-Alpha_21264C-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alpha_21264D" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Alpha_21264D"> <div class="vector-toc-text"> <span class="vector-toc-numb">5.4</span> <span>Alpha 21264D</span> </div> </a> <ul id="toc-Alpha_21264D-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alpha_21264E" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Alpha_21264E"> <div class="vector-toc-text"> <span class="vector-toc-numb">5.5</span> <span>Alpha 21264E</span> </div> </a> <ul id="toc-Alpha_21264E-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Chipsets" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Chipsets"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Chipsets</span> </div> </a> <button aria-controls="toc-Chipsets-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Chipsets subsection</span> </button> <ul id="toc-Chipsets-sublist" class="vector-toc-list"> <li id="toc-21272/21274" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#21272/21274"> <div class="vector-toc-text"> <span class="vector-toc-numb">6.1</span> <span>21272/21274</span> </div> </a> <ul id="toc-21272/21274-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Irongate" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Irongate"> <div class="vector-toc-text"> <span class="vector-toc-numb">6.2</span> <span>Irongate</span> </div> </a> <ul id="toc-Irongate-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>Further reading</span> </div> </a> <ul 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href="https://es.wikipedia.org/wiki/Alpha_21264" title="Alpha 21264 – Spanish" lang="es" hreflang="es" data-title="Alpha 21264" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/Alpha_21264" title="Alpha 21264 – Hungarian" lang="hu" hreflang="hu" data-title="Alpha 21264" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/Alpha_21264" title="Alpha 21264 – Japanese" lang="ja" hreflang="ja" data-title="Alpha 21264" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/Alpha_21264" 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</nav> </div> </div> </div> <div class="vector-column-end"> <div class="vector-sticky-pinned-container"> <nav class="vector-page-tools-landmark" aria-label="Page tools"> <div id="vector-page-tools-pinned-container" class="vector-pinned-container"> </div> </nav> <nav class="vector-appearance-landmark" aria-label="Appearance"> <div id="vector-appearance-pinned-container" class="vector-pinned-container"> <div id="vector-appearance" class="vector-appearance vector-pinnable-element"> <div class="vector-pinnable-header vector-appearance-pinnable-header vector-pinnable-header-pinned" data-feature-name="appearance-pinned" data-pinnable-element-id="vector-appearance" data-pinned-container-id="vector-appearance-pinned-container" data-unpinned-container-id="vector-appearance-unpinned-container" > <div class="vector-pinnable-header-label">Appearance</div> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" 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src="//upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Alpha_21264.png/220px-Alpha_21264.png" decoding="async" width="220" height="207" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Alpha_21264.png/330px-Alpha_21264.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Alpha_21264.png/440px-Alpha_21264.png 2x" data-file-width="1903" data-file-height="1787" /></a><figcaption>Alpha 21264 microarchitecture.</figcaption></figure> <p>The <b>Alpha 21264</b> is a <a href="/wiki/RISC" class="mw-redirect" title="RISC">RISC</a> <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a> developed by <a href="/wiki/Digital_Equipment_Corporation" title="Digital Equipment Corporation">Digital Equipment Corporation</a> launched on 19 October 1998. The 21264 implemented the <a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a> <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> (ISA). </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Description">Description</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=1" title="Edit section: Description"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Alpha 21264 is a four-issue <a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> microprocessor with <a href="/wiki/Out-of-order_execution" title="Out-of-order execution">out-of-order execution</a> and <a href="/wiki/Speculative_execution" title="Speculative execution">speculative execution</a>. It has a peak execution rate of six instructions per cycle and could sustain four instructions per cycle. It has a seven-stage <a href="/wiki/Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">instruction pipeline</a>. </p> <div class="mw-heading mw-heading3"><h3 id="Out_of_order_execution">Out of order execution</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=2" title="Edit section: Out of order execution"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>At any given stage, the microprocessor could have up to 80 instructions in various stages of execution, surpassing any other contemporary microprocessor. </p><p>Decoded instructions are held in instruction queues and are issued when their operands are available. The integer queue contained 20 entries and the floating-point queue 15. Each queue could issue as many instructions as there were pipelines. </p> <div class="mw-heading mw-heading3"><h3 id="Ebox">Ebox</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=3" title="Edit section: Ebox"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Ebox executes integer, load and store instructions. It has two integer units, two load store units and two integer <a href="/wiki/Register_file" title="Register file">register files</a>. Each integer register file contained 80 entries, of which 32 are architectural registers, 40 are rename registers and 8 are PAL shadow registers. There was no entry for register R31 because in the Alpha architecture, R31 is hardwired to zero and is read-only. </p><p>Each register file served an integer unit and a load store unit, and the register file and its two units are referred to as a "cluster". The two clusters were designated U0 and U1. This scheme was used as it reduced the number of write and read ports required to serve operands and receive results, thus reducing the physical size of the register file, enabling the microprocessor to operate at higher clock frequencies. Writes to any of the register files thus have to be synchronized, which required a clock cycle to complete, negatively impacting performance by one percent. The reduction of performance resulting from the synchronization was compensated in two ways. Firstly, the higher clock frequency achievable offset the loss. Secondly, the logic responsible for instruction issue avoided creating situations where the register file had to be synchronized by issuing instructions that were not dependent on data held in other register file where possible. </p><p>The clusters are near identical except for two differences: U1 has a seven-cycle pipelined multiplier while U0 has a three-cycle pipeline for executing Motion Video Instructions (MVI), an extension to the Alpha Architecture defining single instruction multiple data (SIMD) instructions for multimedia. </p><p>The load store units are simple <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">arithmetic logic units</a> used to calculate <a href="/wiki/Virtual_address" class="mw-redirect" title="Virtual address">virtual addresses</a> for memory access. They are also capable of executing simple arithmetic and logic instructions. The Alpha 21264 instruction issue logic utilized this capability, issuing instructions to these units when they were available for use (not performing address arithmetic). </p><p>The Ebox therefore has four 64-bit <a href="/wiki/Adder_(electronics)" title="Adder (electronics)">adders</a>, four logic units, two <a href="/wiki/Barrel_shifter" title="Barrel shifter">barrel shifters</a>, byte-manipulation logic, two sets of conditional branch logic equally divided between U1 and U0. </p> <div class="mw-heading mw-heading3"><h3 id="Fbox">Fbox</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=4" title="Edit section: Fbox"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Fbox is responsible for executing <a href="/wiki/Floating-point" class="mw-redirect" title="Floating-point">floating-point</a> instructions. It consists of two floating-point pipelines and a floating-point register file. The pipelines are not identical, one executes the majority of instructions and the other only multiply instructions. The adder pipeline has two non-pipelined units connected to it, a divide unit and a square root unit. Adds, multiplies and most other instructions have a 4-cycle latency, a double-precision divide has 16-cycle latency and a double-precision square root has a 33-cycle latency. The floating point register file contains 72 entries, of which 32 are architectural registers and 40 are rename registers. </p> <div class="mw-heading mw-heading3"><h3 id="Cache">Cache</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=5" title="Edit section: Cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Alpha 21264 has two levels of <a href="/wiki/CPU_cache" title="CPU cache">cache</a>, a primary cache and secondary cache. The level three (L3, or "victim") cache of the <a href="/wiki/Alpha_21164" title="Alpha 21164">Alpha 21164</a> was not used due to problems with bandwidth. </p> <div class="mw-heading mw-heading4"><h4 id="Primary_caches">Primary caches</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=6" title="Edit section: Primary caches"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The primary cache is split into separate caches for instructions and data ("<a href="/wiki/Modified_Harvard_architecture" title="Modified Harvard architecture">modified Harvard architecture</a>"), the I-cache and D-cache, respectively. Both caches have a capacity of 64 KB. The D-cache is dual-ported by transferring data on both the rising and falling edges of the clock signal. This method of dual-porting enabled any combination of reads or writes to the cache every processor cycle. It also avoided duplication the cache so there are two, as in the Alpha 21164. Duplicating the cache restricted the capacity of the cache, as it required more transistors to provide the same amount of capacity, and in turn increased the area required and power consumed. </p> <div class="mw-heading mw-heading4"><h4 id="B-cache">B-cache</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=7" title="Edit section: B-cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The secondary cache, termed the B-cache, is an external cache with a capacity of 1 to 16 MB. It is controlled by the microprocessor and is implemented by synchronous <a href="/wiki/Static_random_access_memory" class="mw-redirect" title="Static random access memory">static random access memory</a> (SSRAM) chips that operate at two thirds, half, one-third or one-fourth the internal clock frequency, or 133 to 333 MHz at 500 MHz. The B-cache was accessed with a dedicated 128-bit bus that operates at the same clock frequency as the SSRAM or at twice the clock frequency if <a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a> SSRAM is used. The B-cache is direct-mapped.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Branch_prediction">Branch prediction</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=8" title="Edit section: Branch prediction"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Branch_predictor" title="Branch predictor">Branch prediction</a> is performed by a tournament branch prediction algorithm. The algorithm was developed by Scott McFarling at Digital's Western Research Laboratory (WRL) and was described in a 1993 paper. This predictor was used as the Alpha 21264 has a minimum branch misprediction penalty of seven cycles. Due to the instruction cache's two cycle latency and the instruction queues, the average branch misprediction penalty is 11 cycles. The algorithm maintains two history tables, Local and Global, and the table used to predict the outcome of a branch is determined by a Choice predictor. </p><p>The local predictor is a two-level table which records the history of individual branches. It consists of a 1,024-entry by 10-bit branch history table. A two-level table was used as the prediction accuracy is similar to that of a larger single-level table while requiring fewer bits of storage. It has a 1,024-entry branch prediction table. Each entry is a 3-bit saturating counter. The value of the counter determines whether the current branch is taken or not taken. </p><p>The global predictor is a single-level, 4096-entry branch history table. Each entry is a 2-bit saturating counter; the value of this counter determines whether the current branch is taken or not taken. </p><p>The choice predictor records the history of the local and global predictors to determine which predictor is the best for a particular branch. It has a 4,096-entry branch history table. Each entry is a 2-bit saturating counter. The value of the counter determines if the local or global predictor is used. </p> <div class="mw-heading mw-heading3"><h3 id="External_interface">External interface</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=9" title="Edit section: External interface"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The external interface consisted of a bidirectional 64-bit <a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a> (DDR) <a href="/wiki/Bus_(computing)" title="Bus (computing)">data bus</a> and two 15-bit unidirectional time-multiplexed <a href="/wiki/Address_bus" class="mw-redirect" title="Address bus">address</a> and <a href="/wiki/Control_bus" title="Control bus">control</a> buses, one for signals originating from the Alpha 21264 and one for signals originating from the system. Digital licensed the bus to <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">Advanced Micro Devices</a> (AMD), and it was subsequently used in their <a href="/wiki/Athlon" title="Athlon">Athlon</a> microprocessors, where it was known as the EV6 bus. </p> <div class="mw-heading mw-heading2"><h2 id="Memory_addressing">Memory addressing</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=10" title="Edit section: Memory addressing"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Alpha 21264 CPU supports 48-bit or 43-bit virtual address (256 TiB or 8 TiB virtual address space respectively), selectable under IPR control (using VA_CTL control register). Alpha 21264 supports a 44-bit physical address (up to 16 TiB of physical memory). This is an increase from previous Alpha CPUs (43-bit virtual and 40-bit physical for <a href="/wiki/Alpha_21164" title="Alpha 21164">Alpha 21164</a>, and 43-bit virtual and 34-bit physical for <a href="/wiki/Alpha_21064" title="Alpha 21064">Alpha 21064</a>).<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Fabrication">Fabrication</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=11" title="Edit section: Fabrication"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Alpha 21264 contained 15.2 million transistors. The logic consisted of approximately six million transistors, with the rest contained in the caches and branch history tables. The die measured 16.7 mm by 18.8 mm (313.96 mm²).<sup id="cite_ref-JSSC-1998_3-0" class="reference"><a href="#cite_note-JSSC-1998-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> It was fabricated in a 0.35 μm <a href="/wiki/CMOS" title="CMOS">complementary metal–oxide–semiconductor</a> (CMOS) <a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">process</a> with six levels of interconnect. </p> <div class="mw-heading mw-heading2"><h2 id="Packaging">Packaging</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=12" title="Edit section: Packaging"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Alpha 21264 was packaged in a 587-pin ceramic interstitial <a href="/wiki/Pin_grid_array" title="Pin grid array">pin grid array</a> (IPGA). </p><p>Alpha Processor, Inc. later sold the Alpha 21264 in a Slot B package containing the microprocessor mounted on a printed circuit board with the B-cache and voltage regulators. The design was intended to use the success of slot-based microprocessors from Intel and AMD. Slot B was originally developed to be used by AMD's Athlon as well, so that API could obtain materials for the Slot B at commodity prices in order to reduce the cost of the Alpha 21264 to gain a wider market share. This never materialized as AMD chose to use Slot A for their slot-based Athlons. </p> <div class="mw-heading mw-heading2"><h2 id="Derivatives">Derivatives</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=13" title="Edit section: Derivatives"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Alpha_21264A">Alpha 21264A</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=14" title="Edit section: Alpha 21264A"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:DEC_Alpha_21264A_(EV67)_(8875557248)_(cropped).jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/5/5a/DEC_Alpha_21264A_%28EV67%29_%288875557248%29_%28cropped%29.jpg/220px-DEC_Alpha_21264A_%28EV67%29_%288875557248%29_%28cropped%29.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/5a/DEC_Alpha_21264A_%28EV67%29_%288875557248%29_%28cropped%29.jpg/330px-DEC_Alpha_21264A_%28EV67%29_%288875557248%29_%28cropped%29.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/5a/DEC_Alpha_21264A_%28EV67%29_%288875557248%29_%28cropped%29.jpg/440px-DEC_Alpha_21264A_%28EV67%29_%288875557248%29_%28cropped%29.jpg 2x" data-file-width="1870" data-file-height="1870" /></a><figcaption>Alpha 21264A</figcaption></figure> <p>The <b>Alpha 21264A</b>, code-named <b>EV67</b> was a shrink of the Alpha 21264 introduced in late 1999. There were six versions: 600, 667, 700, 733, 750, 833 MHz. The EV67 was the first Alpha microprocessor to implement the count extension (CIX), which extended the instruction set with instructions for performing <a href="/wiki/Hamming_weight" title="Hamming weight">population count</a>. It was fabricated by Samsung Electronics in a 0.25 μm CMOS process that had 0.25 μm transistors but 0.35 μm metal layers. The die had an area of 210 mm². The EV68 used a 2.0 V power supply. It dissipated a maximum of 73 W at 600 MHz, 80 W at 667 MHz, 85 W at 700 MHz, 88 W at 733 MHz and 90 W at 750 MHz. </p> <div class="mw-heading mw-heading3"><h3 id="Alpha_21264B">Alpha 21264B</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=15" title="Edit section: Alpha 21264B"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <b>Alpha 21264B</b> is a further development for increased clock frequencies. There were two models, one fabricated by IBM, code-named <b>EV68C</b>, and one by Samsung, code-named <b>EV68A</b>. </p><p>The EV68A was fabricated in a 0.18 μm CMOS process with <a href="/wiki/Aluminium_interconnects" class="mw-redirect" title="Aluminium interconnects">aluminium interconnects</a>. It had a die size of 125 mm², a third smaller than the Alpha 21264A, and used a 1.7 V power supply. It was available in volume in 2001 at clock frequencies of 750, 833, 875 and 940 MHz. The EV68A dissipated a maximum of 60 W at 750 MHz, 67 W at 833 MHz, 70 W at 875 MHz and 75 W at 940 MHz.<sup id="cite_ref-Compaq_2002-03_4-0" class="reference"><a href="#cite_note-Compaq_2002-03-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p><p>The EV68C was fabricated in a 0.18 μm CMOS process with copper interconnects. It was sampled in early 2000 and achieved a maximum clock frequency of 1.25 GHz. </p><p>In September 1998, Samsung announced they would fabricate a variant of the Alpha 21264B in a 0.18 μm fully depleted <a href="/wiki/Silicon-on-insulator" class="mw-redirect" title="Silicon-on-insulator">silicon-on-insulator</a> (SOI) process with <a href="/wiki/Copper-based_chips" class="mw-redirect" title="Copper-based chips">copper interconnects</a> that was capable of achieving a clock frequency of 1.5 GHz. This version never materialized. </p> <div class="mw-heading mw-heading3"><h3 id="Alpha_21264C">Alpha 21264C</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=16" title="Edit section: Alpha 21264C"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <b>Alpha 21264C</b>, code-named <b>EV68CB</b> was a derivative of the Alpha 21264. It was available at clock frequencies of 1.0, 1.25 and 1.33 GHz. The EV68CB contained 15.5 million transistors and measured 120 mm². It was fabricated by IBM in a 0.18 μm CMOS process with seven levels of copper interconnect and <a href="/wiki/Low-K" class="mw-redirect" title="Low-K">low-K</a> <a href="/wiki/Dielectric" title="Dielectric">dielectric</a>. It was packaged in a 675-pad <a href="/wiki/Flip-chip" class="mw-redirect" title="Flip-chip">flip-chip</a> <a href="/wiki/Ceramic_land_grid_array" class="mw-redirect" title="Ceramic land grid array">ceramic land grid array</a> (CLGA) measuring 49.53 by 49.53 mm. The EV68CB used a 1.7 V power supply, dissipating a maximum of 64 W at 1.0 GHz, 75 W at 1.25 GHz and 80 W at 1.33 GHz.<sup id="cite_ref-Compaq_2000-06_5-0" class="reference"><a href="#cite_note-Compaq_2000-06-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Alpha_21264D">Alpha 21264D</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=17" title="Edit section: Alpha 21264D"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <b>Alpha 21264D</b>, code-named <b>EV68CD</b> is a faster derivative fabricated by IBM. </p> <div class="mw-heading mw-heading3"><h3 id="Alpha_21264E">Alpha 21264E</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=18" title="Edit section: Alpha 21264E"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <b>Alpha 21264E</b>, code-named <b>EV68E</b>, was a cancelled derivative developed by Samsung first announced on 10 October 2000 at Microprocessor Forum 2000 slated for introduction at around mid-2001. Improvements were a higher operating frequency of 1.25 GHz and the addition of an on-die 1.85 MB secondary cache. It was to be fabricated in a 0.18 micrometre CMOS process with copper interconnects. </p> <div class="mw-heading mw-heading2"><h2 id="Chipsets">Chipsets</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=19" title="Edit section: Chipsets"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Digital and <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">Advanced Micro Devices</a> (AMD) both developed chipsets for the Alpha 21264. </p> <div class="mw-heading mw-heading3"><h3 id="21272/21274"><span id="21272.2F21274"></span>21272/21274</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=20" title="Edit section: 21272/21274"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Digital <b>21272</b>, also known as the <b>Tsunami</b>, and the 21274, also known as the <b>Typhoon</b>, were the first chipset for the Alpha 21264. The 21272 chipset supported one- or two-way multiprocessing and up to 8GB of memory, while the 21274 supported one-, two-, three- or four-way multiprocessing, up to 64GB of memory, and both supported one or two 64-bit 33 MHz <a href="/wiki/Peripheral_Component_Interconnect" title="Peripheral Component Interconnect">PCI</a> buses. They had 128- to 512-bit memory bus which operated at 83 MHz, yielding a maximum bandwidth of 5,312 MB/s. The chipset supported 100 MHz registered ECC SDRAM. </p><p>The chipset consisted of three devices, a C-chip, a D-chip and a P-chip. The number of devices which made up the chipset varied as it was determined by the configuration of the chipset. The C-chip is the control chip containing the memory controller. One C-chip was required for every microprocessor. </p><p>The P-chip is the PCI controller, implementing a 33 MHz PCI bus. The 21272 could have one or two P-chips. </p><p>The D-chip is the DRAM controller, implementing access to/from the CPUs, and to/from the P-chip. The 21272 could have two or four D-chips and the 21274 could have two, four, or eight D-chips. </p><p>The 21272 and 21274 were used extensively by Digital, Compaq and Hewlett Packard in their entry-level to mid-range AlphaServers and in all models of the AlphaStation. It was also used in third-party products from Alpha Processor, Inc. (later known as API NetWorks) such as their UP2000+ motherboard. </p> <div class="mw-heading mw-heading3"><h3 id="Irongate">Irongate</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=21" title="Edit section: Irongate"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Socket_A#Chipsets" title="Socket A">Socket A § Chipsets</a></div> <p>AMD developed two Alpha 21264-compatible chipsets, the <b>Irongate</b>, also known as the <b>AMD-751</b>, and its successor, <b>Irongate-2</b>, also known as the <b>AMD-761</b>. These chipsets were developed for their Athlon microprocessors but due to AMD licensing the EV6 bus used in the Alpha from Digital, the Athlon and Alpha 21264 were compatible in terms of bus protocol. The Irongate was used by Samsung in their UP1000 and UP1100 motherboards. The Irongate-2 was used by Samsung in their UP1500 motherboard. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=22" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/w/index.php?title=AlphaVM&action=edit&redlink=1" class="new" title="AlphaVM (page does not exist)">AlphaVM</a>: A full <a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a> system emulator running on Windows or Linux. It contains a high-performance emulator of the Alpha CPU.</li> <li><a href="/wiki/Bulldozer_(microarchitecture)#CMT" title="Bulldozer (microarchitecture)">Clustered Multi-threading</a></li> <li><a href="/wiki/Alpha_21364" title="Alpha 21364">Alpha 21364</a></li> <li><a href="/wiki/Alpha_21464" title="Alpha 21464">Alpha 21464</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=23" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text">The Alpha 21264 Microprocessor Architecture, p. 5.</span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.star.bnl.gov/public/daq/HARDWARE/21264_data_sheet.pdf">"Alpha 21264 Microprocessor Data Sheet"</a> <span class="cs1-format">(PDF)</span>. Compaq Computer Corporation<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-06-03</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Alpha+21264+Microprocessor+Data+Sheet&rft.pub=Compaq+Computer+Corporation&rft_id=https%3A%2F%2Fwww.star.bnl.gov%2Fpublic%2Fdaq%2FHARDWARE%2F21264_data_sheet.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AAlpha+21264" class="Z3988"></span></span> </li> <li id="cite_note-JSSC-1998-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-JSSC-1998_3-0">^</a></b></span> <span class="reference-text"><a href="#JSSC-1998">Gronowski, "High Performance Microprocessor Design", p. 676</a>.</span> </li> <li id="cite_note-Compaq_2002-03-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-Compaq_2002-03_4-0">^</a></b></span> <span class="reference-text"><a href="#Compaq_2002-03">Compaq, "21264/EV68A Microprocessor Hardware Reference Manual"</a>.</span> </li> <li id="cite_note-Compaq_2000-06-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-Compaq_2000-06_5-0">^</a></b></span> <span class="reference-text"><a href="#Compaq_2001-06">Compaq, "21264/EV68CB and 21264/EV68DC Hardware Reference Manual"</a>.</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=24" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Compaq_Computer_Corporation" class="mw-redirect" title="Compaq Computer Corporation">Compaq Computer Corporation</a> (July 1999). <i>Alpha 21264 Microprocessor Hardware Reference Manual</i>.</li> <li><cite id="Compaq_2001-06"><a href="/wiki/Compaq_Computer_Corporation" class="mw-redirect" title="Compaq Computer Corporation">Compaq Computer Corporation</a> (June 2001). <i>21264/EV68CB and 21264/EV68DC Hardware Reference Manual</i>.</cite></li> <li><a href="/wiki/Compaq_Computer_Corporation" class="mw-redirect" title="Compaq Computer Corporation">Compaq Computer Corporation</a> (March 2002). <i>21264/EV67 Microprocessor Hardware Reference Manual</i>.</li> <li><cite id="Compaq_2002-03"><a href="/wiki/Compaq_Computer_Corporation" class="mw-redirect" title="Compaq Computer Corporation">Compaq Computer Corporation</a> (March 2002). <i>21264/EV68A Microprocessor Hardware Reference Manual</i>.</cite></li> <li><cite id="JSSC-1998">Gronowski, Paul E. et al. (1998). "High Performance Microprocessor Design". <i>IEEE Journal of Solid-State Circuits</i>, Volume 33, Number 5, pp. 676–686.</cite></li> <li>Gwennap, Linley (28 October 1996). "Digital 21264 Sets New Standard". <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>, Volume 10, Number 14. MicroDesign Resources.</li> <li>Kessler, R. E.; McLellan, E. J. and Webb, D. A. (1998) "The Alpha 21264 Microprocessor Architecture". <i>Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors</i>. pp. 90–95.</li> <li>Kessler, R. E. (1999). "The Alpha 21264 Microprocessor". <i><a href="/wiki/IEEE_Micro" title="IEEE Micro">IEEE Micro</a></i>, March–April 1999. pp. 24–36.</li> <li>Leibholz, Daniel and Razdan, Rahul (1997). "The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor". <i>Proceedings of Compcon '97</i>. pp. 28–36.</li> <li>Matson, M. et al. "Circuit Implementation of a 600MHz Superscalar RISC Microprocessor". <i>Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors</i>. pp. 104–110.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Alpha_21264&action=edit&section=25" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Benschneider, B.J. et al. (2000). <a rel="nofollow" class="external text" href="https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=839702">"A 1 GHz Alpha microprocessor"</a>. <i>ISSCC Digest of Technical Papers</i>, pp. 86–87.</li> <li>Clouser, J. et al. (July 1999). <a rel="nofollow" class="external text" href="https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=772419">"A 600-MHz superscalar floating-point processor"</a>. <i>IEEE Journal of Solid-State Circuits</i> <b>34</b> (7): pp. 1026–1029.</li> <li>Fischer, T.; Leibholz, D. (1998). <a rel="nofollow" class="external text" href="https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=672448">"Design trade offs in stall-control circuits for 600 MHz instruction queues"</a>. <i>ISSCC Digest of Technical Papers</i>, pp. 232–234, 444.</li> <li>Gieseke, B.A. et al. (1997). "A 600 MHz superscalar RISC microprocessor with out-of-order execution". <i>ISSCC Digest of Technical Papers</i>, pp. 176–177, 451.</li> <li>Gronowski, Paul E. et al. (May 1998). "High-performance microprocessor design". <i>IEEE Journal of Solid-State Circuits</i> <b>33</b> (5): pp. 676–686.</li> <li>Hokinson, R. et al. (2001). <a rel="nofollow" class="external text" href="https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=912656">"Design and migration challenges for an Alpha microprocessor in a 0.18 μm copper process"</a>. <i>ISSCC Digest of Technical Papers</i>, pp. 320–321, 460.</li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul 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style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DEC_V-11" title="DEC V-11">V-11</a></li> <li><a href="/wiki/MicroVAX_78032" title="MicroVAX 78032">MicroVAX 78032</a></li> <li><a href="/wiki/CVAX" title="CVAX">CVAX</a> <ul><li><a href="/wiki/CVAX#SOC" title="CVAX">SOC</a></li></ul></li> <li><a href="/wiki/Rigel_(microprocessor)" title="Rigel (microprocessor)">Rigel</a> <ul><li><a href="/wiki/Rigel_(microprocessor)#Mariah" title="Rigel (microprocessor)">Mariah</a></li></ul></li> <li><a href="/wiki/NVAX" title="NVAX">NVAX</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Alpha_21064" title="Alpha 21064">Alpha 21064</a> <ul><li><a href="/wiki/Alpha_21064#Alpha_21066" title="Alpha 21064">21066</a></li> <li><a href="/wiki/Alpha_21064#Alpha_21068" title="Alpha 21064">21068</a></li></ul></li> <li><a href="/wiki/Alpha_21164" title="Alpha 21164">Alpha 21164</a> (<a href="/wiki/Alpha_21164#Alpha_21164PC_(PCA56)" title="Alpha 21164">21164PC</a>)</li> <li><a class="mw-selflink selflink">Alpha 21264</a></li> <li><a href="/wiki/Alpha_21364" title="Alpha 21364">Alpha 21364</a></li> <li><a href="/wiki/Alpha_21464" title="Alpha 21464">Alpha 21464</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DEC_PRISM" title="DEC PRISM">MicroPRISM</a></li> <li><a href="/wiki/StrongARM" title="StrongARM">StrongARM</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_terminal" title="Computer terminal">Computer<br />terminals</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/VT05" title="VT05">VT05</a> (1970)</li> <li><a href="/wiki/DEC_GT40" title="DEC GT40">GT40</a> (1972)</li> <li><a href="/wiki/VT52" title="VT52">VT50/VT52</a> (1975)</li> <li><a href="/wiki/VT55" class="mw-redirect" title="VT55">VT55</a></li> <li><a href="/wiki/VT62" class="mw-redirect" title="VT62">VT62</a></li> <li><a href="/wiki/VT100" title="VT100">VT100</a> (1978)</li> <li><a href="/wiki/VT101" class="mw-redirect" title="VT101">VT101</a></li> <li><a href="/wiki/VT102" class="mw-redirect" title="VT102">VT102</a></li> <li><a href="/wiki/VT103" class="mw-redirect" title="VT103">VT103</a></li> <li><a href="/wiki/VT105" class="mw-redirect" title="VT105">VT105</a></li> <li><a href="/wiki/VT131" class="mw-redirect" title="VT131">VT131</a></li> <li><a href="/wiki/VT180" title="VT180">VT180</a></li> <li><a href="/wiki/VT220" title="VT220">VT220</a> (1983)</li> <li><a href="/wiki/VT240" class="mw-redirect" title="VT240">VT240</a></li> <li><a href="/wiki/VT241" class="mw-redirect" title="VT241">VT241</a></li> <li><a href="/wiki/VT320" title="VT320">VT320</a> (1987)</li> <li><a href="/wiki/VT330" class="mw-redirect" title="VT330">VT330</a></li> <li><a href="/wiki/VT340" class="mw-redirect" title="VT340">VT340</a></li> <li><a href="/wiki/VT420" title="VT420">VT420</a> (1990)</li> <li><a href="/wiki/VT1000" title="VT1000">VT1000</a> (1990)</li> <li><a href="/wiki/VT510" class="mw-redirect" title="VT510">VT510</a> (1993)</li> <li><a href="/wiki/VT520" title="VT520">VT520</a> (1994)</li> <li><a href="/wiki/VT525" class="mw-redirect" title="VT525">VT525</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Operating_system" title="Operating system">Operating<br />systems</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/PDP-7#Software" title="PDP-7">DECsys</a></li> <li><a href="/wiki/4K_Disk_Monitor_System" class="mw-redirect" title="4K Disk Monitor System">4K DMS</a></li> <li><a href="/wiki/Commercial_Operating_System" title="Commercial Operating System">COS</a></li> <li><a href="/wiki/TOPS-10" title="TOPS-10">TOPS-10</a></li> <li><a href="/wiki/RSX-15" class="mw-redirect" title="RSX-15">RSX-15</a></li> <li><a href="/wiki/TSS/8" title="TSS/8">TSS/8</a></li> <li><a href="/wiki/OS/8" title="OS/8">OS/8</a></li> <li><a href="/wiki/DEC_BATCH-11/DOS-11" title="DEC BATCH-11/DOS-11">DOS-11</a></li> <li><a href="/wiki/RT-11" title="RT-11">RT-11</a></li> <li><a href="/wiki/RSTS/E" title="RSTS/E">RSTS/E</a></li> <li><a href="/wiki/RSX-11" title="RSX-11">RSX-11</a> <ul><li><a href="/wiki/Interactive_Application_System" title="Interactive Application System">IAS</a></li></ul></li> <li><a href="/wiki/MUMPS#1970s" title="MUMPS">DSM-11</a></li> <li><a href="/wiki/TOPS-20" title="TOPS-20">TOPS-20</a></li> <li><a href="/wiki/OpenVMS" title="OpenVMS">VAX/VMS</a></li> <li><a href="/wiki/VAXELN" title="VAXELN">VAXELN</a></li> <li><a href="/wiki/Ultrix" title="Ultrix">Ultrix</a></li> <li><a href="/wiki/DEC_MICA" title="DEC MICA">MICA</a></li> <li><a href="/wiki/Digital_UNIX" class="mw-redirect" title="Digital UNIX">Digital UNIX</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Programming_language" title="Programming language">Programming<br />languages</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/BASIC-8" title="BASIC-8">BASIC-8</a></li> <li><a href="/wiki/DIBOL" title="DIBOL">DIBOL</a></li> <li><a href="/wiki/FOCAL_(programming_language)" title="FOCAL (programming language)">FOCAL</a></li> <li><a href="/wiki/MACRO-10" title="MACRO-10">MACRO-10</a></li> <li><a href="/wiki/MACRO-11" title="MACRO-11">MACRO-11</a></li> <li><a href="/wiki/MUMPS" title="MUMPS">MUMPS</a></li> <li><a href="/wiki/VAX_MACRO" title="VAX MACRO">VAX MACRO</a></li> <li><a href="/wiki/DIGITAL_Command_Language" title="DIGITAL Command Language">DIGITAL Command Language</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Character_encoding" title="Character encoding">Character sets</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multinational_Character_Set" title="Multinational Character Set">Code page 1100</a> (Multinational)</li> <li><a href="/wiki/Code_page_1287" title="Code page 1287">Code page 1287</a> (Greek)</li> <li><a href="/wiki/Code_page_1288" title="Code page 1288">Code page 1288</a> (Turkish)</li> <li><a href="/wiki/DEC_Hebrew" title="DEC Hebrew">Hebrew</a></li> <li><a href="/wiki/National_Replacement_Character_Set" title="National Replacement Character Set">National Replacement</a></li> <li><a href="/wiki/DEC_RADIX_50" title="DEC RADIX 50">RADIX 50</a></li> <li><a href="/wiki/DEC_Special_Graphics" title="DEC Special Graphics">Special Graphics</a></li> <li><a href="/wiki/DEC_Technical_Character_Set" title="DEC Technical Character Set">Technical</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus standards</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Digital_Storage_Systems_Interconnect" title="Digital Storage Systems Interconnect">Digital Storage Systems Interconnect</a></li> <li><a href="/wiki/Massbus" title="Massbus">Massbus</a></li> <li><a href="/wiki/Q-Bus" title="Q-Bus">Q-Bus</a></li> <li><a href="/wiki/Standard_Disk_Interconnect" title="Standard Disk Interconnect">Standard Disk Interconnect</a></li> <li><a href="/wiki/Synchronous_Backplane_Interconnect" title="Synchronous Backplane Interconnect">Synchronous Backplane Interconnect</a></li> <li><a href="/wiki/TURBOchannel" title="TURBOchannel">TURBOchannel</a></li> <li><a href="/wiki/Unibus" title="Unibus">Unibus</a></li> <li><a href="/wiki/VAXBI_bus" title="VAXBI bus">VAXBI bus</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other <a href="/wiki/Computer_hardware" title="Computer hardware">hardware</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DECtalk" title="DECtalk">DECtalk</a></li> <li><a href="/wiki/DECtape" title="DECtape">DECtape</a></li> <li><a href="/wiki/DECwriter" title="DECwriter">DECwriter</a></li> <li><a href="/wiki/Digital_Linear_Tape" title="Digital Linear Tape">Digital Linear Tape</a></li> <li><a href="/wiki/Dynamically_Redefined_Character_Set" title="Dynamically Redefined Character Set">Dynamically Redefined Character Set</a></li> <li><a href="/wiki/Firefly_(cache_coherence_protocol)" title="Firefly (cache coherence protocol)">Firefly</a></li> <li><a href="/wiki/Flip-Chip_module" title="Flip-Chip module">Flip-Chip module</a></li> <li><a href="/wiki/Gold_key_(DEC)" title="Gold key (DEC)">Gold key</a></li> <li><a href="/wiki/LK201" title="LK201">LK201</a></li> <li><a href="/wiki/LK421" title="LK421">LK421</a></li> <li><a href="/wiki/Mass_Storage_Control_Protocol" title="Mass Storage Control Protocol">Mass Storage Control Protocol</a></li> <li><a href="/wiki/PALcode" title="PALcode">PALcode</a></li> <li><a href="/wiki/RA90" title="RA90">RA90</a></li> <li><a href="/wiki/RK05" title="RK05">RK05</a></li> <li><a href="/wiki/RL02" title="RL02">RL02</a></li> <li><a href="/wiki/Star_coupler" title="Star coupler">Star coupler</a></li> <li><a href="/wiki/System_Module" title="System Module">System Module</a></li> <li><a href="/wiki/TU81" title="TU81">TU81</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related topics</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AdvFS" title="AdvFS">AdvFS</a></li> <li><a href="/wiki/AltaVista" title="AltaVista">AltaVista</a></li> <li><a href="/wiki/Compaq" title="Compaq">Compaq</a></li> <li><i><a href="/wiki/CPU_Wars" title="CPU Wars">CPU Wars</a></i></li> <li><a href="/wiki/DECnet" title="DECnet">DECnet</a></li> <li><a href="/wiki/DECUS" title="DECUS">DECUS</a> <ul><li><a href="/wiki/HP-Interex" title="HP-Interex">HP-Interex</a></li></ul></li> <li><a href="/wiki/Digital_Federal_Credit_Union" title="Digital Federal Credit Union">Digital Federal Credit Union</a></li> <li><a href="/wiki/Dynamic_debugging_technique" title="Dynamic debugging technique">Dynamic debugging technique</a></li> <li><a href="/wiki/FX!32" title="FX!32">FX!32</a></li> <li><a href="/wiki/Local_Area_Transport" title="Local Area Transport">Local Area Transport</a></li> <li><a href="/wiki/Maintenance_Operations_Protocol" title="Maintenance Operations Protocol">Maintenance Operations Protocol</a></li> <li><a href="/wiki/On-line_Debugging_Tool" title="On-line Debugging Tool">On-line Debugging Tool</a></li> <li><a href="/wiki/PALcode" title="PALcode">PALcode</a></li> <li><a href="/wiki/Record_Management_Services" title="Record Management Services">Record Management Services</a></li> <li><a href="/wiki/ReGIS" title="ReGIS">ReGIS</a></li> <li>Sequence and Batch Language</li> <li><a href="/wiki/Sixel" title="Sixel">Sixel</a></li> <li><a href="/wiki/System_Reference_Manual" class="mw-redirect" title="System Reference Manual">System Reference Manual</a></li> <li><a href="/wiki/DEC_Systems_Research_Center" title="DEC Systems Research Center">Systems Research Center</a></li> <li><a href="/wiki/TD/SMP" title="TD/SMP">TD/SMP</a></li> <li><i><a href="/wiki/The_Ultimate_Entrepreneur" title="The Ultimate Entrepreneur">The Ultimate Entrepreneur</a></i></li> <li><a href="/wiki/VT640" title="VT640">VT640</a></li> <li><a href="/wiki/WPS-8" title="WPS-8">WPS-8</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="3"><div> <ul><li><span class="noviewer" typeof="mw:File"><span title="Template"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/8/83/Symbol_template_class_pink.svg/16px-Symbol_template_class_pink.svg.png" decoding="async" width="16" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/83/Symbol_template_class_pink.svg/23px-Symbol_template_class_pink.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/83/Symbol_template_class_pink.svg/31px-Symbol_template_class_pink.svg.png 2x" data-file-width="180" data-file-height="185" /></span></span> <a href="/wiki/Template:DEC_hardware" title="Template:DEC hardware">Computers template</a></li> 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