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But on a chip, it becomes necessary to have a grid structure of power, with more than one 'vdd' and 'vss'. The concept of power grid structure would be uploaded soon. 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" class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="eager" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-1-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-1-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-1-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-1-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide2" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-1" alt="Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • Partition and synthesize larger designs into smaller modules consisting of IP’s and std cells " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-2-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-2-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-2-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-2-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide3" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-2" alt="Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • Define width and Height of ‘core’ and ‘Die’ using the physical area of synthesized netlist, utilization factor and aspect ratio " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-3-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-3-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-3-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-3-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide4" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-3" alt="Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • Define locations of pre-placed cells " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-4-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-4-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-4-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-4-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide5" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-4" alt="Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • Place de-coupling capacitors surrounding pre-placed cells " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-5-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-5-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-5-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-5-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide6" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-5" alt="Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • Power Planning " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-6-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-6-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-6-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-6-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide7" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-6" alt="Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • IO Pin/Pad placement " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-7-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-7-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-7-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-7-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide8" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-7" alt="• We have defined the Width and Height of the core. • Also defined the locations of pre-placed cells. • We have encapsulated the Pre-placed Cells by Decoupling capacitor. • We will do the Power Planning for the Chip " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-8-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-8-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-8-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-8-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide9" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-8" alt="Power Planning Power Planning is to connect each cell in the design to the power source i.e. VDD and VSS. • If observed, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. • But on a chip, it becomes necessary to have a grid structure for power source, with more than one 'vdd' and 'vss‘. 3/2/2013 9 " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-9-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-9-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-9-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-9-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide10" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-9" alt="We will convert the power lines into the Power Mesh. " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-10-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-10-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-10-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-10-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide11" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-10" alt="DECAP1 D Block a Block b 4 Pre-placed DECAP2 Cells Block c DECAP3 Die Core " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-11-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-11-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-11-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-11-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide12" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-11" alt="DECAP1 D Block a Block b 4 DECAP2 Block c DECAP3 Die Core " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-12-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-12-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-12-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-12-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide13" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-12" alt="DECAP1 D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-13-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-13-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-13-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-13-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide14" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-13" alt="DECAP1 D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-14-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-14-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-14-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-14-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide15" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-14" alt="DECAP1 D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-15-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-15-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-15-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-15-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide16" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-15" alt="DECAP1 D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-16-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-16-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-16-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-16-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide17" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-16" alt="DECAP1 D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd Contact " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-17-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-17-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-17-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-17-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide18" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-17" alt="DECAP1 D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd Contact " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-18-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-18-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-18-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-18-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide19" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-18" alt="DECAP1 D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd Contact " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-19-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-19-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-19-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-19-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide20" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-19" alt="The Power mesh will look as below. " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-20-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-20-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-20-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-20-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide21" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-20" alt="Vss Vdd Contact " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-21-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-21-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-21-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-21-320.jpg" sizes="100vw"/></div></div></div><div><div id="slide22" class="VerticalSlide_root__jU_9r slide-item" style="aspect-ratio:720 / 540" data-cy="slide-container"><div class="VerticalSlideImage_root__64KSA"><img id="slide-image-21" alt="DECAP1 D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd Contact " class="vertical-slide-image VerticalSlideImage_image__VtE4p" data-testid="vertical-slide-image" loading="lazy" srcSet="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-22-320.jpg 320w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-22-638.jpg 638w, https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/75/Powerplanning-22-2048.jpg 2048w" src="https://image.slidesharecdn.com/powerplanning-130302112400-phpapp01/85/Powerplanning-22-320.jpg" sizes="100vw"/></div></div></div></div></div><div id="sidebar" class="sidebar hide-scrollbar Sidebar_root__1BbNu" style="--slots:8"><div class="above-recs-ad-wrapper AboveRecsAd_root__iTmTR"><div class="AboveRecsAd_desktopAd__ymykj"><div class="freestar-ad-container FreestarAdContainer_root__qPPC_" style="--fallback-aspect-ratio:300 / 260" data-testid="freestar-ad-container"><div><div class="" id="above-recs-desktop-ad-sm"></div></div></div></div></div><div class="rail-recs RailRecommendations_root__zqtZQ"><h2 class="RailRecommendations_title__kt1D2">Recommended</h2><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-0" aria-haspopup="dialog" aria-controls=":Rgql4f6:" popovertarget=":Rgql4f6:" style="anchor-name:--popover-Rgql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/physical-design-flow-challenges-at-28nm-on-multimillion-gate-blocks/46926242"><span class="sr-only">Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:0" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks" src="https://cdn.slidesharecdn.com/ss_thumbnails/einfochipsnileshranpuravineethv1-150413034320-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks" src="https://cdn.slidesharecdn.com/ss_thumbnails/einfochipsnileshranpuravineethv1-150413034320-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mgql4f6:" popovertarget=":R5mgql4f6:" style="anchor-name:--popover-R5mgql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mgql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mgql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/eInfochips_Solution">eInfochips (An Arrow Company)</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This is the presentation that was shared by Nilesh Ranpura and Vineeth Mathramkote at CDNLIVE 2015. The session briefs about the implementation challenges and covers the solution approach and how to achieve results</span></div></div><div class="" id=":Rgql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rgql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-1" aria-haspopup="dialog" aria-controls=":Rhal4f6:" popovertarget=":Rhal4f6:" style="anchor-name:--popover-Rhal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/physical-design-108881407/108881407"><span class="sr-only">Physical design </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:1" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Physical design " src="https://cdn.slidesharecdn.com/ss_thumbnails/physicaldesign-180807064635-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Physical design " src="https://cdn.slidesharecdn.com/ss_thumbnails/physicaldesign-180807064635-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Physical design </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Physical design for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mhal4f6:" popovertarget=":R5mhal4f6:" style="anchor-name:--popover-R5mhal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mhal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mhal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/Manjunathhosmani1">Manjunath hosmani</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Physical design involves taking a synthesized netlist as input and performing floorplanning, placement, and routing to produce a physical layout. Key inputs include the netlist, timing constraints, physical libraries, and technology files. The process involves floor planning to determine block placement and routing areas, power planning to create the power distribution network, and pre-routing of standard cells and power grids. The goal is to meet timing constraints while minimizing area.</span></div></div><div class="" id=":Rhal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rhal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-2" aria-haspopup="dialog" aria-controls=":Rhql4f6:" popovertarget=":Rhql4f6:" style="anchor-name:--popover-Rhql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/flip-chip-technology/44731371"><span class="sr-only">Flip Chip technology</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:2" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Flip Chip technology" src="https://cdn.slidesharecdn.com/ss_thumbnails/flipchip1-150216080723-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Flip Chip technology" src="https://cdn.slidesharecdn.com/ss_thumbnails/flipchip1-150216080723-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Flip Chip technology</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Flip Chip technology for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mhql4f6:" popovertarget=":R5mhql4f6:" style="anchor-name:--popover-R5mhql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mhql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mhql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/DeepakFloria">Mantra VLSI</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">flip chip technology, C4B, RDL routing, solder bump, bump technology, IO ring connection with Bump, Bump to pad routing using redistribution layer.</span></div></div><div class="" id=":Rhql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rhql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-3" aria-haspopup="dialog" aria-controls=":Rial4f6:" popovertarget=":Rial4f6:" style="anchor-name:--popover-Rial4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/timing-and-design-closure-in-physical-design-flows/59774393"><span class="sr-only">Timing and Design Closure in Physical Design Flows </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:3" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Timing and Design Closure in Physical Design Flows " src="https://cdn.slidesharecdn.com/ss_thumbnails/isqed2002-paper-160319220256-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Timing and Design Closure in Physical Design Flows " src="https://cdn.slidesharecdn.com/ss_thumbnails/isqed2002-paper-160319220256-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Timing and Design Closure in Physical Design Flows </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Timing and Design Closure in Physical Design Flows for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mial4f6:" popovertarget=":R5mial4f6:" style="anchor-name:--popover-R5mial4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mial4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mial4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ocoudert">Olivier Coudert</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. We focus on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow. </span></div></div><div class="" id=":Rial4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rial4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-4" aria-haspopup="dialog" aria-controls=":Riql4f6:" popovertarget=":Riql4f6:" style="anchor-name:--popover-Riql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/clock-tree-timing-101/67748105"><span class="sr-only">Clock Tree Timing 101</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:4" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Clock Tree Timing 101" src="https://cdn.slidesharecdn.com/ss_thumbnails/ebookclocktreetiming101-161027204158-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Clock Tree Timing 101" src="https://cdn.slidesharecdn.com/ss_thumbnails/ebookclocktreetiming101-161027204158-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Clock Tree Timing 101</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Clock Tree Timing 101 for later" role="switch" aria-haspopup="dialog" aria-controls=":R5miql4f6:" popovertarget=":R5miql4f6:" style="anchor-name:--popover-R5miql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5miql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5miql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/siliconlabs">Silicon Labs</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Silicon Labs offers the industry’s broadest portfolio of crystal oscillator, clock generator and clock buffer products and PCI Express (PCIe) clock generators and PCI Express buffers.</span></div></div><div class="" id=":Riql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Riql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-5" aria-haspopup="dialog" aria-controls=":Rjal4f6:" popovertarget=":Rjal4f6:" style="anchor-name:--popover-Rjal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/asic-backend-design/15804101"><span class="sr-only">Asic backend design</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:5" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Asic backend design" src="https://cdn.slidesharecdn.com/ss_thumbnails/asicpd-121230112948-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Asic backend design" src="https://cdn.slidesharecdn.com/ss_thumbnails/asicpd-121230112948-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Asic backend design</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Asic backend design for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mjal4f6:" popovertarget=":R5mjal4f6:" style="anchor-name:--popover-R5mjal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mjal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mjal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/kbipeen">kbipeen</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document provides an overview of the ASIC back-end design flow, including physical design steps like floorplanning, placement, clock tree synthesis, and routing. It describes how CAD tools like Astro are used to automate the complex physical design process and optimize a design for timing while meeting other constraints. Key aspects of the flow include floorplanning the design, performing timing-driven placement and routing, building clock trees, and verifying the final implementation against timing and functional requirements.</span></div></div><div class="" id=":Rjal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rjal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-6" aria-haspopup="dialog" aria-controls=":Rjql4f6:" popovertarget=":Rjql4f6:" style="anchor-name:--popover-Rjql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/basic-synthesis-flow-and-commands-in-digital-vlsi/237984417"><span class="sr-only">Basic synthesis flow and commands in digital VLSI</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:6" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Basic synthesis flow and commands in digital VLSI" src="https://cdn.slidesharecdn.com/ss_thumbnails/basicsynthesisflowandcommandsindigitalvlsi-200817143917-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Basic synthesis flow and commands in digital VLSI" src="https://cdn.slidesharecdn.com/ss_thumbnails/basicsynthesisflowandcommandsindigitalvlsi-200817143917-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Basic synthesis flow and commands in digital VLSI</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Basic synthesis flow and commands in digital VLSI for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mjql4f6:" popovertarget=":R5mjql4f6:" style="anchor-name:--popover-R5mjql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mjql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mjql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/SuryakantaMangaraj">Surya Raj</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses logic synthesis, including the basic synthesis flow and commands, synthesis script flow, technology libraries, design objects like cells and ports, timing paths, and constraints like defining clocks and input/output delays. It provides examples of setting library variables, reading and writing designs, and applying constraints to clocks and I/O. The document contains information on synthesis tools and processes at a high level.</span></div></div><div class="" id=":Rjql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rjql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-7" aria-haspopup="dialog" aria-controls=":Rkal4f6:" popovertarget=":Rkal4f6:" style="anchor-name:--popover-Rkal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/synopsys-fusion-compilercomprehensive-rtltogdsii-implementation-system/239633312"><span class="sr-only">Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:7" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System" src="https://cdn.slidesharecdn.com/ss_thumbnails/synopsysfusion-201201040138-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System" src="https://cdn.slidesharecdn.com/ss_thumbnails/synopsysfusion-201201040138-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mkal4f6:" popovertarget=":R5mkal4f6:" style="anchor-name:--popover-R5mkal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mkal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mkal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/mostafa_khamis">Mostafa Khamis</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Fusion Compiler is the next-generation RTL-to-GDSII implementation system architected to address the complexities of advanced node designs and deliver up to 20% improved PPA while reducing Time To Results (TTR) by 2X. </span></div></div><div class="" id=":Rkal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rkal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-8" aria-haspopup="dialog" aria-controls=":Rkql4f6:" popovertarget=":Rkql4f6:" style="anchor-name:--popover-Rkql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-physical-design-flow/14250868"><span class="sr-only">VLSI Physical Design Flow(http://www.vlsisystemdesign.com)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:8" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="VLSI Physical Design Flow(http://www.vlsisystemdesign.com)" src="https://cdn.slidesharecdn.com/ss_thumbnails/odijoopresentation1-120911110437-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="VLSI Physical Design Flow(http://www.vlsisystemdesign.com)" src="https://cdn.slidesharecdn.com/ss_thumbnails/odijoopresentation1-120911110437-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">VLSI Physical Design Flow(http://www.vlsisystemdesign.com)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save VLSI Physical Design Flow(http://www.vlsisystemdesign.com) for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mkql4f6:" popovertarget=":R5mkql4f6:" style="anchor-name:--popover-R5mkql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mkql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mkql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/vlsisyst">VLSI SYSTEM Design</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Learning becomes Fun.. When tedious & difficult topics like Chip Design are explained in simple n creative videos....https://www.udemy.com/vlsi-academy</span></div></div><div class="" id=":Rkql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rkql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-9" aria-haspopup="dialog" aria-controls=":Rlal4f6:" popovertarget=":Rlal4f6:" style="anchor-name:--popover-Rlal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/ShariefShaikSharief/multi-mode-multi-corner-mmmc"><span class="sr-only">Multi mode multi corner (mmmc)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:9" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Multi mode multi corner (mmmc)" src="https://cdn.slidesharecdn.com/ss_thumbnails/multimodemulticornermmmc-190215102744-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Multi mode multi corner (mmmc)" src="https://cdn.slidesharecdn.com/ss_thumbnails/multimodemulticornermmmc-190215102744-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Multi mode multi corner (mmmc)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Multi mode multi corner (mmmc) for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mlal4f6:" popovertarget=":R5mlal4f6:" style="anchor-name:--popover-R5mlal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mlal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mlal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ShariefShaikSharief">shaik sharief</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses multi mode multi corner (MMMC) analysis for chip design. It defines that a mode is a set of design parameters like clocks and timing constraints, and a corner captures process, voltage, and temperature variations. It provides examples of multiple modes like normal, sleep, and test modes and corners for temperature, voltage, process variations, and parasitic interconnects. The document gives an example of analyzing a chip with 4 modes under 3 process-voltage-temperature corners and 3 parasitic interconnect corners, showing 9 analysis cases.</span></div></div><div class="" id=":Rlal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rlal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-10" aria-haspopup="dialog" aria-controls=":Rlql4f6:" popovertarget=":Rlql4f6:" style="anchor-name:--popover-Rlql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/understanding-cts-logmessages/14763325"><span class="sr-only">Understanding cts log_messages</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:10" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Understanding cts log_messages" src="https://cdn.slidesharecdn.com/ss_thumbnails/understandingctslogmessages-121017042528-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Understanding cts log_messages" src="https://cdn.slidesharecdn.com/ss_thumbnails/understandingctslogmessages-121017042528-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Understanding cts log_messages</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Understanding cts log_messages for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mlql4f6:" popovertarget=":R5mlql4f6:" style="anchor-name:--popover-R5mlql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mlql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mlql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/mujahidmohammed94">Mujahid Mohammed</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Clock tree synthesis log messages provide information about: 1) Preprocessing steps like design updates, buffer characterization, and clock tree constraints. 2) The clock tree synthesis process which includes clustering, meeting timing targets, and reporting results. 3) Post processing steps like embedded clock tree optimization, DRC fixing, and placement legalization.</span></div></div><div class="" id=":Rlql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rlql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-11" aria-haspopup="dialog" aria-controls=":Rmal4f6:" popovertarget=":Rmal4f6:" style="anchor-name:--popover-Rmal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-floor-planning/16365140"><span class="sr-only">VLSI-Physical Design- Tool Terminalogy</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:11" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="VLSI-Physical Design- Tool Terminalogy" src="https://cdn.slidesharecdn.com/ss_thumbnails/hwkakoee2-130205113011-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="VLSI-Physical Design- Tool Terminalogy" src="https://cdn.slidesharecdn.com/ss_thumbnails/hwkakoee2-130205113011-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">VLSI-Physical Design- Tool Terminalogy</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save VLSI-Physical Design- Tool Terminalogy for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mmal4f6:" popovertarget=":R5mmal4f6:" style="anchor-name:--popover-R5mmal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mmal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mmal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/muralikancham">Murali Rai</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The physical design flow begins with placement which involves assigning exact locations to modules like gates and standard cells to minimize area and interconnect cost while meeting timing constraints, with the goal of enabling easier routing; placement tools take as input the netlist, floorplan, libraries, and constraints to perform global and detailed placement as well as optimization. The quality of placement significantly impacts the ability to route the design successfully.</span></div></div><div class="" id=":Rmal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rmal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-12" aria-haspopup="dialog" aria-controls=":Rmql4f6:" popovertarget=":Rmql4f6:" style="anchor-name:--popover-Rmql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/DeepakFloria/physical-design-41787809"><span class="sr-only">Physical design </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:12" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Physical design " src="https://cdn.slidesharecdn.com/ss_thumbnails/physicaldesign-141120002209-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Physical design " src="https://cdn.slidesharecdn.com/ss_thumbnails/physicaldesign-141120002209-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Physical design </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Physical design for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mmql4f6:" popovertarget=":R5mmql4f6:" style="anchor-name:--popover-R5mmql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mmql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mmql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/DeepakFloria">Mantra VLSI</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">VLSI Physical Design Data preparation, import design, floorplan Power planing power ring, core power, IO power ring, pad, bump creattion. Physical Verification.</span></div></div><div class="" id=":Rmql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rmql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-13" aria-haspopup="dialog" aria-controls=":Rnal4f6:" popovertarget=":Rnal4f6:" style="anchor-name:--popover-Rnal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/snug-presentation-final4/34267548"><span class="sr-only">Implementing Useful Clock Skew Using Skew Groups</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:13" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Implementing Useful Clock Skew Using Skew Groups" src="https://cdn.slidesharecdn.com/ss_thumbnails/snugpresentationfinal4-140504173230-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Implementing Useful Clock Skew Using Skew Groups" src="https://cdn.slidesharecdn.com/ss_thumbnails/snugpresentationfinal4-140504173230-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Implementing Useful Clock Skew Using Skew Groups</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Implementing Useful Clock Skew Using Skew Groups for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mnal4f6:" popovertarget=":R5mnal4f6:" style="anchor-name:--popover-R5mnal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mnal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mnal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/miaofei">M Mei</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Implementing useful skew through skew groups or manual buffer insertion can improve timing in a large memory block design. Skew groups define a target skew value for groups of clock pins before clock tree synthesis, resulting in a smaller clock tree, lower power increase, and less routing complexity compared to manual buffer insertion. Manual insertion precisely controls skew by adding buffers but dramatically increases clock cell count and power consumption versus skew groups. Both methods effectively improved setup timing for the memory block design.</span></div></div><div class="" id=":Rnal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rnal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-14" aria-haspopup="dialog" aria-controls=":Rnql4f6:" popovertarget=":Rnql4f6:" style="anchor-name:--popover-Rnql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/floor-plan-power-plan/76888278"><span class="sr-only">Floor plan & Power Plan </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:14" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Floor plan & Power Plan " src="https://cdn.slidesharecdn.com/ss_thumbnails/floorplan-170613043300-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Floor plan & Power Plan " src="https://cdn.slidesharecdn.com/ss_thumbnails/floorplan-170613043300-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Floor plan & Power Plan </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Floor plan & Power Plan for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mnql4f6:" popovertarget=":R5mnql4f6:" style="anchor-name:--popover-R5mnql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mnql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mnql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/pratyushamadapalli">Prathyusha Madapalli</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses floor planning, which is the first step in physical design. It involves defining the size of the chip, pre-placing hard macros, I/O pads, and defining the power grid. A good floorplan partitions the design into functional blocks, arranges the blocks on the chip, places macros and I/O pads, and decides on the power distribution. Key inputs to floorplanning include the netlist, physical and timing libraries, timing constraints, and power requirements. The document then discusses various aspects of floorplanning such as die size calculations, macro placement guidelines, and different types of physical cells.</span></div></div><div class="" id=":Rnql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rnql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-15" aria-haspopup="dialog" aria-controls=":Roal4f6:" popovertarget=":Roal4f6:" style="anchor-name:--popover-Roal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/physical-designcomplete/46117353"><span class="sr-only">Physical design-complete</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:15" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Physical design-complete" src="https://cdn.slidesharecdn.com/ss_thumbnails/physical-design-complete-150321120023-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Physical design-complete" src="https://cdn.slidesharecdn.com/ss_thumbnails/physical-design-complete-150321120023-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Physical design-complete</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Physical design-complete for later" role="switch" aria-haspopup="dialog" aria-controls=":R5moal4f6:" popovertarget=":R5moal4f6:" style="anchor-name:--popover-R5moal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5moal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5moal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/muralikancham">Murali Rai</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses various concepts related to physical design implementation. It describes the inputs and outputs of physical design tools, important checks to perform before starting design such as clock and high fanout net budgeting, and concepts like floorplanning, placement, routing, libraries, multi-voltage design, and clock tree synthesis and optimization.</span></div></div><div class="" id=":Roal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Roal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-16" aria-haspopup="dialog" aria-controls=":Roql4f6:" popovertarget=":Roql4f6:" style="anchor-name:--popover-Roql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/VishalYadav29718/zero-wire-load-modelpptx"><span class="sr-only">ZERO WIRE LOAD MODEL.pptx</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:16" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="ZERO WIRE LOAD MODEL.pptx" src="https://cdn.slidesharecdn.com/ss_thumbnails/zerowireloadmodel-220721062722-17cd71a4-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="ZERO WIRE LOAD MODEL.pptx" src="https://cdn.slidesharecdn.com/ss_thumbnails/zerowireloadmodel-220721062722-17cd71a4-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">ZERO WIRE LOAD MODEL.pptx</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save ZERO WIRE LOAD MODEL.pptx for later" role="switch" aria-haspopup="dialog" aria-controls=":R5moql4f6:" popovertarget=":R5moql4f6:" style="anchor-name:--popover-R5moql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5moql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5moql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/VishalYadav29718">VishalYadav29718</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only"> Here are the key points about setup time, hold time, and insertion delay in VLSI physical design: - Setup time is the minimum time before the clock edge that the data needs to be stable in order for it to be correctly captured by the flip-flop. - Hold time is the minimum time after the clock edge that the data needs to remain stable. It provides a "window" after the clock edge for the data to remain valid. - Insertion delay is the time it takes for the clock signal to propagate from the clock source to a flip-flop input pin through the clock tree. - During clock tree synthesis, the tool aims to balance the insertion delays across the clock tree to minimize</span></div></div><div class="" id=":Roql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Roql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-17" aria-haspopup="dialog" aria-controls=":Rpal4f6:" popovertarget=":Rpal4f6:" style="anchor-name:--popover-Rpal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/define-width-and-height-of-core-and-die/16322178"><span class="sr-only">Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:17" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F..." src="https://cdn.slidesharecdn.com/ss_thumbnails/pnrv1-130203063732-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F..." src="https://cdn.slidesharecdn.com/ss_thumbnails/pnrv1-130203063732-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F... for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mpal4f6:" popovertarget=":R5mpal4f6:" style="anchor-name:--popover-R5mpal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mpal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mpal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/vlsisyst">VLSI SYSTEM Design</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">https://www.udemy.com/vlsi-academy The very first step in chip design is floorplanning, in which the width and height of the chip, basically the area of the chip, is defined. A chip consists of two parts, 'core' and 'die'. </span></div></div><div class="" id=":Rpal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rpal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-18" aria-haspopup="dialog" aria-controls=":Rpql4f6:" popovertarget=":Rpql4f6:" style="anchor-name:--popover-Rpql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/pd-flow-i/88973050"><span class="sr-only">Pd flow i</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:18" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Pd flow i" src="https://cdn.slidesharecdn.com/ss_thumbnails/pdflowi-180226131140-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Pd flow i" src="https://cdn.slidesharecdn.com/ss_thumbnails/pdflowi-180226131140-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Pd flow i</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Pd flow i for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mpql4f6:" popovertarget=":R5mpql4f6:" style="anchor-name:--popover-R5mpql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mpql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mpql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/AlokKumar506">Alok Kumar</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">1. The document discusses the key steps in physical design flow, including import design, floorplanning, placement and routing. 2. Floorplanning is described as a critical step, where the quality of the floorplan can significantly impact timing closure and design implementation. Good techniques for floorplanning include understanding the design requirements and data flow. 3. The document outlines the major steps in floorplanning such as sizing and shaping blocks, voltage area creation, pin placement, row creation, macro placement, adding blockages and special cells. Qualifying the floorplan involves checks on pin grids, design rules, power connections and more.</span></div></div><div class="" id=":Rpql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rpql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-19" aria-haspopup="dialog" aria-controls=":Rqal4f6:" popovertarget=":Rqal4f6:" style="anchor-name:--popover-Rqal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/gui-for-drv-fix-in-icc2/64635361"><span class="sr-only">GUI for DRV fix in ICC2</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:19" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="GUI for DRV fix in ICC2" src="https://cdn.slidesharecdn.com/ss_thumbnails/guifordrvfix-160802204229-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="GUI for DRV fix in ICC2" src="https://cdn.slidesharecdn.com/ss_thumbnails/guifordrvfix-160802204229-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">GUI for DRV fix in ICC2</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save GUI for DRV fix in ICC2 for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mqal4f6:" popovertarget=":R5mqal4f6:" style="anchor-name:--popover-R5mqal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mqal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mqal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/PrashanthChokkarapu">Prashanth Chokkarapu</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This is a custom GUI, which eases fixing violations either by adding buffer, cloning or sizing. Drop down menu item is created in ICC2 layout window. Desired terminals can be selected by dragging or adding points in rectilinear fashion and desired locations can be selected for adding new buffer. </span></div></div><div class="" id=":Rqal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rqal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-20" aria-haspopup="dialog" aria-controls=":Rqql4f6:" popovertarget=":Rqql4f6:" style="anchor-name:--popover-Rqql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/AlanTran3/timing-closure-document"><span class="sr-only">Timing closure document</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:20" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Timing closure document" src="https://cdn.slidesharecdn.com/ss_thumbnails/timingclosuredocument-140529200816-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Timing closure document" src="https://cdn.slidesharecdn.com/ss_thumbnails/timingclosuredocument-140529200816-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Timing closure document</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Timing closure document for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mqql4f6:" popovertarget=":R5mqql4f6:" style="anchor-name:--popover-R5mqql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mqql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mqql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/AlanTran3">Alan Tran</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses timing closure in FPGA design flows. It explains that timing requirements include clock period/frequency, throughput, and latency. The timing-driven design flow in Lattice Diamond is outlined, highlighting key steps like defining timing constraints, running synthesis and implementation with timing analysis, and iterating to resolve issues. Timing constraints like input/output delays and exceptions are also covered.</span></div></div><div class="" id=":Rqql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rqql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-21" aria-haspopup="dialog" aria-controls=":Rral4f6:" popovertarget=":Rral4f6:" style="anchor-name:--popover-Rral4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/intellectual-property-in-vlsi/87032314"><span class="sr-only">Intellectual property in vlsi</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:21" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Intellectual property in vlsi" src="https://cdn.slidesharecdn.com/ss_thumbnails/intellectualpropertyinvlsi-180201092003-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Intellectual property in vlsi" src="https://cdn.slidesharecdn.com/ss_thumbnails/intellectualpropertyinvlsi-180201092003-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Intellectual property in vlsi</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Intellectual property in vlsi for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mral4f6:" popovertarget=":R5mral4f6:" style="anchor-name:--popover-R5mral4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mral4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mral4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/SaranshChoudhary2">Saransh Choudhary</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Intellectual property (IP) in VLSI design refers to reusable logic or functionality units that can be licensed and used as building blocks in chip designs. There are two main types of IP: hard IP, which includes a pre-designed layout, and soft IP, which is delivered as synthesizable code. Soft IP is more vulnerable to theft since it is in a synthesizable form. Memories are often delivered as hard IP since they require careful analog design and peripheral circuitry to be useful. IP differs from custom chip design in that it is created before a specific use, with the goal of reuse across multiple designs. The IP lifecycle involves initial creation through specification, design, testing, and documentation, followed by integration into</span></div></div><div class="" id=":Rral4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rral4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-22" aria-haspopup="dialog" aria-controls=":Rrql4f6:" popovertarget=":Rrql4f6:" style="anchor-name:--popover-Rrql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/asic-design-flow-physical-design-vlsi/147367912"><span class="sr-only">ASIC Design Flow | Physical Design | VLSI </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:22" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="ASIC Design Flow | Physical Design | VLSI " src="https://cdn.slidesharecdn.com/ss_thumbnails/asicdesign-190524032643-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="ASIC Design Flow | Physical Design | VLSI " src="https://cdn.slidesharecdn.com/ss_thumbnails/asicdesign-190524032643-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">ASIC Design Flow | Physical Design | VLSI </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save ASIC Design Flow | Physical Design | VLSI for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mrql4f6:" popovertarget=":R5mrql4f6:" style="anchor-name:--popover-R5mrql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mrql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mrql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/JayantSuthar1">Jayant Suthar</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document provides an overview of the ASIC design process, which includes the following main steps: 1. Front-end design including market research, specification, architecture, and RTL design. 2. Verification of the RTL code by verification engineers. 3. Synthesis of the RTL code into a gate-level netlist, followed by equivalence checking. 4. Physical design including placement and routing of standard cells, followed by extraction of parasitic components and timing analysis. 5. Physical verification including design rule checking and layout vs schematic checking.</span></div></div><div class="" id=":Rrql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rrql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-23" aria-haspopup="dialog" aria-controls=":Rsal4f6:" popovertarget=":Rsal4f6:" style="anchor-name:--popover-Rsal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/eco-86088953/86088953"><span class="sr-only">Eco</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:23" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Eco" src="https://cdn.slidesharecdn.com/ss_thumbnails/cvaue7ysvcwge7tvqfrz-signature-639e321f4c3f5d0e1de28845284efb2a4aa3a269cdb933ed274b8e43418cfdb9-poli-180112201509-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Eco" src="https://cdn.slidesharecdn.com/ss_thumbnails/cvaue7ysvcwge7tvqfrz-signature-639e321f4c3f5d0e1de28845284efb2a4aa3a269cdb933ed274b8e43418cfdb9-poli-180112201509-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Eco</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Eco for later" role="switch" aria-haspopup="dialog" aria-controls=":R5msal4f6:" popovertarget=":R5msal4f6:" style="anchor-name:--popover-R5msal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5msal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5msal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/venkatamekala1">Rajesh M</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses engineering change orders (ECOs) used to fix timing, functional, power, and clock issues after physical design and sign-off. It describes the motivation for ECOs due to tool limitations and differences between implementation and sign-off. Common ECO techniques are listed for timing (driver upsizing, buffer insertion, etc.), power (vt-swapping, downsizing, etc.), and metal-only ECOs. Timing ECO tools from Synopsys, Cadence, and other vendors are also mentioned. Upcoming ECO technologies like dynamic power optimization and automatic legalization are noted.</span></div></div><div class="" id=":Rsal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rsal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-24" aria-haspopup="dialog" aria-controls=":Rsql4f6:" popovertarget=":Rsql4f6:" style="anchor-name:--popover-Rsql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/placement-26813258/26813258"><span class="sr-only">Placement</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:24" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Placement" src="https://cdn.slidesharecdn.com/ss_thumbnails/placement-131003012154-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Placement" src="https://cdn.slidesharecdn.com/ss_thumbnails/placement-131003012154-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Placement</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Placement for later" role="switch" aria-haspopup="dialog" aria-controls=":R5msql4f6:" popovertarget=":R5msql4f6:" style="anchor-name:--popover-R5msql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5msql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5msql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/yogeshmusthyala">yogesh kumar</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses physical design and placement optimization in Cadence tools. It covers prerequisites for placement, goals of optimization including timing, power and area. It describes placement flow and discusses pre-placement, in-placement and post-placement optimization stages. Key techniques covered include zero interconnect timing analysis, scan chain handling, pre-placement optimization, congestion-driven placement, and post-placement optimization before and after clock tree synthesis.</span></div></div><div class="" id=":Rsql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rsql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-25" aria-haspopup="dialog" aria-controls=":Rtal4f6:" popovertarget=":Rtal4f6:" style="anchor-name:--popover-Rtal4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/placement-and-routing-in-full-custom-physical-design/10579348"><span class="sr-only">Placement and routing in full custom physical design</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:25" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Placement and routing in full custom physical design" src="https://cdn.slidesharecdn.com/ss_thumbnails/prppt-111213115844-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Placement and routing in full custom physical design" src="https://cdn.slidesharecdn.com/ss_thumbnails/prppt-111213115844-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Placement and routing in full custom physical design</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Placement and routing in full custom physical design for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mtal4f6:" popovertarget=":R5mtal4f6:" style="anchor-name:--popover-R5mtal4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mtal4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mtal4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/deeptishankardas">Deiptii Das</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses placement and routing in full custom VLSI design. Placement involves techniques like diffusion sharing, gate matrix layout, and common centroid to optimize area and performance. Routing creates physical interconnects and involves global routing, track assignment, detail routing, and search and repair to meet timing constraints while resolving design rule checking violations. The quality of placement impacts routability, and routing aims to minimize delay along critical paths through techniques like buffer insertion and wire sizing.</span></div></div><div class="" id=":Rtal4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rtal4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-26" aria-haspopup="dialog" aria-controls=":Rtql4f6:" popovertarget=":Rtql4f6:" style="anchor-name:--popover-Rtql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/asic-design-40306910/40306910"><span class="sr-only">ASIC DESIGN : PLACEMENT</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:26" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="ASIC DESIGN : PLACEMENT" src="https://cdn.slidesharecdn.com/ss_thumbnails/asicppts-141015103057-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="ASIC DESIGN : PLACEMENT" src="https://cdn.slidesharecdn.com/ss_thumbnails/asicppts-141015103057-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">ASIC DESIGN : PLACEMENT</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save ASIC DESIGN : PLACEMENT for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mtql4f6:" popovertarget=":R5mtql4f6:" style="anchor-name:--popover-R5mtql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mtql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mtql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/helloactiva">helloactiva</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses ASIC placement, which involves assigning exact locations to circuit components within a chip's core area. The goals of placement are to minimize the total interconnect length and costs while meeting timing requirements. It describes two main placement techniques - global placement, which groups cells to minimize interconnect between groups, and detailed placement, which further optimizes placement objectives. The document outlines various placement algorithms, goals, and trends like mixed-size placement and whitespace distribution to improve routability and performance.</span></div></div><div class="" id=":Rtql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rtql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-27" aria-haspopup="dialog" aria-controls=":Rual4f6:" popovertarget=":Rual4f6:" style="anchor-name:--popover-Rual4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-physical-design/21131175"><span class="sr-only">Vlsi physical design</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:27" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Vlsi physical design" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsiphysicaldesign-130513191024-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Vlsi physical design" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsiphysicaldesign-130513191024-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Vlsi physical design</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Vlsi physical design for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mual4f6:" popovertarget=":R5mual4f6:" style="anchor-name:--popover-R5mual4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mual4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mual4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/deepak2392">I World Tech</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses the physical design process for VLSI circuits. It describes the main steps as partitioning, floor planning and placement, routing, layout optimization, and extraction and verification. The goals of physical design are to minimize signal delays, interconnection area, and power usage. Physical design transforms the logical structure of a circuit into its physical layout.</span></div></div><div class="" id=":Rual4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rual4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-28" aria-haspopup="dialog" aria-controls=":Ruql4f6:" popovertarget=":Ruql4f6:" style="anchor-name:--popover-Ruql4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/floorplan-16323225/16323225"><span class="sr-only">Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:28" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)" src="https://cdn.slidesharecdn.com/ss_thumbnails/floorplan-130203075712-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)" src="https://cdn.slidesharecdn.com/ss_thumbnails/floorplan-130203075712-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php) for later" role="switch" aria-haspopup="dialog" aria-controls=":R5muql4f6:" popovertarget=":R5muql4f6:" style="anchor-name:--popover-R5muql4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5muql4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5muql4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/vlsisyst">VLSI SYSTEM Design</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">https://www.udemy.com/vlsi-academy Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. </span></div></div><div class="" id=":Ruql4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Ruql4f6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="recommended-card-description-29" aria-haspopup="dialog" aria-controls=":Rval4f6:" popovertarget=":Rval4f6:" style="anchor-name:--popover-Rval4f6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/need-of-decap/16883894"><span class="sr-only">Need of Decoupling Capacitor</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:29" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Need of Decoupling Capacitor" src="https://cdn.slidesharecdn.com/ss_thumbnails/needofdecap-130302115609-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Need of Decoupling Capacitor" src="https://cdn.slidesharecdn.com/ss_thumbnails/needofdecap-130302115609-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Need of Decoupling Capacitor</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Need of Decoupling Capacitor for later" role="switch" aria-haspopup="dialog" aria-controls=":R5mval4f6:" popovertarget=":R5mval4f6:" style="anchor-name:--popover-R5mval4f6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5mval4f6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5mval4f6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/vlsisyst">VLSI SYSTEM Design</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">https://www.udemy.com/vlsi-academy http://vlsisystemdesign.com/need_for_decap.php A decoupling capacitor is a capacitor, which is used decouple the critical cells from main power supply, in order to protect the cells from the disturbance occuring in the power distribution lines and source. The purpose of using decoupling capacitors is to deliver current to the gates during switching. Herein, we would peep inside the reasons for the distrubance occuring in the power distribution lines.</span></div></div><div class="" id=":Rval4f6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-Rval4f6"></div></div></div></div><div class="RelatedContent_root__29Np1"><div class="RelatedContent_wrapper__riU7l"><h2 class="Heading_heading__3MAvZ Heading_h2__f9yvs RelatedContent_title__QUhpL">More Related Content</h2><div class="bottom-recs BottomRecommendation_root__7aU9w"><h3 class="BottomRecommendation_title__SRj68">What's hot <span class="BottomRecommendation_count__4HpLo">(20)</span></h3><div class="BottomRecommendationContent_root__2qm4_"><div class="mobile-recs"><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-0" aria-haspopup="dialog" aria-controls=":R45ipkf6:" popovertarget=":R45ipkf6:" style="anchor-name:--popover-R45ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-physical-design-flow/14250868"><span class="sr-only">VLSI Physical Design Flow(http://www.vlsisystemdesign.com)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:0" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="VLSI Physical Design Flow(http://www.vlsisystemdesign.com)" src="https://cdn.slidesharecdn.com/ss_thumbnails/odijoopresentation1-120911110437-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="VLSI Physical Design Flow(http://www.vlsisystemdesign.com)" src="https://cdn.slidesharecdn.com/ss_thumbnails/odijoopresentation1-120911110437-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">VLSI Physical Design Flow(http://www.vlsisystemdesign.com)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save VLSI Physical Design Flow(http://www.vlsisystemdesign.com) for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dk5ipkf6:" popovertarget=":R1dk5ipkf6:" style="anchor-name:--popover-R1dk5ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dk5ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dk5ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/vlsisyst">VLSI SYSTEM Design</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Learning becomes Fun.. When tedious & difficult topics like Chip Design are explained in simple n creative videos....https://www.udemy.com/vlsi-academy</span></div></div><div class="" id=":R45ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R45ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-1" aria-haspopup="dialog" aria-controls=":R49ipkf6:" popovertarget=":R49ipkf6:" style="anchor-name:--popover-R49ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/ShariefShaikSharief/multi-mode-multi-corner-mmmc"><span class="sr-only">Multi mode multi corner (mmmc)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:1" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Multi mode multi corner (mmmc)" src="https://cdn.slidesharecdn.com/ss_thumbnails/multimodemulticornermmmc-190215102744-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Multi mode multi corner (mmmc)" src="https://cdn.slidesharecdn.com/ss_thumbnails/multimodemulticornermmmc-190215102744-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Multi mode multi corner (mmmc)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Multi mode multi corner (mmmc) for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dk9ipkf6:" popovertarget=":R1dk9ipkf6:" style="anchor-name:--popover-R1dk9ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dk9ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dk9ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ShariefShaikSharief">shaik sharief</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses multi mode multi corner (MMMC) analysis for chip design. It defines that a mode is a set of design parameters like clocks and timing constraints, and a corner captures process, voltage, and temperature variations. It provides examples of multiple modes like normal, sleep, and test modes and corners for temperature, voltage, process variations, and parasitic interconnects. The document gives an example of analyzing a chip with 4 modes under 3 process-voltage-temperature corners and 3 parasitic interconnect corners, showing 9 analysis cases.</span></div></div><div class="" id=":R49ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R49ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-2" aria-haspopup="dialog" aria-controls=":R4dipkf6:" popovertarget=":R4dipkf6:" style="anchor-name:--popover-R4dipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/understanding-cts-logmessages/14763325"><span class="sr-only">Understanding cts log_messages</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:2" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Understanding cts log_messages" src="https://cdn.slidesharecdn.com/ss_thumbnails/understandingctslogmessages-121017042528-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Understanding cts log_messages" src="https://cdn.slidesharecdn.com/ss_thumbnails/understandingctslogmessages-121017042528-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Understanding cts log_messages</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Understanding cts log_messages for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkdipkf6:" popovertarget=":R1dkdipkf6:" style="anchor-name:--popover-R1dkdipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkdipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkdipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/mujahidmohammed94">Mujahid Mohammed</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Clock tree synthesis log messages provide information about: 1) Preprocessing steps like design updates, buffer characterization, and clock tree constraints. 2) The clock tree synthesis process which includes clustering, meeting timing targets, and reporting results. 3) Post processing steps like embedded clock tree optimization, DRC fixing, and placement legalization.</span></div></div><div class="" id=":R4dipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4dipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-3" aria-haspopup="dialog" aria-controls=":R4hipkf6:" popovertarget=":R4hipkf6:" style="anchor-name:--popover-R4hipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-floor-planning/16365140"><span class="sr-only">VLSI-Physical Design- Tool Terminalogy</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:3" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="VLSI-Physical Design- Tool Terminalogy" src="https://cdn.slidesharecdn.com/ss_thumbnails/hwkakoee2-130205113011-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="VLSI-Physical Design- Tool Terminalogy" src="https://cdn.slidesharecdn.com/ss_thumbnails/hwkakoee2-130205113011-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">VLSI-Physical Design- Tool Terminalogy</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save VLSI-Physical Design- Tool Terminalogy for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkhipkf6:" popovertarget=":R1dkhipkf6:" style="anchor-name:--popover-R1dkhipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkhipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkhipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/muralikancham">Murali Rai</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The physical design flow begins with placement which involves assigning exact locations to modules like gates and standard cells to minimize area and interconnect cost while meeting timing constraints, with the goal of enabling easier routing; placement tools take as input the netlist, floorplan, libraries, and constraints to perform global and detailed placement as well as optimization. The quality of placement significantly impacts the ability to route the design successfully.</span></div></div><div class="" id=":R4hipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4hipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-4" aria-haspopup="dialog" aria-controls=":R4lipkf6:" popovertarget=":R4lipkf6:" style="anchor-name:--popover-R4lipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/DeepakFloria/physical-design-41787809"><span class="sr-only">Physical design </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:4" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Physical design " src="https://cdn.slidesharecdn.com/ss_thumbnails/physicaldesign-141120002209-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Physical design " src="https://cdn.slidesharecdn.com/ss_thumbnails/physicaldesign-141120002209-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Physical design </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Physical design for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dklipkf6:" popovertarget=":R1dklipkf6:" style="anchor-name:--popover-R1dklipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dklipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dklipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/DeepakFloria">Mantra VLSI</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">VLSI Physical Design Data preparation, import design, floorplan Power planing power ring, core power, IO power ring, pad, bump creattion. Physical Verification.</span></div></div><div class="" id=":R4lipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4lipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-5" aria-haspopup="dialog" aria-controls=":R4pipkf6:" popovertarget=":R4pipkf6:" style="anchor-name:--popover-R4pipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/snug-presentation-final4/34267548"><span class="sr-only">Implementing Useful Clock Skew Using Skew Groups</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:5" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Implementing Useful Clock Skew Using Skew Groups" src="https://cdn.slidesharecdn.com/ss_thumbnails/snugpresentationfinal4-140504173230-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Implementing Useful Clock Skew Using Skew Groups" src="https://cdn.slidesharecdn.com/ss_thumbnails/snugpresentationfinal4-140504173230-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Implementing Useful Clock Skew Using Skew Groups</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Implementing Useful Clock Skew Using Skew Groups for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkpipkf6:" popovertarget=":R1dkpipkf6:" style="anchor-name:--popover-R1dkpipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkpipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkpipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/miaofei">M Mei</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Implementing useful skew through skew groups or manual buffer insertion can improve timing in a large memory block design. Skew groups define a target skew value for groups of clock pins before clock tree synthesis, resulting in a smaller clock tree, lower power increase, and less routing complexity compared to manual buffer insertion. Manual insertion precisely controls skew by adding buffers but dramatically increases clock cell count and power consumption versus skew groups. Both methods effectively improved setup timing for the memory block design.</span></div></div><div class="" id=":R4pipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4pipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-6" aria-haspopup="dialog" aria-controls=":R4tipkf6:" popovertarget=":R4tipkf6:" style="anchor-name:--popover-R4tipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/floor-plan-power-plan/76888278"><span class="sr-only">Floor plan & Power Plan </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:6" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Floor plan & Power Plan " src="https://cdn.slidesharecdn.com/ss_thumbnails/floorplan-170613043300-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Floor plan & Power Plan " src="https://cdn.slidesharecdn.com/ss_thumbnails/floorplan-170613043300-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Floor plan & Power Plan </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Floor plan & Power Plan for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dktipkf6:" popovertarget=":R1dktipkf6:" style="anchor-name:--popover-R1dktipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dktipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dktipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/pratyushamadapalli">Prathyusha Madapalli</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses floor planning, which is the first step in physical design. It involves defining the size of the chip, pre-placing hard macros, I/O pads, and defining the power grid. A good floorplan partitions the design into functional blocks, arranges the blocks on the chip, places macros and I/O pads, and decides on the power distribution. Key inputs to floorplanning include the netlist, physical and timing libraries, timing constraints, and power requirements. The document then discusses various aspects of floorplanning such as die size calculations, macro placement guidelines, and different types of physical cells.</span></div></div><div class="" id=":R4tipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4tipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-7" aria-haspopup="dialog" aria-controls=":R51ipkf6:" popovertarget=":R51ipkf6:" style="anchor-name:--popover-R51ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/physical-designcomplete/46117353"><span class="sr-only">Physical design-complete</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:7" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Physical design-complete" src="https://cdn.slidesharecdn.com/ss_thumbnails/physical-design-complete-150321120023-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Physical design-complete" src="https://cdn.slidesharecdn.com/ss_thumbnails/physical-design-complete-150321120023-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Physical design-complete</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Physical design-complete for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl1ipkf6:" popovertarget=":R1dl1ipkf6:" style="anchor-name:--popover-R1dl1ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl1ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl1ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/muralikancham">Murali Rai</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses various concepts related to physical design implementation. It describes the inputs and outputs of physical design tools, important checks to perform before starting design such as clock and high fanout net budgeting, and concepts like floorplanning, placement, routing, libraries, multi-voltage design, and clock tree synthesis and optimization.</span></div></div><div class="" id=":R51ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R51ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-8" aria-haspopup="dialog" aria-controls=":R55ipkf6:" popovertarget=":R55ipkf6:" style="anchor-name:--popover-R55ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/VishalYadav29718/zero-wire-load-modelpptx"><span class="sr-only">ZERO WIRE LOAD MODEL.pptx</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:8" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="ZERO WIRE LOAD MODEL.pptx" src="https://cdn.slidesharecdn.com/ss_thumbnails/zerowireloadmodel-220721062722-17cd71a4-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="ZERO WIRE LOAD MODEL.pptx" src="https://cdn.slidesharecdn.com/ss_thumbnails/zerowireloadmodel-220721062722-17cd71a4-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">ZERO WIRE LOAD MODEL.pptx</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save ZERO WIRE LOAD MODEL.pptx for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl5ipkf6:" popovertarget=":R1dl5ipkf6:" style="anchor-name:--popover-R1dl5ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl5ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl5ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/VishalYadav29718">VishalYadav29718</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only"> Here are the key points about setup time, hold time, and insertion delay in VLSI physical design: - Setup time is the minimum time before the clock edge that the data needs to be stable in order for it to be correctly captured by the flip-flop. - Hold time is the minimum time after the clock edge that the data needs to remain stable. It provides a "window" after the clock edge for the data to remain valid. - Insertion delay is the time it takes for the clock signal to propagate from the clock source to a flip-flop input pin through the clock tree. - During clock tree synthesis, the tool aims to balance the insertion delays across the clock tree to minimize</span></div></div><div class="" id=":R55ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R55ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-9" aria-haspopup="dialog" aria-controls=":R59ipkf6:" popovertarget=":R59ipkf6:" style="anchor-name:--popover-R59ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/define-width-and-height-of-core-and-die/16322178"><span class="sr-only">Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:9" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F..." src="https://cdn.slidesharecdn.com/ss_thumbnails/pnrv1-130203063732-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F..." src="https://cdn.slidesharecdn.com/ss_thumbnails/pnrv1-130203063732-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F... for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl9ipkf6:" popovertarget=":R1dl9ipkf6:" style="anchor-name:--popover-R1dl9ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl9ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl9ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/vlsisyst">VLSI SYSTEM Design</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">https://www.udemy.com/vlsi-academy The very first step in chip design is floorplanning, in which the width and height of the chip, basically the area of the chip, is defined. A chip consists of two parts, 'core' and 'die'. </span></div></div><div class="" id=":R59ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R59ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-10" aria-haspopup="dialog" aria-controls=":R5dipkf6:" popovertarget=":R5dipkf6:" style="anchor-name:--popover-R5dipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/pd-flow-i/88973050"><span class="sr-only">Pd flow i</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:10" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Pd flow i" src="https://cdn.slidesharecdn.com/ss_thumbnails/pdflowi-180226131140-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Pd flow i" src="https://cdn.slidesharecdn.com/ss_thumbnails/pdflowi-180226131140-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Pd flow i</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Pd flow i for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dldipkf6:" popovertarget=":R1dldipkf6:" style="anchor-name:--popover-R1dldipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dldipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dldipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/AlokKumar506">Alok Kumar</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">1. The document discusses the key steps in physical design flow, including import design, floorplanning, placement and routing. 2. Floorplanning is described as a critical step, where the quality of the floorplan can significantly impact timing closure and design implementation. Good techniques for floorplanning include understanding the design requirements and data flow. 3. The document outlines the major steps in floorplanning such as sizing and shaping blocks, voltage area creation, pin placement, row creation, macro placement, adding blockages and special cells. Qualifying the floorplan involves checks on pin grids, design rules, power connections and more.</span></div></div><div class="" id=":R5dipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5dipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-11" aria-haspopup="dialog" aria-controls=":R5hipkf6:" popovertarget=":R5hipkf6:" style="anchor-name:--popover-R5hipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/gui-for-drv-fix-in-icc2/64635361"><span class="sr-only">GUI for DRV fix in ICC2</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:11" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="GUI for DRV fix in ICC2" src="https://cdn.slidesharecdn.com/ss_thumbnails/guifordrvfix-160802204229-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="GUI for DRV fix in ICC2" src="https://cdn.slidesharecdn.com/ss_thumbnails/guifordrvfix-160802204229-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">GUI for DRV fix in ICC2</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save GUI for DRV fix in ICC2 for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dlhipkf6:" popovertarget=":R1dlhipkf6:" style="anchor-name:--popover-R1dlhipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dlhipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dlhipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/PrashanthChokkarapu">Prashanth Chokkarapu</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This is a custom GUI, which eases fixing violations either by adding buffer, cloning or sizing. Drop down menu item is created in ICC2 layout window. Desired terminals can be selected by dragging or adding points in rectilinear fashion and desired locations can be selected for adding new buffer. </span></div></div><div class="" id=":R5hipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5hipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-12" aria-haspopup="dialog" aria-controls=":R5lipkf6:" popovertarget=":R5lipkf6:" style="anchor-name:--popover-R5lipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/AlanTran3/timing-closure-document"><span class="sr-only">Timing closure document</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:12" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Timing closure document" src="https://cdn.slidesharecdn.com/ss_thumbnails/timingclosuredocument-140529200816-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Timing closure document" src="https://cdn.slidesharecdn.com/ss_thumbnails/timingclosuredocument-140529200816-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Timing closure document</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Timing closure document for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dllipkf6:" popovertarget=":R1dllipkf6:" style="anchor-name:--popover-R1dllipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dllipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dllipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/AlanTran3">Alan Tran</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses timing closure in FPGA design flows. It explains that timing requirements include clock period/frequency, throughput, and latency. The timing-driven design flow in Lattice Diamond is outlined, highlighting key steps like defining timing constraints, running synthesis and implementation with timing analysis, and iterating to resolve issues. Timing constraints like input/output delays and exceptions are also covered.</span></div></div><div class="" id=":R5lipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5lipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-13" aria-haspopup="dialog" aria-controls=":R5pipkf6:" popovertarget=":R5pipkf6:" style="anchor-name:--popover-R5pipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/intellectual-property-in-vlsi/87032314"><span class="sr-only">Intellectual property in vlsi</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:13" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Intellectual property in vlsi" src="https://cdn.slidesharecdn.com/ss_thumbnails/intellectualpropertyinvlsi-180201092003-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Intellectual property in vlsi" src="https://cdn.slidesharecdn.com/ss_thumbnails/intellectualpropertyinvlsi-180201092003-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Intellectual property in vlsi</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Intellectual property in vlsi for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dlpipkf6:" popovertarget=":R1dlpipkf6:" style="anchor-name:--popover-R1dlpipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dlpipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dlpipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/SaranshChoudhary2">Saransh Choudhary</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Intellectual property (IP) in VLSI design refers to reusable logic or functionality units that can be licensed and used as building blocks in chip designs. There are two main types of IP: hard IP, which includes a pre-designed layout, and soft IP, which is delivered as synthesizable code. Soft IP is more vulnerable to theft since it is in a synthesizable form. Memories are often delivered as hard IP since they require careful analog design and peripheral circuitry to be useful. IP differs from custom chip design in that it is created before a specific use, with the goal of reuse across multiple designs. The IP lifecycle involves initial creation through specification, design, testing, and documentation, followed by integration into</span></div></div><div class="" id=":R5pipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5pipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-14" aria-haspopup="dialog" aria-controls=":R5tipkf6:" popovertarget=":R5tipkf6:" style="anchor-name:--popover-R5tipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/asic-design-flow-physical-design-vlsi/147367912"><span class="sr-only">ASIC Design Flow | Physical Design | VLSI </span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:14" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="ASIC Design Flow | Physical Design | VLSI " src="https://cdn.slidesharecdn.com/ss_thumbnails/asicdesign-190524032643-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="ASIC Design Flow | Physical Design | VLSI " src="https://cdn.slidesharecdn.com/ss_thumbnails/asicdesign-190524032643-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">ASIC Design Flow | Physical Design | VLSI </span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save ASIC Design Flow | Physical Design | VLSI for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dltipkf6:" popovertarget=":R1dltipkf6:" style="anchor-name:--popover-R1dltipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dltipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dltipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/JayantSuthar1">Jayant Suthar</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document provides an overview of the ASIC design process, which includes the following main steps: 1. Front-end design including market research, specification, architecture, and RTL design. 2. Verification of the RTL code by verification engineers. 3. Synthesis of the RTL code into a gate-level netlist, followed by equivalence checking. 4. Physical design including placement and routing of standard cells, followed by extraction of parasitic components and timing analysis. 5. Physical verification including design rule checking and layout vs schematic checking.</span></div></div><div class="" id=":R5tipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5tipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-15" aria-haspopup="dialog" aria-controls=":R61ipkf6:" popovertarget=":R61ipkf6:" style="anchor-name:--popover-R61ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/eco-86088953/86088953"><span class="sr-only">Eco</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:15" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Eco" src="https://cdn.slidesharecdn.com/ss_thumbnails/cvaue7ysvcwge7tvqfrz-signature-639e321f4c3f5d0e1de28845284efb2a4aa3a269cdb933ed274b8e43418cfdb9-poli-180112201509-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Eco" src="https://cdn.slidesharecdn.com/ss_thumbnails/cvaue7ysvcwge7tvqfrz-signature-639e321f4c3f5d0e1de28845284efb2a4aa3a269cdb933ed274b8e43418cfdb9-poli-180112201509-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Eco</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Eco for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dm1ipkf6:" popovertarget=":R1dm1ipkf6:" style="anchor-name:--popover-R1dm1ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dm1ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dm1ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/venkatamekala1">Rajesh M</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses engineering change orders (ECOs) used to fix timing, functional, power, and clock issues after physical design and sign-off. It describes the motivation for ECOs due to tool limitations and differences between implementation and sign-off. Common ECO techniques are listed for timing (driver upsizing, buffer insertion, etc.), power (vt-swapping, downsizing, etc.), and metal-only ECOs. Timing ECO tools from Synopsys, Cadence, and other vendors are also mentioned. Upcoming ECO technologies like dynamic power optimization and automatic legalization are noted.</span></div></div><div class="" id=":R61ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R61ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-16" aria-haspopup="dialog" aria-controls=":R65ipkf6:" popovertarget=":R65ipkf6:" style="anchor-name:--popover-R65ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/placement-26813258/26813258"><span class="sr-only">Placement</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:16" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Placement" src="https://cdn.slidesharecdn.com/ss_thumbnails/placement-131003012154-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Placement" src="https://cdn.slidesharecdn.com/ss_thumbnails/placement-131003012154-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Placement</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Placement for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dm5ipkf6:" popovertarget=":R1dm5ipkf6:" style="anchor-name:--popover-R1dm5ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dm5ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dm5ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/yogeshmusthyala">yogesh kumar</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses physical design and placement optimization in Cadence tools. It covers prerequisites for placement, goals of optimization including timing, power and area. It describes placement flow and discusses pre-placement, in-placement and post-placement optimization stages. Key techniques covered include zero interconnect timing analysis, scan chain handling, pre-placement optimization, congestion-driven placement, and post-placement optimization before and after clock tree synthesis.</span></div></div><div class="" id=":R65ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R65ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-17" aria-haspopup="dialog" aria-controls=":R69ipkf6:" popovertarget=":R69ipkf6:" style="anchor-name:--popover-R69ipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/placement-and-routing-in-full-custom-physical-design/10579348"><span class="sr-only">Placement and routing in full custom physical design</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:17" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Placement and routing in full custom physical design" src="https://cdn.slidesharecdn.com/ss_thumbnails/prppt-111213115844-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Placement and routing in full custom physical design" src="https://cdn.slidesharecdn.com/ss_thumbnails/prppt-111213115844-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Placement and routing in full custom physical design</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Placement and routing in full custom physical design for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dm9ipkf6:" popovertarget=":R1dm9ipkf6:" style="anchor-name:--popover-R1dm9ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dm9ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dm9ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/deeptishankardas">Deiptii Das</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses placement and routing in full custom VLSI design. Placement involves techniques like diffusion sharing, gate matrix layout, and common centroid to optimize area and performance. Routing creates physical interconnects and involves global routing, track assignment, detail routing, and search and repair to meet timing constraints while resolving design rule checking violations. The quality of placement impacts routability, and routing aims to minimize delay along critical paths through techniques like buffer insertion and wire sizing.</span></div></div><div class="" id=":R69ipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R69ipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-18" aria-haspopup="dialog" aria-controls=":R6dipkf6:" popovertarget=":R6dipkf6:" style="anchor-name:--popover-R6dipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/asic-design-40306910/40306910"><span class="sr-only">ASIC DESIGN : PLACEMENT</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:18" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="ASIC DESIGN : PLACEMENT" src="https://cdn.slidesharecdn.com/ss_thumbnails/asicppts-141015103057-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="ASIC DESIGN : PLACEMENT" src="https://cdn.slidesharecdn.com/ss_thumbnails/asicppts-141015103057-conversion-gate01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">ASIC DESIGN : PLACEMENT</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save ASIC DESIGN : PLACEMENT for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dmdipkf6:" popovertarget=":R1dmdipkf6:" style="anchor-name:--popover-R1dmdipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dmdipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dmdipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/helloactiva">helloactiva</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This document discusses ASIC placement, which involves assigning exact locations to circuit components within a chip's core area. The goals of placement are to minimize the total interconnect length and costs while meeting timing requirements. It describes two main placement techniques - global placement, which groups cells to minimize interconnect between groups, and detailed placement, which further optimizes placement objectives. The document outlines various placement algorithms, goals, and trends like mixed-size placement and whitespace distribution to improve routability and performance.</span></div></div><div class="" id=":R6dipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R6dipkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="whatsHot-card-description-19" aria-haspopup="dialog" aria-controls=":R6hipkf6:" popovertarget=":R6hipkf6:" style="anchor-name:--popover-R6hipkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-physical-design/21131175"><span class="sr-only">Vlsi physical design</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:19" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Vlsi physical design" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsiphysicaldesign-130513191024-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Vlsi physical design" src="https://cdn.slidesharecdn.com/ss_thumbnails/vlsiphysicaldesign-130513191024-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Vlsi physical design</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Vlsi physical design for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dmhipkf6:" popovertarget=":R1dmhipkf6:" style="anchor-name:--popover-R1dmhipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dmhipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dmhipkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/deepak2392">I World Tech</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document discusses the physical design process for VLSI circuits. It describes the main steps as partitioning, floor planning and placement, routing, layout optimization, and extraction and verification. The goals of physical design are to minimize signal delays, interconnection area, and power usage. Physical design transforms the logical structure of a circuit into its physical layout.</span></div></div><div class="" id=":R6hipkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R6hipkf6"></div></div><div class="desktop-recs"><div class="Slider_root__c0Jo8"><div class="Slider_scroller__KHjw4"><div class="BottomRecommendationCard_root__gffTk SlideshowCard_root__pD8t4 slideshow-card"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/vlsi-physical-design-flow/14250868"><span class="sr-only">VLSI Physical Design Flow(http://www.vlsisystemdesign.com)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:16 / 9;--index:0" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="VLSI Physical Design Flow(http://www.vlsisystemdesign.com)" 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corner (mmmc)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Multi mode multi corner (mmmc) for later" role="switch" aria-haspopup="dialog" aria-controls=":R5h6ipkf6:" popovertarget=":R5h6ipkf6:" style="anchor-name:--popover-R5h6ipkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R5h6ipkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R5h6ipkf6"></div><a class="SlideshowAuthor_root__IkT1_ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" 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slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/vlsisyst">VLSI SYSTEM Design</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">https://www.udemy.com/vlsi-academy http://vlsisystemdesign.com/need_for_decap.php A decoupling capacitor is a capacitor, which is used decouple the critical cells from main power supply, in order to protect the cells from the disturbance occuring in the power distribution lines and source. The purpose of using decoupling capacitors is to deliver current to the gates during switching. Herein, we would peep inside the reasons for the distrubance occuring in the power distribution lines.</span></div></div><div class="" id=":R29j9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R29j9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-2" aria-haspopup="dialog" aria-controls=":R2dj9kf6:" popovertarget=":R2dj9kf6:" style="anchor-name:--popover-R2dj9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/define-location-of-preplaced-cells/16323144"><span class="sr-only">Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:2" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)" src="https://cdn.slidesharecdn.com/ss_thumbnails/definelocpreplacedcells-130203074907-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)" src="https://cdn.slidesharecdn.com/ss_thumbnails/definelocpreplacedcells-130203074907-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php) for later" role="switch" aria-haspopup="dialog" aria-controls=":Rmqdj9kf6:" popovertarget=":Rmqdj9kf6:" style="anchor-name:--popover-Rmqdj9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":Rmqdj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-Rmqdj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/vlsisyst">VLSI SYSTEM Design</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">https://www.udemy.com/vlsi-academy During placement and routing, most of the placement tools, place/move logic cells based on floorplan specifications. Some of the important or critical cell's locations has to be pre-defined before actual placement and routing stages. The critical cells are mostly the cells related to clocks, viz. clock buffers, clock mux, etc. and also few other cells such as RAM's, ROM,s etc. Since, these cells are placed in to core before placement and routing stage, they are called 'preplaced cells'. </span></div></div><div class="" id=":R2dj9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R2dj9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-3" aria-haspopup="dialog" aria-controls=":R2hj9kf6:" popovertarget=":R2hj9kf6:" style="anchor-name:--popover-R2hj9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/synthesis-10555152/10555152"><span class="sr-only">Synthesis</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:3" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Synthesis" src="https://cdn.slidesharecdn.com/ss_thumbnails/synthesis-111211215549-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Synthesis" src="https://cdn.slidesharecdn.com/ss_thumbnails/synthesis-111211215549-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Synthesis</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Synthesis for later" role="switch" aria-haspopup="dialog" aria-controls=":Rmqhj9kf6:" popovertarget=":Rmqhj9kf6:" style="anchor-name:--popover-Rmqhj9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":Rmqhj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-Rmqhj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/DeepakFloria">Mantra VLSI</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document describes how different Verilog code constructs are synthesized to hardware. It provides examples of how always blocks, variables assignments, if/else statements, case statements, mathematical operations, counters and other code are mapped to logic gates, flip-flops and other digital circuits.</span></div></div><div class="" id=":R2hj9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R2hj9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-4" aria-haspopup="dialog" aria-controls=":R2lj9kf6:" popovertarget=":R2lj9kf6:" style="anchor-name:--popover-R2lj9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/verilog-code/14913105"><span class="sr-only">verilog code</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:4" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="verilog code" src="https://cdn.slidesharecdn.com/ss_thumbnails/verilogcode-121027132700-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="verilog code" src="https://cdn.slidesharecdn.com/ss_thumbnails/verilogcode-121027132700-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">verilog code</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save verilog code for later" role="switch" aria-haspopup="dialog" aria-controls=":Rmqlj9kf6:" popovertarget=":Rmqlj9kf6:" style="anchor-name:--popover-Rmqlj9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":Rmqlj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-Rmqlj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/DeepakFloria">Mantra VLSI</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">All the verilog which will cover all the interview question. cover complete knowledge of verilog. cover vlsi question. vlsi Interview question.</span></div></div><div class="" id=":R2lj9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R2lj9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-5" aria-haspopup="dialog" aria-controls=":R2pj9kf6:" popovertarget=":R2pj9kf6:" style="anchor-name:--popover-R2pj9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/number-system-41983310/41983310"><span class="sr-only">Number system</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:5" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Number system" src="https://cdn.slidesharecdn.com/ss_thumbnails/numbersystem-141124230150-conversion-gate02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Number system" src="https://cdn.slidesharecdn.com/ss_thumbnails/numbersystem-141124230150-conversion-gate02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Number system</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Number system for later" role="switch" aria-haspopup="dialog" aria-controls=":Rmqpj9kf6:" popovertarget=":Rmqpj9kf6:" style="anchor-name:--popover-Rmqpj9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":Rmqpj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-Rmqpj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/DeepakFloria">Mantra VLSI</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Digital number system, Binary Addition, Complemented number system, 1’s Complement, 2’s Complement, 8421 BCD Code, Gray Code, Excess-3 Code , Boolean Algebra, DeMorgan's Theorem</span></div></div><div class="" id=":R2pj9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R2pj9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-6" aria-haspopup="dialog" aria-controls=":R2tj9kf6:" popovertarget=":R2tj9kf6:" style="anchor-name:--popover-R2tj9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/basic-electronics-15190380/15190380"><span class="sr-only">Basic electronics</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:6" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Basic electronics" src="https://cdn.slidesharecdn.com/ss_thumbnails/basicelectronics-121115073938-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Basic electronics" src="https://cdn.slidesharecdn.com/ss_thumbnails/basicelectronics-121115073938-phpapp02-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Basic electronics</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Basic electronics for later" role="switch" aria-haspopup="dialog" aria-controls=":Rmqtj9kf6:" popovertarget=":Rmqtj9kf6:" style="anchor-name:--popover-Rmqtj9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":Rmqtj9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-Rmqtj9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/DeepakFloria">Mantra VLSI</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">The document summarizes basic digital logic gates and components including NOT, AND, OR, NAND, NOR, XOR, XNOR gates. It also discusses multiplexers, demultiplexers, half/full adders, half/full subtractors, encoders, decoders, and conversions between binary and gray codes.</span></div></div><div class="" id=":R2tj9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R2tj9kf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="alsoLiked-card-description-7" aria-haspopup="dialog" aria-controls=":R31j9kf6:" popovertarget=":R31j9kf6:" style="anchor-name:--popover-R31j9kf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/divide-by-n-clock/10570385"><span class="sr-only">Divide by N clock</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:7" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Divide by N clock" src="https://cdn.slidesharecdn.com/ss_thumbnails/clkdiv-111213000346-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Divide by N clock" src="https://cdn.slidesharecdn.com/ss_thumbnails/clkdiv-111213000346-phpapp01-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Divide by N clock</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Divide by N clock for later" role="switch" aria-haspopup="dialog" aria-controls=":Rmr1j9kf6:" popovertarget=":Rmr1j9kf6:" style="anchor-name:--popover-Rmr1j9kf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":Rmr1j9kf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-Rmr1j9kf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/DeepakFloria">Mantra VLSI</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">this presentation is based to construct different frequency divide by clock with reference to the system clock.</span></div></div><div class="" id=":R31j9kf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R31j9kf6"></div></div><div class="desktop-recs"><div class="Slider_root__c0Jo8"><div class="Slider_scroller__KHjw4"><div class="BottomRecommendationCard_root__gffTk SlideshowCard_root__pD8t4 slideshow-card"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/floorplan-16323225/16323225"><span class="sr-only">Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:16 / 9;--index:0" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)" 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video) - https://youtu.be/T4S0uZp1SHw Jim Twin V1 (French video) - https://youtu.be/02hCGRJnCoc Jim Twin OpenSource – https://youtu.be/mwnZjTNegXE Jim Twin Tmpt.me Platform – https://tmpt.app/@jimtwin Jim Blog Post - https://service-science.info/archives/6612 Jim EIT Article (Real Jim) - https://www.eitdigital.eu/newsroom/grow-digital-insights/personal-ai-digital-twins-the-future-of-human-interaction/ Jim EIT Talk (Real Jim) - https://youtu.be/_1X6bRfOqc4 Reid Hoffman (English video) - https://youtu.be/rgD2gmwCS10 John Wolpert wrote: Hey, if you want to work with me on making your twin Twinzie-style, let me know. I'm implementing Twinzie (trained AIs that can interact with each other, discover win/win opportunities without disclosing the session directly to the respective users) in Valuable -- buyer/seller negotiation without exposing the seller's item before a mutually agreeable price can be proposed. Also starting to get traction for same model with the consulting firm I work with, where they have Twinzies of each of the participants of an experience do private 1-1 sessions to create their own Twinzie, and when group sessions are conducted, ideas in the session can get a score on whether they truly resonate with the participants' gestalt intentions or whether the idea might do violence to someone's intention...without revealing those intentions or outing people. Even in a session with three or four people, the live scoring doesn't provide any real sense of who might not like the idea. It just gives the room a sense of true alignment or a sense that something hidden might need to be addressed. </span></div></div><div class="" id=":R45jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R45jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="latest-card-description-1" aria-haspopup="dialog" aria-controls=":R49jpkf6:" popovertarget=":R49jpkf6:" style="anchor-name:--popover-R49jpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/fuel-injection-in-spark-ignition-engine-petrol-engine/277011895"><span class="sr-only">Fuel Injection in Spark Ignition Engine (Petrol Engine)</span></a><div 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href="https://www.slideshare.net/NileshKumbhar21">NileshKumbhar21</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Engine fuel requirements, Simple carburetor, Complete Carburetor , Solex carburettor, A/F ratio, Electronic Petrol injection system (MPFI) like DMPFI, LMPFI– components such as sensors, ECU etc.</span></div></div><div class="" id=":R49jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R49jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="latest-card-description-2" aria-haspopup="dialog" aria-controls=":R4djpkf6:" popovertarget=":R4djpkf6:" style="anchor-name:--popover-R4djpkf6"><a class="SlideshowCardLink_root__p8KI7" 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src="https://cdn.slidesharecdn.com/ss_thumbnails/unit1dvwadamnvulnerablewebapplication-250318065911-b8df7c0c-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Unit 1 DVWA (Damn Vulnerable Web Application).docx" src="https://cdn.slidesharecdn.com/ss_thumbnails/unit1dvwadamnvulnerablewebapplication-250318065911-b8df7c0c-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Unit 1 DVWA (Damn Vulnerable Web Application).docx</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Unit 1 DVWA (Damn Vulnerable Web Application).docx for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkhjpkf6:" popovertarget=":R1dkhjpkf6:" style="anchor-name:--popover-R1dkhjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkhjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkhjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/ChatanBawankar">ChatanBawankar</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Damn Vulnerable Web Application (DVWA) is a deliberately insecure web application designed for security professionals, developers, and students to practice and learn web security vulnerabilities. It provides a safe environment to test and understand common web application security issues, such as SQL injection, XSS, CSRF, command execution, and more. DVWA has different security levels (low, medium, high, and impossible) to help users improve their ethical hacking and penetration testing skills. It is commonly used for security training and research purposes.</span></div></div><div class="" id=":R4hjpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4hjpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="latest-card-description-4" aria-haspopup="dialog" aria-controls=":R4ljpkf6:" popovertarget=":R4ljpkf6:" style="anchor-name:--popover-R4ljpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/requirement-engineering-and-software-requirement-specification/276807118"><span class="sr-only">Requirement Engineering and Software Requirement Specification</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:4" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Requirement Engineering and Software Requirement Specification" src="https://cdn.slidesharecdn.com/ss_thumbnails/unitirequirmentengg-250317101650-d4e16ce8-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Requirement Engineering and Software Requirement Specification" src="https://cdn.slidesharecdn.com/ss_thumbnails/unitirequirmentengg-250317101650-d4e16ce8-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Requirement Engineering and Software Requirement Specification</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Requirement Engineering and Software Requirement Specification for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkljpkf6:" popovertarget=":R1dkljpkf6:" style="anchor-name:--popover-R1dkljpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkljpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkljpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/NitinShelake4">NitinShelake4</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Requirements Capturing : Requirements Capturing,Prioritizing Requirements (Kano Diagram) Requirements Engineering Tasks, Functional Modeling & Information Flow (DFD, CFD).</span></div></div><div class="" id=":R4ljpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4ljpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="latest-card-description-5" aria-haspopup="dialog" aria-controls=":R4pjpkf6:" popovertarget=":R4pjpkf6:" style="anchor-name:--popover-R4pjpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/play-types-value-and-selection-of-play-material-play-therapy-pptx/276796459"><span class="sr-only">PLAY: Types, value and selection of play material PLAY THERAPY.pptx</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:5" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="PLAY: Types, value and selection of play material PLAY THERAPY.pptx" src="https://cdn.slidesharecdn.com/ss_thumbnails/playplaytherapy-250317054635-194dbf0e-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="PLAY: Types, value and selection of play material PLAY THERAPY.pptx" src="https://cdn.slidesharecdn.com/ss_thumbnails/playplaytherapy-250317054635-194dbf0e-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">PLAY: Types, value and selection of play material PLAY THERAPY.pptx</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save PLAY: Types, value and selection of play material PLAY THERAPY.pptx for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dkpjpkf6:" popovertarget=":R1dkpjpkf6:" style="anchor-name:--popover-R1dkpjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dkpjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dkpjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/pradeepabothu1">PRADEEP ABOTHU</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Play: Play is a fun and natural activity that children do on their own for enjoyment. It helps them grow and learn. Even adults can benefit from play in different ways. Play Therapy: Play therapy is a form of psychotherapy that helps children express their emotions, thoughts, and experiences through play. It is used to support their emotional and psychological well-being.</span></div></div><div class="" id=":R4pjpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4pjpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="latest-card-description-6" aria-haspopup="dialog" aria-controls=":R4tjpkf6:" popovertarget=":R4tjpkf6:" style="anchor-name:--popover-R4tjpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/pubh1000-module-5-priority-populations/276963162"><span class="sr-only">PUBH1000 - Module 5: Priority Populations</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:6" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="PUBH1000 - Module 5: Priority Populations" src="https://cdn.slidesharecdn.com/ss_thumbnails/m5tutes12025-250320082050-e526ce46-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="PUBH1000 - Module 5: Priority Populations" src="https://cdn.slidesharecdn.com/ss_thumbnails/m5tutes12025-250320082050-e526ce46-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">PUBH1000 - Module 5: Priority Populations</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save PUBH1000 - Module 5: Priority Populations for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dktjpkf6:" popovertarget=":R1dktjpkf6:" style="anchor-name:--popover-R1dktjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dktjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dktjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/JonathanHallett4">JonathanHallett4</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">.</span></div></div><div class="" id=":R4tjpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R4tjpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="latest-card-description-7" aria-haspopup="dialog" aria-controls=":R51jpkf6:" popovertarget=":R51jpkf6:" style="anchor-name:--popover-R51jpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/agile-development-and-scrum-extreme-programming/276807211"><span class="sr-only">Agile Development and Scrum, Extreme Programming</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:7" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Agile Development and Scrum, Extreme Programming" src="https://cdn.slidesharecdn.com/ss_thumbnails/agiledevelopmentnew-250317101919-7564d8ba-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Agile Development and Scrum, Extreme Programming" src="https://cdn.slidesharecdn.com/ss_thumbnails/agiledevelopmentnew-250317101919-7564d8ba-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Agile Development and Scrum, Extreme Programming</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Agile Development and Scrum, Extreme Programming for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl1jpkf6:" popovertarget=":R1dl1jpkf6:" style="anchor-name:--popover-R1dl1jpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl1jpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl1jpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/NitinShelake4">NitinShelake4</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Agile Development: Agile manifesto, agility and cost of change, agility principles, myth of planned development. Extreme Programming: XP values, process, industrial XP. SCRUM: process flow, scrum roles, scrum cycle description, product backlog, sprint planning meeting, sprint backlog, sprint execution, daily scrum meeting, maintaining sprint backlog and burn-down chart, sprint review and retrospective.</span></div></div><div class="" id=":R51jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R51jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="latest-card-description-8" aria-haspopup="dialog" aria-controls=":R55jpkf6:" popovertarget=":R55jpkf6:" style="anchor-name:--popover-R55jpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/new-widget-to-record-invoice-line-description-odoo-18/276909198"><span class="sr-only">New Widget to Record Invoice Line Description Odoo 18</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:8" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="New Widget to Record Invoice Line Description Odoo 18" src="https://cdn.slidesharecdn.com/ss_thumbnails/newwidgettorecordinvoicelinedescriptionodoo18-250319060824-38dd6db6-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="New Widget to Record Invoice Line Description Odoo 18" src="https://cdn.slidesharecdn.com/ss_thumbnails/newwidgettorecordinvoicelinedescriptionodoo18-250319060824-38dd6db6-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">New Widget to Record Invoice Line Description Odoo 18</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save New Widget to Record Invoice Line Description Odoo 18 for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dl5jpkf6:" popovertarget=":R1dl5jpkf6:" style="anchor-name:--popover-R1dl5jpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dl5jpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dl5jpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/CelineGeorge1">Celine George</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">As we know, Odoo launches every new version with a wide variety of changes both functional and technical so far. Likewise, in Odoo 18 also, there are a lot of new features which can fulfill the needs of the users adequately. In this slide, we are going to discuss a new feature added to Odoo 18’s Invoice line description.</span></div></div><div class="" id=":R55jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R55jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="latest-card-description-9" aria-haspopup="dialog" aria-controls=":R59jpkf6:" popovertarget=":R59jpkf6:" style="anchor-name:--popover-R59jpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/fuel-injection-in-compression-ignition-engine/277011896"><span class="sr-only">Fuel Injection in Compression Ignition Engine</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:9" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Fuel Injection in Compression Ignition Engine" src="https://cdn.slidesharecdn.com/ss_thumbnails/ch2fuelinjectioninci-250321101013-dac56607-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Fuel Injection in Compression Ignition Engine" src="https://cdn.slidesharecdn.com/ss_thumbnails/ch2fuelinjectioninci-250321101013-dac56607-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Fuel Injection in Compression Ignition Engine</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O 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SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Requirements of injection system, Types of injection systems – Individual pump, Common rail and Distributor systems, Unit injector, Types of fuel nozzles- single hole, multi hole, pintle, and pintaux, Electronic diesel injection system.</span></div></div><div class="" id=":R59jpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R59jpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="latest-card-description-10" aria-haspopup="dialog" aria-controls=":R5djpkf6:" popovertarget=":R5djpkf6:" style="anchor-name:--popover-R5djpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" 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src="https://cdn.slidesharecdn.com/ss_thumbnails/howocmodelsalignwithatrlegislationrequirements-32025-250320170438-eb492f46-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Opportunity Culture Models & ATR Legislation" src="https://cdn.slidesharecdn.com/ss_thumbnails/howocmodelsalignwithatrlegislationrequirements-32025-250320170438-eb492f46-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Opportunity Culture Models & ATR Legislation</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Opportunity Culture Models & ATR Legislation for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dlljpkf6:" popovertarget=":R1dlljpkf6:" style="anchor-name:--popover-R1dlljpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dlljpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dlljpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/educationnc">EducationNC</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">This table from Public Impact and The Innovation Project shows how models from Public Impact, called Opportunity Culture models, align with North Carolina's Advanced Teaching Roles (ATR) legislative requirements. </span></div></div><div class="" id=":R5ljpkf6:" popover="manual" data-popover-position="bottom-start" style="position-anchor:--popover-R5ljpkf6"></div><div class="separator Separator_root__70Ime Separator_horizontal__czVEa" style="--color:var(--blue-gray-200);--size:1px" role="separator"></div><div class="RailCard_root__rZUGY RailCard_hasDescription__MjSgf SlideshowCard_root__pD8t4 slideshow-card" aria-describedby="latest-card-description-13" aria-haspopup="dialog" aria-controls=":R5pjpkf6:" popovertarget=":R5pjpkf6:" style="anchor-name:--popover-R5pjpkf6"><a class="SlideshowCardLink_root__p8KI7" data-cy="slideshow-card-link" data-testid="slideshow-card-link" href="https://www.slideshare.net/slideshow/design-policy-and-strategy-in-the-expansion-of-global-economic-initiatives/276875445"><span class="sr-only">Design Policy and Strategy in the Expansion of Global Economic Initiatives</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:13" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Design Policy and Strategy in the Expansion of Global Economic Initiatives" src="https://cdn.slidesharecdn.com/ss_thumbnails/s03-250318145221-957eb6ec-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Design Policy and Strategy in the Expansion of Global Economic Initiatives" src="https://cdn.slidesharecdn.com/ss_thumbnails/s03-250318145221-957eb6ec-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Design Policy and Strategy in the Expansion of Global Economic Initiatives</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Design Policy and Strategy in the Expansion of Global Economic Initiatives for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dlpjpkf6:" popovertarget=":R1dlpjpkf6:" style="anchor-name:--popover-R1dlpjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dlpjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dlpjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" 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class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">How to Manage Your Company Budget Using Odoo 17 Accounting</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save How to Manage Your Company Budget Using Odoo 17 Accounting for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dltjpkf6:" popovertarget=":R1dltjpkf6:" style="anchor-name:--popover-R1dltjpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dltjpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dltjpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/CelineGeorge1">Celine George</a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Effective budget management is vital for a company's success. Odoo 17 streamlines financial management with tools for transactions, invoicing, and budgeting. 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href="https://www.slideshare.net/slideshow/recent-advances-in-insulin-therapy-a-comprehensive-overview/277041072"><span class="sr-only">Recent advances in Insulin therapy: A comprehensive overview</span></a><div class="slideshow-thumbnail Thumbnail_root__qLW0K SlideshowCard_thumb__86aJk" style="aspect-ratio:1.5;--index:16" data-testid="card-thumbnail"><img class="Thumbnail_thumb__UXO3a Thumbnail_blur__opK6A Thumbnail_cover__1zsIi" alt="Recent advances in Insulin therapy: A comprehensive overview" src="https://cdn.slidesharecdn.com/ss_thumbnails/recentadvancesininsulintherapy-250322071648-30ef759d-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/><img class="Thumbnail_thumb__UXO3a Thumbnail_contain__K6M0d" alt="Recent advances in Insulin therapy: A comprehensive overview" src="https://cdn.slidesharecdn.com/ss_thumbnails/recentadvancesininsulintherapy-250322071648-30ef759d-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">Recent advances in Insulin therapy: A comprehensive overview</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save Recent advances in Insulin therapy: A comprehensive overview for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dm5jpkf6:" popovertarget=":R1dm5jpkf6:" style="anchor-name:--popover-R1dm5jpkf6"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/save.ef1812e2.svg);background-color:currentColor"></span><span class="sr-only"></span></span></button><div class="Tooltip_root__7FS0Y" id=":R1dm5jpkf6:" popover="manual" data-popover-position="top" style="position-anchor:--popover-R1dm5jpkf6"></div><a class="SlideshowAuthor_root__IkT1_ RailCard_author__JYeYZ slideshow-author ellipsis" data-testid="slideshow-author" data-cy="slideshow-author" href="https://www.slideshare.net/doc21vignesh">Dr C Vignesh </a><div class="slideshow-stats SlideshowStats_root__EQOR1 RailCard_stats__ZvZms"> </div><span aria-hidden="true" class="seo-only">Recent Advances in Insulin Therapy: A Comprehensive Overview This presentation provides an in-depth overview of insulin therapy, covering its historical evolution, structure, mechanism of action, and recent advances. The session is designed to enhance understanding of insulin's role in diabetes management and the latest innovations in its therapeutic application. Key Highlights: ✅ Pancreatic Anatomy & Physiology – Understanding the endocrine function of the pancreas and insulin secretion mechanisms. ✅ Insulin Structure & Mechanism of Action – Exploring the biochemical structure, receptor interactions, and physiological regulation of insulin. ✅ Diabetes Mellitus (DM)– Definition, classification, diagnostic criteria, and complications associated with diabetes. ✅ Timeline of Insulin Development– A historical perspective on the discovery and evolution of insulin therapy. ✅ Recent Advances in Insulin Therapy – Discussion on novel insulin analogues (ultra-rapid, basal, and glucose-responsive insulins) and innovative insulin delivery systems (smart pens, closed-loop pumps, oral and inhaled insulins). This presentation is useful for medical students, healthcare professionals, and researchers interested in advancements in diabetes management. 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src="https://cdn.slidesharecdn.com/ss_thumbnails/howtosimplifyreconciliationprocessusingreconciliationmodelsusingodooaccounting-250319062000-76d6099a-thumbnail.jpg?width=560&fit=bounds" loading="lazy"/></div><div class="SlideshowCard_content__xh7kV slideshow-card-content"><span class="slideshow-title SlideshowTitle_root__2VccW RailCard_title__Tvfiv ellipsis" style="-webkit-line-clamp:2" data-cy="slideshow-title">How to Simplify Reconciliation Process using Reconciliation Models using odoo...</span><button type="button" class="Button_root__i1yp0 Button_secondary__hHiHI Button_text__ZT_3O Button_small__sqsEx Button_icon__1C4qi save-slideshow-button SaveButton_root__b6zuu" data-testid="button" aria-checked="false" aria-label="Save How to Simplify Reconciliation Process using Reconciliation Models using odoo... for later" role="switch" aria-haspopup="dialog" aria-controls=":R1dmdjpkf6:" popovertarget=":R1dmdjpkf6:" style="anchor-name:--popover-R1dmdjpkf6"><span class="icon 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id="between-recs-ad-2-container" class="freestar-ad-container FreestarAdContainer_root__qPPC_" style="--fallback-aspect-ratio:undefined / undefined" data-testid="freestar-ad-container"><div><div class="" id="between-recs-ad-2"></div></div></div></div></div><div class="Transcript_root__Vrf6Q"><h2 class="Transcript_title__YgAka"><span class="icon Icon_root__AjZyv" style="--size:24px"><span class="Icon_icon__4zzsG" style="mask-image:url(https://public.slidesharecdn.com/_next/static/media/file.5db1ba24.svg);background-color:currentColor"></span><span class="sr-only"></span></span>Powerplanning</h2><div><ul class="Transcript_list__faItj"><div><li>1. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#1">Floorplanning is basically </a> the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. </li></div><div><li>2. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#2">Floorplanning is basically </a> the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • Partition and synthesize larger designs into smaller modules consisting of IP’s and std cells </li></div><div><li>3. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#3">Floorplanning is basically </a> the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • Define width and Height of ‘core’ and ‘Die’ using the physical area of synthesized netlist, utilization factor and aspect ratio </li></div><div><li>4. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#4">Floorplanning is basically </a> the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • Define locations of pre-placed cells </li></div><div><li>5. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#5">Floorplanning is basically </a> the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • Place de-coupling capacitors surrounding pre-placed cells </li></div><div><li>6. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#6">Floorplanning is basically </a> the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • Power Planning </li></div><div><li>7. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#7">Floorplanning is basically </a> the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip. It is attained by following steps: • IO Pin/Pad placement </li></div><div><li>8. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#8">• We have </a> defined the Width and Height of the core. • Also defined the locations of pre-placed cells. • We have encapsulated the Pre-placed Cells by Decoupling capacitor. • We will do the Power Planning for the Chip </li></div><div><li>9. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#9">Power Planning Power Planning </a> is to connect each cell in the design to the power source i.e. VDD and VSS. • If observed, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. • But on a chip, it becomes necessary to have a grid structure for power source, with more than one 'vdd' and 'vss‘. 3/2/2013 9 </li></div><div><li>10. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#10">We will convert </a> the power lines into the Power Mesh. </li></div><div><li>11. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#11">DECAP1 </a> D Block a Block b 4 Pre-placed DECAP2 Cells Block c DECAP3 Die Core </li></div><div><li>12. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#12">DECAP1 </a> D Block a Block b 4 DECAP2 Block c DECAP3 Die Core </li></div><div><li>13. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#13">DECAP1 </a> D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd </li></div><div><li>14. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#14">DECAP1 </a> D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd </li></div><div><li>15. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#15">DECAP1 </a> D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd </li></div><div><li>16. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#16">DECAP1 </a> D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd </li></div><div><li>17. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#17">DECAP1 </a> D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd Contact </li></div><div><li>18. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#18">DECAP1 </a> D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd Contact </li></div><div><li>19. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#19">DECAP1 </a> D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd Contact </li></div><div><li>20. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#20">The Power mesh </a> will look as below. </li></div><div><li>21. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#21">Vss Vdd Contact </a></li></div><div><li>22. <a class="Transcript_link__MLbGS" href="https://www.slideshare.net/slideshow/powerplanning/16883536#22">DECAP1 </a> D Block a Block b 4 DECAP2 Block c DECAP3 Die Vss Core Vdd Contact </li></div></ul></div></div><dialog class="Modal_root__TYkzh FullscreenModal_root__efM9m" id=":R2kf6:"><div class="Modal_wrapper__4UTGq"><div class="modal-content Modal_content__R1F4d FullscreenModal_content__bQ6mt"></div></div></dialog><div class="ad textads banner-ads banner_ads ad-unit ad-zone ad-space adsbox ads prebid" style="position:absolute;height:1px"></div><footer class="Footer_footer__N3WmV"><div class="Footer_top__y0vfl" data-testid="footer-top"><div class="Footer_links__F2xFZ"><a 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11:24:00 UTC","description":"https://www.udemy.com/vlsi-academy\r\nUsually, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. 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aspect ratio\n ","Floorplanning is basically the arrangement of logical blocks (i.e.\nmultiplexer, AND, OR gates, buffers) on silicon chip.\n\nIt is attained by following steps:\n\n• Define locations of pre-placed cells\n ","Floorplanning is basically the arrangement of logical blocks (i.e.\nmultiplexer, AND, OR gates, buffers) on silicon chip.\n\nIt is attained by following steps:\n\n• Place de-coupling capacitors surrounding pre-placed cells\n ","Floorplanning is basically the arrangement of logical blocks (i.e.\nmultiplexer, AND, OR gates, buffers) on silicon chip.\n\nIt is attained by following steps:\n\n• Power Planning\n ","Floorplanning is basically the arrangement of logical blocks (i.e.\nmultiplexer, AND, OR gates, buffers) on silicon chip.\n\nIt is attained by following steps:\n\n• IO Pin/Pad placement\n ","• We have defined the Width and Height of the core.\n\n• Also defined the locations of pre-placed cells.\n\n• We have encapsulated the Pre-placed Cells by Decoupling capacitor.\n\n• We will do the Power Planning for the Chip\n ","Power Planning\n\n\nPower Planning is to connect each cell in the design to the power source i.e. VDD and VSS.\n\n\n\n\n • If observed, while drawing any circuit on\n paper, we have only one 'vdd' at the top\n and one 'vss' at the bottom.\n\n • But on a chip, it becomes necessary to\n have a grid structure for power source,\n with more than one 'vdd' and 'vss‘.\n\n\n\n\n 3/2/2013 9\n ","We will convert the power lines into the Power Mesh.\n ","DECAP1\n D\n Block a Block b\n 4\nPre-placed\n DECAP2\n Cells\n Block c\n DECAP3\n\n\n\n\n Die\n\n\n Core\n ","DECAP1\n D\nBlock a Block b\n 4\n DECAP2\n Block c\n DECAP3\n\n\n\n\n Die\n\n\n Core\n ","DECAP1\n D\n Block a Block b\n 4\n DECAP2\n Block c\n DECAP3\n\n\n\n\n Die\n\n\nVss Core\nVdd\n ","DECAP1\n D\n Block a Block b\n 4\n DECAP2\n Block c\n DECAP3\n\n\n\n\n Die\n\n\nVss Core\nVdd\n ","DECAP1\n D\n Block a Block b\n 4\n DECAP2\n Block c\n DECAP3\n\n\n\n\n Die\n\n\nVss Core\nVdd\n ","DECAP1\n D\n Block a Block b\n 4\n DECAP2\n Block c\n DECAP3\n\n\n\n\n Die\n\n\nVss Core\nVdd\n ","DECAP1\n D\n Block a Block b\n 4\n DECAP2\n Block c\n DECAP3\n\n\n\n\n Die\n\n\n Vss Core\n Vdd\nContact\n ","DECAP1\n D\n Block a Block b\n 4\n DECAP2\n Block c\n DECAP3\n\n\n\n\n Die\n\n\n Vss Core\n Vdd\nContact\n ","DECAP1\n D\n Block a Block b\n 4\n DECAP2\n Block c\n DECAP3\n\n\n\n\n Die\n\n\n Vss Core\n Vdd\nContact\n ","The Power mesh will look as below.\n ","Vss\n Vdd\nContact\n ","DECAP1\n D\n Block a Block b\n 4\n DECAP2\n Block c\n DECAP3\n\n\n\n\n Die\n\n\n Vss Core\n Vdd\nContact\n "],"twitterShareUrl":"https://twitter.com/intent/tweet?via=SlideShare\u0026text=Powerplanning+by+%40Anagha_Ghosh+https%3A%2F%2Fwww.slideshare.net%2Fslideshow%2Fpowerplanning%2F16883536","type":"presentation","viewStats":{"views":3297,"viewsFromEmbeds":957,"topEmbeds":[]},"recommendationsByLocation":{"rightRail":[{"algorithmId":"9","displayTitle":"Physical Design Flow Challenges at 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