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id="toc-Instruction_types-sublist" class="vector-toc-list"> <li id="toc-Data_handling_and_memory_operations" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Data_handling_and_memory_operations"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1.1</span> <span>Data handling and memory operations</span> </div> </a> <ul id="toc-Data_handling_and_memory_operations-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Arithmetic_and_logic_operations" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Arithmetic_and_logic_operations"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1.2</span> <span>Arithmetic and logic operations</span> </div> </a> <ul id="toc-Arithmetic_and_logic_operations-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Control_flow_operations" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Control_flow_operations"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1.3</span> <span>Control flow operations</span> </div> </a> <ul id="toc-Control_flow_operations-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Coprocessor_instructions" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Coprocessor_instructions"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1.4</span> <span>Coprocessor instructions</span> </div> </a> <ul id="toc-Coprocessor_instructions-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Complex_instructions" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Complex_instructions"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Complex instructions</span> </div> </a> <ul id="toc-Complex_instructions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Instruction_encoding" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Instruction_encoding"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Instruction encoding</span> </div> </a> <ul id="toc-Instruction_encoding-sublist" class="vector-toc-list"> <li id="toc-Number_of_operands" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Number_of_operands"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3.1</span> <span>Number of operands</span> </div> </a> <ul id="toc-Number_of_operands-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Register_pressure" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Register_pressure"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4</span> <span>Register pressure</span> </div> </a> <ul id="toc-Register_pressure-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Instruction_length" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Instruction_length"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.5</span> <span>Instruction length</span> </div> </a> <ul id="toc-Instruction_length-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Code_density" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Code_density"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.6</span> <span>Code density</span> </div> </a> <ul id="toc-Code_density-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Representation" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Representation"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.7</span> <span>Representation</span> </div> </a> <ul id="toc-Representation-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Design" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Design"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Design</span> </div> </a> <ul id="toc-Design-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Instruction_set_implementation" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Instruction_set_implementation"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Instruction set implementation</span> </div> </a> <ul id="toc-Instruction_set_implementation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">Instruction set architecture</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 33 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-33" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">33 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%85%D8%AC%D9%85%D9%88%D8%B9%D8%A9_%D8%AA%D8%B9%D9%84%D9%8A%D9%85%D8%A7%D8%AA" title="مجموعة تعليمات – Arabic" lang="ar" hreflang="ar" data-title="مجموعة تعليمات" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-be-x-old mw-list-item"><a href="https://be-tarask.wikipedia.org/wiki/%D0%90%D1%80%D1%85%D1%96%D1%82%D1%8D%D0%BA%D1%82%D1%83%D1%80%D0%B0_%D0%BD%D0%B0%D0%B1%D0%BE%D1%80%D1%83_%D1%96%D0%BD%D1%81%D1%82%D1%80%D1%83%D0%BA%D1%86%D1%8B%D1%8F%D1%9E" title="Архітэктура набору інструкцыяў – Belarusian (Taraškievica orthography)" lang="be-tarask" hreflang="be-tarask" data-title="Архітэктура набору інструкцыяў" data-language-autonym="Беларуская (тарашкевіца)" data-language-local-name="Belarusian (Taraškievica orthography)" class="interlanguage-link-target"><span>Беларуская (тарашкевіца)</span></a></li><li class="interlanguage-link interwiki-bg mw-list-item"><a href="https://bg.wikipedia.org/wiki/%D0%9D%D0%B0%D0%B1%D0%BE%D1%80_%D0%BE%D1%82_%D0%B8%D0%BD%D1%81%D1%82%D1%80%D1%83%D0%BA%D1%86%D0%B8%D0%B8" title="Набор от инструкции – Bulgarian" lang="bg" hreflang="bg" data-title="Набор от инструкции" data-language-autonym="Български" data-language-local-name="Bulgarian" class="interlanguage-link-target"><span>Български</span></a></li><li class="interlanguage-link interwiki-bs mw-list-item"><a href="https://bs.wikipedia.org/wiki/Arhitektura_seta_instrukcija" title="Arhitektura seta instrukcija – Bosnian" lang="bs" hreflang="bs" data-title="Arhitektura seta instrukcija" data-language-autonym="Bosanski" data-language-local-name="Bosnian" class="interlanguage-link-target"><span>Bosanski</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Arquitectura_del_conjunt_d%27instruccions" title="Arquitectura del conjunt d'instruccions – Catalan" lang="ca" hreflang="ca" data-title="Arquitectura del conjunt d'instruccions" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Befehlssatzarchitektur" title="Befehlssatzarchitektur – German" lang="de" hreflang="de" data-title="Befehlssatzarchitektur" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/K%C3%A4sustik" title="Käsustik – Estonian" lang="et" hreflang="et" data-title="Käsustik" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-el mw-list-item"><a href="https://el.wikipedia.org/wiki/%CE%91%CF%81%CF%87%CE%B9%CF%84%CE%B5%CE%BA%CF%84%CE%BF%CE%BD%CE%B9%CE%BA%CE%AE_%CF%83%CF%85%CE%BD%CF%8C%CE%BB%CE%BF%CF%85_%CE%B5%CE%BD%CF%84%CE%BF%CE%BB%CF%8E%CE%BD" title="Αρχιτεκτονική συνόλου εντολών – Greek" lang="el" hreflang="el" data-title="Αρχιτεκτονική συνόλου εντολών" data-language-autonym="Ελληνικά" data-language-local-name="Greek" class="interlanguage-link-target"><span>Ελληνικά</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Conjunto_de_instrucciones" title="Conjunto de instrucciones – Spanish" lang="es" hreflang="es" data-title="Conjunto de instrucciones" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%85%D8%AC%D9%85%D9%88%D8%B9%D9%87_%D8%AF%D8%B3%D8%AA%D9%88%D8%B1%D8%A7%D9%84%D8%B9%D9%85%D9%84" title="مجموعه دستورالعمل – Persian" lang="fa" hreflang="fa" data-title="مجموعه دستورالعمل" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-ga mw-list-item"><a href="https://ga.wikipedia.org/wiki/Tacar_treoracha" title="Tacar treoracha – Irish" lang="ga" hreflang="ga" data-title="Tacar treoracha" data-language-autonym="Gaeilge" data-language-local-name="Irish" class="interlanguage-link-target"><span>Gaeilge</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EB%AA%85%EB%A0%B9%EC%96%B4_%EC%A7%91%ED%95%A9" title="명령어 집합 – Korean" lang="ko" hreflang="ko" data-title="명령어 집합" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/Skup_naredbi" title="Skup naredbi – Croatian" lang="hr" hreflang="hr" data-title="Skup naredbi" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target"><span>Hrvatski</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Architettura_del_set_di_istruzioni" title="Architettura del set di istruzioni – Italian" lang="it" hreflang="it" data-title="Architettura del set di istruzioni" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/%D7%A1%D7%98_%D7%A4%D7%A7%D7%95%D7%93%D7%95%D7%AA" title="סט פקודות – Hebrew" lang="he" hreflang="he" data-title="סט פקודות" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-lv mw-list-item"><a href="https://lv.wikipedia.org/wiki/Instrukciju_kopa" title="Instrukciju kopa – Latvian" lang="lv" hreflang="lv" data-title="Instrukciju kopa" data-language-autonym="Latviešu" data-language-local-name="Latvian" class="interlanguage-link-target"><span>Latviešu</span></a></li><li class="interlanguage-link interwiki-lmo mw-list-item"><a href="https://lmo.wikipedia.org/wiki/Instruction_Set_Architecture" title="Instruction Set Architecture – Lombard" lang="lmo" hreflang="lmo" data-title="Instruction Set Architecture" data-language-autonym="Lombard" data-language-local-name="Lombard" class="interlanguage-link-target"><span>Lombard</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/Utas%C3%ADt%C3%A1sk%C3%A9szlet" title="Utasításkészlet – Hungarian" lang="hu" hreflang="hu" data-title="Utasításkészlet" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-mk mw-list-item"><a href="https://mk.wikipedia.org/wiki/%D0%9D%D0%B0%D1%80%D0%B5%D0%B4%D0%B1%D0%B5%D0%BD%D0%BE_%D0%BC%D0%BD%D0%BE%D0%B6%D0%B5%D1%81%D1%82%D0%B2%D0%BE" title="Наредбено множество – Macedonian" lang="mk" hreflang="mk" data-title="Наредбено множество" data-language-autonym="Македонски" data-language-local-name="Macedonian" class="interlanguage-link-target"><span>Македонски</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%87%E0%B5%BB%E0%B4%B8%E0%B5%8D%E0%B4%9F%E0%B5%8D%E0%B4%B0%E0%B4%95%E0%B5%8D%E0%B4%B7%E0%B5%BB_%E0%B4%B8%E0%B5%86%E0%B4%B1%E0%B5%8D%E0%B4%B1%E0%B5%8D_%E0%B4%86%E0%B5%BC%E0%B4%95%E0%B5%8D%E0%B4%95%E0%B4%BF%E0%B4%9F%E0%B5%86%E0%B4%95%E0%B5%8D%E0%B4%9A%E0%B5%BC" title="ഇൻസ്ട്രക്ഷൻ സെറ്റ് ആർക്കിടെക്ചർ – Malayalam" lang="ml" hreflang="ml" data-title="ഇൻസ്ട്രക്ഷൻ സെറ്റ് ആർക്കിടെക്ചർ" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-mn mw-list-item"><a href="https://mn.wikipedia.org/wiki/%D0%9A%D0%BE%D0%BC%D0%B0%D0%BD%D0%B4%D1%8B%D0%BD_%D0%B1%D0%B0%D0%B3%D1%86" title="Командын багц – Mongolian" lang="mn" hreflang="mn" data-title="Командын багц" data-language-autonym="Монгол" data-language-local-name="Mongolian" class="interlanguage-link-target"><span>Монгол</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Architektura_zestawu_instrukcji" title="Architektura zestawu instrukcji – Polish" lang="pl" hreflang="pl" data-title="Architektura zestawu instrukcji" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/%D0%90%D1%80%D1%85%D0%B8%D1%82%D0%B5%D0%BA%D1%82%D1%83%D1%80%D0%B0_%D0%BD%D0%B0%D0%B1%D0%BE%D1%80%D0%B0_%D0%BA%D0%BE%D0%BC%D0%B0%D0%BD%D0%B4" title="Архитектура набора команд – Russian" lang="ru" hreflang="ru" data-title="Архитектура набора команд" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/In%C5%A1truk%C4%8Dn%C3%BD_s%C3%BAbor" title="Inštrukčný súbor – Slovak" lang="sk" hreflang="sk" data-title="Inštrukčný súbor" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-ckb mw-list-item"><a href="https://ckb.wikipedia.org/wiki/%DA%A9%DB%86%D9%85%DB%95%DA%B5%DB%95_%D9%81%DB%95%D8%B1%D9%85%D8%A7%D9%86" title="کۆمەڵە فەرمان – Central Kurdish" lang="ckb" hreflang="ckb" data-title="کۆمەڵە فەرمان" data-language-autonym="کوردی" data-language-local-name="Central Kurdish" class="interlanguage-link-target"><span>کوردی</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/%D0%A1%D0%BA%D1%83%D0%BF_%D0%B8%D0%BD%D1%81%D1%82%D1%80%D1%83%D0%BA%D1%86%D0%B8%D1%98%D0%B0" title="Скуп инструкција – Serbian" lang="sr" hreflang="sr" data-title="Скуп инструкција" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/Instruktionsupps%C3%A4ttning" title="Instruktionsuppsättning – Swedish" lang="sv" hreflang="sv" data-title="Instruktionsuppsättning" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/%E0%B8%8A%E0%B8%B8%E0%B8%94%E0%B8%82%E0%B8%AD%E0%B8%87%E0%B8%84%E0%B8%B3%E0%B8%AA%E0%B8%B1%E0%B9%88%E0%B8%87%E0%B9%80%E0%B8%84%E0%B8%A3%E0%B8%B7%E0%B9%88%E0%B8%AD%E0%B8%87" title="ชุดของคำสั่งเครื่อง – Thai" lang="th" hreflang="th" data-title="ชุดของคำสั่งเครื่อง" data-language-autonym="ไทย" data-language-local-name="Thai" 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a{color:var(--color-progressive)!important}}@media print{body.ns-0 .mw-parser-output .sidebar{display:none!important}}</style><table class="sidebar nomobile nowraplinks" style="margin-top: 0.5em;"><tbody><tr><th class="sidebar-title" style="background-color: rgba(51, 153, 255, 0.15);"><a href="/wiki/Machine_code" title="Machine code">Machine code</a></th></tr><tr><th class="sidebar-heading" style="background-color: rgba(51, 153, 255, 0.15);"> General concepts</th></tr><tr><td class="sidebar-content" style="text-align: left;"> <ul><li><a class="mw-selflink selflink">Instruction set</a></li> <li><a href="/wiki/Opcode" title="Opcode">Opcode</a> <ul><li><a href="/wiki/Illegal_opcode" title="Illegal opcode">Illegal opcode</a></li> <li><a href="/wiki/Opcode_table" title="Opcode table">Opcode table</a></li></ul></li> <li><a href="/wiki/Operand#Computer_science" title="Operand">Operand</a></li></ul></td> </tr><tr><th class="sidebar-heading" style="background-color: rgba(51, 153, 255, 0.15);"> Instructions</th></tr><tr><td class="sidebar-content" style="text-align: left;"> <ul><li><a href="/wiki/NOP_(code)" title="NOP (code)">NOP</a></li> <li><a href="/wiki/Branch_(computer_science)" title="Branch (computer science)">Branch</a> <ul><li><a href="/wiki/Indirect_branch" title="Indirect branch">Indirect branch</a></li></ul></li> <li><a href="/wiki/Repeat_instruction" title="Repeat instruction">Repeat instruction</a></li> <li><a href="/wiki/Execute_instruction" title="Execute instruction">Execute instruction</a></li></ul></td> </tr><tr><td class="sidebar-navbar"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Machine_code" title="Template:Machine code"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Machine_code" title="Template talk:Machine code"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Machine_code" title="Special:EditPage/Template:Machine code"><abbr title="Edit this template">e</abbr></a></li></ul></div></td></tr></tbody></table> <p>In <a href="/wiki/Computer_science" title="Computer science">computer science</a>, an <b>instruction set architecture</b> (<b>ISA</b>) is an <a href="/wiki/Conceptual_model" title="Conceptual model">abstract model</a> that generally defines how <a href="/wiki/Software" title="Software">software</a> controls the <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> in a computer or a family of computers.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> A device or program that executes instructions described by that ISA, such as a central processing unit (CPU), is called an <i><a href="/wiki/Implementation" title="Implementation">implementation</a></i> of that ISA. </p><p>In general, an ISA defines the supported <a href="/wiki/Machine_code" title="Machine code">instructions</a>, <a href="/wiki/Data_type" title="Data type">data types</a>, <a href="/wiki/Register_(computer)" class="mw-redirect" title="Register (computer)">registers</a>, the hardware support for managing <a href="/wiki/Computer_memory" title="Computer memory">main memory</a>,<sup class="noprint Inline-Template" style="margin-left:0.1em; white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify"><span title="See "What does "Hardware support for managing main memory" refer to?" on the talk page.]] (April 2024)">clarification needed</span></a></i>]</sup> fundamental features (such as the <a href="/wiki/Memory_consistency" class="mw-redirect" title="Memory consistency">memory consistency</a>, <a href="/wiki/Addressing_mode" title="Addressing mode">addressing modes</a>, <a href="/wiki/Virtual_memory" title="Virtual memory">virtual memory</a>), and the <a href="/wiki/Input/output" title="Input/output">input/output</a> model of implementations of the ISA. </p><p>An ISA specifies the behavior of <a href="/wiki/Machine_code" title="Machine code">machine code</a> running on implementations of that ISA in a fashion that does not depend on the characteristics of that implementation, providing <a href="/wiki/Binary_compatibility" class="mw-redirect" title="Binary compatibility">binary compatibility</a> between implementations. This enables multiple implementations of an ISA that differ in characteristics such as <a href="/wiki/Computer_performance" title="Computer performance">performance</a>, physical size, and monetary cost (among other things), but that are capable of running the same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software. It also enables the evolution of the <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitectures</a> of the implementations of that ISA, so that a newer, higher-performance implementation of an ISA can run software that runs on previous generations of implementations. </p><p>If an <a href="/wiki/Operating_system" title="Operating system">operating system</a> maintains a standard and compatible <a href="/wiki/Application_binary_interface" title="Application binary interface">application binary interface</a> (ABI) for a particular ISA, machine code will run on future implementations of that ISA and operating system. However, if an ISA supports running multiple operating systems, it does not guarantee that machine code for one operating system will run on another operating system, unless the first operating system supports running machine code built for the other operating system. </p><p>An ISA can be extended by adding instructions or other capabilities, or adding support for larger addresses and data values; an implementation of the extended ISA will still be able to execute <a href="/wiki/Machine_code" title="Machine code">machine code</a> for versions of the ISA without those extensions. Machine code using those extensions will only run on implementations that support those extensions. </p><p>The binary compatibility that they provide makes ISAs one of the most fundamental abstractions in <a href="/wiki/Computing" title="Computing">computing</a>. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=1" title="Edit section: Overview"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>An instruction set architecture is distinguished from a <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a>, which is the set of <a href="/wiki/Processor_design" title="Processor design">processor design</a> techniques used, in a particular processor, to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, the <a href="/wiki/Intel" title="Intel">Intel</a> <a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">Pentium</a> and the <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> <a href="/wiki/Athlon" title="Athlon">Athlon</a> implement nearly identical versions of the <a href="/wiki/X86_instruction_set" class="mw-redirect" title="X86 instruction set">x86 instruction set</a>, but they have radically different internal designs. </p><p> The concept of an <i>architecture</i>, distinct from the design of a specific machine, was developed by <a href="/wiki/Fred_Brooks" title="Fred Brooks">Fred Brooks</a> at IBM during the design phase of <a href="/wiki/System/360" class="mw-redirect" title="System/360">System/360</a>. <style data-mw-deduplicate="TemplateStyles:r1244412712">.mw-parser-output .templatequote{overflow:hidden;margin:1em 0;padding:0 32px}.mw-parser-output .templatequotecite{line-height:1.5em;text-align:left;margin-top:0}@media(min-width:500px){.mw-parser-output .templatequotecite{padding-left:1.6em}}</style></p><blockquote class="templatequote"><p>Prior to NPL [System/360], the company's computer designers had been free to honor cost objectives not only by selecting technologies but also by fashioning functional and architectural refinements. The SPREAD compatibility objective, in contrast, postulated a single architecture for a series of five processors spanning a wide range of cost and performance. None of the five engineering design teams could count on being able to bring about adjustments in architectural specifications as a way of easing difficulties in achieving cost and performance objectives.<sup id="cite_ref-Pugh_2-0" class="reference"><a href="#cite_note-Pugh-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: p.137">: p.137 </span></sup></p></blockquote> <p>Some <a href="/wiki/Virtual_machine" title="Virtual machine">virtual machines</a> that support <a href="/wiki/Bytecode" title="Bytecode">bytecode</a> as their ISA such as <a href="/wiki/Smalltalk" title="Smalltalk">Smalltalk</a>, the <a href="/wiki/Java_virtual_machine" title="Java virtual machine">Java virtual machine</a>, and <a href="/wiki/Microsoft" title="Microsoft">Microsoft</a>'s <a href="/wiki/Common_Language_Runtime" title="Common Language Runtime">Common Language Runtime</a>, implement this by translating the bytecode for commonly used code paths into native machine code. In addition, these virtual machines execute less frequently used code paths by interpretation (see: <a href="/wiki/Just-in-time_compilation" title="Just-in-time compilation">Just-in-time compilation</a>). <a href="/wiki/Transmeta" title="Transmeta">Transmeta</a> implemented the x86 instruction set atop <a href="/wiki/VLIW" class="mw-redirect" title="VLIW">VLIW</a> processors in this fashion. </p> <div class="mw-heading mw-heading2"><h2 id="Classification_of_ISAs">Classification of ISAs</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=2" title="Edit section: Classification of ISAs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>An ISA may be classified in a number of different ways. A common classification is by architectural <i>complexity</i>. A <a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">complex instruction set computer</a> (CISC) has many specialized instructions, some of which may only be rarely used in practical programs. A <a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">reduced instruction set computer</a> (RISC) simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p><p>Other types include <a href="/wiki/Very_long_instruction_word" title="Very long instruction word">very long instruction word</a> (VLIW) architectures, and the closely related <span class="citation-needed-content" style="padding-left:0.1em; padding-right:0.1em; color:var(--color-subtle, #54595d); border:1px solid var(--border-color-subtle, #c8ccd1);"><i>long instruction word</i> (LIW)</span><sup class="noprint Inline-Template Template-Fact" style="margin-left:0.1em; white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2023)">citation needed</span></a></i>]</sup> and <i><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">explicitly parallel instruction computing</a></i> (EPIC) architectures. These architectures seek to exploit <a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">instruction-level parallelism</a> with less hardware than RISC and CISC by making the <a href="/wiki/Compiler" title="Compiler">compiler</a> responsible for instruction issue and scheduling.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p><p>Architectures with even less complexity have been studied, such as the <a href="/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">minimal instruction set computer</a> (MISC) and <a href="/wiki/One-instruction_set_computer" title="One-instruction set computer">one-instruction set computer</a> (OISC). These are theoretically important types, but have not been commercialized.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Instructions"><span id="NATIVE"></span>Instructions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=3" title="Edit section: Instructions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Machine_code" title="Machine code">Machine language</a> is built up from discrete <i>statements</i> or <i>instructions</i>. On the processing architecture, a given instruction may specify: </p> <ul><li><a href="/wiki/Opcode" title="Opcode">opcode</a> (the instruction to be performed) e.g. add, copy, test</li> <li>any explicit operands:</li></ul> <dl><dd><dl><dd><a href="/wiki/Processor_register" title="Processor register">registers</a></dd> <dd>literal/constant values</dd> <dd><a href="/wiki/Addressing_mode" title="Addressing mode">addressing modes</a> used to access memory</dd></dl></dd></dl> <p>More complex operations are built up by combining these simple instructions, which are executed sequentially, or as otherwise directed by <a href="/wiki/Control_flow" title="Control flow">control flow</a> instructions. </p> <div class="mw-heading mw-heading3"><h3 id="Instruction_types">Instruction types</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=4" title="Edit section: Instruction types"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Examples of operations common to many instruction sets include: </p> <div class="mw-heading mw-heading4"><h4 id="Data_handling_and_memory_operations">Data handling and memory operations</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=5" title="Edit section: Data handling and memory operations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><i>Set</i> a <a href="/wiki/Processor_register" title="Processor register">register</a> to a fixed constant value.</li> <li><i>Copy</i> data from a memory location or a register to a memory location or a register (a machine instruction is often called <i>move</i>; however, the term is misleading). They are used to store the contents of a register, the contents of another memory location or the result of a computation, or to retrieve stored data to perform a computation on it later. They are often called <a href="/wiki/Load%E2%80%93store_unit" title="Load–store unit"><i>load</i> or <i>store</i></a> operations.</li> <li><i>Read</i> or <i>write</i> data from hardware devices.</li></ul> <div class="mw-heading mw-heading4"><h4 id="Arithmetic_and_logic_operations">Arithmetic and logic operations</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=6" title="Edit section: Arithmetic and logic operations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><i>Add</i>, <i>subtract</i>, <i>multiply</i>, or <i>divide</i> the values of two registers, placing the result in a register, possibly setting one or more <a href="/wiki/Flag_(programming)" title="Flag (programming)">condition codes</a> in a <a href="/wiki/Status_register" title="Status register">status register</a>.<sup id="cite_ref-FOOTNOTEHennessyPatterson2003108_7-0" class="reference"><a href="#cite_note-FOOTNOTEHennessyPatterson2003108-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> <ul><li><i><style data-mw-deduplicate="TemplateStyles:r1238216509">.mw-parser-output .vanchor>:target~.vanchor-text{background-color:#b1d2ff}@media screen{html.skin-theme-clientpref-night .mw-parser-output .vanchor>:target~.vanchor-text{background-color:#0f4dc9}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .vanchor>:target~.vanchor-text{background-color:#0f4dc9}}</style><span class="vanchor"><span id="increment"></span><span class="vanchor-text">increment</span></span></i>, <i><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><span class="vanchor"><span id="decrement"></span><span class="vanchor-text">decrement</span></span></i> in some ISAs, saving operand fetch in trivial cases.</li></ul></li> <li>Perform <a href="/wiki/Bitwise_operation" title="Bitwise operation">bitwise operations</a>, e.g., taking the <i><a href="/wiki/Logical_conjunction" title="Logical conjunction">conjunction</a></i> and <i><a href="/wiki/Logical_disjunction" title="Logical disjunction">disjunction</a></i> of corresponding bits in a pair of registers, taking the <i><a href="/wiki/Logical_negation" class="mw-redirect" title="Logical negation">negation</a></i> of each bit in a register.</li> <li><i>Compare</i> two values in registers (for example, to see if one is less, or if they are equal).</li> <li><i><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><span class="vanchor"><span id="Floating-point_instruction"></span><span class="vanchor-text">Floating-point instruction</span></span>s</i> for arithmetic on floating-point numbers.<sup id="cite_ref-FOOTNOTEHennessyPatterson2003108_7-1" class="reference"><a href="#cite_note-FOOTNOTEHennessyPatterson2003108-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading4"><h4 id="Control_flow_operations">Control flow operations</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=7" title="Edit section: Control flow operations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><i><a href="/wiki/Branch_(computer_science)" title="Branch (computer science)">Branch</a></i> to another location in the program and execute instructions there.</li> <li><i><a href="/wiki/Conditional_branch" class="mw-redirect" title="Conditional branch">Conditionally branch</a></i> to another location if a certain condition holds.</li> <li><i><a href="/wiki/Indirect_branch" title="Indirect branch">Indirectly branch</a></i> to another location.</li> <li><i><a href="/wiki/Subroutine" class="mw-redirect" title="Subroutine">Call</a></i> another block of code, while saving the location of the next instruction as a point to return to.</li></ul> <div class="mw-heading mw-heading4"><h4 id="Coprocessor_instructions">Coprocessor instructions</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=8" title="Edit section: Coprocessor instructions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Load/store data to and from a coprocessor or exchanging with CPU registers.</li> <li>Perform coprocessor operations.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Complex_instructions">Complex instructions</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=9" title="Edit section: Complex instructions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Processors may include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many instructions on other computers. Such instructions are <a href="/wiki/Typified" class="mw-redirect" title="Typified">typified</a> by instructions that take multiple steps, control multiple functional units, or otherwise appear on a larger scale than the bulk of simple instructions implemented by the given processor. Some examples of "complex" instructions include: </p> <ul><li>transferring multiple registers to or from memory (especially the <a href="/wiki/Call_stack" title="Call stack">stack</a>) at once</li> <li>moving large blocks of memory (e.g. <a href="/wiki/String_copy" class="mw-redirect" title="String copy">string copy</a> or <a href="/wiki/DMA_transfer" class="mw-redirect" title="DMA transfer">DMA transfer</a>)</li> <li>complicated integer and <a href="/wiki/Floating-point_arithmetic" title="Floating-point arithmetic">floating-point arithmetic</a> (e.g. <a href="/wiki/Square_root" title="Square root">square root</a>, or <a href="/wiki/Transcendental_function" title="Transcendental function">transcendental functions</a> such as <a href="/wiki/Logarithm" title="Logarithm">logarithm</a>, <a href="/wiki/Sine" class="mw-redirect" title="Sine">sine</a>, <a href="/wiki/Cosine" class="mw-redirect" title="Cosine">cosine</a>, etc.)</li> <li><i><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><span class="vanchor"><span id="[[Single_instruction,_multiple_data|SIMD]]_instruction"></span><span id="SIMD_instruction"></span><span class="vanchor-text"><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> instruction</span></span>s</i>, a single instruction performing an operation on many homogeneous values in parallel, possibly in dedicated <a href="/wiki/SIMD_register" class="mw-redirect" title="SIMD register">SIMD registers</a></li> <li>performing an atomic <a href="/wiki/Test-and-set" title="Test-and-set">test-and-set</a> instruction or other <a href="/wiki/Read%E2%80%93modify%E2%80%93write" title="Read–modify–write">read–modify–write</a> <a href="/wiki/Atomic_instruction" class="mw-redirect" title="Atomic instruction">atomic instruction</a></li> <li>instructions that perform <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">ALU</a> operations with an operand from memory rather than a register</li></ul> <p>Complex instructions are more common in CISC instruction sets than in RISC instruction sets, but RISC instruction sets may include them as well. RISC instruction sets generally do not include ALU operations with memory operands, or instructions to move large blocks of memory, but most RISC instruction sets include <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> or <a href="/wiki/Vector_processing" class="mw-redirect" title="Vector processing">vector</a> instructions that perform the same arithmetic operation on multiple pieces of data at the same time. SIMD instructions have the ability of manipulating large vectors and matrices in minimal time. SIMD instructions allow easy <a href="/wiki/Parallelization" class="mw-redirect" title="Parallelization">parallelization</a> of algorithms commonly involved in sound, image, and video processing. Various SIMD implementations have been brought to market under trade names such as <a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/3DNow!" title="3DNow!">3DNow!</a>, and <a href="/wiki/AltiVec" title="AltiVec">AltiVec</a>. </p><p><span class="anchor" id="Parts_of_an_instruction"></span> </p> <div class="mw-heading mw-heading3"><h3 id="Instruction_encoding">Instruction encoding</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=10" title="Edit section: Instruction encoding"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Mips32_addi.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/2a/Mips32_addi.svg/370px-Mips32_addi.svg.png" decoding="async" width="370" height="133" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/2a/Mips32_addi.svg/555px-Mips32_addi.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/2a/Mips32_addi.svg/740px-Mips32_addi.svg.png 2x" data-file-width="500" data-file-height="180" /></a><figcaption>One instruction may have several fields, which identify the logical operation, and may also include source and destination addresses and constant values. This is the MIPS "Add Immediate" instruction, which allows selection of source and destination registers and inclusion of a small constant.</figcaption></figure> <p>On traditional architectures, an instruction includes an <a href="/wiki/Opcode" title="Opcode">opcode</a> that specifies the operation to perform, such as <i>add contents of memory to register</i>—and zero or more <a href="/wiki/Operand" title="Operand">operand</a> specifiers, which may specify <a href="/wiki/Processor_register" title="Processor register">registers</a>, memory locations, or literal data. The operand specifiers may have <a href="/wiki/Addressing_mode" title="Addressing mode">addressing modes</a> determining their meaning or may be in fixed fields. In <a href="/wiki/Very_long_instruction_word" title="Very long instruction word">very long instruction word</a> (VLIW) architectures, which include many <a href="/wiki/Microcode" title="Microcode">microcode</a> architectures, multiple simultaneous opcodes and operands are specified in a single instruction. </p><p>Some exotic instruction sets do not have an opcode field, such as <a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">transport triggered architectures</a> (TTA), only operand(s). </p><p>Most <a href="/wiki/Stack_machine" title="Stack machine">stack machines</a> have "<a href="/wiki/0-operand_instruction_set" class="mw-redirect" title="0-operand instruction set">0-operand</a>" instruction sets in which arithmetic and logical operations lack any operand specifier fields; only instructions that push operands onto the evaluation stack or that pop operands from the stack into variables have operand specifiers. The instruction set carries out most ALU actions with postfix (<a href="/wiki/Reverse_Polish_notation" title="Reverse Polish notation">reverse Polish notation</a>) operations that work only on the expression <a href="/wiki/Stack_(abstract_data_type)" title="Stack (abstract data type)">stack</a>, not on data registers or arbitrary main memory cells. This can be very convenient for compiling high-level languages, because most arithmetic expressions can be easily translated into postfix notation.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p><p>Conditional instructions often have a predicate field—a few bits that encode the specific condition to cause an operation to be performed rather than not performed. For example, a conditional branch instruction will transfer control if the condition is true, so that execution proceeds to a different part of the program, and not transfer control if the condition is false, so that execution continues sequentially. Some instruction sets also have conditional moves, so that the move will be executed, and the data stored in the target location, if the condition is true, and not executed, and the target location not modified, if the condition is false. Similarly, IBM <a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a> has a conditional store instruction. A few instruction sets include a predicate field in every instruction; this is called <a href="/wiki/Branch_predication" class="mw-redirect" title="Branch predication">branch predication</a>. </p> <div class="mw-heading mw-heading4"><h4 id="Number_of_operands">Number of operands</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=11" title="Edit section: Number of operands"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Instruction sets may be categorized by the maximum number of operands <i>explicitly</i> specified in instructions. </p><p>(In the examples that follow, <i>a</i>, <i>b</i>, and <i>c</i> are (direct or calculated) addresses referring to memory cells, while <i>reg1</i> and so on refer to machine registers.) </p> <pre>C = A+B </pre> <ul><li>0-operand (<i>zero-address machines</i>), so called <a href="/wiki/Stack_machine" title="Stack machine">stack machines</a>: All arithmetic operations take place using the top one or two positions on the stack:<sup id="cite_ref-FOOTNOTEHennessyPatterson200392_9-0" class="reference"><a href="#cite_note-FOOTNOTEHennessyPatterson200392-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> <code>push a</code>, <code>push b</code>, <code>add</code>, <code>pop c</code>. <ul><li><code>C = A+B</code> needs <i>four instructions</i>.<sup id="cite_ref-FOOTNOTEHennessyPatterson200393_10-0" class="reference"><a href="#cite_note-FOOTNOTEHennessyPatterson200393-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> For stack machines, the terms "0-operand" and "zero-address" apply to arithmetic instructions, but not to all instructions, as 1-operand push and pop instructions are used to access memory.</li></ul></li> <li>1-operand (<i>one-address machines</i>), so called <a href="/wiki/Accumulator_machine" class="mw-redirect" title="Accumulator machine">accumulator machines</a>, include early computers and many small <a href="/wiki/Microcontroller" title="Microcontroller">microcontrollers</a>: most instructions specify a single right operand (that is, constant, a register, or a memory location), with the implicit <a href="/wiki/Accumulator_(computing)" title="Accumulator (computing)">accumulator</a> as the left operand (and the destination if there is one): <code>load a</code>, <code>add b</code>, <code>store c</code>. <ul><li><code>C = A+B</code> needs <i>three instructions</i>.<sup id="cite_ref-FOOTNOTEHennessyPatterson200393_10-1" class="reference"><a href="#cite_note-FOOTNOTEHennessyPatterson200393-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup></li></ul></li> <li>2-operand — many CISC and RISC machines fall under this category: <ul><li>CISC — <code>move A</code> to <i>C</i>; then <code>add B</code> to <i>C</i>. <ul><li><code>C = A+B</code> needs <i>two instructions</i>. This effectively 'stores' the result without an explicit <i>store</i> instruction.</li></ul></li> <li>CISC — Often machines are <a rel="nofollow" class="external text" href="https://web.archive.org/web/20131105155703/http://cs.smith.edu/~thiebaut/ArtOfAssembly/CH04/CH04-3.html#HEADING3-79">limited to one memory operand</a> per instruction: <code>load a,reg1</code>; <code>add b,reg1</code>; <code>store reg1,c</code>; This requires a load/store pair for any memory movement regardless of whether the <code>add</code> result is an augmentation stored to a different place, as in <code>C = A+B</code>, or the same memory location: <code>A = A+B</code>. <ul><li><code>C = A+B</code> needs <i>three instructions</i>.</li></ul></li> <li>RISC — Requiring explicit memory loads, the instructions would be: <code>load a,reg1</code>; <code>load b,reg2</code>; <code>add reg1,reg2</code>; <code>store reg2,c</code>. <ul><li><code>C = A+B</code> needs <i>four instructions</i>.</li></ul></li></ul></li> <li>3-operand, allowing better reuse of data:<sup id="cite_ref-Cocke_11-0" class="reference"><a href="#cite_note-Cocke-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> <ul><li>CISC — It becomes either a single instruction: <code>add a,b,c</code> <ul><li><code>C = A+B</code> needs <i>one instruction</i>.</li></ul></li> <li>CISC — Or, on machines limited to two memory operands per instruction, <code>move a,reg1</code>; <code>add reg1,b,c</code>; <ul><li><code>C = A+B</code> needs <i>two instructions</i>.</li></ul></li> <li>RISC — arithmetic instructions use registers only, so explicit 2-operand load/store instructions are needed: <code>load a,reg1</code>; <code>load b,reg2</code>; <code>add reg1+reg2->reg3</code>; <code>store reg3,c</code>; <ul><li><code>C = A+B</code> needs <i>four instructions</i>.</li> <li>Unlike 2-operand or 1-operand, this leaves all three values a, b, and c in registers available for further reuse.<sup id="cite_ref-Cocke_11-1" class="reference"><a href="#cite_note-Cocke-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup></li></ul></li></ul></li> <li>more operands—some CISC machines permit a variety of addressing modes that allow more than 3 operands (registers or memory accesses), such as the <a href="/wiki/VAX" title="VAX">VAX</a> "POLY" polynomial evaluation instruction.</li></ul> <p>Due to the large number of bits needed to encode the three registers of a 3-operand instruction, RISC architectures that have 16-bit instructions are invariably 2-operand designs, such as the Atmel AVR, <a href="/wiki/TI_MSP430" title="TI MSP430">TI MSP430</a>, and some versions of <a href="/wiki/ARM_Thumb" class="mw-redirect" title="ARM Thumb">ARM Thumb</a>. RISC architectures that have 32-bit instructions are usually 3-operand designs, such as the <a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a>, <a href="/wiki/AVR32" title="AVR32">AVR32</a>, <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a>, <a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a>, and <a href="/wiki/SPARC" title="SPARC">SPARC</a> architectures. </p><p>Each instruction specifies some number of operands (registers, memory locations, or immediate values) <i>explicitly</i>. Some instructions give one or both operands implicitly, such as by being stored on top of the <a href="/wiki/Stack_(data_structure)" class="mw-redirect" title="Stack (data structure)">stack</a> or in an implicit register. If some of the operands are given implicitly, fewer operands need be specified in the instruction. When a "destination operand" explicitly specifies the destination, an additional operand must be supplied. Consequently, the number of operands encoded in an instruction may differ from the mathematically necessary number of arguments for a logical or arithmetic operation (the <a href="/wiki/Arity" title="Arity">arity</a>). Operands are either encoded in the "opcode" representation of the instruction, or else are given as values or addresses following the opcode. </p> <div class="mw-heading mw-heading3"><h3 id="Register_pressure"><span class="anchor" id="REGISTER-PRESSURE"></span>Register pressure</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=12" title="Edit section: Register pressure"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><i>Register pressure</i> measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use; thus, the higher the register pressure, the more often the register contents must be <a href="/wiki/Register_spilling" class="mw-redirect" title="Register spilling">spilled</a> into memory. Increasing the number of registers in an architecture decreases register pressure but increases the cost.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </p><p>While embedded instruction sets such as <a href="/wiki/ARM_Thumb" class="mw-redirect" title="ARM Thumb">Thumb</a> suffer from extremely high register pressure because they have small register sets, general-purpose RISC ISAs like <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> and <a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a> enjoy low register pressure. CISC ISAs like x86-64 offer low register pressure despite having smaller register sets. This is due to the many addressing modes and optimizations (such as sub-register addressing, memory operands in ALU instructions, absolute addressing, PC-relative addressing, and register-to-register spills) that CISC ISAs offer.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Instruction_length"><span class="anchor" id="Fixed_length"></span><span class="anchor" id="Fixed_width"></span><span class="anchor" id="Variable_length"></span><span class="anchor" id="Variable_width"></span>Instruction length</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=13" title="Edit section: Instruction length"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The size or length of an instruction varies widely, from as little as four bits in some <a href="/wiki/Microcontroller" title="Microcontroller">microcontrollers</a> to many hundreds of bits in some <a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> systems. Processors used in <a href="/wiki/Personal_computer" title="Personal computer">personal computers</a>, <a href="/wiki/Mainframe_computer" title="Mainframe computer">mainframes</a>, and <a href="/wiki/Supercomputer" title="Supercomputer">supercomputers</a> have minimum instruction sizes between 8 and 64 bits. The longest possible instruction on x86 is 15 bytes (120 bits).<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> Within an instruction set, different instructions may have different lengths. In some architectures, notably most <a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">reduced instruction set computers</a> (RISC), <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><span class="vanchor"><span id="instructions_are_a_fixed_length"></span><span id="FIXED_LENGTH_INSTRUCTIONS"></span><span class="vanchor-text">instructions are a fixed length</span></span>, typically corresponding with that architecture's <a href="/wiki/Word_(data_type)" class="mw-redirect" title="Word (data type)">word size</a>. In other architectures, instructions have <a href="/wiki/Variable-length_code" title="Variable-length code">variable length</a>, typically integral multiples of a <a href="/wiki/Byte" title="Byte">byte</a> or a <a href="/wiki/Halfword" class="mw-redirect" title="Halfword">halfword</a>. Some, such as the <a href="/wiki/ARMv7" class="mw-redirect" title="ARMv7">ARM</a> with <i>Thumb-extension</i> have <i>mixed</i> variable encoding, that is two fixed, usually 32-bit and 16-bit encodings, where instructions cannot be mixed freely but must be switched between on a branch (or exception boundary in ARMv8). </p><p>Fixed-length instructions are less complicated to handle than variable-length instructions for several reasons (not having to check whether an instruction straddles a cache line or virtual memory page boundary,<sup id="cite_ref-Cocke_11-2" class="reference"><a href="#cite_note-Cocke-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> for instance), and are therefore somewhat easier to optimize for speed. </p> <div class="mw-heading mw-heading3"><h3 id="Code_density">Code density</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=14" title="Edit section: Code density"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In early 1960s computers, main memory was expensive and very limited, even on mainframes. Minimizing the size of a program to make sure it would fit in the limited memory was often central. Thus the size of the instructions needed to perform a particular task, the <i>code density</i>, was an important characteristic of any instruction set. It remained important on the initially-tiny memories of minicomputers and then microprocessors. Density remains important today, for smartphone applications, applications downloaded into browsers over slow Internet connections, and in ROMs for embedded applications. A more general advantage of increased density is improved effectiveness of caches and instruction prefetch. </p><p>Computers with high code density often have complex instructions for procedure entry, parameterized returns, loops, etc. (therefore retroactively named <i>Complex Instruction Set Computers</i>, <a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a>). However, more typical, or frequent, "CISC" instructions merely combine a basic ALU operation, such as "add", with the access of one or more operands in memory (using <a href="/wiki/Addressing_mode" title="Addressing mode">addressing modes</a> such as direct, indirect, indexed, etc.). Certain architectures may allow two or three operands (including the result) directly in memory or may be able to perform functions such as automatic pointer increment, etc. Software-implemented instruction sets may have even more complex and powerful instructions. </p><p><i>Reduced instruction-set computers</i>, <a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a>, were first widely implemented during a period of rapidly growing memory subsystems. They sacrifice code density to simplify implementation circuitry, and try to increase performance via higher clock frequencies and more registers. A single RISC instruction typically performs only a single operation, such as an "add" of registers or a "load" from a memory location into a register. A RISC instruction set normally has a fixed <a href="#Instruction_length">instruction length</a>, whereas a typical CISC instruction set has instructions of widely varying length. However, as RISC computers normally require more and often longer instructions to implement a given task, they inherently make less optimal use of bus bandwidth and cache memories. </p><p>Certain embedded RISC ISAs like <a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb</a> and <a href="/wiki/AVR32" title="AVR32">AVR32</a> typically exhibit very high density owing to a technique called code compression. This technique packs two 16-bit instructions into one 32-bit word, which is then unpacked at the decode stage and executed as two instructions.<sup id="cite_ref-weaver_15-0" class="reference"><a href="#cite_note-weaver-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">Minimal instruction set computers</a> (MISC) are commonly a form of <a href="/wiki/Stack_machine" title="Stack machine">stack machine</a>, where there are few separate instructions (8–32), so that multiple instructions can be fit into a single machine word. These types of cores often take little silicon to implement, so they can be easily realized in an <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a> or in a <a href="/wiki/Multi-core" class="mw-redirect" title="Multi-core">multi-core</a> form. The code density of MISC is similar to the code density of RISC; the increased instruction density is offset by requiring more of the primitive instructions to do a task.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup><sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability"><span title="That discusses RISC and CISC, but not MISC. (December 2021)">failed verification</span></a></i>]</sup> </p><p>There has been research into <a href="/wiki/Executable_compression" title="Executable compression">executable compression</a> as a mechanism for improving code density. The mathematics of <a href="/wiki/Kolmogorov_complexity" title="Kolmogorov complexity">Kolmogorov complexity</a> describes the challenges and limits of this. </p><p>In practice, code density is also dependent on the <a href="/wiki/Compiler" title="Compiler">compiler</a>. Most <a href="/wiki/Optimizing_compiler" title="Optimizing compiler">optimizing compilers</a> have options that control whether to optimize code generation for execution speed or for code density. For instance <a href="/wiki/GNU_Compiler_Collection" title="GNU Compiler Collection">GCC</a> has the option <code>-Os</code> to optimize for small machine code size, and <code>-O3</code> to optimize for execution speed at the cost of larger machine code. </p> <div class="mw-heading mw-heading3"><h3 id="Representation">Representation</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=15" title="Edit section: Representation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The instructions constituting a program are rarely specified using their internal, numeric form (<a href="/wiki/Machine_code" title="Machine code">machine code</a>); they may be specified by programmers using an <a href="/wiki/Assembly_language" title="Assembly language">assembly language</a> or, more commonly, may be generated from <a href="/wiki/High-level_programming_language" title="High-level programming language">high-level programming languages</a> by <a href="/wiki/Compiler" title="Compiler">compilers</a>.<sup id="cite_ref-FOOTNOTEHennessyPatterson2003120_17-0" class="reference"><a href="#cite_note-FOOTNOTEHennessyPatterson2003120-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Design">Design</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=16" title="Edit section: Design"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The design of instruction sets is a complex issue. There were two stages in history for the microprocessor. The first was the CISC (Complex Instruction Set Computer), which had many different instructions. In the 1970s, however, places like IBM did research and found that many instructions in the set could be eliminated. The result was the RISC (Reduced Instruction Set Computer), an architecture that uses a smaller set of instructions. A simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory and <a href="/wiki/CPU_cache" title="CPU cache">cache</a> efficiency, or simplify programming. </p><p>Some instruction set designers reserve one or more opcodes for some kind of <a href="/wiki/System_call" title="System call">system call</a> or <a href="/wiki/Software_interrupt" class="mw-redirect" title="Software interrupt">software interrupt</a>. For example, <a href="/wiki/MOS_Technology_6502" title="MOS Technology 6502">MOS Technology 6502</a> uses 00<sub>H</sub>, <a href="/wiki/Zilog_Z80" title="Zilog Z80">Zilog Z80</a> uses the eight codes C7,CF,D7,DF,E7,EF,F7,FF<sub>H</sub><sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> while <a href="/wiki/Motorola_68000" title="Motorola 68000">Motorola 68000</a> use codes in the range A000..AFFF<sub>H</sub>. </p><p>Fast virtual machines are much easier to implement if an instruction set meets the <a href="/wiki/Popek_and_Goldberg_virtualization_requirements" title="Popek and Goldberg virtualization requirements">Popek and Goldberg virtualization requirements</a>.<sup class="noprint Inline-Template" style="margin-left:0.1em; white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify"><span title="The text near this tag may need clarification or removal of jargon. (October 2012)">clarification needed</span></a></i>]</sup> </p><p>The <a href="/wiki/NOP_slide" title="NOP slide">NOP slide</a> used in immunity-aware programming is much easier to implement if the "unprogrammed" state of the memory is interpreted as a <a href="/wiki/NOP_(code)" title="NOP (code)">NOP</a>.<sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Accuracy_dispute#Disputed_statement" title="Wikipedia:Accuracy dispute"><span title="The material near this tag is possibly inaccurate or nonfactual. (October 2012)">dubious</span></a> – <a href="/wiki/Talk:Instruction_set_architecture#Dubious" title="Talk:Instruction set architecture">discuss</a></i>]</sup> </p><p>On systems with multiple processors, <a href="/wiki/Non-blocking_synchronization" class="mw-redirect" title="Non-blocking synchronization">non-blocking synchronization</a> algorithms are much easier to implement<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="Opinion unsupported by a textbook (October 2012)">citation needed</span></a></i>]</sup> if the instruction set includes support for something such as "<a href="/wiki/Fetch-and-add" title="Fetch-and-add">fetch-and-add</a>", "<a href="/wiki/Load-link/store-conditional" title="Load-link/store-conditional">load-link/store-conditional</a>" (LL/SC), or "atomic <a href="/wiki/Compare-and-swap" title="Compare-and-swap">compare-and-swap</a>". </p> <div class="mw-heading mw-heading2"><h2 id="Instruction_set_implementation">Instruction set implementation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=17" title="Edit section: Instruction set implementation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Processor_design" title="Processor design">Processor design</a>, <a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a>, and <a href="/wiki/Silicon_compiler" title="Silicon compiler">Silicon compiler</a></div> <p>A given instruction set can be implemented in a variety of ways. All ways of implementing a particular instruction set provide the same <a href="/wiki/Programming_model" title="Programming model">programming model</a>, and all implementations of that instruction set are able to run the same executables. The various ways of implementing an instruction set give different tradeoffs between cost, performance, power consumption, size, etc. </p><p>When designing the <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a> of a processor, engineers use blocks of "hard-wired" electronic circuitry (often designed separately) such as adders, multiplexers, counters, registers, ALUs, etc. Some kind of <a href="/wiki/Register_transfer_language" title="Register transfer language">register transfer language</a> is then often used to describe the decoding and sequencing of each instruction of an ISA using this physical microarchitecture. There are two basic ways to build a <a href="/wiki/Control_unit" title="Control unit">control unit</a> to implement this description (although many designs use middle ways or compromises): </p> <ol><li>Some computer designs "hardwire" the complete instruction set decoding and sequencing (just like the rest of the microarchitecture).</li> <li>Other designs employ <a href="/wiki/Microcode" title="Microcode">microcode</a> routines or tables (or both) to do this, using <a href="/wiki/Read-only_memory" title="Read-only memory">ROMs</a> or writable <a href="/wiki/Random-access_memory" title="Random-access memory">RAMs</a> (<a href="/wiki/Writable_control_store" class="mw-redirect" title="Writable control store">writable control store</a>), <a href="/wiki/Programmable_logic_array" title="Programmable logic array">PLAs</a>, or both.</li></ol> <p>Some microcoded CPU designs with a writable control store use it to allow the instruction set to be changed (for example, the <a href="/wiki/Rekursiv" title="Rekursiv">Rekursiv</a> processor and the <a href="/w/index.php?title=Imsys&action=edit&redlink=1" class="new" title="Imsys (page does not exist)">Imsys</a> <a href="/w/index.php?title=Cjip&action=edit&redlink=1" class="new" title="Cjip (page does not exist)">Cjip</a>).<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p><p>CPUs designed for <a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">reconfigurable computing</a> may use <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate arrays</a> (FPGAs). </p><p>An ISA can also be <a href="/wiki/Emulator" title="Emulator">emulated</a> in software by an <a href="/wiki/Interpreter_(computing)" title="Interpreter (computing)">interpreter</a>. Naturally, due to the interpretation overhead, this is slower than directly running programs on the emulated hardware, unless the hardware running the emulator is an order of magnitude faster. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready. </p><p>Often the details of the implementation have a strong influence on the particular instructions selected for the instruction set. For example, many implementations of the <a href="/wiki/Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">instruction pipeline</a> only allow a single memory load or memory store per instruction, leading to a <a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">load–store architecture</a> (RISC). For another example, some early ways of implementing the <a href="/wiki/Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">instruction pipeline</a> led to a <a href="/wiki/Delay_slot" title="Delay slot">delay slot</a>. </p><p>The demands of high-speed digital signal processing have pushed in the opposite direction—forcing instructions to be implemented in a particular way. For example, to perform digital filters fast enough, the MAC instruction in a typical <a href="/wiki/Digital_signal_processor" title="Digital signal processor">digital signal processor</a> (DSP) must use a kind of <a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard architecture</a> that can fetch an instruction and two data words simultaneously, and it requires a single-cycle <a href="/wiki/Multiply%E2%80%93accumulate_operation" title="Multiply–accumulate operation">multiply–accumulate</a> <a href="/wiki/Binary_multiplier" title="Binary multiplier">multiplier</a>. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=18" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison of instruction set architectures</a></li> <li><a href="/wiki/Compressed_instruction_set" title="Compressed instruction set">Compressed instruction set</a></li> <li><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></li> <li><a href="/wiki/Emulator" title="Emulator">Emulator</a></li> <li><a href="/wiki/Instruction_set_simulator" title="Instruction set simulator">Instruction set simulator</a></li> <li><a href="/wiki/Micro-operation" title="Micro-operation">Micro-operation</a></li> <li><a href="/wiki/No_instruction_set_computing" title="No instruction set computing">No instruction set computing</a></li> <li><a href="/wiki/OVPsim" title="OVPsim">OVPsim</a> full systems simulator providing ability to create/model/emulate any instruction set using C and standard APIs</li> <li><a href="/wiki/Processor_design" title="Processor design">Processor design</a></li> <li><a href="/wiki/Simulation" title="Simulation">Simulation</a></li> <li><a href="/wiki/Register_transfer_language" title="Register transfer language">Register transfer language</a> (RTL)</li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=19" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" 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IEEE International Conference on Computer Design. <a href="/wiki/CiteSeerX_(identifier)" class="mw-redirect" title="CiteSeerX (identifier)">CiteSeerX</a> <span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.398.1967">10.1.1.398.1967</a></span>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FICCD.2009.5413117">10.1109/ICCD.2009.5413117</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=Code+density+concerns+for+new+architectures&rft.date=2009&rft_id=https%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fsummary%3Fdoi%3D10.1.1.398.1967%23id-name%3DCiteSeerX&rft_id=info%3Adoi%2F10.1109%2FICCD.2009.5413117&rft.aulast=Weaver&rft.aufirst=Vincent+M.&rft.au=McKee%2C+Sally+A.&rfr_id=info%3Asid%2Fen.wikipedia.org%3AInstruction+set+architecture" class="Z3988"></span></span> </li> <li id="cite_note-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-16">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/">"RISC vs. CISC"</a>. <i>cs.stanford.edu</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2021-12-18</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=cs.stanford.edu&rft.atitle=RISC+vs.+CISC&rft_id=https%3A%2F%2Fcs.stanford.edu%2Fpeople%2Feroberts%2Fcourses%2Fsoco%2Fprojects%2Frisc%2Frisccisc%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AInstruction+set+architecture" class="Z3988"></span></span> </li> <li id="cite_note-FOOTNOTEHennessyPatterson2003120-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-FOOTNOTEHennessyPatterson2003120_17-0">^</a></b></span> <span class="reference-text"><a href="#CITEREFHennessyPatterson2003">Hennessy & Patterson 2003</a>, p. 120.</span> </li> <li id="cite_note-18"><span class="mw-cite-backlink"><b><a href="#cite_ref-18">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGanssle2001" class="citation web cs1">Ganssle, Jack (February 26, 2001). <a rel="nofollow" class="external text" href="https://www.embedded.com/electronics-blogs/break-points/4023293/Proactive-Debugging">"Proactive Debugging"</a>. <i>embedded.com</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=embedded.com&rft.atitle=Proactive+Debugging&rft.date=2001-02-26&rft.aulast=Ganssle&rft.aufirst=Jack&rft_id=https%3A%2F%2Fwww.embedded.com%2Felectronics-blogs%2Fbreak-points%2F4023293%2FProactive-Debugging&rfr_id=info%3Asid%2Fen.wikipedia.org%3AInstruction+set+architecture" class="Z3988"></span></span> </li> <li id="cite_note-19"><span class="mw-cite-backlink"><b><a href="#cite_ref-19">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://cpushack.net/CPU/cpu7.html">"Great Microprocessors of the Past and Present (V 13.4.0)"</a>. <i>cpushack.net</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2014-07-25</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=cpushack.net&rft.atitle=Great+Microprocessors+of+the+Past+and+Present+%28V+13.4.0%29&rft_id=http%3A%2F%2Fcpushack.net%2FCPU%2Fcpu7.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AInstruction+set+architecture" class="Z3988"></span></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=20" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBowen1985" class="citation journal cs1"><a href="/wiki/Jonathan_Bowen" title="Jonathan Bowen">Bowen, Jonathan P.</a> (July–August 1985). "Standard Microprocessor Programming Cards". <i>Microprocessors and Microsystems</i>. <b>9</b> (6): 274–290. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1016%2F0141-9331%2885%2990116-4">10.1016/0141-9331(85)90116-4</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Microprocessors+and+Microsystems&rft.atitle=Standard+Microprocessor+Programming+Cards&rft.volume=9&rft.issue=6&rft.pages=274-290&rft.date=1985-07%2F1985-08&rft_id=info%3Adoi%2F10.1016%2F0141-9331%2885%2990116-4&rft.aulast=Bowen&rft.aufirst=Jonathan+P.&rfr_id=info%3Asid%2Fen.wikipedia.org%3AInstruction+set+architecture" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHennessyPatterson2003" class="citation book cs1"><a href="/wiki/John_L._Hennessy" title="John L. Hennessy">Hennessy, John L.</a>; <a href="/wiki/David_Patterson_(computer_scientist)" title="David Patterson (computer scientist)">Patterson, David A.</a> (2003). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=XX69oNsazH4C"><i>Computer Architecture: A Quantitative Approach</i></a> (Third ed.). <a href="/wiki/Morgan_Kaufmann_Publishers" title="Morgan Kaufmann Publishers">Morgan Kaufmann Publishers</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/1-55860-724-2" title="Special:BookSources/1-55860-724-2"><bdi>1-55860-724-2</bdi></a><span class="reference-accessdate">. Retrieved <span class="nowrap">2023-03-04</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Computer+Architecture%3A+A+Quantitative+Approach&rft.edition=Third&rft.pub=Morgan+Kaufmann+Publishers&rft.date=2003&rft.isbn=1-55860-724-2&rft.aulast=Hennessy&rft.aufirst=John+L.&rft.au=Patterson%2C+David+A.&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DXX69oNsazH4C&rfr_id=info%3Asid%2Fen.wikipedia.org%3AInstruction+set+architecture" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Instruction_set_architecture&action=edit&section=21" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1235681985">.mw-parser-output .side-box{margin:4px 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src="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/12px-Commons-logo.svg.png" decoding="async" width="12" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/18px-Commons-logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/24px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></a></span> Media related to <a href="https://commons.wikimedia.org/wiki/Category:Instruction_set_architectures" class="extiw" title="commons:Category:Instruction set architectures">Instruction set architectures</a> at Wikimedia Commons</li> <li><a rel="nofollow" class="external text" href="http://www.textfiles.com/programming/CARDS/">Programming Textfiles: Bowen's Instruction Summary Cards</a></li> <li><a rel="nofollow" class="external text" href="http://www.cs.clemson.edu/~mark/hist.html">Mark Smotherman's Historical Computer Designs Page</a></li></ul> <div class="navbox-styles"><link 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.navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="Processor_technologies" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Processor_technologies" title="Template:Processor technologies"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Processor_technologies" title="Template talk:Processor technologies"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Processor_technologies" title="Special:EditPage/Template:Processor technologies"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Processor_technologies" style="font-size:114%;margin:0 4em"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Abstract_machine" title="Abstract machine">Abstract machine</a></li> <li><a href="/wiki/Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li> <li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li> <li><a href="/wiki/Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li> <li><a href="/wiki/Queue_automaton" title="Queue automaton">Queue automaton</a></li> <li><a href="/wiki/Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li> <li><a href="/wiki/Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li> <li><a href="/wiki/Turing_machine" title="Turing machine">Turing machine</a> <ul><li><a href="/wiki/Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li> <li><a href="/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal</a></li> <li><a href="/wiki/Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li> <li><a href="/wiki/Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li> <li><a href="/wiki/Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li> <li><a href="/wiki/Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li> <li><a href="/wiki/Hypercomputation" title="Hypercomputation">Hypercomputation</a></li> <li><a href="/wiki/Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li> <li><a href="/wiki/History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li> <li><a href="/wiki/Stack_machine" title="Stack machine">Stack machine</a></li> <li><a href="/wiki/Register_machine" title="Register machine">Register machines</a> <ul><li><a href="/wiki/Counter_machine" title="Counter machine">Counter</a></li> <li><a href="/wiki/Pointer_machine" title="Pointer machine">Pointer</a></li> <li><a href="/wiki/Random-access_machine" title="Random-access machine">Random-access</a></li> <li><a href="/wiki/Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></li> <li><a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li> <li><a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard</a> <ul><li><a href="/wiki/Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li> <li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li> <li><a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li> <li><a href="/wiki/Cellular_architecture" title="Cellular architecture">Cellular</a></li> <li><a href="/wiki/Endianness" title="Endianness">Endianness</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Memory access</a> <ul><li><a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li> <li><a href="/wiki/Uniform_memory_access" title="Uniform memory access">HUMA</a></li> <li><a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li> <li><a href="/wiki/Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li> <li><a href="/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a> <ul><li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li> <li><a href="/wiki/Fabric_computing" title="Fabric computing">Fabric</a></li> <li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li> <li><a href="/wiki/Cognitive_computing" title="Cognitive computing">Cognitive</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a class="mw-selflink selflink">Instruction set<br />architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li> <li><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></li> <li><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li> <li><a href="/wiki/Explicit_data_graph_execution" title="Explicit data graph execution">EDGE</a> <ul><li><a href="/wiki/TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li> <li><a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> <ul><li><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></li></ul></li> <li><a href="/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">MISC</a></li> <li><a href="/wiki/One-instruction_set_computer" title="One-instruction set computer">OISC</a></li> <li><a href="/wiki/No_instruction_set_computing" title="No instruction set computing">NISC</a></li> <li><a href="/wiki/Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">ZISC</a></li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Quantum_computing" title="Quantum computing">Quantum computing</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a> <ul><li><a href="/wiki/Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br />sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li> <li><a href="/wiki/VAX" title="VAX">VAX</a></li> <li><a href="/wiki/PDP-11_architecture" title="PDP-11 architecture">PDP-11</a></li> <li><a href="/wiki/X86" title="X86">x86</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li>Power <ul><li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li></ul></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a href="/wiki/SuperH" title="SuperH">SuperH</a></li> <li><a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li> <li><a href="/wiki/ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/IA-64" title="IA-64">Itanium</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/Little_man_computer" title="Little man computer">LMC</a></li> <li>System/3x0 <ul><li><a href="/wiki/IBM_System/360_architecture" title="IBM System/360 architecture">S/360</a></li> <li><a href="/wiki/IBM_System/370" title="IBM System/370">S/370</a></li> <li><a href="/wiki/IBM_System/390" title="IBM System/390">S/390</a></li> <li><a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li> <li>Tilera ISA</li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Adapteva#Products" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li> <li><a href="/wiki/Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li> <li><a href="/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Data_dependency" title="Data dependency">Data dependency</a></li> <li><a href="/wiki/Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li> <li><a href="/wiki/Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li> <li><a href="/wiki/False_sharing" title="False sharing">False sharing</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Scoreboarding" title="Scoreboarding">Scoreboarding</a></li> <li><a href="/wiki/Tomasulo%27s_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a> <ul><li><a href="/wiki/Reservation_station" title="Reservation station">Reservation station</a></li> <li><a href="/wiki/Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li> <li><a href="/wiki/Register_renaming" title="Register renaming">Register renaming</a></li> <li><a href="/wiki/Wide-issue" title="Wide-issue">Wide-issue</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch prediction</a></li> <li><a href="/wiki/Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit-level_parallelism" title="Bit-level parallelism">Bit</a> <ul><li><a href="/wiki/Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li> <li><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word</a></li></ul></li> <li><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li> <li><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Pipelining</a> <ul><li><a href="/wiki/Scalar_processor" title="Scalar processor">Scalar</a></li> <li><a href="/wiki/Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li> <li><a href="/wiki/Task_parallelism" title="Task parallelism">Task</a> <ul><li><a href="/wiki/Thread_(computing)" title="Thread (computing)">Thread</a></li> <li><a href="/wiki/Process_(computing)" title="Process (computing)">Process</a></li></ul></li> <li><a href="/wiki/Data_parallelism" title="Data parallelism">Data</a> <ul><li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li></ul></li> <li><a href="/wiki/Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li> <li><a href="/wiki/Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Temporal_multithreading" title="Temporal multithreading">Temporal</a></li> <li><a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> <ul><li><a href="/wiki/Hyper-threading" title="Hyper-threading">Hyperthreading</a></li> <li><a href="/wiki/Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li> <li><a href="/wiki/Speculative_multithreading" title="Speculative multithreading">Speculative</a></li> <li><a href="/wiki/Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li> <li><a href="/wiki/Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single_instruction,_single_data" title="Single instruction, single data">SISD</a></li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> <ul><li><a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li> <li><a href="/wiki/SWAR" title="SWAR">SWAR</a></li></ul></li> <li><a href="/wiki/Multiple_instruction,_single_data" title="Multiple instruction, single data">MISD</a></li> <li><a href="/wiki/Multiple_instruction,_multiple_data" title="Multiple instruction, multiple data">MIMD</a> <ul><li><a href="/wiki/Single_program,_multiple_data" title="Single program, multiple data">SPMD</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_performance" title="Computer performance">Processor<br />performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a></li> <li><a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC) <ul><li><a href="/wiki/Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li> <li><a href="/wiki/Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li> <li><a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li> <li><a href="/wiki/Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li> <li><a href="/wiki/SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li> <li><a href="/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li> <li><a href="/wiki/Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU) <ul><li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li> <li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li> <li><a href="/wiki/Barrel_processor" title="Barrel processor">Barrel</a></li> <li><a href="/wiki/Stream_processing" title="Stream processing">Stream</a></li> <li><a href="/wiki/Tile_processor" title="Tile processor">Tile processor</a></li> <li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">FPOA</a></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li> <li><a href="/wiki/System_in_a_package" title="System in a package">System in a package</a> (SiP)</li> <li><a href="/wiki/Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li> <li><a href="/wiki/Microcontroller" title="Microcontroller">Microcontroller</a></li> <li><a href="/wiki/Mobile_processor" title="Mobile processor">Mobile</a></li> <li><a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">ASIP</a></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br />on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li> <li><a href="/wiki/Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware<br />accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/AI_accelerator" title="AI accelerator">AI accelerator</a></li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li> <li><a href="/wiki/Image_processor" title="Image processor">Image processor</a></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li> <li><a href="/wiki/Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li> <li><a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li> <li><a href="/wiki/Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li> <li><a href="/wiki/Network_processor" title="Network processor">Network processor</a></li> <li><a href="/wiki/Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/1-bit_computing" title="1-bit computing">1-bit</a></li> <li><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></li> <li><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></li> <li><a href="/wiki/12-bit_computing" title="12-bit computing">12-bit</a></li> <li><a href="/wiki/Apollo_Guidance_Computer" title="Apollo Guidance Computer">15-bit</a></li> <li><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></li> <li><a href="/wiki/24-bit_computing" title="24-bit computing">24-bit</a></li> <li><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></li> <li><a href="/wiki/48-bit_computing" title="48-bit computing">48-bit</a></li> <li><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></li> <li><a href="/wiki/128-bit_computing" title="128-bit computing">128-bit</a></li> <li><a href="/wiki/256-bit_computing" title="256-bit computing">256-bit</a></li> <li><a href="/wiki/512-bit_computing" title="512-bit computing">512-bit</a></li> <li><a href="/wiki/Bit_slicing" title="Bit slicing">bit slicing</a></li> <li><a href="/wiki/Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a> <ul><li><a href="/wiki/Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-core" title="Single-core">Single-core</a></li> <li><a href="/wiki/Multi-core_processor" title="Multi-core processor">Multi-core</a></li> <li><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Core</a></li> <li><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li> <li><a href="/wiki/Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li> <li><a href="/wiki/Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li> <li><a href="/wiki/Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">coherence</a></li></ul></li> <li><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus</a></li> <li><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></li> <li><a href="/wiki/Clock_signal" title="Clock signal">Clock signal</a></li> <li><a href="/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a></li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Execution_unit" title="Execution unit">Functional<br />units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li> <li><a href="/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li> <li><a href="/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li> <li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU) <ul><li><a href="/wiki/Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li> <li><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li> <li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch predictor</a></li> <li><a href="/wiki/Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li> <li><a href="/wiki/Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC) <ul><li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li> <li><a href="/wiki/Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential</a></li> <li><a href="/wiki/Glue_logic" title="Glue logic">Glue</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a> <ul><li><a href="/wiki/Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li> <li><a href="/wiki/Gate_array" title="Gate array">Array</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Processor_register" title="Processor register">Processor register</a></li> <li><a href="/wiki/Status_register" title="Status register">Status register</a></li> <li><a href="/wiki/Stack_register" title="Stack register">Stack register</a></li> <li><a href="/wiki/Register_file" title="Register file">Register file</a></li> <li><a href="/wiki/Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li> <li><a href="/wiki/Memory_address_register" title="Memory address register">Memory address register</a></li> <li><a href="/wiki/Program_counter" title="Program counter">Program counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li> <li><a href="/wiki/Instruction_unit" title="Instruction unit">Instruction unit</a></li> <li><a href="/wiki/Data_buffer" title="Data buffer">Data buffer</a></li> <li><a href="/wiki/Write_buffer" title="Write buffer">Write buffer</a></li> <li><a href="/wiki/Microcode" title="Microcode">Microcode</a> <a href="/wiki/ROM_image" title="ROM image">ROM</a></li> <li><a href="/wiki/Counter_(digital)" title="Counter (digital)">Counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multiplexer" title="Multiplexer">Multiplexer</a></li> <li><a href="/wiki/Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li> <li><a href="/wiki/Adder_(electronics)" title="Adder (electronics)">Adder</a></li> <li><a href="/wiki/Binary_multiplier" title="Binary multiplier">Multiplier</a> <ul><li><a href="/wiki/CPU_multiplier" title="CPU multiplier">CPU</a></li></ul></li> <li><a href="/wiki/Binary_decoder" title="Binary decoder">Binary decoder</a> <ul><li><a href="/wiki/Address_decoder" title="Address decoder">Address decoder</a></li> <li><a href="/wiki/Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li> <li><a href="/wiki/Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> <ul><li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D</a></li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li> <li><a href="/wiki/Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean</a></li> <li><a href="/wiki/Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li> <li><a href="/wiki/Analogue_electronics" title="Analogue electronics">Analog</a></li> <li><a href="/wiki/Quantum_circuit" title="Quantum circuit">Quantum</a></li> <li><a href="/wiki/Switch#Electronic_switches" title="Switch">Switch</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Power_management" title="Power management">Power<br />management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Power_Management_Unit" title="Power Management Unit">PMU</a></li> <li><a href="/wiki/Advanced_Power_Management" title="Advanced Power Management">APM</a></li> <li><a href="/wiki/ACPI" title="ACPI">ACPI</a></li> <li><a href="/wiki/Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li> <li><a href="/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li> <li><a href="/wiki/Clock_gating" title="Clock gating">Clock gating</a></li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li> <li><a href="/wiki/Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li> <li><a href="/wiki/Processor_design" title="Processor design">Processor design</a></li> <li><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li> <li><a href="/wiki/Hardware_security_module" title="Hardware security module">Hardware security module</a></li> <li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li> <li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Pin_grid_array" title="Pin grid array">Pin grid array</a></li> <li><a href="/wiki/Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox authority-control" aria-label="Navbox" style="padding:3px"><table class="nowraplinks hlist navbox-inner" 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