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reconfigurable FPGA</title> <meta name="description" content="Search results for: reconfigurable FPGA"> <meta name="keywords" content="reconfigurable FPGA"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> <button class="d-block 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action="https://publications.waset.org/abstracts/search"> <div id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="reconfigurable FPGA"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 141</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: reconfigurable FPGA</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">141</span> Numerical Solution Speedup of the Laplace Equation Using FPGA Hardware</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abbas%20Ebrahimi">Abbas Ebrahimi</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohammad%20Zandsalimy"> Mohammad Zandsalimy</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The main purpose of this study is to investigate the feasibility of using FPGA (Field Programmable Gate Arrays) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the Laplace equation. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is an SoC (System on a Chip) FPGA type that integrates both microprocessor and FPGA architectures into a single device. In the present study the Laplace equation is implemented and solved numerically on both reconfigurable hardware and CPU. The precision of results and speedups of the calculations are compared together. The computational process on FPGA, is up to 20 times faster than a conventional CPU, with the same data precision. An analytical solution is used to validate the results. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=accelerating%20numerical%20solutions" title="accelerating numerical solutions">accelerating numerical solutions</a>, <a href="https://publications.waset.org/abstracts/search?q=CFD" title=" CFD"> CFD</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=hardware%20definition%20language" title=" hardware definition language"> hardware definition language</a>, <a href="https://publications.waset.org/abstracts/search?q=numerical%20solutions" title=" numerical solutions"> numerical solutions</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20hardware" title=" reconfigurable hardware"> reconfigurable hardware</a> </p> <a href="https://publications.waset.org/abstracts/68002/numerical-solution-speedup-of-the-laplace-equation-using-fpga-hardware" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/68002.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">383</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">140</span> Exploration of Various Metrics for Partitioning of Cellular Automata Units for Efficient Reconfiguration of Field Programmable Gate Arrays (FPGAs)</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Peter%20Tabatt">Peter Tabatt</a>, <a href="https://publications.waset.org/abstracts/search?q=Christian%20Siemers"> Christian Siemers</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Using FPGA devices to improve the behavior of time-critical parts of embedded systems is a proven concept for years. With reconfigurable FPGA devices, the logical blocks can be partitioned and grouped into static and dynamic parts. The dynamic parts can be reloaded 'on demand' at runtime. This work uses cellular automata, which are constructed through compilation from (partially restricted) ANSI-C sources, to determine the suitability of various metrics for optimal partitioning. Significant metrics, in this case, are for example the area on the FPGA device for the partition, the pass count for loop constructs and communication characteristics to other partitions. With successful partitioning, it is possible to use smaller FPGA devices for the same requirements as with not reconfigurable FPGA devices or – vice versa – to use the same FPGAs for larger programs. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20FPGA" title="reconfigurable FPGA">reconfigurable FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=cellular%20automata" title=" cellular automata"> cellular automata</a>, <a href="https://publications.waset.org/abstracts/search?q=partitioning" title=" partitioning"> partitioning</a>, <a href="https://publications.waset.org/abstracts/search?q=metrics" title=" metrics"> metrics</a>, <a href="https://publications.waset.org/abstracts/search?q=parallel%20computing" title=" parallel computing"> parallel computing</a> </p> <a href="https://publications.waset.org/abstracts/56244/exploration-of-various-metrics-for-partitioning-of-cellular-automata-units-for-efficient-reconfiguration-of-field-programmable-gate-arrays-fpgas" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/56244.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">272</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">139</span> Embedded Hw-Sw Reconfigurable Techniques For Wireless Sensor Network Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=B.%20Kirubakaran">B. Kirubakaran</a>, <a href="https://publications.waset.org/abstracts/search?q=C.%20Rajasekaran"> C. Rajasekaran </a> </p> <p class="card-text"><strong>Abstract:</strong></p> Reconfigurable techniques are used in many engineering and industrial applications for the efficient data transmissions through the wireless sensor networks. Nowadays most of the industrial applications are work for try to minimize the size and cost. During runtime the reconfigurable technique avoid the unwanted hang and delay in the system performance. In recent world Field Programmable Gate Array (FPGA) as one of the most efficient reconfigurable device and widely used for most of the hardware and software reconfiguration applications. In this paper, the work deals with whatever going to make changes in the hardware and software during runtime it’s should not affect the current running process that’s the main objective of the paper our changes be done in a parallel manner at the same time concentrating the cost and power transmission problems during data trans-receiving. Analog sensor (Temperature) as an input for the controller (PIC) through that control the FPGA digital sensors in generalized manner. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=field%20programmable%20gate%20array" title="field programmable gate array">field programmable gate array</a>, <a href="https://publications.waset.org/abstracts/search?q=peripheral%20interrupt%20controller" title=" peripheral interrupt controller"> peripheral interrupt controller</a>, <a href="https://publications.waset.org/abstracts/search?q=runtime%20reconfigurable%20techniques" title=" runtime reconfigurable techniques"> runtime reconfigurable techniques</a>, <a href="https://publications.waset.org/abstracts/search?q=wireless%20sensor%20networks" title=" wireless sensor networks"> wireless sensor networks</a> </p> <a href="https://publications.waset.org/abstracts/5897/embedded-hw-sw-reconfigurable-techniques-for-wireless-sensor-network-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/5897.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">407</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">138</span> Design and Implementation of Wave-Pipelined Circuit Using Reconfigurable Technique</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Adhinarayanan%20Venkatasubramanian">Adhinarayanan Venkatasubramanian</a> </p> <p class="card-text"><strong>Abstract:</strong></p> For design of high speed digital circuit wave pipeline is the best approach this can be operated at higher operating frequencies by adjusting clock periods and skews so as latch the o/p of combinational logic circuit at the stable period. In this paper, there are two methods are proposed in automation task one is BIST (Built in self test) and second method is Reconfigurable technique. For the above two approaches dedicated AND gate (multiplier) by applying wave pipeline technique. BIST approach is implemented by Xilinx Spartan-II device. In reconfigurable technique done by ASIC. From the results, wave pipeline circuits are faster than nonpipeline circuit and area, power dissipation are reduced by reconfigurable technique. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SOC" title="SOC">SOC</a>, <a href="https://publications.waset.org/abstracts/search?q=wave-pipelining" title=" wave-pipelining"> wave-pipelining</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=self-testing" title=" self-testing"> self-testing</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable" title=" reconfigurable"> reconfigurable</a>, <a href="https://publications.waset.org/abstracts/search?q=ASIC" title=" ASIC"> ASIC</a> </p> <a href="https://publications.waset.org/abstracts/15244/design-and-implementation-of-wave-pipelined-circuit-using-reconfigurable-technique" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/15244.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">427</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">137</span> Reconfigurable Efficient IIR Filter Design Using MAC Algorithm </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Rajesh%20Mehra">Rajesh Mehra</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper an IIR filter has been designed and simulated on an FPGA. The implementation is based on MAC algorithm which uses multiply-and-accumulate operations IIR filter design implementation. Parallel Pipelined structure is used to implement the proposed IIR Filter taking optimal advantage of the look up table of the FPGA device. The designed filter has been synthesized on DSP slice based FPGA to perform multiplier function of MAC unit. The DSP slices are useful to enhance the speed performance. The developed IIR filter is designed and simulated with MATLAB and synthesized with Xilinx Synthesis Tool (XST), and implemented on Virtex 5 and Spartan 3 ADSP FPGA devices. The IIR filter implemented on Virtex 5 FPGA can operate at an estimated frequency of 81.5 MHz as compared to 40.5 MHz in case of Spartan 3 ADSP FPGA. The Virtex 5 based implementation also consumes less slices and slice flip flops of target FPGA in comparison to Spartan 3 ADSP based implementation to provide cost effective solution for signal processing applications. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=butterworth" title="butterworth">butterworth</a>, <a href="https://publications.waset.org/abstracts/search?q=DSP" title=" DSP"> DSP</a>, <a href="https://publications.waset.org/abstracts/search?q=IIR" title=" IIR"> IIR</a>, <a href="https://publications.waset.org/abstracts/search?q=MAC" title=" MAC"> MAC</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA "> FPGA </a> </p> <a href="https://publications.waset.org/abstracts/13274/reconfigurable-efficient-iir-filter-design-using-mac-algorithm" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/13274.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">357</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">136</span> FPGA Based IIR Filter Design Using MAC Algorithm</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Rajesh%20Mehra">Rajesh Mehra</a>, <a href="https://publications.waset.org/abstracts/search?q=Bharti%20Thakur"> Bharti Thakur</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, an IIR filter has been designed and simulated on an FPGA. The implementation is based on MAC algorithm which uses multiply-and-accumulate operations IIR filter design implementation. Parallel Pipelined structure is used to implement the proposed IIR Filter taking optimal advantage of the look up table of the FPGA device. The designed filter has been synthesized on DSP slice based FPGA to perform multiplier function of MAC unit. The DSP slices are useful to enhance the speed performance. The developed IIR filter is designed and simulated with Matlab and synthesized with Xilinx Synthesis Tool (XST), and implemented on Virtex 5 and Spartan 3 ADSP FPGA devices. The IIR filter implemented on Virtex 5 FPGA can operate at an estimated frequency of 81.5 MHz as compared to 40.5 MHz in case of Spartan 3 ADSP FPGA. The Virtex 5 based implementation also consumes less slices and slice flip flops of target FPGA in comparison to Spartan 3 ADSP based implementation to provide cost effective solution for signal processing applications. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Butterworth%20filter" title="Butterworth filter">Butterworth filter</a>, <a href="https://publications.waset.org/abstracts/search?q=DSP" title=" DSP"> DSP</a>, <a href="https://publications.waset.org/abstracts/search?q=IIR" title=" IIR"> IIR</a>, <a href="https://publications.waset.org/abstracts/search?q=MAC" title=" MAC"> MAC</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a> </p> <a href="https://publications.waset.org/abstracts/41409/fpga-based-iir-filter-design-using-mac-algorithm" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/41409.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">388</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">135</span> Preliminary Findings from a Research Survey on Evolution of Software Defined Radio</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=M.%20Srilatha">M. Srilatha</a>, <a href="https://publications.waset.org/abstracts/search?q=R.%20Hemalatha"> R. Hemalatha</a>, <a href="https://publications.waset.org/abstracts/search?q=T.%20Sri%20Aditya"> T. Sri Aditya </a> </p> <p class="card-text"><strong>Abstract:</strong></p> Communication of today world is dominated by wireless technology. This is mainly due to the revolutionary development of new wireless communication system generations. The evolving new generations of wireless systems are accommodating the demand through better resource management including improved transmission technologies with optimized communication devices. To keep up with the evolution of technologies, the communication systems must be designed to optimize transparent insertion of newly evolved technologies virtually at all stages of their life cycle. After the insertion of new technologies, the upgraded devices should continue the communication without squalor in quality. The concern of improving spectrum access and spectrum efficiency combined with both the introduction of Software Defined Radios (SDR) and the possibility of the software application to radios has led to an evolution of wireless radio research. The software defined radio term was coined in the 1970s to overcome the problems in the application of software to wireless radios which eliminates the requirement of hardware changes. SDR has become the prime theme of research since it eliminates the drawbacks associated with conventional wireless communication systems implementation. This paper identifies and discusses key enabling technologies and possibility of research and development in SDRs. In addition transmitter and receiver architectures of SDR are also discussed along with their feasibility for reconfigurable radio application. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=software%20defined%20radios" title="software defined radios">software defined radios</a>, <a href="https://publications.waset.org/abstracts/search?q=wireless%20communication" title=" wireless communication"> wireless communication</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable" title=" reconfigurable"> reconfigurable</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20transmitter" title=" reconfigurable transmitter"> reconfigurable transmitter</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20receivers" title=" reconfigurable receivers"> reconfigurable receivers</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=DSP" title=" DSP"> DSP</a> </p> <a href="https://publications.waset.org/abstracts/11812/preliminary-findings-from-a-research-survey-on-evolution-of-software-defined-radio" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/11812.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">314</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">134</span> Reconfigurable Multiband Meandered Line Antenna</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=D.%20Rama%20Krishna">D. Rama Krishna</a>, <a href="https://publications.waset.org/abstracts/search?q=Y.%20Pandu%20Rangaiah"> Y. Pandu Rangaiah</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents the design of multiband reconfigurable antenna using PIN diodes for four iterations and all the four iterations have been validated by measuring return loss and pattern measurements of developed prototype antenna. The simulated and experimental data have demonstrated the concepts of a multiband reconfigurable antenna by switching OFF and ON of PIN diodes for multiple band frequencies. The technique has taken the advantage of a different number of radiating lengths with the use of PIN diode switches, each configuration resonating at multiband frequencies. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=frequency%20reconfigurable" title="frequency reconfigurable">frequency reconfigurable</a>, <a href="https://publications.waset.org/abstracts/search?q=meandered%20line%20multiband%20antenna" title=" meandered line multiband antenna"> meandered line multiband antenna</a>, <a href="https://publications.waset.org/abstracts/search?q=PIN%20diode" title=" PIN diode"> PIN diode</a>, <a href="https://publications.waset.org/abstracts/search?q=multiband%20frequencies" title=" multiband frequencies"> multiband frequencies</a> </p> <a href="https://publications.waset.org/abstracts/10408/reconfigurable-multiband-meandered-line-antenna" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/10408.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">387</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">133</span> Run-Time Customisation of Soft-Core CPUs on Field Programmable Gate Array</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Rehab%20Abdullah%20Shendi">Rehab Abdullah Shendi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The use of customised soft-core processors in which instructions can be integrated into a system in application hardware is increasing in the Field Programmable Gate Array (FPGA) field. Specifically, the partial run-time reconfiguration of FPGAs in specialised processors for a particular domain can be very beneficial. In this report, the design and implementation for the customisation of a soft-core MIPS processor using an FPGA and partial reconfiguration (PR) of FPGA technology will be addressed to achieve efficient resource use. This can be achieved using a PR design flow that helps the design fit into a smaller device. Moreover, the impact of static power consumption could be reduced due to runtime reconfiguration. This will be done by configurable custom instructions implemented in the hardware as an extension on the MIPS CPU. The aim of this project is to investigate the PR of FPGAs for run-time adaptations of the instruction set of a soft-core CPU, including the integration of custom instructions and the exploration of the potential to use the MultiBoot feature available in Xilinx FPGAs to carry out the PR process. The system will be evaluated and tested on a Nexus 3 development board featuring a Xilinx Spartran-6 FPGA. The system will be able to load reconfigurable custom instructions dynamically into user programs with the help of the trap handler when the custom instruction is called by the MIPS CPU. The results of this experiment demonstrate that custom instructions in hardware can speed up a certain function and many instructions can be saved when compared to a software implementation of the same function. Implementing custom instructions in hardware is perfectly possible and worth exploring. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=customisation" title="customisation">customisation</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=MIPS" title=" MIPS"> MIPS</a>, <a href="https://publications.waset.org/abstracts/search?q=partial%20reconfiguration" title=" partial reconfiguration"> partial reconfiguration</a>, <a href="https://publications.waset.org/abstracts/search?q=PR" title=" PR"> PR</a> </p> <a href="https://publications.waset.org/abstracts/51763/run-time-customisation-of-soft-core-cpus-on-field-programmable-gate-array" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/51763.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">267</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">132</span> Role of Discrete Event Simulation in the Assessment and Selection of the Potential Reconfigurable Manufacturing Solutions</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mohsin%20Raza">Mohsin Raza</a>, <a href="https://publications.waset.org/abstracts/search?q=Arne%20Bilberg"> Arne Bilberg</a>, <a href="https://publications.waset.org/abstracts/search?q=Thomas%20Ditlev%20Brun%C3%B8"> Thomas Ditlev Brunø</a>, <a href="https://publications.waset.org/abstracts/search?q=Ann-Louise%20Andersen"> Ann-Louise Andersen</a>, <a href="https://publications.waset.org/abstracts/search?q=Filip%20SK%C3%A4rin"> Filip SKärin</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Shifting from a dedicated or flexible manufacturing system to a reconfigurable manufacturing system (RMS) requires a significant amount of time, money, and effort. Therefore, it is vital to verify beforehand that the potential reconfigurable solution will be able to achieve the organizational objectives. Discrete event simulation offers the opportunity of assessing several reconfigurable alternatives against the set objectives. This study signifies the importance of using discrete-event simulation as a tool to verify several reconfiguration options. Two different industrial cases have been presented in the study to elaborate on the role of discrete event simulation in the implementation methodology of RMSs. The study concluded that discrete event simulation is one of the important tools to consider in the RMS implementation methodology. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20manufacturing%20system" title="reconfigurable manufacturing system">reconfigurable manufacturing system</a>, <a href="https://publications.waset.org/abstracts/search?q=discrete%20event%20simulation" title=" discrete event simulation"> discrete event simulation</a>, <a href="https://publications.waset.org/abstracts/search?q=Tecnomatix%20plant%20simulation" title=" Tecnomatix plant simulation"> Tecnomatix plant simulation</a>, <a href="https://publications.waset.org/abstracts/search?q=RMS" title=" RMS"> RMS</a> </p> <a href="https://publications.waset.org/abstracts/150254/role-of-discrete-event-simulation-in-the-assessment-and-selection-of-the-potential-reconfigurable-manufacturing-solutions" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/150254.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">124</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">131</span> Computational Analysis on Thermal Performance of Chip Package in Electro-Optical Device</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Long%20Kim%20Vu">Long Kim Vu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The central processing unit in Electro-Optical devices is a Field-programmable gate array (FPGA) chip package allowing flexible, reconfigurable computing but energy consumption. Because chip package is placed in isolated devices based on IP67 waterproof standard, there is no air circulation and the heat dissipation is a challenge. In this paper, the author successfully modeled a chip package which various interposer materials such as silicon, glass and organics. Computational fluid dynamics (CFD) was utilized to analyze the thermal performance of chip package in the case of considering comprehensive heat transfer modes: conduction, convection and radiation, which proposes equivalent heat dissipation. The logic chip temperature varying with time is compared between the simulation and experiment results showing the excellent correlation, proving the reasonable chip modeling and simulation method. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CFD" title="CFD">CFD</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=heat%20transfer" title=" heat transfer"> heat transfer</a>, <a href="https://publications.waset.org/abstracts/search?q=thermal%20analysis" title=" thermal analysis"> thermal analysis</a> </p> <a href="https://publications.waset.org/abstracts/137585/computational-analysis-on-thermal-performance-of-chip-package-in-electro-optical-device" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/137585.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">184</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">130</span> A Low-Area Fully-Reconfigurable Hardware Design of Fast Fourier Transform System for 3GPP-LTE Standard</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Xin-Yu%20Shih">Xin-Yu Shih</a>, <a href="https://publications.waset.org/abstracts/search?q=Yue-Qu%20Liu"> Yue-Qu Liu</a>, <a href="https://publications.waset.org/abstracts/search?q=Hong-Ru%20Chou"> Hong-Ru Chou</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm<sup>2</sup> and dissipates 233.5 mW at maximal operating frequency of 250 MHz. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=reconfigurable" title="reconfigurable">reconfigurable</a>, <a href="https://publications.waset.org/abstracts/search?q=fast%20Fourier%20transform%20%28FFT%29" title=" fast Fourier transform (FFT)"> fast Fourier transform (FFT)</a>, <a href="https://publications.waset.org/abstracts/search?q=single-path%20delay%20feedback%20%28SDF%29" title=" single-path delay feedback (SDF)"> single-path delay feedback (SDF)</a>, <a href="https://publications.waset.org/abstracts/search?q=3GPP-LTE" title=" 3GPP-LTE"> 3GPP-LTE</a> </p> <a href="https://publications.waset.org/abstracts/62069/a-low-area-fully-reconfigurable-hardware-design-of-fast-fourier-transform-system-for-3gpp-lte-standard" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/62069.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">278</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">129</span> A New Design Methodology for Partially Reconfigurable Systems-on-Chip</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Roukaya%20Dalbouchi">Roukaya Dalbouchi</a>, <a href="https://publications.waset.org/abstracts/search?q=Abdelkrin%20Zitouni"> Abdelkrin Zitouni</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, we propose a novel design methodology for Dynamic Partial Reconfigurable (DPR) system. This type of system has the property of being able to be modified after its design and during its execution. The suggested design methodology is generic in terms of granularity, number of modules, and reconfigurable region and suitable for any type of modern application. It is based on the interconnection between several design stages. The recommended methodology represents a guide for the design of DPR architectures that meet compromise reconfiguration/performance. To validate the proposed methodology, we use as an application a video watermarking. The comparison result shows that the proposed methodology supports all stages of DPR architecture design and characterized by a high abstraction level. It provides a dynamic/partial reconfigurable architecture; it guarantees material efficiency, the flexibility of reconfiguration, and superior performance in terms of frequency and power consumption. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=dynamically%20reconfigurable%20system" title="dynamically reconfigurable system">dynamically reconfigurable system</a>, <a href="https://publications.waset.org/abstracts/search?q=block%20matching%20algorithm" title=" block matching algorithm"> block matching algorithm</a>, <a href="https://publications.waset.org/abstracts/search?q=partial%20reconfiguration" title=" partial reconfiguration"> partial reconfiguration</a>, <a href="https://publications.waset.org/abstracts/search?q=motion%20vectors" title=" motion vectors"> motion vectors</a>, <a href="https://publications.waset.org/abstracts/search?q=video%20watermarking" title=" video watermarking"> video watermarking</a> </p> <a href="https://publications.waset.org/abstracts/155577/a-new-design-methodology-for-partially-reconfigurable-systems-on-chip" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/155577.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">95</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">128</span> Attribute Based Comparison and Selection of Modular Self-Reconfigurable Robot Using Multiple Attribute Decision Making Approach</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Manpreet%20Singh">Manpreet Singh</a>, <a href="https://publications.waset.org/abstracts/search?q=V.%20P.%20Agrawal"> V. P. Agrawal</a>, <a href="https://publications.waset.org/abstracts/search?q=Gurmanjot%20Singh%20Bhatti"> Gurmanjot Singh Bhatti</a> </p> <p class="card-text"><strong>Abstract:</strong></p> From the last decades, there is a significant technological advancement in the field of robotics, and a number of modular self-reconfigurable robots were introduced that can help in space exploration, bucket to stuff, search, and rescue operation during earthquake, etc. As there are numbers of self-reconfigurable robots, choosing the optimum one is always a concern for robot user since there is an increase in available features, facilities, complexity, etc. The objective of this research work is to present a multiple attribute decision making based methodology for coding, evaluation, comparison ranking and selection of modular self-reconfigurable robots using a technique for order preferences by similarity to ideal solution approach. However, 86 attributes that affect the structure and performance are identified. A database for modular self-reconfigurable robot on the basis of different pertinent attribute is generated. This database is very useful for the user, for selecting a robot that suits their operational needs. Two visual methods namely linear graph and spider chart are proposed for ranking of modular self-reconfigurable robots. Using five robots (Atron, Smores, Polybot, M-Tran 3, Superbot), an example is illustrated, and raking of the robots is successfully done, which shows that Smores is the best robot for the operational need illustrated, and this methodology is found to be very effective and simple to use. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=self-reconfigurable%20robots" title="self-reconfigurable robots">self-reconfigurable robots</a>, <a href="https://publications.waset.org/abstracts/search?q=MADM" title=" MADM"> MADM</a>, <a href="https://publications.waset.org/abstracts/search?q=TOPSIS" title=" TOPSIS"> TOPSIS</a>, <a href="https://publications.waset.org/abstracts/search?q=morphogenesis" title=" morphogenesis"> morphogenesis</a>, <a href="https://publications.waset.org/abstracts/search?q=scalability" title=" scalability"> scalability</a> </p> <a href="https://publications.waset.org/abstracts/90771/attribute-based-comparison-and-selection-of-modular-self-reconfigurable-robot-using-multiple-attribute-decision-making-approach" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/90771.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">223</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">127</span> FPGA Implementation of the BB84 Protocol</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Jaouadi%20Ikram">Jaouadi Ikram</a>, <a href="https://publications.waset.org/abstracts/search?q=Machhout%20Mohsen"> Machhout Mohsen</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The development of a quantum key distribution (QKD) system on a field-programmable gate array (FPGA) platform is the subject of this paper. A quantum cryptographic protocol is designed based on the properties of quantum information and the characteristics of FPGAs. The proposed protocol performs key extraction, reconciliation, error correction, and privacy amplification tasks to generate a perfectly secret final key. We modeled the presence of the spy in our system with a strategy to reveal some of the exchanged information without being noticed. Using an FPGA card with a 100 MHz clock frequency, we have demonstrated the evolution of the error rate as well as the amounts of mutual information (between the two interlocutors and that of the spy) passing from one step to another in the key generation process. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=QKD" title="QKD">QKD</a>, <a href="https://publications.waset.org/abstracts/search?q=BB84" title=" BB84"> BB84</a>, <a href="https://publications.waset.org/abstracts/search?q=protocol" title=" protocol"> protocol</a>, <a href="https://publications.waset.org/abstracts/search?q=cryptography" title=" cryptography"> cryptography</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=key" title=" key"> key</a>, <a href="https://publications.waset.org/abstracts/search?q=security" title=" security"> security</a>, <a href="https://publications.waset.org/abstracts/search?q=communication" title=" communication"> communication</a> </p> <a href="https://publications.waset.org/abstracts/98812/fpga-implementation-of-the-bb84-protocol" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/98812.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">183</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">126</span> Implementation of a Method of Crater Detection Using Principal Component Analysis in FPGA</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Izuru%20Nomura">Izuru Nomura</a>, <a href="https://publications.waset.org/abstracts/search?q=Tatsuya%20Takino"> Tatsuya Takino</a>, <a href="https://publications.waset.org/abstracts/search?q=Yuji%20Kageyama"> Yuji Kageyama</a>, <a href="https://publications.waset.org/abstracts/search?q=Shin%20Nagata"> Shin Nagata</a>, <a href="https://publications.waset.org/abstracts/search?q=Hiroyuki%20Kamata"> Hiroyuki Kamata</a> </p> <p class="card-text"><strong>Abstract:</strong></p> We propose a method of crater detection from the image of the lunar surface captured by the small space probe. We use the principal component analysis (PCA) to detect craters. Nevertheless, considering　severe environment of the space, it is impossible to use generic computer in practice. Accordingly, we have to implement the method in FPGA. This paper compares FPGA and generic computer by the processing time of a method of crater detection using principal component analysis. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=crater" title="crater">crater</a>, <a href="https://publications.waset.org/abstracts/search?q=PCA" title=" PCA"> PCA</a>, <a href="https://publications.waset.org/abstracts/search?q=eigenvector" title=" eigenvector"> eigenvector</a>, <a href="https://publications.waset.org/abstracts/search?q=strength%20value" title=" strength value"> strength value</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=processing%20time" title=" processing time "> processing time </a> </p> <a href="https://publications.waset.org/abstracts/19004/implementation-of-a-method-of-crater-detection-using-principal-component-analysis-in-fpga" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/19004.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">555</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">125</span> FPGA Implementation of RSA Encryption Algorithm for E-Passport Application</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Khaled%20Shehata">Khaled Shehata</a>, <a href="https://publications.waset.org/abstracts/search?q=Hanady%20Hussien"> Hanady Hussien</a>, <a href="https://publications.waset.org/abstracts/search?q=Sara%20Yehia"> Sara Yehia</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Securing the data stored on E-passport is a very important issue. RSA encryption algorithm is suitable for such application with low data size. In this paper the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented. The module is verified through comparing the result with that obtained from MATLAB tools. The design runs at a frequency of 36.3 MHz on Virtex-5 Xilinx FPGA. The key size is designed to be 1024-bit to achieve high security for the passport information. The whole design is achieved through VHDL design entry which makes it a portable design and can be directed to any hardware platform. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=RSA" title="RSA">RSA</a>, <a href="https://publications.waset.org/abstracts/search?q=VHDL" title=" VHDL"> VHDL</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=modular%20multiplication" title=" modular multiplication"> modular multiplication</a>, <a href="https://publications.waset.org/abstracts/search?q=modular%20exponential" title=" modular exponential"> modular exponential</a> </p> <a href="https://publications.waset.org/abstracts/4249/fpga-implementation-of-rsa-encryption-algorithm-for-e-passport-application" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/4249.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">391</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">124</span> Novel Coprocessor for DNA Sequence Alignment in Resequencing Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Atef%20Ibrahim">Atef Ibrahim</a>, <a href="https://publications.waset.org/abstracts/search?q=Hamed%20Elsimary"> Hamed Elsimary</a>, <a href="https://publications.waset.org/abstracts/search?q=Abdullah%20Aljumah"> Abdullah Aljumah</a>, <a href="https://publications.waset.org/abstracts/search?q=Fayez%20Gebali"> Fayez Gebali</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a novel semi-systolic array architecture for an optimized parallel sequence alignment algorithm. This architecture has the advantage that it can be modiﬁed to be reused for multiple pass processing in order to increase the number of processing elements that can be packed into a single FPGA and to increase the number of sequences that can be aligned in parallel in a single FPGA. This resolves the potential problem of many FPGA resources left unused for designs that have large values of short read length. When using the previously published conventional hardware design. FPGA implementation results show that, for large values of short read lengths (M>128), the proposed design has a slightly higher speed up and FPGA utilization over the the conventional one. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=bioinformatics" title="bioinformatics">bioinformatics</a>, <a href="https://publications.waset.org/abstracts/search?q=genome%20sequence%20alignment" title=" genome sequence alignment"> genome sequence alignment</a>, <a href="https://publications.waset.org/abstracts/search?q=re-sequencing%20applications" title=" re-sequencing applications"> re-sequencing applications</a>, <a href="https://publications.waset.org/abstracts/search?q=systolic%20array" title=" systolic array "> systolic array </a> </p> <a href="https://publications.waset.org/abstracts/23325/novel-coprocessor-for-dna-sequence-alignment-in-resequencing-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/23325.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">531</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">123</span> Frequency Reconfigurable Multiband Patch Antenna Using PIN-Diode for ITS Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Gaurav%20Upadhyay">Gaurav Upadhyay</a>, <a href="https://publications.waset.org/abstracts/search?q=Nand%20Kishore"> Nand Kishore</a>, <a href="https://publications.waset.org/abstracts/search?q=Prashant%20Ranjan"> Prashant Ranjan</a>, <a href="https://publications.waset.org/abstracts/search?q=V.%20S.%20Tripathi"> V. S. Tripathi</a>, <a href="https://publications.waset.org/abstracts/search?q=Shivesh%20Tripathi"> Shivesh Tripathi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A frequency reconfigurable multiband antenna for intelligent transportation system (ITS) applications is proposed in this paper. A PIN-diode is used for reconfigurability. Centre frequencies are 1.38, 1.98, 2.89, 3.86, and 4.34 GHz in “ON” state of Diode and 1.56, 2.16, 2.88, 3.91 and 4.45 GHz in “OFF” state. Achieved maximum bandwidth is 18%. The maximum gain of the proposed antenna is 2.7 dBi in “ON” state and 3.95 dBi in “OFF” state of the diode. The antenna is simulated, fabricated, and tested in the lab. Measured and simulated results are in good confirmation. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=ITS" title="ITS">ITS</a>, <a href="https://publications.waset.org/abstracts/search?q=multiband%20antenna" title=" multiband antenna"> multiband antenna</a>, <a href="https://publications.waset.org/abstracts/search?q=PIN-diode" title=" PIN-diode"> PIN-diode</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable" title=" reconfigurable"> reconfigurable</a> </p> <a href="https://publications.waset.org/abstracts/84977/frequency-reconfigurable-multiband-patch-antenna-using-pin-diode-for-its-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/84977.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">347</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">122</span> Area-Efficient FPGA Implementation of an FFT Processor by Reusing Butterfly Units</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Atin%20Mukherjee">Atin Mukherjee</a>, <a href="https://publications.waset.org/abstracts/search?q=Amitabha%20Sinha"> Amitabha Sinha</a>, <a href="https://publications.waset.org/abstracts/search?q=Debesh%20Choudhury"> Debesh Choudhury</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Fast Fourier transform (FFT) of large-number of samples requires larger hardware resources of field programmable gate arrays and it asks for more area as well as power. In this paper, an area efficient architecture of FFT processor is proposed, that reuses the butterfly units more than once. The FFT processor is emulated and the results are validated on Virtex-6 FPGA. The proposed architecture outperforms the conventional architecture of a N-point FFT processor in terms of area which is reduced by a factor of log_N(2) with the negligible increase of processing time. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=FFT" title="FFT">FFT</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=resource%20optimization" title=" resource optimization"> resource optimization</a>, <a href="https://publications.waset.org/abstracts/search?q=butterfly%20units" title=" butterfly units"> butterfly units</a> </p> <a href="https://publications.waset.org/abstracts/17094/area-efficient-fpga-implementation-of-an-fft-processor-by-reusing-butterfly-units" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/17094.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">523</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">121</span> A Middleware Management System with Supporting Holonic Modules for Reconfigurable Management System</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Roscoe%20McLean">Roscoe McLean</a>, <a href="https://publications.waset.org/abstracts/search?q=Jared%20Padayachee"> Jared Padayachee</a>, <a href="https://publications.waset.org/abstracts/search?q=Glen%20Bright"> Glen Bright</a> </p> <p class="card-text"><strong>Abstract:</strong></p> There is currently a gap in the technology covering the rapid establishment of control after a reconfiguration in a Reconfigurable Manufacturing System. This gap involves the detection of the factory floor state and the communication link between the factory floor and the high-level software. In this paper, a thin, hardware-supported Middleware Management System (MMS) is proposed and its design and implementation are discussed. The research found that a cost-effective localization technique can be combined with intelligent software to speed up the ramp-up of a reconfigured system. The MMS makes the process more intelligent, more efficient and less time-consuming, thus supporting the industrial implementation of the RMS paradigm. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=intelligent%20systems" title="intelligent systems">intelligent systems</a>, <a href="https://publications.waset.org/abstracts/search?q=middleware" title=" middleware"> middleware</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable%20manufacturing" title=" reconfigurable manufacturing"> reconfigurable manufacturing</a>, <a href="https://publications.waset.org/abstracts/search?q=management%20system" title=" management system"> management system</a> </p> <a href="https://publications.waset.org/abstracts/28410/a-middleware-management-system-with-supporting-holonic-modules-for-reconfigurable-management-system" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/28410.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">675</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">120</span> Graphene-Based Reconfigurable Lens Antenna for 5G/6G and Satellite Networks</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Andr%C3%A9%20Lages">André Lages</a>, <a href="https://publications.waset.org/abstracts/search?q=Victor%20Dmitriev"> Victor Dmitriev</a>, <a href="https://publications.waset.org/abstracts/search?q=Juliano%20Bazzo"> Juliano Bazzo</a>, <a href="https://publications.waset.org/abstracts/search?q=Gianni%20Portela"> Gianni Portela</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This work evaluates the feasibility of the graphene application to perform as a wideband reconfigurable material for lens antennas in 5G/6G and satellite applications. Based on transformation optics principles, the electromagnetic waves can be efficiently guided by modifying the effective refractive index. Graphene behavior can range between a lossy dielectric and a good conductor due to the variation of its chemical potential bias, thus arising as a promising solution for electromagnetic devices. The graphene properties and a lens antenna comprising multiples layers and periodic arrangements of graphene patches were analyzed using full-wave simulations. A dipole directivity was improved from 7 to 18.5 dBi at 29 GHz. In addition, the realized gain was enhanced 7 dB across a 14 GHz bandwidth within the Ka/5G band. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=5G%2F6G" title="5G/6G">5G/6G</a>, <a href="https://publications.waset.org/abstracts/search?q=graphene" title=" graphene"> graphene</a>, <a href="https://publications.waset.org/abstracts/search?q=lens" title=" lens"> lens</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable" title=" reconfigurable"> reconfigurable</a>, <a href="https://publications.waset.org/abstracts/search?q=satellite" title=" satellite"> satellite</a> </p> <a href="https://publications.waset.org/abstracts/121554/graphene-based-reconfigurable-lens-antenna-for-5g6g-and-satellite-networks" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/121554.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">146</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">119</span> Single Chip Controller Design for Piezoelectric Actuators with Mixed Signal FPGA </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Han-Bin%20Park">Han-Bin Park</a>, <a href="https://publications.waset.org/abstracts/search?q=Taesam%20Kang"> Taesam Kang</a>, <a href="https://publications.waset.org/abstracts/search?q=SunKi%20Hong"> SunKi Hong</a>, <a href="https://publications.waset.org/abstracts/search?q=Jeong%20Hoi%20Gu"> Jeong Hoi Gu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The piezoelectric material is being used widely for actuators due to its large power density with simple structure. It can generate a larger force than the conventional actuators with the same size. Furthermore, the response time of piezoelectric actuators is very short, and thus, it can be used for very fast system applications with compact size. To control the piezoelectric actuator, we need analog signal conditioning circuits as well as digital microcontrollers. Conventional microcontrollers are not equipped with analog parts and thus the control system becomes bulky compared with the small size of the piezoelectric devices. To overcome these weaknesses, we are developing one-chip micro controller that can handle analog and digital signals simultaneously using mixed signal FPGA technology. We used the SmartFusion™ FPGA device that integrates ARM®Cortex-M3, analog interface and FPGA fabric in a single chip and offering full customization. It gives more flexibility than traditional fixed-function microcontrollers with the excessive cost of soft processor cores on traditional FPGAs. In this paper we introduce the design of single chip controller using mixed signal FPGA, SmartFusion™[1] device. To demonstrate its performance, we implemented a PI controller for power driving circuit and a 5th order H-infinity controller for the system with piezoelectric actuator in the FPGA fabric. We also demonstrated the regulation of a power output and the operation speed of a 5th order H-infinity controller. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=mixed%20signal%20FPGA" title="mixed signal FPGA">mixed signal FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=PI%20control" title=" PI control"> PI control</a>, <a href="https://publications.waset.org/abstracts/search?q=piezoelectric%20actuator" title=" piezoelectric actuator"> piezoelectric actuator</a>, <a href="https://publications.waset.org/abstracts/search?q=SmartFusion%E2%84%A2" title=" SmartFusion™"> SmartFusion™</a> </p> <a href="https://publications.waset.org/abstracts/11815/single-chip-controller-design-for-piezoelectric-actuators-with-mixed-signal-fpga" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/11815.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">520</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">118</span> A Multi Cordic Architecture on FPGA Platform </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ahmed%20Madian">Ahmed Madian</a>, <a href="https://publications.waset.org/abstracts/search?q=Muaz%20Aljarhi"> Muaz Aljarhi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Coordinate Rotation Digital Computer (CORDIC) is a unique digital computing unit intended for the computation of mathematical operations and functions. This paper presents a multi-CORDIC processor that integrates different CORDIC architectures on a single FPGA chip and allows the user to select the CORDIC architecture to proceed with based on what he wants to calculate and his/her needs. Synthesis show that radix 2 CORDIC has the lowest clock delay, radix 8 CORDIC has the highest LUT usage and lowest register usage while Hybrid Radix 4 CORDIC had the highest clock delay. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=multi" title="multi">multi</a>, <a href="https://publications.waset.org/abstracts/search?q=CORDIC" title=" CORDIC"> CORDIC</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=processor" title=" processor"> processor</a> </p> <a href="https://publications.waset.org/abstracts/2193/a-multi-cordic-architecture-on-fpga-platform" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/2193.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">470</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">117</span> Embedded Acoustic Signal Processing System Using OpenMP Architecture</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abdelkader%20Elhanaoui">Abdelkader Elhanaoui</a>, <a href="https://publications.waset.org/abstracts/search?q=Mhamed%20Hadji"> Mhamed Hadji</a>, <a href="https://publications.waset.org/abstracts/search?q=Rachid%20Skouri"> Rachid Skouri</a>, <a href="https://publications.waset.org/abstracts/search?q=Said%20Agounad"> Said Agounad</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, altera de1-SoC FPGA board technology is utilized as a distinguished tool for nondestructive characterization of an aluminum circular cylindrical shell of radius ratio b/a (a: outer radius; b: inner radius). The acoustic backscattered signal processing system has been developed using OpenMP architecture. The design is built in three blocks; it is implemented per functional block, in a heterogeneous Intel-Altera system running under Linux. The useful data to determine the performances of SoC FPGA is computed by the analytical method. The exploitation of SoC FPGA has lead to obtain the backscattering form function and resonance spectra. A0 and S0 modes of propagation in the tube are shown. The findings are then compared to those achieved from the Matlab simulation of analytical method. A good agreement has, therefore, been noted. Moreover, the detailed SoC FPGA-based system has shown that acoustic spectra are performed at up to 5 times faster than the Matlab implementation using almost the same data. This FPGA-based system implementation of processing algorithms is realized with a coefficient of correlation R and absolute error respectively about 0.962 and 5 10⁻⁵. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=OpenMP" title="OpenMP">OpenMP</a>, <a href="https://publications.waset.org/abstracts/search?q=signal%20processing%20system" title=" signal processing system"> signal processing system</a>, <a href="https://publications.waset.org/abstracts/search?q=acoustic%20backscattering" title=" acoustic backscattering"> acoustic backscattering</a>, <a href="https://publications.waset.org/abstracts/search?q=nondestructive%20characterization" title=" nondestructive characterization"> nondestructive characterization</a>, <a href="https://publications.waset.org/abstracts/search?q=thin%20tubes" title=" thin tubes"> thin tubes</a> </p> <a href="https://publications.waset.org/abstracts/162330/embedded-acoustic-signal-processing-system-using-openmp-architecture" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/162330.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">92</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">116</span> High Performance Field Programmable Gate Array-Based Stochastic Low-Density Parity-Check Decoder Design for IEEE 802.3an Standard </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ghania%20Zerari">Ghania Zerari</a>, <a href="https://publications.waset.org/abstracts/search?q=Abderrezak%20Guessoum"> Abderrezak Guessoum</a>, <a href="https://publications.waset.org/abstracts/search?q=Rachid%20Beguenane"> Rachid Beguenane</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper introduces high-performance architecture for fully parallel stochastic Low-Density Parity-Check (LDPC) field programmable gate array (FPGA) based LDPC decoder. The new approach is designed to decrease the decoding latency and to reduce the FPGA logic utilisation. To accomplish the target logic utilisation reduction, the routing of the proposed sub-variable node (VN) internal memory is designed to utilize one slice distributed RAM. Furthermore, a VN initialization, using the channel input probability, is achieved to enhance the decoder convergence, without extra resources and without integrating the output saturated-counters. The Xilinx FPGA implementation, of IEEE 802.3an standard LDPC code, shows that the proposed decoding approach attain high performance along with reduction of FPGA logic utilisation. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=low-density%20parity-check%20%28LDPC%29%20decoder" title="low-density parity-check (LDPC) decoder">low-density parity-check (LDPC) decoder</a>, <a href="https://publications.waset.org/abstracts/search?q=stochastic%20decoding" title=" stochastic decoding"> stochastic decoding</a>, <a href="https://publications.waset.org/abstracts/search?q=field%20programmable%20gate%20array%20%28FPGA%29" title=" field programmable gate array (FPGA)"> field programmable gate array (FPGA)</a>, <a href="https://publications.waset.org/abstracts/search?q=IEEE%20802.3an%20standard" title=" IEEE 802.3an standard"> IEEE 802.3an standard</a> </p> <a href="https://publications.waset.org/abstracts/81538/high-performance-field-programmable-gate-array-based-stochastic-low-density-parity-check-decoder-design-for-ieee-8023an-standard" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/81538.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">297</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">115</span> Crater Detection Using PCA from Captured CMOS Camera Data</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Tatsuya%20Takino">Tatsuya Takino</a>, <a href="https://publications.waset.org/abstracts/search?q=Izuru%20Nomura"> Izuru Nomura</a>, <a href="https://publications.waset.org/abstracts/search?q=Yuji%20Kageyama"> Yuji Kageyama</a>, <a href="https://publications.waset.org/abstracts/search?q=Shin%20Nagata"> Shin Nagata</a>, <a href="https://publications.waset.org/abstracts/search?q=Hiroyuki%20Kamata"> Hiroyuki Kamata</a> </p> <p class="card-text"><strong>Abstract:</strong></p> We propose a method of detecting the craters from the image of the lunar surface. This proposal assumes that it is applied to SLIM (Smart Lander for Investigating Moon) working group aiming at the pinpoint landing on the lunar surface and investigating scientific research. It is difficult to equip and use high-performance computers for the small space probe. So, it is necessary to use a small computer with an exclusive hardware such as FPGA. We have studied the crater detection using principal component analysis (PCA), In this paper, We implement detection algorithm into the FPGA, and the detection is performed on the data that was captured from the CMOS camera. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=crater%20detection" title="crater detection">crater detection</a>, <a href="https://publications.waset.org/abstracts/search?q=PCA" title=" PCA"> PCA</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=image%20processing" title=" image processing"> image processing</a> </p> <a href="https://publications.waset.org/abstracts/19003/crater-detection-using-pca-from-captured-cmos-camera-data" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/19003.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">550</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">114</span> PIN-Diode Based Slotted Reconfigurable Multiband Antenna Array for Vehicular Communication </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Gaurav%20Upadhyay">Gaurav Upadhyay</a>, <a href="https://publications.waset.org/abstracts/search?q=Nand%20Kishore"> Nand Kishore</a>, <a href="https://publications.waset.org/abstracts/search?q=Prashant%20Ranjan"> Prashant Ranjan</a>, <a href="https://publications.waset.org/abstracts/search?q=Shivesh%20Tripathi"> Shivesh Tripathi</a>, <a href="https://publications.waset.org/abstracts/search?q=V.%20S.%20Tripathi"> V. S. Tripathi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, a patch antenna array design is proposed for vehicular communication. The antenna consists of 2-element patch array. The antenna array is operating at multiple frequency bands. The multiband operation is achieved by use of slots at proper locations at the patch. The array is made reconfigurable by use of two PIN-diodes. The antenna is simulated and measured in four states of diodes i.e. ON-ON, ON-OFF, OFF-ON, and OFF-OFF. In ON-ON state of diodes, the resonant frequencies are 4.62-4.96, 6.50-6.75, 6.90-7.01, 7.34-8.22, 8.89-9.09 GHz. In ON-OFF state of diodes, the measured resonant frequencies are 4.63-4.93, 6.50-6.70 and 7.81-7.91 GHz. In OFF-ON states of diodes the resonant frequencies are 1.24-1.46, 3.40-3.75, 5.07-5.25 and 6.90-7.20 GHz and in the OFF-OFF state of diodes 4.49-4.75 and 5.61-5.98 GHz. The maximum bandwidth of the proposed antenna is 16.29%. The peak gain of the antenna is 3.4 dB at 5.9 GHz, which makes it suitable for vehicular communication. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=antenna" title="antenna">antenna</a>, <a href="https://publications.waset.org/abstracts/search?q=array" title=" array"> array</a>, <a href="https://publications.waset.org/abstracts/search?q=reconfigurable" title=" reconfigurable"> reconfigurable</a>, <a href="https://publications.waset.org/abstracts/search?q=vehicular" title=" vehicular"> vehicular</a> </p> <a href="https://publications.waset.org/abstracts/85090/pin-diode-based-slotted-reconfigurable-multiband-antenna-array-for-vehicular-communication" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/85090.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">256</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">113</span> Field-Programmable Gate Arrays Based High-Efficiency Oriented Fast and Rotated Binary Robust Independent Elementary Feature Extraction Method Using Feature Zone Strategy</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Huang%20Bai-Cheng">Huang Bai-Cheng</a> </p> <p class="card-text"><strong>Abstract:</strong></p> When deploying the Oriented Fast and Rotated Binary Robust Independent Elementary Feature (BRIEF) (ORB) extraction algorithm on field-programmable gate arrays (FPGA), the access of global storage for 31×31 pixel patches of the features has become the bottleneck of the system efficiency. Therefore, a feature zone strategy has been proposed. Zones are searched as features are detected. Pixels around the feature zones are extracted from global memory and distributed into patches corresponding to feature coordinates. The proposed FPGA structure is targeted on a Xilinx FPGA development board of Zynq UltraScale+ series, and multiple datasets are tested. Compared with the streaming pixel patch extraction method, the proposed architecture obtains at least two times acceleration consuming extra 3.82% Flip-Flops (FFs) and 7.78% Look-Up Tables (LUTs). Compared with the non-streaming one, the proposed architecture saves 22.3% LUT and 1.82% FF, causing a latency of only 0.2ms and a drop in frame rate for 1. Compared with the related works, the proposed strategy and hardware architecture have the superiority of keeping a balance between FPGA resources and performance. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=feature%20extraction" title="feature extraction">feature extraction</a>, <a href="https://publications.waset.org/abstracts/search?q=real-time" title=" real-time"> real-time</a>, <a href="https://publications.waset.org/abstracts/search?q=ORB" title=" ORB"> ORB</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA%20implementation" title=" FPGA implementation"> FPGA implementation</a> </p> <a href="https://publications.waset.org/abstracts/158130/field-programmable-gate-arrays-based-high-efficiency-oriented-fast-and-rotated-binary-robust-independent-elementary-feature-extraction-method-using-feature-zone-strategy" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/158130.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">122</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">112</span> Embedded System of Signal Processing on FPGA: Underwater Application Architecture</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abdelkader%20Elhanaoui">Abdelkader Elhanaoui</a>, <a href="https://publications.waset.org/abstracts/search?q=Mhamed%20Hadji"> Mhamed Hadji</a>, <a href="https://publications.waset.org/abstracts/search?q=Rachid%20Skouri"> Rachid Skouri</a>, <a href="https://publications.waset.org/abstracts/search?q=Said%20Agounad"> Said Agounad</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The purpose of this paper is to study the phenomenon of acoustic scattering by using a new method. The signal processing (Fast Fourier Transform FFT Inverse Fast Fourier Transform iFFT and BESSEL functions) is widely applied to obtain information with high precision accuracy. Signal processing has a wider implementation in general-purpose pro-cessors. Our interest was focused on the use of FPGAs (Field-Programmable Gate Ar-rays) in order to minimize the computational complexity in single processor architecture, then be accelerated on FPGA and meet real-time and energy efficiency requirements. Gen-eral-purpose processors are not efficient for signal processing. We implemented the acous-tic backscattered signal processing model on the Altera DE-SOC board and compared it to Odroid xu4. By comparison, the computing latency of Odroid xu4 and FPGA is 60 sec-onds and 3 seconds, respectively. The detailed SoC FPGA-based system has shown that acoustic spectra are performed up to 20 times faster than the Odroid xu4 implementation. FPGA-based system of processing algorithms is realized with an absolute error of about 10⁻³. This study underlines the increasing importance of embedded systems in underwater acoustics, especially in non-destructive testing. It is possible to obtain information related to the detection and characterization of submerged cells. So we have achieved good exper-imental results in real-time and energy efficiency. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=DE1%20FPGA" title="DE1 FPGA">DE1 FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=acoustic%20scattering" title=" acoustic scattering"> acoustic scattering</a>, <a href="https://publications.waset.org/abstracts/search?q=form%20function" title=" form function"> form function</a>, <a href="https://publications.waset.org/abstracts/search?q=signal%20processing" title=" signal processing"> signal processing</a>, <a href="https://publications.waset.org/abstracts/search?q=non-destructive%20testing" title=" non-destructive testing"> non-destructive testing</a> </p> <a href="https://publications.waset.org/abstracts/162313/embedded-system-of-signal-processing-on-fpga-underwater-application-architecture" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/162313.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">79</span> </span> </div> </div> <ul class="pagination"> <li class="page-item disabled"><span class="page-link">&lsaquo;</span></li> <li class="page-item active"><span class="page-link">1</span></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=reconfigurable%20FPGA&page=2">2</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=reconfigurable%20FPGA&page=3">3</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=reconfigurable%20FPGA&page=4">4</a></li> <li class="page-item"><a class="page-link" href="https://publications.waset.org/abstracts/search?q=reconfigurable%20FPGA&page=5">5</a></li> <li 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