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Celeron - Wikipedia

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data-event-name="pinnable-header.vector-toc.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-toc.unpin">hide</button> </div> <ul class="vector-toc-contents" id="mw-panel-toc-list"> <li id="toc-mw-content-text" class="vector-toc-list-item vector-toc-level-1"> <a href="#" class="vector-toc-link"> <div class="vector-toc-text">(Top)</div> </a> </li> <li id="toc-Background" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Background"> <div class="vector-toc-text"> <span class="vector-toc-numb">1</span> <span>Background</span> </div> </a> <ul id="toc-Background-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Desktop_Celerons" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Desktop_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Desktop Celerons</span> </div> </a> <button aria-controls="toc-Desktop_Celerons-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Desktop Celerons subsection</span> </button> <ul id="toc-Desktop_Celerons-sublist" class="vector-toc-list"> <li id="toc-P6-based_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#P6-based_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>P6-based Celerons</span> </div> </a> <ul id="toc-P6-based_Celerons-sublist" class="vector-toc-list"> <li id="toc-Covington" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Covington"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.1</span> <span>Covington</span> </div> </a> <ul id="toc-Covington-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Mendocino" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Mendocino"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.2</span> <span>Mendocino</span> </div> </a> <ul id="toc-Mendocino-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Coppermine-128" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Coppermine-128"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.3</span> <span>Coppermine-128</span> </div> </a> <ul id="toc-Coppermine-128-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Tualatin-256" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Tualatin-256"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.4</span> <span>Tualatin-256</span> </div> </a> <ul id="toc-Tualatin-256-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-NetBurst-based_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#NetBurst-based_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>NetBurst-based Celerons</span> </div> </a> <ul id="toc-NetBurst-based_Celerons-sublist" class="vector-toc-list"> <li id="toc-Willamette-128" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Willamette-128"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.1</span> <span>Willamette-128</span> </div> </a> <ul id="toc-Willamette-128-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Northwood-128" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Northwood-128"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.2</span> <span>Northwood-128</span> </div> </a> <ul id="toc-Northwood-128-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Prescott-256" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Prescott-256"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.3</span> <span>Prescott-256</span> </div> </a> <ul id="toc-Prescott-256-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Cedar_Mill-512" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Cedar_Mill-512"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.4</span> <span>Cedar Mill-512</span> </div> </a> <ul id="toc-Cedar_Mill-512-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core-based_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core-based_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Core-based Celerons</span> </div> </a> <ul id="toc-Core-based_Celerons-sublist" class="vector-toc-list"> <li id="toc-Conroe-L" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Conroe-L"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.1</span> <span>Conroe-L</span> </div> </a> <ul id="toc-Conroe-L-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Allendale" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Allendale"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.2</span> <span>Allendale</span> </div> </a> <ul id="toc-Allendale-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Wolfdale-3M" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Wolfdale-3M"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.3</span> <span>Wolfdale-3M</span> </div> </a> <ul id="toc-Wolfdale-3M-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Nehalem-based_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Nehalem-based_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>Nehalem-based Celerons</span> </div> </a> <ul id="toc-Nehalem-based_Celerons-sublist" class="vector-toc-list"> <li id="toc-Clarkdale" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Clarkdale"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.1</span> <span>Clarkdale</span> </div> </a> <ul id="toc-Clarkdale-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Jasper_Forest" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Jasper_Forest"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.2</span> <span>Jasper Forest</span> </div> </a> <ul id="toc-Jasper_Forest-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Sandy_Bridge-based_desktop_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Sandy_Bridge-based_desktop_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.5</span> <span>Sandy Bridge-based desktop Celerons</span> </div> </a> <ul id="toc-Sandy_Bridge-based_desktop_Celerons-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Ivy_Bridge-based_desktop_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Ivy_Bridge-based_desktop_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.6</span> <span>Ivy Bridge-based desktop Celerons</span> </div> </a> <ul id="toc-Ivy_Bridge-based_desktop_Celerons-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Haswell-based_desktop_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Haswell-based_desktop_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.7</span> <span>Haswell-based desktop Celerons</span> </div> </a> <ul id="toc-Haswell-based_desktop_Celerons-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Skylake-based_desktop_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Skylake-based_desktop_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.8</span> <span>Skylake-based desktop Celerons</span> </div> </a> <ul id="toc-Skylake-based_desktop_Celerons-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Kaby_Lake-based_desktop_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Kaby_Lake-based_desktop_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.9</span> <span>Kaby Lake-based desktop Celerons</span> </div> </a> <ul id="toc-Kaby_Lake-based_desktop_Celerons-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Coffee_Lake-based_desktop_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Coffee_Lake-based_desktop_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.10</span> <span>Coffee Lake-based desktop Celerons</span> </div> </a> <ul id="toc-Coffee_Lake-based_desktop_Celerons-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Comet_Lake-based_desktop_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Comet_Lake-based_desktop_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.11</span> <span>Comet Lake-based desktop Celerons</span> </div> </a> <ul id="toc-Comet_Lake-based_desktop_Celerons-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alder_Lake-based_desktop_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Alder_Lake-based_desktop_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.12</span> <span>Alder Lake-based desktop Celerons</span> </div> </a> <ul id="toc-Alder_Lake-based_desktop_Celerons-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Mobile_Celerons" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Mobile_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Mobile Celerons</span> </div> </a> <button aria-controls="toc-Mobile_Celerons-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Mobile Celerons subsection</span> </button> <ul id="toc-Mobile_Celerons-sublist" class="vector-toc-list"> <li id="toc-P6-based_mobile_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#P6-based_mobile_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>P6-based mobile Celerons</span> </div> </a> <ul id="toc-P6-based_mobile_Celerons-sublist" class="vector-toc-list"> <li id="toc-Mendocino_(mobile)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Mendocino_(mobile)"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1.1</span> <span>Mendocino (mobile)</span> </div> </a> <ul id="toc-Mendocino_(mobile)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Tualatin-256_(mobile)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Tualatin-256_(mobile)"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1.2</span> <span>Tualatin-256 (mobile)</span> </div> </a> <ul id="toc-Tualatin-256_(mobile)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-NetBurst-based_mobile_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#NetBurst-based_mobile_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>NetBurst-based mobile Celerons</span> </div> </a> <ul id="toc-NetBurst-based_mobile_Celerons-sublist" class="vector-toc-list"> <li id="toc-Northwood-256" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Northwood-256"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2.1</span> <span>Northwood-256</span> </div> </a> <ul id="toc-Northwood-256-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Pentium_M-based_mobile_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Pentium_M-based_mobile_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Pentium M-based mobile Celerons</span> </div> </a> <ul id="toc-Pentium_M-based_mobile_Celerons-sublist" class="vector-toc-list"> <li id="toc-Banias-512" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Banias-512"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3.1</span> <span>Banias-512</span> </div> </a> <ul id="toc-Banias-512-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Shelton" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Shelton"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3.2</span> <span>Shelton</span> </div> </a> <ul id="toc-Shelton-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Dothan-1024" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Dothan-1024"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3.3</span> <span>Dothan-1024</span> </div> </a> <ul id="toc-Dothan-1024-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Yonah" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Yonah"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3.4</span> <span>Yonah</span> </div> </a> <ul id="toc-Yonah-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core-based_mobile_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core-based_mobile_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4</span> <span>Core-based mobile Celerons</span> </div> </a> <ul id="toc-Core-based_mobile_Celerons-sublist" class="vector-toc-list"> <li id="toc-Merom-L" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Merom-L"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4.1</span> <span>Merom-L</span> </div> </a> <ul id="toc-Merom-L-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Merom-2M" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Merom-2M"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4.2</span> <span>Merom-2M</span> </div> </a> <ul id="toc-Merom-2M-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Penryn-3M" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Penryn-3M"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4.3</span> <span>Penryn-3M</span> </div> </a> <ul id="toc-Penryn-3M-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Nehalem-based_mobile_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Nehalem-based_mobile_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.5</span> <span>Nehalem-based mobile Celerons</span> </div> </a> <ul id="toc-Nehalem-based_mobile_Celerons-sublist" class="vector-toc-list"> <li id="toc-Arrandale" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Arrandale"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.5.1</span> <span>Arrandale</span> </div> </a> <ul id="toc-Arrandale-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Sandy_Bridge-based_mobile_Celerons" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Sandy_Bridge-based_mobile_Celerons"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.6</span> <span>Sandy Bridge-based mobile Celerons</span> </div> </a> <ul id="toc-Sandy_Bridge-based_mobile_Celerons-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Dual-processor_support" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Dual-processor_support"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Dual-processor support</span> </div> </a> <ul id="toc-Dual-processor_support-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">Celeron</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 36 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-36" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">36 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%B3%D9%8A%D9%84%D9%8A%D8%B1%D9%88%D9%86" title="سيليرون – Arabic" lang="ar" hreflang="ar" data-title="سيليرون" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-bn mw-list-item"><a href="https://bn.wikipedia.org/wiki/%E0%A6%B8%E0%A7%87%E0%A6%B2%E0%A7%87%E0%A6%B0%E0%A6%A8" title="সেলেরন – Bangla" lang="bn" hreflang="bn" data-title="সেলেরন" data-language-autonym="বাংলা" data-language-local-name="Bangla" class="interlanguage-link-target"><span>বাংলা</span></a></li><li class="interlanguage-link interwiki-bs mw-list-item"><a href="https://bs.wikipedia.org/wiki/Celeron" title="Celeron – Bosnian" lang="bs" hreflang="bs" data-title="Celeron" data-language-autonym="Bosanski" data-language-local-name="Bosnian" class="interlanguage-link-target"><span>Bosanski</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Celeron" title="Celeron – Catalan" lang="ca" hreflang="ca" data-title="Celeron" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/Celeron" title="Celeron – Czech" lang="cs" hreflang="cs" data-title="Celeron" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Intel_Celeron" title="Intel Celeron – German" lang="de" hreflang="de" data-title="Intel Celeron" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/Celeron" title="Celeron – Estonian" lang="et" hreflang="et" data-title="Celeron" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-el mw-list-item"><a href="https://el.wikipedia.org/wiki/Celeron" title="Celeron – Greek" lang="el" hreflang="el" data-title="Celeron" data-language-autonym="Ελληνικά" data-language-local-name="Greek" class="interlanguage-link-target"><span>Ελληνικά</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Intel_Celeron" title="Intel Celeron – Spanish" lang="es" hreflang="es" data-title="Intel Celeron" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eo mw-list-item"><a href="https://eo.wikipedia.org/wiki/Celeron" title="Celeron – Esperanto" lang="eo" hreflang="eo" data-title="Celeron" data-language-autonym="Esperanto" data-language-local-name="Esperanto" class="interlanguage-link-target"><span>Esperanto</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%B3%D9%84%D8%B1%D9%88%D9%86" title="سلرون – Persian" lang="fa" hreflang="fa" data-title="سلرون" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Celeron" title="Celeron – French" lang="fr" hreflang="fr" data-title="Celeron" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%85%80%EB%9F%AC%EB%A1%A0" title="셀러론 – Korean" lang="ko" hreflang="ko" data-title="셀러론" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Celeron" title="Celeron – Indonesian" lang="id" hreflang="id" data-title="Celeron" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Celeron" title="Celeron – Italian" lang="it" hreflang="it" data-title="Celeron" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/Celeron" title="Celeron – Hungarian" lang="hu" hreflang="hu" data-title="Celeron" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-ms mw-list-item"><a href="https://ms.wikipedia.org/wiki/Celeron" title="Celeron – Malay" lang="ms" hreflang="ms" data-title="Celeron" data-language-autonym="Bahasa Melayu" data-language-local-name="Malay" class="interlanguage-link-target"><span>Bahasa Melayu</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Celeron" title="Celeron – Dutch" lang="nl" hreflang="nl" data-title="Celeron" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/Intel_Celeron" title="Intel Celeron – Japanese" lang="ja" hreflang="ja" data-title="Intel Celeron" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/Celeron" title="Celeron – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="Celeron" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-oc mw-list-item"><a href="https://oc.wikipedia.org/wiki/Intel_Celeron" title="Intel Celeron – Occitan" lang="oc" hreflang="oc" data-title="Intel Celeron" data-language-autonym="Occitan" data-language-local-name="Occitan" class="interlanguage-link-target"><span>Occitan</span></a></li><li class="interlanguage-link interwiki-uz mw-list-item"><a href="https://uz.wikipedia.org/wiki/Intel_Celeron" title="Intel Celeron – Uzbek" lang="uz" hreflang="uz" data-title="Intel Celeron" data-language-autonym="Oʻzbekcha / ўзбекча" data-language-local-name="Uzbek" class="interlanguage-link-target"><span>Oʻzbekcha / ўзбекча</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Intel_Celeron" title="Intel Celeron – Polish" lang="pl" hreflang="pl" data-title="Intel Celeron" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Celeron" title="Celeron – Portuguese" lang="pt" hreflang="pt" data-title="Celeron" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Celeron" title="Celeron – Romanian" lang="ro" hreflang="ro" data-title="Celeron" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/Celeron" title="Celeron – Russian" lang="ru" hreflang="ru" data-title="Celeron" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/Celeron" title="Celeron – Simple English" lang="en-simple" hreflang="en-simple" data-title="Celeron" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target"><span>Simple English</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/Celeron" title="Celeron – Slovak" lang="sk" hreflang="sk" data-title="Celeron" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/Intel_Celeron" title="Intel Celeron – Serbian" lang="sr" hreflang="sr" data-title="Intel Celeron" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/Intel_Celeron" title="Intel Celeron – Finnish" lang="fi" hreflang="fi" data-title="Intel Celeron" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/Celeron" title="Celeron – Swedish" lang="sv" hreflang="sv" data-title="Celeron" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/%E0%B9%80%E0%B8%8B%E0%B9%80%E0%B8%A5%E0%B8%A3%E0%B8%AD%E0%B8%99" title="เซเลรอน – Thai" lang="th" hreflang="th" data-title="เซเลรอน" data-language-autonym="ไทย" data-language-local-name="Thai" class="interlanguage-link-target"><span>ไทย</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/Celeron" title="Celeron – Turkish" lang="tr" hreflang="tr" data-title="Celeron" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/Celeron" title="Celeron – Ukrainian" lang="uk" hreflang="uk" data-title="Celeron" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/Celeron" title="Celeron – Vietnamese" lang="vi" hreflang="vi" data-title="Celeron" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a 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<div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Line of discontinued microprocessors made by Intel</div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 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.ambox{display:none!important}}</style><table class="box-Update plainlinks metadata ambox ambox-content ambox-Update" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/42px-Ambox_current_red_Americas.svg.png" decoding="async" width="42" height="34" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/63px-Ambox_current_red_Americas.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/84px-Ambox_current_red_Americas.svg.png 2x" data-file-width="360" data-file-height="290" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">This article needs to be <b>updated</b>.<span class="hide-when-compact"> Please help update this article to reflect recent events or newly available information.</span> <span class="date-container"><i>(<span class="date">September 2023</span>)</i></span></div></td></tr></tbody></table> <p class="mw-empty-elt"> </p> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">Celeron</caption><tbody><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:Intel_Celeron_2020_logo.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/23/Intel_Celeron_2020_logo.svg/220px-Intel_Celeron_2020_logo.svg.png" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/23/Intel_Celeron_2020_logo.svg/330px-Intel_Celeron_2020_logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/23/Intel_Celeron_2020_logo.svg/440px-Intel_Celeron_2020_logo.svg.png 2x" data-file-width="992" data-file-height="992" /></a></span><div class="infobox-caption">Latest logo used from 2020 to 2023</div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">April&#160;15, 1998<span class="noprint">&#59;&#32;26 years ago</span><span style="display:none">&#160;(<span class="bday dtstart published updated">1998-04-15</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">2023<span class="noprint">&#59;&#32;1&#160;year ago</span><span style="display:none">&#160;(<span class="dtend">2023</span>)</span><sup id="cite_ref-Warren_2022_1-0" class="reference"><a href="#cite_note-Warren_2022-1"><span class="cite-bracket">&#91;</span>1<span class="cite-bracket">&#93;</span></a></sup></td></tr><tr><th scope="row" class="infobox-label">Marketed by</th><td class="infobox-data"><a href="/wiki/Intel" title="Intel">Intel</a></td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data"><a href="/wiki/Intel" title="Intel">Intel</a></td></tr><tr><th scope="row" class="infobox-label">Common manufacturer</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li><a href="/wiki/Intel" title="Intel">Intel</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">266&#160;MHz to 3.6&#160;GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">66&#160;MHz to 1333&#160;MT/s</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> speeds</th><td class="infobox-data">2.0&#160;GT/s to 16&#160;GT/s</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology&#160;node</a></th><td class="infobox-data"><a href="/wiki/250_nm_process" title="250 nm process">250 nm</a> to <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a> (10ESF)</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a></li><li><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></li><li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a></li><li><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a></li><li><a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li><li><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a></li><li><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li><li><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a></li><li><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li><li><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a></li><li><a href="/wiki/Willow_Cove" title="Willow Cove">Willow Cove</a></li><li><a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction&#160;set</a></th><td class="infobox-data"><a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th scope="row" class="infobox-label">Instructions</th><td class="infobox-data"><a href="/wiki/X86" title="X86">x86</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>1–5</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Sockets</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><b>Desktop</b> <div><ul><li><a href="/wiki/Slot_1" title="Slot 1">Slot 1</a></li><li><a href="/wiki/Socket_370" title="Socket 370">Socket 370</a></li><li><a href="/wiki/Socket_478" title="Socket 478">Socket 478</a></li><li><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a></li><li><a href="/wiki/Socket_M" title="Socket M">Socket M</a></li><li><a href="/wiki/Socket_P" title="Socket P">Socket P</a></li><li><a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a></li><li><a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a></li><li><a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a></li><li><a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151</a></li><li><a href="/wiki/LGA_1200" title="LGA 1200">LGA 1200</a></li><li><a href="/wiki/LGA_1700" title="LGA 1700">LGA 1700</a></li></ul></div></li><li><b>Mobile</b> <div><ul><li><a href="/wiki/Socket_495" title="Socket 495">Socket 495</a></li><li><a href="/wiki/Socket_479" title="Socket 479">Socket 479</a></li><li><a href="/wiki/Socket_M" title="Socket M">Socket M</a></li><li><a href="/wiki/Socket_P" title="Socket P">Socket P</a></li></ul></div></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Core&#160;names</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>Covington</li><li>Mendocino</li><li>Coppermine-128</li><li>Tualatin-256</li><li>Willamette-128</li><li>Northwood-128</li><li>Prescott-256</li><li>Cedar Mill-512</li><li>Banias</li><li>Dothan</li><li>Yonah</li><li>Merom</li><li>Conroe</li><li>Allendale</li><li>Penryn</li><li>Wolfdale</li><li>Clarkdale</li><li>Arrandale</li><li>Jasper Forest</li><li>Sandy Bridge</li><li>Ivy Bridge</li><li>Haswell</li><li>Broadwell</li><li>Skylake</li><li>Kaby Lake</li><li>Coffee Lake</li><li>Comet Lake</li><li>Rocket Lake</li><li>Tiger Lake</li><li>Alder Lake</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Variant</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a>, <a href="/wiki/Pentium" title="Pentium">Pentium</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">History</th></tr><tr><th scope="row" class="infobox-label">Predecessors</th><td class="infobox-data"><a href="/wiki/I486" title="I486">i486</a>, <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a></td></tr><tr><th scope="row" class="infobox-label">Successor</th><td class="infobox-data">Intel Processor</td></tr></tbody></table> <p><b>Celeron</b> is a series of <a href="/wiki/IA-32" title="IA-32">IA-32</a> and <a href="/wiki/X86-64" title="X86-64">x86-64</a> computer <a href="/wiki/Microprocessor" title="Microprocessor">microprocessors</a> targeted at low-cost <a href="/wiki/Personal_computer" title="Personal computer">personal computers</a>, manufactured by <a href="/wiki/Intel" title="Intel">Intel</a> from 1998 until 2023. </p><p>The first Celeron-branded CPU was introduced on April 15, 1998, and was based on the <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a>. Celeron-branded processors released from 2009 to 2023 are compatible with <a href="/wiki/IA-32" title="IA-32">IA-32</a> software. They typically offer less performance per clock speed compared to flagship Intel CPU lines, such as the <a href="/wiki/Pentium" title="Pentium">Pentium</a> or <a href="/wiki/Intel_Core" title="Intel Core">Core</a> brands. They often have less <a href="/wiki/CPU_cache" title="CPU cache">cache</a> or intentionally disabled advanced features, with variable impact on performance. While some Celeron designs have achieved strong performance for their segment, the majority of the Celeron line has exhibited noticeably degraded performance.<sup id="cite_ref-Schmid_2-0" class="reference"><a href="#cite_note-Schmid-2"><span class="cite-bracket">&#91;</span>2<span class="cite-bracket">&#93;</span></a></sup> This has been the primary <a href="/wiki/Market_segmentation" title="Market segmentation">justification for the higher cost</a> of other Intel CPU brands versus the Celeron range.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">&#91;<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2024)">citation needed</span></a></i>&#93;</sup> </p><p>In September 2022, Intel announced that the Celeron brand, along with Pentium, were to be replaced with the new "Intel Processor" branding for low-end processors in laptops from 2023 onwards.<sup id="cite_ref-Warren_2022_1-1" class="reference"><a href="#cite_note-Warren_2022-1"><span class="cite-bracket">&#91;</span>1<span class="cite-bracket">&#93;</span></a></sup> This applied to desktops using Celeron processors as well, and was discontinued around the same time laptops stopped using Celeron processors in favor of "Intel Processor" processors in 2023. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Background">Background</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=1" title="Edit section: Background"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>As a product concept, the Celeron was introduced in response to Intel's loss of the low-end market, in particular to the <a href="/wiki/Cyrix" title="Cyrix">Cyrix</a> <a href="/wiki/6x86" class="mw-redirect" title="6x86">6x86</a>, the <a href="/wiki/AMD_K6" title="AMD K6">AMD K6</a>, and the IDT <a href="/wiki/Winchip" class="mw-redirect" title="Winchip">Winchip</a>. Intel's existing low-end product, the <a href="/wiki/Pentium_MMX" class="mw-redirect" title="Pentium MMX">Pentium MMX</a>, was no longer performance-competitive at 233&#160;MHz.<sup id="cite_ref-S7toS1_3-0" class="reference"><a href="#cite_note-S7toS1-3"><span class="cite-bracket">&#91;</span>3<span class="cite-bracket">&#93;</span></a></sup> Although a faster Pentium MMX would have been a lower-risk strategy, the industry-standard <a href="/wiki/Socket_7" title="Socket 7">Socket 7</a> platform hosted a market of competitor CPUs that could be drop-in replacements for the Pentium MMX. Instead, Intel pursued a budget part that was to be pin-compatible with their high-end <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a> product, using the Pentium II's proprietary <a href="/wiki/Slot_1" title="Slot 1">Slot 1</a> interface. </p><p>The Celeron also effectively killed off the nine-year-old <a href="/wiki/80486" class="mw-redirect" title="80486">80486</a> chip, which had been the low-end processor brand for entry-level desktops and laptops until 1998. </p><p>Intel hired marketing firm <a href="/wiki/Lexicon_Branding" title="Lexicon Branding">Lexicon Branding</a>, which had originally come up with the name "Pentium", to devise a name for the new product as well. The <i><a href="/wiki/San_Jose_Mercury_News" class="mw-redirect" title="San Jose Mercury News">San Jose Mercury News</a></i> described Lexicon's reasoning behind the name they chose: "<i><a href="https://en.wiktionary.org/wiki/celer#Latin" class="extiw" title="wikt:celer">Celer</a></i> is <a href="/wiki/Latin" title="Latin">Latin</a> for swift, as in the word 'accelerate', and 'on' as in 'turned on'. Celeron is seven letters and three syllables, like Pentium. The 'Cel' of Celeron rhymes with 'tel' of Intel."<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">&#91;</span>4<span class="cite-bracket">&#93;</span></a></sup> </p> <table class="wikitable" align="center"> <caption>Intel Celeron processor family </caption> <tbody><tr> <th rowspan="2">Based on </th> <th colspan="3"><a href="/wiki/Desktop_computer" title="Desktop computer">Desktop</a> </th> <th colspan="3"><a href="/wiki/Laptop" title="Laptop">Laptop</a> </th> <th colspan="3"><a href="/wiki/Embedded_system#Processors_in_embedded_systems" title="Embedded system">Embedded</a> </th></tr> <tr> <th>Code-named </th> <th>Core </th> <th>Date released </th> <th>Code-named </th> <th>Core </th> <th>Date released </th> <th>Code-named </th> <th>Core </th> <th>Date released </th></tr> <tr> <td>P6 </td> <td>Covington<br />Mendocino<br />Coppermine-128<br />Tualatin-256 </td> <td>(250&#160;nm)<br />(250&#160;nm)<br />(180&#160;nm)<br />(130&#160;nm) </td> <td>1998<br />1998–2000<br />2000–2001<br />2002 </td> <td>Mendocino<br />Coppermine-128 <p>Coppermine&#160;T<br />Tualatin-256 </p> </td> <td>(250&#160;nm)<br />(180&#160;nm) <p>(180&#160;nm)<br />(130&#160;nm) </p> </td> <td>1999<br />2000–2001 <p>2001<br />2002–2003 </p> </td> <th colspan="3" rowspan="9"> </th></tr> <tr> <td>NetBurst </td> <td>Willamette-128<br />Northwood-128 </td> <td>(180&#160;nm)<br />(130&#160;nm) </td> <td>2002<br />2002–2003 </td> <td>Northwood-256<br /> </td> <td>(130&#160;nm)<br /> </td> <td>2002–2003<br /> </td></tr> <tr> <td>Pentium M (Celeron M) </td> <th colspan="3"> </th> <td>Banias-512<br />Dothan-512 <p>Dothan-1024 </p><p>Yonah-512 </p><p>Yonah-1024<br />Sossaman </p> </td> <td>(130&#160;nm) <p>(90&#160;nm) </p><p>(90&#160;nm) </p><p>(65&#160;nm)<br />(65&#160;nm)<br />(65&#160;nm) </p> </td> <td>2004 <p>2004–2007 </p><p>2004–2005 </p><p>2007 </p><p>2006 </p><p>2006–2007 </p> </td></tr> <tr> <td>NetBurst (Celeron D) </td> <td>Prescott-256<br />Cedar Mill-512 </td> <td>(90&#160;nm)<br />(65&#160;nm) </td> <td>2004–2005<br />2006–2007 </td> <th colspan="3" rowspan="3"> </th></tr> <tr> <td>Core (Single) </td> <td>Conroe-L <p>Conroe-CL </p> </td> <td>(65&#160;nm) <p>(65&#160;nm) </p> </td> <td>2007-2008 <p>??? </p> </td></tr> <tr> <td>Core (Dual) </td> <td>Allendale<br />Wolfdale-3M </td> <td>(65&#160;nm)<br />(45&#160;nm) </td> <td>2008–2009 <p>2009–2010 </p> </td></tr> <tr> <td>Core (Celeron M/Celeron) </td> <th colspan="3" rowspan="2"> </th> <td>Merom, Merom-L <p>Merom-2M </p><p>Merom-L (Ultra-Low-Voltage) </p> </td> <td>(65&#160;nm)<br />(65&#160;nm) <p>(65&#160;nm) </p> </td> <td>2007–2008 <p>2008 </p><p>2007, 2009 </p> </td></tr> <tr> <td>Core (Celeron Dual) </td> <td>Merom-2M <p>Penryn-3M </p> </td> <td>(65&#160;nm) <p>(45&#160;nm) </p> </td> <td>2008 <p>2009–2010 </p> </td></tr> <tr> <td rowspan="2">Nehalem/Westmere </td> <td>Clarkdale </td> <td>(32&#160;nm) </td> <td>2010 </td> <td>Arrandale </td> <td>(32&#160;nm) </td> <td>2010–2011 </td></tr> <tr> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td>Jasper Forest </td> <td>Single (45&#160;nm) </td> <td> </td></tr> <tr> <td>Silvermont <p>Airmont Goldmont Goldmont Plus Tremont </p> </td> <td>Bay Trail- <p>Braswell </p><p>Apollo Lake </p><p>Gemini Lake </p><p>Jasper Lake </p> </td> <td>dual &amp; quad (22&#160;nm) <p>dual &amp; quad (14&#160;nm) </p><p>up to quad (14&#160;nm) </p><p>up to quad (14&#160;nm) </p><p>up to quad (10&#160;nm) </p> </td> <td> </td> <td>Bay Trail-M <p>Braswell </p><p>Apollo Lake </p><p>Gemini Lake </p><p>Jasper Lake </p> </td> <td>dual &amp; quad (22&#160;nm) <p>dual &amp; quad (14&#160;nm) </p><p>up to quad (14&#160;nm) </p><p>up to quad (14&#160;nm) </p><p>up to quad (10&#160;nm) </p> </td> <td>October 2013 <p>March 2015 </p><p>April 2016 </p><p>December 2017 </p><p>January 2021 </p> </td> <td>Bay Trail-M <p>Braswell </p><p>Apollo Lake </p><p>Gemini Lake </p><p>Jasper Lake </p> </td> <td>dual &amp; quad (22&#160;nm) <p>dual &amp; quad (14&#160;nm) </p><p>up to quad (14&#160;nm) </p><p>up to dual (14&#160;nm) </p><p>up to dual (10&#160;nm) </p> </td> <td>October 2013 <p>March 2015 </p><p>April 2016 </p><p>December 2017 </p><p>January 2021 </p> </td></tr> <tr> <th colspan="10"><small><a href="/wiki/List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">List of Intel Celeron processors</a></small> </th></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Desktop_Celerons">Desktop Celerons</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=2" title="Edit section: Desktop Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="P6-based_Celerons">P6-based Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=3" title="Edit section: P6-based Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Celeron_microprocessors#P6_based_Celerons" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;P6 based Celerons</a></div> <div class="mw-heading mw-heading4"><h4 id="Covington"><span class="anchor" id="Covington"></span>Covington</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=4" title="Edit section: Covington"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:KL_Intel_Celeron_Covington.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/cb/KL_Intel_Celeron_Covington.jpg/180px-KL_Intel_Celeron_Covington.jpg" decoding="async" width="180" height="109" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/cb/KL_Intel_Celeron_Covington.jpg/270px-KL_Intel_Celeron_Covington.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/cb/KL_Intel_Celeron_Covington.jpg/360px-KL_Intel_Celeron_Covington.jpg 2x" data-file-width="3300" data-file-height="2000" /></a><figcaption>Intel Celeron Covington</figcaption></figure> <p>Launched in April 1998, the first <i>Covington</i> Celeron was essentially a 266&#160;MHz Pentium II manufactured without any secondary cache at all.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">&#91;</span>5<span class="cite-bracket">&#93;</span></a></sup> Covington also shared the 80523 product code of Deschutes. Although clocked at 266 or 300&#160;MHz (frequencies 33 or 66&#160;MHz higher than the desktop version of the Pentium w/MMX), the cacheless Celerons had trouble outcompeting the parts they were designed to replace.<sup id="cite_ref-S7toS1_3-1" class="reference"><a href="#cite_note-S7toS1-3"><span class="cite-bracket">&#91;</span>3<span class="cite-bracket">&#93;</span></a></sup> Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">&#91;</span>6<span class="cite-bracket">&#93;</span></a></sup> The initial market interest faded rapidly in the face of its poor performance, and with sales at a very low level, Intel felt obliged to develop a substantially faster replacement as soon as possible. Nevertheless, the first Celerons were quite popular among some overclockers, for their flexible <a href="/wiki/Overclocking" title="Overclocking">overclockability</a> and reasonable price.<sup id="cite_ref-S7toS1_3-2" class="reference"><a href="#cite_note-S7toS1-3"><span class="cite-bracket">&#91;</span>3<span class="cite-bracket">&#93;</span></a></sup> Covington was only manufactured in <a href="/wiki/Slot_1" title="Slot 1">Slot 1</a> SEPP format. </p> <div class="mw-heading mw-heading4"><h4 id="Mendocino"><span class="anchor" id="Mendocino"></span>Mendocino</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=5" title="Edit section: Mendocino"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Celeron_300A_MHz.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/35/Intel_Celeron_300A_MHz.jpg/180px-Intel_Celeron_300A_MHz.jpg" decoding="async" width="180" height="98" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/35/Intel_Celeron_300A_MHz.jpg/270px-Intel_Celeron_300A_MHz.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/35/Intel_Celeron_300A_MHz.jpg/360px-Intel_Celeron_300A_MHz.jpg 2x" data-file-width="1918" data-file-height="1039" /></a><figcaption>Intel Celeron Mendocino 300&#160;MHz in SEPP package</figcaption></figure> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:KL_Intel_Celeron_Mendocino_Top.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/d4/KL_Intel_Celeron_Mendocino_Top.jpg/150px-KL_Intel_Celeron_Mendocino_Top.jpg" decoding="async" width="150" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/d4/KL_Intel_Celeron_Mendocino_Top.jpg/225px-KL_Intel_Celeron_Mendocino_Top.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/d4/KL_Intel_Celeron_Mendocino_Top.jpg/300px-KL_Intel_Celeron_Mendocino_Top.jpg 2x" data-file-width="1473" data-file-height="1476" /></a><figcaption>Top of a Mendocino-core Socket 370 Celeron (PPGA package)</figcaption></figure> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:KL_Intel_Celeron_Mendocino_S370.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e9/KL_Intel_Celeron_Mendocino_S370.jpg/150px-KL_Intel_Celeron_Mendocino_S370.jpg" decoding="async" width="150" height="151" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e9/KL_Intel_Celeron_Mendocino_S370.jpg/225px-KL_Intel_Celeron_Mendocino_S370.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e9/KL_Intel_Celeron_Mendocino_S370.jpg/300px-KL_Intel_Celeron_Mendocino_S370.jpg 2x" data-file-width="1368" data-file-height="1377" /></a><figcaption>Underside of a Mendocino-core Socket 370 Celeron, 333&#160;MHz</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Celeron_500MHz_Mendocino_SL3LQ_(PNG).png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/Intel_Celeron_500MHz_Mendocino_SL3LQ_%28PNG%29.png/220px-Intel_Celeron_500MHz_Mendocino_SL3LQ_%28PNG%29.png" decoding="async" width="220" height="154" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/Intel_Celeron_500MHz_Mendocino_SL3LQ_%28PNG%29.png/330px-Intel_Celeron_500MHz_Mendocino_SL3LQ_%28PNG%29.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/36/Intel_Celeron_500MHz_Mendocino_SL3LQ_%28PNG%29.png/440px-Intel_Celeron_500MHz_Mendocino_SL3LQ_%28PNG%29.png 2x" data-file-width="12000" data-file-height="8385" /></a><figcaption>Intel Celeron 500MHz Mendocino die shot</figcaption></figure> <p>The <i>Mendocino</i> Celeron, launched August 24, 1998, was the first retail CPU to use on-die <a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2 cache</a>. Whereas Covington had no secondary cache at all, Mendocino included 128&#160;KB of L2 cache running at full clock rate. The first Mendocino-core Celeron was clocked at a then-modest 300&#160;MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clock rate. To distinguish it from the older Covington 300&#160;MHz, Intel called the Mendocino core Celeron <i>300A</i>.<sup id="cite_ref-BigCPUShootout_7-0" class="reference"><a href="#cite_note-BigCPUShootout-7"><span class="cite-bracket">&#91;</span>7<span class="cite-bracket">&#93;</span></a></sup> Although the other Mendocino Celerons (the 333&#160;MHz part, for example) did not have an <i>A</i> appended, some people call all Mendocino processors <i>Celeron-A</i> regardless of clock rate. </p><p>The new Mendocino-core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as <i>too</i> successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. <a href="/wiki/Overclocking" title="Overclocking">Overclockers</a> soon discovered that, given a high-end <a href="/wiki/Motherboard" title="Motherboard">motherboard</a>, many Celeron 300A CPUs could run reliably at 450&#160;MHz. This was achieved by simply increasing the <a href="/wiki/Front-side_bus" title="Front-side bus">front-side bus</a> (FSB) clock rate from the stock 66&#160;MHz to the 100&#160;MHz clock of the <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a>, helped by several facts: the 440BX chipset with nominal support for 100&#160;MHz and correspondent memory had already been on the market, and the internal L2 cache was more tolerant to overclocking than external cache chips, which already had to run at half-CPU speed by design. At this frequency, the budget Mendocino Celeron rivaled the fastest x86 processors available.<sup id="cite_ref-BigCPUShootout_7-1" class="reference"><a href="#cite_note-BigCPUShootout-7"><span class="cite-bracket">&#91;</span>7<span class="cite-bracket">&#93;</span></a></sup> Some motherboards were designed to prevent this modification, by restricting the Celeron's front side bus to 66&#160;MHz. However, <a href="/wiki/Overclocking" title="Overclocking">overclockers</a> soon found that putting tape over pin B21 of the Celeron's interface slot circumvented this, allowing a 100&#160;MHz bus.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">&#91;</span>8<span class="cite-bracket">&#93;</span></a></sup> </p><p>At the time on-die cache was difficult to manufacture; especially <a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock rate as the CPU. All other Intel CPUs at that time used motherboard mounted or slot mounted secondary <a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2 cache</a>, which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512&#160;KB or 1&#160;MB), but they carried the performance penalty of slower cache performance, typically running at a <a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> frequency of 60 to 100&#160;MHz. The Pentium II's 512&#160;KB of L2 cache was implemented with a pair of relatively high-performance L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half the processor's clock rate and communicating with the CPU through a special <a href="/wiki/Back-side_bus" title="Back-side bus">back-side bus</a>. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked higher and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">&#91;</span>9<span class="cite-bracket">&#93;</span></a></sup> </p><p>Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533&#160;MHz. The Mendocino Celeron CPU came only designed for a 66&#160;MHz front-side bus, but this would not be a serious performance bottleneck until clock rates reached higher levels. </p><p>The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and <a href="/wiki/Socket_370" title="Socket 370">Socket 370</a> <a href="/wiki/Pin_grid_array#Plastic" title="Pin grid array">PPGA</a> package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant; beginning with the 466&#160;MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed <a href="/wiki/Slotket" title="Slotket">Slotkets</a>) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is they supported <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a> (SMP), and there was at least one motherboard released (the <a href="/wiki/ABIT_BP6" title="ABIT BP6">ABIT BP6</a>) which took advantage of this fact. </p><p>The Mendocino also came in a mobile variant, with clock rates of 266, 300, 333, 366, 400, 433 and 466&#160;MHz. </p><p>In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related <i>Dixon</i> Mobile Pentium II variant. </p> <div class="mw-heading mw-heading4"><h4 id="Coppermine-128">Coppermine-128</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=6" title="Edit section: Coppermine-128"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1237032888/mw-parser-output/.tmulti">.mw-parser-output .tmulti .multiimageinner{display:flex;flex-direction:column}.mw-parser-output .tmulti .trow{display:flex;flex-direction:row;clear:left;flex-wrap:wrap;width:100%;box-sizing:border-box}.mw-parser-output .tmulti .tsingle{margin:1px;float:left}.mw-parser-output .tmulti .theader{clear:both;font-weight:bold;text-align:center;align-self:center;background-color:transparent;width:100%}.mw-parser-output .tmulti .thumbcaption{background-color:transparent}.mw-parser-output .tmulti .text-align-left{text-align:left}.mw-parser-output .tmulti .text-align-right{text-align:right}.mw-parser-output .tmulti .text-align-center{text-align:center}@media all and (max-width:720px){.mw-parser-output .tmulti .thumbinner{width:100%!important;box-sizing:border-box;max-width:none!important;align-items:center}.mw-parser-output .tmulti .trow{justify-content:center}.mw-parser-output .tmulti .tsingle{float:none!important;max-width:100%!important;box-sizing:border-box;text-align:center}.mw-parser-output .tmulti .tsingle .thumbcaption{text-align:left}.mw-parser-output .tmulti .trow>.thumbcaption{text-align:center}}@media screen{html.skin-theme-clientpref-night .mw-parser-output .tmulti .multiimageinner img{background-color:white}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .tmulti .multiimageinner img{background-color:white}}</style><div class="thumb tmulti tright"><div class="thumbinner multiimageinner" style="width:312px;max-width:312px"><div class="trow"><div class="tsingle" style="width:154px;max-width:154px"><div class="thumbimage" style="height:151px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Celeron_Coppermine-128_600.jpg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1a/Celeron_Coppermine-128_600.jpg/152px-Celeron_Coppermine-128_600.jpg" decoding="async" width="152" height="151" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1a/Celeron_Coppermine-128_600.jpg/228px-Celeron_Coppermine-128_600.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1a/Celeron_Coppermine-128_600.jpg/304px-Celeron_Coppermine-128_600.jpg 2x" data-file-width="800" data-file-height="795" /></a></span></div><div class="thumbcaption">Celeron <i>Coppermine 128</i> 600&#160;MHz (<a href="/wiki/FC-PGA" class="mw-redirect" title="FC-PGA">FC-PGA</a> package)</div></div><div class="tsingle" style="width:154px;max-width:154px"><div class="thumbimage" style="height:151px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Celeron_Coppermine-128_600_back.jpg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/8/82/Celeron_Coppermine-128_600_back.jpg/152px-Celeron_Coppermine-128_600_back.jpg" decoding="async" width="152" height="152" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/82/Celeron_Coppermine-128_600_back.jpg/228px-Celeron_Coppermine-128_600_back.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/82/Celeron_Coppermine-128_600_back.jpg/304px-Celeron_Coppermine-128_600_back.jpg 2x" data-file-width="600" data-file-height="599" /></a></span></div><div class="thumbcaption">Underside of a Celeron <i>Coppermine 128</i>, 600&#160;MHz</div></div></div></div></div> <p>The next generation Celeron was the <i> '<a href="/wiki/Coppermine_(microprocessor)" class="mw-redirect" title="Coppermine (microprocessor)">Coppermine</a>-128' </i> (sometimes known as the <i>Celeron II</i>). These were a derivative of Intel's <i>Coppermine</i> <a href="/wiki/Pentium_III" title="Pentium III">Pentium III</a> and were released on March 29, 2000.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">&#91;</span>10<span class="cite-bracket">&#93;</span></a></sup> This Celeron used a Coppermine core with half of its L2 cache switched off, resulting in 128&#160;KB of 4-way associative on-chip L2 cache as on the Mendocino, and was initially likewise restricted to a 66&#160;MHz Front Side Bus speed. Despite the halved associativity on the L2 cache, which reduced hit rates compared to the full Coppermine design, it kept the 256-bit wide L2 cache bus, which meant an advantage compared to Mendocino and older Katmai/Pentium II designs, which all had a 64-bit datapath to their L2 caches.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">&#91;</span>11<span class="cite-bracket">&#93;</span></a></sup><sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">&#91;</span>12<span class="cite-bracket">&#93;</span></a></sup> <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> instructions were also enabled. </p><p>All Coppermine-128s were produced in the same <a href="/wiki/FCPGA" class="mw-redirect" title="FCPGA">FCPGA</a> Socket 370 format that most Coppermine Pentium III CPUs used. These Celeron processors began at 533&#160;MHz and continued through 566, 600, 633, 667, 700, 733, and 766&#160;MHz. Because of the limitations of the 66&#160;MHz bus, there were diminishing returns on performance as clock rates increased. On January 3, 2001, Intel switched to a 100&#160;MHz bus with the launch of the 800&#160;MHz Celeron, resulting in a significant performance-per-clock improvement.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">&#91;</span>13<span class="cite-bracket">&#93;</span></a></sup> All Coppermine-128 CPUs from 800&#160;MHz and higher use the 100&#160;MHz front side bus. Various models were made at 800, 850, 900, 950, 1000, and 1100&#160;MHz. </p><p>In Intel's "Family/Model/Stepping" scheme, Coppermine Celerons and Pentium IIIs are family 6, model 8 and their Intel product code is 80526. </p> <div class="mw-heading mw-heading4"><h4 id="Tualatin-256">Tualatin-256</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=7" title="Edit section: Tualatin-256"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure typeof="mw:File/Thumb"><a href="/wiki/File:Tualeron_1200.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/en/thumb/9/9e/Tualeron_1200.jpg/150px-Tualeron_1200.jpg" decoding="async" width="150" height="150" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/9e/Tualeron_1200.jpg/225px-Tualeron_1200.jpg 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/9e/Tualeron_1200.jpg/300px-Tualeron_1200.jpg 2x" data-file-width="316" data-file-height="316" /></a><figcaption>A Tualatin-core Celeron 1.2&#160;GHz (<i>Tualeron</i>) (FC-PGA2 package)</figcaption></figure> <p>These Celeron processors, released initially at 1.2&#160;GHz on October 2, 2001,<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">&#91;</span>14<span class="cite-bracket">&#93;</span></a></sup> were based on the Pentium III <b> '<a href="/wiki/Pentium_III#Tualatin" title="Pentium III">Tualatin</a>'</b> core and made with a 0.13 micrometer process for the <a href="/wiki/FCPGA" class="mw-redirect" title="FCPGA">FCPGA 2</a> Socket 370. They were nicknamed "Tualeron" by some enthusiasts — a portmanteau of the words <a href="/wiki/Pentium_III#Tualatin" title="Pentium III">Tualatin</a> and Celeron. Some software and users refer to the chips as <i>Celeron-S</i>, referring to the chip's lineage with the Pentium III-S, but this is not an official designation. Intel later released 1&#160;GHz and 1.1&#160;GHz parts (which were given the extension <i>A</i> to their name to differentiate them from the Coppermine-128 of the same clock rate they replaced).<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">&#91;</span>15<span class="cite-bracket">&#93;</span></a></sup> A 1.3&#160;GHz chip, launched January 4, 2002,<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">&#91;</span>16<span class="cite-bracket">&#93;</span></a></sup> and finally a 1.4&#160;GHz chip, launched May 15, 2002 (the same day as the 1.7&#160;GHz Willamette-based Celeron launch),<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">&#91;</span>17<span class="cite-bracket">&#93;</span></a></sup> marked the end of the Tualatin-256 line. </p><p>The most significant differences compared to the Pentium III Tualatin are a lower 100&#160;MHz bus and fixed 256&#160;KB of L2 cache (whereas the Pentium III was offered with either 256&#160;KB or 512&#160;KB L2 cache); cache associativity stayed at 8-way,<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">&#91;</span>18<span class="cite-bracket">&#93;</span></a></sup> although the newly introduced data prefetching appears to have been disabled.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">&#91;</span>19<span class="cite-bracket">&#93;</span></a></sup> Furthermore, the Tualatin-256's L2 cache has a higher latency which boosted manufacturing yields for this budget CPU.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">&#91;<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (December 2017)">citation needed</span></a></i>&#93;</sup> On the other hand, this improved stability when overclocking and most of them had no problem working at 133&#160;MHz FSB for a substantial performance increase. </p><p>Despite offering much improved performance over the Coppermine Celeron it superseded, the Tualatin Celeron still suffered stiff competition from AMD's <a href="/wiki/Duron" title="Duron">Duron</a> budget processor.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">&#91;</span>20<span class="cite-bracket">&#93;</span></a></sup> Intel later responded by releasing the NetBurst Willamette Celeron, and for some time Tualatin Celerons were manufactured and sold in parallel with the Pentium 4-based Celerons that replaced them. </p><p>In Intel's "Family/Model/Stepping" scheme, Tualatin Celerons and Pentium IIIs are family 6, model 11 and their Intel product code is 80530. </p> <div class="mw-heading mw-heading3"><h3 id="NetBurst-based_Celerons">NetBurst-based Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=8" title="Edit section: NetBurst-based Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Celeron_microprocessors#Netburst_based_Celerons" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;Netburst based Celerons</a></div> <div class="mw-heading mw-heading4"><h4 id="Willamette-128">Willamette-128</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=9" title="Edit section: Willamette-128"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>These Celerons were for socket 478 and were based on the <i><a href="/wiki/Pentium_4#Willamette" title="Pentium 4">Willamette</a></i> <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a> core, being a completely different design compared to the previous Tualatin Celeron. These are often known as the <i>Celeron 4</i>. Their L2 cache (128&#160;KB) is half that of the <i>Willamette</i>-based Pentium 4's 256&#160;KB of L2 cache, but otherwise the two are very similar. With the transition to the Pentium 4 core the Celeron now featured SSE2 instructions. The ability to share the same socket as the Pentium 4 meant that the Celeron now had the option to use <a href="/wiki/RDRAM" title="RDRAM">RDRAM</a>, <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>, or traditional <a href="/wiki/SDRAM#SDR_SDRAM" class="mw-redirect" title="SDRAM">SDRAM</a>. Willamette Celerons were launched May 15, 2002, initially at 1.7&#160;GHz, and offered a noticeable performance improvement over the older 1.3&#160;GHz <i>Tualatin</i>-based Celeron part, being able to finally outperform a 1.3&#160;GHz AMD Duron, which at the time was AMD's top competing budget processor.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">&#91;</span>21<span class="cite-bracket">&#93;</span></a></sup> On June 12, 2002, Intel launched the last Willamette Celeron, a 1.8&#160;GHz model.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">&#91;</span>22<span class="cite-bracket">&#93;</span></a></sup> It contains 42 million transistors and has a die area of 217&#160;mm<sup>2</sup>.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">&#91;</span>23<span class="cite-bracket">&#93;</span></a></sup> </p><p>In Intel's "Family/Model/Stepping" scheme, Willamette Celerons and Pentium 4s are family 15, model 1, and their Intel product code is 80531. </p> <div class="mw-heading mw-heading4"><h4 id="Northwood-128">Northwood-128</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=10" title="Edit section: Northwood-128"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>These socket 478 Celerons are based on the <i><a href="/wiki/Pentium_4#Northwood" title="Pentium 4">Northwood</a></i> Pentium 4 core, and also have 128&#160;KB of L2&#160;cache. The only difference between the <i>Northwood-128</i>-based and the <i>Willamette-128</i>-based Celeron is the fact that it was built on the new 130&#160;nm process which shrank the die size, increased the transistor count, and lowered the core voltage from 1.7&#160;V on the <i>Willamette-128</i> to 1.52&#160;V for the <i>Northwood-128</i>. Despite these differences, they are functionally the same as the Willamette-128 Celeron, and perform largely the same clock-for-clock. The <i>Northwood-128</i> family of processors were initially released as a 2&#160;GHz core (a 1.9&#160;GHz model was announced earlier, but never launched<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">&#91;</span>24<span class="cite-bracket">&#93;</span></a></sup>) on September 18, 2002.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">&#91;</span>25<span class="cite-bracket">&#93;</span></a></sup> Since that time Intel has released a total of 10 different clock speeds ranging from 1.8&#160;GHz to 2.8&#160;GHz, before being surpassed by the Celeron D. Although the <i>Northwood</i>-based Celerons suffer considerably from their small L2&#160;cache, some clock rates have been favored in the enthusiast market because, like the old 300A, they can run well above their specified clock rate.<sup id="cite_ref-Schmid_2-1" class="reference"><a href="#cite_note-Schmid-2"><span class="cite-bracket">&#91;</span>2<span class="cite-bracket">&#93;</span></a></sup> </p><p>In Intel's "Family/Model/Stepping" scheme, Northwood Celerons and Pentium 4s are family 15, model 2, and their Intel product code is 80532. </p> <div class="mw-heading mw-heading4"><h4 id="Prescott-256">Prescott-256 <span class="anchor" id="Celeron_D"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=11" title="Edit section: Prescott-256"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Celeron_D_340_(Prescott)_(JPG).jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_Celeron_D_340_%28Prescott%29_%28JPG%29.jpg/220px-Intel_Celeron_D_340_%28Prescott%29_%28JPG%29.jpg" decoding="async" width="220" height="229" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_Celeron_D_340_%28Prescott%29_%28JPG%29.jpg/330px-Intel_Celeron_D_340_%28Prescott%29_%28JPG%29.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_Celeron_D_340_%28Prescott%29_%28JPG%29.jpg/440px-Intel_Celeron_D_340_%28Prescott%29_%28JPG%29.jpg 2x" data-file-width="24424" data-file-height="25452" /></a><figcaption>Prescott Celeron D 340 die shot </figcaption></figure> <p>Prescott-256 <b>Celeron D</b> processors, initially launched June 25, 2004,<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">&#91;</span>26<span class="cite-bracket">&#93;</span></a></sup> featuring double the L1 cache (16&#160;KB) and L2 cache (256&#160;KB) as compared to the previous Willamette and Northwood desktop Celerons, by virtue of being based on the <i><a href="/wiki/Pentium_4#Prescott" title="Pentium 4">Prescott</a></i> Pentium 4 core.<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">&#91;</span>27<span class="cite-bracket">&#93;</span></a></sup> </p><p>It also features a 533&#160;MT/s bus and <a href="/wiki/SSE3" title="SSE3">SSE3</a>, and a 3xx model number (compared to 5xx for Pentium 4s and 7xx for Pentium Ms). The Prescott-256 Celeron D was manufactured for <a href="/wiki/Socket_478" title="Socket 478">Socket 478</a> and <a href="/wiki/LGA_775" title="LGA 775">LGA 775</a>, with 3x0 and 3x5 designations from 310 through to 355 at clock speeds of 2.13&#160;GHz to 3.33&#160;GHz. </p><p>The Intel Celeron D processor works with the Intel 845 and 865 chipset families. The <i>D</i> suffix actually has no official designation and does not indicate that these models are dual-core. It is used simply to distinguish this line of Celeron from the previous, lower performing Northwood and Willamette series, and also from the mobile series, the Celeron M (which also uses 3xx model numbers).<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">&#91;</span>28<span class="cite-bracket">&#93;</span></a></sup> Unlike the <a href="/wiki/Pentium_D" title="Pentium D">Pentium D</a>, the Celeron D is <i>not</i> a dual core processor. </p><p>The Celeron D was a major performance improvement over previous NetBurst-based Celerons. A test using a variety of applications, run by Derek Wilson at Anandtech.com, showed that the new Celeron D architecture alone offered up performance improvements on average of &gt;10% over a Northwood Celeron when both CPUs were run at the same bus and clock rate.<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">&#91;</span>29<span class="cite-bracket">&#93;</span></a></sup> This CPU also had the addition of SSE3 instructions and the higher FSB which only contributed to this already impressive gain. </p><p>Despite its many improvements, the <i>Prescott</i> core of the Celeron D had at least one major drawback&#160;&#8211;&#32; heat. Unlike the fairly cool-running Northwood Celeron, the Prescott-256 had a class-rated <a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> of 73&#160;W, which prompted Intel to include a more intricate copper core/aluminum finned cooler to help handle the additional heat.<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">&#91;</span>30<span class="cite-bracket">&#93;</span></a></sup> </p><p>In mid-2005, Intel refreshed the Celeron D with <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a> and <a href="/wiki/XD_Bit" class="mw-redirect" title="XD Bit">XD Bit</a> (eXecute Disable) enabled. Model numbers increase by 1 over the previous generation (e.g., 330 became 331). This only applied to <a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> Celeron Ds. There are no <a href="/wiki/Socket_478" title="Socket 478">Socket 478</a> CPUs with XD Bit capabilities. </p><p>In Intel's "Family/Model/Stepping" scheme, Prescott Celeron Ds and Pentium 4s are family 15, model 3 (up to stepping E0) or 4 (stepping E0 onwards), and their Intel product code is 80546 or 80547, depending on socket type. </p> <div class="mw-heading mw-heading4"><h4 id="Cedar_Mill-512">Cedar Mill-512</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=12" title="Edit section: Cedar Mill-512"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Based on the <i>Cedar Mill</i> Pentium 4 core, this version of the Celeron D was launched May 28, 2006, and continued the 3xx naming scheme with the Celeron D 347 (3.06&#160;GHz), 352 (3.2&#160;GHz), 356 (3.33&#160;GHz), 360 (3.46&#160;GHz), and 365 (3.6&#160;GHz). The Cedar Mill Celeron D is largely the same as the Prescott-256, except with double the L2 cache (512&#160;KB) and based on a 65&#160;nm manufacturing process. The Cedar Mill-512 Celeron D is LGA 775 exclusive. The main benefits of the Cedar Mill Celerons over the Prescott Celerons are the slightly increased performance due to the larger L2 cache, higher clock rates, and less heat dissipation, with several models having a TDP lowered to 65&#160;W from Prescott's lowest offering of 73&#160;W.<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">&#91;</span>31<span class="cite-bracket">&#93;</span></a></sup> </p><p>In Intel's "Family/Model/Stepping" scheme, Cedar Mill Celeron Ds and Pentium 4s are family 15, model 6, and their Intel product code is 80552. </p> <div class="mw-heading mw-heading3"><h3 id="Core-based_Celerons">Core-based Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=13" title="Edit section: Core-based Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Celeron_microprocessors#Core_based_Celerons" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;Core based Celerons</a></div> <div class="mw-heading mw-heading4"><h4 id="Conroe-L">Conroe-L</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=14" title="Edit section: Conroe-L"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Celeron_420.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_Celeron_420.png/150px-Intel_Celeron_420.png" decoding="async" width="150" height="151" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_Celeron_420.png/225px-Intel_Celeron_420.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_Celeron_420.png/300px-Intel_Celeron_420.png 2x" data-file-width="1020" data-file-height="1027" /></a><figcaption>Celeron 420 (Conroe-L, 1.6&#160;GHz)</figcaption></figure> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Conroe_(microprocessor)#Conroe-L" title="Conroe (microprocessor)">Conroe (microprocessor) §&#160;Conroe-L</a></div> <p>The Conroe-L Celeron is a single-core processor built on the <a href="/wiki/Core_(microarchitecture)" class="mw-redirect" title="Core (microarchitecture)">Core microarchitecture</a> and is thus clocked much lower than the Cedar Mill Celerons, but still outperforms them. It is based on the 65&#160;nm <a href="/wiki/Conroe_(microprocessor)#Conroe-L" title="Conroe (microprocessor)">Conroe-L</a> core,<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">&#91;</span>32<span class="cite-bracket">&#93;</span></a></sup> and uses a 400-series model number sequence.<sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">&#91;</span>33<span class="cite-bracket">&#93;</span></a></sup> The FSB was increased to 800&#160;MT/s from 533&#160;MT/s in this generation, and the TDP was decreased from 65&#160;W to 35&#160;W. As is traditional with Celerons, it does not have Intel <a href="/wiki/X86_virtualization" title="X86 virtualization">VT-x</a> instruction support or <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> (although Enhanced Halt State is enabled, allowing the Celerons to lower the multiplier to 6× and decrease core voltage while idle). All Conroe-L models are single-core processors for the value segment of the market, much like the AMD K8-based <a href="/wiki/Sempron" title="Sempron">Sempron</a>. The product line was launched on June 5, 2007.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">&#91;</span>34<span class="cite-bracket">&#93;</span></a></sup> </p><p>On October 21, 2007, Intel presented a new processor for its Intel Essential Series. The full name of the processor is Celeron 220 and is soldered on the D201GLY2 motherboard. With 1.2&#160;GHz and a 512&#160;KB L2&#160;cache it has a TDP of 19&#160;W and can be cooled passively. The Celeron 220 is the successor of the Celeron 215 which is based on a Yonah core and used on the D201GLY motherboard. This processor is exclusively used on the mini-ITX boards targeted to the sub-value market segment. </p> <div class="mw-heading mw-heading4"><h4 id="Allendale">Allendale <span class="anchor" id="Allendale-512"></span><span class="anchor" id="Celeron_Dual-Core"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=15" title="Edit section: Allendale"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Conroe_(microprocessor)#Allendale" title="Conroe (microprocessor)">Conroe (microprocessor) §&#160;Allendale</a></div> <p>Intel launched the dual core Celeron E1xxx processor line on January 20, 2008, based on the Allendale core. The CPU has 800&#160;MT/s FSB, 65&#160;W TDP and uses 512&#160;KB of the chip's 2&#160;MB L2&#160;cache, significantly limiting performance for uses such as gaming. New features to the Celeron family included full enhanced halt state and enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> technology. Clock rates range from 1.6&#160;GHz to 2.4&#160;GHz. It is compatible with other Allendale-based CPUs such as the Core 2 Duo E4xxx and Pentium Dual-Core E2xxx.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">&#91;</span>35<span class="cite-bracket">&#93;</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Wolfdale-3M">Wolfdale-3M</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=16" title="Edit section: Wolfdale-3M"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Wolfdale_(microprocessor)#Wolfdale-3M" title="Wolfdale (microprocessor)">Wolfdale (microprocessor) §&#160;Wolfdale-3M</a></div> <p>The Celeron E3000 series, starting with E3200 and E3300, was released in August 2009, featuring the Wolfdale-3M core used in <a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Pentium Dual-Core</a> E5000, Pentium E6000 and <a href="/wiki/Core_2" class="mw-redirect" title="Core 2">Core 2</a> Duo E7000 series. The main difference to Allendale-based Celeron processors is the support for <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a> and increased performance due to the double L2 Cache of 1&#160;MB. </p> <div class="mw-heading mw-heading3"><h3 id="Nehalem-based_Celerons">Nehalem-based Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=17" title="Edit section: Nehalem-based Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/List_of_Intel_Celeron_microprocessors#Nehalem_based_Celerons" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;Nehalem based Celerons</a>, and <a href="/wiki/List_of_Intel_Celeron_microprocessors#Nehalem_based_Celerons_3" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;Nehalem based Celerons 3</a></div> <div class="mw-heading mw-heading4"><h4 id="Clarkdale">Clarkdale</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=18" title="Edit section: Clarkdale"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Clarkdale_(microprocessor)" title="Clarkdale (microprocessor)">Clarkdale (microprocessor)</a></div> <p>With the introduction of the Desktop Core i3 and Core i5 processor code named <i>Clarkdale</i> in January 2010, Intel also added a new Celeron line, starting with the Celeron G1101. This is the first Celeron to come with on-chip <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> and integrated graphics. Despite using the same Clarkdale chip as the Core i5-6xx line, it does not support <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo Boost</a>, <a href="/wiki/HyperThreading" class="mw-redirect" title="HyperThreading">HyperThreading</a>, <a href="/wiki/Intel_VT-d" class="mw-redirect" title="Intel VT-d">VT-d</a>, <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">SMT</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> or <a href="/wiki/AES_instruction_set" title="AES instruction set">AES new instructions</a>, and it comes with only 2&#160;MB of third-level cache enabled.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">&#91;</span>36<span class="cite-bracket">&#93;</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Jasper_Forest">Jasper Forest</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=19" title="Edit section: Jasper Forest"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Jasper_Forest_(microprocessor)" class="mw-redirect" title="Jasper Forest (microprocessor)">Jasper Forest (microprocessor)</a></div> <p>The Celeron P1053 is an embedded processor for <a href="/wiki/Socket_1366" class="mw-redirect" title="Socket 1366">Socket 1366</a> from the <i>Jasper Forest</i> family. All other members of this family are known as Xeon C35xx or C55xx. The Jasper Forest chip is closely related to <a href="/wiki/Lynnfield_(microprocessor)" title="Lynnfield (microprocessor)">Lynnfield</a> and contains four cores, 8&#160;MB of L3&#160;cache and a QPI interface, but most of these are disabled in the Celeron version, leaving a single core with 2&#160;MB of L3&#160;cache. </p> <div class="mw-heading mw-heading3"><h3 id="Sandy_Bridge-based_desktop_Celerons">Sandy Bridge-based desktop Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=20" title="Edit section: Sandy Bridge-based desktop Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Celeron_G530_2.4GHz.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e9/Celeron_G530_2.4GHz.jpg/200px-Celeron_G530_2.4GHz.jpg" decoding="async" width="200" height="197" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e9/Celeron_G530_2.4GHz.jpg/300px-Celeron_G530_2.4GHz.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e9/Celeron_G530_2.4GHz.jpg/400px-Celeron_G530_2.4GHz.jpg 2x" data-file-width="1140" data-file-height="1124" /></a><figcaption>Celeron G530 2.4 GHz "Sandy Bridge"</figcaption></figure> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Celeron_microprocessors#Sandy_Bridge_based_Celerons" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;Sandy Bridge based Celerons</a></div> <p>The Sandy Bridge-based Celeron processors were released in 2011. They are <a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a> processors (available in single- and dual-core versions) with integrated Intel HD Graphics GPU and containing up to 2&#160;MB of L3&#160;cache. Turbo-Boost, AVX and AES-NI have been disabled. Hyper-Threading is available on some single-core models, namely G460, G465 and G470. </p> <div class="mw-heading mw-heading3"><h3 id="Ivy_Bridge-based_desktop_Celerons">Ivy Bridge-based desktop Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=21" title="Edit section: Ivy Bridge-based desktop Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Celeron_microprocessors#.22Ivy_Bridge.22_.2822_nm.29" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;.22Ivy_Bridge.22_.2822_nm.29</a></div> <p>All Celerons of this generation belong in the G16xx series. They give some boost in performance over Sandy Bridge-based Celerons due to a 22&#160;nm die shrink, as well as some other minor improvements. </p> <div class="mw-heading mw-heading3"><h3 id="Haswell-based_desktop_Celerons">Haswell-based desktop Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=22" title="Edit section: Haswell-based desktop Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell (microarchitecture)</a></div> <div class="mw-heading mw-heading3"><h3 id="Skylake-based_desktop_Celerons">Skylake-based desktop Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=23" title="Edit section: Skylake-based desktop Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>All Celerons of this generation added <a href="/wiki/AES-NI" class="mw-redirect" title="AES-NI">AES-NI</a> and <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a> instruction set. </p> <div class="mw-heading mw-heading3"><h3 id="Kaby_Lake-based_desktop_Celerons">Kaby Lake-based desktop Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=24" title="Edit section: Kaby Lake-based desktop Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a></div> <div class="mw-heading mw-heading3"><h3 id="Coffee_Lake-based_desktop_Celerons">Coffee Lake-based desktop Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=25" title="Edit section: Coffee Lake-based desktop Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a></div> <div class="mw-heading mw-heading3"><h3 id="Comet_Lake-based_desktop_Celerons">Comet Lake-based desktop Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=26" title="Edit section: Comet Lake-based desktop Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Comet_Lake" title="Comet Lake">Comet Lake</a></div> <div class="mw-heading mw-heading3"><h3 id="Alder_Lake-based_desktop_Celerons">Alder Lake-based desktop Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=27" title="Edit section: Alder Lake-based desktop Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Alder_Lake" title="Alder Lake">Alder Lake</a></div> <div class="mw-heading mw-heading2"><h2 id="Mobile_Celerons">Mobile Celerons</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=28" title="Edit section: Mobile Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="P6-based_mobile_Celerons">P6-based mobile Celerons <span class="anchor" id="Celeron_M"></span></h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=29" title="Edit section: P6-based mobile Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Celeron_microprocessors#P6_based_Celerons_2" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;P6 based Celerons 2</a></div> <div class="mw-heading mw-heading4"><h4 id="Mendocino_(mobile)"><span id="Mendocino_.28mobile.29"></span>Mendocino (mobile)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=30" title="Edit section: Mendocino (mobile)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Celeron_mobile.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Celeron_mobile.jpg/200px-Celeron_mobile.jpg" decoding="async" width="200" height="131" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Celeron_mobile.jpg/300px-Celeron_mobile.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Celeron_mobile.jpg/400px-Celeron_mobile.jpg 2x" data-file-width="815" data-file-height="534" /></a><figcaption>Mobile Celeron in BGA2 package</figcaption></figure> <p>Similar to the Mendocino (Celeron-A): 250&#160;nm, 32&#160;KB L1 cache and 128&#160;KB L2 cache, but uses a lower voltage (1.5–1.9&#160;V) and two power-saving modes: Quick Start, and Deep Sleep. Packaged in the small, 615-pin <a href="/wiki/BGA2" class="mw-redirect" title="BGA2">BGA2</a> or <a href="/wiki/Micro-PGA2" class="mw-redirect" title="Micro-PGA2">Micro-PGA2</a> package. </p> <div class="mw-heading mw-heading4"><h4 id="Tualatin-256_(mobile)"><span id="Tualatin-256_.28mobile.29"></span>Tualatin-256 (mobile)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=31" title="Edit section: Tualatin-256 (mobile)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>These were the first Mobile Celerons based on the Tualatin core. They differed from their desktop counterparts in that the Mobile series were offered in both 100&#160;MHz and 133&#160;MHz FSB. Like the desktop Tualatins, these chips had 256&#160;KB of L2 cache. </p> <div class="mw-heading mw-heading3"><h3 id="NetBurst-based_mobile_Celerons">NetBurst-based mobile Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=32" title="Edit section: NetBurst-based mobile Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Celeron_microprocessors#Netburst_based_Celerons_2" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;Netburst based Celerons 2</a></div> <div class="mw-heading mw-heading4"><h4 id="Northwood-256">Northwood-256</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=33" title="Edit section: Northwood-256"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>These are the Mobile Celeron range used in laptops. Also based on the Northwood core, they feature a 256&#160;KB L2 cache. These Celeron processors were a good deal higher performing than the desktop counterparts because of their larger L2 cache sizes.<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">&#91;</span>37<span class="cite-bracket">&#93;</span></a></sup> They were eventually replaced by the Celeron M brand which is built around the Pentium M processor design. </p> <div class="mw-heading mw-heading3"><h3 id="Pentium_M-based_mobile_Celerons">Pentium M-based mobile Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=34" title="Edit section: Pentium M-based mobile Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Celeron_microprocessors#Pentium-M_based_Celerons" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;Pentium-M based Celerons</a></div> <div class="mw-heading mw-heading4"><h4 id="Banias-512">Banias-512</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=35" title="Edit section: Banias-512"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>This Celeron (sold under the <b>Celeron M</b> brand) is based on the <i>Banias</i> <a href="/wiki/Pentium_M" title="Pentium M">Pentium M</a>, and differs from its parent in that it has half the L2 cache, and does not support the clock-varying SpeedStep technology. It performs reasonably well compared to the Pentium M, but battery life is noticeably shorter on a Celeron M–based notebook than it is on a comparable Pentium M notebook. </p><p>A system based on the Celeron M processor may not use the <a href="/wiki/Centrino" title="Centrino">Centrino</a> brand name, regardless of what chipset and <a href="/wiki/Wi-Fi" title="Wi-Fi">Wi-Fi</a> components are used. </p><p>In Intel's "Family/Model/Stepping" scheme, Banias Celeron Ms and Pentium Ms are family 6, model 9 and their Intel product code is 80535. </p> <div class="mw-heading mw-heading4"><h4 id="Shelton">Shelton</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=36" title="Edit section: Shelton"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <i>Shelton</i> core is a Banias core without <i>any</i> L2 cache and SpeedStep. It is used in Intel's small form factor D845GVSH motherboard, intended for Asian and South American markets. The processor identifies itself as a "Intel Celeron 1.0B <a href="/wiki/Gigahertz" class="mw-redirect" title="Gigahertz">GHz</a>", to differentiate it from the previous Coppermine-128 and Tualatin 1.0&#160;GHz processors. </p><p>The Shelton'08 is a basic platform for a low cost notebook released by Intel at January 2008. The platform uses Intel's single-core Diamondville CPU with a clock frequency of 1.6&#160;GHz and a 533&#160;MT/s FSB and power consumption of 3.5&#160;W. The platform's total power consumption is around 8&#160;W, translating to battery usage time of between 3–4 hours. The platform consists of a 945GSE chipset, which includes built-in DirectX 9 graphics and supports single channel DDR2 memory. An 802.11g Wi-Fi module, USB/PATA port SSD (solid state drive), and a 7- or 8-inch panel will typically round out the platform. </p> <div class="mw-heading mw-heading4"><h4 id="Dothan-1024">Dothan-1024</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=37" title="Edit section: Dothan-1024"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A 90&#160;nm Celeron M with half of the L2 cache of the 90&#160;nm <i>Dothan</i> Pentium Ms (twice the L2 cache of the 130&#160;nm Celeron Ms, though), and, like its predecessor, lacking SpeedStep. The first Celeron Ms that supports the <a href="/wiki/XD_bit" class="mw-redirect" title="XD bit">XD bit</a> was released in January 2005, in general any Celeron M released after that supports the <a href="/wiki/XD_bit" class="mw-redirect" title="XD bit">XD bit</a>. There is also a 512&#160;KB low voltage version that was used in the early <a href="/wiki/ASUS_Eee_PC" class="mw-redirect" title="ASUS Eee PC">ASUS Eee PC</a> models. </p><p>In Intel's "Family/Model/Stepping" scheme, Dothan Celeron Ms and Pentium Ms are family 6, model 13 and their Intel product code is 80536. </p> <div class="mw-heading mw-heading4"><h4 id="Yonah">Yonah</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=38" title="Edit section: Yonah"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah (microprocessor)</a></div><p><span class="anchor" id="Yonah-1024"></span> </p><p>The Celeron M 400-series is a 65&#160;nm Celeron M based on the single-core <b><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah</a></b> chip, like the <a href="/wiki/Intel_Core#Core_2_Solo" title="Intel Core">Core Solo</a>. Like its predecessors in the Celeron M series, this Celeron M has half of the L2 cache (1&#160;MB) of Core Solo and lacks SpeedStep. This core also brings new features to Celeron M including a higher front side bus (533&#160;MT/s), <a href="/wiki/SSE3" title="SSE3">SSE3</a> instructions. September 2006 and January 4, 2008, mark a discontinuation of many <i>Celeron M</i> branded CPUs.<sup id="cite_ref-See_DigiTimes_38-0" class="reference"><a href="#cite_note-See_DigiTimes-38"><span class="cite-bracket">&#91;</span>38<span class="cite-bracket">&#93;</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Core-based_mobile_Celerons">Core-based mobile Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=39" title="Edit section: Core-based mobile Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Celeron_microprocessors#Core_based_Celerons_2" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;Core based Celerons 2</a></div> <div class="mw-heading mw-heading4"><h4 id="Merom-L">Merom-L <span class="anchor" id="Merom-L"></span><span class="anchor" id="Merom-1024"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=40" title="Edit section: Merom-L"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Merom_(microprocessor)#Merom-L" title="Merom (microprocessor)">Merom (microprocessor) §&#160;Merom-L</a></div> <p>The Celeron M 523 (933&#160;MHz ULV), M&#160;520 (1.6&#160;GHz), M&#160;530 (1.73&#160;GHz), 530 (1.73&#160;GHz), 540 (1.86&#160;GHz), 550 (2.0&#160;GHz), 560 (2.13&#160;GHz), 570 (2.26&#160;GHz)<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">&#91;</span>39<span class="cite-bracket">&#93;</span></a></sup> are single-core 65&#160;nm CPUs based on the <i>Merom</i> <a href="/wiki/Core_2" class="mw-redirect" title="Core 2">Core 2</a> architecture. They feature a 533&#160;MT/s FSB, 1&#160;MB of L2 cache (half that of the low end Core 2 Duo's 2&#160;MB cache), XD-bit support, and Intel 64 technology, but lack SpeedStep and <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Virtualization Technology</a>. Two different processor models are used with identical part numbers with the same part numbers, single-core Merom-L with 1&#160;MB cache and dual-core Merom with 4&#160;MB L2&#160;cache that have the extra cache and core disabled. Celeron M 523, M 520 and M 530 are <a href="/wiki/Socket_M" title="Socket M">Socket M</a>-based, while Celeron 530 through 570 (without the M) are for <a href="/wiki/Socket_P" title="Socket P">Socket P</a>. January 4, 2008, marked the discontinuation of Merom CPUs.<sup id="cite_ref-See_DigiTimes_38-1" class="reference"><a href="#cite_note-See_DigiTimes-38"><span class="cite-bracket">&#91;</span>38<span class="cite-bracket">&#93;</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Merom-2M">Merom-2M <span class="anchor" id="Merom-2M"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=41" title="Edit section: Merom-2M"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Merom_(microprocessor)#Merom-2M" title="Merom (microprocessor)">Merom (microprocessor) §&#160;Merom-2M</a></div> <p>The Celeron 573 (1&#160;GHz, ULV), 575 (2&#160;GHz) and 585 (2.16&#160;GHz) are based on the Merom-2M core with only one core and 1&#160;MB L2&#160;cache enabled. They are similar to the Merom and Merom-L based Celerons but have a faster 667&#160;MT/s FSB. </p><p>The Celeron T1xxx processors are also based on the Merom-2M chips but have both cores enabled. The earlier T1400 (1.73&#160;GHz) and T1500 (1.86&#160;GHz) versions have a 533&#160;MT/s FSB and 512&#160;B L2&#160;cache, while the more recent T1600 (1.66&#160;GHz) and T1700 (1.83&#160;GHz) versions have 667&#160;MT/s and 1&#160;MB L2&#160;cache enabled but come with a lower clock frequency. </p> <div class="mw-heading mw-heading4"><h4 id="Penryn-3M">Penryn-3M</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=42" title="Edit section: Penryn-3M"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Penryn_(microprocessor)#Penryn-3M" title="Penryn (microprocessor)">Penryn (microprocessor) §&#160;Penryn-3M</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Microprocessor_Celeron_900_AW80585900_SLGLQ_in_mPGA478MN_socket-3595.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/80/Intel_Microprocessor_Celeron_900_AW80585900_SLGLQ_in_mPGA478MN_socket-3595.jpg/220px-Intel_Microprocessor_Celeron_900_AW80585900_SLGLQ_in_mPGA478MN_socket-3595.jpg" decoding="async" width="220" height="269" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/80/Intel_Microprocessor_Celeron_900_AW80585900_SLGLQ_in_mPGA478MN_socket-3595.jpg/330px-Intel_Microprocessor_Celeron_900_AW80585900_SLGLQ_in_mPGA478MN_socket-3595.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/80/Intel_Microprocessor_Celeron_900_AW80585900_SLGLQ_in_mPGA478MN_socket-3595.jpg/440px-Intel_Microprocessor_Celeron_900_AW80585900_SLGLQ_in_mPGA478MN_socket-3595.jpg 2x" data-file-width="2983" data-file-height="3643" /></a><figcaption>Celeron 900</figcaption></figure> <p>At the same time as the dual-core Merom-2M, Intel introduced the first 45&#160;nm Celeron processor based on the Penryn-3M core with 800&#160;MT/s FSB, 1&#160;MB L2 cache and one core enabled. This includes the Celeron M 7xx <a href="/wiki/Consumer_Ultra-Low_Voltage" title="Consumer Ultra-Low Voltage">Consumer Ultra-Low Voltage</a> (CULV) series starting at 1.2&#160;GHz and the later Celeron 900 (2.2&#160;GHz). </p><p>The initial 45&#160;nm dual-core Celeron processor was released in June 2009 and is also based on Penryn-3M. The Celeron T3000 (1.8&#160;GHz) and T3100 (1.9&#160;GHz) again come with 1&#160;MB of L2 cache enabled and an 800&#160;MT/s FSB. In September 2009, Intel also started the dual-core CULV Celeron SU2000 series, again with 1&#160;MB L2 cache. Despite the similar name, they are very different from Pentium SU2000 (with 2&#160;MB L2 cache and one active core) and Pentium T3000 (based on the 65&#160;nm <a href="/wiki/Merom_(microprocessor)" title="Merom (microprocessor)">Merom</a> processor). </p> <div class="mw-heading mw-heading3"><h3 id="Nehalem-based_mobile_Celerons">Nehalem-based mobile Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=43" title="Edit section: Nehalem-based mobile Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Celeron_microprocessors#Nehalem_based_Celerons_2" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;Nehalem based Celerons 2</a></div> <div class="mw-heading mw-heading4"><h4 id="Arrandale">Arrandale</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=44" title="Edit section: Arrandale"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Arrandale_(microprocessor)" class="mw-redirect" title="Arrandale (microprocessor)">Arrandale (microprocessor)</a></div> <p>The Arrandale-based Celeron P4xxx and U3xxx lines are low-end versions of the Pentium P6xxx and U5xxx lines, originally released as the mobile dual-core lines of Core i3/i5/i7. Like the Clarkdale-based Celeron G1xxx, they use 2&#160;MB of L3&#160;cache, which is the amount that the earlier "Penryn" based CPUs used in the Pentium brand as their L2&#160;cache. Like all Arrandale processors, the Celeron P4xxx and U3xxx use an integrated graphics core. </p> <div class="mw-heading mw-heading3"><h3 id="Sandy_Bridge-based_mobile_Celerons">Sandy Bridge-based mobile Celerons</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=45" title="Edit section: Sandy Bridge-based mobile Celerons"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/List_of_Intel_Celeron_microprocessors#Sandy_Bridge_based_Celerons" class="mw-redirect" title="List of Intel Celeron microprocessors">List of Intel Celeron microprocessors §&#160;Sandy Bridge based Celerons</a>, and <a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a></div> <p>The Celeron B8xx processors released in 2011 follow the Arrandale line. They are Dual-Core processors with integrated graphics and use the same chips as the Pentium B9xx and Core i3/i5/i7-2xxx mobile processors, but with Turbo-Boost, Hyper-Threading, VT-d, TXT and AES-NI disabled and the L3 cache reduced to 2MB. </p> <div class="mw-heading mw-heading2"><h2 id="Dual-processor_support">Dual-processor support</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=46" title="Edit section: Dual-processor support"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>As a budget processor, the Celeron does not support a <a href="/wiki/Multiprocessing" title="Multiprocessing">dual-processor</a> configuration using multiple CPU sockets, however it has been discovered that multiprocessing could be enabled on Slot 1 Celeron processors by connecting a pin on the CPU core to a contact on the processor card's connector.<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">&#91;</span>40<span class="cite-bracket">&#93;</span></a></sup> In addition, Mendocino Socket 370 processors can use multiprocessing when used on specific dual Slot 1 motherboards by using a slot adapter.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">&#91;<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (August 2013)">citation needed</span></a></i>&#93;</sup> The unofficial SMP support was removed in the Coppermine Celerons, and dual-socket support is now limited to higher-end Xeon server-class processors. Conroe/Allendale based Celeron processors and later support multiprocessing using <a href="/wiki/Multi-core" class="mw-redirect" title="Multi-core">multi-core</a> chips, but are still limited to one socket. </p><p>The <a href="/wiki/ABIT_BP6" title="ABIT BP6">ABIT BP6</a> motherboard also allows two Mendocino Socket 370 Celeron processors to operate in a <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a> (SMP) configuration without any modification to the CPUs or the motherboard. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=47" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">List of Intel Celeron processors</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=48" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-Warren_2022-1"><span class="mw-cite-backlink">^ <a href="#cite_ref-Warren_2022_1-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Warren_2022_1-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFWarren2022" class="citation web cs1">Warren, Tom (September 16, 2022). <a rel="nofollow" class="external text" href="https://www.theverge.com/2022/9/16/23356495/intel-processor-pentium-celeron-brand-2023-notebook-laptops">"Intel Processor will replace Pentium and Celeron in 2023 laptops"</a>. <i>The Verge</i><span class="reference-accessdate">. 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Retrieved <span class="nowrap">April 2,</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=en.wikichip.org&amp;rft.atitle=Braswell+-+Cores+-+Intel+-+WikiChip&amp;rft_id=https%3A%2F%2Fen.wikichip.org%2Fwiki%2Fintel%2Fcores%2Fbraswell&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3ACeleron" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/au/en/embedded/products/apollo-lake/overview.html">"Apollo Lake: Overview"</a>. <i>Intel</i><span class="reference-accessdate">. Retrieved <span class="nowrap">April 2,</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&amp;rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&amp;rft.genre=unknown&amp;rft.jtitle=Intel&amp;rft.atitle=Apollo+Lake%3A+Overview&amp;rft_id=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fau%2Fen%2Fembedded%2Fproducts%2Fapollo-lake%2Foverview.html&amp;rfr_id=info%3Asid%2Fen.wikipedia.org%3ACeleron" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Celeron&amp;action=edit&amp;section=49" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://www.intel.com/products/processor/celeron_m/index.htm">Intel Celeron M Processor – Product overview</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20070820204039/http://balusc.xs4all.nl/srv/har-cpu-int-pm.php">Intel Celeron M Banias, Dothan, and Yonah specifications</a></li> <li><a rel="nofollow" class="external text" href="http://www.cpu-collection.de/?tn=0&amp;l0=co&amp;l1=Intel&amp;l2=P%20II%20Celeron">Intel Pentium II</a> and <a rel="nofollow" class="external text" href="http://www.cpu-collection.de/?tn=0&amp;l0=co&amp;l1=Intel&amp;l2=P%20III%20Celeron">Pentium III</a> based Celerons at cpu-collection.de</li> <li><a rel="nofollow" class="external text" href="http://pc.watch.impress.co.jp/img/pcw/docs/360/112/html/1.jpg.html">Intel CPU Transition Roadmap 2008–2013</a></li> <li><a rel="nofollow" class="external text" href="http://pc.watch.impress.co.jp/img/pcw/docs/360/112/html/2.jpg.html">Intel Desktop CPU Roadmap 2004–2011</a></li> <li><a rel="nofollow" class="external text" href="http://pc.watch.impress.co.jp/img/pcw/docs/360/112/html/5.jpg.html">Intel Mobile CPU Roadmap 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abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Intel_processors" title="Template:Intel processors"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Intel_processors" title="Template talk:Intel processors"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Intel_processors" title="Special:EditPage/Template:Intel processors"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Intel_processors" style="font-size:114%;margin:0 4em"><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Intel processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Processors</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors" title="List of Intel Atom processors">Atom</a></li> <li><a href="/wiki/List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">Celeron</a></li> <li><a href="/wiki/List_of_Intel_Pentium_processors" title="List of Intel Pentium processors">Pentium</a> <ul><li><a href="/wiki/List_of_Intel_Pentium_Pro_processors" title="List of Intel Pentium Pro processors">Pro</a></li> <li><a href="/wiki/List_of_Intel_Pentium_II_processors" title="List of Intel Pentium II processors">II</a></li> <li><a href="/wiki/List_of_Intel_Pentium_III_processors" title="List of Intel Pentium III processors">III</a></li> <li><a href="/wiki/List_of_Intel_Pentium_4_processors" title="List of Intel Pentium 4 processors">4</a></li> <li><a href="/wiki/List_of_Intel_Pentium_D_processors" title="List of Intel Pentium D processors">D</a></li> <li><a href="/wiki/List_of_Intel_Pentium_M_processors" title="List of Intel Pentium M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Core_processors" title="List of Intel Core processors">Core</a> <ul><li><a href="/wiki/List_of_Intel_Core_2_processors" class="mw-redirect" title="List of Intel Core 2 processors">2</a></li> <li><a href="/wiki/List_of_Intel_Core_i3_processors" class="mw-redirect" title="List of Intel Core i3 processors">i3</a></li> <li><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">i5</a></li> <li><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">i7</a></li> <li><a href="/wiki/List_of_Intel_Core_i9_processors" class="mw-redirect" title="List of Intel Core i9 processors">i9</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Xeon_processors" title="List of Intel Xeon processors">Xeon</a></li> <li><a href="/wiki/Intel_Quark#List_of_Intel_Quark_processors" title="Intel Quark">Quark</a></li> <li><a href="/wiki/List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">Itanium</a></li></ul></li> <li><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></li> <li><a href="/wiki/List_of_Intel_chipsets" title="List of Intel chipsets">Chipsets</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a></li> <li><a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a> <ul><li><a href="/wiki/Pentium_M" title="Pentium M">P6 variant (Pentium M)</a></li> <li><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">P6 variant (Enhanced Pentium M)</a></li></ul></li> <li><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a> <ul><li><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></li></ul></li> <li><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> <ul><li><a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li></ul></li> <li><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> <ul><li><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li></ul></li> <li><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> <ul><li><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li></ul></li> <li><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> <ul><li><a href="/wiki/Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake</a></li></ul></li> <li><a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a> <ul><li><a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li></ul></li> <li><a href="/wiki/Willow_Cove" title="Willow Cove">Willow Cove</a></li> <li><a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86" title="X86">x86</a> <a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ULV</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a> <ul><li><a href="/wiki/Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></li> <li><a href="/wiki/Silvermont" title="Silvermont">Silvermont</a></li></ul></li> <li><a href="/wiki/Goldmont" title="Goldmont">Goldmont</a> <ul><li><a href="/wiki/Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></li></ul></li> <li><a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a> <ul><li><a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)" scope="row" class="navbox-group" style="width:8.5em"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a></li> <li><a class="mw-selflink selflink">Celeron</a></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/Intel_Core#12th_generation" title="Intel Core">12th gen</a></li> <li><a href="/wiki/Intel_Core#13th_generation" title="Intel Core">13th gen</a></li> <li><a href="/wiki/Intel_Core#14th_generation" title="Intel Core">14th gen</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Binary-coded_decimal" title="Binary-coded decimal">BCD</a> oriented (<a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_4004" title="Intel 4004">4004</a> (1971)</li> <li><a href="/wiki/Intel_4040" title="Intel 4040">4040</a> (1974)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">pre-x86 (<a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8008" title="Intel 8008">8008</a> (1972)</li> <li><a href="/wiki/Intel_8080" title="Intel 8080">8080</a> (1974)</li> <li><a href="/wiki/Intel_8085" title="Intel 8085">8085</a> (1977)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Early <a href="/wiki/X86" title="X86">x86</a> (<a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8086" title="Intel 8086">8086</a> (1978)</li> <li><a href="/wiki/Intel_8088" title="Intel 8088">8088</a> (1979)</li> <li><a href="/wiki/Intel_80186" title="Intel 80186">80186</a> (1982)</li> <li><a href="/wiki/Intel_80188" class="mw-redirect" title="Intel 80188">80188</a> (1982)</li> <li><a href="/wiki/Intel_80286" title="Intel 80286">80286</a> (1982)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X87" title="X87">x87</a> (external <a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt>8/16-bit databus</dt> <dd><a href="/wiki/Intel_8087" title="Intel 8087">8087</a> (1980)</dd> <dt>16-bit databus</dt> <dd><a href="/wiki/Intel_80C187" class="mw-redirect" title="Intel 80C187">80C187</a></dd> <dd><a href="/wiki/Intel_80287" class="mw-redirect" title="Intel 80287">80287</a></dd> <dd><a href="/wiki/Intel_80387SX" title="Intel 80387SX">80387SX</a></dd> <dt>32-bit databus</dt> <dd><a href="/wiki/Intel_80387" class="mw-redirect" title="Intel 80387">80387DX</a></dd> <dd><a href="/wiki/Intel_80487" class="mw-redirect" title="Intel 80487">80487</a></dd></dl> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/I386" title="I386">i386</a> <ul><li><a href="/wiki/Intel_80386SX" class="mw-redirect" title="Intel 80386SX">SX</a></li> <li><a href="/wiki/Intel_80376" title="Intel 80376">376</a></li> <li><a href="/wiki/Intel_80386EX" title="Intel 80386EX">EX</a></li></ul></li> <li><a href="/wiki/I486" title="I486">i486</a> <ul><li><a href="/wiki/I486SX" title="I486SX">SX</a></li> <li><a href="/wiki/Intel_DX2" title="Intel DX2">DX2</a></li> <li><a href="/wiki/Intel_DX4" title="Intel DX4">DX4</a></li> <li><a href="/wiki/I486SL" title="I486SL">SL</a></li> <li><a href="/wiki/RapidCAD" title="RapidCAD">RapidCAD</a></li> <li><a href="/wiki/I486_OverDrive" title="I486 OverDrive">OverDrive</a></li></ul></li> <li><a href="/wiki/Stealey" title="Stealey">A100/A110</a></li> <li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li> <li><a href="/wiki/Atom_(system_on_a_chip)" title="Atom (system on a chip)">SoC</a></li></ul></li> <li><a class="mw-selflink selflink">Celeron</a> (1998) <ul><li><a class="mw-selflink-fragment" href="#P6-based_Mobile_Celerons">M</a></li> <li><a class="mw-selflink-fragment" href="#Prescott-256">D</a> (2004)</li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_(original)" title="Pentium (original)">Original i586</a></li> <li><a href="/wiki/Pentium_OverDrive" title="Pentium OverDrive">OverDrive</a></li> <li><a href="/wiki/Pentium_Pro" title="Pentium Pro">Pro</a></li> <li><a href="/wiki/Pentium_II" title="Pentium II">II</a></li> <li><a href="/wiki/Pentium_III" title="Pentium III">III</a></li> <li><a href="/wiki/Pentium_4" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_M" title="Pentium M">M</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_P6-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">P6-based</a></li> <li><a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">NetBurst-based</a></li> <li><a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">Core-based</a></li></ul></li> <li><a href="/wiki/Intel_Quark" title="Intel Quark">Quark</a></li> <li><a href="/wiki/Tolapai" title="Tolapai">Tolapai</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/Atom_(system_on_chip)" class="mw-redirect" title="Atom (system on chip)">SoC</a></li> <li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li></ul></li> <li><a class="mw-selflink selflink">Celeron</a> <ul><li><a class="mw-selflink-fragment" href="#Prescott-256">D</a></li> <li><a class="mw-selflink-fragment" href="#Celeron_Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_4#Prescott_2M_(Extreme_Edition)" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_D" title="Pentium D">D</a></li> <li><a href="/wiki/Pentium_D#Smithfield_XE" title="Pentium D">Extreme Edition</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core_2" title="Intel Core 2">2</a></li> <li><a href="/wiki/Intel_Core#1st_generation" title="Intel Core">1st gen</a></li> <li><a href="/wiki/Intel_Core#2nd_generation" title="Intel Core">2nd gen</a></li> <li><a href="/wiki/Intel_Core#3rd_generation" title="Intel Core">3rd gen</a></li> <li><a href="/wiki/Intel_Core#4th_generation" title="Intel Core">4th gen</a></li> <li><a href="/wiki/Intel_Core#5th_generation" title="Intel Core">5th gen</a></li> <li><a href="/wiki/Intel_Core#6th_generation" title="Intel Core">6th gen</a></li> <li><a href="/wiki/Intel_Core#7th_generation" title="Intel Core">7th gen</a></li> <li><a href="/wiki/Intel_Core#8th_generation" title="Intel Core">8th gen</a></li> <li><a href="/wiki/Intel_Core#9th_generation" title="Intel Core">9th gen</a></li> <li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_Xeon_processors_(Nehalem-based)" title="List of Intel Xeon processors (Nehalem-based)">Nehalem-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Sandy_Bridge-based)" title="List of Intel Xeon processors (Sandy Bridge-based)">Sandy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Ivy_Bridge-based)" title="List of Intel Xeon processors (Ivy Bridge-based)">Ivy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Haswell-based)" title="List of Intel Xeon processors (Haswell-based)">Haswell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Broadwell-based)" title="List of Intel Xeon processors (Broadwell-based)">Broadwell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Skylake-based)" title="List of Intel Xeon processors (Skylake-based)">Skylake-based</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></dt> <dd><a href="/wiki/Intel_iAPX_432" title="Intel iAPX 432">iAPX 432</a></dd> <dt><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></dt> <dd><a href="/wiki/Itanium" title="Itanium">Itanium</a></dd> <dt><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></dt> <dd><a href="/wiki/Intel_i860" title="Intel i860">i860</a></dd> <dd><a href="/wiki/Intel_i960" title="Intel i960">i960</a></dd> <dd><a href="/wiki/StrongARM" title="StrongARM">StrongARM</a></dd> <dd><a href="/wiki/XScale" title="XScale">XScale</a></dd></dl> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li> <li><a href="/wiki/List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel GPUs</a> <ul><li><a href="/wiki/Intel_GMA" title="Intel GMA">GMA</a></li> <li><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Intel HD, UHD, and Iris Graphics</a></li> <li><a href="/wiki/Intel_Xe" title="Intel Xe">Xe</a></li> <li><a href="/wiki/Intel_Arc" title="Intel Arc">Arc</a></li></ul></li> <li><a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCHs</a></li> <li><a href="/wiki/System_Controller_Hub" title="System Controller Hub">SCHs</a></li> <li><a href="/wiki/I/O_Controller_Hub" title="I/O Controller Hub">ICHs</a></li> <li><a href="/wiki/PCI_IDE_ISA_Xcelerator" class="mw-redirect" title="PCI IDE ISA Xcelerator">PIIXs</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/List_of_Intel_codenames" title="List of Intel codenames">Codenames</a></li> <li><a href="/wiki/Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></li></ul> 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