TY - JFULL AU - N. Shen and T. T. Le and H. Y. Yu and Z. X. Chen and K. T. Win and N. Singh and G. Q. Lo and D. -L. Kwong PY - 2011/10/ TI - Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor T2 - International Journal of Materials and Metallurgical Engineering SP - 797 EP - 800 VL - 5 SN - 1307-6892 UR - https://publications.waset.org/pdf/4635 PU - World Academy of Science, Engineering and Technology NX - Open Science Index 57, 2011 N2 - In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm. ER -