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h8s – coreboot
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href="https://blogs.coreboot.org/blog/tag/subversion/" class="tag-cloud-link tag-link-4170 tag-link-position-33" style="font-size: 8pt;" aria-label="subversion (1 item)">subversion</a></li> <li><a href="https://blogs.coreboot.org/blog/tag/svn/" class="tag-cloud-link tag-link-4169 tag-link-position-34" style="font-size: 8pt;" aria-label="svn (1 item)">svn</a></li> <li><a href="https://blogs.coreboot.org/blog/tag/thinker/" class="tag-cloud-link tag-link-4186 tag-link-position-35" style="font-size: 8pt;" aria-label="thinker (1 item)">thinker</a></li> <li><a href="https://blogs.coreboot.org/blog/tag/u-boot/" class="tag-cloud-link tag-link-4172 tag-link-position-36" style="font-size: 8pt;" aria-label="U-boot (1 item)">U-boot</a></li> <li><a href="https://blogs.coreboot.org/blog/tag/uefi/" class="tag-cloud-link tag-link-4188 tag-link-position-37" style="font-size: 9.6912751677852pt;" aria-label="UEFI (2 items)">UEFI</a></li> <li><a href="https://blogs.coreboot.org/blog/tag/usb/" class="tag-cloud-link tag-link-16 tag-link-position-38" style="font-size: 8pt;" aria-label="USB (1 item)">USB</a></li> </ul> </div> </nav></aside> </div><!-- .widget-area --> </div><!-- .secondary --> </div><!-- .sidebar --> <div id="content" class="site-content"> <section id="primary" class="content-area"> <main id="main" class="site-main"> <header class="page-header"> <h1 class="page-title">Tag: <span>h8s</span></h1> </header><!-- .page-header --> <article id="post-3890" class="post-3890 post type-post status-publish format-standard hentry category-coreboot category-gsoc category-logic-analyzer tag-ec tag-gsoc tag-gsoc2015 tag-h8s"> <header class="entry-header"> <h2 class="entry-title"><a href="https://blogs.coreboot.org/blog/2015/07/29/gsoc-ech8s-firmware-week-78/" rel="bookmark">[GSoC] EC/H8S firmware week #7|#8</a></h2> </header><!-- .entry-header --> <div class="entry-content"> <p>Week #7 was is little bit frustrating, because of no real progress, only more聽unfinished things which aren’t working. Week #8聽was a lot better.</p> <p><strong>1. Sniffing the communication between the 2 embedded controllers H8S and PMH4.</strong></p> <p>I’ve tried to build an protocol analyser with the msp430, but the data output was somehow strange. For testing purpose I used my H8S firmware to produce testing data. But the msp430 decoded only wrong data. I’m using IRQs on the clock to do the magic and writing it to a buffer before transmitting it via UART.聽Maybe the msp430 is too slow for that? Possible. Set a GPIO to high聽when the IRQ routing start and to low when it ends. Visualize the clock signal and connect聽the 聽IRQ measure pin to an oscilloscope. The msp430 is far too slow. I’m using memory dereference in the IRQ routine, which takes a lot of聽time.聽Maybe the msp430 is fast enough, when using asm routine and registers to buffer the 3 byte transmission. But a logic analyser would definitely work. So I borrowed two logic analyser. An OLS聽(Openbench Logic Sniffer) and a Saleae Logic16.</p> <p>There isn’t so much聽data on the聽lines. Every 50聽ms there is a short transmission of 3 byte. But I don’t want to decode the data by hand. So it needs a聽decoder for the logic analyser. sigrok looks like the best start point and both analyser are supported.</p> <p>I’ve started with the Openbench Logic Sniffer, but unfortunately it doesn’t have enough RAM to buffer the input long enough.聽Maybe the external trigger input can be used.聽But before doing additional things I would like to test with the Logic16.</p> <p>The Logic16 doesn’t support any triggers but it can stream all data over USB聽even with multiple MHz. Good enough to capture all data. I found聽out that the best samplerate聽is 2 MHz. Otherwise the LE signal isn’t captured, because it’s a lot shorter than a clock change. In the end I created聽a decoder with libsigrokdecode.</p> <p><em>sigrok-cli -i boots_and_shutdown_later_because_too_hot.sr –channels 0-3 -P ec_xp:clk=2:data=3:le=1:oe=0 | uniq -c聽</em></p> <p style="padding-left: 30px"><em>67 0x01 0x07 0xc8 </em><br /> <em>3 0x01 0x04 0xc8聽</em><br /> <em> 4 0x01 0x10 0x48 </em><br /> <em> 1120 0x01 0x17 0x48 </em><br /> <em> 67 0x01 0x07 0xc8 </em></p> <p>0x01 0x07 0xc8 is called when only power is plugged in, like a watchdog(every 500ms)<br /> 0x01 0x17 0x48 is called when the device is powered on, like a watchdog (every 50ms)<br /> 0x01 0x04 0xc8聽around聽the time power button pressed<br /> 0x01 0x10 0x48 around the time power button pressed</p> <p><strong>2. Flash back the OEM H8S firmare</strong></p> <p>The OEM H8S firmware is included in the bios updates. <em>cabextract</em> and <em>strings</em> is enough for extracting it out of the update.聽Look for SREC lines. Put the SREC lines into a separate file and flash them back via UART bootloader and the renesas flash tool. The display聽powers up聽and it’s聽booting again with OEM BIOS.<br /> I could imagine they聽are using a similar update method like the聽UART聽bootloader. First transfer a flasher application into RAM and afterwards communicate with the flasher to transfer the new firmware, but the communication works over LPC instead of UART.</p> <p><strong>3. Progress on the bootloader</strong></p> <p>I’ve implemented the ADC converter to enable the speaker聽amp and the display backlight brightness.</p> <p>Written down LPC registers and just enable the Interface in order to get <a href="https://en.wikipedia.org/wiki/A20_line" target="_blank">GateA20</a> working. Still unclear how far this works.</p> <p><strong>4. How聽to break into聽the bootloader?</strong></p> <p>The idea of the bootloader is聽providing a brick free environment for further development. The bootloader loads the application which adds full support for everything. It should be possible to stop the loading application and flash a new application into the EC flash.聽When starting development on the x60 or x201 I want to use I2C line as debug interface. I2C chips have a big聽footstep and are easy to access. But there must be a way to abort the loading. I will use the function key in combination with the leds.</p> <ol> <li>Remove the battery and power plug.</li> <li>Press the function key</li> <li>Put the power plug in</li> <li>Wait until leds blinking</li> <li>release the function key within 5 seconds after the leds starting to blink to enter the bootloader.</li> </ol> <p>The H8S will become I2C slave on a specific address.</p> <p><strong>What next?</strong></p> <ul> <li>Add new PMH4聽commands to the H8S</li> <li>solder additional pins to MAINOFF PWRSW_H8聽A20 KBRC</li> <li>use the logic analyser to put the communication in relation with these signals</li> <li>UART shell</li> <li>I2C master & client</li> <li>solder聽LPC pins to analyse firmware update process</li> <li>test T40 board with new PMH4 commands and look if all power rails are on</li> </ul> </div><!-- .entry-content --> <footer class="entry-footer"> <span class="posted-on"><span class="screen-reader-text">Posted on </span><a href="https://blogs.coreboot.org/blog/2015/07/29/gsoc-ech8s-firmware-week-78/" rel="bookmark"><time class="entry-date published updated" datetime="2015-07-29T01:25:38+00:00">July 29, 2015</time></a></span><span class="byline"><span class="author vcard"><span class="screen-reader-text">Author </span><a class="url fn n" href="https://blogs.coreboot.org/blog/author/lynxis/">Alex Couzens</a></span></span><span class="cat-links"><span class="screen-reader-text">Categories </span><a href="https://blogs.coreboot.org/blog/category/coreboot/" rel="category tag">coreboot</a>, <a href="https://blogs.coreboot.org/blog/category/gsoc/" rel="category tag">GSoC</a>, <a href="https://blogs.coreboot.org/blog/category/logic-analyzer/" rel="category tag">logic analyzer</a></span><span class="tags-links"><span class="screen-reader-text">Tags </span><a href="https://blogs.coreboot.org/blog/tag/ec/" rel="tag">ec</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc/" rel="tag">GSoC</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc2015/" rel="tag">GSoC2015</a>, <a href="https://blogs.coreboot.org/blog/tag/h8s/" rel="tag">h8s</a></span><span class="comments-link"><a href="https://blogs.coreboot.org/blog/2015/07/29/gsoc-ech8s-firmware-week-78/#comments">1 Comment<span class="screen-reader-text"> on [GSoC] EC/H8S firmware week #7|#8</span></a></span> </footer><!-- .entry-footer --> </article><!-- #post-3890 --> <article id="post-3853" class="post-3853 post type-post status-publish format-standard hentry category-coreboot category-gsoc tag-ec tag-gsoc tag-gsoc2015 tag-h8s tag-pmh4 tag-pmh7 tag-thinker"> <header class="entry-header"> <h2 class="entry-title"><a href="https://blogs.coreboot.org/blog/2015/07/13/gsoc-ech8s-firmware-week-6/" rel="bookmark">[GSoC] EC/H8S firmware week #6</a></h2> </header><!-- .entry-header --> <div class="entry-content"> <p>This week I looked at the communication between the EC H8S and the PMH4. The PMH4 (likely power management hub) is an ASIC which takes care of the power control. It controls who get’s power and who not. It聽doesn’t do any high level work, more like a big logic gatter. The PMH4 has inputs from several power good pins from different power rails and chips. On the output side it controls some power rails. It can also reset the H8S. The PMH4 also knows over some pins in which power聽state (ACPI S0,S4,S5) the board is.聽It doesn’t do any high level work. It’s more like a big logic gatter. There are no ADC on any power lines.</p> <p>The PMH4 is connected to the H8S via 4 Pins. ~OE LE DATA CLK.</p> <p><a href="https://blogs.coreboot.org/files/2015/07/pmh4_connector_t40.jpg"><img fetchpriority="high" decoding="async" class="alignnone size-medium wp-image-3858" src="https://blogs.coreboot.org/files/2015/07/pmh4_connector_t40-300x169.jpg" alt="gsoc 2015 pmh4 connector t40" width="300" height="169" srcset="https://blogs.coreboot.org/files/2015/07/pmh4_connector_t40-300x169.jpg 300w, https://blogs.coreboot.org/files/2015/07/pmh4_connector_t40-1024x577.jpg 1024w" sizes="(max-width: 300px) 100vw, 300px" /></a></p> <p>I connected a buspirate in SPI sniffer mode to debug the protocol. But the output looked a little bit strange. There was no data from the PMH4 to H8S (MISO) and the data comes in burst. To get more knowledge on the protocol I used a digital oscilloscope.</p> <p><a href="https://own.fe80.eu/index.php/s/w7uLLz7Qh1AvLHs" target="_blank">pmh4 oscilloscope</a></p> <p>The protocol doesn’t look like聽SPI. LE聽get’s low after every transmission, ~OE is just high, clock and data just transfer the data. Sometimes when the H8S gets an interupt the Clock pause for some time and continues with the data afterwards. The clock聽is around ~400kHz.</p> <p>I confirmed the protocol via the oscilloscope, but still I don’t get any sign from the board. No fan, nothing else. There must be more than this single transmisison. Maybe the board is to much damaged.聽My modified board was already broken when I got it. There is a聽loose connection related to the cardbus. Maybe this is my problem I don’t know.</p> <p>I’ve two board with two connectors for the PMH4 here. Why not using the OEM one as starter help for the other one?</p> <p><a href="https://own.fe80.eu/index.php/s/1WPi7P3AIKBS7b7" target="_blank">t42 gives some starting help</a></p> <p>I think the PMH4 does what it should do. The H8S has an digital-analog-converter pin connected to the video聽brightness. But I haven’t implemented it yet. But I don’t think the device booted, because neither the CPU nor the chipset produce any heat. Ok, maybe it does, I only used my finger as thermometer.聽A thermal camera would help here.聽I’ll borrow a thermal camera for that.</p> <p>There are lot of pins which I ignore atm. E.g.聽A20 pin. Is there聽something to do in a specific time serie?</p> <p><strong>What’s next?</strong></p> <ul> <li>build a small protocol sniffer for the PMH4 XP using a msp430 or stellaris arm</li> <li>make progress on the bootloader</li> <li>find a way to聽flash back the OEM H8S firmware</li> <li>find a way to flash my bootloader聽via OEM flash tools</li> </ul> <p>My requirements to the bootloader are</p> <ul> <li>UART flashing via XMODEM</li> <li>a simple UART shell</li> <li>I2C as recovery and shell as well</li> </ul> <p>I2C pins are a lot easier to find and modify than the H8S UART.聽I’m not yet聽sure if the H8S should be the master or the slave and on what address he should聽use? Multiple? UART tx is working. Rx聽is聽a task to do.</p> <p><strong>PMH4 / PMH7 / Thinker communication</strong></p> <p>On newer board the PMH interfaces changed (>= x60, t60, …). They merge the LPC interface and the聽XP interface into an protocol over聽SPI. And the聽new PMH is used as GPIO expander as well.</p> <p><a href="https://blogs.coreboot.org/files/2015/07/pmh4_pmh7_thinker_communication.png"><img decoding="async" class="alignnone size-medium wp-image-3859" src="https://blogs.coreboot.org/files/2015/07/pmh4_pmh7_thinker_communication-232x300.png" alt="pmh4 pmh7 thinker communication" width="232" height="300" srcset="https://blogs.coreboot.org/files/2015/07/pmh4_pmh7_thinker_communication-232x300.png 232w, https://blogs.coreboot.org/files/2015/07/pmh4_pmh7_thinker_communication-791x1024.png 791w, https://blogs.coreboot.org/files/2015/07/pmh4_pmh7_thinker_communication.png 850w" sizes="(max-width: 232px) 100vw, 232px" /></a></p> <p> </p> </div><!-- .entry-content --> <footer class="entry-footer"> <span class="posted-on"><span class="screen-reader-text">Posted on </span><a href="https://blogs.coreboot.org/blog/2015/07/13/gsoc-ech8s-firmware-week-6/" rel="bookmark"><time class="entry-date published updated" datetime="2015-07-13T20:32:02+00:00">July 13, 2015</time></a></span><span class="byline"><span class="author vcard"><span class="screen-reader-text">Author </span><a class="url fn n" href="https://blogs.coreboot.org/blog/author/lynxis/">Alex Couzens</a></span></span><span class="cat-links"><span class="screen-reader-text">Categories </span><a href="https://blogs.coreboot.org/blog/category/coreboot/" rel="category tag">coreboot</a>, <a href="https://blogs.coreboot.org/blog/category/gsoc/" rel="category tag">GSoC</a></span><span class="tags-links"><span class="screen-reader-text">Tags </span><a href="https://blogs.coreboot.org/blog/tag/ec/" rel="tag">ec</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc/" rel="tag">GSoC</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc2015/" rel="tag">GSoC2015</a>, <a href="https://blogs.coreboot.org/blog/tag/h8s/" rel="tag">h8s</a>, <a href="https://blogs.coreboot.org/blog/tag/pmh4/" rel="tag">pmh4</a>, <a href="https://blogs.coreboot.org/blog/tag/pmh7/" rel="tag">pmh7</a>, <a href="https://blogs.coreboot.org/blog/tag/thinker/" rel="tag">thinker</a></span> </footer><!-- .entry-footer --> </article><!-- #post-3853 --> <article id="post-3821" class="post-3821 post type-post status-publish format-standard hentry category-coreboot category-gsoc tag-coreboot tag-ec tag-gsoc tag-gsoc2015 tag-h8s"> <header class="entry-header"> <h2 class="entry-title"><a href="https://blogs.coreboot.org/blog/2015/07/06/gsoc-ech8s-firmware-week-5/" rel="bookmark">[GSoC] EC/H8S firmware week #5</a></h2> </header><!-- .entry-header --> <div class="entry-content"> <p>The T40 is <a href="https://own.fe80.eu/index.php/s/V8bzLGTxYDjnzp0" target="_blank">flashing leds</a>! The toolchain is still a little bit tricky. I’m using the debian package <a href="https://packages.debian.org/jessie/gcc-h8300-hms" target="_blank">gcc-h8300-hms</a>, written a small linker script and聽took the聽startup assembly routine from <a href="http://www.jogy.ch/files/Circuit_Cellar_Design_Contest_H3210/H3210.zip" target="_blank">Johann Gysin’s led radiator</a>.</p> <p>Now I can flash leds. But what about booting the board? I would say it’s enough to put</p> <ul> <li>(!MAINOFF) = high</li> <li>FAN ON = high</li> <li>pulse high on (!PWRSW_H8)</li> </ul> <p>But聽it’s not enough. Also the FAN isn’t starting to rotate. I’ll try to debug every pin this week and solder聽some debug pins for the 2nd EC (PMHx) to the my modified T40 as well as to an unmodified T42p. The H8S is talking to the PMHx via SPI, while the H8S is the master and is doing bit聽banging SPI in software, because it doesn’t have a hardware unit for that. I’ll also use these pins for testing my SPI implementation. I’ll try to reuse an open source SPI implementation.</p> <p>I also asked me if it’s a good idea to port coreboot for the T40 before聽continuing any efforts to the EC, but it’s a little bit harder, because the T40 uses a LPC/FWH flash in a <a href="https://en.wikipedia.org/wiki/Thin_Small_Outline_Package">TSOP40</a> case. Another option is changing the hardware to a board which is already supported by coreboot like a x60/t60 or x201. But it’s much more harder to access the 8 pins for flashing the EC on these boards.</p> <p>Before switching to another board,聽the powersequencing must work and I need a robust recovery way, because when you kill the EC by flashing a new firmware, you don’t get a second chance, unless you solder a lot. Chrome EC fix this problem by splitting the EC firmware into 2 parts. One read-only part and one read-write’able part. Only the second part gets updated and the read-only part can at least boots the device.</p> <p>Before starting the聽H8S port for Chrome EC I want to have a bootloader. Because it would improve developing speed. I think implement this is much faster than doing the full聽Chrome EC support and most of the bootloader code can be re-used for Chrome EC.</p> <p>I’m also not perfectly sure Chrome EC is the best solution. It’s special use-case is聽EC, which is perfect. But neither the聽documentation (I think there is more than <a href="https://www.chromium.org/chromium-os/ec-development" target="_blank">one page</a>) nor the bugtracker is public. Thus it makes difficult to use. I’m also not sure if Chrome EC would apply my H8S port into their repository.</p> </div><!-- .entry-content --> <footer class="entry-footer"> <span class="posted-on"><span class="screen-reader-text">Posted on </span><a href="https://blogs.coreboot.org/blog/2015/07/06/gsoc-ech8s-firmware-week-5/" rel="bookmark"><time class="entry-date published" datetime="2015-07-06T02:52:01+00:00">July 6, 2015</time><time class="updated" datetime="2015-07-06T02:53:28+00:00">July 6, 2015</time></a></span><span class="byline"><span class="author vcard"><span class="screen-reader-text">Author </span><a class="url fn n" href="https://blogs.coreboot.org/blog/author/lynxis/">Alex Couzens</a></span></span><span class="cat-links"><span class="screen-reader-text">Categories </span><a href="https://blogs.coreboot.org/blog/category/coreboot/" rel="category tag">coreboot</a>, <a href="https://blogs.coreboot.org/blog/category/gsoc/" rel="category tag">GSoC</a></span><span class="tags-links"><span class="screen-reader-text">Tags </span><a href="https://blogs.coreboot.org/blog/tag/coreboot/" rel="tag">coreboot</a>, <a href="https://blogs.coreboot.org/blog/tag/ec/" rel="tag">ec</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc/" rel="tag">GSoC</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc2015/" rel="tag">GSoC2015</a>, <a href="https://blogs.coreboot.org/blog/tag/h8s/" rel="tag">h8s</a></span> </footer><!-- .entry-footer --> </article><!-- #post-3821 --> <article id="post-3811" class="post-3811 post type-post status-publish format-standard hentry category-coreboot category-gsoc tag-ec tag-gsoc tag-gsoc2015 tag-h8s"> <header class="entry-header"> <h2 class="entry-title"><a href="https://blogs.coreboot.org/blog/2015/06/27/gsoc-ech8s-firmware-week-34/" rel="bookmark">[GSoC] EC/H8S firmware week #3|4</a></h2> </header><!-- .entry-header --> <div class="entry-content"> <p>In the last 2 weeks I聽managed to flash the H8S聽on the T40 using the OEM Renesas Flash Tool including their flash application. Flashing works in 2 steps, first upload a flash application聽into the H8S. Second this flash application聽will receive the firmware (via serial) and write it into the flash. Thanks to Renesas this application聽is available in source code.聽I would like to write an own flasher later.</p> <p>But I wasn’t able to create a proper application yet. I could write the led programm聽in assembly, but having a working c聽compile聽is needed anyway.</p> <p>I built a toolchain with gcc 4.9.2. The toolchain buildscript is very simple and can be found on<a href="https://github.com/lynxis/h8300-toolchain-builder" target="_blank">聽github</a>. I stopped my building efforts for now (building one based on gcc 4.4.6). There’s also a debian package for h8300 (based on gcc 3.4.6) which may be a good alternative.聽Before continuing in building toolchains and my led application, I’m聽reading me into linkerscipts and take a look how the compiler is working (e.g. what must a crt0 do?).</p> <p>At the moment I know how the application聽should be compiled, where the reset vectors are and where the entrypoint. But putting these things together into a binary image聽is my task now.</p> <p>The dev board I mentioned in my last post was stuck by the german post for the last 2 weeks, because there were聽on strike. The board is now in the custom office and I’ll collect in the next days, which聽will takes severals hours in Berlin.</p> </div><!-- .entry-content --> <footer class="entry-footer"> <span class="posted-on"><span class="screen-reader-text">Posted on </span><a href="https://blogs.coreboot.org/blog/2015/06/27/gsoc-ech8s-firmware-week-34/" rel="bookmark"><time class="entry-date published updated" datetime="2015-06-27T22:37:25+00:00">June 27, 2015</time></a></span><span class="byline"><span class="author vcard"><span class="screen-reader-text">Author </span><a class="url fn n" href="https://blogs.coreboot.org/blog/author/lynxis/">Alex Couzens</a></span></span><span class="cat-links"><span class="screen-reader-text">Categories </span><a href="https://blogs.coreboot.org/blog/category/coreboot/" rel="category tag">coreboot</a>, <a href="https://blogs.coreboot.org/blog/category/gsoc/" rel="category tag">GSoC</a></span><span class="tags-links"><span class="screen-reader-text">Tags </span><a href="https://blogs.coreboot.org/blog/tag/ec/" rel="tag">ec</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc/" rel="tag">GSoC</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc2015/" rel="tag">GSoC2015</a>, <a href="https://blogs.coreboot.org/blog/tag/h8s/" rel="tag">h8s</a></span> </footer><!-- .entry-footer --> </article><!-- #post-3811 --> <article id="post-3771" class="post-3771 post type-post status-publish format-standard hentry category-coreboot category-gsoc tag-ec tag-gsoc tag-gsoc2015 tag-h8s tag-reproducible"> <header class="entry-header"> <h2 class="entry-title"><a href="https://blogs.coreboot.org/blog/2015/06/10/gsoc-ech8s-firmware-week-2/" rel="bookmark">[GSoC] EC/H8S firmware week #2</a></h2> </header><!-- .entry-header --> <div class="entry-content"> <p>The last聽week was a little bit depressive. I did the some聽resoldering. Pin P90 wasn’t connected to 3.3V which is needed to enter the flash boot mode. It was聽soldered 聽to the VCC of the Serial level shifter MAX3243. After聽searching some minutes with the Multimeter for a better power source, I decieded to聽use 3.3V near the H8S. It’s now a very long cable across the board.</p> <p>Now let’s see, how good this works? Nothing :(. Recheck with a voltmeter and found聽another problem with P91 (/SUS_STAT). When connecting SUS_STAT with an 1k resistor聽to 3.3V the voltmeter shows 0.04V. This means it’s driven by something else to 0V.聽My hope was that the chipset isn’t driving this until it’s powered. But sadly it is driving it to 0V.聽What’s SUS_STAT? SUS_STAT can be used as LPCPD (LPC power down) and is used to notify devices to聽enter a low power state soon. Suspend Status is active low, which means all device should be in low power mode.<br /> What should I do now? I need 3.3V on that line.</p> <p><strong>There are multiple solution:</strong></p> <ul> <li>Remove 1k and burn it to death. But likely this could kill the chipset or<br /> a least this certain pin or multiple pins</li> <li>Cut the pin</li> <li>Bend the pin upwards while desoldering</li> <li>Desolder the whole chip and bend afterwards, resolder</li> <li>Replace the chip with a socket (expensive and rare)</li> </ul> <p>This decision is not easy to take, especially because I never done most<br /> of these things. This got me stuck for a while until Peter helped me out,<br /> he bend a single pin upwards. Thanks!</p> <p>The next week milestone is still flashing the EC, the same goal since the first week. So the time schedule will be a little big chaotic. Maybe I can hurry up and reach another weekly goal fast than a week.</p> <p>Because I was stuck on that a little bit, I took another look on ebay and bought a development board with a H8S/2633. 2633 is a little bit newer than the 2100 series<br /> which is used in Lenovo laptops. The board should arrive in one week, but atm it’s in german customs. Such development boards are hard to get for a “good” price. Brand new boards聽start with聽several hundred euros or聽dollars. E.g. the debugger E10 (USB device) cost聽around 1000 Euro, it’s only a stupid USB device. I already bought on聽ebay an E8, previous generation debugger, but it can not debug the chip, only flash them with the聽Renesas software/IDE.</p> <p>Beside my project I’ve done some other work on coreboot. I helped Holger Levsen on creating a reproducible build job for coreboot on聽<a href="https://reproducible.debian.net/coreboot/coreboot.html" target="_blank">reproducible.debian.net</a>.聽More info about reproducible builds are on their <a href="https://wiki.debian.org/ReproducibleBuilds" target="_blank">wiki page</a>. 聽To improve reproducibility I created 2 patches聽<a href="http://review.coreboot.org/#/c/10448/" target="_blank">#10448</a> <a href="http://review.coreboot.org/#/c/10449/" target="_blank">#10449</a>. They cleaned up聽reproducible bugs in coreboot and without building Payloads, most targets are now reproducible. Great thanks to Holger Levsen for his work on that!</p> </div><!-- .entry-content --> <footer class="entry-footer"> <span class="posted-on"><span class="screen-reader-text">Posted on </span><a href="https://blogs.coreboot.org/blog/2015/06/10/gsoc-ech8s-firmware-week-2/" rel="bookmark"><time class="entry-date published updated" datetime="2015-06-10T21:58:57+00:00">June 10, 2015</time></a></span><span class="byline"><span class="author vcard"><span class="screen-reader-text">Author </span><a class="url fn n" href="https://blogs.coreboot.org/blog/author/lynxis/">Alex Couzens</a></span></span><span class="cat-links"><span class="screen-reader-text">Categories </span><a href="https://blogs.coreboot.org/blog/category/coreboot/" rel="category tag">coreboot</a>, <a href="https://blogs.coreboot.org/blog/category/gsoc/" rel="category tag">GSoC</a></span><span class="tags-links"><span class="screen-reader-text">Tags </span><a href="https://blogs.coreboot.org/blog/tag/ec/" rel="tag">ec</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc/" rel="tag">GSoC</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc2015/" rel="tag">GSoC2015</a>, <a href="https://blogs.coreboot.org/blog/tag/h8s/" rel="tag">h8s</a>, <a href="https://blogs.coreboot.org/blog/tag/reproducible/" rel="tag">reproducible</a></span> </footer><!-- .entry-footer --> </article><!-- #post-3771 --> <article id="post-3749" class="post-3749 post type-post status-publish format-standard hentry category-coreboot category-gsoc tag-ec tag-gsoc tag-gsoc2015 tag-h8s"> <header class="entry-header"> <h2 class="entry-title"><a href="https://blogs.coreboot.org/blog/2015/05/28/progress-gsoc-week-1/" rel="bookmark">[GSoC] EC/H8S firmware week #1</a></h2> </header><!-- .entry-header --> <div class="entry-content"> <p>The first task of my project is a working development board. A development board means that I have聽serial communication and I can flash new firmwares the chip and whole mainboard isn’t booting. The chip is a聽H8S 16-bit microcontroller with 64kb to 128kb EEPROM and is available in different packages.聽BGA and TQFP. BGA means the pins are under the chip, TQFP has pins on the side. TQFP is nice to hack,聽but most modern Thinkpads use the BGAs. But a T40 or T42 use a TQFP package.聽A friend donated his old T42 to me! Thanks a lot! Now with a hackable T42 I can start to create a development board聽out of the T42 mainboard. Like most other microcontroller this chip has a programmable bootloader in a ROM (called rom loader).聽The bootloader can boot to different states, configurable via 5 pins (MD0聽MD1 P90 P91 P92).<br /> P90 to P92 are only read when MD0 and MD1 are in a special bootstate.<br /> After reading the documentation I found that the pins must match the following volatage levels to select the flash boot mode:</p> <p>MD0-MD1 = 0V, P90-P92 = 3.3V.</p> <p>Besides these configuration pins we need some additional wires to the following pins:<br /> /RES – reset active low<br /> UART RX – serial communication<br /> UART TX –</p> <p>Now it gets interesting. The MCU (microcontroller unit) can use a pin for different purposes聽depending on the PCB designer. Those pins called multifunction pins. Hopefully we don’t get blocked by unaccessible聽pins. After reading more documentation and using a Multimeter on the board I found out that聽/RES, RX, TX, MD1 require soldering, but are easy accessible. MD0 is already in a good state.<br /> P90 is connected via a resistor to ground, but we need it to 3.3V.<br /> Let’s find the resistor to solder 3.3V to it… Mhh. tricky! 3h later I found it on the<br /> board hidden under the PMH4 (2nd EC/GPIO expander). Very uncommon.</p> <p>P91 is named /SUS. Suspended active low, but can be driven by multiple controllers (chipset + h8s).<br /> Because we want to boot linux on the main cpu later in the project we should not kill the chipset.聽I added a pin connector to this pin.</p> <p>And the last pin P92 was connected to the SuperIO UART’s level shifter (MAX3242). I had聽to desolder the chip because P92 was driven by the level shifter.</p> <p>Near the EC are 2 testpoints which are connected to an I2C bus. I soldered these too, because聽an I2C could be useful.</p> <p>1 P91<br /> 2 GND<br /> 3 md1<br /> 4 /RESET<br /> 5 RX<br /> 6 TX<br /> 7 I2C SDA<br /> 8 I2C SCL<br /> +<br /> 1 patch cable with a 3.3V + 1k Resistor (for P91).</p> <p>So far so good. But somehow it doesn’t work. Some pins doesn’t have the right level. P92 doesnt have 3.3V. Why not?<br /> P92 is pulled up via a resistor to VCC of the TTL shifter. The VCC isn’t powered. I need to resolder it to another 3.3V pin somewhere and take another look<br /> on the other levels too.</p> <p>PS. Some work was already done before GSoC started. I posted the first part of soldering on <a href="http://lunarius.fe80.eu/blog/coreboot-t40-ec-soldering.html">my blog</a></p> </div><!-- .entry-content --> <footer class="entry-footer"> <span class="posted-on"><span class="screen-reader-text">Posted on </span><a href="https://blogs.coreboot.org/blog/2015/05/28/progress-gsoc-week-1/" rel="bookmark"><time class="entry-date published" datetime="2015-05-28T23:17:07+00:00">May 28, 2015</time><time class="updated" datetime="2015-06-03T20:29:26+00:00">June 3, 2015</time></a></span><span class="byline"><span class="author vcard"><span class="screen-reader-text">Author </span><a class="url fn n" href="https://blogs.coreboot.org/blog/author/lynxis/">Alex Couzens</a></span></span><span class="cat-links"><span class="screen-reader-text">Categories </span><a href="https://blogs.coreboot.org/blog/category/coreboot/" rel="category tag">coreboot</a>, <a href="https://blogs.coreboot.org/blog/category/gsoc/" rel="category tag">GSoC</a></span><span class="tags-links"><span class="screen-reader-text">Tags </span><a href="https://blogs.coreboot.org/blog/tag/ec/" rel="tag">ec</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc/" rel="tag">GSoC</a>, <a href="https://blogs.coreboot.org/blog/tag/gsoc2015/" rel="tag">GSoC2015</a>, <a href="https://blogs.coreboot.org/blog/tag/h8s/" rel="tag">h8s</a></span> </footer><!-- .entry-footer --> </article><!-- #post-3749 --> </main><!-- .site-main --> </section><!-- .content-area --> </div><!-- .site-content --> <footer id="colophon" class="site-footer" role="contentinfo"> <div class="site-info"> <a href="https://wordpress.org/">Proudly powered by WordPress</a> </div><!-- .site-info --> </footer><!-- .site-footer --> </div><!-- .site --> </body> </html>