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taxonomy-description"><h1 class="archive-title">FAQ</h1></div><article class="post-8092 post type-post status-publish format-standard has-post-thumbnail category-faq category-featured tag-faq entry" aria-label="What specifications are needed for card edge connectors in AI/ML systems?"><header class="entry-header"><h2 class="entry-title"><a class="entry-title-link" rel="bookmark" href="https://www.connectortips.com/specifications-needed-card-edge-connectors-ai-ml-systems/">What specifications are needed for card edge connectors in AI/ML systems?</a></h2> <p class="entry-meta"><time class="entry-time">July 3, 2024</time> By <span class="entry-author"><a href="https://www.connectortips.com/author/jeff-shepard/" class="entry-author-link" rel="author"><span class="entry-author-name">Jeff Shepard</span></a></span> <span class="entry-comments-link"><a href="https://www.connectortips.com/specifications-needed-card-edge-connectors-ai-ml-systems/#respond">Leave a Comment</a></span> </p></header><div class="entry-content"><a class="entry-image-link" href="https://www.connectortips.com/specifications-needed-card-edge-connectors-ai-ml-systems/" aria-hidden="true" tabindex="-1"><img width="150" height="150" src="https://www.connectortips.com/wp-content/uploads/2024/06/What-specifications-are-needed-for-card-edge-connectors-in-AI-ML-systems-Figure-3crop-150x150.jpg" class="alignleft post-image entry-image" alt="" decoding="async" /></a><p>Card edge connectors connect peripheral devices or expansion cards to a host system. They provide a reliable interface for data transfer and power delivery, facilitating the integration of artificial intelligence (AI) components into a system. They support AI and machine learning (ML) on the edge, in the cloud, and in hyperscale data centers. This article […]</p> </div><footer class="entry-footer"><p class="entry-meta"><span class="entry-categories">Filed Under: <a href="https://www.connectortips.com/category/faq/" rel="category tag">FAQ</a>, <a href="https://www.connectortips.com/category/featured/" rel="category tag">Featured</a></span> <span class="entry-tags">Tagged With: <a href="https://www.connectortips.com/tag/faq/" rel="tag">faq</a></span></p></footer></article><article class="post-8088 post type-post status-publish format-standard has-post-thumbnail category-faq category-featured tag-1-6-tbps-ethernet tag-224-gbps-pam-4-technology tag-ai-ml-data-centers tag-faq tag-high-speed-interconnects entry" aria-label="How do 224 G connectors support AI/ML training in hyperscale data centers?"><header class="entry-header"><h2 class="entry-title"><a class="entry-title-link" rel="bookmark" href="https://www.connectortips.com/how-do-224-g-connectors-support-ai-ml-training-in-hyperscale-data-centers/">How do 224 G connectors support AI/ML training in hyperscale data centers?</a></h2> <p class="entry-meta"><time class="entry-time">June 26, 2024</time> By <span class="entry-author"><a href="https://www.connectortips.com/author/jeff-shepard/" class="entry-author-link" rel="author"><span class="entry-author-name">Jeff Shepard</span></a></span> <span class="entry-comments-link"><a href="https://www.connectortips.com/how-do-224-g-connectors-support-ai-ml-training-in-hyperscale-data-centers/#respond">Leave a Comment</a></span> </p></header><div class="entry-content"><a class="entry-image-link" href="https://www.connectortips.com/how-do-224-g-connectors-support-ai-ml-training-in-hyperscale-data-centers/" aria-hidden="true" tabindex="-1"><img width="150" height="150" src="https://www.connectortips.com/wp-content/uploads/2024/06/How-do-224-G-connectors-support-AI-ML-training-in-hyperscale-data-centers-Figure-2-1-150x150.jpg" class="alignleft post-image entry-image" alt="" decoding="async" loading="lazy" /></a><p>224 Gigabits per second (Gbps) pulse-amplitude modulation 4-level (PAM 4) technology is foundational for the hyperscale data centers needed for artificial intelligence (AI) and machine learning (ML) training and implementation. This article begins by examining the multiple uses of 224 G connectivity in servers and storage devices. It then considers how multiple 224 G lanes […]</p> </div><footer class="entry-footer"><p class="entry-meta"><span class="entry-categories">Filed Under: <a href="https://www.connectortips.com/category/faq/" rel="category tag">FAQ</a>, <a href="https://www.connectortips.com/category/featured/" rel="category tag">Featured</a></span> <span class="entry-tags">Tagged With: <a href="https://www.connectortips.com/tag/1-6-tbps-ethernet/" rel="tag">1.6 Tbps Ethernet</a>, <a href="https://www.connectortips.com/tag/224-gbps-pam-4-technology/" rel="tag">224 Gbps PAM 4 Technology</a>, <a href="https://www.connectortips.com/tag/ai-ml-data-centers/" rel="tag">AI/ML Data Centers</a>, <a href="https://www.connectortips.com/tag/faq/" rel="tag">faq</a>, <a href="https://www.connectortips.com/tag/high-speed-interconnects/" rel="tag">High-Speed Interconnects</a></span></p></footer></article><article class="post-8066 post type-post status-publish format-standard has-post-thumbnail category-faq category-featured tag-faq entry" aria-label="What interconnects are used with memory for HPC and AI?"><header class="entry-header"><h2 class="entry-title"><a class="entry-title-link" rel="bookmark" href="https://www.connectortips.com/what-interconnects-are-used-with-memory-for-hpc-and-ai/">What interconnects are used with memory for HPC and AI?</a></h2> <p class="entry-meta"><time class="entry-time">June 19, 2024</time> By <span class="entry-author"><a href="https://www.connectortips.com/author/jeff-shepard/" class="entry-author-link" rel="author"><span class="entry-author-name">Jeff Shepard</span></a></span> <span class="entry-comments-link"><a href="https://www.connectortips.com/what-interconnects-are-used-with-memory-for-hpc-and-ai/#respond">Leave a Comment</a></span> </p></header><div class="entry-content"><a class="entry-image-link" href="https://www.connectortips.com/what-interconnects-are-used-with-memory-for-hpc-and-ai/" aria-hidden="true" tabindex="-1"><img width="150" height="150" src="https://www.connectortips.com/wp-content/uploads/2024/06/What-interconnects-are-used-with-memory-for-HPC-and-AI-Figure-1-1-150x150.jpg" class="alignleft post-image entry-image" alt="" decoding="async" loading="lazy" /></a><p>High-performance computing (HPC) for artificial intelligence (AI) applications places extreme demands on memory connectors. They must deliver high-speed connectivity, high levels of signal integrity (SI), and support high-density solutions. This article reviews connector needs for Peripheral Component Interconnect Express 6.0 (PCIe 6.0), Serial Attached SCSI (SAS) including SAS 3.0, 4.0 and SAS/PCIe 5.0, and Data […]</p> </div><footer class="entry-footer"><p class="entry-meta"><span class="entry-categories">Filed Under: <a href="https://www.connectortips.com/category/faq/" rel="category tag">FAQ</a>, <a href="https://www.connectortips.com/category/featured/" rel="category tag">Featured</a></span> <span class="entry-tags">Tagged With: <a href="https://www.connectortips.com/tag/faq/" rel="tag">faq</a></span></p></footer></article><article class="post-8060 post type-post status-publish format-standard has-post-thumbnail category-faq category-featured tag-faq entry" aria-label="How are high-speed board-to-board connectors used in ML and AI systems?"><header class="entry-header"><h2 class="entry-title"><a class="entry-title-link" rel="bookmark" href="https://www.connectortips.com/how-are-high-speed-board-to-board-connectors-used-in-ml-and-ai-systems/">How are high-speed board-to-board connectors used in ML and AI systems?</a></h2> <p class="entry-meta"><time class="entry-time">June 12, 2024</time> By <span class="entry-author"><a href="https://www.connectortips.com/author/jeff-shepard/" class="entry-author-link" rel="author"><span class="entry-author-name">Jeff Shepard</span></a></span> <span class="entry-comments-link"><a href="https://www.connectortips.com/how-are-high-speed-board-to-board-connectors-used-in-ml-and-ai-systems/#respond">Leave a Comment</a></span> </p></header><div class="entry-content"><a class="entry-image-link" href="https://www.connectortips.com/how-are-high-speed-board-to-board-connectors-used-in-ml-and-ai-systems/" aria-hidden="true" tabindex="-1"><img width="150" height="150" src="https://www.connectortips.com/wp-content/uploads/2024/06/How-are-high-speed-board-to-board-connectors-used-in-ML-and-AI-systems-Figure-2-1-150x150.jpg" class="alignleft post-image entry-image" alt="" decoding="async" loading="lazy" /></a><p>High-speed board-to-board connectivity is evolving to meet the increasing performance demands and need for scalability of machine learning (ML) and artificial intelligence (AI) systems. The basic PCIe connectors and Card Electromechanical (CEM) form factor are still widely used to support scalability and high performance, but there are also new contenders. This article reviews the basics […]</p> </div><footer class="entry-footer"><p class="entry-meta"><span class="entry-categories">Filed Under: <a href="https://www.connectortips.com/category/faq/" rel="category tag">FAQ</a>, <a href="https://www.connectortips.com/category/featured/" rel="category tag">Featured</a></span> <span class="entry-tags">Tagged With: <a href="https://www.connectortips.com/tag/faq/" rel="tag">faq</a></span></p></footer></article><article class="post-8048 post type-post status-publish format-standard has-post-thumbnail category-faq category-featured tag-faq entry" aria-label="What multidrop SPE architectures are there to choose from?"><header class="entry-header"><h2 class="entry-title"><a class="entry-title-link" rel="bookmark" href="https://www.connectortips.com/what-multidrop-spe-architectures-are-there-to-choose-from/">What multidrop SPE architectures are there to choose from?</a></h2> <p class="entry-meta"><time class="entry-time">June 5, 2024</time> By <span class="entry-author"><a href="https://www.connectortips.com/author/jeff-shepard/" class="entry-author-link" rel="author"><span class="entry-author-name">Jeff Shepard</span></a></span> <span class="entry-comments-link"><a href="https://www.connectortips.com/what-multidrop-spe-architectures-are-there-to-choose-from/#respond">Leave a Comment</a></span> </p></header><div class="entry-content"><a class="entry-image-link" href="https://www.connectortips.com/what-multidrop-spe-architectures-are-there-to-choose-from/" aria-hidden="true" tabindex="-1"><img width="150" height="150" src="https://www.connectortips.com/wp-content/uploads/2024/05/What-multidrop-SPE-architectures-are-there-Figure-1-1-150x150.jpg" class="alignleft post-image entry-image" alt="" decoding="async" loading="lazy" /></a><p>The IEEE 802.3 single-pair Ethernet (SPE) standards include multidrop and daisy-chain architectures that support applications like automotive, industrial, and smart buildings. In addition, a range of SPE connector standards are available with several environmental classifications and ratings based on mechanical, ingress, climatic/chemical, and electromagnetic (M.I.C.E) attributes. Automotive systems are a key target for SPE deployment. […]</p> </div><footer class="entry-footer"><p class="entry-meta"><span class="entry-categories">Filed Under: <a href="https://www.connectortips.com/category/faq/" rel="category tag">FAQ</a>, <a href="https://www.connectortips.com/category/featured/" rel="category tag">Featured</a></span> <span class="entry-tags">Tagged With: <a href="https://www.connectortips.com/tag/faq/" rel="tag">faq</a></span></p></footer></article><article class="post-8035 post type-post status-publish format-standard has-post-thumbnail category-ee-sync category-ethernet category-faq category-featured tag-faq entry" aria-label="What are the performance requirements for multidrop SPE connectivity?"><header class="entry-header"><h2 class="entry-title"><a class="entry-title-link" rel="bookmark" href="https://www.connectortips.com/what-are-the-performance-requirements-for-multidrop-spe-connectivity/">What are the performance requirements for multidrop SPE connectivity?</a></h2> <p class="entry-meta"><time class="entry-time">May 31, 2024</time> By <span class="entry-author"><a href="https://www.connectortips.com/author/jeff-shepard/" class="entry-author-link" rel="author"><span class="entry-author-name">Jeff Shepard</span></a></span> <span class="entry-comments-link"><a href="https://www.connectortips.com/what-are-the-performance-requirements-for-multidrop-spe-connectivity/#respond">Leave a Comment</a></span> </p></header><div class="entry-content"><a class="entry-image-link" href="https://www.connectortips.com/what-are-the-performance-requirements-for-multidrop-spe-connectivity/" aria-hidden="true" tabindex="-1"><img width="150" height="150" src="https://www.connectortips.com/wp-content/uploads/2024/05/What-are-the-performance-requirements-for-multidrop-SPE-connectivity-Figure-1-1-150x150.jpg" class="alignleft post-image entry-image" alt="" decoding="async" loading="lazy" /></a><p>Specifications are provided for the insertion loss, return loss, and mode conversion loss in the link and mixing segments of a Single-Pair Ethernet (SPE) network. Connector specifications are also provided for coupling attenuation, impedance, return loss, and dielectric strength. This article begins by briefly examining where multidrop fits in the range of Ethernet connectivity options. […]</p> </div><footer class="entry-footer"><p class="entry-meta"><span class="entry-categories">Filed Under: <a href="https://www.connectortips.com/category/ee-sync/" rel="category tag">EE sync</a>, <a href="https://www.connectortips.com/category/ethernet/" rel="category tag">Ethernet</a>, <a href="https://www.connectortips.com/category/faq/" rel="category tag">FAQ</a>, <a href="https://www.connectortips.com/category/featured/" rel="category tag">Featured</a></span> <span class="entry-tags">Tagged With: <a href="https://www.connectortips.com/tag/faq/" rel="tag">faq</a></span></p></footer></article><article class="post-8030 post type-post status-publish format-standard has-post-thumbnail category-ethernet category-faq category-featured category-markets category-telecomdata tag-faq entry" aria-label="What are the PHY implementations of multidrop SPE?"><header class="entry-header"><h2 class="entry-title"><a class="entry-title-link" rel="bookmark" href="https://www.connectortips.com/what-are-the-phy-implementations-of-multidrop-spe/">What are the PHY implementations of multidrop SPE?</a></h2> <p class="entry-meta"><time class="entry-time">May 29, 2024</time> By <span class="entry-author"><a href="https://www.connectortips.com/author/jeff-shepard/" class="entry-author-link" rel="author"><span class="entry-author-name">Jeff Shepard</span></a></span> <span class="entry-comments-link"><a href="https://www.connectortips.com/what-are-the-phy-implementations-of-multidrop-spe/#respond">Leave a Comment</a></span> </p></header><div class="entry-content"><a class="entry-image-link" href="https://www.connectortips.com/what-are-the-phy-implementations-of-multidrop-spe/" aria-hidden="true" tabindex="-1"><img width="150" height="150" src="https://www.connectortips.com/wp-content/uploads/2024/05/What-are-the-PHY-implementations-of-multidrop-SPE-Figure-2-1-150x150.jpg" class="alignleft post-image entry-image" alt="" decoding="async" loading="lazy" /></a><p>There are three common physical layer (PHY) variants for multidrop Single-Pair Ethernet (SPE), basic PHY, media access controller (MAC) PHY, and transceiver. They rely on different interfaces, including a media-independent interface (MII), reduced media-independent interface (RMII), serial peripheral interface (SPI), OPEN Alliance 3-pin (OA-3P), and Ethernet advanced physical layer (Ethernet-APL). This article begins with a […]</p> </div><footer class="entry-footer"><p class="entry-meta"><span class="entry-categories">Filed Under: <a href="https://www.connectortips.com/category/ethernet/" rel="category tag">Ethernet</a>, <a href="https://www.connectortips.com/category/faq/" rel="category tag">FAQ</a>, <a href="https://www.connectortips.com/category/featured/" rel="category tag">Featured</a>, <a href="https://www.connectortips.com/category/markets/" rel="category tag">Markets</a>, <a href="https://www.connectortips.com/category/markets/telecomdata/" rel="category tag">Telecom/Data</a></span> <span class="entry-tags">Tagged With: <a href="https://www.connectortips.com/tag/faq/" rel="tag">faq</a></span></p></footer></article><article class="post-8017 post type-post status-publish format-standard has-post-thumbnail category-ethernet category-faq category-featured tag-faq entry" aria-label="What are the (almost) nine IEEE Single-Pair Ethernet standards?"><header class="entry-header"><h2 class="entry-title"><a class="entry-title-link" rel="bookmark" href="https://www.connectortips.com/what-are-the-almost-nine-ieee-single-pair-ethernet-standards/">What are the (almost) nine IEEE Single-Pair Ethernet standards?</a></h2> <p class="entry-meta"><time class="entry-time">May 24, 2024</time> By <span class="entry-author"><a href="https://www.connectortips.com/author/jeff-shepard/" class="entry-author-link" rel="author"><span class="entry-author-name">Jeff Shepard</span></a></span> <span class="entry-comments-link"><a href="https://www.connectortips.com/what-are-the-almost-nine-ieee-single-pair-ethernet-standards/#respond">Leave a Comment</a></span> </p></header><div class="entry-content"><a class="entry-image-link" href="https://www.connectortips.com/what-are-the-almost-nine-ieee-single-pair-ethernet-standards/" aria-hidden="true" tabindex="-1"><img width="150" height="150" src="https://www.connectortips.com/wp-content/uploads/2024/05/What-are-the-almost-nine-IEEE-single-pair-Ethernet-standards-Figure-1-1-150x150.jpg" class="alignleft post-image entry-image" alt="" decoding="async" loading="lazy" /></a><p>Eight IEEE Single-Pair Ethernet (SPE) standards exist, with a ninth expected to be announced next year. Current standards include 802.3bw (100BASE-T1), two types of 802.3bp (1000BASE-T1), 802.3ch (10BASE-T1) optimized for automated environments, three versions of 802.3cg (10BASE-T1S, 10BASE-T1L, and 10BASE-T1M), and the 802.3da single-pair multidrop segments enhancement standard that was approved in 2023. This article […]</p> </div><footer class="entry-footer"><p class="entry-meta"><span class="entry-categories">Filed Under: <a href="https://www.connectortips.com/category/ethernet/" rel="category tag">Ethernet</a>, <a href="https://www.connectortips.com/category/faq/" rel="category tag">FAQ</a>, <a href="https://www.connectortips.com/category/featured/" rel="category tag">Featured</a></span> <span class="entry-tags">Tagged With: <a href="https://www.connectortips.com/tag/faq/" rel="tag">faq</a></span></p></footer></article><article class="post-8010 post type-post status-publish format-standard has-post-thumbnail category-ethernet category-faq category-featured category-industrial category-markets tag-faq entry" aria-label="How does multidrop SPE work?"><header class="entry-header"><h2 class="entry-title"><a class="entry-title-link" rel="bookmark" href="https://www.connectortips.com/how-does-multidrop-spe-work/">How does multidrop SPE work?</a></h2> <p class="entry-meta"><time class="entry-time">May 22, 2024</time> By <span class="entry-author"><a href="https://www.connectortips.com/author/jeff-shepard/" class="entry-author-link" rel="author"><span class="entry-author-name">Jeff Shepard</span></a></span> <span class="entry-comments-link"><a href="https://www.connectortips.com/how-does-multidrop-spe-work/#respond">Leave a Comment</a></span> </p></header><div class="entry-content"><a class="entry-image-link" href="https://www.connectortips.com/how-does-multidrop-spe-work/" aria-hidden="true" tabindex="-1"><img width="150" height="150" src="https://www.connectortips.com/wp-content/uploads/2024/05/How-does-multidrop-SPE-work-Figure-1-2-150x150.jpg" class="alignleft post-image entry-image" alt="" decoding="async" loading="lazy" /></a><p>Multidrop capability is included in several IEEE single-pair Ethernet (SPE) standards, including the 802.3cg substandards 10BASE-T1S and 10BASE-T1M, and the newer 802.3da, which provides enhancements to 10BASE-T1M. This article begins with a brief review of SPE multidrop standards and then explores the bus timing requirements and the use of Physical Layer Collision Avoidance (PLCA) and […]</p> </div><footer class="entry-footer"><p class="entry-meta"><span class="entry-categories">Filed Under: <a href="https://www.connectortips.com/category/ethernet/" rel="category tag">Ethernet</a>, <a href="https://www.connectortips.com/category/faq/" rel="category tag">FAQ</a>, <a href="https://www.connectortips.com/category/featured/" rel="category tag">Featured</a>, <a href="https://www.connectortips.com/category/markets/industrial/" rel="category tag">Industrial</a>, <a href="https://www.connectortips.com/category/markets/" rel="category tag">Markets</a></span> <span class="entry-tags">Tagged With: <a href="https://www.connectortips.com/tag/faq/" rel="tag">faq</a></span></p></footer></article><article class="post-7993 post type-post status-publish format-standard has-post-thumbnail category-faq category-featured category-featured-contributions tag-faq tag-samtec entry" aria-label="DCI pluggable connectors support evolving applications"><header class="entry-header"><h2 class="entry-title"><a class="entry-title-link" rel="bookmark" href="https://www.connectortips.com/dci-pluggable-connectors-support-evolving-applications/">DCI pluggable connectors support evolving applications</a></h2> <p class="entry-meta"><time class="entry-time">May 15, 2024</time> By <span class="entry-author"><a href="https://www.connectortips.com/author/ecady/" class="entry-author-link" rel="author"><span class="entry-author-name">Ed Cady</span></a></span> <span class="entry-comments-link"><a href="https://www.connectortips.com/dci-pluggable-connectors-support-evolving-applications/#respond">Leave a Comment</a></span> </p></header><div class="entry-content"><a class="entry-image-link" href="https://www.connectortips.com/dci-pluggable-connectors-support-evolving-applications/" aria-hidden="true" tabindex="-1"><img width="150" height="150" src="https://www.connectortips.com/wp-content/uploads/2024/05/CT-article-pluggables-Picture2-Lightcounting-chart-150x150.png" class="alignleft post-image entry-image" alt="" decoding="async" loading="lazy" /></a><p>IO interface groups are supported by AI developers, HPC, Enterprise, and other market segment leaders, driving connector/cabling solutions using higher speed rates, varying lane counts, and pin counts. Besides supporting the very high volume pluggable Hyperscale market segment, various pluggable connector systems support other new applications and network topologies that are driving the use of […]</p> </div><footer class="entry-footer"><p class="entry-meta"><span class="entry-categories">Filed Under: <a href="https://www.connectortips.com/category/faq/" rel="category tag">FAQ</a>, <a href="https://www.connectortips.com/category/featured/" rel="category tag">Featured</a>, <a href="https://www.connectortips.com/category/featured-contributions/" rel="category tag">Featured Contributions</a></span> <span class="entry-tags">Tagged With: <a href="https://www.connectortips.com/tag/faq/" rel="tag">faq</a>, <a href="https://www.connectortips.com/tag/samtec/" rel="tag">samtec</a></span></p></footer></article><div class="archive-pagination pagination" role="navigation" aria-label="Pagination"><ul><li class="pagination-previous"><a href="https://www.connectortips.com/category/faq/" >« <span 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