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class="Header_navBack__SfLTa"></div></header><main><div class="press_pageTitle__QWSKd"><div class="container"><div class="row"><h1>In the <em>News</em></h1><div class="press_line__8w_Jf"></div></div></div></div><div class="PressReleases_pressReleases__OwFqi"><div class="container"><div class="row"><div class="col-lg-11 offset-lg-1"><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div><div class="PressReleases_contact__EUsZf"><h2>Media Inquiries</h2><p><a href="mailto:david.miller@sifive.com" rel="noreferrer">david.miller@sifive.com</a><br/><a href="mailto:SiFive@RacePointGlobal.com" rel="noreferrer">SiFive@RacePointGlobal.com</a></p></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Oct 21, 2024</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/hifive-premier-p550-development-boards-now-shipping"><h1>SiFive HiFive Premier P550 Development Boards Now Shipping</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>The world’s highest performance RISC-V development board unlocks new opportunities for software developers to create the next era of RISC-V applications</strong></p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/hifive-premier-p550-development-boards-now-shipping"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Sep 18, 2024</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-highlights-key-inflection-points-driving-ri"><h1>SiFive Highlights Key Inflection Points Driving RISC‑V Adoption for AI and Introduces Intelligence XM Series for AI Workload Acceleration</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>SiFive event showcases how the RISC-V standard is driving AI innovation</strong></p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-highlights-key-inflection-points-driving-ri"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Aug 30, 2024</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-arkmicro-accelerate-risc-v-automotive-electronics-adoption"><h1>SiFive and Arkmicro Accelerate RISC-V Adoption in Automotive Electronics with SiFive’s Automotive IP for the High-end SoC Market</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>Santa Clara, Calif., Aug. 30, 2024</strong> — Today SiFive, Inc. announced that it has licensed its <a href="https://www.sifive.com/cores/automotive" target="_blank" rel="noopener">SiFive Automotive RISC-V IP cores</a> to Arkmicro Technologies (Shenzhen), accelerating the adoption of RISC-V in automotive electronics. Arkmicro is a well-established chip company in the automotive industry, with products already certified and mass-produced by numerous international automotive companies. Arkmicro will integrate SiFive Automotive solutions into Arkmicro’s high-end automotive SoC chips.</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-arkmicro-accelerate-risc-v-automotive-electronics-adoption"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Aug 14, 2024</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-announces-high-performance-risc-v-datacenter-processor-for-ai-workloads"><h1>SiFive Announces New High‑performance RISC‑V Datacenter Processor for Demanding AI Workloads</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>SiFive Performance P870-D brings high compute density and scalability to datacenters, vehicles, and embedded systems</strong></p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-announces-high-performance-risc-v-datacenter-processor-for-ai-workloads"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Jun 25, 2024</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-announces-4th-generation-of-popular-essential"><h1>SiFive Announces 4th Generation of Popular Essential Product Line to Spur Innovation Across Embedded Applications</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>SiFive is seeing growing adoption, with more than two billion SiFive RISC-V based chips already in the market</strong></p> <p><strong>Munich, Germany, June 25, 2024</strong> – Today SiFive, Inc. the gold standard for RISC-V computing, is unveiling a major upgrade of its SiFive Essential product family at the RISC-V Summit Europe 2024. Developed over a decade, the field-proven Essential IP is already in use in billions of products including mobile phones, sensors, SSDs, FPGA platforms, surveillance cameras, smartwatches and more. This full-portfolio refresh brings higher performance, improved power efficiency and more flexible interfaces, with configuration and integration options to cover virtually any possibility. The SiFive Essential Gen4 products are available today.</p> <p>“The best RISC-V embedded solutions just got much better with this fourth generation,” said John Ronco, SiFive SVP of Product. “With the benefits of cost-effective flexibility, performance and low power, RISC-V has won the battle for embedded. As legacy ISAs have reduced R&D and support, we are expanding SiFive’s broad portfolio of market leading Essential products and reaffirming our commitment and support for customers in these critical areas of innovation.”</p> <p>SiFive has seen strong momentum across embedded segments where the Essential Gen4 products will bring impressive flexibility and features to enable customers to better tailor their designs. More than two billion SiFive RISC-V based chips for embedded devices have shipped to-date and the market continues to grow rapidly.</p> <p>“The embedded space in 2024 represents a huge ($257 billion) market opportunity, growing with an 8.3% CAGR through 2030. RISC-V and SiFive have been increasingly gaining momentum and taking share from the other ISAs. SiFive is launching the products that these customers need while also innovating at the high performance and advanced AI levels,” said Rich Wawrzyniak, Principal Analyst at The <a href="https://theshdgroup.com/" target="_blank" rel="noopener">SHD Group</a>. “It is a mistake to discount the importance of embedded products as the flexibility and software portability of RISC-V makes designing products with multiple cores—including the highest performance cores—easier, creating a clear pathway for RISC-V into the next generations of high-performance chips.”</p> <p><strong>Essential Gen4 IP Portfolio Features:</strong></p> <ul> <li>Broadest RISC-V CPU and system IP portfolio</li> <li>Up to 40% runtime power reduction</li> <li>8 different baseline embedded 32-bit and 64-bit cores</li> <li>From 2 stage single-issue to 8 stage superscalar</li> <li>Improved L2 cache and enhanced L1 memory</li> <li>Extensive configuration and integration options <ul> <li>CPU type, profile and options</li> <li>On-chip memories selection</li> <li>System, peripheral and front ports</li> </ul> </li> <li>Advanced power management and security</li> <li>Debug and trace</li> <li>Leading software support, including embedded Linux, FreeRTOS, Eclipse C/C++/ IDE</li> </ul> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-announces-4th-generation-of-popular-essential"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Jun 17, 2024</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/media-alert-sifive-to-exhibit-and-keynote-at-risc-v"><h1>Media Alert: SiFive to Exhibit and Keynote at RISC-V Summit Europe</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>WHAT:</strong> SiFive (a gold sponsor) will be exhibiting at RISC-V Summit Europe from June 25-27, 2024 in Munich. At its booth, SiFive will be showing off its latest products, including SiFive’s new state-of-the-art RISC-V development board, the <a href="https://www.sifive.com/boards/hifive-premier-p550" target="_blank" rel="noopener">HiFive™ Premier P550</a>. The highest performance RISC-V development board on the market, the HiFive Premier P550 offers developers unmatched flexibility and performance.</p> <p>SiFive will also be giving three talks throughout the event, including a keynote from SiFive’s Krste Asanović discussing the incredible momentum of the RISC-V ecosystem across verticals. Additionally, SiFive will be sharing details on its newest <a href="https://www.sifive.com/cores/essential" target="_blank" rel="noopener">Essential products</a>, which are designed to optimize power and performance in a range of devices.</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/media-alert-sifive-to-exhibit-and-keynote-at-risc-v"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Apr 9, 2024</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-unveils-the-hifive-premier-p550-the-first-commercially"><h1>SiFive Unveils the HiFive Premier P550, the First Commercially Available Out-of-order RISC-V Development Board</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>HiFive Premier P550 is the highest performance RISC-V development board on the market, offering developers unmatched flexibility and performance</strong></p> <p><strong>Nuremberg, Germany – April 9, 2024</strong> – Today at Embedded World, SiFive, Inc., the pioneer and leader of RISC-V computing, unveiled its new state-of-the-art RISC-V development board, the <a href="https://www.sifive.com/boards/hifive-premier-p550" target="_blank" rel="noopener">HiFive™ Premier P550</a>. The board will be available for large-scale deployment through Arrow Electronics so developers around the world can test and develop new RISC-V applications like machine vision, video analysis, AI PC and others, allowing them to use AI and other cutting-edge technologies across many different market segments.</p> <p>With a quad-core SiFive Performance™ P550 processor, the HiFive Premier P550 is the highest performance RISC-V development board in the industry, and the latest in the popular HiFive family. Designed to meet the computing needs of modern workloads, the out-of-order P550 core delivers superior compute density and performance in an energy-efficient area footprint. Furthermore, the modular design of the HiFive Premier P550, which includes a replaceable system-on-module (SOM) board, gives developers the flexibility they need to tailor their designs.</p> <p>“The popularity of our development boards underscores the growth and maturity of the RISC-V ecosystem,” said Patrick Little, CEO and Chairman at SiFive. “The HiFive board has always been the ‘golden reference’ RISC-V development platform. Building on this proven foundation with the new HiFive Premier P550, developers can take advantage of SiFive’s high-performance IP in a cost-efficient platform that will be available in volume, opening up unlimited possibilities for RISC-V innovation in AI applications and beyond.”</p> <p>SiFive is collaborating with <a href="https://canonical.com" target="_blank" rel="noopener">Canonical</a>, the publisher of Ubuntu, to ensure that developers can smoothly run the Linux distribution on the HiFive Premier P550. Ubuntu is free to use and comes with five years of free security maintenance for the operating system. Developers and innovators can rely on Ubuntu’s stable and secure platform to access the open source software ecosystem, and get access to bug fixes and security updates for 10+ years backed by Canonical’s enterprise-grade support.</p> <p>“RISC-V is giving developers a new level of freedom to innovate, and SiFive is one of the top companies leading the charge. The availability of HiFive Premier P550 is a significant milestone for the RISC-V development community,” said Gordan Markuš, Silicon Alliances Director at Canonical. “Thanks to our collaboration with SiFive, developers using the HiFive Premier P550 board will be able to innovate at speed with Ubuntu. Additionally, Canonical’s software and services will accelerate time to market, and ensure long-term support and security maintenance for our enterprise partners.”</p> <p><strong>Technical Features</strong></p> <p>The Eswin EIC7700 SoC found on the board features a high performance 64-bit three-issue, out-of-order, SiFive RISC-V P550 core complex configured with four P550 cores, 256KB L2 cache and 4MB L3 cache. The SoC features a 2D/3D GPU, hardware video encoder/decoder, NPU, DSP, MIPI DSI, a security subsystem, an integrated high speed DDR5 memory controller, root complex PCI Express Gen 3 x4 and standard peripherals. Other features include:</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-unveils-the-hifive-premier-p550-the-first-commercially"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Nov 1, 2023</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sophgo-licenses-sifive-risc-v-processor-cores-to-drive"><h1>Sophgo Licenses SiFive RISC‑V Processor Cores to Drive High-Performance AI Computing Innovation</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>SiFive’s Multi-Cluster, Multi-Cores P670 and X280 Power the Open Standard Platform for High-Performance AI Applications</strong></p> <p><strong>Santa Clara, Calif., November 1, 2023 –</strong> Today, Sophgo announced that the company has licensed several SiFive RISC-V high performance processor cores, the <a href="https://www.sifive.com/cores/performance-p650-670" target="_blank" rel="noopener">SiFive Performance P670</a> and <a href="https://www.sifive.com/cores/intelligence-x280" target="_blank" rel="noopener">SiFive Intelligence X280</a> to develop RISC-V AI computing processors. Presented on SG2380 Kick-off Day at the Zhongguancun IC Park in Beijing, the new SiFive cores will be used in the upcoming, Sophgo SG2380.</p> <p>The new Sophgo SG2380 is a 2.5 GHz 16-core RISC-V processor, utilizing the SiFive Performance P670 with a multi-cluster, multi-core configuration. It boasts high performance and RISC-V vector computation advantages. SG2380 also incorporates SiFive Intelligence X280 and a Vector Cooperative Processor Interface Extension (VCIX), integrating Sophgo's AI/ML hardware design. With complete software toolchain support from RISC-V, this coprocessor is targeting not only AI/ML but various advanced computing needs.</p> <p>The P670, combined with RISC-V's unique instruction set architecture advantages and advanced microarchitecture design with silicon implementation by the SiFive team, offers high computational density and vector computation capabilities. Sophgo has also utilized the proven X280, paired with VCIX, as an NPU, highlighting the synergies between the two companies in this collaboration.</p> <p>The SiFive P670 is currently the highest-performance and fully spec-compliant RISC-V commercial-grade processor IP (SpecINT2k6 exceeding 13/GHz) available in the market. SiFive offers multi-cluster, multi-core P670-compliant with RVA22, supporting the latest RISC-V specifications and operating systems, providing optimal performance and the lowest power consumption. The SiFive X280 offers flexibility and scalability in AI applications, supporting multi-core, multi-cluster configurations and numerous successful chip instances. The development tools and software support the latest OpenXLA framework, in line with the market demand and future application trends of AI.</p> <p>For more information about Sophgo SG2380, please refer to CNX SOFTWARE – EMBEDDED SYSTEMS NEWS: <a href="https://www.cnx-software.com/2023/10/21/sophgo-sg2380-16-core-sifive-p670-risc-v-processor-20-tops-ai-accelerator/" target="_blank" rel="noopener">Sophgo SG2380</a> – A 2.5 GHz 16-core SiFive P670 RISC-V processor with a 20 TOPS AI accelerator.</p> <p><strong>About SOPHGO</strong></p> <p>SOPHGO is committed to becoming the world's leading provider of universal computing power, focusing on the development and promotion of computing power products such as AI and RISC-V processors, following the ecological concept of full open source and openness, and working with ecological partners to create a full-scene product matrix covering "cloud, edge and endpoint". Provide computing products and overall solutions for Internet, Urban operations, Intelligent computing centers, General security, Intelligent manufacturing, and AIGC and other application scenarios. Our company has research and development centers in more than 10 cities in China such as Beijing, Shanghai, Shenzhen, Qingdao, Xiamen, as well as in countries such as the United States and Singapore. Since 2016, our brand's SOPHON series products have undergone multiple iterations, achieving significant improvements in energy efficiency compared to their predecessors in each generation.</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sophgo-licenses-sifive-risc-v-processor-cores-to-drive"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Oct 11, 2023</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-announces-differentiated-solutions-for-generative"><h1>SiFive Announces Differentiated Solutions for Generative AI and ML Applications Leading RISC-V into a New Era of High-Performance Innovation</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>SiFive’s Performance P870 and Intelligence X390 product debut sets new bar for high-performance compute in consumer, infrastructure, and automotive applications</strong></p> <p><strong>Santa Clara, Calif., Oct. 11, 2023</strong> –SiFive, Inc., the pioneer and leader of RISC-V computing today announced two new products designed to address new requirements for high performance compute. The SiFive Performance™ P870 and SiFive Intelligence™ X390 offer a new level of low power, compute density, and vector compute capability, and when combined provide the necessary performance boost for increasingly data intensive compute. Together, the new products create a powerful mix of scalar and vector computing to meet the needs of today’s dataflow and computation intensive AI applications across consumer, automotive, and infrastructure markets.</p> <p>The announcement took place at an in-person press and analyst event in Santa Clara today, where the company also provided an update on several of its product lines currently shipping in silicon to customers around the world. Company executives offered insight into SiFive’s product roadmap and discussed how the overall RISC-V ecosystem continues to expand rapidly as new applications call for the benefits of RISC-V-based high-performance compute solutions.</p> <p>“SiFive is leading the industry into a new era of high-performance RISC-V innovation, and closing the gap with other instruction set architectures with our unparalleled portfolio, while recent silicon tape-outs are demonstrating the tremendous benefits of SiFive RISC-V solutions,” said Patrick Little, SiFive Chairman, President and CEO. “As the Arm IPO showed, there is a fast-growing demand for semiconductors across many sectors, particularly processors for consumer and infrastructure markets. The flexibility of SiFive’s RISC-V solutions allows companies to address the unique computing requirements of these segments and capitalize on the momentum around generative AI, where we have seen double-digit design wins, and for other cutting-edge applications.</p> <p><strong>The SiFive Performance P870</strong></p> <p>Ideal for high performance consumer applications, or when used in conjunction with a vector processor in the datacenter, the P870 core sets an impressive new RISC-V performance bar across instruction set architecture availability, throughput, parallelism, and memory bandwidth. Bringing a 50% peak single thread performance upgrade (specINT2k6) over the previous generation SiFive Performance processors, the P870 is a six-wide out-of-order core, that meets RVA 23 and offers a shared cluster cache enabling up to a 32-core cluster. High execution throughput comes with more instruction sets per cycle, more ALU, and more branch units. The P870 is fully compatible with Google’s platform requirements for Android on RISC-V. The P870 also offers additional proven SiFive features: · x 128b VLEN RVV · Vector crypto and hypervisor extensions · IOMMU and AIA · Non-inclusive L3 cache · Proven RISC-V WorldGuard security</p> <p><strong>The SiFive Intelligence X390</strong></p> <p>Building on the highly popular SiFive Intelligence X280’s success in coupling AI/ML applications with hardware accelerators in mobile, infrastructure, and automotive applications, the new X390 brings a 4x improvement to vector computation with its single core configuration, doubled vector length, and dual vector ALUs. This allows quadruple the amount of sustained data bandwidth. With SiFive Vector Coprocessor Interface eXtension (VCIX) companies can easily add their own vector instructions and/or acceleration hardware, bringing unprecedented flexibility and allowing users to greatly increase performance with custom instructions. Features include: · 1024-bit VLEN, 512-bit DLEN · Single / Dual Vector ALU · VCIX (2048-bit out, 1024-bit in)</p> <p><strong>An Agile Hardware Solution for Generative AI applications</strong></p> <p>Bringing the P870 high-performance general compute SoC together with a high performance NPU cluster, consisting of the X390 and customer AI hardware engines, offers product designers a highly flexible, low power, and programmable solution with superior compute density for complex workloads.</p> <p>The company highlighted how interest in these combined SiFive solutions is high, with a number of customers achieving silicon success and in various stages of commercialization using high performance products.</p> <p>SiFive continues to actively work across the ecosystem (see attached quote sheet) with partners who are ensuring the software, security, and flexibility benefits of the open standard ecosystem are in place for SiFive processors as companies move to commercialize their SiFive-powered products.</p> <p><strong>Supporting quotations from industry partners:</strong></p> <p>SiFive has assembled an array of ecosystem partners to help customers speed their time to commercialization.</p> <p>"We have collaborated with SiFive to deliver <a href="https://www.cadence.com/en_US/home.html" target="_blank" rel="noopener">Cadence</a> AI-driven digital full flow Rapid Adoption Kits (RAKs) for previous generation SiFive Performance™ and Intelligence™ RISC-V processors and are looking forward to producing them for the upcoming P870 and X390 processors" said KT Moore, vice president of Corporate Marketing, Cadence. "The RAKs utilize our leading Generative AI solutions that optimize power, performance and area while our system verification solutions enable optimal verification throughput and productivity. This empowers SiFive customers to accelerate time-to-market, enhance product quality, and deliver innovative solutions for high-performance computing, AI, automotive, and mobile applications."</p> <p>“<a href="https://canonical.com" target="_blank" rel="noopener">Canonical’s</a> strategic alliance with SiFive, a RISC-V CPU IP leader, grants us exclusive privileges, including early access to their cutting-edge processors under development. Canonical has ported Ubuntu to SiFive development systems in the past and is working to have Ubuntu ready at launch with the SiFive HiFive Pro P550 and future platforms,” said Cindy Goldberg, Vice President, Silicon Alliances at Canonical. “We see a growing demand for SiFive RISC-V processors and recognize the opportunity across consumer, automotive and infrastructure markets. Ubuntu is the operating system of choice for infrastructure and cloud use cases. This year with the introduction of Ubuntu Pro we have enhanced security, compliance and support coverage across a broad portfolio of open source software and platform architectures. The combination of SiFive’s RISC-V IP and Canonical’s software is a combination that will lead the transformative future in computing, on RISC-V.”</p> <p>“As an early RISC-V adopter and industry leader for delivering production-proven, safety-certified development tools, C/C+ compilers and operating systems for RISC-V, <a href="https://www.ghs.com/partners/sifive_partner.html" target="_blank" rel="noopener">Green Hills Software</a> is excited to be expanding its close working relationship with SiFive by adding optimized support for the P870 and X390.” said Dan Mender, VP of Business Development at Green Hills Software. “Together, Green Hills and SiFive will help companies realize the maximum performance, power, and area benefit possible for these new SiFive offerings.”</p> <p>“<a href="https://www.iar.com/" target="_blank" rel="noopener">IAR</a> welcomes the new SiFive Performance P870 and Intelligence X390 RISC-V processors and recognizes their opportunity for generative AI and ML as well as high-performance computing applications addressing consumer, automotive, and infrastructure. IAR and SiFive have a strong partnership and stand out in the RISC-V ecosystem. SiFive enables IAR with early access its leading commercial RISC-V IP processors while they are under development, enabling co-optimizations benefiting mutual customers. IAR’s complete development solution for all the leading RISC-V core IP from SiFive helps embedded software developers around the world maximize the energy efficiency, simplicity, security, and flexibility upsides that RISC-V and SiFive offer, like the latest additions for Generative AI/ML applications.”</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-announces-differentiated-solutions-for-generative"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Aug 17, 2023</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/media-alert-sifives-leadership-to-keynote-at-the"><h1>MEDIA ALERT: SIFIVE’S LEADERSHIP TO KEYNOTE AT THE RISC-V SUMMIT CHINA 2023 </h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>WHAT:</strong> SiFive will be onsite at the RISC-V Summit China, scheduled for Aug. 23 – 25, 2023 in Beijing. Hosted in partnership with RISC-V International and the Beijing Institute of Open Source Chip (BOSC), SiFive will deliver two keynotes on the future of RISC-V and the latest on SiFive’s high-performance RISC-V processors. SiFive will also host a series of technical sessions focused on RISC-V vectors, ML compilers, hibernation, and more.</p> <p>At the event, SiFive experts can speak to the company’s broad Core IP portfolio, spanning from high-performance application processors to area-optimized, low-power embedded 64- and 32-bit microcontrollers, to vector processors designed for modern compute requirements and artificial intelligence (AI), and optimized for the specific needs of the automotive industry.</p> <p>At RISC-V Summit China, global innovators will share technical and business innovation around RISC-V. The summit features a multi-track conference, tutorials, exhibitions and poster sessions. There will be real-time Chinese to English translations for in-person and virtual attendees.</p> <p>In-person and virtual attendees are encouraged to check out SiFive’s speaking sessions:</p> <p><strong>Wednesday, 23 August:</strong> • 15:20: KEYNOTE: The RISC-V Future is Unlimited: China’s Role with Yunsup Lee • 17:00: KEYNOTE: It Just Keeps Getting Better: RISC-V Processor Performance with Jack Kang</p> <p><strong>Friday, 25 August:</strong> • 09:50: The Story of Getting RISC-V Vector in Linux with Andy Chiu and Zong Li • 14:10: Discovering the RVV C Intrinsics v1.0 with Eop Chen and Kito Cheng • 14:30: Software Components and Methodology for Designing and Optimizing RISC-V ML Compilers – A 3-Year Lesson of Collaboration With OpenXLA with Hong-Rong Hsu and Pen Li • 16:40: Accelerating the Migration from Arm Neon to RISC-V Vectors with Han-Kuan Chen</p> <p><strong>WHO:</strong> SiFive</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/media-alert-sifives-leadership-to-keynote-at-the"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — May 24, 2023</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-gives-worldguard-to-risc-v-international-to"><h1>SiFive Gives WorldGuard to RISC-V International to Make this Robust Security Model More Accessible to the RISC-V Community</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>The open WorldGuard model provides a system-level approach to securing RISC-V designs</strong></p> <p><strong>Santa Clara, Calif., May 24, 2023 – SiFive, Inc.</strong>, the pioneer and leader of RISC-V computing, today announced the company is giving the WorldGuard security model to RISC-V International, providing the RISC-V community with a uniform way to secure their designs and bring them to market faster. RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community which has more than 3,570 RISC-V members across 70 countries.</p> <p>WorldGuard makes it easy for developers to enable a Trusted Execution Environment (TEE) on RISC-V platforms. As a hardware-enhanced software isolation solution, WorldGuard provides protection against improper access to memory or devices by software applications and other bus initiators (such as DMAs). Designers can quickly create domains, also known as “worlds,” for isolated code execution and data protection. WorldGuard doesn't break the RISC-V ISA and doesn't require new instructions to be used. It simply adds secure metadata to the transactions issued by the various bus initiators and checks permissions against an Access Control List (ACL) at the destination, whether it's memory or a peripheral. The isolation is based on multiple levels of privilege for each world, offering robust SoC-level information control.</p> <p>“Robust security is fundamental to every silicon design, but many of the latest security solutions are out of reach for developers,” said Dany Nativel, Senior Director, Product Marketing at SiFive. “From the start, our WorldGuard security model was open and freely accessible for developers to secure their designs at a system level. By donating WorldGuard to RISC-V International, we hope that even more developers will take advantage of it so the entire RISC-V ecosystem can benefit.”</p> <p>WorldGuard provides an open, system-level approach to securing access to system resources (memory and peripherals) by software applications. This approach is ideal for creating multiple trusted environments, enabling a Trusted Computing Base (TCB) where the highest level of trust is limited to the secure ROM boot, the Machine-mode firmware, the secure applications, and the Operating Systems (OSs) that implement them. This base of trust is also referred to as the “Trusted Agent.”</p> <p>“One of the biggest advantages of RISC-V is the active community that is committed to sharing resources and collaborating. Instead of having to reinvent the wheel, developers can use open tools like WorldGuard to ensure their products are secure and speed up time-to-market,” said Calista Redmond, CEO of RISC-V International. “We appreciate SiFive’s donation of WorldGuard as we all work together to secure the future of RISC-V innovation.”</p> <p>Ongoing development of WorldGuard will now be managed by RISC-V International. SiFive will continue to contribute its expertise and resources.</p> <p><strong>About SiFive</strong> As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit SiFive.com.</p> <p><strong>Media Contacts</strong> Allison DeLeo Racepoint Global for SiFive SiFive@racepointglobal.com Tel.: +1(415) 694-6711</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-gives-worldguard-to-risc-v-international-to"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Dec 13, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-delivers-record-growth-in-2022-with-fast-growing"><h1>SiFive Delivers Record Growth in 2022 with Fast-Growing Roster of New Customers and Products </h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>Highlights leadership in RISC-V and proven performance and power density benefits</strong></p> <p><strong>San Jose, Calif., Dec. 13, 2022</strong> – At the <a href="https://events.linuxfoundation.org/riscv-summit/" target="_blank" rel="noopener">RISC-V Summit</a> today, <a href="https://www.sifive.com" target="_blank" rel="noopener">SiFive, Inc.</a>, the founder and leader of RISC-V computing, celebrated its impressive year of growth and technical achievements. In 2022 SiFive announced collaborations with some of the world’s largest chip companies and hyperscale datacenters, as the company has been laser-focused on expanding growth. Today SiFive has design wins with more than 100 customers, including 8 of the top 10 semiconductor companies, in applications including automotive, AR/VR, client computing, datacenter, and the intelligent edge. This year the company rolled out new products for a range of fast-growing and high-volume markets, including a comprehensive automotive portfolio, and expanded its presence globally. This momentum was recognized last week when SiFive was awarded the prestigious 2022 Most Respected Private Semiconductor Company Award by the Global Semiconductor Alliance <a href="https://www.gsaglobal.org/2022awd/" target="_blank" rel="noopener">GSA</a>.</p> <p>“This was a standout year for SiFive, as we collaborated with some of the biggest companies on the planet to tackle their unmet needs, shifted our portfolio and revenues from embedded to high performance RISC-V products that are shaking up the industry, and expanded our global footprint,” said Patrick Little, CEO and Chairman at SiFive. “With the fast-paced growth of SiFive and rapidly increasing demand for our products, and the overall growth of the RISC-V ecosystem, as we’ve said before, the future of RISC-V ‘has no limits’ as we take the company to new heights.”</p> <p>SiFive has made incredible technical progress over the last year, rolling out several products with unparalleled compute performance and efficiency. The new SiFive Performance™ P670 and P470 RISC-V processors raise the bar for innovative designs in high volume applications like wearables, smart home, industrial automation, AR/VR, and other consumer devices. The company introduced its SiFive Automotive™ E6-A, X280-A, and S7-A solutions to address critical needs for current and future applications like infotainment, cockpit, connectivity, ADAS, and electrification. Plus, SiFive enhanced its popular SiFive Intelligence™ X280 processor IP to meet the accelerated demand for vector processing, especially for AI and ML applications.</p> <p>The company has continued to deepen its collaborations and partnerships as it works to transform the future of compute and define what comes next. Through partnership with Microchip, SiFive is a part of NASA’s next generation High-Performance Spaceflight Computing (HPSC) processor, which delivers a 100x increase in computational capability to help propel next-generation planetary and surface missions. Additionally, the X280 processor with the new SiFive Vector Coprocessor Interface Extension (VCIX) is being used as the AI Compute Host to provide flexible programming in a leading datacenter. SiFive also announced its work with companies including BrainChip, Kinara (Deep Vision), Synopsys, and ProvenRun, as well as a broad set of OS, Software Tools, and EDA ecosystem processors for the SiFive Automotive Family of processors</p> <p>Another big milestone for SiFive is the company’s partnership with Intel to spark innovation in high-performance RISC-V platforms. SiFive is supporting Intel Foundry Services (IFS) Innovation Fund’s goal to build innovative new multi-ISA computing platforms including RISC-V platforms optimized for Intel process technology. The IFS Innovation fund will support the creation of disruptive technologies to address modern computing challenges, with the Intel-SiFive collaboration aiming to extend the RISC-V ecosystem. At the show, the companies unveiled more details about the HiFive Pro P550 Development System (code named Horse Creek); this high-performance development system will enable the RISC-V ecosystem to productively create software when it is commercially available later in 2023. <img src="https://images.prismic.io/sifive/0e38fd4a-c176-4547-b585-f852c1d4104f_Patrick+and+Bob.jpg?auto=compress,format" alt="Patrick Little and Bob Brennan of Intel show off the new Hi-Five Pro P550 development board"></p> <p>SiFive’s stellar growth, technical achievements, and partnerships have been recognized by prestigious organizations. In addition to the recent GSA Awards recognition, SiFive was awarded a 2022 TSMC Open Innovation Platform® (OIP) Partner of the Year award. Additionally, SiFive ranked in the top 10 percent of Inc.’s fastest growing private companies in America list.</p> <p>To meet the strong customer demand for SiFive’s innovative RISC-V IP, SiFive has expanded its headcount to more than 550 employees and has opened new offices around the world, including a Research & Development (R&D) Center in Cambridge, United Kingdom, a design center in Bangalore, India, and a new office in Hyderabad, India..</p> <p>At the RISC-V Summit, taking place from Dec. 12-15 in San Jose, Calif. and virtually, SiFive is presenting in more than 10 sessions, including a keynote on Dec. 13 at 10:35 a.m. PT with SiFive’s CEO Patrick Little: “RISC-V Spotlight: Delivering on Real-World Customer Challenges.” To learn more about SiFive’s business, stop by the SiFive booth in the RISC-V Summit Expo Hall.</p> <p><strong>About SiFive</strong> As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit SiFive.com.</p> <p>Stay current with the latest SiFive updates via <a href="https://www.facebook.com/SiFive/" target="_blank" rel="noopener">Facebook</a>, <a href="https://www.instagram.com/sifive_inc/" target="_blank" rel="noopener">Instagram</a>, <a href="https://www.linkedin.com/company/sifive" target="_blank" rel="noopener">LinkedIn</a>, <a href="https://twitter.com/SiFive" target="_blank" rel="noopener">Twitter</a>, and <a href="https://www.youtube.com/c/SiFiveInc" target="_blank" rel="noopener">YouTube</a>.<br/></p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-delivers-record-growth-in-2022-with-fast-growing"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Nov 2, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-awarded-tsmc-open-innovation-platform-partner"><h1>SiFive Awarded TSMC Open Innovation Platform Partner of the Year</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>Santa Clara, Calif., November 3, 2022</strong> - <a href="https://www.sifive.com" target="_blank" rel="noopener">SiFive, Inc.</a> the founder and leader of RISC-V computing, today announced it has received the 2022 TSMC Open Innovation Platform® (OIP) Partner of the Year award, in the Emerging IP Company category. Dr. L.C Lu, TSMC fellow and vice president of design and technology platform, presented the distinguished award to SiFive executives at the recent TSMC 2022 OIP Ecosystem Forum in Santa Clara, CA. The recognition reflects the ongoing innovation and collaboration between the two companies that is furthering the momentum of RISC-V.</p> <p>The Partner of the Year award honors TSMC OIP ecosystem partners' pursuit of excellence in next-generation silicon enablement over the past year.</p> <p>“OIP Partner of the Year award-winning companies work relentlessly to achieve the highest standards of design, development, and technology implementation to accelerate silicon innovation,” said Dan Kochpatcharin, Head of Design Infrastructure Management Division at TSMC. “SiFive’s partnership with TSMC and leadership in the RISC-V architecture enable our mutual customers to achieve next-generation design innovation for key spaces, such as HPC, mobile, and automotive.”</p> <p>“The global SiFive team is honored to be recognized with this prestigious TSMC award for our partnership, RISC-V leadership, and continued innovation,” said Yunsup Lee, Co-founder and CTO. “This award reflects the importance both companies place on our long-term innovation partnership and the great work by teams in both companies. SiFive offers leading power and area efficiencies in a modern architecture supported by the global RISC- V ecosystem, and working with TSMC we are able to do so on the most advanced process nodes and together help proliferate RISC-V.”</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-awarded-tsmc-open-innovation-platform-partner"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Nov 1, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifives-new-high-performance-processors-offer-a-significant"><h1>SiFive’s New High-Performance Processors Offer a Significant Upgrade for Wearable and Consumer Products</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>Next generation P670 and P470 RISC-V Processors bring ultimate flexibility and balance of performance and efficiency for next-generation wearables and smart consumer devices</strong></p> <p><strong>Santa Clara, Calif., November 1, 2022</strong> - <a href="https://www.sifive.com" target="_blank" rel="noopener">SiFive, Inc.</a> the founder and leader of RISC-V computing, today announced two new products that address the need for high performance and efficiency in a small size in high volume applications like wearables, smart home, industrial automation, AR/VR, and other consumer devices. The SiFive Performance™ P670 and P470 RISC-V processors bring unparalleled compute performance and efficiency that is significantly raising the bar for innovative designs in these high-volume markets. The modern and innovative SiFive design methodologies bring raw compute density that is a substantial advantage for SiFive Performance products and also translates into significant cost savings for customers.</p> <p>“The P670 and P470 are specifically designed for, and capable of handling the most demanding workloads for wearables and other advanced consumer applications. These new products offer powerful performance and compute density for companies looking to upgrade from legacy ISAs,” said Chris Jones, SiFive VP of Product. “We have optimized these new RISC-V Vector enabled products to deliver the performance and efficiency improvements the industry has long been asking for, and we are in evaluations with a number of top-tier customers. Additionally, as the upstream enablement of RISC-V has started within the Android Open Source Project, (AOSP), designers will have unrivaled choice and flexibility as they consider the positive implications with that platform for future designs.”</p> <p>"We are excited to see RISC-V solutions for wearable and consumer devices becoming a reality, and we are looking at possibilities of integrating SiFive’s latest products into Snapdragon platforms,” said Ziad Asghar, Vice President, Product Management- Snapdragon Technologies and Roadmap at Qualcomm.</p> <p>"Samsung’s System LSI Business holds a wide portfolio of solutions for various applications, such as mobile, wearables and other consumer devices. We look forward to evaluating how the latest RISC-V innovations from SiFive can enhance our offerings,” said Jinpyo Park, VP of the Innovative AP Development Team, Samsung Electronics System LSI Business.</p> <p>“SiFive continues to be a market leader in the growing and maturing RISC-V space and again shows its leadership with its new SiFive Performance P670 and P470 RISC-V processors,” said Todd R. Weiss, an analyst with Futurum Research. “These latest and powerful new processors give SiFive feature and performance advantages that will gain plenty of attention from device makers and consumers who want more from their devices. SiFive has been growing its reputation for some time and is truly ready to shake up the marketplace.”</p> <p><strong>Features</strong></p> <p>The SiFive Performance P470 and P670 products offer a finely-tuned combination of compute-density, power efficiency, and robust feature sets ideal for a wide range of applications and markets:</p> <p>• Support for virtualization, including a separate IOMMU for accelerating virtualized device IO</p> <p>• Full, Out-of-Order, RISC-V Vector implementation, based on the ratified RISC-V Vector v1.0 Specification</p> <p>• First to market with the RISC-V Vector Cryptography extensions</p> <p>• SiFive WorldGuard system security</p> <p>• Full RISC-V RVA22 profile compliance</p> <p>• New, Advanced Interrupt Architecture (AIA) compliant interrupt controller, with better support for Message Signal Interrupts (MSI) and virtualization</p> <p>• Enhanced scalability with fully coherent multi-core, multi-cluster, with support for up to 16 cores</p> <p><strong>SiFive Performance P670</strong></p> <p>The P670 is ideal for applications like premium wearables, networking, robotics, and mobile. The P650, which excludes the vector unit, is already shipping to lead customers and is being used in applications that do not require the additional capabilities that vector compute offers or are more area constrained.</p> <p>The feature rich P670:</p> <p>• achieves a maximum frequency exceeding 3.4GHz in 5nm,</p> <p>• has performance of greater than 12 SpecINT2k6/GHz, offering optimized performance in a constrained area and power envelope,</p> <p>• offers higher single threaded performance and 2x compute density compared to legacy solutions, and</p> <p>• includes a 2x 128-bit Vector ALUs compliant with the ratified RISC-V Vector v1.0 specification</p> <p><strong>SiFive Performance P470</strong></p> <p>The P470 is SiFive’s first efficiency-focused Out-of-Order, area optimized, vector processor, ideal for applications like wearables, consumer, and smart home devices. Expanding on the proven P500-Series, the P470 is significantly smaller than competing solutions and optimized to have best-in-class performance efficiency and area density. The P470 was designed to also serve as a companion to the P670 processor for demanding applications that require a sharing of compute resources while optimizing power consumption.</p> <p>The P470 offers a significant upgrade to legacy efficiency cores, achieving a maximum frequency exceeding 3.4GHz in 5nm, and greater than 8 SpecINT2k6/GHz, within a minimal area and power envelope.</p> <p>Other P470 features include:</p> <p>• 4x compute density in comparison to leading competitor</p> <p>• Includes 1x 128-bit RISC-V Vector ALU compliant with the ratified RISC-V Vector v1.0 specification</p> <p>SiFive will also release the P450 – an area-optimized version of the P470 that excludes the Vector Unit.</p> <p>A presentation highlighting the benefits of the new products will be made at the Linley Fall Microprocessor Conference later today.</p> <p>For more information on SiFive’s market-leading RISC-V IP portfolio, please visit <a href="https://www.sifive.com/risc-v-core-ip" target="_blank" rel="noopener">SiFive.com/risc-v-core-ip</a>.</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifives-new-high-performance-processors-offer-a-significant"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Oct 25, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-and-synopsys-collaborate-to-accelerate-soc-design"><h1>SiFive and Synopsys Collaborate to Accelerate SoC Design</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>New Synopsys Fusion QuickStart Implementation Kits Deliver Enhanced Power, Performance and Area for SiFive RISC-V Processors</strong></p> <p>SANTA CLARA, Calif. and MOUNTAIN VIEW, Calif., October 25, 2022 – SiFive and Synopsys, Inc. (Nasdaq: SNPS) today announced their new collaboration to accelerate the design and verification of SiFive RISC-V processor-based SoCs. The collaboration provides mutual customers with Synopsys Fusion QuickStart Implementation Kits (QIKs) that optimize the power, performance and area (PPA) of SiFive’s Intelligence™ X280 and Performance™ P550 processor cores. Synopsys Fusion QIKs for SiFive processors leverage the Synopsys Fusion Compiler™ RTL-to-GDSII product and Synopsys Design Space Optimization (DSO.ai™), which autonomously explores multiple design spaces to enhance PPA metrics. By using the implementation scripts and reference guides included in the QIKs, designers can accelerate the development of their SiFive processor-based SoCs.</p> <p>“As we push the performance of application-specific processors, our collaboration with Synopsys enables us to deliver higher quality, PPA-optimized RISC-V solutions that meet and beat our customers’ compute goals,” said Yunsup Lee, co-founder and CTO at SiFive. “Synopsys has early access to SiFive’s processors under development, enabling the companies co-optimize the processors and Synopsys’ tools. This collaboration delivers Synopsys Fusion QIKs for mutual customers to quickly achieve their challenging design targets for their specific application requirements. We look to extend our collaboration to include verification flows, as well as Foundation and Interface IP.”</p> <p>“The trend towards application-specific silicon is helping to address the intensive compute demands of advanced high-performance systems,” Sanjay Bali, vice president of Marketing and Strategy for the EDA Group at Synopsys. “Our collaboration with SiFive to provide Synopsys Fusion QIKs enables designers to achieve the optimal quality-of-results for their custom RISC-V-based SoCs.”</p> <p>Fusion QIKs for SiFive X280 and P550 processors are available for download today through Synopsys SolvNetPlus.</p> <p>Collaborating to Achieve Design Targets Quickly and Confidently In addition to the Fusion QIKs, SoC designers using SiFive RISC-V processors can take advantage of key Synopsys technologies, including: • The Synopsys Digital Design Family, which provides a framework to achieve optimum PPA across all leading technology processes via a shared engine for implementation, test and signoff of power-optimized architectures for SiFive cores. • The family also includes Synopsys Silicon Lifecycle Management Family optimization software, which enables SiFive users to quickly find the best configurations of their software stack to maximize performance of SiFive cores. • The Synopsys Verification Family, which speeds software development, verification throughput and time-to-market for SiFive based designs, including virtual prototyping with models of SiFive’s cores, simulation, formal verification, hardware and software debug, emulation, FPGA prototyping and verification IP. • The silicon-proven Synopsys Interface IP products for the most widely used protocols, which deliver the required low latency, high performance, power efficiency and security for data-intensive systems implementing the latest SiFive processor cores.</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-and-synopsys-collaborate-to-accelerate-soc-design"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Sep 27, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-and-provenrun-collaborate-to-deliver-best-in-class"><h1>SiFive and ProvenRun Collaborate to deliver Best-in-Class Security for RISC-V Microprocessors </h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p>Paris, France, September 27, 2022 – ProvenRun, a global leader in embedded security, today announced the availability of its flagship secure OS / TEE product called ProvenCore, integrated with SiFive® WorldGuard technology, providing powerful SoC-level mechanism for software isolation.</p> <p>Modern microprocessor SoCs are designed to reduce cost by housing all functionality in a single device. This race for more features, which inevitably increases the size of the code and introduces pieces of code from multiple origins, can lead to security risks when one vulnerable piece of code can affect another, intentionally or not. Add to this the significant increase in the device's interactions with the environment, which greatly increases the attack surface, and it makes sense to develop solutions that can guarantee that the failure of one part of the software does not affect the correct and complete functioning of other software running on the same platform.</p> <p>SiFive is the leading provider of market-ready processor core IP based on the open RISC-V instruction set architecture. As part of their open platform secure architecture called SiFive Shield, SiFive offers the SiFive WorldGuard solution to enable Trusted Execution Environment on its RISC-V platforms. SiFive WorldGuard is a hardware-enhanced software isolation solution that provides protection against improper access to memory or devices by software applications and other initiators (such as DMAs). WorldGuard enables designers to create domains, also known as “worlds,” for isolated code execution and data protection. The isolation is based on multiple levels of privilege for each world, to offer SoC-level information control.</p> <p>The WorldGuard solution provides a system-level approach to securing access to system resources (memory, peripherals) by software applications. This approach is ideal for creating a trusted environment, enabling a Trusted Computing Base (TCB) where the highest level of trust is limited to the secure ROM boot, the Machine-mode firmware, the secure applications, and the OperatingSystems (OSs) that implement them. This base of trust is also referred to as the “Trusted Agent.”</p> <p>ProvenCore is a secure OS developed by ProvenRun using deductive formal method, to guarantee security properties such as integrity, confidentiality, correctness, and isolation in order to get as close as possible to zero defect, leaving almost no attack surface for hackers. ProvenCore is resilient against the most sophisticated attacks and has received a Common Criteria EAL7 certification. It is a key component for being able to develop security services with a high security assurance level in a cost-effective way. These security services include key services for establishing a Root of Trust (key management service (secure storage), cryptographic operation services, TRNG) but can also address advanced use cases such as Secure Firmware Update, Runtime Integrity Monitoring, Trusted UI, and more.</p> <p>Using ProvenCore as a “trusted agent” in a WorldGuard configuration achieves best-in-class security for RISC-V architectures, for a scalable and flexible solution with a well-identified and auditable TCB that will meet all security requirements, up to the highest. The implementation of ProvenCore with SiFive WorldGuard can be done by dedicating a core for security, or by isolating two software domains using the same core. The latter is referred to as Trusted Execution Environment, where ProvenCore will coexist with a Rich environment on the same core. A secure monitor will ensure the coordination between the two environments while maintaining the isolation.</p> <p>“Combining ProvenRun ProvenCore software and SiFive WorldGuard hardware is the best way to address system-level hardware and software isolation with a certifiable solution,” said Chris Jones, VP Products at SiFive.</p> <p>ProvenRun also offers a variety of services to help device makers securing products for their entire life cycle: • Consulting services such as risk analysis, security architecture definition, certification support, and secure provisioning • Engineering services such as secure boot implementation and security applications development (cryptographic operation, key management, secure firmware update…)</p> <p>ABOUT PROVENRUN ProvenRun’s mission is to provide customers with the Trusted Products and Services that will help them Embed Security within their infrastructure of connected devices wherever this is required, at the chip, device, edge or cloud levels. With our security consulting services and secure-by-design off-the-shelf product solutions, we resolve the security challenges arising from the IoT revolution while dramatically improving the protection against remote cyberattacks. For more information, www.provenrun.com</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-and-provenrun-collaborate-to-deliver-best-in-class"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Sep 13, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-rolls-out-powerful-new-risc-v-portfolio-to-address"><h1>SiFive Rolls Out Powerful New RISC-V Portfolio to Address Unmet Performance and Feature Needs of Rapidly Evolving Next-Gen Digital Automobiles</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>SiFive introduces Automotive E6-A, X280-A, and S7-A products and long-term roadmap</strong></p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-rolls-out-powerful-new-risc-v-portfolio-to-address"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Sep 6, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/nasa-selects-sifive-and-makes-risc-v-the-go-to-ecosystem"><h1>NASA Makes RISC-V the Go-to Ecosystem for Future Space Missions</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>SiFive X280 delivers 100x increase in computational capability with leading power efficiency, fault tolerance, and compute flexibility to propel next-generation planetary and surface missions</strong></p> <p><strong>San Mateo, Calif., September 6, 2022</strong> - SiFive, Inc., the founder and leader of RISC-V computing, today announced it is providing the core CPU for NASA’s next generation High-Performance Spaceflight Computing (HPSC) processor. HPSC is expected to be used in virtually every future space mission, from planetary exploration to lunar and Mars surface missions. HPSC will utilize a multiple SiFive® Intelligence™ X280 RISC-V vector core, with additional SiFive RISC-V cores, to deliver 100x the computational capability of today’s space computers. This massive increase in computing performance will help usher in new possibilities for a variety of mission elements such as autonomous rovers, vision processing, space flight, guidance systems, communications, and other applications.</p> <p>“As the leading RISC-V, U.S. based, semiconductor company we are very proud to be chosen as part of the most mission critical applications for the World's premier world space agency,” said Jack Kang, SVP Business Development, SiFive. “The X280 demonstrates orders of magnitude performance gains over competing processor technology and our SiFive RISC-V IP allows NASA to take advantage of the support, flexibility, and long-term viability of the fast-growing global RISC-V ecosystem. We’ve always said that with SiFive the future has no limits, and we’re excited to see the impact of our innovations extend well beyond our planet.”</p> <p>The SiFive X280 is a multi-core capable RISC-V processor with vector extensions and SiFive Intelligence Extensions and is optimized for AI/ML compute at the edge. The X280 is ideal for applications requiring high-throughput, single-thread performance while under significant power constraints. The X280 has demonstrated a 100x increase in compute capabilities compared to today’s space computers. In scientific and space workloads, the X280 provides several orders of magnitude improvement compared to competitive CPU solutions.</p> <p>The open and collaborative nature of RISC-V will allow the broad academic and scientific software development community to contribute and develop scientific applications and algorithms, as well optimizing the many math functions, filters, transforms, neural net libraries, and other software libraries, as part of a robust and long-term software ecosystem.</p> <p>The HPSC processor and X280 compute subsystem is expected to be useful to other government agencies in a variety of applications including industrial automation, edge computing, ratification intelligence, and aerospace applications.</p> <p>For more information on SiFive’s market-leading RISC-V IP portfolio and how it is well-suited for Aerospace and Defense applications, please visit SiFive.com.</p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/nasa-selects-sifive-and-makes-risc-v-the-go-to-ecosystem"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Jun 28, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-expands-global-operations-opens-uk-rd-center"><h1>SiFive Expands Global Operations, Opens UK R&D Center in Cambridge</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><em>Leading RISC-V innovator investing in people, community, and Cambridge, with plans to hire more than 100 within two years</em></p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-expands-global-operations-opens-uk-rd-center"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Jun 21, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-enhances-popular-x280-processor-ip-to-meet-accelerated"><h1>SiFive Enhances Popular X280 Processor IP to Meet Accelerated Demand for Vector Processing</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><em>Leading performance for AI inference, Image Processing, and Datacenter applications driving double-digit design wins</em></p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-enhances-popular-x280-processor-ip-to-meet-accelerated"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>BrainChip</strong> — Apr 5, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://brainchipinc.com/brainchip-sifive-partner-deploy-ai-ml-at-edge/"><h1>BrainChip and SiFive partner to deploy AI/ML technology at the edge</h1></a><div class="PressReleases_articleDeck__u_gHz">BrainChip’s AkidaTM is a revolutionary advanced neural networking processor architecture that brings AI to the edge in a way that existing technologies are not capable, with high performance, ultra-low power, and on-chip learning. SiFive Intelligence™ solutions with their highly configurable multi-core, multi-cluster capable design, integrate software and hardware to accelerate AI/ML applications. The integration of BrainChip’s Akida technology and SiFive’s multi-core capable RISC-V processors will provide a highly efficient solution for integrated edge AI compute.</div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://brainchipinc.com/brainchip-sifive-partner-deploy-ai-ml-at-edge/"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Mar 16, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-leadership-in-risc-v-powers-2.5b-company-valuation"><h1>SiFive Leadership in RISC-V Powers $2.5B+ Company Valuation</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><em>$175M Series F Investment Led by Coatue Validates Relentless Pursuit of Processor Innovation</em></p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-leadership-in-risc-v-powers-2.5b-company-valuation"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Feb 7, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/sifive-partners-with-intel-to-spark-innovation-in-high-performance"><h1>SiFive Partners with Intel to Spark Innovation in High-Performance RISC-V Platforms</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><em>Intel Innovation Fund Combines with SiFive RISC-V Leadership, IP, and Experience to Enable Custom SoC Design</em></p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/sifive-partners-with-intel-to-spark-innovation-in-high-performance"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>Electropages</strong> — Jan 31, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.electropages.com/2022/01/helping-lead-risc-v-revolution"><h1>SiFive and Solid Sands are helping to lead the RISC-V revolution</h1></a><div class="PressReleases_articleDeck__u_gHz">SiFive is creating a new infrastructure to support accelerated ASIC and FPGA design flows, IP delivery, and SoC development. These new developments comprise state-of-the-art compiler algorithms, novel build system integration, and new Verilog RTL generation techniques. It needed a powerful compiler test and verification tool, not only to verify the functionality of its current compiler offering, but also to assist in developing its new IDE infrastructure. The tool SiFive selected was SuperTest from Solid Sands.</div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.electropages.com/2022/01/helping-lead-risc-v-revolution"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_storyItem__qv_iJ"><div class="row"><div class="col-lg-3"><div class="PressReleases_dot__c2DC6"></div></div><div class="col-lg-8 offset-lg-1"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>SiFive</strong> — Jan 17, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.sifive.com/press/deep-vision-adopts-sifive-risc-v-to-add-opencv-enabled"><h1>Deep Vision Adopts SiFive RISC-V to Add OpenCV-Enabled AI Support</h1></a><div class="PressReleases_articleDeck__u_gHz"><div class="MarkDown_markdown__xtH9f"><p><strong>Deep Vision licenses SiFive Intelligence X280 processor to deliver greater flexibility and AI inference pre-processing for many markets</strong></p> </div></div><a class="SecondaryButton_secondary__X3oAx undefined" title="Read More" href="https://www.sifive.com/press/deep-vision-adopts-sifive-risc-v-to-add-opencv-enabled"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div><div class="PressReleases_archivesButton__qNnaC"><a class="SecondaryButton_secondary__X3oAx undefined" target="_self" title="View Archived News & Articles" href="https://www.sifive.com/press/archive"><span><i aria-hidden="true"></i><span>View Archived News & Articles</span></span></a></div></div></div><div class="row"><div class="col-lg-11 offset-lg-1"><h2 class="PressReleases_featuredTitle__LTRAX">Featured Articles</h2><div class="row"><div class="PressReleases_featuredReleases__W0VR3"><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>DigiTimes</strong> — Jun 22, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.digitimes.com/news/a20220621PR200/risc-v-sifive.html"><h1>SiFive Enhances Popular Intelligence X280 Processor</h1></a><div class="PressReleases_articleDeck__u_gHz">Article highlights rapid adoption and recent improvements made to SiFive Intelligence X280 processor.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.digitimes.com/news/a20220621PR200/risc-v-sifive.html"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>Electronics Weekly</strong> — Jun 22, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.electronicsweekly.com/uncategorised/intelligence-processor-gets-smarter-2022-06/"><h1>SiFive Intelligence Processor Gets Smarter</h1></a><div class="PressReleases_articleDeck__u_gHz">SiFive has released the latest version of its SiFive Intelligence X280 processor, which introduces new features including scalability up to a 16-core cache-coherent complex, WorldGuard trusted protection, and an interface allowing for integration between the X280 vector unit and customer-designed external AI accelerators or other coprocessors, called VCIX (Vector Coprocessor Interface eXtension).</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.electronicsweekly.com/uncategorised/intelligence-processor-gets-smarter-2022-06/"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>EEWeb</strong> — Apr 29, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.eeweb.com/the-new-era-of-design-freedom-enabled-by-risc-v/"><h1>The New Era of Design Freedom Enabled by RISC-V</h1></a><div class="PressReleases_articleDeck__u_gHz">Over the past few years, supply chain issues have shaken up the chip industry and have reinforced how important it is to have a competitive market for IP and silicon that isn’t controlled by any one company or country. That’s why we’re seeing a strong push from many regions to boost their domestic semiconductor industries, from the European Chips Act to the America Competes Act to India’s Atmanirbhar Bharat campaign. The open RISC-V architecture is playing a central role in these strategies by giving everyone an opportunity to innovate and compete.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.eeweb.com/the-new-era-of-design-freedom-enabled-by-risc-v/"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>EE Times</strong> — Apr 20, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.eetimes.com/sifive-and-brainchip-partner-to-demo-ip-compatibility"><h1>SiFive and BrainChip Partner to Demo IP Compatibility</h1></a><div class="PressReleases_articleDeck__u_gHz">SiFive and BrainChip have partnered to show their IP is compatible in SoC designs for embedded artificial intelligence (AI). The companies have demonstrated BrainChip’s neuromorphic processing unit (NPU) IP working alongside SiFive’s RISC–V host processor IP.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.eetimes.com/sifive-and-brainchip-partner-to-demo-ip-compatibility"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>VentureBeat</strong> — Apr 5, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://venturebeat.com/2022/04/05/brainchip-sifive-partner-to-bring-ai-and-ml-to-edge-computing/"><h1>BrainChip, SiFive Partner to Bring AI and ML to Edge Computing</h1></a><div class="PressReleases_articleDeck__u_gHz">AI processor maker BrainChip, which makes ultra-low-power neuromorphic chips and supporting software, and SiFive, founder of the RISC-V computing genre, today announced they have combined their respective technologies to offer chip designers optimized artificial intelligence (AI) and machine learning (ML) for edge computing.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://venturebeat.com/2022/04/05/brainchip-sifive-partner-to-bring-ai-and-ml-to-edge-computing/"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>EE Times</strong> — Mar 16, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.eetimes.com/sifive-raises-175m-to-quicken-arm-intercept-strategy/"><h1>SiFive Raises $175M To Quicken ‘Arm Intercept’ Strategy</h1></a><div class="PressReleases_articleDeck__u_gHz">SiFive has raised $175 million in a series F funding round aimed at accelerating its processor roadmap and strengthen its position in the market against Arm. The investment puts the company valuation at over $2.5 billion, and in a position to prepare itself for an initial public offering (IPO) next year.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.eetimes.com/sifive-raises-175m-to-quicken-arm-intercept-strategy/"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>The Register</strong> — Mar 16, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.theregister.com/2022/03/16/sifive_175m_series_f/"><h1>SiFive bags $175m to further challenge Arm with RISC-V</h1></a><div class="PressReleases_articleDeck__u_gHz">SiFive is pulling in nearly $400m in funding this year between a new investment round and the proceeds of a business sale with the ambitious mission of eclipsing rival Arm – and the x86 world of Intel and AMD – with processor designs for everything from smartphones to servers.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.theregister.com/2022/03/16/sifive_175m_series_f/"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>The Information</strong> — Mar 16, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.theinformation.com/briefings/sifive-raises-175-million-at-2-5-billion-valuation"><h1>SiFive raises $175 million at $2.5 billion valuation</h1></a><div class="PressReleases_articleDeck__u_gHz">Semiconductor startup SiFive said Wednesday that it has raised $175 million in a Series F funding round at a $2.5 billion post-money valuation. SiFive is the biggest startup centered around RISC-V, an open-source semiconductor technology that competes with Arm Ltd in supplying an underlying framework of chips called an instruction set architecture.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.theinformation.com/briefings/sifive-raises-175-million-at-2-5-billion-valuation"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>Forbes</strong> — Mar 16, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.forbes.com/sites/karlfreund/2022/03/16/sifive-lands-175m-financing/?sh=4c05fd787926"><h1>SiFive Lands $175M Financing</h1></a><div class="PressReleases_articleDeck__u_gHz">SiFive, Inc., today announced it has raised $175 million in a Series F financing round, valuing the RISC-V company at over $2.5 billion. The Series F round was led by Coatue Management. SiFive intends to use the funds to accelerate the development of the company’s RISC-V products, future roadmap, and develop the ecosystem for the open-source Arm challenger. Intel Capital, Sutter Hill, SK Hynix Inc., and Qualcomm Ventures are also investors. The company has now raised over $350M in capital.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.forbes.com/sites/karlfreund/2022/03/16/sifive-lands-175m-financing/?sh=4c05fd787926"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>siliconANGLE</strong> — Mar 16, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://siliconangle.com/2022/03/16/arm-rival-sifive-raises-175m-accelerate-development-alternative-risc-v-chip-architecture/"><h1>Arm rival SiFive raises $175M to accelerate development of its alternative RISC-V chip architecture</h1></a><div class="PressReleases_articleDeck__u_gHz">SiFive Inc., a computer chip startup that’s developing processor technology based on the open-source RISC-V instruction set architecture, said today it has raised a hefty $175 million in a late-stage round of funding.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://siliconangle.com/2022/03/16/arm-rival-sifive-raises-175m-accelerate-development-alternative-risc-v-chip-architecture/"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>VentureBeat</strong> — Mar 16, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://venturebeat.com/2022/03/16/risv-v-chip-designer-sifive-raises-175m-at-a-2-5-billion-valuation/"><h1>RISC-V chip designer SiFive raises $175M at a $2.5 billion valuation</h1></a><div class="PressReleases_articleDeck__u_gHz">Chip design firm SiFive has raised $175 million at a $2.5 billion as RISC-V emerges as an alternative processor architecture. The funding comes at a time when RISC-V is showing greater momentum as an alternative processor architecture to those run by Intel/AMD and Arm.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://venturebeat.com/2022/03/16/risv-v-chip-designer-sifive-raises-175m-at-a-2-5-billion-valuation/"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>Silicon Valley Business Journal</strong> — Mar 16, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.bizjournals.com/sanjose/news/2022/03/16/sifive-adds-175m-in-funding-at-2-5b-valuation.html"><h1>SiFive just raised $175M in new funding. Its CEO says the failed Nvidia-Arm deal boosted its business</h1></a><div class="PressReleases_articleDeck__u_gHz">Nvidia's attempt to buy Arm scared many in the chip industry. That's been a boon to SiFive...</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.bizjournals.com/sanjose/news/2022/03/16/sifive-adds-175m-in-funding-at-2-5b-valuation.html"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>Bloomberg</strong> — Mar 16, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.bloomberg.com/news/articles/2022-03-16/chip-designer-sifive-raises-175-million-setting-stage-for-ipo?sref=gNR1VP2v"><h1>Chip Designer SiFive Raises $175 Million, Setting Stage for IPO</h1></a><div class="PressReleases_articleDeck__u_gHz">Chip startup SiFive Inc. raised $175 million from investors such as Intel Corp. and Qualcomm Inc., giving it enough funding to work toward going public.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.bloomberg.com/news/articles/2022-03-16/chip-designer-sifive-raises-175-million-setting-stage-for-ipo?sref=gNR1VP2v"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>Reuters</strong> — Mar 16, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.reuters.com/technology/risc-v-chip-technology-firm-sifive-raises-175-mln-valued-25-bln-2022-03-16/"><h1>RISC-V chip technology firm SiFive raises $175 mln, valued at $2.5 bln</h1></a><div class="PressReleases_articleDeck__u_gHz">SiFive, Inc., a RISC-V chip technology startup in Silicon Valley, said on Wednesday it raised $175 million in its latest round of funding and is now valued at $2.5 billion.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.reuters.com/technology/risc-v-chip-technology-firm-sifive-raises-175-mln-valued-25-bln-2022-03-16/"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>Protocol</strong> — Mar 16, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.protocol.com/enterprise/sifive-raises-175-million-riscv"><h1>SiFive raises $175 million in bid to unseat Arm with RISC-V</h1></a><div class="PressReleases_articleDeck__u_gHz">The new funding, which values SiFive at $2.5 billion, was designed to help the company establish RISC-V as a real option in the market for third-party chip designs dominated by Arm.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.protocol.com/enterprise/sifive-raises-175-million-riscv"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div><div class="PressReleases_article__Ca53e layout-list"><div><div><p><strong>CRN</strong> — Feb 3, 2022</p><a class="PressReleases_titleLink__T_E_d" href="https://www.crn.com/slide-shows/components-peripherals/the-10-hottest-semiconductor-companies-to-watch-in-2022/11"><h1>The 10 Hottest Semiconductor Companies To Watch In 2022</h1></a><div class="PressReleases_articleDeck__u_gHz">This group of semiconductor giants and chip startups are poised to make big waves in 2022 between new products, merger and acquisition deals and other newsworthy events. As Arm’s future stewardship has become increasingly uncertain, SiFive has risen as an alternative chip designer for companies that want to make their own processors. The main differentiator for SiFive: its use of the free and open RISC-V instruction set architecture.</div><a class="SecondaryButton_secondary__X3oAx undefined" target="_blank" title="Read More" href="https://www.crn.com/slide-shows/components-peripherals/the-10-hottest-semiconductor-companies-to-watch-in-2022/11"><span><i aria-hidden="true"></i><span>Read More</span></span></a></div></div></div></div></div></div></div></div></div></main><footer class="Footer_footer__KQx25"><div class="container"><div style="z-index:10" class="relative row"><div class="col-xl-5 col-lg-12"><a class="Footer_logo__CBryw" title="SiFive" href="https://www.sifive.com/"><svg xmlns="http://www.w3.org/2000/svg" width="100" height="34" fill="none" viewBox="0 0 100 34"><path fill="#fff" d="M4.274 17.6 8.862 3.375H26.44l1.784 5.534H12.696l-.992 3.14h17.533l2.636 8.175L17.65 30.708 4.135 20.739h9.127l4.349 3.207 8.605-6.343zM28.56 0H6.742L0 21.016 17.651 34l17.651-12.988zM53.086 9.614l-1.083 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More","link":{"link_type":"Web","url":"https://www.electronicsweekly.com/uncategorised/intelligence-processor-gets-smarter-2022-06/"},"featured":"yes","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"The New Era of Design Freedom Enabled by RISC-V","spans":[]}],"deck":[{"type":"paragraph","text":"Over the past few years, supply chain issues have shaken up the chip industry and have reinforced how important it is to have a competitive market for IP and silicon that isn’t controlled by any one company or country. That’s why we’re seeing a strong push from many regions to boost their domestic semiconductor industries, from the European Chips Act to the America Competes Act to India’s Atmanirbhar Bharat campaign. The open RISC-V architecture is playing a central role in these strategies by giving everyone an opportunity to innovate and compete.","spans":[]}],"source":"EEWeb","date":"2022-04-29","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.eeweb.com/the-new-era-of-design-freedom-enabled-by-risc-v/"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive and BrainChip Partner to Demo IP Compatibility","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive and BrainChip have partnered to show their IP is compatible in SoC designs for embedded artificial intelligence (AI). The companies have demonstrated BrainChip’s neuromorphic processing unit (NPU) IP working alongside SiFive’s RISC–V host processor IP.","spans":[]}],"source":"EE Times","date":"2022-04-20","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.eetimes.com/sifive-and-brainchip-partner-to-demo-ip-compatibility"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"BrainChip, SiFive Partner to Bring AI and ML to Edge Computing","spans":[]}],"deck":[{"type":"paragraph","text":"AI processor maker BrainChip, which makes ultra-low-power neuromorphic chips and supporting software, and SiFive, founder of the RISC-V computing genre, today announced they have combined their respective technologies to offer chip designers optimized artificial intelligence (AI) and machine learning (ML) for edge computing.","spans":[]}],"source":"VentureBeat","date":"2022-04-05","cta_text":"Read More","link":{"link_type":"Web","url":"https://venturebeat.com/2022/04/05/brainchip-sifive-partner-to-bring-ai-and-ml-to-edge-computing/"},"featured":"yes","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive Raises $175M To Quicken ‘Arm Intercept’ Strategy","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive has raised $175 million in a series F funding round aimed at accelerating its processor roadmap and strengthen its position in the market against Arm. The investment puts the company valuation at over $2.5 billion, and in a position to prepare itself for an initial public offering (IPO) next year.","spans":[]}],"source":"EE Times","date":"2022-03-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.eetimes.com/sifive-raises-175m-to-quicken-arm-intercept-strategy/"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive bags $175m to further challenge Arm with RISC-V","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive is pulling in nearly $400m in funding this year between a new investment round and the proceeds of a business sale with the ambitious mission of eclipsing rival Arm – and the x86 world of Intel and AMD – with processor designs for everything from smartphones to servers.","spans":[]}],"source":"The Register","date":"2022-03-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.theregister.com/2022/03/16/sifive_175m_series_f/"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive raises $175 million at $2.5 billion valuation","spans":[]}],"deck":[{"type":"paragraph","text":"Semiconductor startup SiFive said Wednesday that it has raised $175 million in a Series F funding round at a $2.5 billion post-money valuation. SiFive is the biggest startup centered around RISC-V, an open-source semiconductor technology that competes with Arm Ltd in supplying an underlying framework of chips called an instruction set architecture.","spans":[]}],"source":"The Information","date":"2022-03-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.theinformation.com/briefings/sifive-raises-175-million-at-2-5-billion-valuation"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive Lands $175M Financing","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive, Inc., today announced it has raised $175 million in a Series F financing round, valuing the RISC-V company at over $2.5 billion. The Series F round was led by Coatue Management. SiFive intends to use the funds to accelerate the development of the company’s RISC-V products, future roadmap, and develop the ecosystem for the open-source Arm challenger. Intel Capital, Sutter Hill, SK Hynix Inc., and Qualcomm Ventures are also investors. The company has now raised over $350M in capital.","spans":[]}],"source":"Forbes","date":"2022-03-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.forbes.com/sites/karlfreund/2022/03/16/sifive-lands-175m-financing/?sh=4c05fd787926"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"Arm rival SiFive raises $175M to accelerate development of its alternative RISC-V chip architecture","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive Inc., a computer chip startup that’s developing processor technology based on the open-source RISC-V instruction set architecture, said today it has raised a hefty $175 million in a late-stage round of funding.","spans":[]}],"source":"siliconANGLE","date":"2022-03-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://siliconangle.com/2022/03/16/arm-rival-sifive-raises-175m-accelerate-development-alternative-risc-v-chip-architecture/"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"RISC-V chip designer SiFive raises $175M at a $2.5 billion valuation","spans":[]}],"deck":[{"type":"paragraph","text":"Chip design firm SiFive has raised $175 million at a $2.5 billion as RISC-V emerges as an alternative processor architecture.","spans":[]},{"type":"paragraph","text":"The funding comes at a time when RISC-V is showing greater momentum as an alternative processor architecture to those run by Intel/AMD and Arm.","spans":[]}],"source":"VentureBeat","date":"2022-03-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://venturebeat.com/2022/03/16/risv-v-chip-designer-sifive-raises-175m-at-a-2-5-billion-valuation/"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive just raised $175M in new funding. Its CEO says the failed Nvidia-Arm deal boosted its business","spans":[]}],"deck":[{"type":"paragraph","text":"Nvidia's attempt to buy Arm scared many in the chip industry. That's been a boon to SiFive...","spans":[]}],"source":"Silicon Valley Business Journal","date":"2022-03-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.bizjournals.com/sanjose/news/2022/03/16/sifive-adds-175m-in-funding-at-2-5b-valuation.html"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"Chip Designer SiFive Raises $175 Million, Setting Stage for IPO","spans":[]}],"deck":[{"type":"paragraph","text":"Chip startup SiFive Inc. raised $175 million from investors such as Intel Corp. and Qualcomm Inc., giving it enough funding to work toward going public.","spans":[]}],"source":"Bloomberg","date":"2022-03-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.bloomberg.com/news/articles/2022-03-16/chip-designer-sifive-raises-175-million-setting-stage-for-ipo?sref=gNR1VP2v"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"RISC-V chip technology firm SiFive raises $175 mln, valued at $2.5 bln","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive, Inc., a RISC-V chip technology startup in Silicon Valley, said on Wednesday it raised $175 million in its latest round of funding and is now valued at $2.5 billion.","spans":[]}],"source":"Reuters","date":"2022-03-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.reuters.com/technology/risc-v-chip-technology-firm-sifive-raises-175-mln-valued-25-bln-2022-03-16/"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive raises $175 million in bid to unseat Arm with RISC-V","spans":[]}],"deck":[{"type":"paragraph","text":"The new funding, which values SiFive at $2.5 billion, was designed to help the company establish RISC-V as a real option in the market for third-party chip designs dominated by Arm.","spans":[{"start":0,"end":181,"type":"em"}]}],"source":"Protocol","date":"2022-03-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.protocol.com/enterprise/sifive-raises-175-million-riscv","target":"_blank"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"The 10 Hottest Semiconductor Companies To Watch In 2022","spans":[]}],"deck":[{"type":"paragraph","text":"This group of semiconductor giants and chip startups are poised to make big waves in 2022 between new products, merger and acquisition deals and other newsworthy events. As Arm’s future stewardship has become increasingly uncertain, SiFive has risen as an alternative chip designer for companies that want to make their own processors. The main differentiator for SiFive: its use of the free and open RISC-V instruction set architecture.","spans":[{"start":0,"end":437,"type":"em"}]}],"source":"CRN","date":"2022-02-03","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.crn.com/slide-shows/components-peripherals/the-10-hottest-semiconductor-companies-to-watch-in-2022/11","target":"_blank"},"featured":"no","publish_to":"Current Releases"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive speeds up computing chip designs as it staffs up","spans":[]}],"deck":[{"type":"paragraph","text":"Chip technology firm SiFive Inc on Thursday said it has sped up its computing core designs by 40% and now has a headcount of 700 employees, with plans to double its staff by next year.","spans":[{"start":0,"end":184,"type":"em"}]}],"source":"Reuters","date":"2021-12-02","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.reuters.com/technology/sifive-speeds-up-computing-chip-designs-it-staffs-up-2021-12-02/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive's new chip could lead to revamped phone brains in 2023","spans":[]}],"deck":[{"type":"paragraph","text":"A startup called SiFive announced a new processor design Thursday that could revamp mobile phones, cars and other digital devices if the company's plans work out. Its Performance P650 design comes with a 50% speed boost over the P550 that arrived in June. ","spans":[{"start":0,"end":256,"type":"em"},{"start":17,"end":23,"type":"hyperlink","data":{"link_type":"Web","url":"https://www.sifive.com/","target":"_blank"}},{"start":167,"end":190,"type":"hyperlink","data":{"link_type":"Web","url":"https://www.sifive.com/press/sifive-raises-risc-v-performance-bar-with-new-best-in-class","target":"_blank"}},{"start":229,"end":233,"type":"hyperlink","data":{"link_type":"Web","url":"https://www.cnet.com/tech/mobile/sifive-chip-design-challenges-arm-and-leads-to-intel-alliance/"}}]}],"source":"CNET","date":"2021-12-02","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.cnet.com/tech/mobile/sifives-new-risc-v-chip-challenges-decades-old-computing-designs/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive moves into high-end RISC-V processors with P650 design","spans":[]}],"deck":[{"type":"paragraph","text":"The design for the P650 processor, which other companies will take and turn into working products, is the highest-performing member of the SiFive Performance family, which the company said is expected to be the fastest licensable RISC-V processor IP core. It’s another step in the ongoing quest to show that the open source hardware movement can keep pace with rivals such as Arm and Intel.","spans":[{"start":0,"end":390,"type":"em"}]}],"source":"VentureBeat","date":"2021-12-02","cta_text":"Read More","link":{"link_type":"Web","url":"https://venturebeat.com/2021/12/02/sifive-moves-into-high-end-risc-v-processors-with-p650-design/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive Envisions 128-Core RISC-V SoCs as Gap With x86 and Arm Closes","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive: RISC-V has no limits. SiFive emerged from stealth mode as a developer of small, low-power cores for microcontrollers in 2016. By late 2020, the company had a chip that could run Linux and this week said that it developed a CPU core that is comparable to modern offerings designed by Intel and Arm. The company believes that such high-performance designs could be used for a wide variety of applications, including server-grade system-on-chips with 128-cores.","spans":[{"start":0,"end":466,"type":"em"}]}],"source":"Tom's Hardware","date":"2021-10-22","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.tomshardware.com/news/sifive-develops-ultra-high-performance-risc-v-core","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive has the fastest RISC-V core","spans":[]}],"deck":[{"type":"paragraph","text":"The performance of the as yet nameless RISC-V core should be 50 percent higher than that of its predecessor, and there is also the option for 16-core clusters. [GER]","spans":[{"start":0,"end":165,"type":"em"}]}],"source":"Golem","date":"2021-10-22","cta_text":"Read More","link":{"link_type":"Web","url":"https://www-golem-de.translate.goog/sonstiges/zustimmung/auswahl.html?from=https://www.golem.de/news/offene-befehlssatzarchitektur-sifive-hat-den-schnellsten-risc-v-kern-2110-160508.html\u0026_x_tr_sl=auto\u0026_x_tr_tl=destination_language\u0026_x_tr_hl=en-US\u0026_x_tr_pto=nui","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"We're closing the gap with Arm and x86, claims SiFive: New RISC-V CPU core for PCs, servers, mobile incoming","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive reckons its fastest RISC-V processor core yet is closing the gap on being a mainstream computing alternative to x86 and Arm.","spans":[{"start":0,"end":131,"type":"em"}]}],"source":"The Register","date":"2021-10-21","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.theregister.com/2021/10/21/sifive_riscv_cpu/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"Proposed RISC-V vector instructions crank up computing power on small devices","spans":[]}],"deck":[{"type":"paragraph","text":"When you need to do audio, voice or image processing at the network edge or on a battery budget. ","spans":[{"start":0,"end":97,"type":"em"}]}],"source":"The Register","date":"2021-10-08","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.theregister.com/2021/10/08/riscv_vector_instructions/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"RISC-V is here to stay","spans":[]}],"deck":[{"type":"paragraph","text":"With the HiFive Unmatched, there is finally a powerful developer board with RISC-V, the software is also well-engineered. Apple, Google, Nvidia, Samsung, Qualcomm - they all use them: The open instruction set architecture RISC-V is primarily used in embedded controllers in smartphones, for example. With the HiFive Unmatched, however, Sifive has released a well-equipped mini-ITX board that is aimed at developers or people who want to try out RISC-V. [GER]","spans":[{"start":0,"end":458,"type":"em"},{"start":76,"end":82,"type":"hyperlink","data":{"link_type":"Web","url":"https://www.golem.de/specials/riscv/","target":"_blank"}}]}],"source":"Golem","date":"2021-10-07","cta_text":"Read More","link":{"link_type":"Web","url":"https://www-golem-de.translate.goog/sonstiges/zustimmung/auswahl.html?from=https://www.golem.de/news/sifive-hifive-unmatched-im-test-risc-v-ist-gekommen-um-zu-bleiben-2110-159992.html\u0026_x_tr_sl=auto\u0026_x_tr_tl=en\u0026_x_tr_hl=en-US\u0026_x_tr_pto=nui","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive HiFive Unmatched Hands-On, Initial RISC-V Performance Benchmarks","spans":[]}],"deck":[{"type":"paragraph","text":"A few weeks ago I finally received the HiFive Unmatched from SiFive as their flagship RISC-V development board. As a reminder this is their mini-ITX development board that is powered by their U740 SoC and features 16GB of DDR4 system memory, one PCI Express x16 slot that can work with AMD Radeon graphics cards on Linux, and other features. It's been a delight playing with this developer platform and enclosed are some early benchmarks as well showing off the U740 performance as well as how the Linux software support/performance has been evolving.","spans":[{"start":0,"end":551,"type":"em"}]}],"source":"Phoronix","date":"2021-09-24","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.phoronix.com/scan.php?page=article\u0026item=hifive-unmatched-benchmarks\u0026num=1","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive shepherds RISC-V ISA to enterprise applications, broader adoption","spans":[]}],"deck":[{"type":"paragraph","text":"The company is pushing the capabilities of the heretofore predominately embedded and IoT-focused RISC-V ISA further into visibility with the introduction of the SiFive Performance and SiFive Intelligence processor lines. The latter integrates RISC-V vector extensions and SiFive's proprietary vector extensions for use with AI/ML applications.","spans":[{"start":0,"end":343,"type":"em"}]}],"source":"451 Research","date":"2021-07-12","cta_text":"Read More","link":{"id":"YYRgzhIAACEAWYuy","type":"case_study","tags":[],"lang":"en-us","slug":"sifive-shepherds-risc-v-isa-to-enterprise-applications-broader-adoption","first_publication_date":"2021-11-04T22:38:10+0000","last_publication_date":"2022-10-26T22:40:45+0000","uid":"sifive-shepherds-risc-v-isa-to-enterprise-applications","link_type":"Document","isBroken":false},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"Canonical enables Ubuntu on SiFive’s HiFive RISC-V boards","spans":[]}],"deck":[{"type":"paragraph","text":"With Canonical announcing Ubuntu support for so much new hardware, the announcement of Ubuntu ported to a new architecture can go unnoticed. But today, we have a big one. Working with the leading RISC-V core IP designer and development board manufacturer, SiFive, we are proud to announce the first Ubuntu release for two of the most prominent SiFive boards, Unmatched and Unleashed.","spans":[{"start":0,"end":384,"type":"em"}]}],"source":"Canonical","date":"2021-06-23","cta_text":"Read More","link":{"link_type":"Web","url":"https://ubuntu.com/blog/canonical-enables-ubuntu-on-sifives-hifive-risc-v-boards","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"Intel Licenses SiFive’s Portfolio for Intel Foundry Services on 7nm","spans":[]}],"deck":[{"type":"paragraph","text":"Today’s announcement from SiFive comes in two parts; this part is significant as it recognizes that Intel will be enabling SiFive’s IP portfolio on its 7nm manufacturing process for upcoming foundry customers. ","spans":[{"start":0,"end":210,"type":"em"}]},{"type":"paragraph","text":"[Note - this process technology is now known as 'Intel 4']","spans":[{"start":0,"end":58,"type":"em"},{"start":49,"end":57,"type":"hyperlink","data":{"link_type":"Web","url":"https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros","target":"_blank"}}]}],"source":"Anandtech","date":"2021-06-22","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.anandtech.com/show/16777/intel-licenses-sifives-portfolio-for-intel-foundry-services-on-7nm","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive Inc on Tuesday released a new computing chip design that aims to challenge Arm Ltd's dominance in smartphone chips","spans":[]}],"deck":[{"type":"paragraph","text":"Intel said it is working with SiFive to ensure that the new cores can be manufactured in its newest 7-nanometer chip factories. Intel will offer those manufacturing services to outside chip companies as part of its effort to become a chip contract manufacturer.","spans":[{"start":0,"end":261,"type":"em"}]}],"source":"Reuters","date":"2021-06-22","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.reuters.com/technology/sifive-aims-challenge-arm-with-new-tech-pairs-with-intel-effort-2021-06-22/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive chip design challenges Arm and leads to Intel alliance","spans":[]}],"deck":[{"type":"paragraph","text":"Startup SiFive announced a faster new processor design, the P550, that means its chips can better challenge Arm, the leader in processors for mobile devices and many other electronics products. And the company also deepened a partnership with another rival, Intel, for actually manufacturing the chips.","spans":[{"start":0,"end":302,"type":"em"}]}],"source":"CNet","date":"2021-06-22","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.cnet.com/tech/mobile/sifive-chip-design-challenges-arm-and-leads-to-intel-alliance/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"BSC, Codeplay, and SiFive help accelerate applications on RISC-V thanks to V-extension support in LLVM","spans":[]}],"deck":[{"type":"paragraph","text":"The Barcelona Supercomputing Center (BSC) has been collaborating with Codeplay Software and SiFive to implement support for the RISC-V V-extension v0.10 in the LLVM compilation infrastructure. Thanks to this support, users of RISC-V will be able to take advantage of vector computation capabilities of the RISC-V V-extension through C/C++ intrinsics.","spans":[{"start":0,"end":350,"type":"em"}]}],"source":"Barcelona Supercomputing Center","date":"2021-06-22","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.bsc.es/news/bsc-news/bsc-codeplay-and-sifive-help-accelerate-applications-risc-v-thanks-v-extension-support-llvm","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"Jim Keller-Led Tenstorrent Licenses RISC-V for AI","spans":[]}],"deck":[{"type":"paragraph","text":"The very fact that Tenstorrent chose to use SiFive-developed RISC-V CPU design is noteworthy by itself and is a testament to the new architecture.","spans":[{"start":0,"end":146,"type":"em"}]}],"source":"Tom's Hardware","date":"2021-04-22","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.tomshardware.com/news/tenstorrent-licenses-risc-v","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications ","spans":[]}],"deck":[{"type":"paragraph","text":"“RISC-V is an important element in providing additional capabilities and options for new and existing customers,” said Takeshi Kataoka, Senior Vice President, General Manager of Automotive Solution Business Unit at Renesas. “We are very excited to work with SiFive as their lead partner to develop next-generation semiconductor solutions through the collaboration of our accumulated expertise in the automotive field, and SiFive’s high-end RISC-V technologies.”","spans":[{"start":0,"end":461,"type":"em"}]}],"source":"Renesas","date":"2021-04-20","cta_text":"Read more","link":{"link_type":"Web","url":"https://www.renesas.com/us/en/about/press-room/renesas-and-sifive-partner-jointly-develop-next-generation-high-end-risc-v-solutions-automotive","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive Tapes Out First 5nm TSMC RISC-V Chip With 7.2 Gbps HBM3","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive on Tuesday said that its OpenFive division has successfully taped out the company's first system-on-chip (SoC) on TSMC's N5 process technology. The SoC can be used for AI and HPC applications and can be further customized by SiFive customers to meet their needs.","spans":[{"start":0,"end":269,"type":"em"}]}],"source":"Tom's Hardware","date":"2021-04-13","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.tomshardware.com/news/openfive-tapes-out-5nm-risc-v-soc","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"SiFive announces new RISC-V processor architecture plus its first-ever desktop PC processor","spans":[]}],"deck":[{"type":"paragraph","text":"In the event that Nvidia compromises most processor-related ARM IPs, SiFive's RISC-V scalable CPUs could see increased adoption even from mobile and smartphone OEMs. SiFive is already prepared to meet the increased demand with its updated AI-focused RISC-V microarchitecture that enables different classes of performance, efficiency and features for server-grade, HPC and even desktop PC systems.","spans":[{"start":0,"end":396,"type":"em"}]}],"source":"NotebookCheck","date":"2020-09-15","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.notebookcheck.net/SiFive-announces-new-RISC-V-processor-architecture-plus-its-first-ever-desktop-PC-processor-in-response-to-Nvidia-s-plans-to-dominate-the-server-market.494053.0.html","target":"_blank"},"featured":"no","publish_to":"Archive"},{"press_release":{"link_type":"Document"},"title":[{"type":"heading1","text":"Qualcomm uses RISC-V in Snapdragon chips","spans":[]}],"deck":[{"type":"paragraph","text":"One of the largest SoC developers is now relying on RISC-V: Qualcomm integrates cores with the open instruction set architecture for embedded use in current and future Snapdragon chips.","spans":[{"start":0,"end":185,"type":"em"}]}],"source":"Golem.de","date":"2020-01-24","cta_text":"Read More","link":{"link_type":"Web","url":"http://translate.google.com/translate?js=n\u0026sl=auto\u0026tl=destination_language\u0026u=https://www.golem.de/news/smartphones-qualcomm-nutzt-risc-v-in-snapdragon-chips-2001-146266.html","target":"_blank"},"featured":"no","publish_to":"Archive"}],"stories":[{"title":[{"type":"heading1","text":"Samsung to use SiFive RISC-V Cores for SoCs, Automotive, 5G Applications","spans":[]}],"deck":[{"type":"paragraph","text":"At the annual RISC-V Summit this week, Samsung disclosed the use SiFive’s RISC-V cores for upcoming chips for a variety of applications. The company is joining a growing list of leading high-tech companies that have adopted the RISC-V architecture","spans":[{"start":0,"end":247,"type":"em"}]}],"source":"Anandtech","date":"2019-12-12","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.anandtech.com/show/15228/samsung-to-use-riscv-cores","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V Silicon Startup Raises $50.6 Million and Inks Western Digital Deal","spans":[]}],"deck":[{"type":"paragraph","text":"This week saw another indication that open source hardware is ready to seriously vie for a slice of the enterprise IT pie. On Monday the major company behind the open source RISC-V processor, SiFive, reported it had raised $50.6 million in a Series C funding round, bringing total funding to $64.1 million.","spans":[{"start":0,"end":306,"type":"em"}]}],"source":"Data Center Knowledge","date":"2018-04-07","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.datacenterknowledge.com/hardware/risc-v-silicon-startup-raises-506-million-and-inks-western-digital-deal","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive raises $50.6 million for licensable custom microprocessors","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive has raised $50.6 million in a third round of funding to further its ambition to create a new licensing model for the semiconductor industry. San Francisco-based SiFive wants to democratize access to custom silicon chip designs. The company’s founders invented RISC-V, a free and open instruction set architecture for modern microprocessors. SiFive is taking that architecture and making it easy to design the custom variants that companies need.","spans":[{"start":0,"end":452,"type":"em"}]}],"source":"VentureBeat","date":"2018-04-02","cta_text":"Read More","link":{"link_type":"Web","url":"https://venturebeat.com/2018/04/02/sifive-raises-50-6-million-for-licensable-custom-microprocessors/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Moore’s Law is Dead: So, Let’s Talk About the Future of SoCs","spans":[]}],"deck":[{"type":"paragraph","text":"By now, you’ve likely heard someone tell you: Moore’s Law is dead. To be sure, it is worthwhile to point out that the design aspect of Moore’s Law is – in most circumstances – very much alive. There are still techniques to be discovered to make the transistors smaller, for them to work faster, and to still put more of them in the same footprint. Rather, it is the economics behind Moore’s Law that has clearly reached its endpoint. Chips might continue to get smaller and faster. But if the economics mean that almost no one can afford to buy them, where exactly are we headed?","spans":[{"start":0,"end":579,"type":"em"}]}],"source":"Sensors Online","date":"2018-02-27","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.sensorsmag.com/components/moore-s-law-dead-so-let-s-talk-about-future-socs"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"First Open-Source RISC-V SoC for Linux Released","spans":[]}],"deck":[{"type":"paragraph","text":"Only months after debuting the Freedom U540, the world's first Linux-compatible processor based on the open-source RISC-V chip architecture, RISC-V chipmaker SiFive has surprised the open-source community again by unveiling a full development board built around the ISA.","spans":[{"start":0,"end":270,"type":"em"}]}],"source":"Design News","date":"2018-02-15","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.designnews.com/electronics-test/first-open-source-risc-v-soc-linux-released/86012081658262"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Is Open Source RISC-V Ready to Take on Intel, AMD, and ARM in the Data Center?","spans":[]}],"deck":[{"type":"paragraph","text":"While software is eating the world, open source hardware might soon be eating the data center. Definitely not tomorrow or next month, and probably not even next year, but sooner than you think, there might be as much open source hardware as the old-fashioned proprietary kind running data centers. Need proof? Take a look at RISC-V, an open processor architecture.","spans":[{"start":0,"end":365,"type":"em"}]}],"source":"Data Center Knowledge","date":"2018-02-13","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.datacenterknowledge.com/hardware/open-source-risc-v-ready-take-intel-amd-and-arm-data-center"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"HiFive Unleashed: The first Linux-capable RISC-V single board computer is here","spans":[]}],"deck":[{"type":"paragraph","text":"For low-power and embedded purposes RISC-V, an ISA developed principally by researchers at UC Berkeley with significant outside contributions, is gaining popularity. While early RISC-V devices have been intended for embedded applications and IoT devices, SiFive has released the first RISC-V SoC (Freedom U540) and SBC (Hi-Five Unleashed) which are powerful enough to run Linux distributions.","spans":[{"start":0,"end":393,"type":"em"}]}],"source":"Tech Republic","date":"2018-02-05","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.techrepublic.com/article/hi-five-unleashed-the-first-linux-capable-risc-v-single-board-computer-is-here/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Interview with Palmer Dabbelt: Igniting the Open Hardware Ecosystem with RISC-V. SiFive's Freedom U500 is the World's First Linux-capable Open Source SoC Platform","spans":[]}],"deck":[{"type":"paragraph","text":"Palmer Dabbelt will give a talk about Igniting the Open Hardware Ecosystem with RISC-V. SiFive's Freedom U500 is the World's First Linux-capable Open Source SoC Platform at FOSDEM 2018.","spans":[{"start":0,"end":185,"type":"em"}]}],"source":"FOSDEM 2018","date":"2018-02-03","cta_text":"Read More","link":{"link_type":"Web","url":"https://fosdem.org/2018/interviews/palmer-dabbelt/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"The Bisquick Alternative","spans":[]}],"deck":[{"type":"paragraph","text":"“Our vision is to enable two guys in a garage to build a custom chip.” Thus spake Jack Kang, Vice President of SiFive, the 40-person startup making RISC-V chips. SiFive isn’t just another company pulling the RISC-V bandwagon. They’re trying to change the way we create SoCs. The au courant open-source processor design is just a means to that end.","spans":[{"start":0,"end":347,"type":"em"}]}],"source":"EE Journal","date":"2018-01-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.eejournal.com/article/the-bisquick-alternative/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Joins Microsemi's New Mi-V Ecosystem to Accelerate Adoption of RISC-V Open Instruction Set Architecture","spans":[]}],"deck":[{"type":"paragraph","text":"Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced SiFive, the first fabless provider of customized, open-source-enabled semiconductors, has joined Microsemi's new Mi-V™ RISC-V ecosystem, further building out the growing ecosystem and expanding the number of RISC-V designs users can consider. Microsemi will leverage its strategic relationship with SiFive and other ecosystem participants to increase adoption of RISC-V open instruction set architecture (ISA) central processing units (CPUs) and maximize their leadership positions with this expanding design technology.","spans":[{"start":0,"end":684,"type":"em"}]}],"source":"Microsemi","date":"2017-12-06","cta_text":"Read More","link":{"link_type":"Web","url":"https://investor.microsemi.com/2017-12-07-SiFive-Joins-Microsemis-New-Mi-V-Ecosystem-to-Accelerate-Adoption-of-RISC-V-Open-Instruction-Set-Architecture"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Western Digital Gives A Billion Unit Boost To Open Source RISC-V CPU","spans":[]}],"deck":[{"type":"paragraph","text":"Western Digital is known for its storage products. What many do not realize is that the company ships over 1 billion processor cores within its products each year and is moving toward 2 billion per year. At the workshop, Western Digital CTO Martin Fink announced that over the next few years those billion plus processors will be transitioned over to RISC-V.","spans":[{"start":0,"end":358,"type":"em"}]}],"source":"Forbes","date":"2017-12-05","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.forbes.com/sites/tiriasresearch/2017/12/06/western-digital-gives-a-billion-unit-boost-to-open-source-risc-v-cpu/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"DesignShare is all About Enabling Design Wins!","spans":[]}],"deck":[{"type":"paragraph","text":"One of the barriers to silicon success has always been design costs, especially if you are an emerging company or targeting an emerging market such as IoT. Today design start costs are dominated by IP which is paid at the start of the project and that is after costly IP evaluations and other IP verification and integration challenges. Given that, reducing design costs and enabling design starts has always been a major industry focus starting with the fabless semiconductor transformation that began 30 years ago, which brings us to the DesignShare announcement made by SiFive and Flex Logix last week.","spans":[{"start":0,"end":605,"type":"em"}]}],"source":"SemiWiki","date":"2017-11-07","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.semiwiki.com/forum/content/7126-designshare-all-about-enabling-design-winse.html-designshare-all-about-enabling-design-wins"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"FlexLogix joins SiFive’s DesignShare program","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive and FlexLogix have teamed up to offer embedded FPGAs in the DesignShare development program. This is the third IP vendor that SemiAccurate knows of to join that program and it is an interesting idea. SiFive’s DesignShare program is unique in it’s aim to lower the barriers of entry for companies interested in making silicon.","spans":[{"start":0,"end":333,"type":"em"}]}],"source":"SemiAccurate","date":"2017-11-01","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.semiaccurate.com/2017/11/02/flexlogix-joins-sifives-designshare-program/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"64bit quad-core RISC-V for Linux","spans":[]}],"deck":[{"type":"paragraph","text":"RISC-V is a free and open instruction set architecture [ISA] designed to enable chips across the full spectrum of computing devices, from embedded devices to the data centre,” said the firm. “The release of the U54-MC Coreplex marks the architecture’s expansion into the application processor space – opening entirely new use cases for RISC-V. It is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways and smart IoT devices.","spans":[{"start":0,"end":487,"type":"em"}]}],"source":"Electronics Weekly","date":"2017-10-09","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.electronicsweekly.com/news/design/eda-and-ip/64bit-quad-core-risc-v-linux-2017-10/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive launches Linux-ready RISC-V quad-core processor","spans":[]}],"deck":[{"type":"paragraph","text":"The Coreplex U54-MC contains four U54 CPUs and a single E51 CPU and is the first Coreplex processor core to offer multicore support and support for cache coherence. The U54 cores support the RV64GC ISA with a five-stage, in-order pipeline ALU. The 64bit E51 CPU serves as a management core and is fully coherent with the U54 cores. The U54-MC Coreplex is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways, and smart IoT devices.","spans":[{"start":0,"end":493,"type":"em"}]}],"source":"eeNews Europe","date":"2017-10-09","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eenewseurope.com/news/sifive-launches-linux-ready-risc-v-quad-core-processor"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"2018 will be the year of the RISC V Linux processors","spans":[]}],"deck":[{"type":"paragraph","text":"Linux fanboys tend to announce a lot of “year of” events. There is the year of the desktop which appears to be every year and still never happens and now there is the year of RISC V Linux processor. SiFive has declared that 2018 will be the year of RISC V Linux processor, so mark your penguin diaries accordingly. In the UK there will be all sorts of events planned, including guess the weight of Linus Torvalds competitions, there will be penguin tossing at Slough.","spans":[{"start":0,"end":468,"type":"em"}]}],"source":"Fudzilla","date":"2017-10-08","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.fudzilla.com/news/processors/44667-2018-will-be-the-year-of-the-risc-v-linux-processors"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Linux Gets Its First Multi-Core, RISC-V Based Open Source Processor","spans":[]}],"deck":[{"type":"paragraph","text":"Last year, Silicon Valley Startup SiFive released the first open source SoC (system on a chip), which was named Freeform Everywhere 310. Now, going one step ahead from the embedded systems, the company has released U54-MC Coreplex IP, which is the world’s first RISC-V based 64-bit quad-core CPU that supports fully featured operating systems like Linux.","spans":[{"start":0,"end":354,"type":"em"}]}],"source":"Fossbytes","date":"2017-10-08","cta_text":"Read More","link":{"link_type":"Web","url":"https://fossbytes.com/u54-mc-coreplex-ip-linux-open-source-risc-v-processor/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Linux Now Has its First Open Source RISC-V Processor","spans":[]}],"deck":[{"type":"paragraph","text":"When it released its first open-source system on a chip, the Freeform Everywhere 310, last year, Silicon Valley startup SiFive was aiming to push the RISC-V (\"risk five\") architecture to transform the hardware industry in the way that Linux transformed the software industry. Now the company has delivered further on that promise with the release of the U54-MC Coreplex , the first RISC-V-based chip that supports Linux, Unix, and FreeBSD.","spans":[{"start":0,"end":439,"type":"em"}]}],"source":"Design News","date":"2017-10-05","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.designnews.com/content/linux-now-has-its-first-open-source-risc-v-processor/71646867257598"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"The Week In Review: Design","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive launched U54-MC Coreplex IP, a RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The cores utilize a five-stage in-order pipeline, support the RV64GC ISA and cache coherence. It is targeted at AI, machine learning, networking, gateways and smart IoT devices.","spans":[{"start":0,"end":350,"type":"em"}]}],"source":"Mention","date":"2017-10-05","cta_text":"Read More","link":{"link_type":"Web","url":"https://semiengineering.com/the-week-in-review-design-100/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Announces RISC-V SoC","spans":[]}],"deck":[{"type":"paragraph","text":"At the Linley Processor Conference today, SiFive, the semiconductor company building chips around the Open RISC-V instruction set has announced the availability of a quadcore processor that runs Linux. We’ve seen RISC-V implementations before, and SiFive has already released silicon-based on the RISC-V ISA. These implementations are rather small, though, and this is the first implementation designed for more than simple embedded devices.","spans":[{"start":0,"end":441,"type":"em"}]}],"source":"Hackaday","date":"2017-10-03","cta_text":"Read More","link":{"link_type":"Web","url":"https://hackaday.com/2017/10/04/sifive-announces-risc-v-soc/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V Boots Linux at SiFive","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive has taped out and started licensing its U54-MC Coreplex, its first RISC-V IP designed to run Linux. The design lags the performance of a comparable ARM Cortex-A53 but shows progress creating a commercial market for the open-source instruction set architecture.","spans":[{"start":0,"end":267,"type":"em"}]}],"source":"EE Times","date":"2017-10-03","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.eetimes.com/document.asp?doc_id=1332398"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive's RISC-V Goes Multicore","spans":[]}],"deck":[{"type":"paragraph","text":"The RISC-V universe just got a little bigger with SiFive’s 1.5 GHz U54-MC Coreplex (Fig. 1). The four U54 cores implement RV64GC that includes support for hardware multiple and divide, atomic instructions, 16-bit compressed instructions, and single and double precision floating point support.","spans":[{"start":0,"end":293,"type":"em"}]}],"source":"Electronic Design","date":"2017-10-03","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.electronicdesign.com/technologies/embedded-revolution/article/21805661/sifives-riscv-goes-multicore","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Unleashes the First Linux-Ready, 64-Bit RISC-V SoC","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive has taped out the first multi-core RISC-V based processor design, and the first to run Linux, featuring 4x 1.5GHz \"U54\" cores and a management core. SiFive announced \"early access\" availability of the 64-bit, quad-core U54-MC Coreplex – the first Linux-ready application processor built around the open source RISC-V architecture.","spans":[{"start":0,"end":337,"type":"em"}]}],"source":"LinuxGizmos.com","date":"2017-10-03","cta_text":"Read More","link":{"link_type":"Web","url":"http://linuxgizmos.com/sifive-unleashes-the-first-linux-ready-64-bit-risc-v-soc/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive FE310: Setting The RISC Free","spans":[]}],"deck":[{"type":"paragraph","text":"It is out of this that SiFive began. SiFive was founded by the creators of the first commercially successful open RISC architecture, known as RISC-V. RISC-V was developed at Berkeley, fittingly, in 2010 and was designed to be a truly useful, general purpose RISC processor, easy to design with, easy to code for, and with enough features to be commercially useful, not limited to the classroom. It is called the RISC-V because it is the fifth RISC design developed at Berkeley, RISC I and RISC II being designed in 1981, followed by SOAR (Smalltalk On A RISC) in 1984 and SPUR (Symbolic Processing Using RISC) in 1988. RISC-V has already proved to be a success, it is licensed freely, and in a way (BSD license) that allows products that use it to be either open, or proprietary. One of the more well known users is Nvidia, which announced they are replacing their own proprietary FALCON processors (used in their GPUs and Tegra processors) with RISC-V. Samsung, Qualcomm, and others are already using RISC-V. These cores are often so deeply embedded that their existence goes without mention, but they are there, working in the background to make whatever tech needs to work, work.","spans":[{"start":0,"end":1189,"type":"em"}]}],"source":"CPU Shack Museum","date":"2017-06-04","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.cpushack.com/2017/06/05/sifive-fe310-setting-the-risc-free/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive让RISC-V商业化之路不再难行","spans":[]}],"deck":[{"type":"paragraph","text":"开源是当今最热门的话题之一，也是未来的趋势，就像1998年时任微软CEO的鲍尔默痛斥Linux是癌症，而如今的CEO 却称“Microsoft love Linux”，因为开源“以人为本”，然而开源的商业化是一条必行却又难行的路。","spans":[{"start":0,"end":115,"type":"em"}]},{"type":"paragraph","text":"如今的处理器、SoC基本被x86与ARM 这样封闭的指令集架构（ISA）所统治。所以谁能成为微处理器中的 Linux ，成为业界探讨与期待的事情。而目前RISC-V成为最受关注的对象。","spans":[{"start":0,"end":92,"type":"em"}]},{"type":"paragraph","text":"5月8日，第六届RISC-V技术研讨会在上海交通大学举行，这是RISC-V在华首度亮相。参会的国内外顶尖学者和企业人员超过200名，RISC-V发明者创建的SiFive公司分享了RISC-V指令集和其相关前景应用。","spans":[{"start":0,"end":107,"type":"em"}]}],"source":"EEFocus","date":"2017-05-17","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eefocus.com/mcu-dsp/383594"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive携全新产品和商业模式让RISC-V触手可及","spans":[]}],"deck":[{"type":"paragraph","text":"由免费开源RISC-V指令集架构发明者创建的企业SiFive于今日在上海参加RISC-V基金会主办，NVIDIA和上海交通大学联合承办的第六届RISC-V技术研讨会，首次在中国与到会的200余名国内外顶尖学者和企业共同分享RISC-V指令集和其相关前景应用。作为首家基于免费开源RISC-V指令集架构的定制半导体公司，SiFive还在研讨会上分享了公司的最新进展 – SiFive即将推出目前访问RISC-V内核最快捷也最简单的方式 – Coreplex IP产品。随着RISC-V生态系统的快速发展，SiFive Coreplex IP设计已成为RISC-V内核的实际领导者，拥有比任何其他RISC-V架构厂商更多的客户群、硅产品和开发板。另外，SiFive还提供了简易的“调研-评估-购买”(Study – Evaluate – Buy)的采购流程，帮助工程师们迅速获得实用的Coreplex IP RTL源代码。","spans":[{"start":0,"end":409,"type":"em"}]}],"source":"EEWorld","date":"2017-05-09","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eeworld.com.cn/manufacture/article_2017051014322.html"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive让RISC-V商业化之路不再难行 ","spans":[]}],"deck":[{"type":"paragraph","text":"在你购买一个PC或者服务器的时候，在做主芯片选择的时候，你会想到X86架构，或者至少时候ARM架构的芯片。","spans":[{"start":0,"end":53,"type":"em"}]},{"type":"paragraph","text":"但是像软件里的LINUX一样，一个开源的架构项目准备打破这个由Intel、AMD和ARM主导的芯片市场，那就是Risc-V。","spans":[{"start":0,"end":62,"type":"em"}]},{"type":"paragraph","text":"这个由加州大学伯克利分校研究院在2010年打造的芯片架构是免费向所有人开放的。而据介绍，开发者可以基于这个架构开发应用于PC、服务器、智能手机、可穿戴和其他设备的芯片。","spans":[{"start":0,"end":84,"type":"em"}]},{"type":"paragraph","text":"初创企业SiFive是首个基于Risc-V架构开拓业务的公司，这个公司也是首个将Risc-V指令转为硅片的企业。日前，该公司宣布，他们已经开发出了两款芯片设计，并能够将其授权给客户。","spans":[{"start":0,"end":91,"type":"em"}]}],"source":"谁是目标 (via 百家号)","date":"2017-05-08","cta_text":"Read More","link":{"link_type":"Web","url":"https://baijiahao.baidu.com/po/feed/share?context=%7B%22nid%22%3A%22news_3321011278391643526%22%7D"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"A Patient Disciple of RISC-V, SiFive Starts Selling Cores","spans":[]}],"deck":[{"type":"paragraph","text":"Last year, SiFive went fishing for engineers willing to test out chips based on the RISC-V instruction set, releasing a basic core called Rocket that anyone could download and modify. But now the company, whose founders invented RISC-V, is using richer bait for more ambitious customers.","spans":[{"start":0,"end":287,"type":"em"}]},{"type":"paragraph","text":"Last week, SiFive started selling two embedded cores under the brand Coreplex, with applications ranging from wearables to servers. The company is aiming to lower the bar for engineers trained on Intel or ARM instruction sets to take RISC-V for a spin, when few companies appear to be turned off by the inflexibility or licensing fees of rival technology.","spans":[{"start":0,"end":355,"type":"em"}]}],"source":"Electronic Design","date":"2017-05-08","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.electronicdesign.com/technologies/embedded-revolution/article/21805031/sifive-a-disciple-of-the-riscv-architecture-starts-selling-cores","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive raises $8.5 million for licensable custom microprocessors","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive is pioneering a new model in the semiconductor business and to do so has raised $8.5 million in a second round of funding, led by Spark Capital.","spans":[{"start":0,"end":151,"type":"em"}]},{"type":"paragraph","text":"San Francisco-based SiFive is on a mission to democratize access to custom silicon chip designs. The company’s founders invented RISC-V, a free and open instruction set architecture for modern microprocessors. It consists of all of the software instructions needed to program a microprocessor based on the RISC-V architecture. And SiFive is taking that architecture and making it easy to design the custom variants that companies need.","spans":[{"start":0,"end":435,"type":"em"}]}],"source":"VentureBeat","date":"2017-05-07","cta_text":"Read More","link":{"link_type":"Web","url":"https://venturebeat.com/2017/05/08/sifive-raises-8-5-million-for-licensable-custom-microprocessors/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Design your own RISC-V SoC with SiFive’s new “hassle-free” process","spans":[]}],"deck":[{"type":"paragraph","text":"This week, SiFive announced a new “study-evaluate-buy” purchase process, that lets developers “get their hands on Coreplex IP RTL in a matter of minutes.” The immediately downloadable E31 Coreplex and E51 Coreplex IP RTL is described as “fully synthesizable and verified soft IP implementations that scale across multiple design nodes, making them ideal for your next SoC design.” On its Coreplex IP evaluation web page, SiFive describes the IP evaluation and purchase as being fast, NDA-free, and with a pricing model that is not based on royalties.","spans":[{"start":0,"end":550,"type":"em"}]}],"source":"LinuxGizmos","date":"2017-05-07","cta_text":"Read More","link":{"link_type":"Web","url":"http://linuxgizmos.com/diy-a-risc-v-soc-with-sifives-hassle-free-process/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive raises $8.5M to build low-cost custom chips","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive Inc. wants to give businesses access to custom-designed silicon chips at an affordable price, and today the San Francisco-based semiconductor startup announced that ii has closed an $8.5 million Series B funding round.","spans":[{"start":0,"end":225,"type":"em"}]},{"type":"paragraph","text":"The round was led by Spark Capital, and it also included participation from Osage University Partners and existing investor Sutter Hill Ventures. SiFive’s Series B round brings the startup’s total investments to date to $13.5 million.","spans":[{"start":0,"end":234,"type":"em"}]}],"source":"SiliconAngle","date":"2017-05-07","cta_text":"Read More","link":{"link_type":"Web","url":"https://siliconangle.com/blog/2017/05/08/sifive-raises-8-5m-build-low-cost-custom-chips/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Open-source chip mimics Linux's path to take on closed x86, ARM CPUs","spans":[]}],"deck":[{"type":"paragraph","text":"A startup called SiFive is the first to make a business out of the RISC-V architecture. The company is also the first to convert the RISC-V instruction set architecture into actual silicon. The company on Thursday announced it has created two new chip designs that can be licensed.","spans":[{"start":0,"end":281,"type":"em"}]}],"source":"CIO","date":"2017-05-03","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.cio.com/article/3194354/internet-of-things/open-source-chip-mimics-linuxs-path-to-take-on-closed-x86-arm-cpus.html"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Is Bringing Open Source to the Chip Level","spans":[]}],"deck":[{"type":"paragraph","text":"There has been an upswell of interest in custom, open hardware among makers, in which community-developed and shared designs abound. The availability of low-cost development boards such as Arduino and Raspberry Pi, together with open source software, has made it easier to get started with making innovative, new hardware designs.","spans":[{"start":0,"end":330,"type":"em"}]}],"source":"Make","date":"2017-05-02","cta_text":"Read More","link":{"link_type":"Web","url":"http://makezine.com/2017/05/03/sifive-brings-open-source-to-chip-level/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Open Source Chip Design Hack Chat Transcript","spans":[]}],"deck":[{"type":"paragraph","text":"Come hang out for 30 or so minutes and talk to Jack Kang, VP of Product and Business Development at SiFive. Join this chat to learn about RISC-V, the free and open Instruction Set. Ask questions about what it means to have open-source chips, and how SiFive plans to help everybody—from the smallest company, inventor, and maker, get access to custom silicon.","spans":[{"start":0,"end":358,"type":"em"}]}],"source":"Hackaday","date":"2017-04-13","cta_text":"Read More","link":{"link_type":"Web","url":"https://hackaday.io/event/21084-open-source-chip-design-hack-chat/log/57313-open-source-chip-design-hack-chat-transcript"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Customer Corner: SiFive's Freedom Everywhere 310 (FE310) SoC Alternative","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive is the first fabless provider of customized, open-source-enabled semiconductors. The RISC-V ISA has been central to our vision of enabling a whole new range of applications for everyone. In November 2016, we announced the availability of the Freedom Everywhere 310 (FE310) SoC, the industry's first commercially available chip based on RISC-V. Bringing the first commercially available SoC based on the RISC-V ISA is a huge milestone for the open-source hardware community.","spans":[{"start":0,"end":480,"type":"em"}]}],"source":"Sidense","date":"2017-03-08","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.sidense.com/support-resources/nvm-insider/604-the-nvm-insider-issue-28?showall=\u0026start=3"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V \"The thing that you learn and the thing that you use are the same\"","spans":[]}],"deck":[{"type":"paragraph","text":"The SiFive business model is that lots of people are locked out of silicon. SiFive can do custom design and deliver chips. \"We believe we can do it cheaper, quicker and more predictably than anyone else.” They have also been getting lots of calls to help with designs. Growing the RISC-V ecosystem is a big opportunity.","spans":[{"start":0,"end":319,"type":"em"}]},{"type":"paragraph","text":"The traditional semiconductor business models take a lot of resources, so you have to pick the winners. But there aren't any $1B sockets anymore, so you can't easily pick the winners. The market is fragmented. SiFive wants to give everyone a chance. In a bit more detail, they will do a customer microcontroller platform and deliver 100 or so chips for under $100K.","spans":[{"start":0,"end":365,"type":"em"}]}],"source":"Cadence","date":"2017-01-22","cta_text":"Read More","link":{"link_type":"Web","url":"https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2017/01/23/hogan-evening"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"專訪SiFive產品暨業務開發總監剛至堅　開源處理器生態系統邁開大步","spans":[]}],"deck":[{"type":"paragraph","text":"源自柏克萊大學的開放原始碼指令集架構(ISA)處理器RISC-V，目前已陸續獲得多家科技大廠支持，開始應用在自家產品中。為進一步推動RISC-V處理器的商業應用，由柏克萊教授與研究生共同創辦了一家名為SiFive的新創晶片設計服務公司，並獲得台積電大力奧援。目前SiFive已推出基於台積電0.18微米與28奈米製程的微控制器(MCU)與微處理器SoC平台。","spans":[{"start":0,"end":179,"type":"em"}]}],"source":"Micro-Electronics (Taiwanese Publication)","date":"2017-01-11","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.mem.com.tw/article_content.asp?sn=1611300020"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive rolls out fully open source chip for IoT devices","spans":[]}],"deck":[{"type":"paragraph","text":"In an interview, Jack Kang, VP of Product and Business Development at SiFive, discusses the FE310 chip, which will allow IoT vendors to build their own custom SoC on top of it","spans":[{"start":0,"end":175,"type":"em"}]},{"type":"paragraph","text":"SiFive is a relatively new fabless chip manufacturing startup that is developing fully open source chips. Its new FE310 chip is its first chip (and apparently the first open source chip) targeted at IoT devices.","spans":[{"start":0,"end":211,"type":"em"}]}],"source":"InfoWorld","date":"2017-01-04","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.infoworld.com/article/3155047/internet-of-things/sifive-rolls-out-fully-open-source-chip-for-iot-devices.html"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Hands On With The First Open Source Microcontroller","spans":[]}],"deck":[{"type":"paragraph","text":"2016 was a great year for Open Hardware. The Open Source Hardware Association released their certification program, and late in the year, a few silicon wizards met in Mountain View to show off the latest happenings in the RISC-V instruction set architecture.","spans":[{"start":0,"end":258,"type":"em"}]},{"type":"paragraph","text":"We’ve seen a lot of RISC-V stuff in recent months, from OnChip’s Open-V, and now the HiFive 1 from SiFive. The folks at SiFive offered to give me a look at the HiFive 1, so here it is, the first hands-on with the first Open Hardware microcontroller.","spans":[{"start":0,"end":249,"type":"em"}]}],"source":"Hackaday","date":"2017-01-04","cta_text":"Read More","link":{"link_type":"Web","url":"https://hackaday.com/2017/01/05/hands-on-with-the-first-open-source-microcontroller/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive: Low-Cost Custom Silicon","spans":[]}],"deck":[{"type":"paragraph","text":"One of the lessons learned years ago in the open-source Linux world is that free software isn’t always good enough. Consequently, being able to add commercial value around freeware can turn into a lucrative business.","spans":[{"start":0,"end":216,"type":"em"}]},{"type":"paragraph","text":"Enter SiFive, a startup that has been building customized platforms based on the RISC-V CPU. Started by the creators of the RISC V instruction set architecture (ISA), the company’s stated goal is to shake up the economics of the chip industry.","spans":[{"start":0,"end":243,"type":"em"}]}],"source":"SemiEngineering","date":"2017-01-03","cta_text":"Read More","link":{"link_type":"Web","url":"http://semiengineering.com/sifive-low-cost-custom-silicon/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Is Setting Silicon Free with Open-Source Chips","spans":[]}],"deck":[{"type":"paragraph","text":"Moore's Law is dead...just not in the way everyone thinks. Technological advances keep allowing chips to scale, but the economics are another story – particularly for smaller companies that can't afford chips in the volumes that the big chipmakers would like from their customers.","spans":[{"start":0,"end":280,"type":"em"}]},{"type":"paragraph","text":"The solution, according to San Francisco-based startup, SiFive, is open-source hardware, specifically an architecture developed by the company's founders called RISC-V (pronounced “risk-five”). Done right SiFive, which was awarded Startup of the Year at the 2016 Creativity in Electronics (ACE) Awards, believes that RISC-V will do for the hardware industry what Linux has done for software.","spans":[{"start":0,"end":391,"type":"em"}]}],"source":"Design News","date":"2016-12-15","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.designnews.com/electronics-test/sifive-setting-silicon-free-open-source-chips/10136142447173"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"UBM Announces 2016 ACE Award Winners","spans":[]}],"deck":[{"type":"paragraph","text":"The best and brightest were on display last night as UBM announced the 2016 Annual Creativity in Electronics (ACE) Awards winners during a ceremony held in conjunction with ESC Silicon Valley and BIOMEDevice San Jose. The awards, presented in partnership with EETimes and EDN, showcase the best in today’s electronics industry, including the hottest new products, start-ups, design teams, executives, and more.","spans":[{"start":0,"end":410,"type":"em"}]}],"source":"Design News","date":"2016-12-07","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.designnews.com/electronics-test/ubm-announces-2016-ace-award-winners/3686741846244"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Open Source RISC-V Architecture Makes Strides Towards Customizable SoCs","spans":[]}],"deck":[{"type":"paragraph","text":"The RISC-V footprint is expanding with the commercial availability of open-source chips and related development boards from silicon startups like SiFive and OnChip.","spans":[{"start":0,"end":164,"type":"em"}]},{"type":"paragraph","text":"The open-source hardware movement's journey from academia to the commercial realm is finally gaining some momentum. This is in large part thanks to free RISC-V instruction set architecture (ISA), which was developed at the University of California, Berkeley a few years ago.","spans":[{"start":0,"end":274,"type":"em"}]}],"source":"All About Circuits","date":"2016-12-06","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.allaboutcircuits.com/news/open-source-silicon-splash-aided-by-extensible-risc-v-architecture/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V Available in Silicon","spans":[]}],"deck":[{"type":"paragraph","text":"One of the announcements at the recent RISC-V workshop was by SiFive. This is the company started by the creators of the RISC-V instruction set architecture (Krste, Andrew, and Yunsup) to commercialize silicon implementations.","spans":[{"start":0,"end":226,"type":"em"}]},{"type":"paragraph","text":"Four months ago, at the previous RISC-V workshop, they announced FPGA implementations of the two flavors, Freedom Everywhere (16-bit microcontroller) and Freedom Unleashed (64-bit multi-core, high performance). They also announced that silicon would be coming \"soon.\"","spans":[{"start":0,"end":267,"type":"em"}]},{"type":"paragraph","text":"Well, it is now \"soon.\"","spans":[{"start":0,"end":23,"type":"em"}]}],"source":"Cadence","date":"2016-12-05","cta_text":"Read More","link":{"link_type":"Web","url":"https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2016/12/06/risc-v-sifive"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Will RISC-V Rescue the Internet of Things?","spans":[]}],"deck":[{"type":"paragraph","text":"In a nutshell, RISC-V is an instruction set architecture (ISA) that scales from 16-bit to 128-bit register platforms. The E310 is targets the Cortex-M0 space, but it can run at 320 MHz while sipping power—making it an interesting solution for the Internet of Things (IoT). The chip is available on the HiFive1 board ... that has an Arduino form factor.","spans":[{"start":0,"end":352,"type":"em"}]}],"source":"Electronic Design","date":"2016-12-04","cta_text":"Read More","link":{"link_type":"Web","url":"http://electronicdesign.com/blog/will-risc-v-rescue-internet-things"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Open Source SoC Debuts","spans":[]}],"deck":[{"type":"paragraph","text":"Startup SiFive started selling today a $59 Arduino board running its first RISC-V-based SoC and made open source RTL code available online for the chip. The news marks a milestone for a still nascent open source hardware movement.","spans":[{"start":0,"end":230,"type":"em"}]},{"type":"paragraph","text":"Open source cores have been available previously but they tended to be academic efforts or lacked broad commercial support. The HiFive board is intended to drive demand for custom SoCs SiFive will design and comes with a growing pool of open source Linux variants and tools fed by an expanding foundation that maintains the RISC-V instruction set.","spans":[{"start":0,"end":347,"type":"em"}]}],"source":"EE Times","date":"2016-11-28","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eetimes.com/document.asp?doc_id=1330905"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"HiFive1: RISC-V In An Arduino Form Factor","spans":[]}],"deck":[{"type":"paragraph","text":"The RISC-V ISA has seen an uptick in popularity as of late — almost as if there’s a conference going on right now — thanks to the fact that this instruction set is big-O Open. This openness allows anyone to build their own software and hardware. Of course, getting your hands on a RISC-V chip has until now, been a bit difficult. You could always go over to opencores, grab some VHDL, and run a RISC-V chip on an FPGA. Last week, OnChip released the RISC-V Open-V in real, tangible silicon.","spans":[{"start":0,"end":490,"type":"em"}]}],"source":"Hackaday","date":"2016-11-28","cta_text":"Read More","link":{"link_type":"Web","url":"http://hackaday.com/2016/11/29/hifive1-risc-v-in-an-arduino-form-factor/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Launches Open Source RISC-V Custom Chip","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive wants to democratize the custom chip business, and so today it is launching the industry’s first open-source RISC-V system-on-chip processor. The Freedom Everywhere 310 SoC and HiFive1 development board will enable a wide variety of system architects, embedded designers, and Internet of Things providers — people who normally have to rely on chip engineers for the detailed engineering work — to create their own products.","spans":[{"start":0,"end":431,"type":"em"}]}],"source":"VentureBeat","date":"2016-11-28","cta_text":"Read More","link":{"link_type":"Web","url":"http://venturebeat.com/2016/11/29/sifive-launches-open-source-risc-v-custom-chip/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Microsemi is First FPGA Provider to Offer Open Architecture RISC\u0026#8209;V IP Core and Comprehensive Software Solution for Embedded Designs","spans":[]}],"deck":[{"type":"paragraph","text":"Microsemi's new RV32IM RISC-V core, developed in collaboration with SiFive, enables customers to design with an open instruction set architecture (ISA), enabling complete portability and a more secure processor architecture governed by a permissive BSD license. RISC-V is a new ISA which is now a standard open architecture under the governance of the RISC-V Foundation. RISC-V offers a compelling soft processor solution for Microsemi's low power, reliable, secure FPGAs.","spans":[{"start":0,"end":472,"type":"em"}]}],"source":"PR Newswire","date":"2016-11-15","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.prnewswire.com/news-releases/microsemi-is-first-fpga-provider-to-offer-open-architecture-risc-v-ip-core-and-comprehensive-software-solution-for-embedded-designs-300363645.html"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive execs share ideas on their RISC-V strategy","spans":[]}],"deck":[{"type":"paragraph","text":"Since its formation just last year, SiFive has been riding the RISC-V rocket from purely academic interest to first commercialization. In an exclusive discussion, I talked with CEO Stefan Dyckerhoff and VP of Product and Business Development Jack Kang about their progress so far and what may be coming next.","spans":[{"start":0,"end":308,"type":"em"}]}],"source":"SemiWiki","date":"2016-10-02","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.semiwiki.com/forum/content/6257-sifive-execs-share-ideas-their-risc-v-strategy.html"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Back to the future for RISC","spans":[]}],"deck":[{"type":"paragraph","text":"In their 2014 technical report for the University of California at Berkeley, Krste Asanovic and Professor David Patterson – who developed the concepts behind the SPARC architecture in the 1980s – argued that, while there are good commercial reasons for processor makers to maintain proprietary instruction sets, there is no good technical reason for users to adopt them. Their proposal was for an instruction set architecture (ISA) offered on a similar basis to open source software that could stimulate an ecosystem similar to that built around Linux.","spans":[{"start":0,"end":552,"type":"em"}]},{"type":"paragraph","text":"As their proposal represented the fifth generation of RISC processor design, it was called RISC-V.","spans":[{"start":0,"end":98,"type":"em"}]}],"source":"New Electronics","date":"2016-09-26","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.newelectronics.co.uk/electronics-technology/back-to-the-future-for-risc/146172/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Creating the free-licensed semiconductor market","spans":[]}],"deck":[{"type":"paragraph","text":"As many would-be open hardware manufacturers have discovered, free-licensed computer chips are nearly non-existent. However, SiFive, a recently announced startup in San Francisco, is hoping to change that with its custom chip designs. SiFive has its origins in the RISC-V instruction set architecture (ISA) developed in the Computer Science Division of the Electrical Engineering and Computer Science Department at the University of California, Berkeley.","spans":[{"start":0,"end":454,"type":"em"}]}],"source":"Linux Pro Magazine","date":"2016-09-20","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.linuxpromagazine.com/Online/Features/SiFive"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"EE Times Silicon 60: 2016’s Emerging Companies to Watch","spans":[]}],"deck":[{"type":"paragraph","text":"It has been a year since EE Times produced a version16.1 of the Silicon 60. Over that time while the global economic situation can — at best — be said to have stabilized the semiconductor and electronics industries are on the edge of \"great expectations.” There seems no doubt that the Internet of Things will have a revolutionary impact on how people can live their lives, but exactly how that will manifest itself in terms of components, software, platforms, legal and business models, is not yet clear nor is the next big thing.","spans":[{"start":0,"end":531,"type":"em"}]}],"source":"EE Times","date":"2016-09-18","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eetimes.com/document.asp?doc_id=1330484"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Itching to Play With the Open-Source RISC-V Processor? Here Are Three Xilinx-Based Kits to Start With","spans":[]}],"deck":[{"type":"paragraph","text":"RISC-V (pronounced “risk five”) is an open, 32/64-bit RISC microprocessor architecture first developed at the Computer Science Division of the EECS Department at the U. of California, Berkeley. Now it’s managed by the RISC-V Foundation. If you are an aficionado of processor architectures and you’re looking to get your feet wet with the RISC-V architecture, SiFive has released three Freedom FPGA Platforms based on Xilinx All Programmable devices that allow you to start working with the RISC-V ISA immediately.","spans":[{"start":0,"end":513,"type":"em"}]}],"source":"Xilinx","date":"2016-09-07","cta_text":"Read More","link":{"link_type":"Web","url":"https://forums.xilinx.com/t5/Xcell-Daily-Blog/Itching-to-play-with-the-open-source-RISC-V-processor-Here-are/ba-p/722573"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive: A RISC-V Fabless Semiconductor Company","spans":[]}],"deck":[{"type":"paragraph","text":"A couple of weeks ago I talked to Krste Asanović and Jack Kang of SiFive. One of their motivations is to bring the cost reduction that goes along with open-source software (and instruction sets!) to the hardware world. There is an increasing move in this direction as companies like Facebook, IBM, and Google put parts of their server infrastructure into the public domain. This is especially important in semiconductors since Moore's law has run into a wall, at least economically, even though we have a couple more process generations coming at us.","spans":[{"start":0,"end":550,"type":"em"}]}],"source":"Cadence","date":"2016-09-06","cta_text":"Read More","link":{"link_type":"Web","url":"https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2016/09/07/sifive-a-risc-v-fabless-semiconductor-company"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V Gathering Momentum","spans":[]}],"deck":[{"type":"paragraph","text":"A week or so ago I talked to Krste Asanović, who is the UC Berkeley professor who led the project to define RISC-V, chairman of the RISC-V foundation, and in July co-founded a fabless semiconductor company, SiFive, to produce silicon implementations (and IP). I'll talk about SiFive in Breakfast Bytes one day next week. RISC-V has taken off strongly in academic circles due to its unrestricted availability compared to other instruction sets, which are often not really ideal for academic work, and/or come with legal encumbrance.","spans":[{"start":0,"end":531,"type":"em"}]}],"source":"Cadence","date":"2016-09-01","cta_text":"Read More","link":{"link_type":"Web","url":"https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2016/09/02/risc-v-gathering-momentum"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive – Freedom Family of RISC-V ISA-Based SoC Platforms","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive recently unveiled its flagship Freedom family of SoC platforms. Built around the RISC-V ISA invented by the company’s founders at the University of California, Berkeley, the Freedom U500 and Freedom E300 platforms represent a new approach to designing and producing SoCs that redefines traditional silicon business models and reverses prohibitively rising licensing, design and implementation costs.","spans":[{"start":0,"end":406,"type":"em"}]}],"source":"Pinestream Consulting Group","date":"2016-08-15","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.pinestream.com/profile/153092/SiFive/06362a7a"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Custom Silicon for Makers","spans":[]}],"deck":[{"type":"paragraph","text":"Makers are the epitome of what big chip vendors used to consider a waste of time for their valuable salesfolk. “Fred in the shed,” as they said. No volume, no ROI. “Stick with Tier 1s.”","spans":[{"start":0,"end":185,"type":"em"}]}],"source":"EE Journal","date":"2016-08-10","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eejournal.com/archives/articles/20160811-sifive/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Why the Time Is Right for Open Source to Meet Hardware","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive is a San Francisco-based fabless chip manufacturing startup that is developing the first fully open source chips. The company, which launched earlier this month, announced two chips of their flagship platform: Freedom U500 and Freedom E300, each targeting different audience.","spans":[{"start":0,"end":283,"type":"em"}]}],"source":"CIO","date":"2016-08-02","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.cio.com/article/3103964/cpu-processors/why-the-time-is-right-for-open-source-to-meet-hardware.html"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"An Open-Source SoCs with RISC-V From SiFive","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive, a startup from San Francisco, is trying to democratize the access to the world of SoC designing and manufacturing by giving the ability of customizing silicon to the smallest company, inventor, or maker, and taking “the hard parts of building chips working with 3rd part IP, EDA tools and foundries. SiFive is a fabless semiconductor company building customizable SoCs. SiFive takes benefits from using RISC-V in their SoC design. Some of inventors of the open source ISA RISC-V are behind SiFive.","spans":[{"start":0,"end":505,"type":"em"}]}],"source":"Electronics Lab","date":"2016-08-02","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.electronics-lab.com/open-source-socs-risc-v-sifive/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive More News","spans":[]}],"deck":[{"type":"paragraph","text":"As many of you may already know, SiFive is the first company that will make open source ISA Risc-V SoCs. What will be open and what not ? This was main question that people ask. In this video they answered that they will open as much as they can.PCI-E 3 controllers and some other 3-d party stuff will remain closed. They said time to develop some controllers and other 3d party tools and all to be open sourced will take ~ another 2 years of work.","spans":[{"start":0,"end":448,"type":"em"}]}],"source":"IOT-DEV.net","date":"2016-07-25","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.iot-dev.net/full.php?ar=63"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Introduces E300 \u0026 U500 Open-Source Chip Platforms","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive has introduced the Freedom family of open-source SoC-platform intellectual property based on the RISC-V instruction set architecture. The company offers the Freedom U500 and Freedom E300 processing platforms that are a new approach to designing and producing SoCs in that they are based on open-source and extensible architecture with no licensing fees.","spans":[{"start":0,"end":360,"type":"em"}]}],"source":"Electronics Products","date":"2016-07-21","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.electronicproducts.com/Digital_ICs/SoCs_ASICs_ASSPs_MEMS/SiFive_introduces_E300_amp_U500_open_source_chip_platforms.aspx"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive, STEM and Apple Reality TV","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive, a new Silicon Valley startup, is teaming up with RISC-V Foundation and the infrastructure set to develop open source chip products. Two chips are in development – Freedom Unleashed (designed for machine learning, storage and networking) and Freedom Everywhere (designed for low-power devices in the “Internet of Things” market). SiFive is trying to drive down the cost of chip manufacturing, open the industry up to designers and engineers, and squeeze into an industry that has several barriers of entry.","spans":[{"start":0,"end":513,"type":"em"}]}],"source":"ModernLife Network","date":"2016-07-18","cta_text":"Read More","link":{"link_type":"Web","url":"https://modernlifepodcastnetwork.com/sifive-stem-jobs-apple-reality-tv/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"California Dreaming: DIY, Open-Source SoCs With RISC-V","spans":[]}],"deck":[{"type":"paragraph","text":"With its customizable, open-source SoCs built on the free and open RISC-V instruction set architecture, SiFive, a San Francisco start-up, is poised to reverse the industry’s rising licensing, design and implementation costs. System designers can use the SiFive Freedom platforms to focus on their own differentiated processor without having the overhead of developing a modern SoC, fabric or software infrastructure.","spans":[{"start":0,"end":416,"type":"em"}]}],"source":"Elektor Magazine","date":"2016-07-18","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.elektormagazine.com/news/california-dreaming-diy-open-source-socs-with-risc-v"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Unveils Freedom Platforms for RISC-V-Based Semi-Custom Chips","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive, a company established by researchers who invented the RISC-V instruction set architecture in the University of California Berkeley several years ago, has this week announced two platforms which could be used to design semi-custom SoCs based on RISC-V cores.","spans":[{"start":0,"end":265,"type":"em"}]}],"source":"AnandTech","date":"2016-07-17","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.anandtech.com/show/10488/sifive-unveils-freedom-platforms-for-riscvbased-semicustom-chips"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V Startup Aims to Democratize Silicon","spans":[]}],"deck":[{"type":"paragraph","text":"Momentum for open source hardware made a significant step this week with the launch of startup SiFive and its open source chip platforms based on the RISC-V instruction set architecture. The founders of the fabless semiconductor company — Krste Asanovic, Andrew Waterman, and Yunsup Lee — invented the free and open RISC-V ISA at the University of California, Berkeley, six years ago.","spans":[{"start":0,"end":384,"type":"em"}]}],"source":"HPCwire","date":"2016-07-12","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.hpcwire.com/2016/07/13/risc-v-startup-aims-democratize-silicon/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Launches Freedom FOSS SoC Platforms","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive on Monday announced its flagship Freedom family of system on a chip platforms. The platforms are based on the free and open source RISC-V instruction set architecture that several of the company's founders created at the University of California at Berkeley. SiFive's Freedom U500 and E300 platforms take a new approach to SoCs, redefining traditional silicon business models and reversing the industry's increasingly high licensing, design and implementation costs.","spans":[{"start":0,"end":473,"type":"em"}]}],"source":"Linux Insider","date":"2016-07-12","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.linuxinsider.com/story/83689.html"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Introduces Freedom U500 and E500 Open Source RISC-V SoCs","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive, a startup founded by the creators of the free and open RISC-V architecture, has announced two open source SoCs with Freedom U500 processor and Freedom E300 micro-controller. Three real-time operating systems, including FreeRTOS, have already been ported to Freedom E300 for embedded micro-controllers, IoT, and wearable markets.","spans":[{"start":0,"end":336,"type":"em"}]},{"type":"paragraph","text":"CNXSoft","spans":[]}],"source":"CNXSoft","date":"2016-07-11","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.cnx-software.com/2016/07/12/sifive-introduces-freedom-u500-and-e500-open-source-risc-v-socs/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive brings open-source SoCs","spans":[]}],"deck":[{"type":"paragraph","text":"It has developed customizable, open-source SoCs built on the free and open RISC-V instruction set architecture. “The semiconductor industry is at an important crossroads. Moore’s Law has ended, and the traditional economic model of chip building no longer works,” said Yunsup Lee, co-founder of SiFive and one of the original creators of RISC-V at UC Berkeley.","spans":[{"start":0,"end":360,"type":"em"}]}],"source":"Electronics Weekly","date":"2016-07-11","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.electronicsweekly.com/news/business/sifive-shipping-socs-with-risc-v-cores-2016-07/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"First SoCs Based on Open Source RISC-V Run Linux","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive unveiled the first embedded SoCs based on the open source RISC-V platform: A Linux-ready octa-core Freedom U500 and a FreeRTOS-based Freedom E300. A VC-backed startup closely associated with the RISC-V project announced the first system-on-chip implementations of the open source RISC-V processor platform.","spans":[{"start":0,"end":313,"type":"em"}]}],"source":"HackerBoards","date":"2016-07-11","cta_text":"Read More","link":{"link_type":"Web","url":"https://linuxgizmos.com/first-socs-based-on-open-source-risc-v-run-linux/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Comes with World First U500 and U300 Open Source RISC-V SoCs","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive will publish specifications for an SoC based high-performance Unix-capable cache-coherent 64-bit multiprocessor U500 and one using a microcontroller core E300 both based on work of the RISC-V Foundation. The U500 platform is the first member of SiFive's Freedom Unleashed family of customizable RISC-VSoCs. Freedom Un-leashed family reduces NRE and time-to-market for customized SoCs in diverse markets such as machine learning, storage and networking.","spans":[{"start":0,"end":459,"type":"em"}]}],"source":"IOT-DEV.net","date":"2016-07-11","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.iot-dev.net/full.php?ar=51"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"L'Américain SiFive se lance dans la conception de puces open source","spans":[]}],"deck":[{"type":"paragraph","text":"Un groupe de chercheurs de l'Université de Californie lançait en avril dernier une fondation visant à porter un projet d'architecture de processeur open source (le projet RISC-V). Ces chercheurs passent maintenant à la vitesse supérieure : ils lancent une entreprise, baptisée SiFive, visant à commercialiser leur technologie. SiFive doit développer des puces reposant sur l'architecture open source RISC-V.","spans":[{"start":0,"end":407,"type":"em"}]}],"source":"Journal Dunet (French Publication)","date":"2016-07-11","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.journaldunet.com/solutions/cloud-computing/1181918-sifive-commercialise-une-puce-open-source/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Launches a Line of Open Source Chips","spans":[]}],"deck":[{"type":"paragraph","text":"A San Francisco-based company known as SiFive is trying to bring the open source development model to the chip industry. The company has announced its first Freedom family of system-on-a-chip (SoC) products, including the Freedom U500 and Freedom E300 platforms. SiFive is a fabless semiconductor company, similar to AMD. The company doesn’t fabricate the chip but outsources it to manufacturers.","spans":[{"start":0,"end":396,"type":"em"}]}],"source":"Linux Magazine","date":"2016-07-11","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.linux-magazine.com/Online/News/SiFive-Launches-a-Line-of-Open-Source-Chips"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Startup Releases Open Source System-on-Chip","spans":[]}],"deck":[{"type":"paragraph","text":"Fabless semiconductor company SiFive has announced a new system on a chip platform that takes the SoC platform into the realm of open-source. The RISC-V instruction set architecture was originally developed by SiFive’s founders at the University of California, Berkeley, and has now been packaged into the Freedom U500 and Freedom E300 platforms.","spans":[{"start":0,"end":346,"type":"em"}]}],"source":"Product Design and Development","date":"2016-07-11","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.pddnet.com/news/2016/07/startup-releases-open-source-system-chip"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Eyes Silicon Reset With RISC-V","spans":[]}],"deck":[{"type":"paragraph","text":"A San Francisco-based startup known as SiFive has announced plans to develop and sell chips based on open-source RISC-V architecture. According to Don Clark of the Wall Street Journal, the tech includes a set of instructions that define the functions of a microprocessor, which can serve as a starting point for designing a chip.","spans":[{"start":0,"end":329,"type":"em"}]}],"source":"Rambus","date":"2016-07-11","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.rambusblog.com/2016/07/12/sifive-eyes-silicon-reset-with-risc-v/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Backers of Open Source Chips Launch Startup","spans":[]}],"deck":[{"type":"paragraph","text":"A group of university researchers recently attracted attention by applying principles of open-source software to computer chips. Now they’re turning the concept into a company. A San Francisco-based startup called SiFive on Monday is announcing plans to develop and sell chips based on a technology called RISC-V. The tech includes a set of instructions that define the functions of a microprocessor, which can serve as a starting point for designing a chip.","spans":[{"start":0,"end":458,"type":"em"}]}],"source":"Wall Street Journal","date":"2016-07-10","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.wsj.com/articles/backers-of-open-source-chips-launch-startup-1468242001"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"This New Chip Startup Wants To Bring Open Source To A Stagnant Industry","spans":[]}],"deck":[{"type":"paragraph","text":"Open source has taken off in the software world. RISC-V maybe has the opportunity to bring open source to the rigid chip industry. Born out of university research, RISC-V is a chip architecture that lets developers freely change and customize chip designs without having to pay for expensive licenses or royalty fees.","spans":[{"start":0,"end":317,"type":"em"}]}],"source":"Forbes","date":"2016-07-10","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.forbes.com/sites/aarontilley/2016/07/11/risc-v-sifive-chips/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V opens for business with SiFive Freedom","spans":[]}],"deck":[{"type":"paragraph","text":"When we talk about open source, free usually comes in the context of “freedom”, not as in “free beer”, and open IP often serves as a base layer of value add for commercialization. The creators of the RISC-V instruction set, now working at startup SiFive, have released specifications for their aptly-named Freedom processor IP cores looking for \"enablement of great ideas\".","spans":[{"start":0,"end":373,"type":"em"}]}],"source":"SemiWiki","date":"2016-07-10","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.semiwiki.com/forum/content/5978-risc-v-opens-business-sifive-freedom.html"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Startup SiFive Aims for Open-Source Chips","spans":[]}],"deck":[{"type":"paragraph","text":"The open-source RISC-V chip architecture was created to help developers more easily and cheaply customize processors that run their devices, and last year an industry consortium was formed around the technology. Now the inventors of RISC-V want to see if they can build a business based on the architecture.","spans":[{"start":0,"end":307,"type":"em"}]}],"source":"eWEEK","date":"2016-07-10","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eweek.com/developer/startup-sifive-aims-for-open-source-chips.html"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Startup Debuts Open Source SoCs","spans":[]}],"deck":[{"type":"paragraph","text":"A startup aims to help a broader set of engineers roll their own silicon using its customizable open-source systems-on-chips. SiFive will publish specifications for an SoC based on an embedded Linux processor core and one using a microcontroller core both based on work of the RISC-V Foundation.","spans":[{"start":0,"end":295,"type":"em"}]}],"source":"EE Times","date":"2016-07-10","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eetimes.com/document.asp?doc_id=1330086"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Opens Up Silicon Access With Freedom E300 and U500","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive is unveiling two open source RISC-V based platforms today called the Freedom U500 and E300 Series. SemiAccurate thinks what SiFive is doing has a good chance of changing how the silicon market works.","spans":[{"start":0,"end":206,"type":"em"}]}],"source":"SemiAccurate","date":"2016-07-10","cta_text":"Read More","link":{"link_type":"Web","url":"http://semiaccurate.com/2016/07/11/sifive-opens-silicon-access-freedom-e300-u500/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Startup Takes a Risk on RISC-V Custom Silicon","spans":[]}],"deck":[{"type":"paragraph","text":"As we are carefully watching here, there is a perfect storm brewing in the semiconductor space, both for manufacturers and system designers.","spans":[{"start":0,"end":140,"type":"em"}]}],"source":"The Next Platform","date":"2016-07-10","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.nextplatform.com/2016/07/11/startup-takes-risk-risc-v-custom-silicon/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Will Open-Source Work For Chips?","spans":[]}],"deck":[{"type":"paragraph","text":"Open source is getting a second look by the semiconductor industry, driven by the high cost of design at complex nodes along with fragmentation in end markets, which increasingly means that one size or approach no longer fits all.","spans":[{"start":0,"end":230,"type":"em"}]}],"source":"SemiEngineering","date":"2016-06-29","cta_text":"Read More","link":{"link_type":"Web","url":"http://semiengineering.com/will-open-source-work-for-chips/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V—Instruction Sets Want to Be Free","spans":[]}],"deck":[{"type":"paragraph","text":"I had never heard of RISC-V (pronounced five, not vee) until earlier this year when there was a presentation about it at EDPS in Monterey. I immediately texted the daughter of a friend of mine who is a CS major at Berkeley where it originated and she gave me a bit more background.","spans":[{"start":0,"end":281,"type":"em"}]}],"source":"Cadence Blogs","date":"2016-06-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2016/06/17/risc-v"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Alternative To X86, Arm Architectures?","spans":[]}],"deck":[{"type":"paragraph","text":"Software developed by professors and graduate students from the University of California at Berkeley? That will never fly in the semiconductor industry, right?","spans":[{"start":0,"end":159,"type":"em"}]}],"source":"SemiEngineering","date":"2016-06-06","cta_text":"Read More","link":{"link_type":"Web","url":"http://semiengineering.com/an-alternative-to-x86-arm-architectures/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Can Open Source Hardware Crack Semiconductor Industry Economics?","spans":[]}],"deck":[{"type":"paragraph","text":"The running joke is that when a headline begs a question, the answer is, quite simply, “No.” However, when the question is multi-layered, wrought with dependencies that stretch across an entire supply chain, user bases, and device range, and across companies in the throes of their own economic and production uncertainties, a much more nuanced answer is required.","spans":[{"start":0,"end":364,"type":"em"}]}],"source":"Next Platform","date":"2016-05-15","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.nextplatform.com/2016/05/16/can-open-source-hardware-crack-semiconductor-industry-economics/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V Offers Simple, Modular ISA","spans":[]}],"deck":[{"type":"paragraph","text":"RISC-V is a new general-purpose instruction-set architecture (ISA) that’s BSD licensed, extensible, and royalty free. It’s clean and modular with a 32-, 64-, or 128-bit integer base and various optional extensions (e.g., floating point). RISC-V is easier to implement than some alternatives—minimal RISC-V cores are roughly half the size of equivalent ARM cores—and the ISA has already gathered some support from the semiconductor industry.","spans":[{"start":0,"end":440,"type":"em"}]}],"source":"Linley Group","date":"2016-03-31","cta_text":"Read More","link":{"link_type":"Web","url":"https://riscv.org/2016/04/risc-v-offers-simple-modular-isa/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V Inching Closer to Reality at Scale","spans":[]}],"deck":[{"type":"paragraph","text":"Back in the early 1990s, the common view was that there was little money to be made in the business of open source. As the wave of Linux distributions rolled forth, however, that was quickly disproven, setting the decades-long chain of companies that have secured their footing, funding, and futures on the back of open software.","spans":[{"start":0,"end":329,"type":"em"}]}],"source":"Next Platform","date":"2016-03-07","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.nextplatform.com/2016/03/08/risc-v-inching-closer-to-reality-at-scale/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Charting a New Course for Semiconductors","spans":[]}],"deck":[],"source":"Global Semiconductor Alliance","date":"2016-03-02","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.gsaglobal.org/gsa-resources/publications/charting-a-new-course-for-semicoductors/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Chip Makers Need New Business Models","spans":[]}],"deck":[],"source":"EE Times","date":"2016-03-01","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eetimes.com/author.asp?doc_id=1329078"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"India Preps RISC-V Processors","spans":[]}],"deck":[],"source":"EE Times","date":"2016-01-26","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eetimes.com/document.asp?doc_id=1328790"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Open Source RISC-V Core Designs, Why Google Cares and Why They Matter","spans":[]}],"deck":[],"source":"XDA Developers","date":"2016-01-07","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.xda-developers.com/risc-v-cores-and-why-they-matter/"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Google, HP, Oracle Join RISC-V","spans":[]}],"deck":[],"source":"EE Times","date":"2015-12-27","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eetimes.com/document.asp?doc_id=1328561"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V: An Open Standard for SoCs","spans":[]}],"deck":[{"type":"paragraph","text":"Just as Linux has become the standard OS for most computing devices, Berkeley researchers envision RISC-V becoming the standard ISA for all computing...","spans":[{"start":0,"end":152,"type":"em"}]}],"source":"EE Times","date":"2014-08-06","cta_text":"Read More","link":{"link_type":"Web","url":"http://www.eetimes.com/author.asp?doc_id=1323406"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Raises $50.6 Million to Recreate Chip Prototyping ","spans":[]}],"deck":[{"type":"paragraph","text":"The RISC-V architecture is making an impression. That was reflected Monday in the announcement of $50.6 million raised by SiFive, a semiconductor startup that has been leveraging the free and open source architecture to reduce the cost and manpower required for chip development.","spans":[{"start":0,"end":279,"type":"em"}]}],"source":"Electronic Design","date":"2018-04-05","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.electronicdesign.com/technologies/embedded-revolution/article/21806355/sifive-raises-506-million-to-recreate-chip-prototyping","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Media Alert: Rambus to Demo CryptoManager Root of Trust at the RISC-V Summit in Santa Clara","spans":[]}],"deck":[{"type":"paragraph","text":"At the RISC-V Summit, Rambus is demonstrating our programmable root of trust core that provides secure processing based on the RISC-V architecture and incorporating industry-leading hardware security and anti-tamper capabilities. The Rambus CryptoManager Root of Trust is designed for applications from networking to automotive to IoT.","spans":[{"start":0,"end":335,"type":"em"}]}],"source":"Rambus","date":"2018-12-03","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.businesswire.com/news/home/20181203005034/en/Media-Alert-Rambus-to-Demo-CryptoManager-Root-of-Trust-at-the-RISC-V-Summit-in-Santa-Clara","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Raises RISC-V Performance","spans":[]}],"deck":[{"type":"paragraph","text":"Series 7 Comprises First Superscalar RISC-V CPUs","spans":[{"start":0,"end":48,"type":"em"}]}],"source":"Linley Group","date":"2018-11-12","cta_text":"Read More","link":{"link_type":"Media","kind":"file","id":"XBKwTBAAACQAaMyI","url":"https://sifive.cdn.prismic.io/sifive%2F5ec09861-351b-420c-b6e3-e2b76843044f_linley+report+-+sifive+raises+risc-v+performance.pdf","name":"Linley Report - SiFive Raises RISC-V Performance.pdf","size":"538940"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Portfolio Watch: By Democratizing Custom Silicon, SiFive Is Igniting Global Innovation in the Semiconductor Industry and Beyond","spans":[]}],"deck":[{"type":"paragraph","text":"What if anyone could afford to build customized chips? And what if it was as easy as pushing a button?","spans":[{"start":0,"end":102,"type":"em"}]}],"source":"Qualcomm Ventures","date":"2019-06-07","cta_text":"Read More","link":{"link_type":"Web","url":"https://insights.qualcommventures.com/portfolio-watch-by-democratizing-custom-silicon-sifive-is-igniting-global-innovation-in-the-c565eeab1cbd?postPublishedType=initial","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Morse Micro Partners with SiFive to Host Tech Symposium on RISC-V in Sydney","spans":[]}],"deck":[{"type":"paragraph","text":"Powerful and engaging one-day event fosters education and collaboration within the RISC-V ecosystem.","spans":[{"start":0,"end":100,"type":"em"}]}],"source":"ChipEstimate","date":"2019-06-18","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.chipestimate.com/Morse-Micro-Partners-with-SiFive-to-Host-Tech-Symposium-on-RISC-V-in-Sydney/Semiconductor-IP-Core/news/49005","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Celebrates Historic 100 Design Win Milestone","spans":[]}],"deck":[{"type":"paragraph","text":"Compelling Portfolio and Strategic Partnerships Propel RISC-V Leader into Hypergrowth","spans":[{"start":0,"end":85,"type":"em"}]}],"source":"SiFive","date":"2019-06-06","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.sifive.com/press/sifive-celebrates-historic-100-design-win-milestone"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Qualcomm Backs Startup Taking On SoftBank-Owned Arm","spans":[]}],"deck":[{"type":"paragraph","text":"An emerging open source chip design, called RISC-V, appears to be picking up steamin the tech industry, changing how companies make custom chips, and one of the technology’s leading startups is growing fast along with it","spans":[{"start":0,"end":222,"type":"em"}]}],"source":"The Information","date":"2019-06-06","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.theinformation.com/articles/qualcomm-backs-startup-taking-on-softbank-owned-arm?shared=1aed906297236299https://","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Recognized as Most Respected Private Semiconductor Company","spans":[]}],"deck":[{"type":"paragraph","text":"RISC-V leader honored for its products, growth and performance by Global Semiconductor Alliance","spans":[{"start":0,"end":95,"type":"em"}]}],"source":"SiFive","date":"2018-12-11","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.sifive.com/press/sifive-recognized-as-most-respected-private-semiconductor"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V grows globally as an alternative to Arm and it’s licensing fees","spans":[]}],"deck":[{"type":"paragraph","text":"ARM is the most successful microprocessor architecture on the planet, with its licensees shipping billions of chips a year. But a rival has emerged in the past few years called RISC-V, a new kind of royalty-free architecture started by academics. Its proponents are holding an event in the heart of Silicon Valley to tout its growth","spans":[{"start":0,"end":332,"type":"em"}]}],"source":"Venturebeat","date":"2019-12-11","cta_text":"Read More","link":{"link_type":"Web","url":"https://venturebeat.com/2019/12/11/risc-v-grows-globally-as-an-alternative-to-arm-and-its-license-fees/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V Xmas gifts: SiFive Emits Vector Enabled Cores","spans":[]}],"deck":[{"type":"paragraph","text":"The RISC-V Summit kicks off in Silicon Valley today, and there were a few interesting announcements this morning","spans":[{"start":0,"end":112,"type":"em"}]}],"source":"TheRegister","date":"2019-12-10","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.theregister.co.uk/2019/12/10/riscv_sifive_western_digital/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Key Takeways from the 2019 RISC-V Summit","spans":[]}],"deck":[{"type":"paragraph","text":"This week in San Jose, California I had the opportunity to join the 2019 RISC-V Summit. I wanted to do a short piece giving some thoughts on the summit itself while also covering a few of the big announcements from Western Digital, Microchip, and SiFive","spans":[{"start":0,"end":253,"type":"em"}]}],"source":"ServeTheHome","date":"2019-12-14","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.servethehome.com/key-takeaways-from-the-2019-risc-v-summit/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Wind River Announces RISC-V Support for VxWorks RTOS","spans":[]}],"deck":[{"type":"paragraph","text":"Wind River, a developer of software for the intelligent edge, announced RISC-V open architecture support for its VxWorks real-time operating system (RTOS)","spans":[{"start":0,"end":154,"type":"em"}]}],"source":"Embedded Computing Design","date":"2019-12-11","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.embedded-computing.com/hardware/wind-river-announces-risc-v-support-for-vxworks-rtos","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Brekker RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis","spans":[]}],"deck":[{"type":"paragraph","text":"Breker Verification Systems, a provider of Test Suite Synthesis tools based on the Portable Stimulus Standard (PSS), introduced its RISC-V TrekApp","spans":[{"start":0,"end":146,"type":"em"}]}],"source":"Embedded Computing Design","date":"2019-12-12","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.embedded-computing.com/home-page/brekerverificationsystemslaunchesrisc-vtrekappforautomatedhigh-coveragesystemintegrationtestsuitesynthesis","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V business: SiFive and CEVA join forces to enable the development AI-amenable, edge-oriented processors","spans":[]}],"deck":[{"type":"paragraph","text":"System-on-a-chip IP partnership seeks to create more smart home, automobile, robotics, IoT, and industrial applications, among others","spans":[{"start":0,"end":133,"type":"em"}]}],"source":"TheRegister","date":"2020-01-08","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.theregister.co.uk/2020/01/08/riscv_sifive_ceva/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"GLOBALFOUNDRIES and SiFive to Deliver Next Level of High Bandwidth Memory on 12LP Platform for AI Applications","spans":[]}],"deck":[{"type":"paragraph","text":"Next generation high bandwidth memory solution based on GF’s most advanced FinFET platform aims to deliver capacity, speed and power for cloud based AI Applications","spans":[{"start":0,"end":164,"type":"em"}]}],"source":"GLOBALFOUNDRIES (GF)","date":"2019-11-05","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.globalfoundries.com/news-events/press-releases/globalfoundries-and-sifive-deliver-next-level-high-bandwidth-memory-12lp","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Selects Synopsys Fusion Design Platform and Verification Continuum Platform to Enable Rapid SoC Design","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive, Inc. has selected Synopsys Fusion Design Platform™ and Verification Continuum® platform to enable rapid cloud-based design of next-generation customer silicon products.","spans":[{"start":0,"end":176,"type":"em"}]}],"source":"Synopsys","date":"2020-03-25","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.prnewswire.com/news-releases/sifive-selects-synopsys-fusion-design-platform-and-verification-continuum-platform-to-enable-rapid-soc-design-301029184.html"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Green Hills Software Adds Industry-Leading Advanced Software Development Tools Support for RISC-V","spans":[]}],"deck":[{"type":"paragraph","text":"Green Hills Software, the worldwide leader in embedded safety and security, today announced the availability and early customer adoption of its advanced software development tools targeting 32- and 64-bit RISC-V processor architectures.","spans":[{"start":0,"end":236,"type":"em"}]}],"source":"Green Hills Software","date":"2020-06-02","cta_text":"Learn more from Green Hills Software","link":{"link_type":"Web","url":"https://www.ghs.com/news/20200602_RISC-V_tools_support.html","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Special COVID-19 Edition of Embedded Executive featuring SiFive CEO, Dr. Naveed Sherwani","spans":[]}],"deck":[{"type":"paragraph","text":"Different vendors are doing different things to cope with the COVID-19 pandemic. Many of them are doing their part to help get us through this awful time. One of those is SiFive, a fabless semiconductor company specializing in the RISC-V instruction set architecture. Hear what they are doing to help society in this week’s Embedded Executives podcast.","spans":[{"start":0,"end":352,"type":"em"}]}],"source":"Embedded Computing Design","date":"2020-06-24","cta_text":"Listen now with Embedded Computing Design","link":{"link_type":"Web","url":"https://www.embedded-computing.com/embedded-insiders/special-covid-19-edition-of-embedded-executive-naveed-sherwani-ceo-sifive","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"IAR Systems delivers advanced trace for RISC-V based applications","spans":[]}],"deck":[{"type":"paragraph","text":"Enhanced support for the SiFive Insight solution in IAR Embedded Workbench brings leading debug and trace capabilities to the RISC-V community","spans":[{"start":0,"end":142,"type":"em"}]}],"source":"IAR Systems","date":"2020-06-24","cta_text":"Learn more from IAR Systems","link":{"link_type":"Web","url":"https://www.iar.com/about-us/newsroom/press/?releaseId=3702222","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive named to EETimes 2020 'Silicon 100' List","spans":[]}],"deck":[{"type":"paragraph","text":"The EETimes Silicon 100 is a place identify the building blocks for future wonders: the daring innovators, fervent visionaries, serial investors, and barrier-busting men and women who have collectively given the world inventions that were unimaginable barely 100 years ago. ","spans":[{"start":0,"end":275,"type":"em"}]}],"source":"EETimes","date":"2020-06-28","cta_text":"Explore the Silicon 100 List at EETimes","link":{"link_type":"Web","url":"https://www.eetimes.com/books/silicon-100-emerging-startups-to-watch/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"H3C Creates Research Network Processor using U7-Series Core IP","spans":[]}],"deck":[{"type":"paragraph","text":"The new development chip from H3C Semiconductor Technology is a dual-core design with 400G Ethernet interface built using TSMC 16nm FinFET Compact Technology (FFC) process technology, and was able to run at up to 3.2GHz.","spans":[{"start":0,"end":220,"type":"em"}]}],"source":"StarFive (China)","date":"2020-07-27","cta_text":"Press Release","link":{"link_type":"Web","url":"http://translate.google.com/translate?js=n\u0026sl=auto\u0026tl=destination_language\u0026u=https://mp.weixin.qq.com/s/az5VoyNFZsON3JUOrfFjUg","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"ISA-agnostic OpenFive unit will focus on custom SoCs while parent will crack on with CPU blueprints","spans":[]}],"deck":[{"type":"paragraph","text":"RISC-V processor specialist SiFive will double down on improving its CPU cores after pushing its system-on-chip design efforts into a new unit.","spans":[{"start":0,"end":143,"type":"em"}]}],"source":"The Register","date":"2020-08-17","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.theregister.com/2020/08/17/sifive_openfive/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Wins 3rd Consecutive Global Semiconductor Alliance 'Most Respected Private Company' Award!","spans":[]}],"deck":[{"type":"paragraph","text":"For over a quarter century, the GSA Awards have recognized the achievements of top performing semiconductor companies in several categories ranging from outstanding leadership to financial accomplishments, as well as overall respect within the industry.","spans":[{"start":0,"end":253,"type":"em"}]}],"source":"Global Semiconductor Alliance","date":"2020-12-03","cta_text":"Watch Award Presentation Here","link":{"link_type":"Web","url":"https://youtu.be/Wcr_9Qq2CA0","target":"_blank"},"featured":"yes","publish_to":"Archive"},{"title":[{"type":"heading1","text":"BeagleV™ single-board computer features SiFive 7-Series Multicore RISC-V Processor IP","spans":[]}],"deck":[{"type":"paragraph","text":"Seeed, BeagleBoard.org, and StarFive are collaborating to produce an affordable, Linux-capable 64-bit multicore RISC-V single board computer at an affordable price, using SiFive U74-MC Core IP","spans":[{"start":0,"end":192,"type":"em"}]}],"source":"BusinessWire","date":"2021-01-13","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.businesswire.com/news/home/20210113005169/en/BeagleBoard.org%C2%AE-and-Seeed-Introduce-the-First-Affordable-RISC-V-Board-Designed-to-Run-Linux","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"eTopus Technology Announces Innovative SerDes Technology for Data Center, Cloud, Edge, and 5G Base Stations","spans":[]}],"deck":[{"type":"paragraph","text":"Danfeng Xu, co-founder \u0026 VP of analog design, will present the paper titled “A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm” in the 2021 International Solid-State Circuits Virtual Conference Ultra-High-Speed Wireline session beginning on Tuesday, February 16th, 2021. The eTopus high-speed transceiver architecture supports a wide range of data rates for multiple standards, such as Ethernet, OIF CEI-112G, PCI-SIG® PCIe® Gen 1 through 6, and insertion loss from few to above 35dB. eTopus has selected SiFive E2-Series RISC-V Core IP to power the receiver DSP control functions.","spans":[{"start":0,"end":673,"type":"em"},{"start":227,"end":285,"type":"hyperlink","data":{"link_type":"Web","url":"https://cts.businesswire.com/ct/CT?id=smartlink\u0026url=http%3A%2F%2Fisscc.org%2F\u0026esheet=52376099\u0026newsitemid=20210210005035\u0026lan=en-US\u0026anchor=2021+International+Solid-State+Circuits+Virtual+Conference\u0026index=1\u0026md5=e3ce21946b96ed5d5a921cf0e47fa890","target":"_blank"}}]}],"source":"eTopus","date":"2021-02-10","cta_text":"Read More","link":{"link_type":"Web","url":"https://etopus.com/etopus-presents-innovative-serdes-technology-at-isscc-2021/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"ArchiTek announces \"AiOnIc\" AI processor for edge computing using \"aIPE\" architecture combined with SiFive RISC-V processor cores","spans":[]}],"deck":[{"type":"paragraph","text":"ArchiTek announces \"AiOnIc\" proof-of-concept chip equipped with its own \"aIPE\" (ArchiTek Intelligence® Pixel Engine) architecture and featuring SiFive RISC-V Processor cores. The chip aims to be the de facto edge AI processor through offering fanless operation in a small size and low power consumption, using a 12nm process. Highly efficient hardware processing makes it ideal for embedded systems such as IoT. In addition, a cooling fan is not required, and a waterproof and dustproof system can be constructed in a closed housing. ","spans":[{"start":0,"end":534,"type":"em"}]}],"source":"PRTimes (JP)","date":"2021-02-08","cta_text":"Read More (Japanese)","link":{"link_type":"Web","url":"https://translate.google.com/translate?js=n\u0026sl=auto\u0026tl=destination_language\u0026u=https://prtimes.jp/main/html/rd/p/000000005.000052561.html","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"aicas and SiFive Bridge Flexibility and Performance with RISC-V, JamaicaVM Integration","spans":[]}],"deck":[{"type":"paragraph","text":"Together with Amazon Web Services (AWS), SiFive and aicas will deliver a virtual demonstration of the solution during embedded world 2021 DIGITAL, March 1-5, 2021. See aicas events online for details about the demo of AWS IoT Greengrass 2.0 running on a SiFive RISC-V unmatched board and go to aicas’ virtual exhibition stand and claim a voucher for a free ticket to attend the virtual event","spans":[{"start":0,"end":391,"type":"em"}]}],"source":"aicas","date":"2021-02-18","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.aicas.com/wp/jamaicavm-risc-v/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Wanxiang Blockchain Forms RISC-V International Blockchain SIG with SiFive \u0026 Others","spans":[]}],"deck":[{"type":"paragraph","text":"At MWC Shanghai, Wanxiang Blockchain and aitos.io announced they joined RISC-V International as strategic members and have formed RISC-V International’s new Blockchain SIG (special interest group) in collaboration with LeapFive, StarFive and SiFive. This group will help integrate blockchain technologies with RISC-V solutions, and promote the development of trusted blockchain databases.","spans":[{"start":0,"end":388,"type":"em"}]},{"type":"paragraph","text":"“The adoption of RISC-V to develop blockchain technologies, and the use of RISC-V International working groups to encourage broad industry collaboration, demonstrates the power and flexibility of the freely available and open specification ISA,” said Dr. Chris Lattner, President of Engineering and Product, SiFive.","spans":[{"start":0,"end":315,"type":"em"}]}],"source":"Wanxiang Blockchain on Medium","date":"2021-02-23","cta_text":"Read More","link":{"link_type":"Web","url":"https://wxblockchain.medium.com/wanxiang-blockchain-forms-risc-v-international-blockchain-sig-with-ecosystem-partners-524b9201f60c","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"AWS IoT at Embedded World 2021 DIGITAL Features SiFive HiFive Unmatched","spans":[]}],"deck":[{"type":"paragraph","text":"Building a successful IoT solution depends on the tens of billions of devices that sit at the edge, in our homes and offices, in factories, in oil and agricultural fields, in planes and ships, in automobiles — everywhere. Quickly start building with solutions for cross-industry edge applications using the SiFive HiFive Unmatched developer board, as featured in the demonstrations.","spans":[{"start":0,"end":382,"type":"em"}]}],"source":"AWS IoT","date":"2021-02-25","cta_text":"Learn More","link":{"link_type":"Web","url":"https://pages.awscloud.com/embeddedworld21.html","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"A Number Of Exciting RISC-V Improvements For Linux 5.13","spans":[]}],"deck":[{"type":"paragraph","text":"From bringing up the PolarFire ICICLE SoC to adding support for KProbes, FORTIFY_SOURCE, and other new kernel features for the RISC-V architecture, the Linux 5.13 kernel changes are exciting for this open-source processor ISA.","spans":[{"start":0,"end":226,"type":"em"},{"start":152,"end":162,"type":"hyperlink","data":{"link_type":"Web","url":"https://www.phoronix.com/scan.php?page=search\u0026q=Linux+5.13"}}]}],"source":"Phoronix","date":"2021-05-06","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.phoronix.com/scan.php?page=news_item\u0026px=Linux-5.13-RISC-V","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive 21G1 Update Boosts Hash Rates","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive’s intellectual-property (IP) portfolio is getting smarter thanks to its “Intelligence” platform and 21G1 release. At the recent Linley Spring Processor Conference, the company announced a new AI platform that uses the Intelligence extensions to reduce convolution-processing time by 4x compared with a standard RISC-V vector implementation. A few weeks earlier, it announced the 21G1 update, which increases SHA-256 hash rates by 35%, among other instruction-set and architectural improvements.","spans":[{"start":0,"end":501,"type":"em"}]}],"source":"The Linley Group Microprocessor Report","date":"2021-05-11","cta_text":"Read More [subscription required]","link":{"link_type":"Web","url":"https://www.linleygroup.com/newsletters/newsletter_detail.php?num=6307","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Dialog Semiconductor Selected as SiFive Preferred Power Management Partner for RISC-V Development Platforms","spans":[]}],"deck":[{"type":"paragraph","text":"Dialog is the preferred power management partner for the SiFive HiFive Unmatched PC form-factor RISC-V Linux Development Platform, featuring the SiFive Freedom U740 RISC-V SoC.","spans":[{"start":0,"end":176,"type":"em"}]}],"source":"Dialog Semiconductor","date":"2021-05-11","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.dialog-semiconductor.com/press-releases/dialog-semiconductor-selected-sifive-preferred-power-management-partner-risc-v","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"HiFive Unmatched RISC-V computer board is now shipping","spans":[]}],"deck":[{"type":"paragraph","text":"At first glance, the HiFive Unmatched from SiFive looks like just another mini ITX computer motherboard. But rather than an x86 chip, this system is powered by RISC-V processor.","spans":[{"start":0,"end":177,"type":"em"}]},{"type":"paragraph","text":"First introduced last fall, the board is aimed at developers rather than the general public, and with a $665 price tag, it’s a lot more expensive than some other RISC-V development boards. But the HiFive Unmatched is also one of the most powerful products in this emerging category to date, thanks to SiFive’s FU740 processor.","spans":[{"start":0,"end":326,"type":"em"}]}],"source":"Liliputing","date":"2021-05-21","cta_text":"Read More","link":{"link_type":"Web","url":"https://liliputing.com/2021/05/hifive-unmatched-risc-v-computer-board-is-now-shipping.html","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SEGGER’s emRun Runtime Library Licensed by SiFive for Superior Code Size and Performance Improvements","spans":[]}],"deck":[{"type":"paragraph","text":"The SEGGER emRun runtime library is available as part of the recently announced SiFive 21G1 release. SiFive’s focus on toolchain and library support enables key market requirements, including reduced code size and lower memory footprints. To support this goal, SiFive has licensed emRun as part of the SiFive Freedom Tools and Freedom-E-SDK packages. This integration enables chip designers to easily achieve optimum performance, while reducing code size by up to 25%.","spans":[{"start":0,"end":468,"type":"em"}]}],"source":"SEGGER","date":"2021-05-27","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.segger.com/news/seggers-emrun-runtime-library-licensed-by-sifive-for-superior-code-size-and-performance-improvements/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"The 10 Hottest Semiconductor Startups of 2021","spans":[]}],"deck":[{"type":"paragraph","text":"These startups are taking on semiconductor heavyweights like Intel and Nvidia with new kinds of silicon solutions for compute, storage and networking, many of which are headed for the data center. SiFive is providing an open-source alternative to Arm’s CPU design business with core designs and custom silicon solutions for AI, high-performance computing and other growing markets based on the open and free RISC-V instruction set architecture.","spans":[{"start":0,"end":445,"type":"em"}]}],"source":"CRN","date":"2021-06-16","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.crn.com/slide-shows/components-peripherals/the-10-hottest-semiconductor-startups-of-2021-so-far-/9","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive’s brand-new P550 is one of the world’s fastest RISC-V CPUs","spans":[]}],"deck":[{"type":"paragraph","text":"Today, RISC-V CPU design company SiFive launched a new processor family with two core designs: P270 (a Linux-capable CPU with full support for RISC-V's vector extension 1.0 release candidate) and P550 (the highest-performing RISC-V CPU to date).","spans":[{"start":0,"end":245,"type":"em"}]}],"source":"ArsTechnica","date":"2021-06-22","cta_text":"Read More","link":{"link_type":"Web","url":"https://arstechnica.com/gadgets/2021/06/sifives-brand-new-p550-is-one-of-the-worlds-fastest-risc-v-cpus/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"World's First Desktop PC RISC-V Board Meets AMD Radeon RX 6700 XT","spans":[]}],"deck":[{"type":"paragraph","text":"When SiFive introduced its HiFive Unmatched RISC-V desktop motherboard for developers last year, it was clear from the start that sooner or later an enthusiast would attempt to try using its U7 SoC for something it is not meant for: general PC usage with high-performance graphics and video decoding. That time has come as an enthusiast has managed to make AMD's Radeon RX 6700 XT work with a RISC-V SoC under Linux. ","spans":[{"start":0,"end":417,"type":"em"}]}],"source":"Tom's Hardware","date":"2021-07-22","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.tomshardware.com/news/radeon-rx-6700-xt-works-with-risc-v","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"RISC-V Business: Testing Gaming and More on the HiFive Unmatched from SiFive","spans":[]}],"deck":[{"type":"paragraph","text":"Wendell Wilson of Level 1 Techs tests the SiFive HiFive Unmatched RISC-V developer board in this 13:50 video on YouTube.","spans":[]}],"source":"Level1Techs on YouTube","date":"2020-09-24","cta_text":"Watch Now","link":{"link_type":"Web","url":"https://www.youtube.com/watch?v=lgatG_i8UMg","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Sneak peek into SiFive’s most powerful RISC-V yet","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive has briefly pulled back the curtains on its most powerful Risc-V processor yet.","spans":[{"start":0,"end":86,"type":"em"}]},{"type":"paragraph","text":"So far only called ‘Next Generation Core’ or Next-Gen, its official name, final design specs and availability will be unveiled early in December at the Risc-V Summit.","spans":[{"start":0,"end":166,"type":"em"}]}],"source":"Electronics Weekly","date":"2021-10-26","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.electronicsweekly.com/news/design/sneak-peek-sifives-powerful-risc-v-yet-2021-10/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"A look into the future? SiFive HiFive Unmatched viewed","spans":[]}],"deck":[{"type":"paragraph","text":"X86 designs have dominated for years, but not only the power niche of IBM or the up-and-coming arm competition are putting pressure on the established microprocessor architecture. The open instruction set architecture (ISA) RISC-V could play an increasingly important role in many areas in the future. On the basis of the SiFive HiFive Unmatched, we want to take a closer look at this topic. [GER]","spans":[{"start":0,"end":397,"type":"em"}]}],"source":"HardwareLuxx","date":"2021-10-01","cta_text":"Read More","link":{"link_type":"Web","url":"https://www-hardwareluxx-de.translate.goog/index.php/artikel/hardware/prozessoren/57184-ein-blick-in-die-zukunft-sifive-hifive-unmatched-angeschaut.html?_x_tr_sl=auto\u0026_x_tr_tl=en\u0026_x_tr_hl=en-US\u0026_x_tr_pto=nui","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"Safety-critical real-time operating system (RTOS) for RISC-V microprocessors introduced by Green Hills","spans":[]}],"deck":[{"type":"paragraph","text":"The INTEGRITY for RISC-V RTOS is integrated with RISC-V processor solutions including hardware reference boards from Microchip and SiFive, along with processor intellectual property (IP) from SiFive, a RISC-V IP provider.","spans":[]}],"source":"Military \u0026 Aerospace Electronics","date":"2021-11-04","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.militaryaerospace.com/computers/article/14213391/realtime-operating-system-rtos-safetycritical-riscv","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"FADU's PCIe 5.0 SSD controller uses S5 cores from SiFive","spans":[]}],"deck":[{"type":"paragraph","text":"The South Korean chip startup FADU has announced its new generation of SSD controllers, the FC5161.If the South Koreans have their way, this will be one of the fastest for PCIe 5.0 SSDs, primarily in the data center area.The FADU FC5161 is to connect the storage via four PCIe 5.0 lanes, speaks NVMe 1.4+ and OCP Cloud Spec 2.0. [GER]","spans":[{"start":0,"end":334,"type":"em"}]}],"source":"HardwareLuxx","date":"2021-11-13","cta_text":"Read More","link":{"link_type":"Web","url":"https://www-hardwareluxx-de.translate.goog/index.php/news/hardware/festplatten/57520-fadus-pcie-5-0-ssd-controller-nutzt-s5-kerne-von-sifive.html?_x_tr_sl=auto\u0026_x_tr_tl=en\u0026_x_tr_hl=en-US\u0026_x_tr_pto=nui","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"BrainChip and SiFive partner to deploy AI/ML technology at the edge","spans":[]}],"deck":[{"type":"paragraph","text":"BrainChip’s AkidaTM is a revolutionary advanced neural networking processor architecture that brings AI to the edge in a way that existing technologies are not capable, with high performance, ultra-low power, and on-chip learning. SiFive Intelligence™ solutions with their highly configurable multi-core, multi-cluster capable design, integrate software and hardware to accelerate AI/ML applications. The integration of BrainChip’s Akida technology and SiFive’s multi-core capable RISC-V processors will provide a highly efficient solution for integrated edge AI compute.","spans":[{"start":0,"end":571,"type":"em"}]}],"source":"BrainChip","date":"2022-04-05","cta_text":"Read More","link":{"link_type":"Web","url":"https://brainchipinc.com/brainchip-sifive-partner-deploy-ai-ml-at-edge/","target":"_blank"},"featured":"no","publish_to":"Current Releases"},{"title":[{"type":"heading1","text":"Next generation music AI engine available for RISC-V","spans":[]}],"deck":[{"type":"paragraph","text":"Helios is an advanced patent-protected AI music recommendation engine that can be used to search commercial music catalogues using music itself as the search key. Applications are wide ranging, such as production studios seeking synchronization licenses from record labels, streaming services, online music stores, and much more.","spans":[{"start":0,"end":329,"type":"em"},{"start":0,"end":6,"type":"hyperlink","data":{"link_type":"Web","url":"https://vimeo.com/477202206"}}]},{"type":"paragraph","text":"The engine’s debut on RISC-V opens a goldmine of new commercial opportunities in the embedded space for digital jukeboxes, IoT, in-flight entertainment, and luxury vehicles to name a few.","spans":[{"start":0,"end":187,"type":"em"}]}],"source":"RISC-V International","date":"2021-12-06","cta_text":"Read More","link":{"link_type":"Web","url":"https://riscv.org/blog/2021/12/next-generation-music-ai-engine-available-for-risc-v/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Announces Latest RISC-V CPU, The P650","spans":[]}],"deck":[{"type":"paragraph","text":"San Francisco-based fabless semiconductor provider SiFive today announced a new processor it describes as “the fastest licensable RISC-V processor IP core in the market”. The SiFive Performance P650.","spans":[{"start":0,"end":199,"type":"em"}]}],"source":"Tom's Hardware","date":"2021-12-03","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.tomshardware.com/news/sifive-announces-p650-riscv","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive Essential 6-Series RISC-V processors target Linux, real-time applications","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive has been busy. Just a few days after the SiFive Performance P650 announcement, the company has announced the SiFive Essential 6-Series RISC-V processor family starting with four 64-bit/32-bit real-time core, and two Linux capable application cores, plus the SiFive 21G3 release with various improvements to existing families.","spans":[{"start":0,"end":332,"type":"em"},{"start":48,"end":84,"type":"hyperlink","data":{"link_type":"Web","url":"https://www.cnx-software.com/2021/12/03/sifive-performance-p650-risc-v-core-to-outperform-arm-cortex-a77-performance-per-mm2/"}},{"start":98,"end":111,"type":"hyperlink","data":{"link_type":"Web","url":"https://www.sifive.com/press/sifive-expands-and-improves-industry-leading-risc-v"}}]}],"source":"CNX Software","date":"2021-12-10","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.cnx-software.com/2021/12/10/sifive-essential-6-series-risc-v-processors-target-linux-real-time-applications/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"The 2021 RISC-V Summit Charts the Wildfire Expansion of Open-source Hardware","spans":[]}],"deck":[{"type":"paragraph","text":"With this year’s RISC-V Summit officially concluded, open-source processors are being adopted faster than ever. Membership in RISC-V International has grown by 130% in 2021 alone—and individual contributors have enthusiastically chipped in. What has the electrical-engineering community achieved throughout the past 12 months with RISC-V? ","spans":[{"start":0,"end":339,"type":"em"},{"start":17,"end":30,"type":"hyperlink","data":{"link_type":"Web","url":"https://events.linuxfoundation.org/riscv-summit/","target":"_blank"}}]}],"source":"All About Circuits","date":"2021-12-10","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.allaboutcircuits.com/news/2021-riscv-summit-charts-wildfire-expansion-open-source-hardware/","target":"_blank"},"featured":"no","publish_to":"Archive"},{"title":[{"type":"heading1","text":"SiFive and Solid Sands are helping to lead the RISC-V revolution","spans":[]}],"deck":[{"type":"paragraph","text":"SiFive is creating a new infrastructure to support accelerated ASIC and FPGA design flows, IP delivery, and SoC development. These new developments comprise state-of-the-art compiler algorithms, novel build system integration, and new Verilog RTL generation techniques. It needed a powerful compiler test and verification tool, not only to verify the functionality of its current compiler offering, but also to assist in developing its new IDE infrastructure. The tool SiFive selected was SuperTest from Solid Sands.","spans":[{"start":0,"end":516,"type":"em"}]}],"source":"Electropages","date":"2022-01-31","cta_text":"Read More","link":{"link_type":"Web","url":"https://www.electropages.com/2022/01/helping-lead-risc-v-revolution","target":"_blank"},"featured":"no","publish_to":"Current Releases"}],"media_inquiries":[{"title":"Media Inquiries","contact_info":"SiFive@RacePointGlobal.com"}]}},"header":{"id":"W6V1zB0AACNRrnB8","uid":null,"url":null,"type":"header","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W6V1zB0AACNRrnB8%22%29+%5D%5D","tags":[],"first_publication_date":"2018-09-21T22:50:55+0000","last_publication_date":"2023-03-07T17:41:45+0000","slugs":["header"],"linked_documents":[],"lang":"en-us","alternate_languages":[{"id":"ZJC9UREAACQAzUkH","type":"header","lang":"zh-cn"}],"data":{"title":"Header","primary_nav":[{"text":"Core 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Dropdown","spans":[]}],"links":[{"text":"Core Designer","link":{"id":"W47SSiYAACUAfX3G","type":"core_designer_page","tags":[],"lang":"en-us","slug":"core-designer-page","first_publication_date":"2018-09-04T18:43:26+0000","last_publication_date":"2021-12-27T19:24:55+0000","link_type":"Document","isBroken":false},"sub_menu":null},{"text":"Chip Designer","link":{"id":"W47r9yYAACQAfe9i","type":"broken_type","tags":[],"lang":null,"slug":"-","first_publication_date":null,"last_publication_date":null,"link_type":"Document","isBroken":true},"sub_menu":null}]}}],"version":"fca3ea7","license":"All Rights Reserved"},"pressReleases":[{"id":"XzcQDBAAACEAP7aV","uid":"sifive-announces-openfive-an-industry-leading-custom","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XzcQDBAAACEAP7aV%22%29+%5D%5D","tags":[],"first_publication_date":"2020-08-17T13:00:00+0000","last_publication_date":"2024-10-31T12:27:39+0000","slugs":["sifive-announces-openfive-an-industry-leading-custom-silicon-business-unit"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Announces OpenFive, an Industry-Leading Custom Silicon Business Unit","spans":[]}],"publish_to":"Archive","publish_date":"2020-08-17","share_image":{"link_type":"Media","kind":"image","id":"XzcPRBAAAB4AP7Mk","url":"https://images.prismic.io/sifive/ee096da4-8c1a-4888-8049-38122b2e7f97_openfive-announcement-social.png?auto=compress,format","name":"openfive-announcement-social.png","size":"621513","width":"1200","height":"600"},"body":[{"type":"preformatted","text":"*OpenFive is a solution-centric and processor agnostic custom silicon business unit dedicated to building optimized domain-specific SoCs*\n\n**SAN MATEO, Calif. Aug 17, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced OpenFive, a self-contained and autonomous business unit to capture the opportunity offered by enabling customizable, silicon-focused solutions with differentiated-IP. OpenFive will be led by Dr. Shafy Eltoukhy, SVP, and general manager of OpenFive. OpenFive is solution-centric and uniquely positioned to design processor agnostic SoCs and deliver high-quality silicon.\u003cbr/\u003e \n\n“The world is moving towards domain-specific architectures to solve the needs of power, performance, and cost”, said Dr. Shafy Eltoukhy, SVP \u0026 GM of OpenFive. “Working collaboratively with our partners and customers, OpenFive innovates with segment-specific silicon solutions based on optimized processor and SoC IP targeted to our customer’s requirements.”\u003cbr/\u003e\n\nDomain-specific silicon has emerged as the method for delivering efficient, high-performance silicon and software solutions for modern computing challenges. OpenFive’s Idea-to-Silicon solutions built with our advanced design methodologies on leading-edge foundry processes nodes down to 5nm, and 2.5D packaging technology enable domain-specific SoCs in exciting new applications.\u003cbr/\u003e\n\nOpenFive offers customizable and differentiated SoC IP for Artificial Intelligence, Edge Computing, HPC, and Networking solutions. The OpenFive portfolio includes low-latency, high-throughput Interlaken connectivity fabric, 400/800G Ethernet, High-bandwidth memory (HBM2/E), USB subsystem IP, and die-to-die interconnect IP for next-generation heterogeneous chiplet-style products.\u003cbr/\u003e\n\n“OpenFive will accelerate the adoption of domain-specific silicon designs for workload-focused performance”, said Dr. Naveed Sherwani, Chairman, President, and CEO of SiFive. “The adoption of RISC-V in heterogenous ISA designs will benefit the performance and scalability of products, and encourage more technology companies to move to open, free ISAs for their computing needs.”\u003cbr/\u003e\n\nOpenFive’s end-to-end expertise in Architecture, Design Implementation, Software, Silicon Validation and Manufacturing delivers high-quality silicon, with first-time-right results. \n\nLearn more about [SiFive’s market-leading RISC-V IP portfolio](https://www.sifive.com/risc-v-core-ip).\u003cbr/\u003e\n\n**About SiFive**\u003cbr/\u003e\nSiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK hynix, Intel Capital, and Western Digital. For more information, please visit [www.sifive.com](https://www.sifive.com).\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\n\n**Media Contact**\u003cbr/\u003e\n\n**SiFive**\u003cbr/\u003e\nHilary Livingston Castle\u003cbr/\u003e\nINK Communications\u003cbr/\u003e\n203.858.7259\u003cbr/\u003e\n","spans":[],"direction":"ltr"}]}},{"id":"ZxSJbxIAAB8AXUZ7","uid":"hifive-premier-p550-development-boards-now-shipping","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZxSJbxIAAB8AXUZ7%22%29+%5D%5D","tags":[],"first_publication_date":"2024-10-21T15:03:16+0000","last_publication_date":"2024-10-24T17:55:12+0000","slugs":["sifive-hifive-premier-p550-development-boards-now-shipping"],"linked_documents":[],"lang":"en-us","alternate_languages":[{"id":"ZxpIyxIAAB8AZXKh","type":"press_release","lang":"zh-cn","uid":"hifive-premier-p550-development-boards-now-shipping"}],"data":{"page_title":"HiFive Premier P550 - \"Early Access\" Edition Now Shipping","meta_description":"SiFive announces the availability of its state-of-the-art HiFive™ Premier P550 development board. An initial pre-release batch of 100 Yocto Linux-based boards, called the \"Early Access Edition,\" is available for purchase through Arrow Electronics. Read more on the release here.","title":[{"type":"heading1","text":"SiFive HiFive Premier P550 Development Boards Now Shipping","spans":[],"direction":"ltr"}],"publish_to":"Current Releases","publish_date":"2024-10-21","share_image":{"link_type":"Media","kind":"image","id":"Zw136oF3NbkBXaxW","url":"https://images.prismic.io/sifive/Zw136oF3NbkBXaxW_HiFive-Premier-P550-Promo.png?auto=format,compress?auto=compress,format","name":"HiFive-Premier-P550-Promo.png","size":"977097","width":"1350","height":"846"},"body":[{"type":"preformatted","text":"**The world’s highest performance RISC-V development board unlocks new opportunities for software developers to create the next era of RISC-V applications**\n\n**Santa Clara, Calif. – Oct. 21, 2024 – SiFive, Inc.**, the gold standard for RISC-V computing, today announced the availability of its state-of-the-art [HiFive™ Premier P550 development board](https://www.sifive.com/boards/hifive-premier-p550). An initial pre-release batch of 100 Yocto Linux-based boards, called the \"Early Access Edition,\" is available for purchase through [Arrow Electronics](https://www.arrow.com/en/products/hf106/sifive-inc). A broader release with Canonical Ubuntu 24.04 pre-installed is scheduled for December, providing developers with an unparalleled out-of-box experience.\n\n[![HiFive Board](https://images.prismic.io/sifive/Zw136oF3NbkBXaxW_HiFive-Premier-P550-Promo.png?auto=format,compress)](https://www.sifive.com/boards/hifive-premier-p550)\n\n“Since announcing the HiFive Premier P550 boards in April, we’ve worked closely with [Canonical](https://canonical.com/) to deliver a best-in-class hardware and software experience,” said Martyn Stroeve, Head of the HiFive board program at SiFive. “We know many developers are eager to get their hands on this powerful new board, so we decided to release a limited Early Access Edition. At the same time, we are finalizing the software stack for the December release, which we believe will deliver powerful performance and usability for developers. We’re excited to see the innovation and creativity that will come from this.”\n\nThe quad-core SiFive Performance™ P550 processor, running at 1.4GHz, makes the HiFive Premier P550 the highest-performing RISC-V development board available. Its out-of-order core architecture delivers exceptional compute density and performance, all within an energy-efficient footprint.\n\nSiFive is showcasing the HiFive Premier P550 as part of its sponsorship of the Developer Zone at the [RISC-V Summit North America](https://riscv.org/event/risc-v-summit-north-america-2024/), taking place Oct. 21-23 in Santa Clara, Calif. SiFive will show the new board along with the popular [HiFive Unmatched Rev. B](https://www.sifive.com/boards/hifive-unmatched-revb), and share insights into its long-term board strategy, which spans from embedded systems to advanced AI applications. SiFive provides comprehensive support for its RISC-V development boards, including documentation, development kits, toolchains, utilities, and software ecosystem solutions.\n\nBo Wang, Vice Chairman of [ESWIN Computing](https://www.eswin.com/en/), stated: “We are excited to see ESWIN’s high-performance EIC7700X SoC powering the HiFive Premier P550, enabling developers to fully realize the advantages of RISC-V. We look forward to our continued partnership with SiFive in bringing this board to market and driving innovation in RISC-V design.”\n\n“The collaboration between ESWIN Computing, SiFive, and Canonical to bring Ubuntu 24.04 to the HiFive Premier P550 highlights the core values of RISC-V: openness and collaboration,” said Gordan Markuš, Director of Silicon Alliances at Canonical. “The HiFive Premier P550 stands out as the premium development board for enthusiasts and developers, helping drive the next wave of cutting-edge RISC-V development. We’re proud to see Ubuntu Linux as a key enabler of this innovation and development on the Premier P550 board.”\n\nBeyond the HiFive Premier P550, SiFive is committed to addressing the growing demand for RISC-V silicon. “To meet this need, we are creating a new series of HiFive boards offering varying performance levels, capabilities like scalar and vector compute, and at different price points,” said Stroeve. “We’re excited to announce our new HiFive Partner strategy and HiFive Approved program, which will help scale our offerings and bring more silicon solutions to market, in collaboration with our ecosystem partners. This builds on our broad product portfolio, and with over 400 design wins we’re positioned to bring customers the best RISC-V platforms across more applications and markets.”\n\n**HiFive Premier P550 Key Features:**\n- The world’s highest performing commercially available RISC-V CPU- SiFive P550\n- 16-32GB LPDDR5 / 128GB eMMC\n- Robust PC connectivity: SATA, PCIe, SD, M.2, USB 3\n- Integrated Imagination GPU and ESWIN NPU\n\nOrders for the HiFive Premier P550 can be placed on [Arrow.com](https://www.arrow.com/en/products/hf106/sifive-inc). For more information, visit: [HiFive Premier P550](https://www.sifive.com/boards/hifive-premier-p550).\n\n**About SiFive**\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n","spans":[],"direction":"ltr"}]}},{"id":"ZnEBVxEAACMAkPEp","uid":"media-alert-sifive-to-exhibit-and-keynote-at-risc-v","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZnEBVxEAACMAkPEp%22%29+%5D%5D","tags":[],"first_publication_date":"2024-06-18T03:41:16+0000","last_publication_date":"2024-06-18T16:41:10+0000","slugs":["media-alert-sifive-to-exhibit-and-keynote-at-risc-v-summit-europe"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Media Alert: SiFive to Exhibit and Keynote at RISC-V Summit Europe","spans":[]}],"publish_to":"Current Releases","publish_date":"2024-06-17","share_image":{"link_type":"Media","kind":"image","id":"ZKL8PREAACQAGb8I","url":"https://images.prismic.io/sifive/798d7bc2-f7ea-4a0f-9fda-23998b35fc55_control-management.png?auto=format,compress?auto=compress,format","name":"control-management.png","size":"154003","width":"972","height":"843"},"body":[{"type":"preformatted","text":"**WHAT:** SiFive (a gold sponsor) will be exhibiting at RISC-V Summit Europe from June 25-27, 2024 in Munich. At its booth, SiFive will be showing off its latest products, including SiFive’s new state-of-the-art RISC-V development board, the [HiFive™ Premier P550](https://www.sifive.com/boards/hifive-premier-p550). The highest performance RISC-V development board on the market, the HiFive Premier P550 offers developers unmatched flexibility and performance.\n\r\nSiFive will also be giving three talks throughout the event, including a keynote from SiFive’s Krste Asanović discussing the incredible momentum of the RISC-V ecosystem across verticals. Additionally, SiFive will be sharing details on its newest [Essential products](https://www.sifive.com/cores/essential), which are designed to optimize power and performance in a range of devices.\r\n\n\nAttendees are encouraged to check out SiFive’s speaking sessions on Tuesday, June 25:\r\n\n11:30 CEST: “RISC-V State of the Union” keynote with Krste Asanović, co-founder and chief architect at SiFive.\r\n\n13:00 CEST: “Enhancements to SiFive's Essential Product Line” demo theatre talk with Pete Lewin, Embedded and Automotive Product Director at SiFive.\r\n\n16:15 CEST: “Exciting Possibilities with the SiFive HiFive Premier P550 Development Board and Essential Series Benefits for Embedded applications” lightning talk with John Ronco, SVP of Product.\r\n\r\n**WHEN:** RISC-V Summit Europe will be taking place from June 24-28, with the main conference program and the Expo running from June 25-27. \r\n\r\n**WHERE:** RISC-V Summit Europe will be located at MOC – Event Center Messe Munich in Munich, Germany. \n\n[Visit the RISC-V Summit Europe 2024 Website](https://riscv-europe.org/)\n\r\n\n\u003cp\u003e\n\r\n### Contacts\n\r\nDave Miller\u003cbr\u003e\r\nSiFive Corporate Communications\u003cbr\u003e\r\n\u003cdavid.miller@sifive.com\u003e\r\n\r\nRacepoint Global for SiFive\u003cbr\u003e\r\n\u003cSiFive@racepointglobal.com\u003e\u003cbr\u003e\r\nTel.: +1 (415) 694-6711\r\n\r\n\u003c/p\u003e\r\n","spans":[]}]}},{"id":"Y_4e_RAAACAA3jrb","uid":"sifive-adds-adam-dolinko-as-chief-legal-officer-and","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Y_4e_RAAACAA3jrb%22%29+%5D%5D","tags":[],"first_publication_date":"2023-02-28T15:41:02+0000","last_publication_date":"2024-05-28T20:15:39+0000","slugs":["sifive-adds-adam-dolinko-as-chief-legal-officer-and-svp-of-corporate-development"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Adds Adam Dolinko as Chief Legal Officer and SVP of Corporate Development ","spans":[]}],"publish_to":"Archive","publish_date":"2023-02-28","share_image":{"link_type":"Media","kind":"image","id":"Y_17MxAAACAA23YM","url":"https://images.prismic.io/sifive/764ed8c3-02f9-43fe-a467-958f6111fefd_adamD.jpg?auto=compress,format","name":"adamD.jpg","size":"190638","width":"960","height":"960"},"body":[{"type":"preformatted","text":"\r\n**Adam brings 25+ years of experience driving Technology Industry IPOs, Mergers and Acquisitions\r\n and Strategic Partnerships**\r\n\r\n**San Jose, Calif., Feb. 28, 2023** –SiFive, Inc., the pioneer and leader of RISC-V computing, today announced that Adam Dolinko recently joined the company as Chief Legal Officer and SVP of Corporate Development.\r\n\r\nAdam brings a proven 25+ year proven track record of leading, negotiating and closing more than 80 transformative corporate IPOs, mergers \u0026 acquisitions, and strategic deals, along with leading internal teams to help scale operations to drive billions in commercial revenues. \n \r\n“Time and time again, Adam has delivered by leading successful IPOs, M\u0026A and complex strategic deals with virtually every titan in the semiconductor ecosystem--he is a key addition to our executive team,” said Patrick Little, SiFive’s Chairman of the Board and CEO. “He brings seasoned leadership as an executive of public companies on different trading markets, deep experience managing investment banks, and his industry expertise maps directly to SiFive’s core sectors. We are delighted that he’s joined us as we work closely with customers and strategic partners to continue to rapidly scale our business and drive the RISC-V ecosystem.”\n\n![Adam Dolinko](https://images.prismic.io/sifive/764ed8c3-02f9-43fe-a467-958f6111fefd_adamD.jpg?auto=compress,format) \n\r\nOver his career, Adam was a Corporate/Capital Markets and M\u0026A Partner at Wilson Sonsini, where he advised high growth to Fortune 500 companies and the world’s leading investment banks. He then served as a Senior Executive at three global public companies (trading on NASDAQ, NYSE, and the London Stock Exchange) each an innovating pioneer in semiconductors and software solutions, along with commercial focus in automotive, IoT, industrial and mobile devices, among others. In addition to leading each of these public companies through successful and transformative M\u0026A deals, as an Executive General Counsel he led a FTSE250 company through its US IPO.\n\r\n“Adam’s industry expertise, combined with his business and legal acumen even in the most complex of circumstances, is beyond reproach and he will be an invaluable resource for SiFive as it continues its ongoing ascent, as well as for its customers, Board, corporate partners and the ecosystem overall,” said Joep van Beurden, former Global Semiconductor Alliance Chair of the Board. \n\r\nAdam serves on the Advisory Board for the Center for Transnational Law and Business, at the USC Gould School of Law, and volunteers on an Advisory Board for Abilities United, which assists children and adults with developmental disabilities to fully participate in the community and forging friendships through employment, education, and recreational activities.\n\n**About SiFive**\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit SiFive.com.\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\n**Media Contact**\r\nAllison DeLeo\r\nRacepoint Global for SiFive\r\nSiFive@racepointglobal.com\r\nTel.: +1(415) 694-6711\r\n \r\nDavid Miller\r\nCorporate Communications\r\nSiFive\r\nDavid.Miller@sifive.com\r\n\r\n","spans":[]}]}},{"id":"YkTiBBQAACAA_LyH","uid":"sifive-appoints-nicole-singer-as-chief-human-resources","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YkTiBBQAACAA_LyH%22%29+%5D%5D","tags":[],"first_publication_date":"2022-03-31T12:55:14+0000","last_publication_date":"2024-05-28T20:14:02+0000","slugs":["sifive-appoints-nicole-singer-as-chief-human-resources-officer-to-drive-sifive-growth-and-hiring"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Appoints Nicole Singer as Chief Human Resources Officer to Drive SiFive Growth and Hiring","spans":[]}],"publish_to":"Archive","publish_date":"2022-03-31","share_image":{"link_type":"Media","kind":"image","id":"YkThLBQAACAA_LjJ","url":"https://images.prismic.io/sifive/56dadb17-96c7-4b92-bacc-84fe90024526_SiFiveCHRO03312022.png?auto=compress,format","name":"SiFiveCHRO03312022.png","size":"352951","width":"1080","height":"1080"},"body":[{"type":"preformatted","text":"*Singer to drive company hypergrowth, accelerating high-performance processor IP roadmap to challenge Arm*\n\n**SAN MATEO, Calif., March 31, 2022** – [SiFive, Inc.](https://www.sifive.com), the founder and leader of RISC-V computing, today announced that Nicole Singer has joined SiFive as Senior Vice President and Chief Human Resources Officer. In this role, Singer will be responsible for leading the company’s global HR organization, supporting the rapid growth SiFive is experiencing as the company accelerates its mission to build the best computing platforms in the world, enabling customers to deliver differentiated, best-in-class products, taking the open standard RISC-V ISA to every corner of computing. Singer joins SiFive from Synaptics, where she was SVP of worldwide human resources, supporting their mission to be the leader in combining human interfaces with IoT and AI technologies.\u003cbr/\u003e \r\n\r\n“I’m excited to welcome Nicole to the team and can’t wait to see her leadership and passion invigorate our company growth on our mission to the top of the high-performance processor IP market,” said Patrick Little, CEO and Chairman, SiFive. “Our recent announcements and company valuation of over $2.5B have provided what we need to grow into the opportunity and take RISC-V to the next level. SiFive is the leader in RISC-V computing, and we’re building the fastest processor cores to enable our customers’ roadmaps to achieve their goals. Nicole’s talents and expertise will help us expand our team’s already prodigious capabilities with the right people to realize our goal of RISC-V everywhere.”\u003cbr/\u003e \r\n\r\n“I’m delighted to be part of the innovative team at SiFive, to help the company move onto the next stage of its journey in building a leading high-performance processor IP business,” said Nicole Singer, SVP and CHRO, SiFive. “SiFive is attracting talent at a fast pace to address the challenges of modern chip design and guiding that growth will be key to our success in executing our roadmap. I’m pleased to be joining at this pivotal time when every employee’s actions will have maximum impact.”\u003cbr/\u003e \r\n\r\nSinger brings more than 25 years of varied professional experience with technology companies to her role at SiFive, including most recently serving as SVP of Human Resources at Synaptics, and before that, VP of Human Resources at Xilinx. Prior to joining Xilinx, she served in various technology sales and customer implementation roles at management consulting and software companies such as Accenture, Deloitte Consulting, and PeopleSoft. Singer received a BA Degree in Sociology, with a minor in Psychology and Business, from George Washington University in Washington, DC, and an MBA plus MS in Management Information Systems (MIS) from Boston University in Boston, MA.\u003cbr/\u003e\n\r\nSiFive recently announced a $2.5B+ company valuation after completing a [$175M Series F](https://www.sifive.com/press/sifive-leadership-in-risc-v-powers-2.5b-company-valuation) funding round. [In December](https://www.sifive.com/press/sifive-raises-risc-v-performance-bar-with-new-best-in-class), SiFive announced the SiFive Performance™ P650 processor, a best-in-class RISC-V-based commercially licensable processor core that is now available to lead customers. Offering up to 30% better performance per area and class-leading efficiency, the SiFive Performance P650 is the fastest commercially available RISC-V processor.\u003cbr/\u003e\r\n\n**About SiFive**\u003cbr/\u003e\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\n","spans":[]}]}},{"id":"ZhQyzxIAACIAszSJ","uid":"media-alert-sifive-at-embedded-world-2024","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZhQyzxIAACIAszSJ%22%29+%5D%5D","tags":[],"first_publication_date":"2024-04-08T18:10:32+0000","last_publication_date":"2024-05-28T20:10:40+0000","slugs":["media-alert-sifive-at-embedded-world-2024"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"MEDIA ALERT: SiFive at embedded world 2024","spans":[]}],"publish_to":"Archive","publish_date":"2024-04-08","share_image":{"link_type":"Media","kind":"image","id":"ZhBMMxIAACQAohC-","url":"https://images.prismic.io/sifive/295e8b80-0c25-4cd4-8dc5-97fcaab9c058_HiFive-Premier-P550.jpg?auto=compress,format","name":"HiFive-Premier-P550.jpg","size":"786367","width":"1200","height":"1093"},"body":[{"type":"preformatted","text":"WHAT: SiFive will be exhibiting at embedded world 2024, showcasing the company’s portfolio of high-performance RISC-V solutions. SiFive’s comprehensive portfolio includes the company’s latest products for generative AI and ML applications, the SiFive Performance™ P870 and SiFive Intelligence™ X390. Additionally, SiFive will be highlighting the SiFive Automotive™ solutions, which address critical needs for current and future applications such as infotainment, cockpit, connectivity, ADAS, and electrification. Attendees will also be able to check out SiFive’s lineup of RISC-V development boards, including the company’s next-generation high-performance board. \r\n\r\nAt the theater in the RISC-V International booth, SiFive’s Dany Nativel will be giving two presentations about SiFive’s robust development tools. These tools are enabling developers to bring cutting-edge RISC-V products across a variety of market segments. The first session will be held on Tuesday, April 9 at 14:00 CET, and then Dany will give the presentation again on Wednesday, April 10 at 12:00 CET.\r\n\r\nSpeak with a SiFive representative at embedded world to learn more about how the company is bringing the limitless potential of RISC-V to consumer products, datacenters, aerospace, autonomous vehicles, wearables, and beyond.\r\n\r\nWHEN: 9-11 April 2024\r\n09:00 - 18:00 (9-10 June)\r\n09:00 - 17:00 (11 June)\r\n\r\nWHERE: embedded world\r\nRISC-V International booth\r\nHall 5, Stand 5-119\r\nNuremberg Messe\r\nMessezentrum 1, 90471 Nürnberg, Germany\r\nSee the floorplan here.\r\n\r\nAbout SiFive:\r\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\r\n\r\nContacts\r\nDave Miller\r\nSiFive Corporate Communications\r\nDavid.miller@sifive.com \r\n\r\nRacepoint Global for SiFive\r\nSiFive@racepointglobal.com\r\n","spans":[]}]}},{"id":"XXu2JBEAACUAw6KQ","uid":"sifive-announces-key-enablement-of-trace-and-debug","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XXu2JBEAACUAw6KQ%22%29+%5D%5D","tags":[],"first_publication_date":"2019-09-26T13:00:03+0000","last_publication_date":"2024-06-05T16:05:29+0000","slugs":["sifive-announces-key-enablement-of-trace-and-debug"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Announces Key Enablement Of Trace And Debug","spans":[]}],"publish_to":"Archive","publish_date":"2019-09-23","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*World Leading RISC-V IP Portfolio with integrated Instruction Trace Encoder*\n\nSAN MATEO, Calif. – September 23rd, 2019 – [SiFive](https://www.sifive.com/), Inc., has announced the general availability of the latest update to SiFive Core IP and SiFive Core Designer in the Q3 2019 quarterly update. This release is specifically focused on the enablement of Trace and Debug functionality in the development of configurable SoC design. \n\nReal-time analysis enabled via tracing permits a deeper insight into the interactions of software and hardware to accelerate development, debug, and validation. To support this goal, the full range of SiFive Core IP is now enabled with [Nexus 5001](https://nexus5001.org/nexus-5001-forum-standard/)™ Instruction Trace capabilities. \n\nConfiguring a SiFive Core IP project with advanced trace capabilities can now be performed in [SiFive Core Designer](https://www.sifive.com/core-designer). The core complex design including Nexus 5001™ trace encoders is configured in SiFive’s cloud environment and delivered pre-integrated and verified in a single package to save silicon design teams time, money, and engineering resources.\n\nOpen-source contributions are a core value for SiFive, and clearly demonstrated by the immediate availability of a SiFive contributed open-source cross-platform, C++ based, Nexus 5001™ Trace decoder for RISC-V on [Github](https://github.com/sifive/trace-decoder-tests), to ease integration into existing debug and trace environments.\n\nThrough the use of Nexus 5001™ trace, SiFive processors are supported by a number of leading industry tools: \n\n“As a leader in the debug space, we are pleased to work with SiFive to expand the trace and debug offerings available for RISC-V,” said Anders Holmberg, Chief Strategy Officer, IAR Systems, “Our mission is to make software development easier, faster, and more robust, and we are confident that the debug and trace features SiFive now adds will contribute to that vision. We will continue to collaborate and share knowledge in order to ensure the RISC-V community have access to the tools needed to take RISC-V development to the next level.”\n\n“As a leading provider in the embedded debug space, Lauterbach are pleased to adopt SiFive Core IP as part of our Trace and Debug support,” said Stephan Lauterbach, Lauterbach CTO, “The Lauterbach mission is to accelerate software development, and the addition of SiFive’s debug and trace features in our product line delivers on that vision. The momentum of SiFive and their excellent industry engagement made deciding to invest in bringing debug and trace support for SiFive RISC-V development, simple.”\n\n“We are excited to be working with SiFive in further advancing debug and trace for RISC-V,” said Rolf Segger of SEGGER Microcontroller. \"The decision to put engineering efforts into support for the SiFive Trace IP was an easy one thanks to their adoption of industry standards, their strong business momentum, and the ease of dealing with the SiFive team. We believe this is great news for SiFive, SEGGER, and the RISC-V community.” \n\n“SiFive continues to lead in the RISC-V ecosystem,” said Yunsup Lee, SiFive CTO and co-founder, “as demonstrated by this update that enables SiFive to be first to offer a full portfolio of RISC-V based microarchitectures with integrated instruction trace, supported by major software providers. SiFive based platform development is now simpler and more robust than ever before, leading the industry in ease of adoption.” \n\nSiFive momentum continues to grow with the fast-paced evolution of silicon design enablement, RISC-V IP, and solution support offered by the company. For more details about SiFive Trace and Debug enablement inside the SiFive Q3 quarterly update, visit [https://www.sifive.com/blog/making-it-easy-to-get-it-right](https://www.sifive.com/blog/making-it-easy-to-get-it-right). \n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.\n\n## MEDIA CONTACTS\n\nLeslie Clavin\nSHIFT Communications for SiFive\n415-591-8440\nsifive@shiftcomm.com","spans":[]}]}},{"id":"ZUKGIRIAACIAvB_D","uid":"media-alert-sifive-to-participate-in-numerous-speaking","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZUKGIRIAACIAvB_D%22%29+%5D%5D","tags":[],"first_publication_date":"2023-11-01T17:26:05+0000","last_publication_date":"2024-05-28T20:10:00+0000","slugs":["media-alert-sifive-to-participate-in-numerous-speaking-sessions-and-sponsor-developer-zone-at-risc-v-summit-north-america-2023"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"MEDIA ALERT: SiFive to Participate in Numerous Speaking Sessions and Sponsor Developer Zone at RISC-V Summit North America 2023 ","spans":[]}],"publish_to":"Archive","publish_date":"2023-11-01","share_image":{"link_type":"Media","kind":"image","id":"ZSWZLRAAAB4AYgL4","url":"https://images.prismic.io/sifive/dea8a105-856d-4d62-a28c-c778d8174e6e_SiFive-High-Performance-NPU.PNG?auto=compress,format","name":"SiFive-High-Performance-NPU.PNG","size":"888530","width":"4000","height":"2250"},"body":[{"type":"preformatted","text":"**WHAT:** SiFive will be onsite at the annual RISC-V Summit, scheduled for Nov. 6 – 8, 2023 in Santa Clara, CA. The Summit brings together the fast-growing RISC-V ecosystem for several days of discussion. SiFive’s Krste Asanović will deliver the RISC-V ISA: State of the Union in his keynote and will address recent developments in RISC-V standards and the roadmap for future advancements. \n\nSiFive will also host a series of technical sessions on RISC-V cryptography extensions, RVV C intrinsic API v. 1.0, RISC-V N-Trace specifications, LLVM RISC-V compilers, and more. \r\nAt the event, SiFive experts can speak to the company’s broad [Core IP portfolio](https://www.sifive.com/risc-v-core-ip), including the company’s most recent products, the [SiFive Performance P870 and SiFive Intelligence X390](https://www.sifive.com/press/sifive-announces-differentiated-solutions-for-generative), which were designed to address new requirements for high-performance compute. \r\nSiFive is a sponsor of the Developer Zone where attendees can meet with SiFive technical experts and see the latest development boards. \r\n\nAlso make sure to check out SiFive’s speaking sessions at the show:\n•\tMonday, Nov. 6 (Member Day):\r\n•\t1 p.m. PST: Member Day Session: Future Direction of RISC-V Cryptography Extensions – Richard Newell, Microchip Technology Inc \u0026 Nicholas Bruine, SiFive\n•\t1:30 p.m. PST: Member Day Session: Unprivileged Specification ISA Committee – Krste Asanović, SiFive \u0026 Earl Killian, Aril Inc.\n•\t2 p.m. PST: Member Day Session: Discovering the RVV C Intrinsic API v. 1.0 – Eop Chen, SiFive\n•\t3 p.m. PST: Member Day Session: RISC-V N-Trace Specification – An Overview \r\n•\tTuesday, Nov. 7:\n•\t11:50 a.m. PST: Making LLVM RISC-V Compiler More Performant for Everyone \nSiFive \n•\t2:35 p.m. PST: Challenges in Porting Android to RISC-V – Samuel Holland, SiFive\r\n•\tWednesday, Nov. 8:\n•\t9 a.m. PST: Keynote: RISC-V ISA: State of the Union – Krste Asanović, RISC-V founder, SiFIve Chief Architect \u0026 RISC-V International BOD\r\n\r\n**WHO:** SiFive\r\n**WHEN:** Nov. 6-8, 2023\r\n\r\nSchedule [here](https://events.linuxfoundation.org/riscv-summit/program/schedule/).\r\n\r\n**WHERE:** RISC-V Summit North America\r\nSanta Clara Convention Center\r\n5001 Great America Parkway\r\nSanta Clara, California, 95054\r\n\r\nRegistration for the event is still open, [register today](https://events.linuxfoundation.org/riscv-summit/register/#register-now). \r\n\r\nTo schedule a meeting with SiFive onsite at the RISC-V Summit, please email: sifive@racepointglobal.com. \r\n\r\nSee more information on SiFive’s market-leading [RISC-V IP portfolio](https://www.sifive.com/risc-v-core-ip), please visit SiFive.com.\r\n\n","spans":[]}]}},{"id":"YqreURAAACEAj9kz","uid":"media-alert-sifive-at-embedded-world-2022","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YqreURAAACEAj9kz%22%29+%5D%5D","tags":[],"first_publication_date":"2022-06-16T13:00:05+0000","last_publication_date":"2024-05-28T20:13:23+0000","slugs":["media-alert-sifive-at-embedded-world-2022"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Media Alert: SiFive at Embedded World 2022","spans":[]}],"publish_to":"Archive","publish_date":"2022-06-16","share_image":{"link_type":"Media","kind":"image","id":"YqrljBAAACIAj_RN","url":"https://images.prismic.io/sifive/5346475c-9f9a-4983-a925-a7025915fbcf_EW%2BSiFiveLogo.png?auto=compress,format","name":"EW+SiFiveLogo.png","size":"918174","width":"1356","height":"779"},"body":[{"type":"preformatted","text":"**WHAT**: Onsite at Embedded World 2022, SiFive will be demonstrating its leadership in [vector processing](https://www.sifive.com/technology/vectors) and showcasing its SiFive® Intelligence™ X280 processor. Based on the RISC-V Vector Extension (RVV) Version 1.0 that was ratified by RISC-V International in 2021, SiFive’s vector processing addresses the explosive demand for data driven applications. As the market continues to witness new applications with multiple cores and added AI, ML, and computer vision capabilities, faster and power efficient processing is imperative. Built on RISC-V’s open standard foundation, SiFive’s vector processors deliver easy-to-program, scalable, flexible, and power efficient solutions to address today’s modern workloads. \n\nAttendees are encouraged to check out SiFive’s speaking sessions in the RISC-V Pavilion (1-550, Hall 1):\n\u003cbr\u003e**Tuesday, 21 June at 10:30**: [Introducing SiFive Vector Processor Portfolio](https://riscvew22.sched.com/event/128RZ/introducing-sifive-vector-processor-portfolio-andrew-frame-sifive) with Andrew Frame\n\u003cbr\u003e**Wednesday, 22 June at 10:00**: [The Next Generation SiFive Intelligence X280](https://riscvew22.sched.com/event/128Rc/the-next-generation-sifive-intelligence-x280-drew-barbier-sifive) with Drew Barbier\n\u003cbr\u003e**Thursday, 23 June at 14:00**: [Securing SiFive Vector Processors with an Open, Scalable Security Architecture](https://riscvew22.sched.com/event/128Rf/securing-sifive-vector-processors-with-an-open-scalable-security-architecture-dany-nativel-sifive) with Dany Nativel \n\nAdditionally, SiFive’s Drew Barbier is presenting the talk “Leveraging the Extensibility of RISC-V to Deliver Continuous Innovation” on Tuesday, 21 June at 17:00 as part of Embedded World’s 10.3: RISC-V Development track.\r\n\r\nCome by SiFive’s booth to learn more and discuss how SiFive can help differentiate your product to better target demanding market requirements.\n\n**WHO**: [SiFive](https://www.sifive.com)\n\n**WHEN**: 21-23 June 2022\r\n\u003cbr\u003e09:00 - 18:00 (21-22 June)\r\n\u003cbr\u003e09:00 - 17:00 (23 June)\r\n\r\n**WHERE**: [Embedded World](https://www.embedded-world.de/en)\n\u003cbr\u003eRISC-V International Pavillion\r\n\u003cbr\u003eBooth 1-550, Hall 1\r\n\u003cbr\u003eNuremberg Messe\r\n\u003cbr\u003eMessezentrum 1, 90471 Nürnberg, Germany\r\n\u003cbr\u003eSee the floorplan [here](https://www.embedded-world.de/en/exhibition-info/floorplan).\r\n\r\nRegistration for the conference is still open; sign up [today](https://www.embedded-world.de/en/participants/tickets/ticketshop). \n\r\nFor more information on SiFive’s market-leading RISC-V IP portfolio, please visit [SiFive.com](https://www.sifive.com).\r\n\n**About SiFive**\u003cbr/\u003e\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\n\n**Media Contact**\r\n\u003cbr\u003eAllison DeLeo\r\n\u003cbr\u003eRacepoint Global for SiFive\r\n\u003cbr\u003e[SiFive@racepointglobal.com](mailto:SiFive@racepointglobal.com)\r\n\u003cbr\u003eTel.: +1 (415) 694-6711 \r\n\n","spans":[]}]}},{"id":"ZGzsyRAAACIA8iZk","uid":"media-alert-sifive-to-showcase-automotive-solutions","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZGzsyRAAACIA8iZk%22%29+%5D%5D","tags":[],"first_publication_date":"2023-05-23T16:47:38+0000","last_publication_date":"2024-05-28T20:12:08+0000","slugs":["media-alert-sifive-to-showcase-automotive-solutions-at-automobil-elektronik-kongress-2023"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Media Alert: SiFive to Showcase Automotive Solutions at Automobil-Elektronik Kongress 2023","spans":[]}],"publish_to":"Archive","publish_date":"2023-05-23","share_image":{"link_type":"Media","kind":"image","id":"YyH61RIAAB8AR5tl","url":"https://images.prismic.io/sifive/049508cd-e3e0-49ad-8650-69ddb76710c0_automotive-familiy-graphic.png?auto=compress,format","name":"automotive-familiy-graphic.png","size":"4733","width":"202","height":"76"},"body":[{"type":"preformatted","text":"*WHAT: Onsite at Automobil-Elektronik Kongress*, SiFive will demonstrate the SiFive Automotive™ portfolio which features a wide range of current and future applications, including; electrification, cockpit, ADAS, safety, and others. SiFive’s Automotive Optimized CPU Portfolio, offers automakers simplicity, security and software flexibility that is supported by a broad industry ecosystem. \n\n\nAt the conference, SiFive experts can speak to the company’s broad, tailored Automotive portfolio including the Automotive E6-A series, offering automakers IP options that are both area and performance optimized for different integrity levels like ASIL B, ASIL D or split-lock, in line with ISO26262. With an ever-expansive need for automotive solutions, SiFive’s optimized RISC-V CPU IP helps to deliver high-end applications and real time processors that bring industry leading performance, with the lowest area and power consumption, tailored to vehicle specific needs for safety, security and performance. \n\n\nSiFive is the only RISC-V IP supplier to offer multiple processor series that optimally meet automotive designers’ exact compute, integrity, and security requirements across a broad range of computing applications, from MCUs to complex SoC \n\nCome by the booth to learn more and discuss how SiFive can help differentiate your product to better target demanding market requirements. \n\n*WHEN*: June 27-28, 2023 \n09:00 - 18:00 (27 June 2023) \n09:00 – 16:00 (28 June 2023) \nAgenda here. \n \n*WHERE*: Automobil-Elektronik Kongress \nBooth No. 47 \nForum am Schlosspark GmbH \nStuttgarter Strasse 33 \n71638 Ludwigsburg \n \nFor details on the conference visit their site [here](https://www.automobil-elektronik-kongress.de) \nFor more information on SiFive’s market-leading RISC-V IP portfolio, please visit [SiFive.com](https://www.sifive.com/cores/automotive) \n\n\nAbout SiFive \nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit SiFive.com. \n\n\nMedia Contact \nAllison DeLeo \nRacepoint Global for SiFive \nSiFive@racepointglobal.com \nTel.: +1(415)694-6711 \n \n\n","spans":[]}]}},{"id":"ZuoezBYAACQAZkob","uid":"sifive-highlights-key-inflection-points-driving-ri","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZuoezBYAACQAZkob%22%29+%5D%5D","tags":[],"first_publication_date":"2024-09-18T15:00:28+0000","last_publication_date":"2024-09-25T16:16:23+0000","slugs":["sifive-highlights-key-inflection-points-driving-riscv-adoption-for-ai-and-introduces-intelligence-xm-series-for-ai-workload-acceleration"],"linked_documents":[],"lang":"en-us","alternate_languages":[{"id":"ZvPcpBEAACYAzX13","type":"press_release","lang":"zh-cn","uid":"sifive-highlights-key-inflection-points-driving-ri"}],"data":{"page_title":"SiFive Announces New XM Series designed for accelerating high performance AI workloads","meta_description":"SiFive Highlights Key Inflection Points Driving RISC‑V Adoption for AI and Introduces Intelligence XM Series for AI Workload Acceleration.","title":[{"type":"heading1","text":"SiFive Highlights Key Inflection Points Driving RISC‑V Adoption for AI and Introduces Intelligence XM Series for AI Workload Acceleration","spans":[],"direction":"ltr"}],"publish_to":"Current Releases","publish_date":"2024-09-18","share_image":{"link_type":"Media","kind":"image","id":"ZuaeeLVsGrYSvX2t","url":"https://images.prismic.io/sifive/ZuaeeLVsGrYSvX2t_XMEnablesHighScalability.png?auto=format,compress?auto=compress,format","name":"XM Enables High Scalability.png","size":"670891","width":"959","height":"632"},"body":[{"type":"preformatted","text":"**SiFive event showcases how the RISC-V standard is driving AI innovation**\n\n**Santa Clara, Calif. – Sept. 18, 2024** – Today, SiFive, Inc. the gold standard for RISC-V computing, announced the SiFive [Intelligence XM Series™](https://www.sifive.com/cores/intelligence-xm-series) designed for accelerating high performance AI workloads. This is the first IP from SiFive to include a highly scalable AI matrix engine, which accelerates time to market for semiconductor companies building system on chip solutions for edge IoT, consumer devices, next generation electric and/or autonomous vehicles, data centers, and beyond.\n\nAs part of SiFive’s commitment to supporting its customers and the broader RISC-V ecosystem, SiFive also announced its intention to open source a reference implementation of its SiFive Kernel Library (SKL).\n\nThe announcement was made at a SiFive press event on Tuesday, Sept. 17 in Santa Clara, where executives discussed the leadership role the RISC-V architecture is playing at the core of AI solutions across a diverse range of market leaders, and provided an update on SiFive’s strategy, roadmap and business momentum.\n\nSiFive’s new XM Series offers an extremely scalable and efficient AI compute engine. By integrating scalar, vector, and matrix engines, XM Series customers can take advantage of very efficient memory bandwidth. The XM Series also continues SiFive’s legacy of offering extremely high performance per watt for compute-intensive applications. \n\n“Many companies are seeing the benefits of an open processor standard while they race to keep up with the rapid pace of change with AI. AI plays to SiFive’s strengths with performance per watt and our unique ability to help customers customize their solutions,” said Patrick Little, CEO of SiFive. “We’re already supplying our RISC-V solutions to five of the ‘Magnificent 7’ companies, and as companies pivot to a ‘software first’ design strategy we are working on new AI solutions with a wide variety of companies from automotive to datacenter and the intelligent edge and IoT.” \n\n“RISC-V was originally developed to efficiently support specialized computing engines including mixed-precision operations,” said Krste Asanovic, SiFive Founder and Chief Architect. “This, coupled with the inclusion of efficient vector instructions and the support of specialized AI extensions, are the reasons why many of the largest datacenter companies have already adopted RISC-V AI accelerators.” \n\nAs part of his presentation, Krste introduced more details on the new XM Series which broadens its [Intelligence Product family](https://www.sifive.com/cores/intelligence). The XM Series also continues SiFive’s legacy of offering extremely high performance per watt for compute-intensive applications. Featuring four X-Cores per cluster, a cluster can deliver 16 TOPS (INT8) or 8 TFLOPS (BF16) per GHz. There is 1TB/s of sustained memory bandwidth per XM Series cluster, with the clusters being able to access memory via a high bandwidth port or via a CHI port for coherent memory access. SiFive envisions the creation of systems incorporating no host CPU or ones based on RISC-V, x86 or Arm.\n\nThose interested in learning how to access the open source SKL or learn more about the XM family or other AI solutions from SiFive can contact us at [AIsolutions@sifive.com](mailto:AIsolutions@sifive.com). \n\nSiFive will be at the RISC-V Summit North America, taking place Oct. 22-23, 2024 in Santa Clara, Calif. To schedule an on-site meeting, please contact your sales representative or contact [sales](https://www.sifive.com/contact). \n \n**About SiFive**\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\n\n**Contact:**\n\nDavid Miller\u003cbr/\u003e\nCorporate Communications\u003cbr/\u003e\nDavid.miller@sifive.com\n\n\n\n","spans":[],"direction":"ltr"}]}},{"id":"YgC5QRIAANnjC6DT","uid":"sifive-partners-with-intel-to-spark-innovation-in-high-performance","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YgC5QRIAANnjC6DT%22%29+%5D%5D","tags":[],"first_publication_date":"2022-02-07T16:01:00+0000","last_publication_date":"2024-06-27T16:25:09+0000","slugs":["sifive-partners-with-intel-to-spark-innovation-in-high-performance-risc-v-platforms"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Partners with Intel to Spark Innovation in High-Performance RISC-V Platforms","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-02-07","share_image":{"link_type":"Media","kind":"image","id":"YgDIVBIAACYAC-ME","url":"https://images.prismic.io/sifive/8b608176-7639-4a35-b879-c1799ea4d677_IFS-SiFive-PR-1080x1080-Feb2022.png?auto=compress,format","name":"IFS-SiFive-PR-1080x1080-Feb2022.png","size":"157766","width":"1080","height":"1080"},"body":[{"type":"preformatted","text":"*Intel Innovation Fund Combines with SiFive RISC-V Leadership, IP, and Experience to Enable Custom SoC Design*\n\n**SAN MATEO, Calif., February 7, 2022** – [SiFive, Inc.](https://www.sifive.com), the founder and leader of RISC-V computing, today announced the company will support Intel Foundry Services (IFS) innovation fund’s goal to build innovative new RISC-V computing platforms optimized for Intel process technology. The $1B Intel fund will support the creation of disruptive technologies to address modern computing challenges, with the Intel-SiFive collaboration aiming to extend the RISC-V ecosystem. Compute blocks in future silicon chips, optimized for specific classes of workloads, require a vibrant market of semiconductor IP that is further enabled by SiFive’s leading RISC-V processor IP optimized and available to customers of IFS. The open nature of the RISC-V instruction set architecture creates freedom to innovate, with specifications and extensions developed by expert contributors from leaders in the semiconductor industry, research institutions, and academia.\u003cbr/\u003e\n\r\nSiFive has partnered with IFS to develop a RISC-V development platform, codenamed “Horse Creek,” featuring a multi-core SiFive Performance™ P550 processor, and implemented on the Intel 4 technology platform, on track for availability in 2022. The “Horse Creek” SoC will enable a new generation of RISC-V developer boards, continuing the tradition of SiFive HiFive boards that have helped drive the growth of the RISC-V ecosystem. To be informed of updates on the “Horse Creek” RISC-V developer board, please register [here](https://www.sifive.com/horse-creek-updates).\u003cbr/\u003e\n\r\n“Intel is making a substantial investment in the U.S. and Europe to create a world-class foundry business to serve the growing demand for semiconductors. We are pleased to be part of the IFS Innovation fund and work with Intel to significantly grow the RISC-V ecosystem based on SiFive platforms,” said Rohit Kumar, SVP Engineering, SiFive. “The unlimited potential of RISC-V is at the heart of SiFive’s leading portfolio of processor IP and will enable IFS Customers to build advanced designs using Intel technology.”\u003cbr/\u003e\n\r\n“The IFS innovation fund will help IFS customers develop modular technology including SiFive RISC-V processor IP optimized for the latest Intel process technology,” said Bob Brennan, VP and general manager, Customer Solutions Engineering, Intel Foundry Services. “We are looking forward to a multi-year coordinated effort with SiFive to continue to build out the RISC-V ecosystem by combining Intel open-source software expertise and resources with SiFive’s RISC-V expertise and IP.”\u003cbr/\u003e\n \r\nSiFive is also a proud member of the newly launch IFS ecosystem alliance, IFS Accelerator. SiFive will enable IFS customers to create computing platforms featuring RISC-V, optimized for their market applications. Intel’s broad portfolio of IP compliments the SiFive portfolio of performance-driven processor IP such as the [SiFive Intelligence™](https://www.sifive.com/cores/intelligence) and [SiFive Performance](https://www.sifive.com/cores/performance) families of processor IP. Recently, SiFive introduced the [SiFive Performance P650 processor](https://www.sifive.com/press/sifive-raises-risc-v-performance-bar-with-new-best-in-class), the fastest commercially available RISC-V CPU, intended for performance-driven markets including automotive, client computing, data center, mobile, and other applications. For more information on SiFive and IFS Accelerator - IP Alliance, please read our blog [here](https://www.sifive.com/blog/risc-v-is-ready-for-great-challenges).\u003cbr/\u003e\n\r\nSiFive continues to grow to meet the requirements of our customers and their roadmaps, and is looking for talented individuals to work alongside the inventors of RISC-V to help accelerate our roadmap of advanced high-performance processor IP. For more information, please visit [sifive.com/careers](https://www.sifive.com/careers). \u003cbr/\u003e\r\n\n**About SiFive**\u003cbr/\u003e\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\n\n\n\n","spans":[]}]}},{"id":"ZnmmNREAACYAnXLe","uid":"sifive-announces-4th-generation-of-popular-essential","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZnmmNREAACYAnXLe%22%29+%5D%5D","tags":[],"first_publication_date":"2024-06-25T06:00:00+0000","last_publication_date":"2024-06-26T16:08:21+0000","slugs":["sifive-announces-4th-generation-of-popular-essential-product-line-to-spur-innovation-across-embedded-applications"],"linked_documents":[],"lang":"en-us","alternate_languages":[{"id":"ZnrTuBEAACYAny9Z","type":"press_release","lang":"zh-cn","uid":"sifive-announces-4th-generation-of-popular-essential"}],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Announces 4th Generation of Popular Essential Product Line to Spur Innovation Across Embedded Applications","spans":[]}],"publish_to":"Current Releases","publish_date":"2024-06-25","share_image":{"link_type":"Media","kind":"image","id":"ZKL8PREAACQAGb8I","url":"https://images.prismic.io/sifive/798d7bc2-f7ea-4a0f-9fda-23998b35fc55_control-management.png?auto=format,compress?auto=compress,format","name":"control-management.png","size":"154003","width":"972","height":"843"},"body":[{"type":"preformatted","text":"**SiFive is seeing growing adoption, with more than two billion SiFive RISC-V based chips already in the market**\r\n\r\n**Munich, Germany, June 25, 2024** – Today SiFive, Inc. the gold standard for RISC-V computing, is unveiling a major upgrade of its SiFive Essential product family at the RISC-V Summit Europe 2024. Developed over a decade, the field-proven Essential IP is already in use in billions of products including mobile phones, sensors, SSDs, FPGA platforms, surveillance cameras, smartwatches and more. This full-portfolio refresh brings higher performance, improved power efficiency and more flexible interfaces, with configuration and integration options to cover virtually any possibility. The SiFive Essential Gen4 products are available today. \r\n \r\n“The best RISC-V embedded solutions just got much better with this fourth generation,” said John Ronco, SiFive SVP of Product. “With the benefits of cost-effective flexibility, performance and low power, RISC-V has won the battle for embedded. As legacy ISAs have reduced R\u0026D and support, we are expanding SiFive’s broad portfolio of market leading Essential products and reaffirming our commitment and support for customers in these critical areas of innovation.” \r\n\r\nSiFive has seen strong momentum across embedded segments where the Essential Gen4 products will bring impressive flexibility and features to enable customers to better tailor their designs. More than two billion SiFive RISC-V based chips for embedded devices have shipped to-date and the market continues to grow rapidly.\r\n \r\n“The embedded space in 2024 represents a huge ($257 billion) market opportunity, growing with an 8.3% CAGR through 2030. RISC-V and SiFive have been increasingly gaining momentum and taking share from the other ISAs. SiFive is launching the products that these customers need while also innovating at the high performance and advanced AI levels,” said Rich Wawrzyniak, Principal Analyst at The [SHD Group](https://theshdgroup.com/). “It is a mistake to discount the importance of embedded products as the flexibility and software portability of RISC-V makes designing products with multiple cores—including the highest performance cores—easier, creating a clear pathway for RISC-V into the next generations of high-performance chips.”\r\n\r\n**Essential Gen4 IP Portfolio Features:**\r\n\r\n- Broadest RISC-V CPU and system IP portfolio\n- Up to 40% runtime power reduction\n- 8 different baseline embedded 32-bit and 64-bit cores\n- From 2 stage single-issue to 8 stage superscalar\n- Improved L2 cache and enhanced L1 memory\n- Extensive configuration and integration options\n - CPU type, profile and options\n - On-chip memories selection\n - System, peripheral and front ports\n- Advanced power management and security\n- Debug and trace\n- Leading software support, including embedded Linux, FreeRTOS, Eclipse C/C++/ IDE\n\n\u003cbr/\u003e\n\n**Essential Gen4 portfolio:**\n\n\u003cdiv data-class=\"table-responsive\"\u003e\n\u003ctable data-class=\"simple head column\"\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth style=\"min-width:130px\"\u003e\u003c/th\u003e\n\u003cth style=\"min-width:140px\"\u003e2-3 stage single issue with lowest power and area\u003c/th\u003e\n\u003cth style=\"min-width:140px\"\u003e8-stage single issue for performance efficiency\u003c/th\u003e\n\u003cth style=\"min-width:140px\"\u003e8-stage dual issue for highest performance\u003c/th\u003e\n\u003c/tr\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd\u003e64-bit Application processors\u003c/td\u003e\n\u003ctd\u003e\u003c/td\u003e\n\u003ctd\u003eU6 Gen4\u003c/td\u003e\n\u003ctd\u003eU7 Gen4\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e64-bit real-time Embedded processors\u003c/td\u003e\n\u003ctd\u003eS2 Gen4\u003c/td\u003e\n\u003ctd\u003eS6 Gen4\u003c/td\u003e\n\u003ctd\u003eS7 Gen4\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e32-bit real-time Embedded processors\u003c/td\u003e\n\u003ctd\u003eE2 Gen4\u003c/td\u003e\n\u003ctd\u003eE6 Gen4\u003c/td\u003e\n\u003ctd\u003eE7 Gen4\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/thead\u003e\n\u003c/table\u003e\n\u003c/div\u003e\n\u003cbr/\u003e\n\nLearn more about the [SiFive Essential product family](https://www.sifive.com/cores/essential) here.\r\n\r\n**About SiFive**\n\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n ","spans":[]}]}},{"id":"Zrv0sxAAACIAkQ0j","uid":"sifive-announces-high-performance-risc-v-datacenter-processor-for-ai-workloads","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Zrv0sxAAACIAkQ0j%22%29+%5D%5D","tags":[],"first_publication_date":"2024-08-14T13:00:14+0000","last_publication_date":"2024-08-15T16:18:20+0000","slugs":["sifive-announces-new-highperformance-riscv-datacenter-processor-for-demanding-ai-workloads"],"linked_documents":[],"lang":"en-us","alternate_languages":[{"id":"Zr3RahEAAB4Aq2Kh","type":"press_release","lang":"zh-cn","uid":"sifive-announces-high-performance-risc-v-datacenter-processor-for-ai-workloads"}],"data":{"page_title":"SiFive Announces New High-performance RISC-V Datacenter Processor for Demanding AI Workloads","meta_description":"SiFive Performance P870-D brings high compute density and scalability to datacenters, vehicles, and embedded systems.","title":[{"type":"heading1","text":"SiFive Announces New High‑performance RISC‑V Datacenter Processor for Demanding AI Workloads","spans":[],"direction":"ltr"}],"publish_to":"Current Releases","publish_date":"2024-08-14","share_image":{"link_type":"Media","kind":"image","id":"ZJX-UhEAACcA5A5F","url":"https://images.prismic.io/sifive/9f85c5eb-f5b9-4da0-8a54-a2e29e67df6b_data-center-news.png?auto=format,compress?auto=compress,format","name":"data-center-news.png","size":"367243","width":"640","height":"361"},"body":[{"type":"preformatted","text":"**SiFive Performance P870-D brings high compute density and scalability to datacenters, vehicles, and embedded systems** \n\n**Santa Clara, Calif., Aug. 14, 2024** – Today SiFive, Inc., the gold standard for RISC‑V computing, announced its new [SiFive Performance™ P870-D datacenter processor](https://www.sifive.com/cores/performance-p870d) to meet customer requirements for highly parallelizable infrastructure workloads including video streaming, storage, and web appliances. When used in combination with products from the [SiFive Intelligence](https://www.sifive.com/cores/intelligence) product family, datacenter architects can also build an extremely high-performance, energy efficient compute subsystem for AI-powered applications. \n\nBuilding on the success of the P870, the P870-D supports the open AMBA CHI protocol so customers have more flexibility to scale the number of clusters. This scalability allows customers to boost performance while minimizing power consumption. By harnessing a standard CHI bus, the P870-D enables SiFive’s customers to scale up to 256 cores while harnessing industry-standard protocols, including Compute Express Link (CXL) and CHI chip to chip (C2C), to enable coherent high core count heterogeneous SoCs and chiplet configurations. \n\nThe P870-D processor enables the creation of infrastructure SoCs with higher compute density compared to the competition, offering improved performance per watt metrics for workloads that require the execution of multiple compute tasks in parallel. As a result, SiFive’s P870-D offers advantages in total cost of ownership, which is especially important as the industry is looking for ways to lower the cost of training AI models. Additionally, the power-efficiency of the P870-D aligns with the industry’s growing focus on sustainability. \n\n“SiFive brings a clean, modern approach to the AI era with our broad portfolio of RISC-V solutions. The new P870-D enhances our proven Performance architecture to bring new levels of performance, flexibility, and scalability ,” said John Ronco, SiFive SVP of Product. “The full solution offering from SiFive –- including software, IOMMU, interrupt controller and other uncore blocks -– combined with our intelligence processors for dedicated AI compute makes it easy for our customers to achieve the most effective performance/watt/dollar metrics on AI and Datacenter workloads”\n\n\"Energy efficiency is going to be a major factor for data center architects for the foreseeable future; This is a clear differentiator for RISC-V and why we expect the architecture to play a major role in the continued growth of high-performance data center processing,“ said Edward Wilford, Senior Research Director, Omdia. “We forecast that more power-efficient data center processors will make up over 40% of the market by volume in 2030, driven by the growth of open-source software and open-standard architecture.”\n\nSiFive is working with a number of ecosystem partners to help further streamline the development of complete systems. For example, Arteris has collaborated with SiFive as a lead partner to deliver emulation-ready reference design with the X280 and P870-D processors as the first products to validate the platform. By integrating SiFive’s RISC-V based processors with Arteris’ Network-on-Chip (NoC) IP, SiFive’s customers can accelerate development and get their products to market faster.\n\n“Network-on-Chip IP significantly helps streamline the process of building complex, multi-core heterogeneous SoCs with the lowest latency and high bandwidth to accommodate AI workloads,” said Michal Siwinski, CMO of Arteris. “We are pleased to continue the collaboration with SiFive, enabling the ecosystem to create high-performance and low-power RISC-V-based systems on time and budget while reducing risk.”\n\nSiFive also added Reliability Availability Serviceability (RAS) features to the P870-D. These RAS features are designed to detect errors before an issue arises and protect data integrity, helping to prevent downtime and ensure the overall reliability of the system. Additionally, the P870-D includes a distributed and scalable IOMMU for accelerating virtualized device IO, which is also critical to address the latest functional safety and security requirements. \n\n**Key Features**:\n\n- Delivers compute on demand with solutions scalable to 256 cores.\n- Fully compatible with the RVA23 profile, enabling system developers to leverage a breadth of operating systems, toolchains, and application software frameworks, which improves time to market while reducing program risk and development costs.\n- Supports the RISC-V Sv57 extension to enable 57-bit virtual address space support.\n- Supports 4 CHI ports/clusters and a wider link for multiple peripheral and memory device ports.\n- Integrates an Advanced Interrupt Architecture (AIA) compliant interrupt controller with support for Message Signaled Interrupts (MSI) and virtualization. \n\nFrom a software perspective, customers that create datacenter platforms harness a combination of open source software and first party software. Many of the foundational open source software elements already exist for RISC-V and this momentum is accelerating due to the collaborative efforts across the community such as the RISE Project. The P870-D processor is aligned with the platform and profile standards defined by RISC-V International which enables customers to utilize this software for their designs, saving time, cost, and increasing the chances of program success.\n\nTo further accelerate the development process, customers can leverage SiFive’s standard run-control debug capabilities, along with supported debugging solutions from leading tool vendors. To secure P870-D designs, SiFive’s customers can take advantage of the open WorldGuard model, which helps streamline the process of enabling a Trusted Execution Environment (TEE).\n\nThe P870-D processor is sampling to lead customers now with a final production release by the end of 2024.\n\n**About SiFive**\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\n","spans":[],"direction":"ltr"}]}},{"id":"ZtH56hEAACUAz7TJ","uid":"sifive-arkmicro-accelerate-risc-v-automotive-electronics-adoption","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZtH56hEAACUAz7TJ%22%29+%5D%5D","tags":[],"first_publication_date":"2024-08-30T17:13:56+0000","last_publication_date":"2024-08-30T17:13:56+0000","slugs":["sifive-and-arkmicro-accelerate-risc-v-adoption-in-automotive-electronics-with-sifives-automotive-ip-for-the-high-end-soc-market"],"linked_documents":[],"lang":"en-us","alternate_languages":[{"id":"ZtH7xBEAACUAz7e2","type":"press_release","lang":"zh-cn","uid":"sifive-arkmicro-accelerate-risc-v-automotive-electronics-adoption"}],"data":{"page_title":"SiFive and Arkmicro Accelerate RISC-V Adoption in Automotive Electronics with SiFive’s Automotive IP for the High-end SoC Market","meta_description":"Santa Clara, Calif., Aug. 30, 2024 — Today SiFive, Inc. announced that it has licensed its SiFive Automotive RISC-V IP cores to Arkmicro Technologies (Shenzhen), accelerating the adoption of RISC-V in automotive electronics. Arkmicro is a well-established chip company in the automotive industry, with products already certified and mass-produced by numerous international automotive companies. Arkmicro will integrate SiFive Automotive solutions into Arkmicro’s high-end automotive SoC chips.","title":[{"type":"heading1","text":"SiFive and Arkmicro Accelerate RISC-V Adoption in Automotive Electronics with SiFive’s Automotive IP for the High-end SoC Market","spans":[],"direction":"ltr"}],"publish_to":"Current Releases","publish_date":"2024-08-30","share_image":{"link_type":"Media","kind":"image","id":"ZtH8skaF0TcGJmfj","url":"https://images.prismic.io/sifive/ZtH8skaF0TcGJmfj_press-automotive.jpg?auto=format,compress?auto=compress,format","name":"press-automotive.jpg","size":"275596","width":"1445","height":"925"},"body":[{"type":"preformatted","text":"**Santa Clara, Calif., Aug. 30, 2024** — Today SiFive, Inc. announced that it has licensed its [SiFive Automotive RISC-V IP cores](https://www.sifive.com/cores/automotive) to Arkmicro Technologies (Shenzhen), accelerating the adoption of RISC-V in automotive electronics. Arkmicro is a well-established chip company in the automotive industry, with products already certified and mass-produced by numerous international automotive companies. Arkmicro will integrate SiFive Automotive solutions into Arkmicro’s high-end automotive SoC chips.\n\nSiFive has made significant investments in the automotive market over the years and the company has a growing list of top-tier customers and leading ecosystem partners. The SiFive Automotive series has achieved ISO 26262 and ISO 21434 certification; this pre-certified IP helps to reduce customers’ development time and effort. The SiFive Automotive series includes the 32-bit E6-A processor family and the [64-bit S7-AD processor family](https://www.sifive.com/cores/automotive-s7-ad). The [E6-A series](https://www.sifive.com/cores/automotive-e6-a) consists of the E6-AB processor, designed for real-time applications requiring ASIL B hardware safety integrity; the E6-AD processor, specifically developed for advanced driver assistance systems (ADAS) and other critical safety applications; and the E6-AS processor, which supports configurable lockstep and non-lockstep modes and achieves ASIL D integrity when configured in lockstep mode. The 64-bit S7-AD processor supports key safety applications, meeting customer demands for high-performance functional safety in applications such as zone controllers and functional safety islands.\n\n“SiFive recognized early on that the automotive market places exceptionally high demands on quality and safety. To address this, we assembled a world-class team of automotive functional safety (FuSa) experts to help our customers quickly deliver safe, reliable, and certified products,” said Pete Lewin, Senior Director of Automotive Products at SiFive.\n“We highly value our collaboration with Arkmicro, which possesses advanced technology in the automotive sector and has been dedicated to automotive electronics for years. Arkmicro's chip products have been successfully mass-produced and adopted by renowned automotive manufacturers globally. This partnership will contribute to the development of RISC-V in high-end automotive MCU chips.”\n\nThe collaboration between SiFive and Arkmicro will not only accelerate the progress of RISC-V in the automotive electronics domain, but also mark the beginning of a new chapter for the adoption of RISC-V in the automotive market at large. \nFor more information about the SiFive Automotive portfolio, please visit: [https://www.sifive.com/cores/automotive](https://www.sifive.com/cores/automotive).\n\n**About Arkmicro**\n\nArkmicro Technologies (Shenzhen), founded by prestigious inventors, is headquartered in Shenzhen with branches in Xian, Chengdu, and Qingdao. The company holds nearly 300 patents, and its products include chips for In-Vehicle Infotainment (IVI), digital instrument control, camera monitoring, driving data record/multi-segment display, video transmission, HUD display, navigation and positioning and ISP. With ISO26262 and AEC-Q100 certifications, Arkmicro’s products are widely used by companies such as BYD Auto,Chery Automobile, and SAIC Motor Corporation Limited.\n\n**About SiFive**\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.","spans":[],"direction":"ltr"}]}},{"id":"ZUJ2LRIAACMAu9qI","uid":"sophgo-licenses-sifive-risc-v-processor-cores-to-drive","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZUJ2LRIAACMAu9qI%22%29+%5D%5D","tags":[],"first_publication_date":"2023-11-01T16:01:41+0000","last_publication_date":"2023-11-02T16:47:35+0000","slugs":["sophgo-licenses-sifive-riscv-processor-cores-to-drive-high-performance-ai-computing-innovation","sophgo-licenses-sifive-risc-v-processor-cores-to-drive-high-performance-ai-computing-innovation"],"linked_documents":[],"lang":"en-us","alternate_languages":[{"id":"ZUJ2exIAACAAu9sB","type":"press_release","lang":"zh-cn","uid":"sophgo-licenses-sifive-risc-v-processor-cores-to-drive"}],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Sophgo Licenses SiFive RISC‑V Processor Cores to Drive High-Performance AI Computing Innovation","spans":[]}],"publish_to":"Current Releases","publish_date":"2023-11-01","share_image":{"link_type":"Media","kind":"image","id":"ZJYAAxEAACQA5BNE","url":"https://images.prismic.io/sifive/bf7492ca-34df-41c3-8a79-c5b042356a4f_AI-ML-vector-news.jpg?auto=compress,format","name":"AI-ML-vector-news.jpg","size":"63060","width":"640","height":"361"},"body":[{"type":"preformatted","text":"\r\n**SiFive’s Multi-Cluster, Multi-Cores P670 and X280 Power the Open Standard Platform for High-Performance AI Applications**\r\n\r\n**Santa Clara, Calif., November 1, 2023 –** Today, Sophgo announced that the company has licensed several SiFive RISC-V high performance processor cores, the [SiFive Performance P670](https://www.sifive.com/cores/performance-p650-670) and [SiFive Intelligence X280](https://www.sifive.com/cores/intelligence-x280) to develop RISC-V AI computing processors. Presented on SG2380 Kick-off Day at the Zhongguancun IC Park in Beijing, the new SiFive cores will be used in the upcoming, Sophgo SG2380. \r\n\r\nThe new Sophgo SG2380 is a 2.5 GHz 16-core RISC-V processor, utilizing the SiFive Performance P670 with a multi-cluster, multi-core configuration. It boasts high performance and RISC-V vector computation advantages. SG2380 also incorporates SiFive Intelligence X280 and a Vector Cooperative Processor Interface Extension (VCIX), integrating Sophgo's AI/ML hardware design. With complete software toolchain support from RISC-V, this coprocessor is targeting not only AI/ML but various advanced computing needs.\r\n\r\nThe P670, combined with RISC-V's unique instruction set architecture advantages and advanced microarchitecture design with silicon implementation by the SiFive team, offers high computational density and vector computation capabilities. Sophgo has also utilized the proven X280, paired with VCIX, as an NPU, highlighting the synergies between the two companies in this collaboration.\r\n\r\nThe SiFive P670 is currently the highest-performance and fully spec-compliant RISC-V commercial-grade processor IP (SpecINT2k6 exceeding 13/GHz) available in the market. SiFive offers multi-cluster, multi-core P670-compliant with RVA22, supporting the latest RISC-V specifications and operating systems, providing optimal performance and the lowest power consumption. The SiFive X280 offers flexibility and scalability in AI applications, supporting multi-core, multi-cluster configurations and numerous successful chip instances. The development tools and software support the latest OpenXLA framework, in line with the market demand and future application trends of AI.\r\n\r\nFor more information about Sophgo SG2380, please refer to CNX SOFTWARE – EMBEDDED SYSTEMS NEWS: [Sophgo SG2380](https://www.cnx-software.com/2023/10/21/sophgo-sg2380-16-core-sifive-p670-risc-v-processor-20-tops-ai-accelerator/) – A 2.5 GHz 16-core SiFive P670 RISC-V processor with a 20 TOPS AI accelerator.\r\n\r\n**About SOPHGO**\r\n\r\nSOPHGO is committed to becoming the world's leading provider of universal computing power, focusing on the development and promotion of computing power products such as AI and RISC-V processors, following the ecological concept of full open source and openness, and working with ecological partners to create a full-scene product matrix covering \"cloud, edge and endpoint\". Provide computing products and overall solutions for Internet, Urban operations, Intelligent computing centers, General security, Intelligent manufacturing, and AIGC and other application scenarios. Our company has research and development centers in more than 10 cities in China such as Beijing, Shanghai, Shenzhen, Qingdao, Xiamen, as well as in countries such as the United States and Singapore. Since 2016, our brand's SOPHON series products have undergone multiple iterations, achieving significant improvements in energy efficiency compared to their predecessors in each generation.\r\n\r\n\r\n","spans":[]}]}},{"id":"ZhRRcRIAACQAs7uj","uid":"sifive-unveils-the-hifive-premier-p550-the-first-commercially","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZhRRcRIAACQAs7uj%22%29+%5D%5D","tags":[],"first_publication_date":"2024-04-09T06:00:08+0000","last_publication_date":"2024-04-10T17:30:20+0000","slugs":["sifive-unveils-the-hifive-premier-p550-the-first-commercially-available-out-of-order-risc-v-development-board"],"linked_documents":[],"lang":"en-us","alternate_languages":[{"id":"ZhYtDRIAACAAglvo","type":"press_release","lang":"zh-cn","uid":"sifive-unveils-the-hifive-premier-p550-the-first-commercially"}],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Unveils the HiFive Premier P550, the First Commercially Available Out-of-order RISC-V Development Board","spans":[]}],"publish_to":"Current Releases","publish_date":"2024-04-09","share_image":{"link_type":"Media","kind":"image","id":"ZhBMMxIAACQAohC-","url":"https://images.prismic.io/sifive/295e8b80-0c25-4cd4-8dc5-97fcaab9c058_HiFive-Premier-P550.jpg?auto=compress,format","name":"HiFive-Premier-P550.jpg","size":"786367","width":"1200","height":"1093"},"body":[{"type":"preformatted","text":"**HiFive Premier P550 is the highest performance RISC-V development board on the market, offering developers unmatched flexibility and performance**\r\n\r\n**Nuremberg, Germany – April 9, 2024** – Today at Embedded World, SiFive, Inc., the pioneer and leader of RISC-V computing, unveiled its new state-of-the-art RISC-V development board, the [HiFive™ Premier P550](https://www.sifive.com/boards/hifive-premier-p550). The board will be available for large-scale deployment through Arrow Electronics so developers around the world can test and develop new RISC-V applications like machine vision, video analysis, AI PC and others, allowing them to use AI and other cutting-edge technologies across many different market segments.\r\n\r\nWith a quad-core SiFive Performance™ P550 processor, the HiFive Premier P550 is the highest performance RISC-V development board in the industry, and the latest in the popular HiFive family. Designed to meet the computing needs of modern workloads, the out-of-order P550 core delivers superior compute density and performance in an energy-efficient area footprint. Furthermore, the modular design of the HiFive Premier P550, which includes a replaceable system-on-module (SOM) board, gives developers the flexibility they need to tailor their designs.\r\n\r\n“The popularity of our development boards underscores the growth and maturity of the RISC-V ecosystem,” said Patrick Little, CEO and Chairman at SiFive. “The HiFive board has always been the ‘golden reference’ RISC-V development platform. Building on this proven foundation with the new HiFive Premier P550, developers can take advantage of SiFive’s high-performance IP in a cost-efficient platform that will be available in volume, opening up unlimited possibilities for RISC-V innovation in AI applications and beyond.”\r\n\r\nSiFive is collaborating with [Canonical](https://canonical.com), the publisher of Ubuntu, to ensure that developers can smoothly run the Linux distribution on the HiFive Premier P550. Ubuntu is free to use and comes with five years of free security maintenance for the operating system. Developers and innovators can rely on Ubuntu’s stable and secure platform to access the open source software ecosystem, and get access to bug fixes and security updates for 10+ years backed by Canonical’s enterprise-grade support.\r\n\r\n“RISC-V is giving developers a new level of freedom to innovate, and SiFive is one of the top companies leading the charge. The availability of HiFive Premier P550 is a significant milestone for the RISC-V development community,” said Gordan Markuš, Silicon Alliances Director at Canonical. “Thanks to our collaboration with SiFive, developers using the HiFive Premier P550 board will be able to innovate at speed with Ubuntu. Additionally, Canonical’s software and services will accelerate time to market, and ensure long-term support and security maintenance for our enterprise partners.”\r\n\r\n**Technical Features**\r\n\r\nThe Eswin EIC7700 SoC found on the board features a high performance 64-bit three-issue, out-of-order, SiFive RISC-V P550 core complex configured with four P550 cores, 256KB L2 cache and 4MB L3 cache. The SoC features a 2D/3D GPU, hardware video encoder/decoder, NPU, DSP, MIPI DSI, a security subsystem, an integrated high speed DDR5 memory controller, root complex PCI Express Gen 3 x4 and standard peripherals.\r\nOther features include:\r\n\n•\t16 GB of 64-bit LPDDR5-6400 memory, 128 GB of eMMC memory for fast boot\r\n\n•\tHigh speed interconnects with PCI Express Gen3 x4 via a PCIe x16 slot\r\n\n•\t5 USB 3 ports for peripheral connectivity\r\n\n•\tSoftware support with Freedom U-SDK, including Linux\r\n\n•\tReplaceable SOM for flexibility in design\r\n\r\nSiFive’s lineup of development boards also includes the popular [HiFive Unmatched Rev. B](https://www.sifive.com/boards/hifive-unmatched-revb), which is available today. To help streamline the development process, SiFive provides comprehensive documentation, software development kits, toolchains, utilities, and software ecosystem solutions for each SiFive RISC-V development board.\r\n\nThe HiFive Premier P550 is expected to be available through Arrow Electronics in July 2024. Pre-orders can be placed on [Arrow.com](https://www.arrow.com/en/products?utm_currency=USD\u0026gad_source=1\u0026gclid=Cj0KCQjwq86wBhDiARIsAJhuphmHYM5OwXSNugkKDx9rT3lYp3aOda0ftb4XyxqvkyGW8V218xAkJSMaAkZnEALw_wcB\u0026gclsrc=aw.ds)). To learn more, please visit: [https://www.sifive.com/boards/hifive-premier-p550](https://www.sifive.com/boards/hifive-premier-p550). \r\n\r\n**About [SiFive](https://www.sifive.com)**\r\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\r\n\r\n###\r\n\r\n","spans":[]}]}},{"id":"XNnVbBAAACQAPa61","uid":"media-alert-sifive-tech-symposiums-on-risc-v-coming","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XNnVbBAAACQAPa61%22%29+%5D%5D","tags":[],"first_publication_date":"2019-05-13T21:05:38+0000","last_publication_date":"2024-04-09T19:24:25+0000","slugs":["media-alert-sifive-tech-symposiums-on-risc-v-coming-to-europe-this-month"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Media Alert: SiFive Tech Symposiums on RISC-V Coming to Europe This Month","spans":[]}],"publish_to":"Archive","publish_date":"2019-05-08","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"_Powerful one-day events to be held in Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam_\n\n**SAN MATEO, California, May 8, 2019 -**\r\n[SiFive](https://www.sifive.com), the company founded by the inventors of the RISC-V architecture, and leading provider of commercial RISC-V processor IP and custom SoC solutions, and several co-hosts and ecosystem partners, including:\r\n\r\n- Co-hosts: Imagination Technologies, Mentor, Qamcom, Syntacore\r\n- Partners: Antmicro, Credo, IAR Systems, Rambus, SecureRF, UltraSoC\r\n\r\n**WHAT:** The SiFive Tech Symposiums on RISC-V will take place in six cities in Europe throughout the month of May. These highly educational events are free to attend, and present many opportunities for engagement with the hardware community. Each event will feature presentations by industry veterans, ecosystem partners and academic luminaries. Attendees will learn about the RISC-V ecosystem and the SaaS-based approach that is enabling fast access to the custom cores, design platforms, and custom SoC solutions for emerging applications.\r\n\r\n**WHEN/WHERE:**\r\n\r\n- Cambridge – May 13, 2019\r\n- Grenoble – May 15, 2019 \r\n- Stockholm – May 17, 2019\r\n- Moscow – May 20, 2019 \r\n- Munich – May 23, 2019 \r\n- Amsterdam – May 29, 2019\r\n\r\n**About SiFive**\r\n\r\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [www.sifive.com](https://www.sifive.com).","spans":[]}]}},{"id":"ZN5LiBAAACIAHwRE","uid":"media-alert-sifives-leadership-to-keynote-at-the","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZN5LiBAAACIAHwRE%22%29+%5D%5D","tags":[],"first_publication_date":"2023-08-17T16:43:13+0000","last_publication_date":"2023-08-24T23:58:55+0000","slugs":["media-alert-sifives-leadership-to-keynote-at-the-risc-v-summit-china-2023"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"MEDIA ALERT: SIFIVE’S LEADERSHIP TO KEYNOTE AT THE RISC-V SUMMIT CHINA 2023 ","spans":[]}],"publish_to":"Current Releases","publish_date":"2023-08-17","share_image":{"link_type":"Media","kind":"image","id":"ZN4uhxAAACAAHob4","url":"https://images.prismic.io/sifive/cfd727e8-24a8-49eb-a384-25dbd7c0d5a3_risc-v-logo.png?auto=compress,format","name":"risc-v-logo.png","size":"14996","width":"700","height":"700"},"body":[{"type":"preformatted","text":"**WHAT:** SiFive will be onsite at the RISC-V Summit China, scheduled for Aug. 23 – 25, 2023 in Beijing. Hosted in partnership with RISC-V International and the Beijing Institute of Open Source Chip (BOSC), SiFive will deliver two keynotes on the future of RISC-V and the latest on SiFive’s high-performance RISC-V processors. SiFive will also host a series of technical sessions focused on RISC-V vectors, ML compilers, hibernation, and more.\n \r\nAt the event, SiFive experts can speak to the company’s broad Core IP portfolio, spanning from high-performance application processors to area-optimized, low-power embedded 64- and 32-bit microcontrollers, to vector processors designed for modern compute requirements and artificial intelligence (AI), and optimized for the specific needs of the automotive industry.\n\r\nAt RISC-V Summit China, global innovators will share technical and business innovation around RISC-V. The summit features a multi-track conference, tutorials, exhibitions and poster sessions. There will be real-time Chinese to English translations for in-person and virtual attendees.\n\r\nIn-person and virtual attendees are encouraged to check out SiFive’s speaking sessions:\n\r\n**Wednesday, 23 August:**\r\n•\t15:20: KEYNOTE: The RISC-V Future is Unlimited: China’s Role with Yunsup Lee\r\n•\t17:00: KEYNOTE: It Just Keeps Getting Better: RISC-V Processor Performance with Jack Kang\n\r\n**Friday, 25 August:**\r\n•\t09:50: The Story of Getting RISC-V Vector in Linux with Andy Chiu and Zong Li\r\n•\t14:10: Discovering the RVV C Intrinsics v1.0 with Eop Chen and Kito Cheng\r\n•\t14:30: Software Components and Methodology for Designing and Optimizing RISC-V ML Compilers – A 3-Year Lesson of Collaboration With OpenXLA with Hong-Rong Hsu and Pen Li\r\n•\t16:40: Accelerating the Migration from Arm Neon to RISC-V Vectors with Han-Kuan Chen\r\n\r\n\r\n**WHO:** SiFive\r\n\n**WHEN:** August 23-25, 2023\r\n09:00 - 18:00 CST (23 August 2023)\r\n09:00 – 19:10 CST (24-25 August 2023)\r\n\nAgenda [English](https://riscv-summit-china.com/en/agenda.html), [Chinese](https://riscv-summit-china.com/cn/agenda.html).\r\n\r\n**WHERE:** RISC-V Summit China\r\nShangri-La Hotel Beijing\r\nBeijing\r\n\r\nRegistration for the in-person and virtual event is open, register today. \r\n\r\nTo schedule a meeting with SiFive onsite at RISC-V China Summit, please email: sifive@racepointglobal.com. \r\n\r\nAbout SiFive \r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. \r\n\nFollow live news and updates from the show floor with the #RISCVSummitChina hashtag on X and LinkedIn.\r\n\nMedia Contact \r\nAllison DeLeo\r\nRacepoint Global for SiFive\r\nSiFive@racepointglobal.com \r\nTel.: +1(415)694-6711\r\n\r\n","spans":[]}]}},{"id":"ZSXyfxAAACAAY44W","uid":"sifive-announces-differentiated-solutions-for-generative","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZSXyfxAAACAAY44W%22%29+%5D%5D","tags":[],"first_publication_date":"2023-10-11T21:30:00+0000","last_publication_date":"2023-10-13T20:29:16+0000","slugs":["sifive-announces-differentiated-solutions-for-generative-ai-and-ml-applications-leading-risc-v-into-a-new-era-of-high-performance-innovation"],"linked_documents":[],"lang":"en-us","alternate_languages":[{"id":"ZSmowhAAAB4Ac5Cv","type":"press_release","lang":"zh-cn","uid":"sifive-announces-differentiated-solutions-for-generative"}],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Announces Differentiated Solutions for Generative AI and ML Applications Leading RISC-V into a New Era of High-Performance Innovation","spans":[]}],"publish_to":"Current Releases","publish_date":"2023-10-11","share_image":{"link_type":"Media","kind":"image","id":"ZSWZLRAAAB4AYgL4","url":"https://images.prismic.io/sifive/dea8a105-856d-4d62-a28c-c778d8174e6e_SiFive-High-Performance-NPU.PNG?auto=compress,format","name":"SiFive-High-Performance-NPU.PNG","size":"888530","width":"4000","height":"2250"},"body":[{"type":"preformatted","text":"**SiFive’s Performance P870 and Intelligence X390 product debut sets new bar for high-performance compute in consumer, infrastructure, and automotive applications**\r\n \r\n**Santa Clara, Calif., Oct. 11, 2023** –SiFive, Inc., the pioneer and leader of RISC-V computing today announced two new products designed to address new requirements for high performance compute. The SiFive Performance™ P870 and SiFive Intelligence™ X390 offer a new level of low power, compute density, and vector compute capability, and when combined provide the necessary performance boost for increasingly data intensive compute. Together, the new products create a powerful mix of scalar and vector computing to meet the needs of today’s dataflow and computation intensive AI applications across consumer, automotive, and infrastructure markets. \r\n\r\nThe announcement took place at an in-person press and analyst event in Santa Clara today, where the company also provided an update on several of its product lines currently shipping in silicon to customers around the world. Company executives offered insight into SiFive’s product roadmap and discussed how the overall RISC-V ecosystem continues to expand rapidly as new applications call for the benefits of RISC-V-based high-performance compute solutions.\r\n \r\n“SiFive is leading the industry into a new era of high-performance RISC-V innovation, and closing the gap with other instruction set architectures with our unparalleled portfolio, while recent silicon tape-outs are demonstrating the tremendous benefits of SiFive RISC-V solutions,” said Patrick Little, SiFive Chairman, President and CEO. “As the Arm IPO showed, there is a fast-growing demand for semiconductors across many sectors, particularly processors for consumer and infrastructure markets. The flexibility of SiFive’s RISC-V solutions allows companies to address the unique computing requirements of these segments and capitalize on the momentum around generative AI, where we have seen double-digit design wins, and for other cutting-edge applications. \r\n \r\n**The SiFive Performance P870**\r\n \r\nIdeal for high performance consumer applications, or when used in conjunction with a vector processor in the datacenter, the P870 core sets an impressive new RISC-V performance bar across instruction set architecture availability, throughput, parallelism, and memory bandwidth. Bringing a 50% peak single thread performance upgrade (specINT2k6) over the previous generation SiFive Performance processors, the P870 is a six-wide out-of-order core, that meets RVA 23 and offers a shared cluster cache enabling up to a 32-core cluster. High execution throughput comes with more instruction sets per cycle, more ALU, and more branch units. The P870 is fully compatible with Google’s platform requirements for Android on RISC-V. The P870 also offers additional proven SiFive features:\r\n·\tx 128b VLEN RVV\r\n·\tVector crypto and hypervisor extensions\r\n·\tIOMMU and AIA\r\n·\tNon-inclusive L3 cache\r\n·\tProven RISC-V WorldGuard security\r\n \r\n**The SiFive Intelligence X390**\r\n\r\nBuilding on the highly popular SiFive Intelligence X280’s success in coupling AI/ML applications with hardware accelerators in mobile, infrastructure, and automotive applications, the new X390 brings a 4x improvement to vector computation with its single core configuration, doubled vector length, and dual vector ALUs. This allows quadruple the amount of sustained data bandwidth. With SiFive Vector Coprocessor Interface eXtension (VCIX) companies can easily add their own vector instructions and/or acceleration hardware, bringing unprecedented flexibility and allowing users to greatly increase performance with custom instructions. Features include:\r\n·\t1024-bit VLEN, 512-bit DLEN\r\n·\tSingle / Dual Vector ALU\r\n·\tVCIX (2048-bit out, 1024-bit in)\r\n\r\n**An Agile Hardware Solution for Generative AI applications**\r\n \r\nBringing the P870 high-performance general compute SoC together with a high performance NPU cluster, consisting of the X390 and customer AI hardware engines, offers product designers a highly flexible, low power, and programmable solution with superior compute density for complex workloads. \r\n \r\nThe company highlighted how interest in these combined SiFive solutions is high, with a number of customers achieving silicon success and in various stages of commercialization using high performance products.\r\n \r\nSiFive continues to actively work across the ecosystem (see attached quote sheet) with partners who are ensuring the software, security, and flexibility benefits of the open standard ecosystem are in place for SiFive processors as companies move to commercialize their SiFive-powered products.\r\n \r\n**Supporting quotations from industry partners:**\r\n\r\nSiFive has assembled an array of ecosystem partners to help customers speed their time to commercialization. \r\n\r\n\"We have collaborated with SiFive to deliver [Cadence](https://www.cadence.com/en_US/home.html) AI-driven digital full flow Rapid Adoption Kits (RAKs) for previous generation SiFive Performance™ and Intelligence™ RISC-V processors and are looking forward to producing them for the upcoming P870 and X390 processors\" said KT Moore, vice president of Corporate Marketing, Cadence. \"The RAKs utilize our leading Generative AI solutions that optimize power, performance and area while our system verification solutions enable optimal verification throughput and productivity. This empowers SiFive customers to accelerate time-to-market, enhance product quality, and deliver innovative solutions for high-performance computing, AI, automotive, and mobile applications.\"\r\n\r\n“[Canonical’s](https://canonical.com) strategic alliance with SiFive, a RISC-V CPU IP leader, grants us exclusive privileges, including early access to their cutting-edge processors under development. Canonical has ported Ubuntu to SiFive development systems in the past and is working to have Ubuntu ready at launch with the SiFive HiFive Pro P550 and future platforms,” said Cindy Goldberg, Vice President, Silicon Alliances at Canonical. “We see a growing demand for SiFive RISC-V processors and recognize the opportunity across consumer, automotive and infrastructure markets. Ubuntu is the operating system of choice for infrastructure and cloud use cases. This year with the introduction of Ubuntu Pro we have enhanced security, compliance and support coverage across a broad portfolio of open source software and platform architectures. The combination of SiFive’s RISC-V IP and Canonical’s software is a combination that will lead the transformative future in computing, on RISC-V.”\r\n\r\n“As an early RISC-V adopter and industry leader for delivering production-proven, safety-certified development tools, C/C+ compilers and operating systems for RISC-V, [Green Hills Software](https://www.ghs.com/partners/sifive_partner.html) is excited to be expanding its close working relationship with SiFive by adding optimized support for the P870 and X390.” said Dan Mender, VP of Business Development at Green Hills Software. “Together, Green Hills and SiFive will help companies realize the maximum performance, power, and area benefit possible for these new SiFive offerings.”\r\n\r\n“[IAR](https://www.iar.com/) welcomes the new SiFive Performance P870 and Intelligence X390 RISC-V processors and recognizes their opportunity for generative AI and ML as well as high-performance computing applications addressing consumer, automotive, and infrastructure. IAR and SiFive have a strong partnership and stand out in the RISC-V ecosystem. SiFive enables IAR with early access its leading commercial RISC-V IP processors while they are under development, enabling co-optimizations benefiting mutual customers. IAR’s complete development solution for all the leading RISC-V core IP from SiFive helps embedded software developers around the world maximize the energy efficiency, simplicity, security, and flexibility upsides that RISC-V and SiFive offer, like the latest additions for Generative AI/ML applications.”\n\n\n“As the world leader in debugging and trace tools used by all major and well-known technology companies, [Lauterbach](https://www.lauterbach.com/supported-platforms/architectures/risc-v) has been committed to supporting the RISC-V ecosystem from the beginning and is a close long-term partner of SiFive, a leading provider of RISC-V CPU IP. Currently, we see a strong growing global demand for RISC-V based processors including generative AI and ML applications as well as high performance compute across consumer, automotive, and infrastructure markets, all markets in which we have been successfully active for many years. Our early access to SiFive's processors under development allows both SiFive and Lauterbach to co-optimize their products for an optimal user experience.” Norbert Weiss, Managing Director, Lauterbach GmbH\r\n\r\n\"SiFive has been instrumental in bringing the RISC-V architecture to [Automotive Grade Linux](https://www.automotivelinux.org) and providing additional hardware options for automakers and suppliers, many of whom are already using the open source AGL platform in production,\" said Dan Cauchy, Executive Director of Automotive Grade Linux (AGL), an open source project at The Linux Foundation. \"SiFive is an active AGL member, and we look forward to their continued collaboration with the broader community.\" \r\n\r\n“The growth of AI and machine learning systems is driving significant compute demands in application-specific processors. Our collaboration with SiFive to provide co-optimized solutions including [Synopsys.ai™](https://www.synopsys.com) full-stack AI-driven EDA suite and Fusion QuickStart Implementation Kits, along with Synopsys Interface and Foundation IP, hardware-assisted verification, and virtual prototyping solutions help mutual customers accelerate the design of high-performance, RISC-V-based SoCs.” Kiran Vittal, Senior Director of Partner Alliances Marketing for the EDA Group, Synopsys.\n\n**About SiFive**\r\n\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. \n\n####\r\n\r\n\r\n\r\n","spans":[]}]}},{"id":"ZG6EwBAAACIA-SAF","uid":"sifive-gives-worldguard-to-risc-v-international-to","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22ZG6EwBAAACIA-SAF%22%29+%5D%5D","tags":[],"first_publication_date":"2023-05-24T21:45:23+0000","last_publication_date":"2023-06-22T14:41:28+0000","slugs":["sifive-gives-worldguard-to-risc-v-international-to-make-this-robust-security-model-more-accessible-to-the-risc-v-community"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Gives WorldGuard to RISC-V International to Make this Robust Security Model More Accessible to the RISC-V Community","spans":[]}],"publish_to":"Current Releases","publish_date":"2023-05-24","share_image":{"link_type":"Media","kind":"image","id":"Yo5e3hAAACMAE1GU","url":"https://images.prismic.io/sifive/7786bbd1-64b7-48fe-8f77-b1330c8591f8_Introduction-to-SiFive-Vector-Processors.png?auto=compress,format","name":"Introduction-to-SiFive-Vector-Processors.png","size":"194097","width":"780","height":"440"},"body":[{"type":"preformatted","text":"\r\n**The open WorldGuard model provides a system-level approach to securing RISC-V designs**\r\n\r\n**Santa Clara, Calif., May 24, 2023 – SiFive, Inc.**, the pioneer and leader of RISC-V computing, today announced the company is giving the WorldGuard security model to RISC-V International, providing the RISC-V community with a uniform way to secure their designs and bring them to market faster. RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community which has more than 3,570 RISC-V members across 70 countries.\r\n\r\nWorldGuard makes it easy for developers to enable a Trusted Execution Environment (TEE) on RISC-V platforms. As a hardware-enhanced software isolation solution, WorldGuard provides protection against improper access to memory or devices by software applications and other bus initiators (such as DMAs). Designers can quickly create domains, also known as “worlds,” for isolated code execution and data protection. WorldGuard doesn't break the RISC-V ISA and doesn't require new instructions to be used. It simply adds secure metadata to the transactions issued by the various bus initiators and checks permissions against an Access Control List (ACL) at the destination, whether it's memory or a peripheral. The isolation is based on multiple levels of privilege for each world, offering robust SoC-level information control. \r\n\r\n“Robust security is fundamental to every silicon design, but many of the latest security solutions are out of reach for developers,” said Dany Nativel, Senior Director, Product Marketing at SiFive. “From the start, our WorldGuard security model was open and freely accessible for developers to secure their designs at a system level. By donating WorldGuard to RISC-V International, we hope that even more developers will take advantage of it so the entire RISC-V ecosystem can benefit.”\r\n\r\nWorldGuard provides an open, system-level approach to securing access to system resources (memory and peripherals) by software applications. This approach is ideal for creating multiple trusted environments, enabling a Trusted Computing Base (TCB) where the highest level of trust is limited to the secure ROM boot, the Machine-mode firmware, the secure applications, and the Operating Systems (OSs) that implement them. This base of trust is also referred to as the “Trusted Agent.”\r\n\r\n“One of the biggest advantages of RISC-V is the active community that is committed to sharing resources and collaborating. Instead of having to reinvent the wheel, developers can use open tools like WorldGuard to ensure their products are secure and speed up time-to-market,” said Calista Redmond, CEO of RISC-V International. “We appreciate SiFive’s donation of WorldGuard as we all work together to secure the future of RISC-V innovation.”\r\n\r\nOngoing development of WorldGuard will now be managed by RISC-V International. SiFive will continue to contribute its expertise and resources.\r\n\r\n**About SiFive**\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit SiFive.com.\r\n\r\n\r\n**Media Contacts**\r\nAllison DeLeo \r\nRacepoint Global for SiFive \r\nSiFive@racepointglobal.com \r\nTel.: +1(415) 694-6711\n\nDave Miller,\nCorporate Communications\ndavid.miller@sifive.com","spans":[]}]}},{"id":"XK1DoREAAB8ABmd_","uid":"sifive-launches-the-worlds-smallest-commercial-64-bit","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XK1DoREAAB8ABmd_%22%29+%5D%5D","tags":[],"first_publication_date":"2019-04-10T13:00:00+0000","last_publication_date":"2023-05-16T14:05:57+0000","slugs":["sifive-launches-the-worlds-smallest-commercial-64-bit-embedded-core"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Launches the World’s Smallest Commercial 64-bit Embedded Core","spans":[]}],"publish_to":"Archive","publish_date":"2019-04-10","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*RISC-V Leader brings unmatched advanced 64-bit Core IP capability to embedded space*\n\n**SAN MATEO, Calif. \u0026mdash; April 10, 2019 \u0026mdash;**\n[SiFive](https://www.sifive.com), the leading provider of commercial\nRISC-V processor IP, today announced the launch of the S2 Core IP Series at the Linley Spring Processor Conference in Santa Clara. The S2 Core IP Series is a 64-bit addition to SiFive’s 2 Series Core IP and brings advanced features to SiFive’s smallest microcontrollers. The S2 Series further adds to SiFive’s extensive, vastly customizable, optimized, silicon-proven, embedded core IP portfolio, which comprises the 2, 3, 5, and 7 Core IP Series in E (32-bit) and S (64-bit) variants.\n\nEdge SoCs face the diverse requirements of real-time latency, deterministic capability and stringent power constraints. The S2 enables SoCs to have an always-on low power CPU that can be combined with high-performance CPUs that switch on only when applications demand performance, such as in voice-activated smart devices. The 2 Series can be configured to be as small as just 13,500 gates (in RV32E form). The S2 is just half the size of a similarly configured S5 core. Security is enhanced by separation between secure and non-secure domains. This degree of flexibility is what is needed to meet the constraints in terms of power, area and real-time demands as well as the requirements in terms of performance of modern edge workloads and applications. The S2 Series will be available as a customizable Core IP Series as well as in the form of standard cores via [SiFive’s Core Designer](https://www.sifive.com/core-designer).\n\n“SiFive’s 64-bit S Cores bring their hallmark efficiency, configurability and silicon-proven Core IP expertise to 64-bit embedded architectures,” said Ted Speers, head of product architecture and planning at Microchip Technology’s Microsemi subsidiary and RISC-V Foundation board member. “The S Cores will enable innovation for the next generation of embedded compute.”\n\nThe ever-growing number of connected devices with artificial intelligence, machine learning, IoT, and real-time workloads have generated a massive demand for greatly enhanced embedded intelligence in compute at the edge. Legacy architectures have long ignored the need for small, efficient, 64-bit, real-time embedded processors. SiFive has secured more than 25 design wins for the 2 Series Core IP alone since its launch at DAC in June 2018 and is now launching the S2 Series for power- and area-constrained, high performance 64-bit embedded applications. The S2 has no direct competitive equivalent in the market in terms of offering 64-bit capabilities or advanced features within the footprint of a SiFive 2 Series Core IP. The 64-bit capability of the S2 allows for far easier integration than 32-bit physical addressing and provides the benefit of fast and efficient access to slow or far-away memories via flexible memory maps and micro instruction caches. SiFive is the sole RISC-V Core IP provider to offer 64-bit fully coherent heterogenous compute all the way up to nine cores per cluster where high-throughput processing is needed. Existing and new features are shared across E and S variants of the 2 Series, which include enhanced debug and trace.\n\n“To achieve SiFive’s mission to democratize silicon and compute, we must rapidly enable embedded intelligence where data touches the real world,” said Yunsup Lee, CTO and co-founder, SiFive. “SiFive recognized a deep need for a full 64-bit embedded solution. We leveraged our unique methodology to rapidly innovate and architect 64-bit, fully heterogenous and coherent, real-time core capability. Our S2 Core IP Series is silicon proven and brings efficiency, performance, and security to enable greater innovation at the edge.”\n\n**About SiFive**\n\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [www.sifive.com](https://www.sifive.com).\n\n**MEDIA CONTACTS**\n\nLeslie Clavin \nSHIFT Communications for SiFive \n415-591-8440 \n[sifive\\@shiftcomm.com](mailto:sifive@shiftcomm.com)\n","spans":[]}]}},{"id":"XoKNPBEAACMApqhO","uid":"sifive-to-present-at-virtual-linley-spring-processor","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XoKNPBEAACMApqhO%22%29+%5D%5D","tags":[],"first_publication_date":"2020-03-31T13:00:04+0000","last_publication_date":"2023-05-15T17:50:50+0000","slugs":["sifive-to-present-at-virtual-linley-spring-processor-conference"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive to Present at Virtual Linley Spring Processor Conference","spans":[]}],"publish_to":"Archive","publish_date":"2020-03-31","share_image":{"link_type":"Media","kind":"image","id":"XoKLDhEAACQApp6t","url":"https://images.prismic.io/sifive/f4d2c904-4dd9-4d3f-afdd-2a965eddc667_SiFive-Linley2020SpringProcessorConferenceAnnouncement.png?auto=compress,format","name":"SiFive-Linley2020SpringProcessorConferenceAnnouncement.png","size":"623234","width":"800","height":"601"},"body":[{"type":"preformatted","text":"*The idea-to-silicon company will be hosting two sessions during the online conference, in addition to serving as a Platinum sponsor.*\n\n**SAN MATEO, Calif. Mar 31, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced it will be participating in the [Linley Spring Processor Conference](https://www.linleygroup.com/events/event.php?num=48), which will now be held virtually April 6-9, 2020. SiFive will host two virtual sessions, during which attendees will have the opportunity to learn more about the RISC-V uprising driving chip customization and how SiFive is powering the next generation of custom SoCs. The company, whose mission is to reduce the time, complexity, and cost of custom silicon for people trying to solve today’s computing challenges – otherwise known as the idea-to-silicon journey, is also a Platinum sponsor of the event.\u003cbr/\u003e\r\n\r\n“Vector processors provide untapped compute power for solving today’s modern machine learning computing challenges that can in many cases achieve the performance of domain specific chips without the associated programming complexity,” said Randy Allen, VP of RISC-V Software. “I’m looking forward to sharing our thoughts on our approach to programming high-performance, high-efficiency computing solutions.”\u003cbr/\u003e\r\n\r\nAttendees will be able to view live-streamed presentations and interact with the speakers during Q\u0026A and breakout sessions daily from 9:00am – 1:00pm Pacific Daylight Time (PDT) / 12:00 – 4:00pm Eastern Daylight Time (EDT). The virtual program features more than 20 technical presentations on processors and IP cores for AI applications, embedded, data center, automotive, IoT, and server designs. Leveraging its experience in high-quality IP and SoC design for 5G, AI, and mission-critical markets with comprehensive tools and support, SiFive’s presentations include:\u003cbr/\u003e \r\n\r\n*The Direction and Magnitude of SiFive Intelligence* \nNick Knight, Software Performance Team, SiFive\r\n- Tuesday, April 7 at 9:30am PDT\r\n- \"The key to \"achieving supercomputer performance” is to combine a vector unit with \"real\" vector registers and an intelligent restructuring compiler to focus computations into the processor. This presentation will discuss SiFive's RISC-V Vector extension and the technical tradeoffs among the three components, illustrating the resulting advantages with specific benchmark performance.\"\n\r\n*“Vectors are History”: 30 Years Later* \nRandy Allen, VP of RISC-V Software, SiFive\r\n- Thursday, April 9 at 11:40am PDT\r\n- Three decades ago, Forest Baskett accurately predicted the decline of vector computing in a paper entitled \"Vectors are History.\" The analytic approach of this paper still applies, but it leads to different conclusions today. This presentation will apply that analysis to today's computing world, leading to the conclusion of the increasing importance of vector, parallel, heterogeneous, and domain-specific computing. Today's Intelligence of Things trends require a compiling framework to enable effective programming of such complex architectures without superhuman effort.\u003cbr/\u003e\n\n“AI acceleration is quickly spreading from the cloud to the edge as the rapid adoption of AI across multiple applications and industries is driving the development of a wide variety of AI chips and IP,” said Linley Gwennap, principal analyst and conference chairperson. “This will be our biggest Linley Spring Processor Conference program yet and will showcase the newest AI and processor technologies from established suppliers as well as a host of exciting startups. We’re also looking forward to several new technology and product announcements.”\u003cbr/\u003e\n\nOnline registration for the conference closes Friday, April 3 at 5:00pm PDT. To register, please visit [https://linleygroup.com/SPC20](https://linleygroup.com/events/event.php?num=48). Registration is free for qualified attendees. Those who have already registered for the in-person event do not need to re-register for the virtual program.\u003cbr/\u003e\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is on a mission to free semiconductor roadmaps and declare silicon independence from the constraints of legacy ISAs and fragmented solutions. As the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all markets to build customized RISC-V based semiconductors. Founded by the inventors of RISC-V, SiFive has 16 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit [www.sifive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\u003c/br\u003e\n\r\n**Media Contact**\r\n\r\nHilary Livingston Castle\u003cbr/\u003e \r\nINK Communications for SiFive\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e \r\n","spans":[]}]}},{"id":"Xe_c6xEAAHgTIIYg","uid":"sifive-announces-new-technologies-for-mission-critical","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Xe_c6xEAAHgTIIYg%22%29+%5D%5D","tags":[],"first_publication_date":"2019-12-10T19:10:00+0000","last_publication_date":"2023-05-15T18:28:32+0000","slugs":["sifive-announces-new-technologies-for-mission-critical-and-ai-markets"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Announces New Technologies for Mission-Critical and AI Markets","spans":[]}],"publish_to":"Archive","publish_date":"2019-12-10","share_image":{"link_type":"Media","kind":"image","id":"Xe_avREAAGcgIH0e","url":"https://images.prismic.io/sifive/ec8bd749-0c80-43c9-9e7e-e19a1651f5ee_sifiveinnovationapexintelligence.png?auto=compress,format","name":"sifiveinnovationapexintelligence.png","size":"669343","width":"799","height":"430"},"body":[{"type":"preformatted","text":"*New SiFive Apex cores for mission-critical markets and SiFive Intelligence cores for vector processing workloads create a comprehensive IP portfolio for high-growth markets*\n\n**SAN MATEO, Calif. - Dec 10, 2019** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced two new leading-edge products: SiFive Apex for mission-critical processors and SiFive Intelligence processor cores for deep learning markets. Today during a RISC-V Summit keynote, Yunsup Lee, CTO of SiFive and co-inventor of the free and open RISC-V ISA, announced the new high-performance, efficient processor core generators, designed to create an unmatched portfolio of IP for markets that require functional correctness or the ability to process deep learning workloads. Recently, SiFive announced the world’s first RISC-V out-of-order superscalar processor core IP, [SiFive U8-Series](https://www.sifive.com/press/sifive-announces-new-u8-series-core-ip-for-high-performance), and a whole SoC solution for security, [SiFive Shield](https://www.sifive.com/press/sifive-announces-new-sifive-shield-for-modern-soc-design).\u003cbr/\u003e\n \r\n**New SiFive Apex for Mission-Critical Solutions**\u003cbr/\u003e\r\n\t\r\nThe new SiFive Apex line of products employs an innovative new approach to processor core design for mission-critical workloads, based on formally verified core generators. SiFive Apex processor cores are generated using the open-source Kami methodology while retaining the SiFive key principle of parameterized cores configured to the needs of the customer. Using Kami, an open-source high-level parametric methodology for verification, SiFive will introduce a series of clean-sheet new design processor cores based on the RISC-V ISA to address a wide range of efficiency and performance requirements. SiFive Apex technology is designed to enable Size, Weight, and Power (SWaP) optimized cores for mission-critical markets.\u003cbr/\u003e \r\n\r\nSiFive is partnering with [ResilTech S.R.L.](https://www.resiltech.com/), the leader in resilient computing and functional safety, to support SiFive and its customers to achieve safety compliance at the system or SoC level. More details about SiFive Apex will be presented at the RISC-V Summit in the San Jose Convention Center at 3:40 p.m., Tuesday, Dec. 10, in Grand Ballroom 220-B.\u003cbr/\u003e \r\n\r\n**New SiFive Intelligence for Vector Processing Workloads**\u003cbr/\u003e\r\n\r\nSiFive Intelligence technology is a series of processor core generators that enable high-performance compute workload support via vector processing. The RISC-V specification enables many extensions to permit the creation of central processing units that are both domain-specific and unified to the target workload needs. Leveraging the RISC-V Vector Extension (RVV), SiFive Intelligence processor cores enable configurable designs for markets from audio, speech or vision processing, to inference processing and machine learning. SiFive showed an average performance uplift of 9X vs traditional scalar processing on RISC-V processing, to demonstrate the benefit of SiFive Intelligence processor cores.\u003cbr/\u003e \r\n\r\nSiFive announced the new Vector Experience Evaluation Program, in which lead customers can evaluate the benefits of SiFive Intelligence processor IP with a comprehensive support package, including software libraries and compiler support.\u003cbr/\u003e \r\n\r\nMore details about SiFive Intelligence will be presented at the RISC-V Summit in San Jose Convention Center at 1:20 p.m. on Wednesday, Dec. 11, in Grand Ballroom 220-B.\u003cbr/\u003e \r\n\r\n“SiFive has had a tremendous year in 2019, and the introduction of SiFive Apex and SiFive Intelligence is the crowning achievement,” said Dr. Naveed Sherwani, president and CEO of SiFive. “SiFive’s broad suite of foundational technologies positions us well for continued growth and success next year as adoption of RISC-V advances.”\u003c/br\u003e\r\n\r\nSaid Lee: “The announcement of SiFive Apex and SiFive Intelligence is a tipping point for SiFive. SiFive Apex’s innovation in functional correctness permits the creation of differentiated roadmaps without legacy cruft. SiFive Intelligence creates a new level of configurable, scalable CPU that is sorely needed for enabling machine learning and inference processors in AI markets.”\u003c/br\u003e\r\n\r\nSiFive is a Ruby sponsor of the RISC-V Summit 2019, and is participating in more than a dozen presentations over the three days of the public conference. Attendees can visit the SiFive booth to discover more about the latest IP, products, partnerships, and a chance to meet with the inventors of RISC-V.\u003c/br\u003e \r\n\r\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [www.sifive.com](htttps://www.sifive.com).\u003cbr/\u003e\r\nStay current with the latest SiFive updates via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\u003cbr/\u003e\r\n\n**Media Contact**\u003c/br\u003e\r\n \r\nLeslie Clavin\u003cbr/\u003e\r\nSHIFT Communications for SiFive\u003cbr/\u003e\r\n(415) 591-8440\u003cbr/\u003e\r\nsifive@shiftcomm.com\u003cbr/\u003e\r\n","spans":[]}]}},{"id":"XY39bRAAACgA0RVL","uid":"sifive-enables-embedded-vision-with-new-designshare","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XY39bRAAACgA0RVL%22%29+%5D%5D","tags":[],"first_publication_date":"2019-09-30T13:00:02+0000","last_publication_date":"2023-05-15T18:19:38+0000","slugs":["sifive-enables-embedded-vision-with-new-designshare-partners"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Enables Embedded Vision With New DesignShare Partners","spans":[]}],"publish_to":"Archive","publish_date":"2019-09-30","share_image":{"link_type":"Media","kind":"image","id":"XUx5jxcAAGNxEFjs","url":"https://images.prismic.io/sifive%2F44821da7-9e96-4765-bde9-fa154926ae8e_ai+camera.png?auto=compress,format","name":"AI Camera.png","size":"68678","width":"1280","height":"1409"},"body":[{"type":"preformatted","text":"*New Partnerships Add Key IP For Efficient Embedded Vision SoC Designs*\n\n**SAN MATEO, Calif. – September 30th, 2019** – [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, announced today new partners for SiFive’s uniquely collaborative DesignShare IP ecosystem program, enabling the AI and Embedded Vision market. With rising costs on advanced process technology nodes, modern SoC design must include essential IP focused on the target market, designed in an efficient way. The SiFive DesignShare IP program offers a streamlined process, partnering with leading vendors to provide key IP for bringing new SoCs to market. \r\n\r\nEmbedded Vision is a leading market for the use of deep learning inference models, processing video and images in IoT Edge solutions where network and latency limitations make processing at the Edge more desirable than in the Datacenter. Applications of Embedded Vision with AI processing are surveillance cameras, augmented and/or virtual reality, industrial monitoring and inspection, and commercial or consumer drones and robotics. \r\n\r\nThe Embedded Vision market is expected to grow to reach $6Bn by 2023, and is expected to require design platforms on leading FinFET nodes featuring scalable SoC designs, created in partnership with leading IP providers for image signal processing, high-speed connectivity, and efficient process technology libraries. \r\n\r\nThe latest additions to the SiFive DesignShare IP family are: \r\n\r\n## Chips\u0026Media\r\n\r\nChips\u0026Media, a leading video IP company headquartered in Seoul, Korea, offers an extensive catalog of leading-edge image signal processing IP that is now available through SiFive DesignShare. Image signal processing IP is key to collating and feeding information into deep learning inference processing models used in Embedded Vision devices to make application-specific decisions, or prepare data for further processing in Datacenters. \r\n\r\n“We are pleased to be a part of the SiFive DesignShare IP program,” said Steve SangHyun Kim, CEO, Chips\u0026Media, Inc. “The combination of Chips\u0026Media’s leading-edge image signal processing portfolio with SiFive’s comprehensive SoC IP and RISC-V Core IP is perfectly suited to new Embedded Vision designs.” \r\n\n## Dolphin Technology\n\r\nDolphin Technology is focused on providing quality, high performance, and low power, Semiconductor IP (SIP) to maximize the efficiency of hardware design teams. Dolphin Technology enables optimized embedded memory architectures, standard and specialty memory compilers with selectable PPA optimization points, and comprehensive design-for-test modes. By supporting both leading and the most common process nodes, Dolphin Technology provides SoC designers with a broad array of silicon-proven IP. \r\n\r\n“Dolphin has been enhancing quality and reducing time to market for many years,” said Mo Tamjidi, CEO, Dolphin Technology. “Joining the SiFive DesignShare program broadens our reach and helps enable the next generation of efficient, advanced AI SoCs in a scalable and simple way.”\r\n\r\n## M31 Technology Corporation\n\r\nM31, based in Hsinchu, Taiwan, is a leading Silicon IP (SIP) provider focusing on high-speed interface IP, memory compilers, and standard cell library solutions. Many of M31’s portfolio of IPs are targeted to advanced process technologies, making inclusion of M31 high-speed interface IP a natural fit for the SiFive DesignShare IP program, and well suited to enabling Embedded Vision products. \r\n\r\nM31’s high-speed interface IP includes USB 1.1 to USB 3.2 PHY, with Type-C support. Besides, M31 provides M-PHY/D-PHY/C-PHY, and C/D-PHY Combo RX/TX IP; and PCIe/SATA PHY for high bandwidth interconnect devices that require high-performance and low-power consumption.\n\r\n“The M31 Technology Corporation vision is to enable short design cycles, low manufacturing cost, and highly competitive products.” Said H.P. Lin, Chairman of M31 Technology Corp. “The adoption of M31 high-speed interface IP through SiFive DesignShare will help companies competing in the Embedded Vision market grasp opportunities and rapidly go to market with a differentiated IP solution.” \r\n\nFor more details, please visit [SiFive DesignShare](https://www.sifive.com/designshare)\n\r\n“SiFive’s silicon IP, design methodology, and RISC-V Core IP are well-positioned to lead in the growth of the Embedded Vision market.” Said Dr. Naveed Sherwani, President \u0026 CEO, SiFive, Inc. “We continue to offer our customers a configurable, scalable, portfolio of IP including key technologies from leading partners in our DesignShare program. The partnerships with Chips\u0026Media, Dolphin Technology, and M31 Technology Corp., offer innovative IP solutions for IoT, Edge, and AI designs and will help fuel SiFive’s ongoing hypergrowth.” \r\n\r\n## About SiFive\r\n\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit www.sifive.com.\r\n\r\n## MEDIA CONTACTS\r\n\r\nSara Dodrill \nSHIFT Communications for SiFive \n415-591-8429 \nsdodrill@shiftcomm.com ","spans":[]}]}},{"id":"Xm_yoxEAAB8Afuez","uid":"sifive-launches-advanced-trace-and-debug-portfolio","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Xm_yoxEAAB8Afuez%22%29+%5D%5D","tags":[],"first_publication_date":"2020-03-17T11:00:14+0000","last_publication_date":"2023-05-15T18:30:00+0000","slugs":["sifive-launches-advanced-trace-and-debug-portfolio-sifive-insight"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Launches Advanced Trace and Debug Portfolio, SiFive Insight","spans":[]}],"publish_to":"Archive","publish_date":"2020-03-17","share_image":{"link_type":"Media","kind":"image","id":"Xm_fnBEAACEAfpNo","url":"https://images.prismic.io/sifive/9f27cb1b-cecb-4a3d-ae85-0a1e701bd911_sifive-insight-aoc.png?auto=compress,format","name":"sifive-insight-aoc.png","size":"5948142","width":"2989","height":"1478"},"body":[{"type":"preformatted","text":"*The portfolio enables users to access, observe, and control processor development in real-time, accelerating silicon time-to-market*\n\n**SAN MATEO, Calif., Mar. 17, 2020** – [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced SiFive Insight, a technology portfolio that enables faster silicon bring-up, software/hardware integration, and application development through hardware trace and debug. SiFive Insight is the industry’s first combined trace and debug solution for the freely-available, open-specification RISC-V ISA.\u003cbr/\u003e\n\n**Access, Observe, and Control**\u003cbr/\u003e\r\nSiFive Insight combines trace and debug capabilities to offer a comprehensive portfolio that enables faster and easier product development. SiFive has invested heavily in SiFive Insight’s trace capabilities to meet customer demand and expectations for the capability to access, observe, and control products deploying SiFive’s RISC-V Core IP portfolio.\u003cbr/\u003e \r\n\r\nSiFive Insight includes many open-source contributions to develop the growing ecosystem of RISC-V developers, including a C++ cross-platform Nexus 5001™ trace decoder for RISC-V. The Nexus 5001™ trace specification is an open, well-documented standard that includes an extensive portfolio of processor trace and trace related features. The SiFive Insight trace implementation is compliant with the proposed RISC-V Nexus Trace Working Group specification, currently under consideration.\u003cbr/\u003e \r\n\r\nSiFive Insight is available for all SiFive RISC-V Core IP product lines offered by SiFive Core Designer, the award-winning(1) cloud-based tool to define and customize RISC-V processor cores.\u003cbr/\u003e\r\n\r\n**Industry Support**\u003cbr/\u003e\r\nPopular toolsets from the leading application and embedded processor software development companies also support SiFive Insight, simplifying the adoption of SiFive processor IP and RISC-V application development.\u003cbr/\u003e \r\n\r\n”The fast-paced growth of the RISC-V ecosystem requires robust tools and solutions to speed up new product development,” says Anders Holmberg, Chief Strategy Officer, IAR Systems. “IAR Systems leading software tools support the comprehensive trace and debug solution SiFive Insight, enabling boosted application performance and shortened time to market for companies choosing RISC-V for their next innovation.”\u003cbr/\u003e\r\n\r\n\"Lauterbach sees RISC-V as an important contributor to the expanding domain of Smart Devices,\" said Stephan Lauterbach, CTO of Lauterbach Development Tools. \"Our TRACE32 debug and trace tools fully support SiFive Insight, providing developers with world-leading tools that seamlessly integrate into the rapidly-growing RISC-V ecosystem.\"\u003cbr/\u003e\r\n\n“All of our products are fully compatible with SiFive’s RISC-V cores,” says Rolf Segger, founder of SEGGER. “With SiFive Insight, SiFive now offers valuable additional debug and trace capabilities. At SEGGER, we are making sure these great new features can be fully leveraged using our industry-leading J-Link debug probe and Ozone debugger.“\u003cbr/\u003e\r\n\r\n**Market Focus**\u003cbr/\u003e\r\nWith RISC-V adoption increasing in many markets such as automotive, networking, enterprise, mission-critical, and IoT, the ability to swiftly create reliable systems is critical. SiFive’s use of open ISA’s, software and standards ensure quality through trust-but-verify processes.\u003cbr/\u003e\r\n\r\n“Our mission is to enable higher-quality products with fast time to market, especially in the fast-growing Intelligence of Things and TinyML markets,” said Dr. Naveed Sherwani, President, and CEO of SiFive. “SiFive Insight enables our customers to continue to develop RISC-V based applications without changing workflows, and new designers to simply and easily adopt the exciting new technology. This will drive the rapid creation of new domain-specific accelerators and embedded devices with on-device decision-making capabilities.”\u003cbr/\u003e\r\n\r\nFor more information on SiFive Insight, please visit [SiFive.com/SiFive-Insight](https://www.sifive.com/soc-ip/sifive-insight) and read the [SiFive Insight launch blog.](https://www.sifive.com/blog/introducing-sifive-insight)\u003cbr/\u003e \r\n\r\n**About SiFive**\u003cbr/\u003e\r\nSiFive is on a mission to free semiconductor roadmaps and declare silicon independence from the constraints of legacy ISAs and fragmented solutions. As the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all markets to build customized RISC-V based semiconductors. Founded by the inventors of RISC-V, SiFive has 16 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit [www.sifive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\u003c/br\u003e\n\n(1) – SiFive Core Designer won Design Tool and Development Software category at the [Elektra Awards, 2019.](https://www.elektraawards.co.uk/elektraawards2019/en/page/2019-winners)\r\n\r\nMedia Contact\r\n\r\nHilary Livingston Castle\u003cbr/\u003e \r\nINK Communications for SiFive\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e \r\n","spans":[]}]}},{"id":"XhOS_BMAACEAhK5H","uid":"sifive-to-attend-ces-2020","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XhOS_BMAACEAhK5H%22%29+%5D%5D","tags":[],"first_publication_date":"2020-01-06T21:43:39+0000","last_publication_date":"2023-05-15T18:34:28+0000","slugs":["sifive-to-attend-ces-2020","sifive-announces-new-u8-series-core-ip-for-high-performance-compute"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive to Attend CES 2020","spans":[]}],"publish_to":"Archive","publish_date":"2019-12-30","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*SiFive to deepen AI portfolio with strategic new disclosures at CES 2020, unleashing semiconductor product roadmaps for consumer and commercial SoCs*\n\nSAN MATEO, Calif.--(BUSINESS WIRE)--SiFive, Inc., the leading provider of commercial RISC-V chips, today announced its first-ever participation in the premier technology event, [CES 2020](https://www.ces.tech/), held January 7 – 10. Seven executives will be present over the multi-day event held at the Las Vegas Convention Center. The company will be making a strategic announcement on January 6th at 6am ET to demonstrate its leadership in IP licensing for AI solutions. \r\n\nAs the leading provider of commercial RISC-V chips, SiFive enables high-quality IP and SoC design with comprehensive tools and support. Engineers at leading semiconductor companies worldwide have declared silicon independence and unleash product roadmaps by designing custom cores and SoCs that maximize the potential of domain-specific designs needed for 5G, AI, and mission-critical markets. With RISC-V, a free, open-source alternative to proprietary, legacy ISAs, these emerging markets now have low-power, high-performance designs for products to power continued market growth. CES attendees will have the opportunity to learn more about the RISC-V uprising that is driving chip customization and how SiFive is powering the next generation of custom SoCs and shipping millions of cores worldwide.\r\n\r\n- **CES Unveiled** – On Sunday, January 5th from 5 – 8:30pm PT, SiFive will be at table #223 at the Shorelines Exhibit Hall at Mandalay Bay.\r\n- **Pepcom Digital Experience!** – On Monday, January 6th from 7 – 10:30pm PT, SiFive will be exhibiting at the Mirage Hotel.\n\r\n\"We are thrilled to take part in the biggest consumer technology event of the year. It’s an honor to be part of the global stage for innovation, surrounded by the industry’s top change-makers in breakthrough technology,” said Dr. Naveed Sherwani, president and CEO of SiFive. \"We’re looking forward to sharing the latest integrations to the SiFive ecosystem and pushing the boundaries for what is possible with our domain-specific IP and silicon.\"\n\nVisit the SiFive table at CES Unveiled and the Pepcom Digital Experience! to learn more about how the company is delivering the scalability, rapid enablement, and reliability necessary to power the next generation of IoT. Media are encouraged to schedule briefings with SiFive at LVCC South Hall MP25372 by contacting INK Communications at [sifive@ink-co.com](mailto:sifive@ink-co.com). \r\n\r\n**About SiFive**\u003cbr\u003e\nSiFive is on a mission to free semiconductor roadmaps and declare silicon independence from the constraints of legacy ISAs and fragmented solutions. As the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all markets to build customized RISC-V based semiconductors. Founded by the inventors of RISC-V, SiFive has 16 design centers worldwide, and has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit, [www.sifive.com](https://www.sifive.com).\r\n\nStay current with the latest SiFive updates via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\n\r\n**MEDIA CONTACTS**\u003cbr\u003e\nHilary Livingston Castle\u003cbr\u003e\nINK Communications for SiFive\u003cbr\u003e \n203-858-7259\u003cbr\u003e \nsifive@ink-co.com\n","spans":[]}]}},{"id":"XzaITxAAACEAPWUi","uid":"sifive-and-innovium-announce-collaboration-to-accelerate","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XzaITxAAACEAPWUi%22%29+%5D%5D","tags":[],"first_publication_date":"2020-08-18T13:00:05+0000","last_publication_date":"2023-05-15T18:23:27+0000","slugs":["sifive-and-innovium-announce-collaboration-to-accelerate-innovation-in-data-center-networking"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and Innovium Announce Collaboration to Accelerate Innovation in Data Center Networking","spans":[]}],"publish_to":"Archive","publish_date":"2020-08-18","share_image":{"link_type":"Media","kind":"image","id":"XzaG-BAAACEAPV75","url":"https://images.prismic.io/sifive/2f2d8066-4282-479d-acd7-519119c38576_sifive-innovium-promo.png?auto=compress,format","name":"sifive-innovium-promo.png","size":"82311","width":"1024","height":"575"},"body":[{"type":"preformatted","text":"*Innovium TERALYNX® products integrate SiFive RISC-V processor cores to increase lead in breakthrough switch silicon for Cloud and Edge data center networks*\n\n**SAN MATEO, Calif. Aug 18, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, and Innovium, Inc., a leading provider of networking switch solutions for cloud and edge data centers, today announced a collaboration to drive faster innovation in switch silicon solutions. These new designs incorporate SiFive E2-Series processor cores to extend Innovium’s leadership position in programmable switch silicon for Cloud and Edge data centers.\u003cbr/\u003e\n\nInnovium’s TERALYNX offers customers a highly differentiated and comprehensive programmable switch silicon portfolio, from 1 to 25.6Tbps performance and an architecture scaling to 51.2Tbps+, with consistent features and software. It delivers customers superior telemetry, robust quality, and unmatched features \u0026 power efficiency. TERALYNX has been deployed at scale by a number of the world’s leading cloud customers across all network tiers to meet their growing demands from remote work, 5G, Cloud-native, and AI applications. This has resulted in TERALYNX becoming the only credible silicon diversity option in the market with over 20% market share for 50G SerDes switch silicon.\u003cbr/\u003e\r\n\r\n“As Innovium’s highly successful TERALYNX switches ramp in Cloud and Edge data centers, we continue to invest in an industry-leading roadmap for next-generation networks,” said Rajiv Khemani, CEO of Innovium, Inc. “We are pleased to use SiFive’s processor IP in our products for additional flexible and programmable capabilities in the areas of management and configuration.”\u003cbr/\u003e\r\n\r\n“SiFive’s winning processor portfolio is well suited to new designs for datacenter infrastructure thanks to the highly-efficient, silicon-proven, configurable cores we offer,” said Dr. Naveed Sherwani, Chairman, President \u0026 CEO of SiFive. “The data center market is searching for efficient and scalable networking solutions that, through collaborating with Innovium, we can help provide.”\u003cbr/\u003e\r\n \r\n**About Innovium**\u003cbr/\u003e\r\nInnovium is a leading provider of high performance, innovative switching silicon solutions for Cloud and Edge data centers. Innovium TERALYNX family delivers software compatible products ranging from 1Tbps to 25.6Tbps with unmatched telemetry, low latency, programmability, and large buffers, and a feature rich architecture that scales to 51.2Tbps+. Innovium’s products have been selected and validated by market-leading switch OEM, ODM and cloud providers. The company is headquartered in Silicon Valley, California and is backed by leading venture capital firms including Greylock, WRVI, Capricorn, Premji Invest, Qualcomm, Xilinx, Blackrock and others. For more information, please visit: [www.innovium.com](https://www.marvell.com/products/switching/datacenter.html) and follow us on [Twitter](https://twitter.com/InnoviumInc) and [LinkedIn](https://www.linkedin.com/company/innovium-inc./).\u003cbr/\u003e\r\n\r\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\n\n**Innovium**\u003cbr/\u003e\r\nAmit Sanyal\u003cbr/\u003e\nasanyal@innovium.com \u003cbr/\u003e\n\r\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrs","uid":"sifive-unveils-the-first-risc-v-based-arduino-board-at-maker-faire-bay-area","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrs%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2023-05-15T14:28:46+0000","slugs":["sifive-unveils-the-first-risc-v-based-arduino-board-at-maker-faire-bay-area"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Unveils the first RISC-V-based Arduino Board at Maker Faire Bay Area","spans":[]}],"publish_to":"Archive","publish_date":"2017-05-19","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN FRANCISCO – May 19, 2017\u003c/span\u003e – [SiFive](https://www.sifive.com), the first fabless provider of customized, open-source-enabled RISC-V semiconductors, today announced the release of the Arduino Cinque, the first RISC-V-based development board for the popular open-source hardware platform. Today’s announcement marks the latest development in SiFive’s work to democratize access to custom silicon.\n\nThe Arduino Cinque features SiFive’s Freedom E310, the industry’s first commercially available RISC-V SoC. Running at 320MHz, the FE310 is one of the fastest microcontrollers available in the market. Along with the FE310, the Arduino Cinque also features support for 2.4 GHz Wi-Fi and Bluetooth via the inclusion of an ESP32 chip from Espressif, making this among the most advanced Arduino boards available today.\n\n“The availability of the Arduino Cinque provides the many dreamers, tinkerers, professional makers and aspiring entrepreneurs access to state-of-the-art silicon on one of the world’s most popular development architectures,” said Dale Dougherty, founder and executive chairman of Maker Media. “Using an open-source chip built on top of RISC-V is the natural evolution of open-source hardware, and the Arduino Cinque has the ability to put powerful SiFive silicon into the hands of makers around the world.”\n\nSaid Jack Kang, vice president of product and business development at SiFive: “By partnering with a pioneer in open-source hardware, SiFive can further advance the progress of open custom silicon among makers, system designers and everyone else in between. We continue to be blown away by the support and attention the open-source silicon movement has gained in the past year alone. We look forward to seeing the community’s reaction to the Arduino Cinque board, and believe that the Arduino concepts of openness and distribution mean that more people than ever will be exposed to RISC-V.”\n\n## SiFive at Maker Faire Bay Area\n\nToday’s announcement comes on the eve of a panel moderated by SiFive titled, “Manufacturing Your Own Chips: Is Open Source (like RISC-V) Making it Easier?” which is scheduled for Saturday, May 20, 2017, at the Maker Pro stage at Maker Faire Bay Area 2017, held at the San Mateo Event Center in San Mateo, Calif., May 19-21. The panel, which features American computer pioneer David Patterson and other prominent members of the open source community, will discuss the free and open RISC-V architecture (past, present and future) and the general future of chips and how RISC-V plays into that vision.\n\nIn addition, the first prototypes of Arduino Cinque will be on display at Maker Faire at the Arduino booth. For more information on this panel and its presenters, please visit: \u003chttp://makerfaire.com/maker/entry/60546/\u003e\n\n## Additional Information\n\nSiFive website: \u003chttps://www.sifive.com\u003e\u003cbr\u003e\nTwitter: \u003chttps://twitter.com/SiFive\u003e\u003cbr\u003e\nLinkedIn: \u003chttp://linkedin.com/company/sifive\u003e\u003cbr\u003e\nFacebook: \u003chttps://www.facebook.com/SiFive/\u003e\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Krste Asanovic, Yunsup Lee and Andrew Waterman, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit [www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@sifive.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"XZz2vhAAAB4ATwLi","uid":"sifive-to-host-risc-v-tech-symposium-and-workshop-in","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XZz2vhAAAB4ATwLi%22%29+%5D%5D","tags":[],"first_publication_date":"2019-10-08T21:41:25+0000","last_publication_date":"2023-05-15T15:06:44+0000","slugs":["sifive-to-host-risc-v-tech-symposium-and-workshop-in-cairo-on-october-12-2019"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive to Host RISC-V Tech Symposium and Workshop in Cairo on October 12, 2019","spans":[]}],"publish_to":"Archive","publish_date":"2019-10-06","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"_Mentor Graphics, a Siemens business; EITESAL NGO; the American University in Cairo. and Efabless are co hosting the RISC-V symposium \u0026amp; workshop_\n\n\r\nCAIRO, EGYPT, October 6, 2019 /[EINPresswire.com](http://www.einpresswire.com)/ -- WHAT:\r\nThe [RISC-V Tech Symposium](https://drive.google.com/file/d/1D62VMIYdyb-WjRwS1gOLA-cFWAIAHf9q/view) and Workshop is intended to be highly educational and serve as an all-inclusive venue to foster and grow the RISC-V ecosystem. Attendees will learn about SiFive custom cores and design platforms, and the SaaS-based approach that is enabling fast and easy access to them. Attendees will also have a unique hands-on opportunity to configure their own custom core and bring up on FPGA.\r\n\r\nIn combination with co-hosts and ecosystem partners, SiFive has been actively promoting the RISC-V ISA throughout the world via its SiFive Tech Symposiums and coordinating RISC-V workshops. In all, there will be over 50 events that will have taken place in 2019 alone. The RISC-V Tech Symposium Workshop in Cairo, Egypt is a unique event in that its magnitude and participants represent the prominence and growth of the RISC-V ecosystem throughout the region.\r\nWHO:\r\nThe RISC-V Tech Symposium and Workshop will feature keynote presentations by Hazem El Tahawy, managing director of the Middle East and North Africa Region for Mentor Graphics, and Mohamed Shedeed, managing director of EITESAL. Shafy Eltoukhy, senior vice president of operations and general manager of the Silicon Business Unit at SiFive will also deliver a keynote presentation. In addition, Mohamed Shalan, associate professor in the CSCE Department at The American University in Cairo and Mohamed Kassem, Co-Founder \u0026amp; CTO of eFabless.com will be featured presenters.\r\n\r\nWHERE \u0026amp; WHEN:\r\nMoataz Al-Alfi Hall\r\nThe AUC - New Campus (5th Settlement)\r\nNew Cairo,\r\n\r\nReception \u0026amp; networking starts 9am\r\nPresentations and Workshop: 9:20 a.m. – 17:00 p.m.\r\nLunch will be provided.\r\n[Event Agenda](https://drive.google.com/file/d/1ndJJYZ4SDwMGSnGia06j0eCGMGpZo9ur/view?usp=sharing)\r\n\r\nPlease register now at: [Registration](https://docs.google.com/forms/d/e/1FAIpQLSfktrLxdXT0fQcCBuqYVG7agFp71QJT9oh1pmf4wohm58rZUw/viewform?usp=pp_url)\r\nAttendance is free, but seating is limited.\r\n\r\nAbout Mentor Graphics, a Siemen\u0026#39;s Business\r\nMentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world\u0026#39;s most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Web site: [http://www.mentor.com](http://www.mentor.com).\r\n\r\nAbout EITESAL\r\nEITESAL is a private NGO of ICTE companies, Multi-national corporations, Organizations and Institutions operating in Egypt. EITESAL is working under the Egyptian Civil Organizations law 84/2002.\r\n\r\nAbout The American University in Cairo\r\nThe American University in Cairo (AUC) was founded in 1919 and is major contributor to the social, political and cultural life of the Arab Region. It is a vital bridge between East and West, linking Egypt and the region to the world through scholarly research, partnerships with academic and research institutions, and study abroad programs. An independent, nonprofit, apolitical, non-sectarian and equal opportunity institution, AUC is fully accredited in Egypt and the United States.\r\n\r\nAbout SiFive\r\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 14 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [www.sifive.com](https://www.sifive.com).\r\n\r\nAbout Efabless Corporation\r\nEfabless.com is the world\u0026#39;s first crowdsourcing platform for semiconductors. Through Efabless\u0026#39; platform customers connect with a global community of design firms and professionals to deliver mixed signal IC design solutions. Efabless provides its IC design community with an online platform offering everything needed to deliver a complete solution. This includes design flows, a marketplace and a repository of IP and SoC reference designs as well as access to foundry processes and MPW services to get to prototypes. The entire offering is designed to eliminate the cost and administrative barriers that have traditionally inhibited IC designers from realizing new solutions.","spans":[]}]}},{"id":"XAa2MREAAC4AoahZ","uid":"sifive-announces-multiple-technical-advances-at-risc-v","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XAa2MREAAC4AoahZ%22%29+%5D%5D","tags":[],"first_publication_date":"2018-12-04T17:37:24+0000","last_publication_date":"2023-05-15T14:57:13+0000","slugs":["sifive-announces-multiple-technical-advances-at-risc-v-summit"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Announces Multiple Technical Advances at RISC-V Summit","spans":[]}],"publish_to":"Archive","publish_date":"2018-12-04","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*SiFive leads RISC-V ecosystem at inaugural summit with range of cores,\nRISC-V silicon, proof points, demonstrations, partnerships, talks and\npanels*\n\n**SANTA CLARA, Calif. — Dec. 4, 2018 —**\n[SiFive](https://www.sifive.com), the leading provider of commercial\nRISC-V processor IP, today announced a series of technical advancements\nduring the inaugural RISC-V Summit. The leading provider of commercial\nsilicon based on the open source RISC-V instruction set architecture,\nSiFive, demonstrated the strength of its product offerings via a number\nof product demos, keynote talks and panel participation.\n\nSiFive recently secured significant double-digit design wins across its\nCore IP 2, 3, 5, and 7 Series. Of those, more than 10 design wins were\nfor their highly successful E2 Core IP Series, it was revealed at the\ninaugural RISC-V Summit in Santa Clara. The design wins represent the\nrapidly growing adoption of SiFive's RISC-V based IP in a wide array of\nuse cases by some of the industry's largest brands. Some customers with\ncomplex implementations chose to bundle E2 Core IP with higher\nperformance E3, E5, and E7 Core IP Series. These in-cluster combinations\ndemonstrate the completeness of SiFive's Core IP, particularly in\nconstrained designs where architectural customization and optimization\nstand to offer substantial real-world performance advantages. SiFive\nwill be announcing further details in the coming weeks.\n\nKrste Asanovic, co-founder and chief architect at SiFive as well as an\ninventor of the RISC-V ISA and chairman of the RISC-V Foundation, will\npresent the \"RISC-V State of the Union\" today to kick off the Summit.\nDuring the session, Asanovic commented on the progress the ecosystem has\nmade in the past four years.\n\nOther Summit presentations by SiFive include:\n\n- Embedded Intelligence Everywhere by Jack Kang, Tuesday, 1:10 p.m. to\n 1:30 p.m.\n\n- NVIDIA\\'s Deep Learning Accelerator meets SiFive\\'s Freedom Platform\n by Yunsup Lee and Frans Sijstermans, NVIDIA, Tuesday, 1:35 p.m. to\n 1:55 p.m.\n\n- SiFive Freedom Revolution: Customizable RISC-V AI Platform with HBM2\n and 56-112Gb/s SerDes by Krste Asanovic, Tuesday, 2 p.m. to 2:20\n p.m.\n\n- Opportunities and Challenges of Building Silicon in the Cloud by\n Yunsup Lee, Wednesday, 9 a.m. to 9:20 a.m.\n\n- SiFive TERP: A Trusted Execution Reference Platform for Embedded\n Secure Applications by Palmer Dabbelt and Nathaniel Graff,\n Wednesday, 2:40 p.m. to 3 p.m.\n\n## Expansive Array of Demos\n\nSiFive also will feature a wide array of chips and devices based on its\ncore IP at its Booth, No. 202.\n\nMicrosemi will demonstrate an object detection algorithm running on\ntheir current expansion board. Announced at the RISC-V Summit,\nMicrochip's new PolarFire SoC FPGA architecture, in collaboration with\nSiFive, brings real-time deterministic asymmetric multiprocessing\ncapability to Linux platforms in a multi-core, coherent CPU cluster. The\nPolarFire SoC FPGA architecture includes SiFive's U54-MC and features a\nflexible 2 MB L2 memory subsystem that can be configured as a cache,\nscratchpad or a direct access memory. This allows designers to implement\ndeterministic real-time embedded applications simultaneously with a rich\noperating system for a variety of thermal and space constrained\napplications in collaborative, networked IoT systems, all in a single,\ncoherent central processing unit (CPU) complex.\n\nRambus and SiFive will showcase SiFive's FU540 processor integrated with\nthe Rambus CryptoManager Root of Trust (CMRT). The Rambus CMRT soft IP\ncore is delivered as Verilog RTL for inclusion in any chip or FPGA\ndesign. Features include a security-optimized multi-stage 32-bit RISC-V\nRV32I based processor, self-contained secure boot, memory protection\nunit locked at boot time, private SRAM and CPU bus isolated from secure\nkey bus. The CMRT uses a layered security model for software, using the\nhardware enforced privilege levels of the RISC-V ISA for separation of\ndata between layers (user, supervisor, machine).\n\nSiFive will display FADU's Annapurna SSD controller featuring SiFive\\'s\nindustry-leading 64-bit, E51 multicore RISC-V Core IP. The FADU\nAnnapurna SSD controller is the world\\'s first RISC-V based SSD\ncontroller and provides the highest throughput (3.5GB) and IOPS (800K)\namong its peers, while consuming less than 1.8W active power. Powered by\nFADU Annapurna, the FADU Bravo SSD is the first 7mm low-power U.2\nsupporting dual port and offers 3-4X IOPS / watt greater efficiency, 30\npercent lower power and the most consistent latency QoS in its class.\nDespite consuming only 6W to 8W of active power, FADU Bravo easily\noutperforms competing solutions at 25W, due to its innovative design,\nadvanced flash memory controller and use of SiFive\\'s high-performance\n64-bit embedded RISC-V Core IP.\n\nSiFive also will display a silicon development board by Upbeat. The\nwearable chip is based on SiFive's E31 Core IP and is optimized for\nlow-power, wearable applications and features a built-in AI inference\nand graphics accelerator engines.\n\nEideticom will be demonstrating their NoLoad™ NVM Express Computational\nStorage Accelerator.\n\nSiFive will demonstrate Debian Linux running on SiFive's HiFive\nUnleashed board and Microsemi's expansion board (over 94 percent of\nDebian packages have been ported to RISC-V).\n\nAdditionally, SiFive will demonstrate a flexible AI application\nconstructed with a standard Linux-capable design. The YOLO (You Only\nLook Once) image recognition application was constructed with the\nopen-source NVDLA framework, demonstrating the flexibility of the\nhardware and software stack. The demo consists of the NVDLA accelerator\nrunning on an FPGA connected via ChipLink to SiFive's HiFive Unleashed\nboard powered by the Freedom U540, the world's first Linux-capable\nRISC-V processor. The complete SiFive implementation is well-suited for\nintelligence at the edge, where high performance with improved power,\nperformance and area profiles are crucial. SiFive's silicon design\ncapabilities allow a simplified path to building custom silicon on the\nRISC-V architecture with NVDLA.\n\nMany other demos will use SiFive's development boards, including Western\nDigital's NAS demonstration of their state-of-the-art SMR (Shingled\nMagnetic Recording) hard disk connected to a HiFive Unleashed board and\nMicrosemi expansion board.\n\nOnChip will highlight an SoC prototype that integrates a 32-bit E31\nRISC-V IMAC based core featuring a low-energy, always on (AON) subsystem\nwith peripherals for low-duty-cycle sensor node applications.\n\nThe Keystone research project, currently led by research groups at UC\nBerkeley, including Asanovic, and CSAIL at MIT will demonstrate an open\nsource secure hardware enclave. This allows the building of trusted\nexecution environments (TEE) with secure hardware enclaves, based on the\nRISC-V architecture.\n\n## Robust Tools Available\n\nThe RISC-V technology and ecosystem are evolving rapidly. With the rapid\ngrowth, the need for professional development tools is increasing.\nSiFive is working closely with the leading tool providers to improve\nRISC-V support by commercial providers of compilers, debuggers, IDEs,\ntrace units and development platforms. Alongside SiFive's own Freedom\nSDK, a fuller development stack and toolchain is rapidly making its way\nto market.\n\nIAR Systems and SiFive have collaborated to bring IAR Systems' leading\ncompiler and debugger technology to users of SiFive's high-performance\nand highly configurable core IP. By tightly integrating IAR's\nindustry-leading compiler and debug tools with SiFive's industry-leading\nRISC-V Core IP, the companies will provide developers with powerful,\neasy-to-use, complete solutions enabling users to get started quickly.\n\nIAR, Segger, Lauterbach, Ashling and Green Hills Software tools all\nsupport SiFive RISC-V Core IP and will be demonstrated at SiFive's\nbooth.\n\n## Partner Ecosystem Momentum\n\nWith the recent signing of PLDA's extensive suite of PCIe controllers,\nSiFive DesignShare program has grown to 17 partners and includes: Analog\nBits, ASIC Design Services, Brite Semiconductor, Chipus, Chips \u0026 Media,\nDover, eMemory, FlexLogix, Mobiveil, OpenEdges, PLDA, Rambus, Terminus\nCircuits, Think Silicon, UltraSoC and Wasiela. The range of IP on offer\nvia the unique IP sharing program now ranges from analog and mixed\nsignal IP to ultra-low power and security IP, broadly covering IP needs\nfor SoC designers. The IP selection on offer is particularly well\nintegrated for IoT, edge, networking and storage, AI/ML, wearables and\nintelligent embedded applications.\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP,\ndevelopment tools and silicon solutions based on the free and open\nRISC-V instruction set architecture. Led by a team of seasoned silicon\nexecutives and the RISC-V inventors, SiFive helps SoC designers reduce\ntime-to-market and realize cost savings with customized,\nopen-architecture processor cores, and democratizes access to optimized\nsilicon by enabling system designers in all market verticals to build\ncustomized RISC-V based semiconductors. Located in Silicon Valley,\nSiFive has backing from Sutter Hill Ventures, Spark Capital, Osage\nUniversity Partners, Chengwei, Huami, SK Hynix, Intel Capital, and\nWestern Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\nJamie Feller\n\nSHIFT Communications for SiFive\n\n415-591-8432\n\n[sifive@shiftcomm.com](mailto:sifive@shiftcomm.com)","spans":[]}]}},{"id":"XdLUcBAAACUAPnsI","uid":"architek-select-sifive-and-dts-insight-to-enable-next-generation","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XdLUcBAAACUAPnsI%22%29+%5D%5D","tags":[],"first_publication_date":"2019-11-18T17:39:10+0000","last_publication_date":"2023-05-15T18:32:22+0000","slugs":["architek-select-sifive-and-dts-insight-to-enable-next-generation-ai-solution-development"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"ArchiTek Select SiFive and DTS-Insight To Enable Next-Generation AI Solution Development","spans":[]}],"publish_to":"Archive","publish_date":"2019-11-18","share_image":{"link_type":"Media","kind":"image","id":"XdLSmxAAACUAPnL2","url":"https://images.prismic.io/sifive/d22080ec-706c-4967-9bce-7a29fd35cf4b_sifivearchiteklockup.PNG?auto=compress,format","name":"sifivearchiteklockup.PNG","size":"831991","width":"993","height":"475"},"body":[{"type":"preformatted","text":"*Use of SiFive’s RISC-V Core IP Enables Low Power AI IoT Edge and End Point Devices*\n\n**SAN MATEO, Calif. – Nov. 12, 2019** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, announced today a new partnership with [ArchiTek Corporation](https://www.architek.ai), a leading embedded technology designer, in collaboration with [DTS-Insight](https://www.dts-insight.co.jp/en/index.html), a leading embedded platform software developer. The new partnership will enable ArchiTek to design a new embedded, low-cost, high-performance SoC for AI, based on the high-performance, low-power, ArchiTek Intelligence Pixel Engine. \u003c/br\u003e\r\n\n**ArchiTek Intelligence Pixel Engine**\u003c/br\u003e\r\nThe ArchiTek Intelligence Pixel Engine (aIPE) is a programmable local space imaging and image processing engine that combines a custom hardware architecture with innovative software flexibility. Using virtual engine technology, the aIPE is optimized for low-power consumption with low latency performance, to provide a versatile and affordable AI solution. Low power, high-performance silicon for computer vision and AI algorithms can be used in autonomous vehicles, security cameras, cybersecurity systems, robotics, and data centers.\u003c/br\u003e\r\n\n**SiFive RISC-V IP**\u003c/br\u003e\r\nWith local support from official SiFive partner [DTS-Insight](https://www.sifive.com/press/sifive-signs-dts-insight-as-official-distributor-to), ArchiTek selected SiFive Core IP and SiFive Core Designer to develop the next-generation aIPE SoC. Optimized to ArchiTek’s workload requirements via SiFive’s web-based Core Designer tool, ArchiTek will leverage the power of custom-configured RISC-V based processor cores to maximize the performance of the aIPE engine.\u003c/br\u003e\r\n\n“The superior performance, power, and area delivered by SiFive Core IP made the choice for the next-generation aIPE SoC simple,” said Shuichi Takada, President \u0026 CTO at ArchiTek Corporation. “We have great confidence in selecting SiFive over competitor or legacy providers due to the rich heritage of SiFive, as leading commercial provider of RISC-V IP, combined with the local technical support of DTS-Insight to ensure success. ”\u003c/br\u003e\r\n\r\n“I am very excited to see SiFive Core IP enabling the design of new AI processors,” said Naveed Sherwani, President and CEO of SiFive. “The migration of deep learning out of the data center is driving the need for configurable solutions. SiFive is uniquely positioned to enable domain-specific solutions with silicon-proven IP.”\u003c/br\u003e\r\n\r\nConnect with ArchiTek Corporation at the [Embedded Technology \u0026 IoT Technology Conference 2019](http://www.jasa.or.jp/expo/english/), in Yokohama, Japan, from November 20th to 22nd.\u003c/br\u003e\r\n\r\n**About SiFive**\u003c/br\u003e\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [SiFive.com](https://www.sifive.com).\u003c/br\u003e\r\n\n**About ArchiTek**\u003c/br\u003e\r\nArchiTek chip, a startup that addresses the pressing need to lower the cost and increase the performance of artificial intelligence, demonstrated its low power, high performance chip that runs computer vision and AI algorithms with high performance. The chip can be used for autonomous vehicles, security cameras, cybersecurity systems, robotics, and data centers. It aims to make AI more affordable and integrated into mainstream applications. For more information, visit [ArchiTek.ai](https://www.architek.ai).\u003cbr/\u003e\r\n \r\n**Media Contacts**\u003cbr/\u003e \r\nLeslie Clavin\u003cbr/\u003e\nSHIFT Communications for SiFive\u003cbr/\u003e\n(415) 591-8440\u003cbr/\u003e\nsifive@shiftcomm.com\u003cbr/\u003e","spans":[]}]}},{"id":"XaYXZRAAACAAdzZo","uid":"quicklogic-teams-with-sifive-to-make-efpga-technology","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XaYXZRAAACAAdzZo%22%29+%5D%5D","tags":[],"first_publication_date":"2019-10-16T13:00:03+0000","last_publication_date":"2023-05-15T17:48:14+0000","slugs":["quicklogic-teams-with-sifive-to-make-efpga-technology-available-via-designshare-portfolio"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"QuickLogic Teams with SiFive to Make eFPGA Technology Available via DesignShare Portfolio","spans":[]}],"publish_to":"Archive","publish_date":"2019-10-16","share_image":{"link_type":"Media","kind":"image","id":"XUEakxAAAPn_QbhJ","url":"https://images.prismic.io/sifive%2F3a4aea94-f7a2-4b9f-bf93-beba50fc9514_ai+camera.png?auto=compress,format","name":"AI Camera.png","size":"30349","width":"640","height":"705"},"body":[{"type":"preformatted","text":"*Gives SoC designers an easy way to add post-manufacturing design flexibility*\r\n*Builds on previously announced strategic partnership and SoC template*\n\n**SAN MATEO, Calif. - October 16th, 2019** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP, announced today that is has partnered with QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, to add QuickLogic’s [embedded FPGA](https://www.quicklogic.com/products/efpga/arcticpro/) (eFPGA) technology to the SiFive DesignShare program of IP for SoC designs. This license makes it easy for SoC developers to add voice and AI subsystems, along with post-manufacturing design flexibility, to their SoCs via SiFive’s DesignShare program. \n\nThe SiFive DesignShare IP program offers a streamlined process for companies seeking to partner with leading vendors to provide pre-integrated premium Silicon IP for bringing new SoCs to market. As part of SiFive’s business model to license IP when ready for mass production, the flexibility and choice of the DesignShare IP program reduces the complexities of contract negotiation and licensing agreements to enable faster time to market through simpler prototyping, no legal red tape, and no upfront payment. \r\n\n“The demand for voice and AI-based IoT solutions is growing,” said Mohit Gupta, vice president of IP solutions at SiFive. “Because this is a quickly-evolving market, designers also need flexibility in their SoC designs, often with further customization taking place post-production. Adding QuickLogic’s eFPGA IP to our DesignShare ecosystem offers our customers a solution that is not only flexible but low-cost, ultra-low power and very high-performance.” \r\n\n“SiFive’s DesignShare program provides an extensive IP offering for developers of RISC-V based SoCs, and now those same developers can easily add our eFPGA technology to their designs,” said Brian Faith, president and CEO of QuickLogic Corporation. “This relationship with SiFive gives IoT and other SoC designers easy access to the flexibility and low power benefits associated with eFPGA technology.”\r\n\r\n**Availability**\n\r\nSiFive’s DesignShare program, including QuickLogic’s eFGPA IP, is available now. Visit the [SiFive DesignShare page](/designshare) for more information.\r\n\r\n**About SiFive**\n\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [www.sifive.com](https://www.sifive.com).\r\n\r\n**About QuickLogic**\r\n\nQuickLogic Corporation (NASDAQ: QUIK) is a fabless semiconductor company that develops low power, multi-core semiconductor platforms and Intellectual Property (IP) for Artificial Intelligence (AI), voice and sensor processing. The solutions include embedded FPGA IP (eFPGA) for hardware acceleration and pre-processing, and heterogeneous multi-core SoCs that integrate eFPGA with other processors and peripherals. The Analytics Toolkit from our recently acquired wholly-owned subsidiary, SensiML Corporation, completes the end-to-end solution with accurate sensor algorithms using AI technology. The full range of platforms, software tools and eFPGA IP enables the practical and efficient adoption of AI, voice and sensor processing across mobile, wearable, hearable, consumer, industrial, edge and endpoint IoT. For more information, visit [quicklogic.com](https://www.quicklogic.com) and [quicklogic.com/blog](https://www.quicklogic.com/blog/).\r\n\r\n\r\nQuickLogic and logo are registered trademarks of QuickLogic. All other trademarks are the property of their respective holders and should be treated as such.\r\n\r\n**MEDIA CONTACTS**\n\nSara Dodrill \nSHIFT Communications for SiFive \n415-591-8429 \nsdodrill@shiftcomm.com\n\nAndrea Vedanayagam \nVeda Communications \n408-656-4494 \npr@quicklogic.com \n\n\n","spans":[]}]}},{"id":"XdXK9xAAACoAS4UM","uid":"sifive-welcomes-stuart-ching-as-chief-revenue-officer","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XdXK9xAAACoAS4UM%22%29+%5D%5D","tags":[],"first_publication_date":"2019-11-21T14:00:02+0000","last_publication_date":"2023-05-15T18:21:03+0000","slugs":["sifive-welcomes-stuart-ching-as-chief-revenue-officer"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Welcomes Stuart Ching As Chief Revenue Officer","spans":[]}],"publish_to":"Archive","publish_date":"2019-11-21","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Arm Veteran to Oversee and Drive Strategy for Continued Sales and Revenue Hypergrowth*\n\n**SAN MATEO, Calif. – Nov. 21, 2019** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Stuart Ching has joined the company as Chief Revenue Officer. He will lead sales and revenue development for the company, which has experienced hypergrowth this year, recently disclosing 130 design wins, over 500 employees worldwide and several new technologies. SiFive most recently unveiled the world’s first RISC-V based out-of-order superscalar processor IP, SiFive U8-Series Core IP; and the SiFive Shield security platform architecture, including SiFive WorldGuard, for whole SoC security. \u003c/br\u003e\r\n\n“SiFive has tremendous opportunity ahead of it,” said Ching. “The potent combination of high-performance, high-efficiency Core IP with proven silicon expertise, provided as a scalable, configurable design space is perfectly positioned to take advantage of the growing need for domain-specific SoCs in SiFive’s focus markets. The migration of deep learning to the edge and endpoint for both consumer and industrial devices requires new designs that SiFive’s innovation and expertise can rapidly and easily provide.” \u003c/br\u003e\r\n\r\nChing has a deep background in technology and semiconductor sales, strategy and IP, bringing more than 20 years of sales and strategy leadership experience to SiFive. Ching worked at Arm for 17 years, swiftly progressing through prominent executive roles, advancing to senior vice president of commercial strategic development. Ching also has served as a board advisor to companies in the AI, eMobilty and semiconductor spaces across the globe, and has served as Principal at Hoko Consulting. \u003c/br\u003e\r\n\r\n“We’re pleased to add Stuart to our executive team to further drive our sales and revenue operations as part of SiFive’s hypergrowth,” said Naveed Sherwani, President and CEO of SiFive. “Stuart’s proven acumen and deep industry connections will be instrumental in propelling SiFive’s business growth. As we deepen our presence in deep learning from the data center attach to edge, endpoint, automotive, industrial \u0026 consumer IoT. I’m confident Stuart’s experience and drive will bring success.” \u003c/br\u003e\r\n\r\nChing holds a Bachelor’s degree in electronic engineering from the University of Portsmouth, United Kingdom, and is a graduate of the Stanford University Executive Program. \r\n\n**About SiFive**\u003c/br\u003e\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [SiFive.com](https://www.sifive.com).\u003c/br\u003e\n\nStay current with the latest SiFive updates via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\u003c/br\u003e\n\n**Media Contacts**\u003cbr/\u003e \r\nSara Dodrill\u003cbr/\u003e\nSHIFT Communications for SiFive\u003cbr/\u003e\n(415) 591-8429\u003cbr/\u003e\nsifive@shiftcomm.com\u003cbr/\u003e","spans":[]}]}},{"id":"X1vQPBMAACIA_tRM","uid":"sifive-to-introduce-new-risc-v-processor-architecture","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22X1vQPBMAACIA_tRM%22%29+%5D%5D","tags":[],"first_publication_date":"2020-09-14T13:00:04+0000","last_publication_date":"2023-05-15T18:41:18+0000","slugs":["sifive-to-introduce-new-risc-v-processor-architecture-and-risc-v-pc-at-linley-fall-virtual-processor-conference"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive To Introduce New RISC-V Processor Architecture and RISC-V PC at Linley Fall Virtual Processor Conference","spans":[]}],"publish_to":"Archive","publish_date":"2020-09-14","share_image":{"link_type":"Media","kind":"image","id":"X1vO6RMAACIA_s53","url":"https://images.prismic.io/sifive/1f739e9b-1c1d-456d-8db2-2f2c2ce300ca_linleygroup-fallvpc2020-social.png?auto=compress,format","name":"linleygroup-fallvpc2020-social.png","size":"432694","width":"1000","height":"541"},"body":[{"type":"preformatted","text":"*SiFive Founders and Inventors of RISC-V will deep dive new vector-based architecture, and debut new SoC for professional developers of RISC-V applications*\n\n**SAN MATEO, Calif. Sep 14, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP, today announced that Dr. Yunsup Lee, CTO of SiFive, and Dr. Krste Asanovic, Chief Architect of SiFive, will present at the technology industry’s premier processor conference, the Linley Fall Virtual Processor Conference. The conference will be held on October 20th – 22nd and 27th – 29th, 2020 and will feature high-quality technical content from leading semiconductor companies worldwide.\u003cbr/\u003e\n\n\"Industry demand for AI performance has skyrocketed over the last few years driven by rapid adoption from the data center to the edge. This year's Linley Fall Processor Conference will feature our biggest program yet and will introduce a host of new technology disclosures and product announcements of innovative processor architectures and IP technologies,\" said Linley Gwennap, principal analyst and conference chairperson. \"In spite of the challenges posed by the pandemic, development of these technologies continues to accelerate and we're excited to be sharing these presentations with a global audience via our live-streamed format.\"\u003cbr/\u003e\r\n\r\nSiFive’s portfolio of processor Core IP is based on the free and open RISC-V instruction set architecture, and consists of four unique micro-architectures designed to enable different classes of performance, efficiency, and features for application and deeply embedded uses. Designed for scalability, SiFive Core IP can be tailored to workload requirements through the highly-configurable parameters of the architecture. \u003cbr/\u003e\r\n\n**Extending AI SoC design possibilities through Linux-capable vector processors**\u003cbr/\u003e\nThe combination of scalable vector processing with a Linux-capable superscalar multi-core processor opens up a wide range of design points and applications for RISC-V. This new processor core features a complete implementation of the latest RISC-V Vector (RVV) extension. Presented by Dr. Krste Asanovic, SiFive Intelligence is slated for production use based on the fully ratified version of the RVV specification and enables a single processing and development environment for scalar and high-performance vector processing applications. Recently, SiFive announced a collaboration with the Barcelona Supercomputing Center to create a [new API](https://www.sifive.com/press/sifive-and-barcelona-supercomputing-center-advance) for popular compilers, further enabling applications to use the RISC-V Vector Extension currently under development for high-performance computing, artificial intelligence, and computer vision applications.\u003cbr/\u003e\r\n\n“SiFive Intelligence will offer a high-performance converged processor core capable of flexible execution of many workloads based on a single, industry-standard ISA,” said Chris Lattner, President of Product and Engineering at SiFive. “This is a transformative option for the technology industry as innovators look for ways to build solutions to intense computational challenges, from deep learning in the datacenter to image, video, or audio processing at the edge.”\u003cbr/\u003e\n \r\n**Creating a RISC-V PC Ecosystem for Linux Application Development**\u003cbr/\u003e\r\nNew processor architectures require access to development environments to create and optimize software. The SiFive Freedom U740 next-generation SoC will enable professional developers to create RISC-V applications from bare-metal to Linux-based, including porting of existing applications. The FU740 combines a heterogeneous mix+match core complex with modern PC expansion capabilities and form factor with a suite of included tools to facilitate broad professional software development. Presented by Dr. Yunsup Lee, SiFive will debut the world’s first RISC-V PC, based on the upcoming new FU740, which will be publicly demonstrated at the Linley Conference. The SiFive FU740 will enable professional developers to create RISC-V applications in a bare-metal environment, from OS to end-user application, using powerful SiFive U7-series processor cores.\u003cbr/\u003e\r\n\nRegistration for The Linley Group Fall Virtual Processor Conference is free and open [now](https://www.linleygroup.com/events/event.php?num=49) for qualified registrants. The conference is intended for chip designers, system designers, equipment vendors, OEM/ODMs, service providers, press, and the financial community.\u003c/br\u003e\n\r\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\n\r\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e","spans":[]}]}},{"id":"XKvpthEAAB4Av6Vv","uid":"synaptics-selects-and-designs-sifive-custom-e2-series","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XKvpthEAAB4Av6Vv%22%29+%5D%5D","tags":[],"first_publication_date":"2019-04-09T13:00:21+0000","last_publication_date":"2023-05-15T15:03:02+0000","slugs":["synaptics-selects-and-designs-sifive-custom-e2-series-core-ip-in-record-time"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Synaptics Selects and Designs SiFive Custom E2 Series Core IP in Record Time","spans":[]}],"publish_to":"Archive","publish_date":"2019-04-09","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Human interface solutions leader uses SiFive Core Designer to configure\nembedded processor in two months*\n\n**SAN MATEO, Calif. \u0026mdash; April 9, 2019 \u0026mdash;**\n[SiFive](https://www.sifive.com), the leading provider of commercial\nRISC-V processor IP, today announced that Synaptics Incorporated has\nlicensed the SiFive E2 Series Core IP. Synaptics, a leading developer of\nhuman interface solutions, used the SiFive Core Designer cloud-based\nplatform to evaluate, configure and finalize its custom processor\nsolution in just two months, a significant reduction from traditional\ndesign platforms.\n\nSiFive Core IP enables the differentiation and customization desperately\nneeded in the embedded market and enables intelligence at the edge of\nthe network with 64-bit embedded and advanced, coherent, heterogenous\nsystems. SiFive Core Designer allows customers to conduct the evaluation\nprocess quickly, and customize their processor with a core that fits\ntheir specific needs in an efficient performance and power envelope.\nSynaptics was able to go through the selection, customization and\nenhancement phases of design in just two months.\n\n\"SiFive's Core Designer allowed our design team to get direct, hands-on\naccess much earlier in the process and enabled us to rapidly optimize\nour configuration,\" said Prashant Shamarao, vice president, product\ndevelopment, Synaptics. \"We were impressed by the robustness and\ncompleteness of SiFive Core Designer as well as the support we\nreceived.\"\n\n\"We are proud to partner with an industry leader in human-machine\ninterfaces,\" said Naveed Sherwani, CEO, SiFive. \"Our Core IP is well\nsuited for high-performance embedded solutions, and Synaptics'\nexperience with our Core Designer showcases the rapid innovation and\ntime-to-market the platform enables. We foresee more solutions like this\nmoving to a cloud design.\"\n\n**About SiFive**\n\nSiFive is the leading provider of market-ready processor core IP,\ndevelopment tools and silicon solutions based on the free and open\nRISC-V instruction set architecture. Led by a team of seasoned silicon\nexecutives and the RISC-V inventors, SiFive helps SoC designers reduce\ntime-to-market and realize cost savings with customized,\nopen-architecture processor cores, and democratizes access to optimized\nsilicon by enabling system designers in all market verticals to build\ncustomized RISC-V based semiconductors. Located in Silicon Valley,\nSiFive has backing from Sutter Hill Ventures, Spark Capital, Osage\nUniversity Partners, Chengwei, Huami, SK Hynix, Intel Capital, and\nWestern Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n**MEDIA CONTACTS**\n\nLeslie Clavin \nSHIFT Communications for SiFive \n415-591-8440 \n[sifive\\@shiftcomm.com](mailto:sifive@shiftcomm.com)\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqy","uid":"sifive-launches-first-risc-v-based-cpu-core-with-linux-support","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqy%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2023-05-16T14:03:11+0000","slugs":["sifive-launches-first-risc-v-based-cpu-core-with-linux-support"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Launches First RISC-V Based CPU Core with Linux Support","spans":[]}],"publish_to":"Archive","publish_date":"2017-10-04","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Oct. 4, 2017 –\u003c/span\u003e\n[SiFive](https://www.sifive.com), the first fabless provider of customized,\nopen-source-enabled semiconductors, today announced the availability of \n[U54-MC Coreplex IP](https://www.sifive.com/cores/u54-mc),\nthe industry’s first RISC-V based, 64-bit, quadcore real-time\ncapable application processor with support for full featured operating systems\nsuch as Linux. The free and open RISC-V architecture, which is supported by an\necosystem comprising more than 70 companies, has seen tremendous growth in the\nembedded segment. The release of the U54-MC Coreplex marks the architecture’s\nexpansion into the application processor space – opening entirely new use cases\nfor RISC-V.\n\nRISC-V is a free and open instruction set architecture (ISA) designed to enable\nchips across the full spectrum of computing devices, from embedded devices to\nthe data center. As the first RISC-V application processor capable of running\nembedded Linux, the standard U54-MC Coreplex contains four U54 CPUs along with\na single E51 CPU, and is the first commercial RISC-V core to include multicore\nsupport and cache coherence. Each U54 CPU utilizes a highly efficient\nfive-stage in-order pipeline. The U54 cores support the RV64GC ISA, which is\nexpected to be the standard for Linux-based RISC-V devices. The\n[64-bit E51 CPU](https://www.sifive.com/risc-v-core-ip)\nserves as a management core and is fully coherent with the main U54 cores.\nThe U54-MC Coreplex is ideal for applications which need full operating system\nsupport such as AI, machine learning, networking, gateways and smart IoT\ndevices.\n\n\"SiFive has achieved another significant milestone for the RISC-V community,\" said Rick\nO’Connor, executive director of the non-profit [RISC-V Foundation](https://riscv.org/).\n\"The ability for RISC-V\ndevelopers to develop Linux and other Unix-based operating systems on commercial grade\nsilicon will enable the RISC-V software ecosystem to quickly expand beyond embedded systems,\nand bring new solutions to market. We look forward to seeing the various markets that are now\naddressable with SiFive’s U54-MC Coreplex IP.\"\n\nSiFive’s U54-MC Coreplex has been taped out as part of SiFive’s Freedom\nUnleashed family of high-performance, customizable RISC-V SoCs. As implemented\nin the Freedom Unleashed platform, the U54 and E51 CPUs run at 1.5+ GHz in 28nm\ntechnology. Each of the U54 CPUs implement a 32KB Instruction Cache and 32KB\nData Cache, and all of the cores share a coherent, 2MB L2 Cache. Customers can\nlicense the U54-MC Coreplex in a variety of configurations besides the 4+1\ndefault configuration.\n\n\"The U54-MC Coreplex is the first fully Linux-compatible CPU based on RISC-V.\nIt takes the industry one step closer to making custom silicon available to\neveryone,\" said Andrew Waterman, co-founder of SiFive. \"We continue to be\namazed by the support SiFive has received since we launched the industry’s\nfirst open-source RISC-V SoC last year, and look forward to additional\nmilestones in the coming months.\"\n\n## Availability\n\nThe U54-MC Coreplex can be accessed at\n[https://www.sifive.com/cores/u54-mc](https://www.sifive.com/cores/u54-mc).\nA development\nboard based on U54-MC Coreplex IP will be available in Q1 2018. For more\ninformation on the U-series Coreplex IP, please visit\n[https://www.sifive.com/core-designer](https://www.sifive.com/core-designer).\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the\nfree and open RISC-V instruction set architecture. Founded by RISC-V inventors\nYunsup Lee, Andrew Waterman and Krste Asanovic, SiFive democratizes access to\ncustom silicon by helping system designers reduce time-to-market and realize\ncost savings with customized RISC-V based semiconductors. SiFive is located in\nSilicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital\nand Osage University Partners. For more information, visit [www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqi","uid":"sifive-inc-and-andes-technology-corporation-join-forces-to-promote-risc-v","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqi%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2023-05-15T15:16:18+0000","slugs":["sifive-inc.-and-andes-technology-corporation-join-forces-to-promote-risc-v"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Inc. and Andes Technology Corporation Join Forces to Promote RISC-V","spans":[]}],"publish_to":"Archive","publish_date":"2018-05-17","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eShanghai and San Mateo, Calif. – May 17, 2018 – \u003c/span\u003e\nAndes Technology Corporation, the prominent CPU IP provider, and SiFive Inc., the leading provider of ASIC design service and RISC-V CPU Core IP, have announced they are joining forces to jointly promote RISC-V. The two companies will each contribute their unique expertise in CPU development and support to expand the ecosystem for the RISC-V instruction set architecture (ISA) to enable a new era of processor innovation through open standard collaboration. \n\n“RISC-V is providing a newfound freedom in silicon design, fostering stronger collaboration across the semiconductor industry. We’re excited to see SiFive and Andes partnering to expand the RISC-V ecosystem, making it easier for other industry players to quickly bring to market innovative designs based on the free and open RISC-V ISA,” said Rick O’Connor, Executive Director of the non-profit RISC-V Foundation.\n\nAs a founding member of the RISC-V Foundation, Andes Technology is dedicated to bringing its expertise in low-power and high performance 32/64 bit processor cores to the development of the RISC-V ISA. For example, at the recent RISC-V Workshop in Barcelona, Andes proposed an extension to the RISC-V ISA based on the DSP ISA used in Andes’ successful D10 and D15 processors. In addition, Andes debuted four new RISC-V processor IPs with compliant floating-point and Linux support: the 64-bit NX25F and AX25, and 32-bit N25F and A25. Andes’ innovative ACE (Andes Custom Extension™) solution allows Andes' customers to construct unique system architecture and hardware/software partitioning by defining domain-specific acceleration instructions to provide the best optimization for their SoC designs. Offering technologies in processor, system architecture, operating system, software toolchains development, and SoC design platforms IP, Andes enables its customers to shorten time-to-market while developing high-quality silicon in the shortest design time.\n\nSiFive’s cloud-based SaaS approach allows its customers to produce ASIC and IP solutions that meets their needs quickly and affordably. SiFive’s mission is to democratize access to custom silicon through its IPs and platforms. Since becoming available, the HiFive1 and HiFive Unleashed software development boards have been deployed in more than 50 countries. Additionally, the company has engaged with multiple customers across its IP and SoC products [shipped the industry’s first RISC-V SoC](https://www.sifive.com/press/sifive-introduces-industrys-first-open-source-chip-platforms) in 2016 and the industry’s first RISC-V Core IP with support for Linux in October 2017.\n\nLed by a team of industry veterans and founded by the inventors of RISC-V, SiFive has recently raised $50.6M in Series C funding to fund innovation and provide leadership in bringing highly disruptive RISC-V technologies to the marketplace.\n\n\n## RISC-V Enables Innovation\n\nRISC-V is an open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, the RISC-V ISA delivers a new level of extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. As the focus of a new upsurge in technology, RISC-V has flourished around the world. RISC-V is the new open ISA. It can be reduced, modularized, customized, easily expanded, and enable the rapid development of a design ecosystem. A large and growing number of leading technology companies have joined the RISC-V Foundation. SiFive and Andes have chosen Shanghai as the ideal location to relay efforts in promoting RISC-V to the world.\n\nRISC-V is an open, extensible ISA, and its applications include the emerging areas such as AI, IoT, and ADAS. Its expansive ecosystem is even more valuable. The RISC-V ISA is expected to have a bright future of computing design in China.\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Western Digital, Intel, SK Telecom, and Huami. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## About Andes \n\nAndes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications. The company delivers the best super low power CPU cores, including the rising star RISC-V series with integrated development environment and associated software and hardware solutions for efficient SoC design. Up to the end of 2017, the cumulative amount of SoCs containing Andes’ CPU IP reaches 2.5 billion. To meet the demanding requirements of today's electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers' needs for quality products and faster time-to-market. Andes Technology's comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line and provides a total solution of RISC-V, the RISC-V series as V5 families processors cores include N25/NX25 and upcoming N25F/NX25F and A25/AX25. For more information about Andes Technology, please visit [http://www.andestech.com/](http://www.andestech.com/).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n\n\u003caddress\u003e\nJonah McLeod\u003cbr\u003e\nAndes Technology Corporation\u003cbr\u003e\n(510) 449-8634\u003e\u003cbr\u003e\njonahm@andestech.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"Xeg6jxIAACIAJoUZ","uid":"sifive-announces-sifive-learn-initiative","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Xeg6jxIAACIAJoUZ%22%29+%5D%5D","tags":[],"first_publication_date":"2019-12-05T00:41:55+0000","last_publication_date":"2023-05-15T14:58:21+0000","slugs":["sifive-announces-sifive-learn-initiative"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Announces SiFive Learn Initiative","spans":[]}],"publish_to":"Archive","publish_date":"2019-12-02","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Innovative New SiFive Learn Inventor To Empower a New Generations of Makers and Engineers*\n\nSAN MATEO, Calif., Dec. 2, 2019 /PRNewswire/ -- SiFive Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today unveiled its SiFive Learn initiative, a program designed to enable makers and universities with low-cost, fully-featured RISC-V hardware supported by comprehensive learning materials. As part of this initiative, SiFive also announced the availability of the SiFive Learn Inventor development platform. The most accessible SiFive board to date, the SiFive Learn Inventor features a comprehensive software package and education enablement course.\r\n\r\n\"We're excited to see the new SiFive Learn Inventor board come to market,\" said Dr. Naveed Sherwani, President, and CEO of SiFive. \"The broad features and comprehensive tools will help a wide range of people develop their coding skills for the next generation of devices.\"\r\n\r\n\"SiFive Learn supports our efforts to democratize access to custom silicon and to empower the next generation of makers and engineers,\" said Jeff Mulhausen, Chief Evangelist at SiFive and leader of the SiFive Learn initiative. \"Education is an important part of our vision, and we feel SiFive Learn is a great way to provide teaching tools for universities, academics, and corporations.\"\r\n\r\nThe programmable SiFive Learn Inventor includes the following features:\r\n\r\n- SiFive FE310 Processor with 150 Mhz clock speed\r\n- Bluetooth + Wi-Fi\r\n- Accelerometer\r\n- Gyroscope\r\n- Temperature Sensor\r\n- Compass\r\n- Ambient Light Sensor\r\n- 6X8 display lights with 16M colors\n\n## Pricing and Availability:\nThe SiFive Learn Inventor board is available for pre-order at [https://www.pimoroni.com/sifive](https://www.pimoroni.com/sifive), and first shipments expected in December 2019.\r\n\r\nThe SiFive Learn Inventor board will be shown at Amazon AWS re:Invent in Las Vegas, NV, Dec. 2nd – 6th. Please visit the SiFive kiosk at the Sands Expo, hall B, level 2, booth #2704.\r\n\r\n## About SiFive\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [visit SiFive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\r\n\r\nAmazon, Amazon Web Services, and AWS are registered trademarks of Amazon.com, Inc. All brands or product names are the property of their respective holders.\r\n\r\n**Media Contact**\u003cbr\u003e\r\nSara Dodrill\u003cbr\u003e \r\nSHIFT Communications for SiFive\u003cbr\u003e\r\n(415) 591-8429\u003cbr\u003e\r\nsifive@shiftcomm.com\u003cbr\u003e\r\n","spans":[]}]}},{"id":"X2K66xMAACIAHUW_","uid":"sifive-appoints-patrick-little-as-president-and-chief","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22X2K66xMAACIAHUW_%22%29+%5D%5D","tags":[],"first_publication_date":"2020-09-17T13:00:04+0000","last_publication_date":"2023-05-15T18:36:53+0000","slugs":["sifive-appoints-patrick-little-as-president-and-chief-executive-officer"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Appoints Patrick Little as President and Chief Executive Officer","spans":[]}],"publish_to":"Archive","publish_date":"2020-09-17","share_image":{"link_type":"Media","kind":"image","id":"X2Ku_xMAACMAHRFi","url":"https://images.prismic.io/sifive/0c1ac729-0353-4d7c-9c01-c318b643bad6_CEOblogsocialimage.png?auto=compress,format","name":"CEOblogsocialimage.png","size":"748342","width":"1000","height":"584"},"body":[{"type":"preformatted","text":"*Industry Veteran To Lead Mission To Develop RISC-V-based Platforms to Solve Next-Generation Computing Challenges*\n\n**SAN MATEO, Calif. Sep 17, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V-based platforms and custom silicon solutions, today announced the appointment of Patrick Little as President and CEO, effective immediately. Mr. Little succeeds Dr. Naveed Sherwani, who has stepped down as President and CEO and will remain Chairman of the board of directors of SiFive as part of a growth plan to accelerate the adoption of SiFive technology for next-generation computing solutions. Recently, SiFive announced the completion of a successful [Series E investment](https://www.sifive.com/press/sifive-secures-61-million-in-series-e-funding) round which secured an additional $61M to continue the development of RISC-V based platforms for high-growth markets such as high-performance computing, artificial intelligence and deep learning, automotive, computational storage, and computer vision. This brings investment in the company to $190M to date.\u003cbr/\u003e\r\n\r\n“I am honored to lead the brilliant, hard-working team of innovators and engineers at SiFive who are responsible for creating some of the most impactful architectures in our industry,” said Patrick Little, President and CEO of SiFive. “Across the technology industry, a sharpened focus on workload-acceleration to solve next-generation computing challenges is driving demand for SiFive’s configurable RISC-V-based platforms. Our industry-leading technology portfolio provides a unique platform that empowers our customers to deliver differentiated solutions in their markets.”\u003cbr/\u003e\r\n\r\nMr. Little joins SiFive from Qualcomm where he led their successful expansion into the automotive industry as Senior Vice President and General Manager. Patrick has over 30 years of operating experience in executive roles in the technology and semiconductor industries, including CEO of eASIC Corp., Senior Vice President of CSR Technology, and Senior Vice President at Xilinx Inc. Patrick has served on the board of directors of numerous public and private technology companies throughout his career. Mr. Little holds a Bachelor of Science degree in Electrical Engineering from San Jose State University.\u003cbr/\u003e \r\n\r\n“The fast pace of SiFive’s growth and advanced portfolio is directly related to the strength and uniqueness of SiFive’s technology,” said Stefan Dyckerhoff, Managing Director of Sutter Hill Ventures. “The sharpening focus of the technology industry on using high-quality IP based on open-standards continues to create demand for technology that SiFive is uniquely positioned to provide. Industry support for RISC-V has never been stronger, as seen during recent industry events showcasing new, breakthrough designs based on RISC-V.”\u003cbr/\u003e\r\n\r\n“I am pleased and excited to help Patrick elevate SiFive to the next level of success,” said Dr. Naveed Sherwani, Chairman of SiFive’s board of directors. “Patrick's proven expertise in execution and strategy will benefit SiFive tremendously as we continue to increase focus on enabling domain-specific architectures for markets such as high-performance computing, artificial intelligence, and computer vision.”\u003cbr/\u003e\r\n\r\nSiFive’s portfolio of processor Core IP is based on the free and open RISC-V instruction set architecture, invented by the founders of SiFive, 10 years ago. Development of the RISC-V ISA and extensions is governed by RISC-V International, in open working groups composed of technology leaders and company representatives. Designed for scalability, SiFive RISC-V-based platforms can be tailored to customer workload requirements through the highly-configurable parameters of the architecture, and focused using custom instructions.\u003cbr/\u003e \r\n\r\nSiFive recently announced a collaboration with the Barcelona Supercomputing Center to create an open-source [new API](https://www.sifive.com/press/sifive-and-barcelona-supercomputing-center-advance) for popular compilers, further enabling applications to use the RISC-V Vector Extension currently under development for high-performance computing, artificial intelligence, and computer vision applications. SiFive continues to lead the development of the RISC-V ecosystem, enabling support for existing toolchains, operating systems, compilers, and developer environments to integrate RISC-V support into their workflows to simplify the adoption of RISC-V in new designs.\u003cbr/\u003e \r\n\r\nRead more from Patrick on his thoughts about joining SiFive in his blog, [here](https://www.sifive.com/blog/the-incredible-opportunity-for-sifive).\u003cbr/\u003e\r\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\n\r\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vq2","uid":"sifive-introduces-industrys-first-open-source-chip-platforms","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vq2%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2023-05-15T14:32:57+0000","slugs":["sifive-introduces-industrys-first-open-source-chip-platforms"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Introduces Industry’s First Open-Source Chip Platforms","spans":[]}],"publish_to":"Archive","publish_date":"2016-07-11","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN FRANCISCO – July 11, 2016\u003c/span\u003e – [SiFive](https://www.sifive.com), the first fabless semiconductor company to build customized, open-source enabled semiconductors, today announced its flagship Freedom family of system on a chip (SoC) platforms. Built around the free and open RISC-V instruction set architecture invented by the company’s founders at the University of California, Berkeley, SiFive’s Freedom U500 and Freedom E300 platforms represent a fundamentally new approach to designing and producing SoCs that redefines traditional silicon business models and reverses the industry’s prohibitively rising licensing, design and implementation costs.\n\n“The semiconductor industry is at an important crossroads. Moore’s Law has ended, and the traditional economic model of chip building no longer works,” said Yunsup Lee, co-founder of SiFive and one of the original creators of RISC-V. “Unless you have tens — if not hundreds — of millions of dollars, it is simply impossible for smaller system designers to get a modern, high- performance chip, much less one customized to their unique requirements. The Freedom platforms unleash the flexibility and power of custom silicon to the smallest company, inventor or maker. And companies of all sizes are no longer held hostage to current semiconductor providers’ software deliveries and outdated business models.”\n\nRISC-V was born from the dire need to address the skyrocketing cost of designing and manufacturing increasingly complex new chip architectures, as a result of the economic demise of Moore’s Law. SiFive’s hardware designs leverage the body of software and tools available from the open-source community under the guidance of the RISC-V Foundation, dramatically reducing the cost of developing custom silicon. System designers can use the SiFive Freedom platforms to focus on their own differentiated processor without having the overhead of developing a modern SoC, fabric or software infrastructure.\n\n“RISC-V represents a bold new path for system designers in embedded and industrial markets,” said Ted Speers, head of product architecture and planning for [Microsemi Corporation’s](http://www.microsemi.com) SoC business unit. “We went to SiFive not only because its co-founders created RISC-V, but also due to its team’s agile methodology which enabled the company to deliver a complete RISC-V sub-system and tool-chain targeting our secure, low power SmartFusion™2 SoC FPGA platform on a very aggressive schedule.”\n\nThe Freedom platforms comprise a complete software specification, board OS support packages (BSPs), development boards and base silicon. The platforms provide customers the ability to create their own silicon enhancements and customizations, which SiFive then quickly incorporates and delivers to the customer at a much lower cost and faster time-to-market than traditional custom silicon designs. The platforms also provide significant performance and power advantages over existing microcontrollers and FPGAs.\n\n- Freedom U500 Series: The Freedom Unleashed (U) family features a fully Linux-capable embedded application processor featuring the world’s most advanced, multicore RISC-V CPUs, running at a speed of 1.6 GHz or higher with support for accelerators and cache coherency. Designed in TSMC 28nm, the Freedom U500 platform targets initial customers in diverse markets such as machine learning, storage and networking. The Freedom U500 platform also supports standard high-speed peripherals including PCIe 3.0, USB 3.0, Gigabit Ethernet, and DDR3/DDR4.\n- Freedom E300 Series: The Freedom Everywhere (E) family is designed for embedded microcontroller, IoT and wearables markets. Designed in TSMC 180nm and architected to have minimal area and power, the Freedom E300 platform features the world’s most efficient RISC-V cores with support for RISC-V compressed instructions, which have been shown to reduce code size by up to 30 percent.\n\n## For Developers\n\nTo give developers a head start on software development, full FPGA models of each SoC are available through SiFive today. Developers will also be able to prototype their customizations in the form of custom RISC-V instructions, accelerators and co-processors. For more information, including how to purchase development boards with the Microsemi [SmartFusion™2 SoC FPGA](http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2), please visit [www.sifive.com](https://www.sifive.com).\n\nSiFive will showcase the Freedom family of SoC platforms during the [RISC-V 4th Workshop](https://riscv.org/2016/07/4th-risc-v-workshop-final-agenda/) in Boston on Tuesday, July 12.\n\n## About SiFive\n\nSiFive is the first fabless semiconductor company to build customized silicon based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Krste Asanovic, Yunsup Lee and Andrew Waterman, SiFive democratizes access to custom silicon by helping system designers reduce time- to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in San Francisco and has venture backing from Sutter Hill Ventures. For more information visit [www.sifive.com](https://www.sifive.com).\n","spans":[]}]}},{"id":"YIoHqxMAACEA7Epo","uid":"sifive-and-samsung-foundry-extend-partnership-to-accelerate","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YIoHqxMAACEA7Epo%22%29+%5D%5D","tags":[],"first_publication_date":"2021-04-29T13:00:02+0000","last_publication_date":"2023-05-15T15:14:47+0000","slugs":["sifive-and-samsung-foundry-extend-partnership-to-accelerate-ai-soc-development"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and Samsung Foundry Extend Partnership to Accelerate AI SoC Development","spans":[]}],"publish_to":"Archive","publish_date":"2021-04-29","share_image":{"link_type":"Media","kind":"image","id":"YIoHnBMAACMA7Eoh","url":"https://images.prismic.io/sifive/e88e0651-cc87-487e-bf53-ce691c80b328_samsungfoundrysifiveaisoc04292021.jpg?auto=compress,format","name":"samsungfoundrysifiveaisoc04292021.jpg","size":"175555","width":"1200","height":"672"},"body":[{"type":"preformatted","text":"**Configurable SiFive RISC-V AI SoC Development Platform is built on 14nm Samsung process technology to accelerate custom Machine Learning solutions**\n\n**SAN MATEO, Calif., April 29, 2021** – [SiFive, Inc.](https://www.sifive.com), the industry leader in RISC-V processors and silicon solutions, today announced the next phase of their partnership with [Samsung Foundry](https://www.samsungfoundry.com/foundry/homepage/anonymous/about.do?_mainLayOut=homepageLayout\u0026menuIndex=01), a world leader in advanced semiconductor technology. The extended partnership will enable and accelerate the development of Artificial Intelligence and Machine Learning inference and training SoCs based on SiFive RISC-V processors and built using Samsung Foundry technology infrastructure.\u003cbr/\u003e\r\n\r\nThe SiFive RISC-V AI SoC Development Platform combines SiFive RISC-V technology, high-speed peripherals, and multiple AI accelerator blocks. The collaborative effort was further customized with a customer-specific AI inference accelerator IP and an Open Compute Project Microsoft Zipline accelerator, resulting in an AI accelerator SoC tape out on Samsung 2nd generation 14LPP FinFET technology on April 13th, 2021. The ability to rapidly integrate additional IP to the SiFive RISC-V AI SoC Development Platform enables customers to optimize workload processing with custom SoCs.\u003cbr/\u003e\r\n\r\nThe AI accelerator SoC tapeout and inference IP integration utilized SEMIFIVE Platform SoC technology. SEMIFIVE Inc. is the pioneer of platform-based SoC design for the Samsung Foundry ecosystem. Featuring verified PCIe Gen. 4 connectivity and quad-channel 32-bit LPDDR4/4X interfaces, SEMIFIVE provides off-the-shelf opportunities to develop custom hardware focused on the AI workload.\u003cbr/\u003e\r\n\r\n\"Samsung Foundry is committed to building a rich and resilient ecosystem with our industry partners,\" said Mijung Noh, VP of Foundry Design Service Team at Samsung Electronics. \"We are pleased to work with SiFive to accelerate our customers' AI / ML custom SoC design, illustrating the innovation potential we can achieve together.\"\u003cbr/\u003e\n \r\n“Working in partnership with Samsung Foundry has accelerated SiFive’s ability to deliver our highly-efficient and configurable approach for SoC design and implementation,” said Dr. Yunsup Lee, CTO of SiFive. “We’re excited to continue to co-innovate with Samsung Foundry as we launch our latest SiFive Intelligence products to accelerate the development of next-generation AI SoCs with Samsung’s advanced process technology.”\u003cbr/\u003e\r\n\r\nSiFive’s industry-leading portfolio of RISC-V-based processor Core IP scales from the AI-focused SiFive Intelligence line of Linux-capable 64-bit multi-core processors with enhanced RISC-V Vector capabilities to area-optimized real-time cores. SiFive Core IP is silicon-proven and pre-integrated with SiFive Shield, a whole-SoC security solution, SiFive Insight advanced trace and debug capabilities, and optional SiFive hardware cryptographic accelerator (HCA). Read more information on the latest update for the SiFive 21G1 release on the [SiFive Intelligence](https://www.sifive.com/cores/intelligence) page.\u003cbr/\u003e\r\n\r\nFurther development of the AI accelerator SoC by integrating SiFive Intelligence products into the chip will create a heterogeneous compute platform for machine learning that can be tuned to meet the needs of edge AI, automotive, 5G/networking, or data center accelerator needs.\u003cbr/\u003e\r\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, AI accelerators, and SoC IP to enable domain-specific designs based on the open RISC-V instruction set architecture specification. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\r\n(Remarks) All names of products or services mentioned in this press release are trademarks or registered trademarks of their respective owners.\u003cbr/\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications for SiFive\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e","spans":[]}]}},{"id":"XcnGYhAAACQAFsdV","uid":"aerendir-mobile-inc.-and-sifive-inc.-collaborate-to","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XcnGYhAAACQAFsdV%22%29+%5D%5D","tags":[],"first_publication_date":"2019-11-12T14:00:12+0000","last_publication_date":"2023-05-15T17:49:31+0000","slugs":["aerendir-mobile-inc.-and-sifive-inc.-collaborate-to-accelerate-the-adoption-of-ai-enabled-processors"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Aerendir Mobile Inc. and SiFive Inc. Collaborate to Accelerate the Adoption of AI-Enabled Processors","spans":[]}],"publish_to":"Archive","publish_date":"2019-11-12","share_image":{"link_type":"Media","kind":"image","id":"XcnGdRAAACoAFsew","url":"https://images.prismic.io/sifive/5cb24f59-62ec-42c0-a79f-fd17cfd12f96_sifiveaerendirimage.PNG?auto=compress,format","name":"sifiveaerendirimage.PNG","size":"994419","width":"1444","height":"915"},"body":[{"type":"preformatted","text":"*Use of SiFive’s RISC-V Core IP Enables Low Power AI IoT Edge and End Point Devices*\n\n**SAN MATEO, Calif. – Nov. 12, 2019** - [Aerendir Mobile Inc.](http://www.aerendir.info/) will merge its mathematical deep learning cores and AI infrastructure with innovative [SiFive, Inc.](https://www.sifive.com), RISC-V Core IP to enable a new low-cost board format for deep learning. This combined, unique approach will radically decrease the cost of true AI, allowing it to be enabled at the IoT Edge and End Point, inside affordable devices.\u003cbr/\u003e\n \r\nAerendir and SiFive expect that the IoT market, bolstered by future 5G networks, will require the most cost-effective high-end distributed learning capabilities. As data collection continues to grow and outstrip the ability of datacenters to store, process and analyze new devices at the edge, and end point can help to make accurate machine learning decisions. Local data analysis reduces network congestion and latency, improving local device performance and helping to send important data to the cloud for further analysis. \u003cbr/\u003e\n\r\nAerendir will offer three versions of cloudless, on-device AI: a very high end allowing for high DSP performances, an intermediate and a low-cost one.\u003cbr/\u003e\n\r\n“A user-friendly connected IoT ecosystem requires ultra-smart, low-cost components that can perform adequately without relying on the Ccloud,” said Dr. Martin Zizi, CEO of Aerendir Mobile Inc. “Cloudless connectivity also enforces everyone’s privacy.”\u003cbr/\u003e\n\r\n“The need for custom SoCs designed with deep learning and scalability in mind is a key focus for SiFive,” said Naveed Sherwani, CEO of SiFive. “The potent combination of Aerendir’s IP with SiFive’s configurable RISC-V cores will help to drive the adoption of true AI at IoT edge and end point, where machine learning can benefit both industrial IoT and consumer device functionality.”\u003cbr/\u003e \r\n\u003cbr/\u003e\n**About SiFive**\n\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\r\n**About Aerendir Mobile Inc.**\n\r\nAerendir Mobile Inc. is the developer of a neural tapping technology based on mobile devices that allows for a next-generation AI-powered authentication, identification, encryption and bot segregation platform. Among the first two products available are a foolproof authenticator and a neural anti AI-bot. Aerendir’s products use its patented NeuroPrint® technology to extract a unique proprioceptive signal from micro-vibrational patterns found in the user’s hands, using the existing hardware found in today’s mobile devices. Aerendir’s solution can be embedded in any device or active surface to capture a biometric reading from any muscle in the body. Aerendir’s code can function at all levels of integration from binary libraries, OS and firmware to SoC/ASIC. Aerendir’s biometric technology is designed to put security back in the hands of the individual. For more information, please visit www.aerendir.info.\u003cbr/\u003e\r\n \r\n**Media Contacts**\n\u003cbr/\u003e\nJaShel Jones\u003cbr/\u003e\nKWT Global for Aerendir Mobile Inc.\u003cbr/\u003e\n(646) 989-8149\u003cbr/\u003e\njjones@kwtglobal.com\u003cbr/\u003e\n\u003cbr/\u003e\n\u003cbr/\u003e \r\nLeslie Clavin\u003cbr/\u003e\nSHIFT Communications for SiFive\u003cbr/\u003e\n(415) 591-8440\u003cbr/\u003e\nsifive@shiftcomm.com\u003cbr/\u003e\n\n\r\n","spans":[]}]}},{"id":"X87-IBMAAN2EnUl6","uid":"sifive-wins-3rd-consecutive-title-of-most-respected","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22X87-IBMAAN2EnUl6%22%29+%5D%5D","tags":[],"first_publication_date":"2020-12-08T14:00:04+0000","last_publication_date":"2023-05-15T18:38:01+0000","slugs":["sifive-wins-3rd-consecutive-title-of-most-respected-private-semiconductor-company"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Wins 3rd Consecutive Title of Most Respected Private Semiconductor Company","spans":[]}],"publish_to":"Archive","publish_date":"2020-12-08","share_image":{"link_type":"Media","kind":"image","id":"X877kBMAANX-nT4s","url":"https://images.prismic.io/sifive/6eaf9ef7-1ab6-491e-9f36-f84770227247_Winner2.1.png?auto=compress,format","name":"Winner2.1.png","size":"512193","width":"1080","height":"1080"},"body":[{"type":"preformatted","text":"*RISC-V Leader Recognized by Global Semiconductor Alliance For Developing RISC-V-based IP Solutions to Solve Next-Generation Computing Challenges*\n\n**San Mateo, CA - December 8, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and custom silicon solutions, today announced it has been recognized for the third consecutive year as the Most Respected Private Semiconductor Company by the Global Semiconductor Alliance (GSA) at the [GSA Awards Virtual Dinner](https://www.gsaglobal.org/gsa-announces-its-2020-award-recipients/) on Dec 3rd, 2020. This recognition caps an extraordinary year that generated the highest ever levels of interest in platforms based on RISC-V, driving SiFive’s Series E investment round to secure over $200M total funding to date and enabling further development of innovative new technology.\u003cbr/\u003e\n\nSiFive’s inspiring third consecutive win of the private company award is a testament to the reputation for leadership that SiFive enjoys,” said Jodi Shelton, GSA CEO and Co-Founder. “I’m pleased to see the membership of the GSA continuing to support innovation and opportunity, and recognizing the hard work and dedication of everyone at SiFive.”\r\n“From the beginning, SiFive’s mission has been to bring the power of the RISC-V architecture to the semiconductor industry,” said Patrick Little, President and CEO of SiFive. “This award recognizes that vision and the innovation and execution of the SiFive team as we continue to enable production RISC-V silicon.”\u003cbr/\u003e\r\n\r\nSiFive’s portfolio of processor Core IP is based on the free and open RISC-V instruction set architecture, invented by the founders of SiFive, 10 years ago. Development of the RISC-V ISA and extensions is governed by RISC-V International, in open working groups composed of technology leaders and company representatives. Designed for scalability, SiFive RISC-V-based Core IP can be tailored to individual SoC workload requirements through the award-winning Core Designer tool and focused further using custom instructions.\u003cbr/\u003e\r\n\r\nThe SiFive HiFive boards enable developers to create RISC-V applications and optimize code for the free and open instruction set architecture. The new SiFive HiFive Unmatched board is a Linux-capable development system featuring SiFive 7-Series processor cores, and modern PC form factor and expansion capabilities. Originally specified to feature 8GB DDR4 RAM, the HiFive Unmatched is being updated to include 16GB DDR4 memory, at no increase in price. The HiFive Unmatched board will now ship in mid-Q1 2021 and is available for [pre-order](https://www.sifive.com/boards/hifive-unmatched) now.\u003cbr/\u003e\r\n\r\nSiFive recently announced the SiFive Intelligence VIU7 Linux-capable processor architecture, based on the RISC-V Vector extension to enable a single processing and development environment for scalar and high-performance vector processing applications, such as artificial intelligence, computer vision, and high-performance computing. At the RISC-V Summit 2020, SiFive Chief Architect and co-inventor of RISC-V, Krste Asanovic, will announce details of the new SiFive Intelligence VIS7 processor architecture, based on the silicon-proven SiFive S7 and optimized for deterministic real-time processing platform requirements such as on-device decisions at the edge and end-point. Register for the [RISC-V Summit](https://tmt.knect365.com/risc-v-summit/plan-your-visit/) with code SiFive for a 25% discount on conference or all-access passes with on-demand videos and networking opportunities with the leaders of RISC-V.\u003cbr/\u003e \r\n\r\nThe BBC HiFive Inventor heralds a new educational technology collaboration between BBC Learning, Tynker, and SiFive, culminating in the Doctor Who Coding Kit. The BBC HiFive Inventor is the perfect introduction to learning how to code, for children aged 7 and up. The self-paced, home-based learning environment is powered by the award-winning Tynker software platform and features the voice of the Thirteenth Doctor, Jodie Whitaker, narrating guided instructional courses. For more information or to purchase, please visit [HiFiveInventor.com](https://www.hifiveinventor.com/).\u003cbr/\u003e\r\n\r\nSiFive leaders and experts are attending and presenting at the RISC-V Summit 2020, an online virtual event held on December 8th \u0026 9th. Please visit the virtual SiFive booth at the RISC-V Summit [here](https://tmt.knect365.com/risc-v-summit/sponsors/sifive-2020/) to learn more about SiFive from our experts and also get a chance to win one of two HiFive Unmatched boards in a free sweepstakes drawing. You can hear more from Patrick Little, SiFive CEO and President, about the GSA Award win, [here](https://youtu.be/Wcr_9Qq2CA0).\u003c/br\u003e\r\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\n\r\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e","spans":[]}]}},{"id":"XoT__xEAACMAsXJG","uid":"leading-industry-veteran-joins-sifive-as-chief-financial","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XoT__xEAACMAsXJG%22%29+%5D%5D","tags":[],"first_publication_date":"2020-04-02T13:00:00+0000","last_publication_date":"2023-05-15T18:26:51+0000","slugs":["leading-industry-veteran-joins-sifive-as-chief-financial-officer"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Leading Industry Veteran Joins SiFive as Chief Financial Officer","spans":[]}],"publish_to":"Archive","publish_date":"2020-04-02","share_image":{"link_type":"Media","kind":"image","id":"XoT-jxEAACQAsWvY","url":"https://images.prismic.io/sifive/e677de5d-645a-4739-b92e-5c13293e2928_sifivecfosammaheswari_sm.png?auto=compress,format","name":"sifivecfosammaheswari_sm.png","size":"802894","width":"1200","height":"672"},"body":[{"type":"preformatted","text":"*Tech industry veteran to lead financial operations and drive SiFive growth*\n\n**SAN MATEO, Calif. Apr 2, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Shubham “Sam” Maheshwari has joined the company as Chief Financial Officer (CFO). Maheshwari will lead SiFive financial operations to enable sustainable company growth in support of industry needs and new market opportunities.\u003cbr/\u003e\n\n“SiFive’s idea to silicon methodology and silicon prowess is aligned with the needs of domain-specific accelerators in key growth markets, which is why I’m very excited to join the SiFive team,” said Sam Maheshwari, CFO of SiFive. “There is huge potential for growth and value creation based on smart and passionate people, a leading technology portfolio, and a worldwide footprint. I’m confident we will continue to develop and execute plans for consistent growth.”\u003cbr/\u003e\n\nMaheshwari has 25 years of experience in silicon industry finance, operations, and acquisitions. Before SiFive, he served for 6 years as CFO and later as CFO \u0026 COO of the semiconductor process equipment company Veeco (Nasdaq VECO). Previous notable positions also include SVP, Finance, for Spansion, where he helped lead the company through its restructuring and IPO in 2010. Maheshwari was also VP of mergers and acquisitions for KLA-Tencor and served as Corporate Controller.\u003cbr/\u003e\n\n“We are excited to have Sam join the SiFive team. His operational knowledge and experience are a great fit to our mission of accelerating idea to silicon, enabling the vision of creative thinkers to build spectacular products,” said Dr. Naveed Sherwani, President, and CEO of SiFive. “His impressive reputation for execution and achieving results will ensure our continued growth and success in executing our roadmap.”\u003cbr/\u003e\n\nMaheshwari holds an MBA in Finance from Wharton, and a Bachelors degree in Chemical Engineering from the Indian Institute of Technology, Delhi.\u003cbr/\u003e\n\nSiFive invests in scalable technology and workforce growth to enable [“Idea to Silicon”](https://www.sifive.com/blog/cloud-accelerated-idea-to-silicon) chip design and manufacturing. Most recently, SiFive announced the industry’s first line of RISC-V processor cores with pre-integrated trace and debug capabilities, using [SiFive Insight](https://www.sifive.com/blog/introducing-sifive-insight).\u003cbr/\u003e\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is on a mission to free semiconductor roadmaps and declare silicon independence from the constraints of legacy ISAs and fragmented solutions. As the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all markets to build customized RISC-V based semiconductors. Founded by the inventors of RISC-V, SiFive has 16 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit [www.sifive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\u003c/br\u003e\n\r\n**Media Contact**\r\n\r\nHilary Livingston Castle\u003cbr/\u003e \r\nINK Communications for SiFive\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e \r\n\r\n","spans":[]}]}},{"id":"XhO8ZBMAACIAhWVs","uid":"sifive-and-ceva-partner-to-bring-machine-learning-processors","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XhO8ZBMAACIAhWVs%22%29+%5D%5D","tags":[],"first_publication_date":"2020-01-07T11:00:22+0000","last_publication_date":"2023-05-16T14:05:00+0000","slugs":["sifive-and-ceva-partner-to-bring-machine-learning-processors-to-mainstream-markets"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and CEVA Partner to Bring Machine Learning Processors to Mainstream Markets","spans":[]}],"publish_to":"Archive","publish_date":"2020-01-07","share_image":{"link_type":"Media","kind":"image","id":"XhO3uRMAACMAhVEO","url":"https://images.prismic.io/sifive/686c05e2-fabe-4e31-a5be-aa8b18aecef8_Ceva_SiFive_Banner_Social_PR_200105_v4.jpg?auto=compress,format","name":"Ceva_SiFive_Banner_Social_PR_200105_v4.jpg","size":"584792","width":"1200","height":"628"},"body":[{"type":"preformatted","text":"*Joint silicon development through SiFive’s DesignShare Program combines IP and design strengths of both companies to develop Edge AI SoCs for a range of high-volume end markets including smart home, automotive, robotics, security, augmented reality, industrial and IoT*\n\n**SAN MATEO and MOUNTAIN VIEW, Calif. – Jan. 7th, 2020** – [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions and [CEVA, Inc.](https://www.ceva-dsp.com/) (NASDAQ: CEVA), the leading licensor of wireless connectivity and smart sensing technologies, today announced a new partnership to enable the design and creation of ultra-low-power domain-specific Edge AI processors for a range of high-volume end markets. The partnership, as part of SiFive’s DesignShare program, is centered around RISC-V CPUs, CEVA’s DSP cores, AI processors and software, which will be designed into SoCs targeting an array of end markets where on-device neural networks inferencing supporting imaging, computer vision, speech recognition and sensor fusion applications is required. Initial end markets include smart home, automotive, robotics, security and surveillance, augmented reality, industrial and IoT.\n\n**Machine Learning Processing at the Edge**\u003cbr\u003e\r\nDomain-specific SoCs which can handle machine learning processing on-device are set to become mainstream, as the processing workloads of devices increasingly includes a mix of traditional software and efficient deep neural networks to maximize performance, battery life and to add new intelligent features. Cloud-based AI inference is not suitable for many of these devices due to security, privacy and latency concerns. SiFive and CEVA are directly addressing these challenges through the development of a range of domain-specific scalable edge AI processor designs, with the optimal balance of processing, power efficiency and cost.\n\nThe Edge AI SoCs are supported by CEVA’s award-winning CDNN Deep Neural Network machine learning software compiler that creates fully-optimized runtime software for the CEVA-XM vision processors, CEVA-BX audio DSPs and NeuPro AI processors. Targeted for mass-market embedded devices, CDNN incorporates a broad range of network optimizations, advanced quantization algorithms, data flow management and fully-optimized compute CNN and RNN libraries into a holistic solution that enables cloud-trained AI models to be deployed on edge devices for inference processing. CEVA will also supply a full development platform for partners and developers based on the CEVA-XM and NeuPro architectures to enable the development of deep learning applications using the CDNN, targeting any advanced network, as well as DSP tools and libraries for audio and voice pre- and post-processing workloads.\n\n**SiFive DesignShare Program**\u003cbr\u003e\r\nThe SiFive DesignShare IP program offers a streamlined process for companies seeking to partner with leading vendors to provide pre-integrated premium Silicon IP for bringing new SoCs to market. As part of SiFive’s business model to license IP when ready for mass production, the flexibility and choice of the DesignShare IP program reduces the complexities of contract negotiation and licensing agreements to enable faster time to market through simpler prototyping, no legal red tape, and no upfront payment.\n\n“CEVA’s partnership with SiFive enables the creation of Edge AI SoCs that can be quickly and expertly tailored to the workloads, while also retaining the flexibility to support new innovations in machine learning,” said Issachar Ohana, Executive Vice President, Worldwide Sales at CEVA. “Our market leading DSPs and AI processors, coupled with the CDNN machine learning software compiler, allow these AI SoCs to simplify the deployment of cloud-trained AI models in intelligent devices and provides a compelling offering for anyone looking to leverage the power of AI at the edge.”\n\n“Enabling future-proof, technology-leading processor designs is a key step in SiFive’s mission to unlock technology roadmaps,” said Dr. Naveed Sherwani, president and CEO, SiFive. “The rapid evolution of AI models combined with the requirements for low power, low latency, and high-performance demand a flexible and scalable approach to IP and SoC design that our joint CEVA / SiFive portfolio is superbly positioned to provide. The result is shorter time-to-market, while lowering the entry barriers for device manufacturers to create powerful, differentiated products.”\n\n**Availability**\u003cbr\u003e\r\nSiFive’s DesignShare program, including CEVA-BX Audio DSPs, CEVA-XM Vision DSPs and NeuPro AI processors, is available now. Visit [sifive.com/designshare](https://www.sifive.com/designshare) for more information.\n\n\r\n**About SiFive**\u003cbr\u003e\r\nSiFive is on a mission to free semiconductor roadmaps and declare silicon independence from the constraints of legacy ISAs and fragmented solutions. As the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all markets to build customized RISC-V based semiconductors. Founded by the inventors of RISC-V, SiFive has 16 design centers worldwide, and has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit www.sifive.com.\nStay current with the latest SiFive updates via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\r\n\n**About CEVA, Inc.**\u003cbr\u003e\r\nCEVA is the leading licensor of wireless connectivity and smart sensing technologies. We offer Digital Signal Processors, AI processors, wireless platforms and complementary software for sensor fusion, image enhancement, computer vision, voice input and artificial intelligence, all of which are key enabling technologies for a smarter, connected world. We partner with semiconductor companies and OEMs worldwide to create power-efficient, intelligent and connected devices for a range of end markets, including mobile, consumer, automotive, robotics, industrial and IoT. Our ultra-low-power IPs include comprehensive DSP-based platforms for 5G baseband processing in mobile and infrastructure, advanced imaging and computer vision for any camera-enabled device and audio/voice/speech and ultra-low power always-on/sensing applications for multiple IoT markets. For sensor fusion, our Hillcrest Labs sensor processing technologies provide a broad range of sensor fusion software and IMU solutions for AR/VR, robotics, remote controls, and IoT. For artificial intelligence, we offer a family of AI processors capable of handling the complete gamut of neural network workloads, on-device. For wireless IoT, we offer the industry’s most widely adopted IPs for Bluetooth (low energy and dual mode), Wi-Fi 4/5/6 (802.11n/ac/ax) and NB-IoT. Visit us at [www.ceva-dsp.com](http://www.ceva-dsp.com/) and follow us on [Twitter](http://www.twitter.com/CEVA_IP), [YouTube](https://www.youtube.com/user/cevadsp), [Facebook](https://business.facebook.com/CEVAIP/), [LinkedIn](https://www.linkedin.com/company/ceva) and [Instagram](https://www.instagram.com/ceva_ip/).\r\n\n**MEDIA CONTACTS**\u003cbr\u003e\n\n**CEVA**\u003cbr\u003e\nRichard Kingston\u003cbr\u003e\nCEVA, Inc.\u003cbr\u003e\n650-417-7976\u003cbr\u003e\nmailto:richard.kingston@ceva-dsp.com\u003cbr\u003e\n\u003cbr\u003e\nSimon Flatt\u003cbr\u003e\nPublitek for CEVA\u003cbr\u003e\n+44 20 8869 9229\u003cbr\u003e\nsimon.flatt@publitek.com\u003cbr\u003e\n\n**SIFIVE**\u003cbr\u003e\nHilary Livingston Castle\u003cbr\u003e\nINK Communications for SiFive\u003cbr\u003e \n203-858-7259\u003cbr\u003e \nsifive@ink-co.com\u003cbr\u003e\n","spans":[]}]}},{"id":"XqnzWBMAACIAze1e","uid":"sifive-joins-open-covid-pledge-to-fight-global-pandemic","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XqnzWBMAACIAze1e%22%29+%5D%5D","tags":[],"first_publication_date":"2020-04-30T13:00:06+0000","last_publication_date":"2023-05-15T18:17:32+0000","slugs":["sifive-joins-open-covid-pledge-to-fight-global-pandemic"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Joins Open COVID Pledge to Fight Global Pandemic","spans":[]}],"publish_to":"Archive","publish_date":"2020-04-30","share_image":{"link_type":"Media","kind":"image","id":"XnK7-xEAACEAix5n","url":"https://images.prismic.io/sifive/f9bd6f75-b658-4835-af07-73a89cbfe438_sifive-insight-thumb.jpg?auto=compress,format","name":"sifive-insight-thumb.jpg","size":"14789","width":"700","height":"394"},"body":[{"type":"preformatted","text":"*The idea-to-silicon company pledges free SiFive E21 Standard Core for use in healthcare products*\n\n**SAN MATEO, Calif. Apr 30, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced it has taken the Open COVID Pledge, offering the SiFive E21 Standard Embedded Processor Core free of charge for use in ending the COVID-19 pandemic and minimizing the impact of the disease. Potential applications include use in control systems for healthcare products such as ventilators and other life-saving equipment. SiFive joins other leading companies in the fight against COVID-19 by offering intellectual property free of charge to accelerate the rapid development and deployment of diagnostics, vaccines, therapeutics, medical equipment, and software solutions.\u003cbr/\u003e \r\n\r\n“At SiFive, we believe making custom silicon more accessible is key to innovation, and that holds now more than ever,” said Dr. Naveed Sherwani, SiFive President and CEO. “By providing the SiFive E21 Standard Core IP to companies addressing COVID-19, our goal is to remove business and technological barriers. We’re encouraging our customers and partners to join us in making this pledge. Together, through technology, we can minimize the virus’s spread and ultimately save lives.”\u003cbr/\u003e\r\n\r\nSiFive’s mission is to help democratize access to custom silicon, improving quality, and reducing time to market. Since its founding in 2015, SiFive has been fostering accelerated innovation through open-source contributions . The company has pledged the SiFive E21 Standard Core, a high-performance, full-featured embedded processor core designed to address efficient microcontroller applications, which will help in manufacturing healthcare products such as ventilators.\u003cbr/\u003e\r\n\r\nThe Open COVID Pledge calls on organizations around the world to make their patents and copyrights freely available in the fight against the COVID-19 pandemic. The Pledge was developed by the Open COVID Coalition, an international group of scientists and lawyers seeking to accelerate the rapid development and deployment of diagnostics, vaccines, therapeutics, medical equipment and software solutions in this urgent public health crisis.\r\nLearn more at [https://opencovidpledge.org/](https://opencovidpledge.org). \r\nFor more information on using the SiFive E21 Standard Core IP in a design under the terms of the COVID-19 pledge, please visit [SiFive.com](https://www.sifive.com/contact-sales).\u003cbr/\u003e\n\r\n**About SiFive**\u003cbr/\u003e\r\nSiFive is on a mission to free semiconductor roadmaps and declare silicon independence from the constraints of legacy ISAs and fragmented solutions. As the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all markets to build customized RISC-V based semiconductors. Founded by the inventors of RISC-V, SiFive has 16 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit [www.sifive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\u003c/br\u003e\n\r\n**Media Contact**\r\n\r\nHilary Livingston Castle\u003cbr/\u003e \r\nINK Communications for SiFive\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e \r\n","spans":[]}]}},{"id":"Xa_3XxAAACAAoTUs","uid":"sifive-announces-new-sifive-shield-for-modern-soc-design","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Xa_3XxAAACAAoTUs%22%29+%5D%5D","tags":[],"first_publication_date":"2019-10-23T20:30:00+0000","last_publication_date":"2023-05-15T18:06:13+0000","slugs":["sifive-announces-new-sifive-shield-for-modern-soc-design"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Announces New SiFive Shield For Modern SoC Design","spans":[]}],"publish_to":"Archive","publish_date":"2019-10-23","share_image":{"link_type":"Media","kind":"image","id":"Xa_mzBAAAB8AoOwv","url":"https://images.prismic.io/sifive%2Feb594e74-4063-4bfa-84ce-d0f79fe04291_sifive_shield_metal_wordmark.png?auto=compress,format","name":"SiFive_Shield_Metal_WordMark.png","size":"219128","width":"512","height":"562"},"body":[{"type":"preformatted","text":"*Linley Fall Processor Conference Presentation Details New SiFive IP For Secure SoC Designs*\n\n**SAN MATEO, Calif. - October 23rd, 2019** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP, today announced the release of SiFive Shield, a class-leading new platform security architecture. Introduced at the Linley Fall Processor Conference, the industry’s premier processor event, SiFive Director of Security Dany Nativel detailed the new SiFive Shield and SiFive WorldGuard solutions for designing and implementing security in modern SoCs. \r\n\r\n**SiFive Shield**\n\nSiFive Shield is an innovative new approach to SoC design, offering a whole SoC approach to security that enables secure lifecycle management, reduces trusted computing base, and offers a clear root-of-trust. Modern SoC designs require scalable security architectures with greater isolation than today’s offerings to ensure continuous protection. With fine-grain controls and system-level security the SiFive Shield open platform architecture enables a secure SoC that utilizes an auditable software stack to ensure trustability. The SiFive Shield platform offers FIPS verified true random number generation (TRNG), fault detectors and secure cryptographic engines. \r\n\r\n**SiFive WorldGuard**\n\nSiFive WorldGuard is a hardware-enforced fine-grain security model for isolated code execution and data protection. Multiple domains or worlds with configurable privileges inside each world offer SoC level information control with advanced isolation control, enabling data protection across multiple cores and other bus masters found in modern SoCs.\r\n\r\n**Securing The RISC-V Revolution**\n\nThe rapid growth of intelligent IoT devices for Edge and End Point requires a modern SoC solution unencumbered with legacy design choices, able to offer fine-grain control and scale across multiple cores. SiFive Shield delivers on this modern requirement, with a low trusted computing base while keeping full compatibility with RISC-V ISA. \r\n\r\nSiFive Shield enables secure lifecycle management with secure key generation, storage, and provisioning, to enable full lifecycle security. Open source secure boot with open source development software stack ensures trust in application development. Key elements of SiFive Shield are externally and/or community evaluated to ensure trust and operation. \r\n\r\n“The introduction of the new SiFive Shield security solution is a pivotal moment for SiFive, and the RISC-V Industry,” said Naveed Sherwani, CEO, SiFive. “The availability of best-in-class security that is a scalable and configurable security solution and replaces legacy solutions with a modern, forward-thinking design enables SiFive to continue to win IP and SoC designs. SiFive partners and customers will be able to implement modern security principles into their next generation products to ensure data protection and trusted execution in the critical IoT, Automotive, and Data Center accelerator markets.” \r\n\n**About SiFive**\n\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [www.sifive.com](https://www.sifive.com).\r\n\n**MEDIA CONTACTS**\n\nSara Dodrill \nSHIFT Communications for SiFive \n415-591-8429 \nsdodrill@shiftcomm.com","spans":[]}]}},{"id":"XfBFSBEAAFDyIlH7","uid":"industry-veteran-randy-allen-joinssifiveas-vice-president","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XfBFSBEAAFDyIlH7%22%29+%5D%5D","tags":[],"first_publication_date":"2019-12-11T14:00:00+0000","last_publication_date":"2023-05-15T18:16:10+0000","slugs":["industry-veteran-randy-allen-joinssifiveas-vice-president-of-risc-v-software"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Industry Veteran Randy Allen Joins SiFive as Vice President of RISC-V Software","spans":[]}],"publish_to":"Archive","publish_date":"2019-12-11","share_image":{"link_type":"Media","kind":"image","id":"Xer65hEAAFDyCyZL","url":"https://images.prismic.io/sifive/eb1ba5b3-2c51-47fa-bc25-79aba9d4cee1_randy-allen-bio.jpg?auto=compress,format","name":"randy-allen-bio.jpg","size":"197019","width":"612","height":"612"},"body":[{"type":"preformatted","text":"*SiFive’s new hire brings unparalleled experience in vectorization*\n\n**SAN MATEO, Calif. - Dec 11, 2019** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Randy Allen has joined the company as vice president of RISC-V software. Dr. Allen will be responsible for developing and implementing RISC-V software strategy for SiFive.\u003cbr/\u003e \r\n \r\n“I met the SiFive founders while teaching at Berkeley some years ago,” said Allen. “It was clear even then that RISC-V and SiFive were going to be special, once-in-a-lifetime events. I’m excited to join the SiFive team and spearhead software strategy for this revolutionary technology.”\u003cbr/\u003e\r\n \r\nAllen brings more than 30 years of industry experience and, most recently, served as vice president of software engineering at Wave Computing. He has also served in leadership roles at tech companies such as Mentor Graphics, National Instruments and Cypress Semiconductor.\u003cbr/\u003e\r\n \r\n“Randy’s expertise in everything from embedded software design and development to high performance computing makes him an obvious choice for the role,” said Dr. Naveed Sherwani, president and CEO of SiFive. “His skill in the development of vectorizing and parallelizing compilers is world-class and will be instrumental in the future of SiFive.”\u003cbr/\u003e \r\n \r\nAllen earned an artium baccalaureus degree in Chemistry from Harvard University and a PhD in Mathematical Sciences from Rice University. Today, at the RISC-V Summit, Randy Allen will deliver the current state of the union of RISC-V software at 12:50 p.m. PST at the San Jose Convention Center in Grand Ballroom 220-C.\u003cbr/\u003e \r\n\nSiFive is a Ruby sponsor of the RISC-V Summit 2019, and is participating in more than a dozen presentations over the three days of the public conference. Attendees can visit the SiFive booth to discover more about the latest IP, products, partnerships, and a chance to meet with the inventors of RISC-V.\u003c/br\u003e \r\n\r\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [www.sifive.com](htttps://www.sifive.com).\u003cbr/\u003e\r\nStay current with the latest SiFive updates via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\u003cbr/\u003e\r\n\n**Media Contact**\u003c/br\u003e\r\nSara Dodrill\u003cbr/\u003e\r\nSHIFT Communications for SiFive\u003cbr/\u003e\r\n(415) 591-8429\u003cbr/\u003e\r\nsifive@shiftcomm.com\u003cbr/\u003e\r\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqq","uid":"sifive-secures-8-5-million-series-b-funding-to-advance-risc-v-based-semiconductors","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqq%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2023-05-15T14:30:13+0000","slugs":["sifive-secures-8.5-million-series-b-funding-to-advance-risc-v-based-semiconductors"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Secures $8.5 Million Series B Funding to Advance RISC-V Based Semiconductors","spans":[]}],"publish_to":"Archive","publish_date":"2017-05-08","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN FRANCISCO – May 8, 2017\u003c/span\u003e – [SiFive](https://www.sifive.com), the first fabless provider of customized, open-source-enabled semiconductors, today announced it has raised $8.5 million in a Series B round led by Spark Capital with participation from Osage University Partners and existing investor Sutter Hill Ventures. This Series B round brings the total investment in SiFive to $13.5 million. The funding comes as SiFive experiences a growing demand for RISC-V IP and increased interest in custom silicon.\n\nSiFive was founded by the inventors of RISC-V – Krste Asanovic, Yunsup Lee and Andrew Waterman – with a mission to democratize access to custom silicon. In its first six months of availability, more than 1,000 HiFive1 software development boards have been purchased and delivered to developers in over 40 countries. Additionally, the company has engaged with multiple customers across its IP and SoC products, started [shipping the industry’s first RISC-V SoC](/press/sifive-introduces-industrys-first-open-source-chip-platforms) in November 2016 and announced the [availability of its Coreplex RISC-V based IP](/press/sifive-launches-cpu-ip-industry-into-the-cloud-with-new-risc-v-cores-and-an-easy-online-business-model) earlier this month.\n\n“At Spark Capital, we believe technology is the great equalizer. SiFive’s singular goal of putting custom chips into the hands of everyone from startups to exploratory design teams to inventors with a healthy crowdfunding campaign resonates with our core values,” said Todd Dagres, general partner at Spark Capital, who will join the SiFive board of directors. “We are excited at the potential for SiFive to enable new and emerging sectors to bring innovative solutions to market that might otherwise never see the light of day.”\n\nRISC-V has developed a strong ecosystem of more than 60 companies including Google, HPE, Microsoft, IBM, Qualcomm, NVIDIA, Samsung, Microsemi and others. Member companies, as well as third-party open-source contributors, are actively contributing to a maturing stable of software and toolchains, including GCC and binutils, both of which have been upstreamed. SiFive maintains an easy to install toolchain, SDK and BSPs with binaries of the latest open source tools, including OpenOCD, GNU Debugger, Arduino IDE and the Eclipse integrated development environment. More updates are expected at the [6th RISC-V Workshop](https://riscv.org/2017/03/6th-risc-v-workshop-registration-and-call-for-papers/) this week in Shanghai.\n\nThis Series B financing comes amid a string of significant milestones for SiFive in the past year:\n\n- **Product Innovation:** SiFive launched its Freedom Everywhere platform – designed for microcontroller, embedded, IoT and wearable applications – and its Freedom Unleashed platform – for machine learning, storage and networking applications – in July 2016. At the 5th RISC-V Workshop in November, SiFive announced general availability of the Freedom Everywhere 310 (FE310) SoC and the HiFive1 software development board.\n- **Industry Recognition:** SiFive was recognized as the Startup of the Year by the 2016 ACE Awards. Its contributions to the open source community were noted by the Linley Group’s Analyst Choice Awards, which named RISC-V its Technology of the Year for 2016. Additionally, the seminar computer architecture textbook, “Computer Organization and Design,” has been updated to include RISC-V in the latest edition, which was released in April.\n- **Customer Adoption:** Earlier this month, SiFive launched its Coreplex IP and announced a growing ecosystem of partners, including Faraday, Microsemi and United Design Systems, making SiFive Coreplex IP available to their downstream customers.\n- **Company Growth:** SiFive’s employee base has grown more than 280 percent to support the development of its Freedom Everywhere and Freedom Unleashed SoCs, as well as the launch of its E31 and E51 Coreplex IPs. SiFive’s leadership team continues to grow with key engineers from Altera, ARM, Atmel, Cadence Design Systems, Cisco, Intel, Juniper, Marvell, Nvidia Qualcomm, Synopsys and Xilinx.\n\n“We are energized by the partnerships we have forged with our investors and their strong belief in SiFive’s mission,” said Jack Kang, vice president of product and business development at SiFive. “This investment will enable our continued growth for years to come, and will allow SiFive to further establish that alternatives really matter in an era where traditional silicon vendors no longer are the most innovative in the industry.”\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Krste Asanovic, Yunsup Lee and Andrew Waterman, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit [www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W9kcdRAAACcAURBY","uid":"sifive-core-ip-7-series-creates-new-class-of-embedded","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W9kcdRAAACcAURBY%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-31T13:27:49+0000","last_publication_date":"2023-05-15T15:04:46+0000","slugs":["sifive-core-ip-7-series-creates-new-class-of-embedded-intelligent-devices-powered-by-risc-v"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Core IP 7 Series Creates New Class of Embedded Intelligent Devices Powered by RISC-V","spans":[]}],"publish_to":"Archive","publish_date":"2018-10-31","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"_Newly unveiled features and continued RISC-V investment in domain-specific architectures enable innovations in 5G, networking, storage, artificial intelligence and sensor fusion_\n\n\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Oct. 31, 2018\u003c/a\u003e – [SiFive](https://www.sifive.com/), the leading provider of commercial RISC-V processor IP, today announced the availability of the SiFive Core IP 7 Series, the highest performance commercially available RISC-V cores. The 7 Series product family is designed to enable embedded intelligence with features that have not been commercially available until today. The 7 Series includes the E7, S7 and the U7 series. SiFive Core IP provides a truly heterogenous, customizable architecture that provides customers with the ability to flexibly combine E, S and U cores within a single coherent core complex. Together, the SiFive E7, S7 and U7 Core IP Series will enable the next generation of RISC-V cores that will power 5G, networking, storage, augmented reality, virtual reality, artificial intelligence, simultaneous location and mapping (SLAM), and sensor fusion functionality.\n\n\u0026quot;The SiFive Core IP 7 Series represents a major advancement in RISC-V. The 7 Series brings features to market that have been in-demand but unavailable to customers. SiFive offers the broadest portfolio of RISC-V Core IP with the most power efficient and highest performance cores,\u0026quot; said Jack Kang, VP of Product Marketing, SiFive. \u0026quot;The 7 Series is our latest innovation that will allow designers to achieve higher efficiency by tailoring their core to the characteristics of their domain – from the smallest edge devices to the data center.\u0026quot;\n\nThe E7 Core IP Series comprises the 32-bit E76 and E76-MC and provides hard real-time capabilities. The SiFive Core IP S7 Series brings high performance 64-bit architectures to the embedded markets with the S76 and S76-MC. The SiFive Core IP U7 Series is a Linux-capable applications processor with a highly configurable memory architecture for domain-specific customization. The 64-bit U74 and U74-MC, like all SiFive U cores, fully support Linux, while the E76, E76-MC, S76 and S76-MC support bare metal environments and real-time operating systems. All new cores offer efficient performance and optimized power consumption, appropriate for supporting smart offloads of data center workloads as well as those of extremely power-efficient edge devices. The U74-MC provides 64-bit addressability for real-time, latency sensitive applications such as 5G baseband processing, enterprise-class storage for fast or big data and multi-mode sensor fusion for AR/VR/SLAM applications.\n\n\u0026quot;We selected SiFive Core IP due to its best-in-class performance as it was one-third the power and one-third the area of competing solutions,\u0026quot; said Jihyo Lee, co-founder and CEO, FADU. \u0026quot;As we target our next generation of advanced memory products, we look forward to seeing SiFive\u0026#39;s 7 Series Core IP bringing truly heterogenous architectures, customizable 64-bit capability and intelligence to the embedded space.\u0026quot;\n\nThe SiFive 7 Series provides a compelling feature set that includes scalable throughput provided by 8+1 cores per cluster, 64-bit memory addressability for real-time processors and in-cluster coherent combination of real-time processors and application processors. These features are currently not available from any other CPU IP vendor and are unique to SiFive\u0026#39;s Core IP series. The SiFive 7 Series also includes enhanced determinism for hard, real-time constraints and functional safety provided through a combination of built-in fault tolerance mechanisms. The 7 series is designed on a highly optimized 8-stage in-order pipeline, which introduces microarchitectural features to prevent side channel attacks thereby enabling a robust and secure processor implementation.\n\n\u0026quot;We are pushing the throughput and performance limits of latency-sensitive standards and devices,\u0026quot; said Yonghua Song, CEO, Bouffalo. \u0026quot;SiFive\u0026#39;s E7 allows us to maximize embedded performance. SiFive\u0026#39;s 7 Series of Core IP is an important step forward with powerful new features. The flexibility and extensibility of their cores allow us to optimize our architecture and complements our use of their E24.\u0026quot;\n\nFor more information on SiFive\u0026#39;s RISC-V Core IP including full datasheets, specifications and app notes, visit [https://www.sifive.com/core-designer](https://www.sifive.com/core-designer).\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom, Western Digital and Intel Capital. For more information, visit [www.sifive.com.](https://www.sifive.com/)\n\n## Contact:\n\u003caddress\u003e\nJamie Feller\u003cbr\u003e\nSHIFT Communications for SiFive\u003cbr\u003e\n\u003ca href=\"mailto:sifive@shiftcomm.com\"\u003esifive@shiftcomm.com\u003c/a\u003e\u003cbr\u003e\n(415) 591-8432\n\u003c/address\u003e","spans":[]}]}},{"id":"X1BJfBMAACQAzRqW","uid":"sifive-and-barcelona-supercomputing-center-advance","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22X1BJfBMAACQAzRqW%22%29+%5D%5D","tags":[],"first_publication_date":"2020-09-03T13:00:05+0000","last_publication_date":"2023-05-15T18:25:45+0000","slugs":["sifive-and-barcelona-supercomputing-center-advance-industry-adoption-of-risc-v-vector-extension"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and Barcelona Supercomputing Center Advance Industry Adoption of RISC-V Vector Extension","spans":[]}],"publish_to":"Archive","publish_date":"2020-09-03","share_image":{"link_type":"Media","kind":"image","id":"X1BIARMAACQAzRQF","url":"https://images.prismic.io/sifive/e827cc82-20f0-435f-895e-7fdb8572c8f8_SiFive-rvvapi-pr-social.png?auto=compress,format","name":"SiFive-rvvapi-pr-social.png","size":"83389","width":"1000","height":"561"},"body":[{"type":"preformatted","text":"*The new API adds critical capabilities to widely used compilers, GCC \u0026 LLVM*\n\n**SAN MATEO, Calif. Sep 3, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced several new updates to their leading RISC-V portfolio in the areas of security, and vector processing. In collaboration with the Barcelona Supercomputing Center, SiFive created an API for vector intrinsics for popular open-source compilers GCC, and LLVM. Additionally, SiFive reports that the SiFive Shield Hardware Cryptographic Accelerator (HCA) true random number generator (TRNG) has successfully passed conformance evaluation to SP 800-90B standard, to enable FIPS 140 certified security solutions.\u003cbr/\u003e\n\n**RISC-V Vector Processing**\u003cbr/\u003e\nThe new API will speed up the development of vector processor applications using RISC-V processor cores with RISC-V Vector Extension (RVV) 1.0 support, such as the upcoming SiFive Intelligence line of products. The API is available on [GitHub](https://github.com/riscv/rvv-intrinsic-doc) now and will be upstreamed to GCC and LLVM compilers once the RVV specification is ratified. SiFive previously added upstream support for the RISC-V ISA to GCC in 2017, and expects to continue to work with the RISC-V community to ensure the API is aligned to the final RVV 1.0 specification. Learn more about SiFive’s open-source contributions for RISC-V Vectors in our blog, [here](https://www.sifive.com/blog/risc-v-vector-extension-intrinsic-support).\u003cbr/\u003e\n\n“The RISC-V Vector extension will enable new RISC-V based processor designs to accelerate many workloads, from AI to signal processing and scientific research,” said Chris Lattner, President of Platform Engineering, SiFive. “With the integration of support for intrinsics in popular compilers, the RISC-V community is enabled to create efficient, scalable hardware and software solutions to address modern computing challenges.”\u003cbr/\u003e\n\n**SiFive Shield SoC-level Security**\u003cbr/\u003e\r\nThe SiFive Shield Hardware Cryptographic Accelerator (HCA) was introduced in the recent [SiFive 20G1](https://www.sifive.com/blog/sifive-core-ip-20g1) release in July, enabling the acceleration of cryptographic functions used to securely boot an SoC, protect communications, and restrict access to the debug interface. The SiFive HCA IP block includes a 100% digital true random number generator (TRNG) that has successfully passed a conformance evaluation against the stringent NIST SP-800-90B recommendation for entropy sources used for random bit generation. Learn more about SiFive Shield HCA in our blog, [here](https://www.sifive.com/blog/randomness-is-secure-with-sifive-shield-hca).\r\n\r\nSiFive will release more updates to its RISC-V-based Core IP portfolio in October, with enhanced performance for the SiFive 7-Series range of U-, S-, and E-Series processor cores. These updates will improve performance in Artificial Intelligence workloads where data streaming performance is important, and be deployed to all customers using the [award-winning](https://www.elektraawards.co.uk/elektraawards2020/en/page/2019-winners) SiFive Core Designer automatically.\r\n\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK hynix, Intel Capital, and Western Digital. For more information, please visit [www.sifive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\n\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\n\r\n\n\n","spans":[]}]}},{"id":"XNsHyREAACcAlft1","uid":"powervr-gpu-and-nna-available-on-sifive-platform","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XNsHyREAACcAlft1%22%29+%5D%5D","tags":[],"first_publication_date":"2019-05-14T19:31:32+0000","last_publication_date":"2023-05-15T14:35:53+0000","slugs":["powervr-gpu-and-nna-available-on-sifive-platform"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"PowerVR GPU and NNA available on SiFive platform","spans":[]}],"publish_to":"Archive","publish_date":"2019-05-14","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"_Imagination Technologies joins SiFive\u0026#39;s DesignShare Ecosystem, Enabling RISC-V users to access industry-leading IP_\n\n**London, UK and San Mateo, California - 13th May 2019** - [Imagination Technologies](http://www.imgtec.com/) announces that it has joined [SiFive\u0026#39;s](https://www.sifive.com) [DesignShare](https://www.sifive.com/designshare) ecosystem, giving system designers easy access to its industry-leading PowerVR GPU and neural network accelerator (NNA) IP cores. The PowerVR GPU will be the first fully-featured GPU supporting the Vulkan® applications programming interface (API) available via the DesignShare ecosystem.\r\n\r\nDesignShare reduces the upfront costs of acquiring IP for System-on-Chip (SoC) prototyping. Imagination\u0026#39;s PowerVR Series8XE GPU and PowerVR Series3NX NNA IP will be available for customers to use in their DesignShare SoCs, with the expectation of further Imagination IP being made available in the future to meet market demand. PowerVR\u0026#39;s integrated GPU and NNA software stack will enable customers to achieve the very best performance and flexibility. The PowerVR software has been designed to work with all processor architectures, including the rapidly-growing, open-standard RISC-V that is at the heart of the SiFive DesignShare ecosystem.\r\n\r\nNeal Forse, senior director of product management, PowerVR, Imagination, says: \u0026quot;Joining SiFive\u0026#39;s DesignShare ecosystem was an easy decision for Imagination. We understand the challenges customers can face when it comes to designing new SoCs and welcome the innovative approach created by SiFive to address these challenges. By joining DesignShare, we will help customers overcome barriers and ultimately enable them get to market quicker with pioneering products.\u0026quot;\r\n\r\nDesignShare provides efficient and pre-integrated IP solutions that make SoC prototyping more accessible to companies and teams of all sizes.\r\n\r\nMohit Gupta, vice president, SoC IP solutions, strategy and business development, SiFive; says: \u0026quot;We\u0026#39;re delighted to welcome Imagination into the DesignShare movement. Imagination is renowned for its industry-leading GPU IP and award-winning NNA IP. PowerVR\u0026#39;s support of APIs such as Vulkan, OpenCL™, Android NNAPI, and SYCL will deliver new opportunities for customer growth for the ecosystem. Together, we hope to inspire customers to challenge the norm and develop groundbreaking custom silicon. We\u0026#39;re excited to see the creativity that our collaboration inspires.\u0026quot;\r\n\r\nThe PowerVR GPU and NNA IP is available now through the DesignShare program. For more information, contact [info@imagination.com](mailto:info@imagination.com) or [sales@sifive.com](mailto:sales@sifive.com).\r\n\r\nImagination is co-hosting and delivering a keynote presentation at the SiFive Tech Symposium in Cambridge on Monday 13th May. For information, please visit [sifivetechsymposium.com/agenda-cambridge/](https://sifivetechsymposium.com/agenda-cambridge/)\r\n\r\n**About SiFive**\r\n\r\nSiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit [www.sifive.com](https://www.sifive.com).\r\n\r\n**About Imagination Technologies**\r\n\nImagination is a global technology leader whose products touch the lives of billions of people across the globe. The company\u0026#39;s range of silicon IP (intellectual property) includes key processing blocks needed to create the SoCs (Systems on Chips) that power all mobile, consumer and embedded electronics. Its unique multimedia, vision \u0026amp; AI, and connectivity technologies enable its customers to get to market quickly with complete and differentiated SoC platforms. Imagination\u0026#39;s licensees include many of the world\u0026#39;s leading semiconductor manufacturers, innovative start-ups and OEMs/ODMs who are creating the world\u0026#39;s most iconic products. See [www.imgtec.com](http://www.imgtec.com).\r\n\r\nFollow Imagination on [Twitter](https://twitter.com/ImaginationTech), [YouTube](http://www.youtube.com/imgtec), [LinkedIn](http://www.linkedin.com/company/imagination-technologies), [RSS](http://www.imgtec.com/pressrelease-rss.asp), [Facebook](https://www.facebook.com/imgtec) and [Blog](http://imgtec.com/blog).\r\n\r\nImagination, PowerVR and the Imagination Technologies logo are trademarks of Imagination Technologies Limited and/or its affiliated group companies in the United Kingdom and/or other countries. Vulkan is a registered trademark and OpenCL is a trademark of the Khronos Group. All other logos, products, trademarks and registered trademarks are the property of their respective owners.\r\n\r\nImagination Technologies was acquired in 2017 by Canyon Bridge, a California-headquartered, global private equity investment fund.\r\n\r\n\r\n\r\n**Imagination Technologies\u0026#39;s Press Contacts:**\n\nDavid Harold \n[david.harold@imgtec.com](mailto:david.harold@imgtec.com) \n+44 (0)1923 260 511\n\r\nJo Ashford \n[jo.ashford@imgtec.com](mailto:jo.ashford@imgtec.com) \n+44 (0)1923 260511\n\r\n**SiFive\u0026#39;s Press Contacts:**\r\n\r\nJack Kang \n[jack@sifive.com](mailto:jack@sifive.com) \n(510) 673-1309\n\r\nStephanie Chan \n[sifive@shiftcomm.com](mailto:sifive@shiftcomm.com) \n(646) 756-3713","spans":[]}]}},{"id":"XxeERhUAACQAWUBI","uid":"sifive-elevates-custom-soc-design-with-enhanced-processor","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XxeERhUAACQAWUBI%22%29+%5D%5D","tags":[],"first_publication_date":"2020-07-22T15:00:03+0000","last_publication_date":"2023-05-15T18:35:26+0000","slugs":["sifive-elevates-custom-soc-design-with-enhanced-processor-ip-portfolio"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Elevates Custom SoC Design With Enhanced Processor IP Portfolio","spans":[]}],"publish_to":"Archive","publish_date":"2020-07-22","share_image":{"link_type":"Media","kind":"image","id":"XxeC7RUAACUAWTpb","url":"https://images.prismic.io/sifive/d08b53f3-23d1-44bf-8b45-26e85984f9a8_072220-SiFive-CoreIP-20G1-PR.png?auto=compress,format","name":"072220-SiFive-CoreIP-20G1-PR.png","size":"97339","width":"1200","height":"676"},"body":[{"type":"preformatted","text":"*The SiFive 20G1 release delivers up to 2.8x more performance(1); up to 25% lower power(2); and up to 11% smaller area(3), for designing next-generation SoCs*\n\n**SAN MATEO, Calif. July 22, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced a comprehensive update to SiFive’s RISC-V Core IP portfolio with the public availability of the SiFive 20G1 release. The SiFive Core IP portfolio is a broad range of microarchitectures that scale from high-performance application processors, for running Linux-based applications or real-time deterministic workloads, to low-power microcontrollers focused on efficiency. SiFive Core IP is developed in partnership with customer requirements that include pre-integrated SiFive Insight, for advanced trace and debug capabilities, and SiFive Shield, for whole-SoC security.\u003cbr/\u003e\r\n\r\n“This release combines our roadmap enhancements with feedback from industry-leading customers to extend our leadership in RISC-V processor IP,” said Dr. Yunsup Lee, co-inventor of RISC-V and CTO of SiFive. “Our intent is always to deliver the best customer experience combined with a winning product portfolio, and the 20G1 release upholds that promise.”\u003cbr/\u003e\r\n\r\nSiFive RISC-V processor cores enable the creation of domain-specific heterogeneous SoCs, based on SiFive U-Series, S-Series, and E-Series Core IP. SiFive U-Series 64-bit processors are Linux-capable and multi-core ready, enabling high-performance core complexes for use in storage, networking, and AI inference processing applications. In this release, the SiFive U7-Series has increased load bandwidth up to 2.8x for memory-intensive workloads such as AI inference processing(1). The SiFive 20G1 release also delivers lower power in the entire portfolio, with the SiFive U74 standard core running at up to 25% lower power(2).\u003cbr/\u003e\r\n\r\nSiFive S-Series 64-bit processors and E-Series 32-bit processors are designed for real-time embedded applications, area-optimized for low power. Combining SiFive’s RISC-V processor cores to create heterogeneous multi-core complexes using domain-specific architectures for AI, aerospace, automotive, IoT, mobile, networking, storage, or vision applications. SiFive E-Series processors are now available with the RISC-V Embedded extension, RV32E, to deliver significant area saving with the SiFive E3-Series measuring up to 11% smaller area than previous versions.\u003cbr/\u003e \r\n\r\nSiFive Core IP seamlessly integrates into mixed-ISA designs with native Arm® CoreSight™ compatibility, enabling developers to leverage their existing software development environment. The suite of SiFive Freedom Tools has been updated to support the SiFive 20G1 release, offering a comprehensive suite of SDKs, compilers, libraries, and code examples to accelerate adoption and use of SiFive RISC-V processor Core IP.\u003cbr/\u003e \r\n\r\n“SiFive’s leadership and talent in RISC-V are demonstrated in the quality and breadth of our products,” said Dr. Naveed Sherwani, Chairman, President \u0026 CEO of SiFive. “SiFive’s customers return because of our winning product portfolio and our great CX team to help develop new products quickly and efficiently.”\u003cbr/\u003e\r\n\r\nThe SiFive 20G1 release is now available through the award-winning SiFive Core Designer to simplify the selection and configuration of RISC-V cores for domain-specific architecture designs. The full details of the SiFive 20G1 release are available in our launch blog here.\u003cbr/\u003e\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is on a mission to free semiconductor roadmaps and declare silicon independence from the constraints of legacy ISAs and fragmented solutions. As the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all markets to build customized RISC-V based semiconductors. Founded by the inventors of RISC-V, SiFive has 16 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003c/br\u003e\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\n\r\n**Media Contact**\u003cbr/\u003e\r\n\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e \r\nINK Communications for SiFive\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e \r\n\n(1) - 2.8x higher performance based on SiFive internal engineering measurement of improving performance in memory-intensive workloads running on a SiFive U7-Series processor core\u003cbr/\u003e\n(2) - 25% lower power based on SiFive internal engineering measurement of SiFive U74 processor (20G1) core power consumed while running Dhrystone benchmark as compared to SiFive U74 processor (19.08)\u003cbr/\u003e\n(3) - 11% area reduction based on SiFive internal engineering measurement of SiFive E3-Series area using RISC-V Embedded extension RV32E in 28nm process technology vs. RV32I.\u003cbr/\u003e\nArm and CoreSight are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.\u003cbr/\u003e\n \r\n","spans":[]}]}},{"id":"Xe_k8xEAAKbkIKlB","uid":"lattice-and-sifive-announce-collaboration-to-allow","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Xe_k8xEAAKbkIKlB%22%29+%5D%5D","tags":[],"first_publication_date":"2019-12-11T21:00:00+0000","last_publication_date":"2023-05-15T18:39:03+0000","slugs":["lattice-and-sifive-announce-collaboration-to-allow-lattice-fpga-developers-easy-access-to-risc-v-processors"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Lattice and SiFive Announce Collaboration to Allow Lattice FPGA Developers Easy Access to RISC-V Processors","spans":[]}],"publish_to":"Archive","publish_date":"2019-12-11","share_image":{"link_type":"Media","kind":"image","id":"Xe_hwBEAAFDyIJtN","url":"https://images.prismic.io/sifive/49d12fcd-1772-4c67-a2ab-26110ae6dd1e_Lattice_Logo_Color_TransparentBG.png?auto=compress,format","name":"Lattice_Logo_Color_TransparentBG.png","size":"26547","width":"1809","height":"367"},"body":[{"type":"preformatted","text":"*Scalable Processor Core IP Running on Low Power, Small Form Factor FPGAs Could Power Millions of Smart Devices at the Edge*\n\n**SAN MATEO, Calif. – Dec. 11th, 2019** – [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, and [Lattice Semiconductor Corporation](http://www.latticesemi.com/) (NASDAC: LSCC), the low power programmable leader, today announced they have agreed to collaborate to enable easy availability of SiFive scalable Core IP for developers using Lattice FPGA product families, including Lattice’s new 28 nm CrossLink-NX™ FPGAs.\u003cbr/\u003e\n \r\nThe need for intelligent processing at the Edge and endpoint is increasing, with new AI/ML applications in industrial, automotive, and consumer IoT being developed to reduce latency, power, and cost. Performing AI/ML processing outside of the data center reduces bandwidth and privacy concerns while increasing responsiveness through lower latency. These factors combine to drive the increasing need for embedded intelligence in an anticipated more than 64 billion new devices* at the Edge and endpoint in the coming decade. Lattice low power FPGAs utilizing SiFive RISC-V implementations are well-positioned to create embedded solutions that enable a smart, secure, and connected world.\u003cbr/\u003e\r\n\r\n**Enabling Low Power Solutions**\u003cbr/\u003e\r\n\nSiFive’s scalable approach to processor core design enables Lattice to create application targeted Core IP, focused on the features and performance requirements of the workload. Lattice and SiFive plan to collaborate on delivering new, optimized processor cores using SiFive IP based on the free and open RISC-V ISA. SiFive E2 Core IP will power Lattice FPGA solutions for a diverse array of use cases and markets, from control plane processing in communications infrastructure to data path processing in Edge applications.\u003cbr/\u003e\n\r\n“Lattice is pleased to be collaborating with SiFive to enable easy customer access to the SiFive Core IP on our small form factor, low power FPGAs,” said Esam Elashmawi, Chief Marketing \u0026 Strategy Officer, Lattice Semiconductor. “SiFive’s flexible and scalable RISC-V based Core IP running on our FPGAs will provide developers with a compelling hardware solution for emerging applications such as embedded vision and AI processing on Edge devices.”\u003cbr/\u003e\r\n\r\n“The collaboration with Lattice is a great moment for SiFive,” said Dr. Naveed Sherwani, President \u0026 CEO of SiFive. “The simple and rapid creation of smart new products requires a flexible solution to scalable IP design that SiFive is perfectly positioned to provide. The ability for Lattice FPGAs to support RISC-V applications is expected to drive the production of millions of innovative, efficient solutions.”\u003cbr/\u003e\r\n\r\n**About SiFive**\u003cbr/\u003e\r\n\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com. You can also follow SiFive via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured). \u003cbr/\u003e\r\n\r\n**About Lattice Semiconductor**\r\n\nLattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world.\u003cbr/\u003e\r\n\r\nFor more information about Lattice, please visit [www.latticesemi.com](http://www.latticesemi.com/?pr111419). You can also follow Lattice via [LinkedIn](), [Twitter](https://cts.businesswire.com/ct/CT?id=smartlink\u0026url=https%3A%2F%2Fwww.linkedin.com%2Fcompany%2Flattice-semiconductor%2F\u0026esheet=51928388\u0026newsitemid=20190122005135\u0026lan=en-US\u0026anchor=LinkedIn\u0026index=3\u0026md5=690203317c56bc93cf209085b1316116), [Facebook](https://cts.businesswire.com/ct/CT?id=smartlink\u0026url=https%3A%2F%2Ftwitter.com%2Flatticesemi\u0026esheet=51928388\u0026newsitemid=20190122005135\u0026lan=en-US\u0026anchor=Twitter\u0026index=4\u0026md5=475870b4663a6b680bb3f72c676c01ae), [YouTube](https://cts.businesswire.com/ct/CT?id=smartlink\u0026url=https%3A%2F%2Fwww.youtube.com%2Fuser%2Flatticesemiconductor\u0026esheet=51928388\u0026newsitemid=20190122005135\u0026lan=en-US\u0026anchor=YouTube\u0026index=6\u0026md5=b4f944c76a78d166da1d57d75d006c81), [WeChat](https://cts.businesswire.com/ct/CT?id=smartlink\u0026url=http%3A%2F%2Fwww.latticesemi.com%2FAbout%2FNewsroom%2FWeChat\u0026esheet=51928388\u0026newsitemid=20190122005135\u0026lan=en-US\u0026anchor=WeChat\u0026index=7\u0026md5=5f50374bdc657024dfa79bfe93e76df5), [Weibo](https://cts.businesswire.com/ct/CT?id=smartlink\u0026url=https%3A%2F%2Fwww.weibo.com%2Flatticesemi%3Fis_all%3D1\u0026esheet=51928388\u0026newsitemid=20190122005135\u0026lan=en-US\u0026anchor=Weibo\u0026index=8\u0026md5=e8bba7e4ad3d76c464ad4fea3d829a35) or [Youku](https://cts.businesswire.com/ct/CT?id=smartlink\u0026url=http%3A%2F%2Fi.youku.com%2Flatticesemi\u0026esheet=51928388\u0026newsitemid=20190122005135\u0026lan=en-US\u0026anchor=Youku\u0026index=9\u0026md5=5ccf5a926515f60603ff2777c13745de).\r\n\r\nLattice Semiconductor Corporation, Lattice Semiconductor (\u0026 design) and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. The use of the word “partner” does not imply a legal partnership between Lattice and any other entity.\u003cbr/\u003e\r\n\n*General Notice*\u003cbr/\u003e\r\nOther product names used in this publication are for identification purposes only and may be trademarks of their respective holders.\u003cbr/\u003e\n\r\n**Media Contact**\u003cbr/\u003e\r\nSara Dodrill\u003cbr/\u003e\r\nSHIFT Communications for SiFive\u003cbr/\u003e \r\nPhone: 415-591-8429\u003cbr/\u003e\r\nsifive@shiftcomm.com\u003cbr/\u003e\r\n\r\nBob Nelson\u003cbr/\u003e\r\nLattice Semiconductor\u003cbr/\u003e\r\nPhone: 408-826-6339\u003cbr/\u003e\r\nBob.Nelson@latticesemi.com\u003cbr/\u003e\r\n\r\nInvestor Contact\u003cbr/\u003e\r\nRick Muscha\u003cbr/\u003e\r\nLattice Semiconductor\u003c/br\u003e\r\nPhone: 408-826-6000\u003cbr/\u003e\r\nRick.Muscha@latticesemi.com\u003cbr/\u003e\r\n\r\n/* Semico forecasts strong growth for RISC-V, predicting the market will consume 62.4 billion RISC-V CPU cores by 2025 - [RISC-V Foundation](https://riscv.org/2019/11/9679/)\r\n","spans":[]}]}},{"id":"Xis0qxIAACIAbN6G","uid":"former-google-and-tesla-engineer-chris-lattner-to-lead","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Xis0qxIAACIAbN6G%22%29+%5D%5D","tags":[],"first_publication_date":"2020-01-27T14:01:05+0000","last_publication_date":"2023-05-15T18:33:37+0000","slugs":["former-google-and-tesla-engineer-chris-lattner-to-lead-sifive-platform"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Former Google and Tesla Engineer Chris Lattner to Lead SiFive Platform ","spans":[]}],"publish_to":"Archive","publish_date":"2020-01-27","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Distinguished Silicon Valley software engineer to bring increased customization and implementation tooling to SiFive SoC design methodology*\n\n**SAN MATEO, Calif., Jan. 27, 2020** – [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Chris Lattner, a distinguished Silicon Valley software engineer, has joined the company to lead SiFive Platform Engineering as SVP. Lattner brings 15 years of leadership in software engineering and machine learning infrastructure, leading teams at Apple, Tesla, and most recently, Google. He is credited for authoring Clang, the compiler front-end, and LLVM, the compiler infrastructure open source project.\u003cbr/\u003e\r\n\r\n“I’m thrilled to be joining the SiFive team and for the opportunity to work with a company that is enabling the future of silicon, all the way from idea to silicon,” said Lattner. “RISC-V offers an exciting opportunity for customizable chips, and SiFive’s RISC-V design methodology is unmatched in the industry. By making custom SoC development more accessible, we can accomplish technological breakthroughs that couldn’t happen anywhere else.” \r\n\r\nLattner has a reputation for engineering excellence. During a decade-long stint with Apple, he spearheaded the creation of Swift, the programming language used to build the current generation of iPhone, iPad, Apple Watch, Mac, and Apple TV apps. As the driving force behind the influential LLVM and Clang projects that brought speed, safety, portability, and power to developers by providing scalable frameworks to programmatically generate machine native code, and with additional contributions to Tesla Autopilot and Google TPU, Lattner is set to evolve and enhance SiFive’s scalable engineering capabilities as part of SiFive’s mission to simplify the enablement of designing custom cores and SoCs.\r\n\r\n“SiFive is on a mission to democratize access to custom silicon, and innovative leaders in the industry are taking notice,” said Dr. Naveed Sherwani, president and CEO of SiFive. “Chris has made significant contributions to the software used by millions of developers today. This is a significant period of strategic growth for us, and we are thrilled to welcome Chris to our product engineering practice.”\r\n\r\nSiFive enables the configuration and production of domain-specific hardware to suit software optimized solutions. Most recently, the company announced a partnership with CEVA to simplify the creation of processors capable of supporting smart home, automobile, robotics, IoT, and industrial applications. \r\n\r\nLattner holds a Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign and a bachelor’s degree in Computer Science from the University of Portland. Read his introductory blog post, [With SiFive, We Can Change the World](/blog/with-sifive-we-can-change-the-world).\r\n\r\n**About SiFive**\u003cbr/\u003e\r\nSiFive is on a mission to free semiconductor roadmaps and declare silicon independence from the constraints of legacy ISAs and fragmented solutions. As the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all markets to build customized RISC-V based semiconductors. Founded by the inventors of RISC-V, SiFive has 16 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit [www.sifive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\r\n\r\nMedia Contact\r\n\r\nHilary Livingston Castle\u003cbr/\u003e \r\nINK Communications for SiFive\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e \r\n","spans":[]}]}},{"id":"XBKSXRAAACYAaEid","uid":"sifive-recognized-as-most-respected-private-semiconductor","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XBKSXRAAACYAaEid%22%29+%5D%5D","tags":[],"first_publication_date":"2018-12-13T17:17:13+0000","last_publication_date":"2023-05-15T14:37:25+0000","slugs":["sifive-recognized-as-most-respected-private-semiconductor-company"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Recognized as Most Respected Private Semiconductor Company","spans":[]}],"publish_to":"Archive","publish_date":"2018-12-11","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*RISC-V leader honored for its products, growth and performance by\nGlobal Semiconductor Alliance*\n\n**SAN MATEO, Calif. — Dec. 11, 2018 —**\n[SiFive](https://www.sifive.com), the leading provider of commercial\nRISC-V processor IP, today announced it has been recognized as the 2018\nMost Respected Private Semiconductor Company by the Global Semiconductor\nAlliance (GSA) at the GSA awards dinner on Dec. 6, 2018. This\nrecognition caps a momentous year for the company, in which SiFive has\nexperienced unprecedented growth.\n\n\"SiFive's unique model makes it one of the most exciting and\nrevolutionary emerging companies in the industry today and accordingly\ntheir peers have chosen them as the Most Respected Private Semiconductor\nCompany,\" said Jodi Shelton, GSA President. \"The GSA is proud to honor\nthem with this award which is a recognition of their leadership in the\nRISC-V ecosystem and its innovative cloud-based design platform. We\nlook forward to their continuous leadership in pushing open hardware to\naddress the burgeoning global opportunities.\" \n\nThe GSA Most Respected Private Semiconductor Company award honors\ncompanies that garner the most respect from the industry in terms of its\nproducts, vision and future opportunities. Since its founding in 2015,\nSiFive has grown its Core Series IP to seven distinct 32- and 64-bit\nproduct lines, suitable for use in real-time, embedded and high end,\nlinux application use cases. At the RISC-V Summit earlier this month,\nmore than 10 SiFive partners showcased [a wide array of prototypes and\ndemo devices](https://www.youtube.com/watch?v=jNnCok1H3-g). The company\nalso has grown from its core founding employees to more than 300 people,\nand established a robust set of partnerships including TSMC, Cadence and\nMicrosoft. In total, SiFive recently secured significant double-digit\ndesign wins across their Core IP 2, 3, 5, and 7 Series. Of those, over\n10 design wins alone were for their highly successful E2 Core IP Series.\nSiFive will be announcing further details in the coming weeks.\n\n\"To be honored by the GSA as the most respected privately held company\nin the industry less than three years after our launch is quite\nrewarding,\" said Naveed Sherwani, CEO, SiFive. \"This industry\nrecognition is a rewarding validation of SiFive's mission to lead the\nparadigm shift under way in the silicon industry as it looks for the\nnext wave of innovation. I am so proud of our team for their efforts to\npush the boundaries of what's possible every day.\"\n\n**About SiFive**\n\nSiFive is the leading provider of market-ready processor core IP,\ndevelopment tools and silicon solutions based on the free and open\nRISC-V instruction set architecture. Led by a team of seasoned silicon\nexecutives and the RISC-V inventors, SiFive helps SoC designers reduce\ntime-to-market and realize cost savings with customized,\nopen-architecture processor cores, and democratizes access to optimized\nsilicon by enabling system designers in all market verticals to build\ncustomized RISC-V based semiconductors. Located in Silicon Valley,\nSiFive has backing from Sutter Hill Ventures, Spark Capital, Osage\nUniversity Partners, Chengwei, Huami, SK Hynix, Intel Capital, and\nWestern Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n**About GSA**\n\nGSA is Where Leaders Meet to establish an efficient, profitable and\nsustainable semiconductor and high technology global ecosystems\nencompassing semiconductors, software, solutions, systems, and services.\nIt is a leading industry organization that provides a unique neutral\nplatform for collaboration, where global executives interface and\ninnovate with peers, partners and customers to accelerate industry\ngrowth and maximize return on invested and intellectual capital.\n\nGSA has an impressive global footprint representing over 30 countries\nand 350 corporate members comprised of top companies in the\nsemiconductor industry. The global membership ranges from the most\nexciting emerging companies to industry stalwarts and technology\nleaders—representing 75% of industry revenues. Members value\ncollaboration as a key to the advancement of their companies and\nindustry.\n\nGSA offers the broadest and most efficient thought-leadership platform\nthrough curated regional and global executive and technology events,\nnetworking forums, dinners, workshops and working groups. These\ngatherings allow members to engage in thought leading dialogues shaping\nthe industry, expand business opportunities and remain up-to-date on\nrelevant topical issues, share best practices and gain precious\nvisibility opportunities. GSA members also have access to a repository\nof data and information including financial reports and resources,\ncompany data, surveys and technology and market reports.\n\nTo learn more about the GSA please visit: [https://www.gsaglobal.org/](https://www.gsaglobal.org/)\n\n**MEDIA CONTACTS**\n\nJamie Feller\u003cbr\u003e\nSHIFT Communications for SiFive\u003cbr\u003e\n415-591-8432\u003cbr\u003e\n[sifive@shiftcomm.com](mailto:sifive@shiftcomm.com)","spans":[]}]}},{"id":"XsLpOBMAACAAawnY","uid":"sifive-partners-with-coherent-logix-for-milaero-processor","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XsLpOBMAACAAawnY%22%29+%5D%5D","tags":[],"first_publication_date":"2020-05-19T13:00:04+0000","last_publication_date":"2023-05-15T18:11:46+0000","slugs":["sifive-partners-with-coherent-logix-for-mission-critical-processor-solutions","sifive-partners-with-coherent-logix-for-milaero-processor-solutions"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Partners With Coherent Logix for Mission-Critical Processor Solutions","spans":[]}],"publish_to":"Archive","publish_date":"2020-05-19","share_image":{"link_type":"Media","kind":"image","id":"XsLpChMAACIAawkM","url":"https://images.prismic.io/sifive/98949c6e-0b94-4d59-9249-7ea1c173a0d6_sifive-coherentlogix-social.png?auto=compress,format","name":"sifive-coherentlogix-social.png","size":"632389","width":"897","height":"600"},"body":[{"type":"preformatted","text":"*SiFive Core IP Enables Market-Leading Applications for Military and Aerospace Markets*\n\n**SAN MATEO, Calif. May 19, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that [Coherent Logix](https://www.coherentlogix.com/) has chosen SiFive Core IP to complement its HyperX™ memory network processor for its next-generation solutions targeting mission-critical markets. Coherent Logix performed a comparison of CPU IP available in the market based on requirements of the military and aerospace customers and selected SiFive IP that enabled very low Size, Weight, Area, and Power (SWAP) of the overall solution.\u003cbr/\u003e \r\n\r\n“SiFive Core IP enabled us to quickly design a HyperX™ architecture-based customized solution which met the target platform requirements,” said Michael Doerr, CEO of Coherent Logix. “SiFive’s flexible business model enabled a seamless engagement for us while offering market-leading SWAP for our end customer.”\u003cbr/\u003e\r\n\r\nThe Coherent Logix HyperX™ Platform provides the tools and libraries needed to solve mission-critical problems in multiple disciplines, including hyperspectral and multispectral image/data fusion, software-defined radio, synthetic aperture radar, portable sensor systems, remote sensor platforms, surveillance receivers, anti-jam Global Positioning System, automatic target recognition and threat cueing, ad-hoc networking, and secure data transmission. The Coherent Logix HyperX™ platform features a large library of supported waveforms and delivers these capabilities in a low-power, high-performance environment.\u003cbr/\u003e\r\n\r\nSiFive’s Custom Instruction Extension feature accelerates domain-specific workloads, a key requirement for military and aerospace customers. SiFive has an extensive IP portfolio that can be used for solutions with SWAP constraints. In comparison to other solutions in the market, SiFive provides high-performance solutions with half to third of the power of competitor solutions(1). SiFive Core IP deterministic real-time processing capabilities support low latency mission-critical workloads.\u003cbr/\u003e \r\n\r\n“We are pleased to partner with Coherent Logix on their next-generation design for mission-critical markets,” said Dr. Naveed Sherwani, CEO of SiFive. “The SiFive Core IP portfolio complements CLX HyperX processor technology perfectly to create a scalable, low power, high-performance solution for mission-critical applications.”\u003cbr/\u003e\r\n\r\nLearn more about SiFive Core IP [here](https://www.sifive.com/risc-v-core-ip).\u003c/br\u003e\r\n\r\n**About CLX**\u003cbr/\u003e\r\nCoherent Logix, Incorporated (“Company”) is a world leader in low-power, high-performance, programmable processors for embedded systems markets. Coherent Logix’s comprehensive portfolio of solutions includes processors, integrated system development tools, optimized libraries, system reference designs, and a customizable system development platform that reduces development complexity and time to market. Our solutions support a wide variety of industries, Military/Aerospace, TV, Computer Vision, 5G, and IoT home markets.\u003c/br\u003e\r\n\r\nLinkedin: [https://www.linkedin.com/company/coherent-logix-inc-](https://www.linkedin.com/company/coherent-logix-inc-)\u003cbr/\u003e\r\nTwitter: [https://twitter.com/CoherentLogix](https://twitter.com/CoherentLogix)\u003cbr/\u003e\r\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is on a mission to free semiconductor roadmaps and declare silicon independence from the constraints of legacy ISAs and fragmented solutions. As the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all markets to build customized RISC-V based semiconductors. Founded by the inventors of RISC-V, SiFive has 16 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003c/br\u003e\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\n\r\n**Media Contact**\u003cbr/\u003e\r\n\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e \r\nINK Communications for SiFive\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e \r\n\n**Coherent Logix**\u003c/br\u003e\nHailie Sieven\u003c/br\u003e\n631.449.0750\u003c/br\u003e\nsieven@coherentlogix.com\u003c/br\u003e\n\n1 - Based on SiFive internal estimates of SPEC Int/GHz per Watt, and Power/mm2 of SiFive Core IP with L2$ vs competitor processor core implementation in 16nm process technology","spans":[]}]}},{"id":"XZIUkxEAACAAyoB0","uid":"sifive-signs-dts-insight-as-official-distributor-to","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XZIUkxEAACAAyoB0%22%29+%5D%5D","tags":[],"first_publication_date":"2019-09-30T16:56:04+0000","last_publication_date":"2023-05-11T20:23:31+0000","slugs":["sifive-signs-dts-insight-as-official-distributor-to-japan"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Signs DTS INSIGHT as Official Distributor to Japan","spans":[]}],"publish_to":"Archive","publish_date":"2019-09-24","share_image":{"link_type":"Media","kind":"image","id":"XZITTxEAACAAynse","url":"https://images.prismic.io/sifive%2F2be3cb1a-b703-496f-9952-3184fc471704_dts-insight_japan_sifive.png?auto=compress,format","name":"DTS-Insight_Japan_SiFive.PNG","size":"454194","width":"866","height":"1235"},"body":[{"type":"preformatted","text":"*DTS INSIGHT expands into Semiconductor Market with SiFive IP and tools*\n\n**SAN MATEO, Calif. – September 24th, 2019** – [SiFive, Inc.](https://www.sifive.com/), the leading provider of commercial RISC-V processor IP and silicon solutions, announced today that leading embedded platform software development provider DTS INSIGHT has formed a new business group in partnership with SiFive to provide RISC-V IP and tools to the Japanese market.\n\n\r\nWith this new agreement, semiconductor designers in Japan will have access to SiFive IP and tools, enabling the next generation of silicon solutions to be created. SiFive’s powerful portfolio of RISC-V IP and silicon IP enables modern SoCs to be rapidly designed with a focus on application-specific use cases. DTS INSIGHT’s proven reputation for excellence of in-circuit emulator (ICE), embedded software development and migration services makes it perfectly positioned to enable the development of new products based on SiFive IP, and assist in the software stack transition for existing product lines migrating to RISC-V based designs. \r\n\n\nAs the next billion devices extending the IoT are designed, area, efficiency and performance are top of mind for leading semiconductor companies. SiFive’s proven IP on popular and leading process technology nodes – combined with the scalable, configurable SiFive Core IP microarchitecture range – provides a wide choice for next-generation application-specific processor design.\r\n\n\n“DTS INSIGHT’s proven success in software development and migration makes them the perfect choice to extend SiFive’s opportunities in Japan,” said Naveed Sherwani, CEO of SiFive. “We are very pleased to announce DTS INSIGHT as the SiFive distributor to Japan and truly appreciate its investment in offering local engineering and FAE resources to support SiFive’s growth.”\r\n\n\n\"The broad portfolio of IP from SiFive is well-suited to the Japanese market,” said Isao Asami, president of DTS INSIGHT. “Combined with the excellent software development and support offered by DTS INSIGHT, I am very excited to begin driving the design of next-generation products using our combined strengths.”\r\n\n\nConnect in person with RISC-V leaders SiFive and others at the upcoming [RISC-V Day](https://riscv.org/2019/08/risc-v-day-tokyo/) in Tokyo on Monday, Sept. 30 at Hitachi BABA Memorial Hall. \r\n\n\n**About SiFive**\r\n\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.\r\n\r\n## MEDIA CONTACTS\r\n\r\nSara Dodrill \nSHIFT Communications for SiFive \n415-591-8429 \nsdodrill@shiftcomm.com ","spans":[]}]}},{"id":"Y1a2QRAAAB4ArDCc","uid":"sifive-and-synopsys-collaborate-to-accelerate-soc-design","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Y1a2QRAAAB4ArDCc%22%29+%5D%5D","tags":[],"first_publication_date":"2022-10-25T13:00:03+0000","last_publication_date":"2022-10-25T13:00:03+0000","slugs":["sifive-and-synopsys-collaborate-to-accelerate-soc-design"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and Synopsys Collaborate to Accelerate SoC Design","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-10-25","share_image":{"link_type":"Media","kind":"image","id":"YyHYRhIAACAARvdW","url":"https://images.prismic.io/sifive/e57b86a2-9225-4be7-a9f3-260d6d654ad5_blog-card-only-logo.png?auto=compress,format","name":"blog-card-only-logo.png","size":"264063","width":"780","height":"440"},"body":[{"type":"preformatted","text":"**New Synopsys Fusion QuickStart Implementation Kits Deliver Enhanced Power, Performance and Area for SiFive RISC-V Processors**\r\n\r\nSANTA CLARA, Calif. and MOUNTAIN VIEW, Calif., October 25, 2022 – SiFive and Synopsys, Inc. (Nasdaq: SNPS) today announced their new collaboration to accelerate the design and verification of SiFive RISC-V processor-based SoCs. The collaboration provides mutual customers with Synopsys Fusion QuickStart Implementation Kits (QIKs) that optimize the power, performance and area (PPA) of SiFive’s Intelligence™ X280 and Performance™ P550 processor cores. Synopsys Fusion QIKs for SiFive processors leverage the Synopsys Fusion Compiler™ RTL-to-GDSII product and Synopsys Design Space Optimization (DSO.ai™), which autonomously explores multiple design spaces to enhance PPA metrics. By using the implementation scripts and reference guides included in the QIKs, designers can accelerate the development of their SiFive processor-based SoCs. \r\n\r\n“As we push the performance of application-specific processors, our collaboration with Synopsys enables us to deliver higher quality, PPA-optimized RISC-V solutions that meet and beat our customers’ compute goals,” said Yunsup Lee, co-founder and CTO at SiFive. “Synopsys has early access to SiFive’s processors under development, enabling the companies co-optimize the processors and Synopsys’ tools. This collaboration delivers Synopsys Fusion QIKs for mutual customers to quickly achieve their challenging design targets for their specific application requirements. We look to extend our collaboration to include verification flows, as well as Foundation and Interface IP.” \r\n\r\n“The trend towards application-specific silicon is helping to address the intensive compute demands of advanced high-performance systems,” Sanjay Bali, vice president of Marketing and Strategy for the EDA Group at Synopsys. “Our collaboration with SiFive to provide Synopsys Fusion QIKs enables designers to achieve the optimal quality-of-results for their custom RISC-V-based SoCs.”\r\n\r\nFusion QIKs for SiFive X280 and P550 processors are available for download today through Synopsys SolvNetPlus.\r\n\r\nCollaborating to Achieve Design Targets Quickly and Confidently \r\nIn addition to the Fusion QIKs, SoC designers using SiFive RISC-V processors can take advantage of key Synopsys technologies, including:\r\n•\tThe Synopsys Digital Design Family, which provides a framework to achieve optimum PPA across all leading technology processes via a shared engine for implementation, test and signoff of power-optimized architectures for SiFive cores. •\tThe family also includes Synopsys Silicon Lifecycle Management Family optimization software, which enables SiFive users to quickly find the best configurations of their software stack to maximize performance of SiFive cores.\r\n•\tThe Synopsys Verification Family, which speeds software development, verification throughput and time-to-market for SiFive based designs, including virtual prototyping with models of SiFive’s cores, simulation, formal verification, hardware and software debug, emulation, FPGA prototyping and verification IP.\r\n•\tThe silicon-proven Synopsys Interface IP products for the most widely used protocols, which deliver the required low latency, high performance, power efficiency and security for data-intensive systems implementing the latest SiFive processor cores. \r\n\n**About Synopsys**\n\r\nSynopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As an S\u0026P 500 company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and offers the industry's broadest portfolio of application security testing tools and services. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing more secure, high-quality code, Synopsys has the solutions needed to deliver innovative products. Learn more at www.synopsys.com. \r\n\r\n**About SiFive** \r\n\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit SiFive.com.\r\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\n**Editorial Contacts:**\n\t\t\t\t\t\t\r\nDavid Miller\r\nSiFive, Inc.\r\n‭(408) 425-2820‬‬‬‬‬‬‬‬‬\r\ndavid.miller@sifive.com\r\n\r\nSimone Souza \r\nSynopsys, Inc.\r\n650-584-6454\r\nsimone@synopsys.com\r\n\r\n\r\n###\r\n\r\n","spans":[]}]}},{"id":"Y5gfnBAAAB8A4ZeB","uid":"sifive-delivers-record-growth-in-2022-with-fast-growing","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Y5gfnBAAAB8A4ZeB%22%29+%5D%5D","tags":[],"first_publication_date":"2022-12-13T22:40:44+0000","last_publication_date":"2022-12-13T22:40:44+0000","slugs":["sifive-delivers-record-growth-in-2022-with-fast-growing-roster-of-new-customers-and-products"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Delivers Record Growth in 2022 with Fast-Growing Roster of New Customers and Products ","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-12-13","share_image":{"link_type":"Media","kind":"image","id":"Y5j6lBAAAB8A5S2B","url":"https://images.prismic.io/sifive/0e38fd4a-c176-4547-b585-f852c1d4104f_Patrick+and+Bob.jpg?auto=compress,format","name":"Patrick and Bob.jpg","size":"10303685","width":"6048","height":"4024"},"body":[{"type":"preformatted","text":"**Highlights leadership in RISC-V and proven performance and power density benefits**\r\n\r\n**San Jose, Calif., Dec. 13, 2022** – At the [RISC-V Summit](https://events.linuxfoundation.org/riscv-summit/) today, [SiFive, Inc.](https://www.sifive.com), the founder and leader of RISC-V computing, celebrated its impressive year of growth and technical achievements. In 2022 SiFive announced collaborations with some of the world’s largest chip companies and hyperscale datacenters, as the company has been laser-focused on expanding growth. Today SiFive has design wins with more than 100 customers, including 8 of the top 10 semiconductor companies, in applications including automotive, AR/VR, client computing, datacenter, and the intelligent edge. This year the company rolled out new products for a range of fast-growing and high-volume markets, including a comprehensive automotive portfolio, and expanded its presence globally. This momentum was recognized last week when SiFive was awarded the prestigious 2022 Most Respected Private Semiconductor Company Award by the Global Semiconductor Alliance [GSA](https://www.gsaglobal.org/2022awd/).\r\n\r\n“This was a standout year for SiFive, as we collaborated with some of the biggest companies on the planet to tackle their unmet needs, shifted our portfolio and revenues from embedded to high performance RISC-V products that are shaking up the industry, and expanded our global footprint,” said Patrick Little, CEO and Chairman at SiFive. “With the fast-paced growth of SiFive and rapidly increasing demand for our products, and the overall growth of the RISC-V ecosystem, as we’ve said before, the future of RISC-V ‘has no limits’ as we take the company to new heights.”\r\n\r\nSiFive has made incredible technical progress over the last year, rolling out several products with unparalleled compute performance and efficiency. The new SiFive Performance™ P670 and P470 RISC-V processors raise the bar for innovative designs in high volume applications like wearables, smart home, industrial automation, AR/VR, and other consumer devices. The company introduced its SiFive Automotive™ E6-A, X280-A, and S7-A solutions to address critical needs for current and future applications like infotainment, cockpit, connectivity, ADAS, and electrification. Plus, SiFive enhanced its popular SiFive Intelligence™ X280 processor IP to meet the accelerated demand for vector processing, especially for AI and ML applications.\r\n\r\nThe company has continued to deepen its collaborations and partnerships as it works to transform the future of compute and define what comes next. Through partnership with Microchip, SiFive is a part of NASA’s next generation High-Performance Spaceflight Computing (HPSC) processor, which delivers a 100x increase in computational capability to help propel next-generation planetary and surface missions. Additionally, the X280 processor with the new SiFive Vector Coprocessor Interface Extension (VCIX) is being used as the AI Compute Host to provide flexible programming in a leading datacenter. SiFive also announced its work with companies including BrainChip, Kinara (Deep Vision), Synopsys, and ProvenRun, as well as a broad set of OS, Software Tools, and EDA ecosystem processors for the SiFive Automotive Family of processors\r\n\r\nAnother big milestone for SiFive is the company’s partnership with Intel to spark innovation in high-performance RISC-V platforms. SiFive is supporting Intel Foundry Services (IFS) Innovation Fund’s goal to build innovative new multi-ISA computing platforms including RISC-V platforms optimized for Intel process technology. The IFS Innovation fund will support the creation of disruptive technologies to address modern computing challenges, with the Intel-SiFive collaboration aiming to extend the RISC-V ecosystem. At the show, the companies unveiled more details about the HiFive Pro P550 Development System (code named Horse Creek); this high-performance development system will enable the RISC-V ecosystem to productively create software when it is commercially available later in 2023. \n![Patrick Little and Bob Brennan of Intel show off the new Hi-Five Pro P550 development board](https://images.prismic.io/sifive/0e38fd4a-c176-4547-b585-f852c1d4104f_Patrick+and+Bob.jpg?auto=compress,format) \r\n\r\nSiFive’s stellar growth, technical achievements, and partnerships have been recognized by prestigious organizations. In addition to the recent GSA Awards recognition, SiFive was awarded a 2022 TSMC Open Innovation Platform® (OIP) Partner of the Year award. Additionally, SiFive ranked in the top 10 percent of Inc.’s fastest growing private companies in America list.\r\n\r\nTo meet the strong customer demand for SiFive’s innovative RISC-V IP, SiFive has expanded its headcount to more than 550 employees and has opened new offices around the world, including a Research \u0026 Development (R\u0026D) Center in Cambridge, United Kingdom, a design center in Bangalore, India, and a new office in Hyderabad, India.. \r\n\r\nAt the RISC-V Summit, taking place from Dec. 12-15 in San Jose, Calif. and virtually, SiFive is presenting in more than 10 sessions, including a keynote on Dec. 13 at 10:35 a.m. PT with SiFive’s CEO Patrick Little: “RISC-V Spotlight: Delivering on Real-World Customer Challenges.” To learn more about SiFive’s business, stop by the SiFive booth in the RISC-V Summit Expo Hall.\r\n\r\n**About SiFive**\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit SiFive.com.\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\n**Media Contact**\r\nAllison DeLeo\r\nRacepoint Global for SiFive\r\nSiFive@racepointglobal.com\r\nTel.: +1(415) 694-6711\r\n \r\nDavid Miller\r\nCorporate Communications\r\nSiFive\r\nDavid.Miller@sifive.com\r\n","spans":[]}]}},{"id":"Y2Lw-xAAAB0A4VF_","uid":"sifive-awarded-tsmc-open-innovation-platform-partner","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Y2Lw-xAAAB0A4VF_%22%29+%5D%5D","tags":[],"first_publication_date":"2022-11-02T22:45:10+0000","last_publication_date":"2022-11-02T22:45:10+0000","slugs":["sifive-awarded-tsmc-open-innovation-platform-partner-of-the-year"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Awarded TSMC Open Innovation Platform Partner of the Year","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-11-02","share_image":{"link_type":"Media","kind":"image","id":"Y2LwgBAAAHMd4U9h","url":"https://images.prismic.io/sifive/5c87f5a5-bcef-47c0-a88c-915bc3fdd2f4_Yunsup+Receiving+TSMC+Partner+of+the+Year+Award.jpg?auto=compress,format","name":"Yunsup Receiving TSMC Partner of the Year Award.jpg","size":"279455","width":"801","height":"1298"},"body":[{"type":"preformatted","text":"**Santa Clara, Calif., November 3, 2022** - [SiFive, Inc.](https://www.sifive.com) the founder and leader of RISC-V computing, today announced it has received the 2022 TSMC Open Innovation Platform® (OIP) Partner of the Year award, in the Emerging IP Company category. Dr. L.C Lu, TSMC fellow and vice president of design and technology platform, presented the distinguished award to SiFive executives at the recent TSMC 2022 OIP Ecosystem Forum in Santa Clara, CA. The recognition reflects the ongoing innovation and collaboration between the two companies that is furthering the momentum of RISC-V.\r\n\r\nThe Partner of the Year award honors TSMC OIP ecosystem partners' pursuit of excellence in next-generation silicon enablement over the past year.\r\n\r\n“OIP Partner of the Year award-winning companies work relentlessly to achieve the highest standards of design, development, and technology implementation to accelerate silicon innovation,” said Dan Kochpatcharin, Head of Design Infrastructure Management Division at TSMC. “SiFive’s partnership with TSMC and leadership in the RISC-V architecture enable our mutual customers to achieve next-generation design innovation for key spaces, such as HPC, mobile, and automotive.”\r\n\r\n“The global SiFive team is honored to be recognized with this prestigious TSMC award for our partnership, RISC-V leadership, and continued innovation,” said Yunsup Lee, Co-founder and CTO. “This award reflects the importance both companies place on our long-term innovation partnership and the great work by teams in both companies. SiFive offers leading power and area efficiencies in a modern architecture supported by the global RISC- V ecosystem, and working with TSMC we are able to do so on the most advanced process nodes and together help proliferate RISC-V.”\r\n\n**About SiFive**\n\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit SiFive.com.\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\n**Media Contact**\r\nAllison DeLeo\r\nRacepoint Global for SiFive\r\nSiFive@racepointglobal.com\r\nTel.: +1(415) 694-6711\r\n \r\nDavid Miller\r\nCorporate Communications\r\nSiFive\r\nDavid.Miller@sifive.com\r\n\r\n\r\n","spans":[]}]}},{"id":"Y2B6OBAAAB4A1wm0","uid":"sifives-new-high-performance-processors-offer-a-significant","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Y2B6OBAAAB4A1wm0%22%29+%5D%5D","tags":[],"first_publication_date":"2022-11-01T13:00:07+0000","last_publication_date":"2022-11-01T14:11:00+0000","slugs":["sifives-new-high-performance-processors-offer-a-significant-upgrade-for-wearable-and-consumer-products"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive’s New High-Performance Processors Offer a Significant Upgrade for Wearable and Consumer Products","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-11-01","share_image":{"link_type":"Media","kind":"image","id":"Y2B5uhAAAB0A1weI","url":"https://images.prismic.io/sifive/c2add8c0-0d59-4475-be2d-c33921a4ed93_Performance.jpg?auto=compress,format","name":"Performance.jpg","size":"100162","width":"960","height":"540"},"body":[{"type":"preformatted","text":"**Next generation P670 and P470 RISC-V Processors bring ultimate flexibility and balance of performance and efficiency for next-generation wearables and smart consumer devices**\r\n \r\n**Santa Clara, Calif., November 1, 2022** - [SiFive, Inc.](https://www.sifive.com) the founder and leader of RISC-V computing, today announced two new products that address the need for high performance and efficiency in a small size in high volume applications like wearables, smart home, industrial automation, AR/VR, and other consumer devices. The SiFive Performance™ P670 and P470 RISC-V processors bring unparalleled compute performance and efficiency that is significantly raising the bar for innovative designs in these high-volume markets. The modern and innovative SiFive design methodologies bring raw compute density that is a substantial advantage for SiFive Performance products and also translates into significant cost savings for customers.\r\n \r\n“The P670 and P470 are specifically designed for, and capable of handling the most demanding workloads for wearables and other advanced consumer applications. These new products offer powerful performance and compute density for companies looking to upgrade from legacy ISAs,” said Chris Jones, SiFive VP of Product. “We have optimized these new RISC-V Vector enabled products to deliver the performance and efficiency improvements the industry has long been asking for, and we are in evaluations with a number of top-tier customers. Additionally, as the upstream enablement of RISC-V has started within the Android Open Source Project, (AOSP), designers will have unrivaled choice and flexibility as they consider the positive implications with that platform for future designs.” \r\n \r\n\"We are excited to see RISC-V solutions for wearable and consumer devices becoming a reality, and we are looking at possibilities of integrating SiFive’s latest products into Snapdragon platforms,” said Ziad Asghar, Vice President, Product Management- Snapdragon Technologies and Roadmap at Qualcomm. \r\n\r\n\"Samsung’s System LSI Business holds a wide portfolio of solutions for various applications, such as mobile, wearables and other consumer devices. We look forward to evaluating how the latest RISC-V innovations from SiFive can enhance our offerings,” said Jinpyo Park, VP of the Innovative AP Development Team, Samsung Electronics System LSI Business.\r\n\r\n“SiFive continues to be a market leader in the growing and maturing RISC-V space and again shows its leadership with its new SiFive Performance P670 and P470 RISC-V processors,” said Todd R. Weiss, an analyst with Futurum Research. “These latest and powerful new processors give SiFive feature and performance advantages that will gain plenty of attention from device makers and consumers who want more from their devices. SiFive has been growing its reputation for some time and is truly ready to shake up the marketplace.” \r\n \r\n**Features**\n\r\nThe SiFive Performance P470 and P670 products offer a finely-tuned combination of compute-density, power efficiency, and robust feature sets ideal for a wide range of applications and markets:\r\n \r\n•\tSupport for virtualization, including a separate IOMMU for accelerating virtualized device IO\n\r\n•\tFull, Out-of-Order, RISC-V Vector implementation, based on the ratified RISC-V Vector v1.0 Specification\n\r\n•\tFirst to market with the RISC-V Vector Cryptography extensions\n\r\n•\tSiFive WorldGuard system security \n\r\n•\tFull RISC-V RVA22 profile compliance\n\r\n•\tNew, Advanced Interrupt Architecture (AIA) compliant interrupt controller, with better support for Message Signal Interrupts (MSI) and virtualization\n\r\n•\tEnhanced scalability with fully coherent multi-core, multi-cluster, with support for up to 16 cores\r\n \r\n**SiFive Performance P670**\n\r\nThe P670 is ideal for applications like premium wearables, networking, robotics, and mobile. The P650, which excludes the vector unit, is already shipping to lead customers and is being used in applications that do not require the additional capabilities that vector compute offers or are more area constrained. \r\n \r\nThe feature rich P670:\n \r\n•\tachieves a maximum frequency exceeding 3.4GHz in 5nm,\n\r\n•\thas performance of greater than 12 SpecINT2k6/GHz, offering optimized performance in a constrained area and power envelope,\n\r\n•\toffers higher single threaded performance and 2x compute density compared to legacy solutions, and\n\r\n•\tincludes a 2x 128-bit Vector ALUs compliant with the ratified RISC-V Vector v1.0 specification\r\n\r\n**SiFive Performance P470**\n\r\nThe P470 is SiFive’s first efficiency-focused Out-of-Order, area optimized, vector processor, ideal for applications like wearables, consumer, and smart home devices. Expanding on the proven P500-Series, the P470 is significantly smaller than competing solutions and optimized to have best-in-class performance efficiency and area density. \r\nThe P470 was designed to also serve as a companion to the P670 processor for demanding applications that require a sharing of compute resources while optimizing power consumption.\r\n \r\nThe P470 offers a significant upgrade to legacy efficiency cores, achieving a maximum frequency exceeding 3.4GHz in 5nm, and greater than 8 SpecINT2k6/GHz, within a minimal area and power envelope.\r\n\r\nOther P470 features include:\n\r\n•\t4x compute density in comparison to leading competitor\n\r\n•\tIncludes 1x 128-bit RISC-V Vector ALU compliant with the ratified RISC-V Vector v1.0 specification\r\n \r\nSiFive will also release the P450 – an area-optimized version of the P470 that excludes the Vector Unit.\r\n\r\nA presentation highlighting the benefits of the new products will be made at the Linley Fall Microprocessor Conference later today. \r\n \r\nFor more information on SiFive’s market-leading RISC-V IP portfolio, please visit [SiFive.com/risc-v-core-ip](https://www.sifive.com/risc-v-core-ip).\r\n\n**About SiFive**\n\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit SiFive.com.\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\n**Media Contact**\r\nAllison DeLeo\r\nRacepoint Global for SiFive\r\nSiFive@racepointglobal.com\r\nTel.: +1(415) 694-6711\r\n \r\nDavid Miller\r\nCorporate Communications\r\nSiFive\r\nDavid.Miller@sifive.com\r\n\r\n\r\n","spans":[]}]}},{"id":"X7SkBxMAACAAKlfT","uid":"bouffalo-lab-standardizes-on-sifive-risc-v-embedded","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22X7SkBxMAACAAKlfT%22%29+%5D%5D","tags":[],"first_publication_date":"2020-11-18T14:00:06+0000","last_publication_date":"2022-08-08T21:13:19+0000","slugs":["bouffalo-lab-standardizes-on-sifive-risc-v-embedded-cpu-core-ip-for-new-iot-products"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Bouffalo Lab Standardizes on SiFive RISC-V Embedded CPU Core IP for New IoT Products","spans":[]}],"publish_to":"Archive","publish_date":"2020-11-18","share_image":{"link_type":"Media","kind":"image","id":"X7SncBMAACAAKmbp","url":"https://images.prismic.io/sifive/d16383f0-ad80-4d72-8e92-6da5dfaa9677_SiFiveBouffaloLabsAnnouncement.png?auto=compress,format","name":"SiFiveBouffaloLabsAnnouncement.png","size":"505409","width":"1000","height":"532"},"body":[{"type":"preformatted","text":"*SiFive E2 Core IP Flexibility and Power-efficient Performance Enable Bouffalo Product differentiation*\n\n**SAN MATEO, Calif. – November 18, 2020** – [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, and Bouffalo Lab, a leading provider of ultra-low-power, safe, AIoT hardware and software platforms, today announced the adoption of SiFive E2-Series Core IP based on RISC-V as part of Bouffalo’s new IoT Bluetooth, Zigbee, Thread and WiFi products, the BL70x and BL602. Bouffalo selected SiFive E2-Series Cores to meet the need for power-efficient performance and ultra-low-power operation in IoT devices for applications such as smart home.\u003cbr/\u003e\n\nThe Bouffalo BL70x chipset is designed for IoT applications and features highly-integrated Bluetooth Low Energy 5.0 connectivity, Zigbee 3.0 (IEEE 082.15.4) wireless mesh with a 2.4GHz radio, and incorporates a SiFive E2-Series 32-bit RISC-V microcontroller. The Bouffalo BL60x series is a Wi-Fi and Bluetooth combination chipset designed for ultra-low-power applications, and features Wi-Fi 802.11 b/g/n 2.4GHz support with Bluetooth Low Energy 5.0, and also incorporates a SiFive E2-Series 32-bit RISC-V microcontroller.\u003cbr/\u003e\n\nThe SiFive E2 Core is a compact and power-efficient 32-bit RISC-V-based core design for embedded applications such as IoT, edge computing, and microcontroller use where efficient operation is key to battery life or thermally-constrained designs. Using SiFive Core Designer, Buffalo Labs configured the SiFive E2 Cores to focus on their workload for performance and efficiency in a tiny footprint, creating a 32-bit RISC-V microcontroller with a single-precision floating-point unit, high-speed cache and memories, enabling micro-amp power draw during deep sleep mode for the ultra-low-power Bouffalo chipsets.\u003cbr/\u003e\n\n“Working with SiFive, the inventors of the open-standard RISC-V architecture, reduces our business risk and enhances Bouffalo’s product viability,” said Yonghua Song, Founder \u0026 CEO at Bouffalo Lab. “Our trust was well-placed in SiFive and its silicon-proven Core IP, as we realized the efficiency and performance of SiFive RISC-V IP, and quality of their support for integrating the IP into our IoT products.”\u003cbr/\u003e\n\n“The power-efficient, area-optimized E2 core has seen significant traction in IoT applications where battery life is key,” said Chris Lattner, President of Product and Platform Engineering at SiFive. “We’re proud to see Bouffalo bring optimized IoT products to market with our industry-leading RISC-V processor cores.”\u003cbr/\u003e\n\n**About Bouffalo**\u003cbr/\u003e\r\nBouffalo Lab is one of very few semiconductor chip design companies that provide high performance, ultra-low-power, safe and reliable AIoT intelligent software and hardware solutions with a complete set of wireless connectivity technologies, including WiFi 6, BT/BLE5.2, Zigbee3.0 and Thread to enable the creation of technology platforms for the Internet of Everything. Bouffalo Lab solutions enable a new generation of high-performance AIoT chips for smart homes, smart cities, smart retails, smart manufacturing, smart robots, communication equipment, in-vehicle smart systems, and smart wearable systems. For more information, please visit [bouffalolab.com](https://www.bouffalolab.com).\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\n\r\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e\n203.858.7259\u003cbr/\u003e","spans":[]}]}},{"id":"XeqMVBEAAKbkCUk-","uid":"tech-industry-heavyweight-joins-sifive---manoj-gujral","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XeqMVBEAAKbkCUk-%22%29+%5D%5D","tags":[],"first_publication_date":"2019-12-06T17:44:17+0000","last_publication_date":"2022-08-08T21:02:51+0000","slugs":["tech-industry-heavyweight-joins-sifive---manoj-gujral-tapped-as-svp--gm-of-silicon-business-unit"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Tech Industry Heavyweight Joins SiFive - Manoj Gujral Tapped As SVP \u0026 GM of Silicon Business Unit","spans":[]}],"publish_to":"Archive","publish_date":"2019-12-06","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Tech Industry Veteran to Lead SiFive Silicon BU Growth and Execution*\n\nSAN MATEO, Calif., Dec. 6, 2019 /PRNewswire/ -- SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Manoj Gujral has joined the company as senior vice president and co-general manager of the SiFive silicon business unit. SiFive continues to invest in the democratization of access to silicon, most recently announcing the SiFive Learn Inventor board, the world's first RISC-V based device to become Amazon FreeRTOS qualified. The SiFive Learn Inventor board was developed to demonstrate the potential for creating differentiated products based on existing validated and qualified designs to accelerate go to market while including customer IP integration.\r\n\r\n\"SiFive is positioned to take full advantage of the switch from off-the-shelf products to domain-specific SoCs designed in partnership with leading IP providers,\" said Gujral. \"The growth of computer vision and industrial IoT devices that require designs tailored to workload-specific requirements will benefit from the SiFive silicon business unit's capabilities to rapidly enable differentiated products.\"\r\n\r\nGujral brings more than 25 years of experience in system architecture and business unit management in developing revenue streams based on disruptive new products. Gujral has held several general manager positions at leading tech companies including NVIDIA, Cavium, Cypress Semiconductor, and several innovative startups.\r\n\r\n\"We warmly welcome Manoj to SiFive as his proven ability to define strategic vision and drive quality will further sharpen SiFive's focus on silicon design and production,\" said Dr. Naveed Sherwani, president and CEO of SiFive. \"The need for domain-specific designs is increasing and Manoj's demonstrated ability in system architecture will ensure SiFive growth.\"\r\n\r\nGujral holds a Master of Science in Electrical Engineering from Oregon State University and a Masters of Business Administration from San Jose State University. He has completed the Standford University Graduate School of Business Executive Leadership Program and holds ten patents in the field of system architecture.\r\n\r\n## About SiFive\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [visit SiFive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\n\n**Media Contact**\u003cbr\u003e\r\nSara Dodrill\u003cbr\u003e \r\nSHIFT Communications for SiFive\u003cbr\u003e\r\n(415) 591-8429\u003cbr\u003e\r\nsifive@shiftcomm.com\u003cbr\u003e\r\n","spans":[]}]}},{"id":"Xeg94hIAACQAJpQw","uid":"sifive-welcomes-ann-chin-as-sifive-ip-business-unit","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Xeg94hIAACQAJpQw%22%29+%5D%5D","tags":[],"first_publication_date":"2019-12-05T00:41:28+0000","last_publication_date":"2022-08-08T21:02:20+0000","slugs":["sifive-welcomes-ann-chin-as-sifive-ip-business-unit-general-manager"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Welcomes Ann Chin As SiFive IP Business Unit General Manager","spans":[]}],"publish_to":"Archive","publish_date":"2019-11-26","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Arm Veteran to Enable Next-Generation High-Performance Processor Development*\n\nSAN MATEO, Calif., Nov. 26, 2019 /PRNewswire/ -- SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Ann Chin has joined the company as vice president and co-general manager of the SiFive IP business unit. Chin joins SiFive IP Business Unit Vice President and Co-General Manager Mohit Gupta to ensure the development and execution of next-generation high-performance, scalable processor core IP. SiFive continues to invest in expanding the performance of RISC-V processor IP, and most recently announced the SiFive U8-Series of processor Core IP, the world's first out-of-order superscalar RISC-V processor Core IP on the market.\r\n\r\n\"SiFive has a unique opportunity to enable a broad array of leading semiconductor companies with new, scalable, high-performance processor core IP,\" said Chin. \"I'm excited to help guide the development of next-generation high-performance processor cores based on a free and open ISA, and help ensure the execution and delivery of our Core IP roadmap.\" \r\n\r\nChin has a background in microprocessor design and processor architecture IP development, bringing nearly 30 years of technical experience combined with organizational leadership. Chin worked at Arm for 19 years, holding many key lead technical positions for next-generation high-end infrastructure and mobile Arm CPUs. As an Arm Fellow, Chin participated in multiple leadership groups, including worldwide CPU project planning, execution, and delivery. Chin also worked at Motorola in various design and verification roles.\r\n\r\n\"We're pleased to welcome Ann to SiFive to help lead our Core IP roadmap and execution,\" said SiFive President and CEO Dr. Naveed Sherwani. \"Ann's leadership in high-performance processor development is a key ingredient in our next generation RISC-V core roadmap, and her vision for high-quality deliverables and execution is perfectly aligned to our values for customer success.\"\r\n\r\nChin holds a Master's degree in Electrical Engineering from the University of Texas at Austin, and a Bachelor's degree in Electrical Engineering from the University of Texas at Austin.\r\n\r\n## About SiFive\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [visit SiFive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\r\n\r\nArm is a registered trademark of Arm Limited (or its subsidiaries). All brands or product names are the property of their respective holders.\n\n**Media Contact**\u003cbr\u003e\r\nSara Dodrill\u003cbr\u003e \r\nSHIFT Communications for SiFive\u003cbr\u003e\r\n(415) 591-8429\u003cbr\u003e\r\nsifive@shiftcomm.com\u003cbr\u003e\r\n\n","spans":[]}]}},{"id":"X7W9KxMAACIALwEh","uid":"bbc-learning-and-tynker-collaborate-on-coding-for-kids","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22X7W9KxMAACIALwEh%22%29+%5D%5D","tags":[],"first_publication_date":"2020-11-19T14:00:01+0000","last_publication_date":"2022-08-08T21:11:45+0000","slugs":["bbc-learning-and-tynker-collaborate-on-coding-for-kids-with-a-next-generation-education-technology-mini-computer","bbc-learning-and-tynker-collaborate-on-coding-for-kids-with-a-next-generation-education-technology-mini-computer-and-coding-for-kids"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"BBC Learning and Tynker Collaborate on Coding for Kids with a Next-Generation Education Technology Mini-Computer","spans":[]}],"publish_to":"Archive","publish_date":"2020-11-19","share_image":{"link_type":"Media","kind":"image","id":"X8qMaxMAACAAidte","url":"https://images.prismic.io/sifive/1336dca2-88a0-4cec-bfc3-31682bce1715_BBCHiFiveInventor.png?auto=compress,format","name":"BBCHiFiveInventor.png","size":"629684","width":"1000","height":"529"},"body":[{"type":"preformatted","text":"*Featuring the voice and star of the Thirteenth Doctor, Jodie Whittaker, the HiFive Inventor is a powerful Internet of Things programmable computer designed to teach kids to code*\n\n**New York, NY - November 19, 2020** - BBC Learning, a division of BBC Studios and Tynker, a world-leading K-12 creative coding platform have partnered to bring engaging next-generation coding education to students with the BBC Doctor Who HiFive Inventor, including coding lessons narrated by the star of the Thirteenth Doctor, Jodie Whittaker, on November 23, Doctor Who Day.\u003cbr/\u003e \r\n\r\nWith the rapid increase in Internet of Things (IoT) devices and smart consumer products, opportunities for bright young minds with coding skills are being created every day. The HiFive Inventor is a visually stunning IoT-enabled hand-shaped mini-computer designed to teach kids how to control robots or interface with IoT systems to investigate the world around them. The BBC HiFive Inventor will be available to order through [BBC Shop](https://shop.bbc.com/products/doctor-who-hifive-inventor-coding-kit-22984), Amazon, Pimoroni, and other leading retailers on November 23, 2020. Learn more at [HiFiveInventor.com](http://www.hifiveinventor.com/)\u003cbr/\u003e \r\n\r\nThe HiFive Inventor will engage kids with its friendly hand-shaped form factor. With built-in Wi-Fi and Bluetooth technologies this reinforces the wireless data handoff between devices (or “HiFive”) that will power 21st-century technology applications of computing for smart cities, intelligent factories, and enhanced wearable technology. Students will be able to read data from the on-board suite of sensors and program on-device decisions to display results using the fun and colorful LED-matrix display. The HiFive Inventor is powered by a robust SiFive processor and comes with an illuminated USB cable, battery pack, and edge connectors to allow for expandability to a range of additional sensors and devices.\u003cbr/\u003e\r\n\r\nThe HiFive Inventor aims to impart building-block knowledge students can marry with their imagination and creativity to tackle global opportunities and challenges like environmental changes, health and wellness, and a host of other areas to positively impact lives. At a time, when many students are experiencing disruption to their education patterns, it is a key moment for all members of the global community - parents, teachers, and organizations – to work together to give all students the skills they need to participate in the future economy.\u003cbr/\u003e \r\n\r\nEnabled by the award-winning Tynker creative coding platform, the HiFive Inventor engages students to begin coding quickly in a self-paced and learner-driven environment. Tynker has vast experience and knowledge on how to engage kids to learn to code and has created hundreds of hours of content that has motivated millions to become makers of technology. Narrated by Jodie Whittaker, the Thirteenth Doctor, she takes students on intergalactic journeys and challenges like learning to code and pilot an alien spaceship, control a robot and program an exotic musical instrument. Like all Tynker courses, the BBC Doctor Who HiFive Inventor will teach kids essential skills as they are having fun. Younger students will begin their learning journey with the Tynker visual block coding and advanced students with Micropython.\u003cbr/\u003e\r\n\r\nDoctor Who, is a BBC AMERICA co-production with BBC Studios, and is one of the longest-running action-adventure television series in the world spanning 56 years and winning over 100 awards. It premieres exclusively on BBC AMERICA with past seasons available to stream exclusively on HBO Max.\u003cbr/\u003e\r\n\r\n“At the heart of BBC Learning is a mission to use industry-leading story-telling to educate people worldwide,” said Kara Iaconis, Global Head of BBC Learning. “This initiative builds upon the storied legacy of the BBC, and we are excited to bring cutting-edge education to students in a way that enables learning like never before. We look forward to working with organizations and companies globally to broaden this platform and to get kids coding.”\u003cbr/\u003e\r\n\r\nKrishna Vedati, CEO of Tynker stated, “Over the last eight years, Tynker has engaged 60 million kids worldwide in coding and we look to continue to build the next generation of innovators and problem solvers with this partnership. The BBC Doctor Who HiFive Inventor is perfectly designed to spark kids’ curiosity in physical computing as they learn to program the Internet of Things using block-coding and MicroPython.”\u003cbr/\u003e\r\n\r\nDr. Chris Lattner, President of Engineering and Product at SiFive says “Kids are the future, and my six- and eight-year-old love the BBC Doctor Who HiFive Inventor. It provides a great combination of block-based and real coding in a physical space that they can interact with and learn from. Coding is an incredible skill that allows us to build anything that you can imagine - apps, autonomous cars, and things we haven’t dreamed up yet - and kids have the best imaginations. We at SiFive love working with BBC Learning and Tynker to help drive this amazing collaboration, and move the state of computer education forward.\"\u003cbr/\u003e \r\n\r\nFor educational institutions or not-for-profits interested in bulk purchases, please contact *schools@hifiveinventor.com*.\u003cbr/\u003e \r\n\n**Media Contact**\u003cbr/\u003e\n*BBC Studios*\u003cbr/\u003e\r\nAmy Mulcair\u003cbr/\u003e\r\namy.mulcair@bbc.com\u003cbr/\u003e\r\n646.404.0941\u003cbr/\u003e\r\n\r\n*Tynker*\u003cbr/\u003e\r\nTeri Llach\u003cbr/\u003e\r\npress@tynker.com\u003cbr/\u003e\r\n650.575.6913\u003cbr/\u003e\r\n\r\n*SiFive*\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e\n203.858.7259\u003cbr/\u003e","spans":[]}]}},{"id":"Yx-HrxIAACMAPNJK","uid":"sifive-rolls-out-powerful-new-risc-v-portfolio-to-address","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Yx-HrxIAACMAPNJK%22%29+%5D%5D","tags":[],"first_publication_date":"2022-09-13T12:58:38+0000","last_publication_date":"2022-09-13T12:58:38+0000","slugs":["sifive-rolls-out-powerful-new-risc-v-portfolio-to-address-unmet-performance-and-feature-needs-of-rapidly-evolving-next-gen-digital-automobiles"],"linked_documents":[],"lang":"en-us","alternate_languages":[{"id":"ZKRL3REAACEAs_JT","type":"press_release","lang":"zh-cn","uid":"sifive-rolls-out-powerful-new-risc-v-portfolio-to-address"}],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Rolls Out Powerful New RISC-V Portfolio to Address Unmet Performance and Feature Needs of Rapidly Evolving Next-Gen Digital Automobiles","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-09-13","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"**SiFive introduces Automotive E6-A, X280-A, and S7-A products and long-term roadmap**\n\n**San Mateo, Calif. , September 13, 2022** - [SiFive, Inc.](https://www.sifive.com) the founder and leader of RISC-V computing, today announced three products as part of the first phase of a long-term roadmap and portfolio designed to meet the specific needs of automotive manufacturers and their suppliers. SiFive Automotive™ E6-A, X280-A, and S7-A solutions address critical needs for current and future applications like infotainment, cockpit, connectivity, ADAS, and electrification, as the market transitions to zonal architectures and manufacturers require the energy efficiency, simplicity, security, and software flexibility that RISC-V offers. SiFive's high-end applications and real-time processors offer industry-leading performance, with the lowest area and power consumption, and are being tailored to vehicle specific needs for safety, security, and performance. The company also highlighted a growing list of top-tier customers and leading ecosystem partners, and how they are collaborating to deliver comprehensive automotive solutions. \r\n \r\nThe transformation to the digital automobile has changed, accelerated, and increased the demands on computing requirements, the pace of innovation, and the flexibility required within the automotive supply ecosystem. This rapid evolution is driving the success of RISC-V in the automotive market, which is taking advantage of its flexible, modern architecture, fast growing ecosystem, and proven power and performance benefits to bring solutions that accelerate the pace of innovation in the vehicle space. \r\n\r\n“SiFive is combining the best RISC-V benefits in the only end-to-end portfolio designed to meet automotive needs today and long into the future,” said Patrick Little, CEO and Chairman, SiFive. “We are seeing widespread interest in our new RISC-V automotive solutions and are working closely with several leading semiconductor companies and top-tier suppliers, who are turning to the flexibility of our highest performance cores in areas like safety-critical compute applications. Customers are now able to take advantage of our latest, most powerful cores to bring exciting innovations to consumers.”\r\n\r\n“Renesas has been closely collaborating with SiFive to bring the strong benefits of RISC-V to many of our products,” said Takeshi Kataoka, Senior Vice President and General Manager of the Automotive Solution Business Unit at Renesas. “RISC-V continues to gain momentum around the world, and we plan to leverage SiFive’s portfolio of automotive RISC-V products in our future automotive SoC solutions to meet the exacting demands of these global customers. Partnering with an innovation leader like SiFive is a logical step that allows us to fuel our growth and meet our customer’s evolving requirements.” \r\n \r\n**RISC-V: Meeting Automotive Requirements Today and Into the Future**\r\n \r\nRISC-V brings a host of benefits to the automotive industry. Using a single instruction set architecture (ISA) across all product offerings – from safety islands to real-time products to highest performance ADAS and central zone compute – increases code portability and can greatly reduce cost and time-to-market, while RISC-V vector extensions bring enhanced machine learning and DSP capabilities. The global RISC-V ecosystem is growing rapidly, particularly in the U.S. and China, and consists of more than three thousand members. This provides wide choice and ensures future support and innovation. Working without proprietary lock-in, companies can license from multiple vendors and have more flexibility to design their own IP where needed, while maintaining software and ecosystem compatibility.\r\n\r\n\"Semiconductors are rapidly becoming the most critical component to the next generation of vehicles. With chips set to be over 20% of the BoM for cars by the end of the decade, the development of power-efficient, highly performant chips will continue to be a key priority for automotive manufacturers seeking to develop the most innovative automobiles for the future,” said Daniel Newman, Principal Analyst for Futurum Research. “SiFive continues to play an important role in leading the evolution of chip designs based on RISC-V, which I expect will gain market momentum as auto manufacturers seek to level up their vehicles to meet the increased demands of consumers wanting the most forward thinking, safe, and secure technology in their cars.\"\r\n\r\nThe company is also working with a growing list of ecosystem partners to build a comprehensive RISC-V automotive solution set. [Check out the partner list here.](/cores/automotive#partners). Also see the list of partner quotes below.\r\n \r\n**The SiFive Automotive E6-A, S7-A, and X280-A Series of Processors**\r\n \r\nThe SiFive Automotive processor family offers the highest level of flexibility from any CPU IP vendor, with options that enable both area and performance optimization for different integrity levels like ASIL B, ASIL D, or mixed criticalities with split-lock, in line with ISO26262.\r\n \r\n- E6-A series for a variety of real-time, 32-bit applications, from system control to hardware security modules (HSMs) and safety islands, and as standalone in microcontrollers.\r\n- S7-A is a 64-bit, high-performance real-time core perfectly suited to the needs of modern SoCs with performant safety islands, requiring both low latency interrupt support and the same 64b memory space visibility as the main application CPUs.\r\n- X280-A builds on the successful performance and power efficiency of the X280 and is ideal for sensors, sensor fusion, and other vector or ML intensive workloads in automotive applications.\r\n\r\nThe SiFive Automotive family will also expand its portfolio in 2023 with a very high performance, out of order, application CPU with best-in-class performance and automotive capabilities.\r\n \r\nSiFive's automotive products are accompanied by relevant safety packages that include documentation to accelerate the integration of the Safety Element out of Context (SEooC) and, with it, our customers’ time-to-market. Independent assessments of ASIL claims will support SiFive's safety claims. \r\n\r\nEnabling solutions include proven SiFive WorldGuard security solutions. With tailored levels of integrity for functional safety, SiFive Automotive products are also compliant with relevant cybersecurity standards, such as WP.29, R155, and ISO21434.\r\n \r\n**Future Automobiles will be Powered by RISC-V**\r\n \r\nSiFive is creating a complete lineup of compute IP for MCUs, MPUs, and high-performance SoCs, as well as vector processing solutions tailored for automotive applications, with the first high-performance, out-of-order, Automotive family cores planned for late 2023.\r\n\r\n\"We are making a significant long-term investment into the future of automotive, and we are continuing to assemble a world-class team of automotive CPU design experts who are collaborating with industry leaders to drive the digital vehicle forward,\" continued Little.\r\n\r\nFrom technologists like Monia Chiavacci who is a globally recognized pioneer in Functional Safety (FuSA) applied to systems-on-a-chip, a critical auto safety innovation, to Chairman and CEO, Patrick Little, who helped build the successful automotive business at Qualcomm, SiFive has put in place the team and tools to advance the digital automobile with RISC-V. \r\n \r\n\"One of the things that brought me to a leader like SiFive was the incredible potential of RISC-V, enabled by SiFive's innovations, to develop solutions for some of the automotive industry’s greatest challenges while ensuring flexibility and faster time to market for both suppliers and manufacturers,\" said Monia Chiavacci, SiFive Senior Principal Architect. \"In addition to delivering our powerful processors, we are equally focused on ensuring the highest levels of functional safety without compromising performance and innovation.\"\r\n\r\nWith several lead customers already, the SiFive Automotive E6 products will ship in Q4 of this year and the S7A and X280A are expected to be available shortly after. \r\n \nLearn more about [SiFive’s Automotive Family of Products](/cores/automotive) here.\n\r\n**In addition to the announcement of our own new RISC-V automotive product portfolio, SiFive is pleased to have the support of a wide base of ecosystem partners who are collaborating closely with us as we work to create the industry’s most comprehensive automotive solutions offering.**\r\n\r\n**Ashling**\r\nAshling’s toolchain and RISC-V have grown to be synonymous as the embedded market continues to move from general purpose chips to fully/semi-custom multi-core solutions. Ashling’s RiscFree™ toolchain offers full customization package that allows development of a comprehensive, multi-core, heterogeneous, SDK tool suite tailored and optimized for any RISC-V based IP or device. Since the early days of RISC-V, Ashling’s comprehensive debug and trace solutions have supported SiFive Essential™ processors, with strong customer adoption, and we have plans to support SiFive’s RISC-V processor roadmap.\r\n\r\n“For more than thirty years, Ashling’s toolchain and its various trace development solutions, including Ashling’s VITRA trace debug product, have been used by leading automotive companies. We are happy to extend our collaboration with SiFive to join in their automotive initiative by adding support for new SiFive Automotive processor portfolio, including work already underway for the SiFive Automotive™ E6-A. We are confident our Ashling toolchain and trace solution will offer significant added value to customers adopting SiFive Automotive processors,” said Hugh O’Keeffe, CEO of Ashling.\r\n\r\n**Cadence**\r\n“Cadence looks forward to collaborating with SiFive on an automotive reference flow that utilizes our industry-leading digital, custom and verification solutions to enable mutual customers to design and deliver their SoCs quickly with optimal power, performance and area,” said KT Moore, vice president, Corporate Marketing, Cadence\r\n\r\n**Canonical**\r\n“Canonical is thrilled to collaborate with SiFive in co-creating automotive solutions. With the advent of autonomous and connected cars, open-source software has become essential in fueling innovation in the automotive industry,” said Gordan Markus, silicon alliances partner manager, Canonical. “With the growing need to manage hardware and software complexity, Canonical and SiFive are perfectly positioned to allow our partners to bring efficient and performant automotive solutions to market at an accelerated pace. Furthermore, Ubuntu provides our partners with development simplicity, while ensuring enterprise-grade support and security.”\r\n\r\n**Elektrobit**\r\n“Elektrobit is a leading provider of software solutions and services for the automotive industry with years of deep expertise in developing safety-critical applications to the highest standards,” said Mike Robertson, vice president, global product management and strategy, Elektrobit. “We see RISC-V building momentum in processor IP. As the automotive market continues to grow and evolve, Elektrobit is excited about the opportunities to develop applications based on SiFive’s extensive roadmap of RISC-V Automotive processors.”\r\n\r\n**Green Hills**\r\n“As a global leader in embedded software with the broadest portfolio of ASIL D certified software solutions for 32-bit MCU to 64-bit MPUs, Green Hills is excited to be supporting SiFive’s impressive range of automotive-focused RISC-V CPU IP,” said Dan Mender, Vice President, Business Development, Green Hills Software. “To complement this remarkable new SiFive Automotive portfolio, Green Hills brings its unique ability to deliver MCU-to-MPU production-proven FuSa-certified tools, C/C++ compilers and RTOSes, along with decades of safety program expertise.”\r\n\r\n**IAR Systems**\r\n“SiFive is a leading provider in the RISC-V ecosystem and has a long-standing relationship with IAR Systems. We are equally both excited and committed to supporting their increased focus on the Automotive-vertical,” said Anders Holmberg, CTO at IAR Systems. “The combination of innovative Automotive Functional Safety IP from SiFive and the certified development tools from IAR Systems is a perfect match. Building on IAR Systems’ 20+ years of experience supporting Functional Safety use cases, and the tens of thousands of developers using our products, there is now a true better-together offering to accelerate innovation in automobiles.”\r\n\r\n**iSystem AG**\r\n “We are working with SiFive and other ecosystem partners on early support of RISC-V cores as we see them as an important contender in the future automotive market,” said Erol Simsek, CEO of iSYSTEM AG. “Our tools are designed to verify stringent safety requirements for automotive electronics, and a close cooperation with SiFive ensures that the very first device will offer all the necessary debug and real-time trace capabilities. Early adopters looking to evaluate RISC-V architecture can already use iSYSTEM tools to do so on existing SiFive devices or pre-silicon FPGA platforms.”\r\n\r\n**Lauterbach**\r\n“It has always been a priority for Lauterbach to work closely with innovation leaders like SiFive to provide our customers with proven tools as soon as they are needed,” said Markus Herdin, head of marketing at Lauterbach. “We see the automotive industry as one of the big growth areas for RISC-V and are here to help with debug and trace solutions that meet the specific needs of this industry. We believe that with SiFive’s E6-A series, RISC-V will gain further momentum in automotive applications, which we will be delighted to support with our tools.”\r\n\r\n**Resiltech**\r\n“Resiltech, aware of the importance of the role of RISC-V products and its ecosystems for the next generation automotive applications, is fully committed to confirm long-term support to SiFive to enable compliance of its automotive IP with the highest automotive safety requirements.” – Dr. Rosaria Esposito, CEO, Resiltech s.r.l.\r\n\r\n**SEGGER**\r\n“SEGGER has been supporting RISC-V since 2017, and we support the complete range of RV32 and RV64 cores from SiFive,” said Rolf Segger, founder of SEGGER. “The SEGGER Software Platform – including the Embedded Studio IDE, the J-Link debug probes, as well as our embOS RTOS and associated middleware – provides a comprehensive one-stop solution for complete product development with microcontrollers based on the RISC-V architecture. We are excited to be part of SiFive’s Automotive initiative, and we are looking forward to supporting the E6-A product series in the near future.”\r\n\r\n**Siemens**\r\n“Siemens Digital Industries Software has a long history of offering leading embedded software solutions for the automotive industry and is excited to extend our existing partnership with SiFive to enable even greater innovation in future automotive products,” said Jeff Hancock, Sr. Product Manager, Siemens Digital Industries Software.\r\n\r\n**Solid Sands**\r\nOver the past few years, we have seen accelerated adoption of RISC-V worldwide. What surprises us is the speed of this also happening in the safety-critical automotive market, which is known to be conservative. Which implies that SiFive, with its RISC-V solution, solves a problem that is hard to crack. We are happy to assist SiFive customers with compiler and library automotive qualifications and see no inherent roadblocks to prevent open hardware and software from being used in safety-critical applications. - Marcel Beemster, CTO - Solid Sands\r\n\r\n**Synopsys**\r\n“In the era of software-defined vehicles, Synopsys is helping to drive safety, security, reliability, and quality in the automotive digital value chain,” said Kiran Vittal, senior director of marketing in the Silicon Realization Group at Synopsys. “By collaborating with SiFive, we are enabling mutual customers to leverage our EDA design and verification solutions to achieve the optimal performance, power, area, and prototyping efficiency, while accelerating automotive-compliance for their RISC-V designs.”\r\n\r\n**SYSGO**\r\n“SYSGO is proud to be a leading partner of SiFive with support for SiFive’s portfolio of RISC-V processors,” said Franz Walkembach, VP Marketing \u0026 Alliances at SYSGO. “With our certifiable hard real-time PikeOS operating system and hypervisor software combined with extensive technology expertise in functional safety, we will further support SiFive’s RISC-V solutions in markets such as Automotive, Space, Railway and Avionics.”\r\n\r\n**TASKING**\r\n“As a trusted supplier to the automotive industry, TASKING is pleased to support the market introduction of SiFive Automotive processors. The TASKING® VX-toolset for RISC-V is a complete solution for code development for RISC-V based automotive ECUs. The VX-toolset for RISC-V produces fast and compact code and is being certified according to ISO 26262 functional safety and ISO/SAE 21434 cybersecurity standards,” said Gerard Vink, RISC-V Product Line Responsible, Tasking.\r\n\r\n**VIRTUAL OPEN SYSTEMS**\r\n\"At Virtual Open Systems (VOSyS) we are excited to port our ISO26260 certifiable mixed criticality virtualization solution VOSySmonitoRV to the SiFive automotive product family. The work at VOSyS side is well started, and we have proven Linux OS with FreeRTOS co-execution; this activity continues, and we are proceeding with MISRA and functional coverage. The plan is to complete ASIL certification based on the S7-A processor series in 2023,\" said\r\nDaniel Raho, CEO\r\n\r\n**WITTENSTEIN**\r\n“As RISC-V becomes more popular, WITTENSTEIN high integrity systems’ partnership with SiFive allows us to support customers with the most cutting-edge processors, said Stephen Ridley, Engineering Manager at WHIS. “We are excited to see the ever-expanding automotive portfolio of SiFive and look expectantly to what is to come. SiFive have made it possible to develop new hardware faster than ever before, a must in the evolving automotive market. SiFive's automotive offerings are a great fit with SAFERTOS, our safety critical RTOS. Together they make a compelling package for automotive. WHIS and SiFive look forward to a continuation of our close collaboration in the future.\n\n**About SiFive**\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit [SiFive.com.](https://www.sifive.com)\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\r\n\n**Media Contacts** \u003cbr/\u003e\nAllison DeLeo\u003cbr/\u003e\nRacepoint Global for SiFive,\u003cbr/\u003e\n[SiFive@racepointglobal.com](mailto:SiFive@racepointglobal.com), \u003cbr/\u003e\r\nTel.: +1 (415) 694-6711\r\n\r\nDavid Miller,\u003cbr/\u003e\r\nCorporate Communications,\u003cbr/\u003e\r\nSiFive,\u003cbr/\u003e\r\n[David.Miller@sifive.com](mailto:david.miller@sifive.com)\u003cbr/\u003e\n\r\n\r\n\r\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqY","uid":"sifive-secures-50-million-funding-to-advance-risc-v-based-semiconductors","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqY%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T21:52:42+0000","slugs":["sifive-secures-50.6-million-funding-to-advance-risc-v-based-semiconductors"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Secures $50.6 Million Funding to Advance RISC-V Based Semiconductors","spans":[]}],"publish_to":"Archive","publish_date":"2018-04-02","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN FRANCISCO – April 2, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today announced it raised $50.6 million in a Series C round led by existing investors Sutter Hill Ventures, Spark Capital and Osage University Partners alongside new investor Chengwei Capital, and strategic investors including Huami, SK Telecom and Western Digital and other companies that are among the most respected and iconic companies in the industry. This Series C round brings the total investment in SiFive to $64.1 million. Additionally, the company also announced it has signed a multi-year license to its Freedom Platform with Western Digital, which has pledged to produce 1 billion RISC-V cores.\n\nThis investment will enable SiFive to continue to innovate and provide leadership in bringing highly disruptive RISC-V technologies to the marketplace. “Over the past two years, SiFive has been at the forefront of the RISC-V ecosystem,” said Stefan Dyckerhoff, managing director at Sutter Hill Ventures and member of the SiFive board of directors. “Sutter Hill Ventures is confident that SiFive will continue to provide innovative solutions that will fundamentally change the semiconductor industry.”\n\nSaid Martin Fink, chief technology officer, Western Digital: “RISC-V delivers a platform for innovation unshackled from the proprietary interface of the past. This freedom allows us to bring compute closer to data to optimize special purpose compute capabilities targeted at Big Data and Fast Data applications. The next generation of applications like Machine Learning, AI, and Analytics require this ability to focus on a specific task. Western Digital is focused on the next generation of innovation to enable this new class of applications to deliver the possibilities of data.”\n\nThis Series C financing comes amid continued milestones for SiFive since its last round of funding in May 2017. Since then, SiFive has expanded its executive team with seasoned industry veterans including CEO Naveed Sherwani. The company also moved to a new, larger headquarters in Silicon Valley, a move that was prompted by a projected 3X growth in headcount.\n\n“We are honored by the continued partnership with our investors and energized by new engagements with longtime industry leaders,” said Naveed Sherwani, CEO of SiFive. “This funding from our investors and licensing agreements with strategic partners establishes a strong financial foundation which will help us to continue our trailblazing path of engineering innovations and extend our market leadership around the world.”\n\nSiFive’s mission is to democratize access to custom silicon through its IPs and platforms, globally. Since becoming available, HiFive1 and HiFive Unleashed software development boards have been deployed in more than 50 countries. Additionally, the company has engaged with multiple customers across its IP and SoC products, [shipped the industry’s first RISC-V SoC](/press/sifive-introduces-industrys-first-open-source-chip-platforms) in 2016 and the industry’s first RISC-V IP with support for Linux in October 2017\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit \n[www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrW","uid":"sifive-launches-worlds-first-linux-capable-risc-v-based-soc","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrW%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T21:51:18+0000","slugs":["sifive-launches-worlds-first-linux-capable-risc-v-based-soc"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Launches World’s First Linux-Capable RISC-V Based SoC","spans":[]}],"publish_to":"Archive","publish_date":"2018-02-07","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Feb. 7, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com/),\nthe leading provider of commercial RISC-V processor IP, launched the industry’s first Linux-capable RISC-V based processor SoC. The company demonstrated the first real-world use of the HiFive Unleashed board featuring the Freedom U540 SoC, based on its U54-MC Core IP, at the FOSDEM open source developer conference on Saturday. \n\nDuring the session, SiFive provided updates on the RISC-V Linux effort, surprising attendees with an announcement that the presentation had been run on the HiFive Unleashed development board. With the availability of the HiFive Unleashed board and Freedom U540 SoC, SiFive has brought to market the first multicore RISC-V chip designed for commercialization, and now offers the industry’s widest array of RISC-V based Core IP.\n\n“This is truly a historic moment and a major milestone for RISC-V,” said Yunsup Lee, co-founder and CTO, SiFive. “From the first days of inventing RISC-V, Andrew, Krste, and I have been anticipating this moment. As the leading champions of the RISC-V ISA, we’re proud to debut the HiFive Unleashed board to inspire new innovations and experience this record achievement for the RISC-V community.”\n\nWith the Freedom U540, the first RISC-V based, 64-bit 4+1 multicore SoC with support for full featured operating systems such as Linux, the HiFive Unleashed development board will greatly spur open-source software development. The underlying CPU, the U54-MC Core IP, is ideal for applications that need full operating system support such as artificial intelligence, machine learning, networking, gateways and smart IoT devices.\n\nThe company also announced its first hackathon, which will be held during the [Embedded Linux Conference](https://events.linuxfoundation.org/events/elc-openiot-north-america-2018/), March 12 to 14 in Portland, Ore. The hackathon will enable registered SiFive Developers to be among the first test out SiFive’s HiFive Unleashed board featuring the U540 SoC.\n\nFreedom U540 processor specs include:\n\n* 4+1 Multi-Core Coherent Configuration, up to 1.5 GHz\n* 4x U54 RV64GC Application Cores with Sv39 Virtual Memory Support\n* 1x E51 RV64IMAC Management Core\n* Coherent 2MB L2 Cache\n* 64-bit DDR4 with ECC\n* 1x Gigabit Ethernet\n* Built in 28nm process technology\n\nThe HiFive Unleashed development board specs include:\n\n* SiFive Freedom U540 SoC\n* 8GB DDR4 with ECC for serious application development\n* Gigabit Ethernet Port\n* 32MB Quad SPI Flash\n* MicroSD Card for removable storage\n* FMC Connector for future expansion with add-in cards\n\nDevelopers can [purchase the HiFive Unleashed development board](/boards/hifive-unleashed). A limited batch of early access boards will ship in late March 2018, with a wider release in June. \n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit \n[www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (646) 756-3713\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"YH7vBRMAACEA9qrd","uid":"renesas-and-sifive-partner-to-jointly-develop-next-generation","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YH7vBRMAACEA9qrd%22%29+%5D%5D","tags":[],"first_publication_date":"2021-04-21T13:00:00+0000","last_publication_date":"2022-08-09T21:49:54+0000","slugs":["renesas-and-sifive-partner-to-jointly-develop-next-generation-high-end-risc-v-solutions-for-automotive-applications"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications","spans":[]}],"publish_to":"Archive","publish_date":"2021-04-21","share_image":{"link_type":"Media","kind":"image","id":"YH7wIxMAACAA9qyR","url":"https://images.prismic.io/sifive/be371a14-8256-41ea-88bd-07543f834fcc_Renesas+SiFive+RISC-V+PR-en.jpg?auto=compress,format","name":"Renesas SiFive RISC-V PR-en.jpg","size":"263045","width":"1920","height":"1080"},"body":[{"type":"preformatted","text":"**SiFive to License Industry-Leading RISC-V Core IP Portfolio to Renesas**\n\n**TOKYO, Japan, and SAN MATEO, Calif., April 21, 2021** – [Renesas Electronics Corporation](https://www.renesas.com/us/en) ([TSE:6723](http://www.jpx.co.jp/english/)), a premier supplier of advanced semiconductor solutions, and [SiFive, Inc.](https://www.sifive.com), the industry leader in RISC-V processors and silicon solutions, today announced a strategic partnership to jointly develop next-generation, high-end RISC-V solutions for automotive applications. The partnership will also include SiFive licensing the use of their RISC-V core IP portfolio to Renesas. \r\n\r\n“RISC-V is an important element in providing additional capabilities and options for new and existing customers,” said Takeshi Kataoka, Senior Vice President, General Manager of Automotive Solution Business Unit at Renesas. “We are very excited to work with SiFive as their lead partner to develop next-generation semiconductor solutions through the collaboration of our accumulated expertise in the automotive field, and SiFive’s high-end RISC-V technologies.” \r\n \r\n“We are excited to collaborate with Renesas to develop next-generation automotive solutions powered by the SiFive Intelligence platform,” said Patrick Little, Chairman and CEO, SiFive. “Our roadmap of advanced, high-performance RISC-V processor cores and AI accelerators will deliver significant core performance increases with the capabilities needed to meet Automotive application requirements, along with enhanced AI capabilities to power scalable, workload-accelerated solutions.” \r\n\r\nRenesas provides automotive solutions including ADAS, Autonomous Driving (AD), Electric Vehicles (EV), and Connected Gateway (CoGW) to customers all over the world by utilizing its diverse portfolio of industry-leading microcontrollers (MCUs) and system-on-chips (SoCs), as well as analog and power products. With a safe, comfortable, and environmentally-conscious society of future mobility in mind, Renesas is exploring the use of next-generation, high-performance RISC-V cores optimized for automotive applications to expand high-end SoC and MCU development capabilities to continue providing innovative and trusted automotive solutions to customers worldwide.\r\n\r\nThe SiFive Intelligence platform, based on SiFive RISC-V Vector processors with AI ISA extensions, features a differentiated software toolchain to enable the development of scalable solutions for AI and ML applications. SiFive RISC-V processors are pre-integrated with advanced trace, debug, and security solutions compatible with industry tools to simplify heterogeneous integration and migration. The SiFive RISC-V portfolio is silicon-proven and available in leading and advanced manufacturing foundries, offering flexibility for customers and partners. \r\n\r\n**About Renesas Electronics Corporation**\u003cbr/\u003e\r\nRenesas Electronics Corporation ([TSE: 6723](http://www.jpx.co.jp/english/)) delivers trusted embedded design innovation with complete semiconductor solutions that enable billions of connected, intelligent devices to enhance the way people work and live. A [global](https://www.renesas.com/us/en/about/company/profile/global.html) leader in microcontrollers, analog, power, and SoC products, Renesas provides comprehensive solutions for a broad range of automotive, industrial, Infrastructure, and IoT applications that help shape a limitless future. Learn more at [renesas.com](https://www.renesas.com/). Follow us on [LinkedIn](https://www.linkedin.com/company/renesas/), [Facebook](https://www.facebook.com/RenesasElectronics/), [Twitter](https://twitter.com/renesasglobal), and [YouTube](https://www.youtube.com/user/RenesasPresents).\u003cbr/\u003e\r\n\r\n\r\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, AI accelerators, and SoC IP to enable domain-specific designs based on the open RISC-V instruction set architecture specification. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\r\n(Remarks) All names of products or services mentioned in this press release are trademarks or registered trademarks of their respective owners.\u003cbr/\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\r\nKyoko Okamoto\u003cbr/\u003e\r\nRenesas Electronics Corporation\u003cbr/\u003e\r\n(+)81-3-6773-3001 (Japan)\u003cbr/\u003e\r\nkyoko.okamoto.sx@renesas.com\u003cbr/\u003e\n\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications for SiFive\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e\r\n","spans":[]}]}},{"id":"Ya1jdhEAACIAx9Y6","uid":"sifive-expands-and-improves-industry-leading-risc-v","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Ya1jdhEAACIAx9Y6%22%29+%5D%5D","tags":[],"first_publication_date":"2021-12-06T13:59:56+0000","last_publication_date":"2022-08-09T21:47:04+0000","slugs":["sifive-expands-and-improves-industry-leading-risc-v-processor-portfolio"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Expands and Improves Industry-Leading RISC-V Processor Portfolio","spans":[]}],"publish_to":"Archive","publish_date":"2021-12-06","share_image":{"link_type":"Media","kind":"image","id":"Ya1jcREAAB8Ax9Yj","url":"https://images.prismic.io/sifive/f65f06ea-f530-4b73-a8d0-abe3e97e5e9d_SiFive21G3-promo.png?auto=compress,format","name":"SiFive21G3-promo.png","size":"288912","width":"1080","height":"810"},"body":[{"type":"preformatted","text":"**The SiFive 21G3 Release introduces the new SiFive Essential 6-Series range of RISC-V processors for area-focused computing applications**\n\n**SAN MATEO, Calif., December 2, 2021** – [SiFive, Inc.](https://www.sifive.com), the founder and leader of RISC-V computing, today announced the availability of the SiFive 21G3 release, a comprehensive suite of product updates for the industry’s broadest and most successful RISC-V processor IP portfolio, and introduced the new SiFive Essential™ 6-Series range of RISC-V processor IP to address market demands for mid-range application capable and real-time processors. With the new SiFive Essential 6-Series, SiFive stretches further its leadership position in delivering the broadest portfolio of RISC-V processors to the market. The SiFive product portfolio scales from performance-leading state-of-the-art processors down to the most power-sensitive deeply embedded microcontrollers.\u003c/br\u003e \r\n\r\nThe new product line includes SiFive Essential U6, S6, and E6 processors to offer 64-bit Linux-capable, 64-bit real-time, and 32-bit real-time processors, respectively. SiFive Essential 6-Series processors leverage the widely-used and silicon-proven nature of the SiFive Essential™ 7-Series architecture and feature pre-configured product specifications that may be tuned towards applications such as general-purpose embedded, industrial, IoT, high-performance real-time embedded, and automotive applications.\u003c/br\u003e \r\n\r\nAcross the entire SiFive portfolio, the SiFive 21G3 Release introduces improved clock gating and power management, and adds SiFive Shield™ WorldGuard support to the Essential family. Additionally, SiFive Intelligence Extensions, as utilized by the SiFive Intelligence™ X280, now supports BFLOAT16 compute, quantization acceleration, and features improved multi-cluster support, to deliver significant performance improvements across a wide range of machine learning workloads. The SiFive Performance™ family now features the RISC-V Hypervisor extension.\u003c/br\u003e \r\n\r\n“The SiFive 21G3 release demonstrates SiFive’s commitment to relentless innovation and continuous improvement,” said Chris Jones, Vice President of Products, SiFive. “The new SiFive Essential 6-Series focuses our offerings for mid-range performance, and enacts our vision for comprehensive processor solutions across all application domains. The SiFive Essential 6-Series, along with significant performance and feature enhancements to the Intelligence and Performance Series of products, solidifies SiFive’s standing as the leader in RISC-V.”\u003c/br\u003e\r\n\r\n“SiFive’s introduction of its 6-Series processor cores expands the company’s 'Essential' family of processor cores and creates an even more comprehensive offering of application-tuned, 64- and 32-bit RISC-V processor cores, starting with high-end, multi-core application processors and extending all the way down to individual, low-power, embedded microcontrollers, which can all be customized to cover an even broader design spectrum.” – Steve Leibson, Principal Analyst, TIRIAS Research\u003c/br\u003e\n\nDrew Barbier, Senior Director of Product Marketing, will discuss more details of the SiFive Essential 6-Series and SiFive 21G3 release in a presentation at the [RISC-V Summit 2021](https://events.linuxfoundation.org/riscv-summit/register/), held December 6-8 in-person at the Moscone Center, and online.\u003c/br\u003e \r\n\n**About SiFive**\u003cbr/\u003e\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\r\nKristine Parker\u003cbr/\u003e\r\nINK Communications for SiFive\u003cbr/\u003e\r\n413.233.7860\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e","spans":[]}]}},{"id":"YafZYREAACEAr2Qe","uid":"sifive-raises-risc-v-performance-bar-with-new-best-in-class","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YafZYREAACEAr2Qe%22%29+%5D%5D","tags":[],"first_publication_date":"2021-12-02T14:00:00+0000","last_publication_date":"2022-08-09T21:47:46+0000","slugs":["sifive-raises-risc-v-performance-bar-with-new-best-in-class-sifive-performance-p650-processor"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Raises RISC-V performance bar with New Best-in-Class SiFive Performance P650 Processor","spans":[]}],"publish_to":"Archive","publish_date":"2021-12-02","share_image":{"link_type":"Media","kind":"image","id":"YafcExEAACEAr26u","url":"https://images.prismic.io/sifive/2980fa8f-a8a1-4175-9fd9-8cbf6d8719d0_SiFivePerformanceP650-2.png?auto=compress,format","name":"SiFivePerformanceP650-2.png","size":"228197","width":"1080","height":"607"},"body":[{"type":"preformatted","text":"**The SiFive Performance P650 processor is expected to be the fastest licensable RISC-V processor IP core in the market, bringing RISC-V into new markets and applications, and will debut to lead partners in Q1 2022.**\n\n**SAN MATEO, Calif., December 2, 2021** – [SiFive, Inc.](https://www.sifive.com), the founder and leader of RISC-V computing, today announced the availability of the SiFive Performance™ P650 processor, the new range-topping member of the SiFive Performance family, which is expected to be the fastest licensable RISC-V processor IP core in the market. The SiFive Performance P650 will enable RISC-V designs for performance-demanding application processor markets from data center to edge, automotive, compute, mobile and more.\u003cbr/\u003e \r\n\r\n“SiFive’s mission is to answer the semiconductor industry’s call for more processor IP choices. SiFive is singularly focused on bringing innovative processor technology based on the RISC-V architecture to market,” said Dr. Yunsup Lee, co-founder and CTO, SiFive. “Since the announcement of the Performance Series of RISC-V cores earlier this year, SiFive has continued to push the limits of what was previously possible with RISC-V. The SiFive Performance P650 processor IP represents our commitment towards relentless execution, delivering significant performance improvements in record time. This announcement is the next step towards our long-term vision of bringing RISC-V processors to all performance-hungry applications.\"\u003cbr/\u003e\r\n\r\nThe SiFive Performance P650 processor builds upon the SiFive Performance P550 processor, maintaining an efficient core pipeline while expanding the processor instruction-issue width to deliver an impressive 40% performance increase per clock cycle(1). Additional architecture enhancements improve maximum clock frequency, achieving an overall 50% performance gain compared to SiFive’s previous fastest processor. With a projected score of 11+ SPECInt2006/GHz, the SiFive Performance P650 brings RISC-V into a new category of high-end computing applications. The SiFive Performance P650 is scalable to sixteen cores using a coherent multicore complex, complete with essential system components such as platform-level memory management and interrupt control units, and supports the new RISC-V hypervisor extension for virtualization. SiFive will offer an “Architecture Preview” to select lead customers, for evaluation of the SiFive Performance P650 ahead of general availability.\u003cbr/\u003e \r\n\r\n“The introduction of the SiFive Performance P650 processor IP, coming so quickly on the heels of the SiFive Performance P550 processor, shows how devoted SiFive is to driving the RISC-V processor architecture deep into the data center and applications with similar high-performance requirements,“ said Steve Leibson, Principal Analyst at TIRIAS Research. “The company’s announced plans for 16-core, coherent processor complexes based on this IP will deliver considerable computing performance and requires the commitment of significant development resources, which are simply out of reach for many other companies playing in the RISC-V processor IP arena.”\u003cbr/\u003e\n\r\n“With the new SiFive Performance P650 processor, SiFive’s engineering team has rapidly and successfully delivered a significant performance uplift for the SiFive processor family,” said Rohit Kumar, Senior Vice President of Engineering, SiFive. “SiFive’s rapid execution and expertise is on display as we build world-class products and serve high-performance markets. At SiFive, we’re determined to push the envelope of performance and demonstrate RISC-V has no limits, and the SiFive Performance P650 is the next step in a far-reaching product development roadmap.”\u003cbr/\u003e \r\n\r\nThe SiFive Performance P650 Architecture Preview will be offered to lead customers in Q1 of 2022 with general availability coming mid-year. Dr. Lee will discuss future product direction and the SiFive Performance P650 during a keynote presentation at the upcoming [RISC-V Summit 2021](https://events.linuxfoundation.org/riscv-summit/register/), held December 6-8 in-person at the Moscone Center, and online.\u003cbr/\u003e \r\n\r\n**About SiFive**\u003cbr/\u003e\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\r\n(Remarks) All names of products or services mentioned in this press release are trademarks or registered trademarks of their respective owners.\u003cbr/\u003e\n\n(1) – Based on SiFive engineering estimated performance in SPECInt2006/GHz\n\n**Media Contact**\u003cbr/\u003e\r\nKristine Parker\u003cbr/\u003e\r\nINK Communications for SiFive\u003cbr/\u003e\r\n413.233.7860\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e","spans":[]}]}},{"id":"YFFNxBEAACUACwXl","uid":"sifive-and-architek-enable-secure-private-flexible","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YFFNxBEAACUACwXl%22%29+%5D%5D","tags":[],"first_publication_date":"2021-03-18T13:00:05+0000","last_publication_date":"2022-08-09T21:51:14+0000","slugs":["sifive-and-architek-enable-secure-private-flexible-edge-ai-computing-with-aionic-processor"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and ArchiTek Enable Secure, Private, Flexible Edge AI Computing With AiOnIc® Processor","spans":[]}],"publish_to":"Archive","publish_date":"2021-03-18","share_image":{"link_type":"Media","kind":"image","id":"YFFNCxEAACUACwK6","url":"https://images.prismic.io/sifive/c65b08d2-71ff-4d97-ac59-195c1568e958_architek-aipe-031821.png?auto=compress,format","name":"architek-aipe-031821.png","size":"1093782","width":"1000","height":"655"},"body":[{"type":"preformatted","text":"*New Edge AI processor accelerates key workloads while offering flexibility for changing AI needs*\n\n**SAN MATEO, Calif. – March 18, 2021** – [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, and Osaka R\u0026D venture ArchiTek Corporation today announced ArchiTek’s first in-house developed AI processor, AiOnIc®, featuring the ArchiTek Intelligence® Pixel Engine (aIPE), and SiFive E3-Series RISC-V processor Core IP. The ArchiTek AiOnIc® chip is developed to demonstrate an edge AI concept of processing sensor data in real-time to create meta-data for reduced latency of AI inference processing while offering increased security and privacy.\u003cbr/\u003e\r\n\r\n“The ArchiTek AiOnIc® processor featuring ArchiTek aIPE offers support for different algorithms by dynamically rebalancing hardware use, combining the advantages of CPUs, GPUs, and dedicated LSIs,” said Shuichi Takada, CEO \u0026 CTO of ArchiTek. “SiFive E3-Series Core IP enabled us to hit our performance, power, and area targets, while SiFive Core Designer and SiFive partner DTS-Insight helped reduce our development time.”\u003cbr/\u003e\n\r\n“Edge AI is a massive opportunity for new architectures that can deliver low-power, area-optimized designs,” said Chris Lattner, President of Engineering \u0026 Product, SiFive. “The power of SiFive RISC-V Core IP combined with AI accelerators and other compute elements enable the flexibility and programmability needed for shifting AI applications.”\u003cbr/\u003e\n\r\nThe ArchiTek AiOnIc® architecture was designed for use in Edge AI applications, offering a low-power, high-efficiency chip that enables fanless designs, suitable for harsh environments. The aIPE architecture reduces processing time for Simultaneous Localization and Mapping (SLAM), reducing processing time to 1/20th of the time seen for general-purpose CPUs, and improves the operating speed of perceptual computing using OpenPose for human pose estimation by 3.8X vs. GPUs. The dynamic configuration capabilities of the AiOnIc chip enable various algorithms to be supported and can be used for autonomous vehicles, cybersecurity systems, robotics, and security cameras.\u003cbr/\u003e\n\r\nThe ArchiTek AiOnIc® processor includes built-in engines for signal processing, general-purpose sort, multi-functional DMA, inverse matrix operation, fast Fourier transforms (FFT), general-purpose matrix multiply-add, and a high-performance general-purpose GPU. The processor is built using TSMC 12nm N12FFC process technology, with a die size of 4.5mm x 4.5mm. The chip features the SiFive E3-Series processor core, a 32-bit RISC-V processor with 5-stage pipeline configured to include hardware floating-point unit. The AiOnIc® processor also features an 8MB SRAM, DDR4, Ethernet, UART, I2C, and other standard interfaces. SiFive Core IP has been adopted worldwide and is available in products by leading technology companies including BeagleBoard, Bouffalo Lab, Coherent Logix, eTopus, Innovium, FADU, Huami, MicroChip, Synaptics, Qualcomm, Samsung, and Tynker with BBC Learning.\u003cbr/\u003e\n\r\nThe Architek AiOnIc® proof of concept silicon demonstrates the versatility and programming capabilities of the chip to address the requirements of modern AI solutions and opens the door to deliver the promise of AR, VR, smart cities and countless other 21st century use cases by proliferating AI on the Edge.\u003cbr/\u003e\n\r\n**About ArchiTek**\u003cbr/\u003e\r\nArchiTek Corporation is a start-up venture engaged in the research and development of simple and beautiful architecture and algorithms. It is developing Edge AI processors that will form the nucleus of digital transformation in the areas of smart cities, smart factories, smart retail and smart agriculture. These results from research commissioned by New Energy and Industrial Technology Development Organisation (NEDO), a Japanese government agency. Formed in 2011, ArchiTek aims to expand from Japan into the global market as a platform for AI technology. For more details, please see our website at [architek.ai](https://www.architek.ai).\u003cbr/\u003e\r\n\r\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\n\r\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e\n203.858.7259\u003cbr/\u003e\r\n","spans":[]}]}},{"id":"YG5LFhIAACQAoM8C","uid":"sifive-intelligence-for-modern-ml-architectures-presentation","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YG5LFhIAACQAoM8C%22%29+%5D%5D","tags":[],"first_publication_date":"2021-04-08T14:12:02+0000","last_publication_date":"2022-08-09T21:50:20+0000","slugs":["sifive-intelligence-for-modern-ml-architectures-presentation-at-linley-spring-processor-conference"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Intelligence for Modern ML Architectures Presentation at Linley Spring Processor Conference","spans":[]}],"publish_to":"Archive","publish_date":"2021-04-08","share_image":{"link_type":"Media","kind":"image","id":"YG5P-hIAACQAoOSK","url":"https://images.prismic.io/sifive/50cf1edb-4166-432e-b9cb-2f73a8b8d455_sifivelinleyapr2021.png?auto=compress,format","name":"sifivelinleyapr2021.png","size":"471807","width":"1000","height":"531"},"body":[{"type":"preformatted","text":"**Leading provider of RISC-V processor IP to share details of new initiatives for AI-enabled markets**\n\n**SAN MATEO, Calif. – April 8, 2021** – [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Dr. Chris Lattner, President of Engineering and Product, will present at the technology industry’s premier processor conference, the Linley Spring Virtual Processor Conference, on Friday, April 23. Dr. Lattner will discuss the benefits of SiFive Intelligence to meet the changing needs of modern machine-learning workloads and creating accelerated processing platforms.\u003cbr/\u003e\r\n\r\nA recent Linley Group study found that growth in edge devices and embedded systems continues to fuel the acceleration of AI. Tremendous progress has been made in the last year in preparing the RISC-V vector extensions for market readiness in both hardware implementations and supporting software toolchains that enable AI applications. SiFive has gone a step further with the development of new AI-focused instructions specifically tuned for the acceleration of common machine learning processing. The presentation will demonstrate how these new instructions enable high-performance, low-power inference applications. SiFive Intelligence solutions incorporate multicore, Linux-capable, RISC-V microarchitecture processors with scalable RVV 1.0-specification vector lengths, and provide TensorFlow Lite support.\u003cbr/\u003e\r\n\r\n“SiFive’s vision is to take a ‘software-first’ approach to its SiFive Intelligence products, delivering flexible acceleration strategies that scale with the evolving nature of AI,” said Chris Lattner, President of Engineering and Product, SiFive. “RISC-V provides an open specification, making it easier for software to communicate with hardware and encouraging developer creativity. This is a transformative moment, as SiFive expands its presence in the AI space with SiFive Intelligence platforms for the next generation of automotive, mobile, IoT, 5G networking, and data center computing solutions.”\u003cbr/\u003e\n\r\n\"AI has generated an explosion of silicon-architecture diversity, as evidenced by our Linley Spring Processor Conference program. Our biggest spring program yet will include new technology disclosures and product announcements from both startups and established semiconductor, and IP vendors,\" said Bob Wheeler, principal analyst and conference chairperson. \"Following the success of our 2020 virtual conferences, which achieved record attendance, we are excited to once again be sharing these presentations with a global audience via our live-streamed format.”\u003cbr/\u003e\n\r\nThe RISC-V ecosystem is growing rapidly as more leading technology companies invest in RISC-V hardware and software development, optimizing their technology roadmaps and product development. SiFive Core IP has been adopted worldwide and is available in products by leading technology companies including Architek, BBC Learning, BeagleBoard, Bouffalo Lab, Coherent Logix, eTopus, Innovium, FADU, Huami, MicroChip, Qualcomm, Samsung, and Synaptics.\u003cbr/\u003e\n\r\nRecently, SiFive [announced](https://www.sifive.com/blog/sifive-collaborates-with-new-intel-foundry-business) that SiFive RISC-V IP will be available to customers of Intel Foundry Service business, for building next-generation heterogeneous compute platforms with Intel leading-edge technology and demonstrating the industry-wide support and adoption of RISC-V. The SiFive Core IP portfolio was recently updated with the introduction of the 21G1 release that delivers important enhancements and new capabilities. More information on the SiFive 21G1 release can be found in our blog, [here](https://www.sifive.com/blog/sifive-core-ip-21g1).\r\n\u003cbr/\u003e\n\r\nThe Linley Spring Processor Conference will be held April 19 – 23 and will feature 28 live-streamed presentations addressing processors and IP cores for AI applications, embedded, data center, automotive, and IoT designs. Attendees will be able to participate in the virtual forum which runs Monday – Friday from 8:30 a.m.–12:40 p.m. PDT. The conference includes opportunities for attendees to interact with the speakers during Q\u0026A and breakout sessions. Dr. Lattner will present on Friday, April 23 during Session 8: Edge AI (part II) running from 8.30 a.m. – 10 a.m. PDT. SiFive is a Gold sponsor of the event.\r\n\u003cbr/\u003e\n\r\nTo register, please visit [Linleygroup.com/SPC21](https://linleygroup.com/SPC21). Registration is free for qualified attendees. To learn more about SiFive Intelligence and the integration of vector processing software and hardware in a single-ISA processor core, visit our website [here](https://www.sifive.com/blog/sifive-intelligence-at-linley-spring).\u003cbr/\u003e\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\n\r\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e\n203.858.7259\u003cbr/\u003e","spans":[]}]}},{"id":"YrnlTBEAACIAcuu4","uid":"sifive-expands-global-operations-opens-uk-rd-center","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YrnlTBEAACIAcuu4%22%29+%5D%5D","tags":[],"first_publication_date":"2022-06-28T13:00:04+0000","last_publication_date":"2022-08-08T21:55:17+0000","slugs":["sifive-expands-global-operations-opens-uk-rd-center-in-cambridge"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Expands Global Operations, Opens UK R\u0026D Center in Cambridge","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-06-28","share_image":{"link_type":"Media","kind":"image","id":"Ydc3XBEAACEAKeGy","url":"https://images.prismic.io/sifive/128301dd-264d-44ca-8789-433a5ed0d110_ABOUT_Gallery_Group2B.png?auto=compress,format","name":"ABOUT_Gallery_Group2B.png","size":"1979413","width":"2548","height":"1222"},"body":[{"type":"preformatted","text":"*Leading RISC-V innovator investing in people, community, and Cambridge, with plans to hire more than 100 within two years*\n\n**San Mateo, Calif. and Cambridge, UK, June 28, 2022** - SiFive, Inc., the founder and leader of RISC-V computing, today announced the opening of its new UK Research \u0026 Development (R\u0026D) Center headquartered in Cambridge, United Kingdom. SiFive is committed to hiring more than 100 new employees across many roles and positions. This is an exciting opportunity for local Cambridge talent to be part of SiFive’s founding team in the UK, to make an impact today, and define the technologies of tomorrow. \r\n\r\n“The market demand for SiFive’s leading RISC-V cores is unprecedented, providing an incredible opportunity for both seasoned and up-and-coming talent to join us in delivering innovative solutions to customers who represent an elite list of leading global technology brands. As part of our global expansion, we’re proud to open our UK R\u0026D Center in Cambridge to access the considerable local technical talent, especially CPU experts,” said Patrick Little, CEO and Chairman, SiFive. “We offer a chance to work alongside true industry pioneers to develop critical technology that is fundamentally changing the way the semi industry does business. With long-term plans to grow talent and teams in Cambridge and across the UK, we are looking for employees who want to make an impact, working on some of SiFive’s highest performance products. It’s a great chance to join us early in our growth in the UK and beyond.” \r\n \r\n“Overseas investment supports jobs and boosts local economies across the UK, playing an important role in this government’s Levelling Up agenda. SiFive’s UK expansion is both a strong example of this and a major vote of confidence in our thriving $1 trillion tech sector, cementing the UK as a tech and science superpower,” said Minister for Investment, Lord Grimstone. “This investment is a fantastic opportunity to be part of SiFive’s growing team in the UK and work alongside the co-creators of RISC-V, and is a great compliment to the UK and its future.”\r\n \r\n\"Our workforce has some of the brightest minds in technology and our region is a dynamic, exciting place to do business. I’m delighted to see more world-class technology companies – such as SiFive – drawn to Cambridge to open new research centers and support jobs and opportunity in our region and for our communities. Once again our dedicated Growth Works inward investment service has played an important role in helping another globally competitive tech company choose our region as a place to invest,” said Dr Nik Johnson, Mayor of Cambridgeshire and Peterborough. \r\n\r\nSiFive’s new R\u0026D operation underscores its accelerated momentum and growth across the globe. The company is on a mission to build the world’s best computing platforms and bring the open standard RISC-V ISA to all by giving designers the tools to deliver differentiated and best-in-class products. In March 2022, SiFive announced its $175M Series F funding round and appointed Nicole Singer as Senior Vice President and Chief Human Resources Officer. With Singer on board, SiFive plans to more than double the company’s global staff across its international offices (U.S. headquarters, France, India, UK, and Taiwan) by 2024. Currently, SiFive is seeking UK and Cambridge-based candidates in CPU design, architecture, verification, software development, sales, and customer experience (CX). A current list of open positions can be found on the SiFive UK careers page: [SiFive.com/careers-uk](https://www.sifive.com/careers-uk).\r\n\r\nFor more information on SiFive’s market-leading RISC-V IP portfolio, please visit SiFive.com.\r\n\n**About SiFive**\u003cbr\u003e\r\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit SiFive.com. \r\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\n\n**Media Contact**\r\n\u003cbr\u003eAllison DeLeo\r\n\u003cbr\u003eRacepoint Global for SiFive\r\n\u003cbr\u003e[SiFive@racepointglobal.com](mailto:SiFive@racepointglobal.com)\r\n\u003cbr\u003eTel.: +1 (415) 694-6711\n\r\n\n\r\n","spans":[]}]}},{"id":"YrDZmREAACQAS_o3","uid":"sifive-enhances-popular-x280-processor-ip-to-meet-accelerated","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YrDZmREAACQAS_o3%22%29+%5D%5D","tags":[],"first_publication_date":"2022-06-21T12:00:04+0000","last_publication_date":"2022-08-08T21:54:12+0000","slugs":["sifive-enhances-popular-x280-processor-ip-to-meet-accelerated-demand-for-vector-processing"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Enhances Popular X280 Processor IP to Meet Accelerated Demand for Vector Processing","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-06-21","share_image":{"link_type":"Media","kind":"image","id":"Yo_bdxAAACAAGbXk","url":"https://images.prismic.io/sifive/0bbdc08b-9aa2-44f3-88ce-f94e7e97bc10_sifive-vectors-card-big-logo.png?auto=compress,format","name":"sifive-vectors-card-big-logo.png","size":"14842","width":"780","height":"440"},"body":[{"type":"preformatted","text":"*Leading performance for AI inference, Image Processing, and Datacenter applications driving double-digit design wins*\n\n**San Mateo, Calif., June 21, 2022** – [SiFive Inc.](https://www.sifive.com), the founder and leader of RISC-V computing, today announced the release of the latest version of its SiFive® Intelligence™ X280 processor, which introduces significant new features including scalability up to a 16-core cache-coherent complex, WorldGuard trusted protection, and a new interface allowing for seamless integration between the X280 vector unit and customer-designed external AI accelerators or other coprocessors, called VCIX (Vector Coprocessor Interface eXtension). Collectively, these enhanced features deliver unmatched scalability, security, and interoperability to the SiFive X280, the most widely adopted implementation of the RISC-V Vector extension. This latest version of the X280 is a powerful solution for those looking for alternatives to legacy SIMD-style architectures.\r\n\r\nPublicly available since April 2021, the SiFive Intelligence X280 has seen rapid adoption as customers gravitate towards its unique combination of performance, power efficiency, and an intuitive programming model. The X280 has claimed double-digit design wins in the past six months alone, in a wide variety of data-driven applications, including AI inference, image processing, datacenter acceleration, and automotive use cases.\r\n\r\n“The market feedback about our X280 has been nothing short of incredible. The product maps extremely well to the needs of the modern workload and vector processing and was introduced at the exact right moment to accelerate RISC-V’s already considerable momentum,” said Chris Jones, VP Product at SiFive. “The new X280 enhancements are a direct result of listening and collaborating with customers and are already designed into multiple sockets around the world. Additionally, the software ecosystem around the RISC-V vector extension is growing exponentially which ensures broad support for customers and is driving the inevitable, wide industry adoption of RISC-V.” \r\n\r\nThe X280 SiFive® Intelligence™ X280 is a multi-core and multi-cluster capable RISC-V processor with full support of the RISC-V vector extension standard and SiFive Intelligence Extensions and is optimized for AI/ML compute at the edge.\r\n\r\nThe X280 is also ideal for applications requiring high-throughput, single-thread performance while under power constraints (e.g., AR, VR, sensor hubs, IVI systems, IP cameras, digital cameras, and gaming devices).\r\nSeveral unique and important new SiFive features include:\r\n \r\n**Multi-cluster**: SiFive has built upon our industry-first multi-cluster RISC-V solution in the X280, which offers up to 4 clusters of 4-core complexes and scaling to multi-TOP performance. \r\n\r\n**VCIX (Vector Coprocessor Interface eXtension)**: This innovative vector coprocessor accelerator interface allows for seamless integration with customer AI architectures including a wide and growing number of 3rd party accelerators, enabling easily programmed, low latency data movement between the host processor and customer owned AI accelerator solutions.\r\n \r\n**WorldGuard Ready**: SiFive’s implementation of the open standard WorldGuard security solution brings a trusted execution environment to high core count platforms to protect your AI/ML algorithm against malicious attacks and offers an alternative to legacy security solutions. \r\n\r\nFor more information about SiFive vector solutions visit [sifive.com/technology/vectors](https://www.sifive.com/technology/vectors). For more information about the SiFive Intelligence X280 visit [sifive.com/cores/intelligence-x280](https://www.sifive.com/cores/intelligence-x280).\n\r\n**About SiFive**\u003cbr\u003e\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit [www.sifive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\n\n[SiFive Fact Sheet](https://prismic-io.s3.amazonaws.com/sifive/d4fe07c1-0242-4bff-a2ec-5e4329904f0e_SiFive+Corporate+Update+Q1+2022+-+Media+%26+Analysts+FINAL.pdf)\r\n\n**Media Contact**\r\n\u003cbr\u003eAllison DeLeo\r\n\u003cbr\u003eRacepoint Global for SiFive\r\n\u003cbr\u003e[SiFive@racepointglobal.com](mailto:SiFive@racepointglobal.com)\r\n\u003cbr\u003eTel.: +1 (415) 694-6711","spans":[]}]}},{"id":"Xeg1mBIAACQAJm8u","uid":"sifive-to-present-new-technologies-at-risc-v-summit","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Xeg1mBIAACQAJm8u%22%29+%5D%5D","tags":[],"first_publication_date":"2019-12-05T00:42:09+0000","last_publication_date":"2022-08-08T21:02:35+0000","slugs":["sifive-to-present-new-technologies-at-risc-v-summit-2019"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive To Present New Technologies At RISC-V Summit 2019","spans":[]}],"publish_to":"Archive","publish_date":"2019-12-04","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Key new technologies for artificial intelligence, automotive, and industrial markets to be unveiled*\n\nSAN MATEO, Calif., Dec. 4, 2019 /PRNewswire/ -- SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced its participation in the premier technology event, RISC-V Summit 2019 held December 10 – 12. SiFive founders, leaders, and RISC-V inventors will present on various topics over the multi-day event held at the San Jose Convention Center in San Jose, California.\r\n\r\nThis year, SiFive Co-Founder and RISC-V Foundation President Krste Asanovic will present the RISC-V state of the union keynote with the latest details and updates. SiFive Co-Founder and CTO Yunsup Lee will present a keynote on taking RISC-V into new markets, including details of upcoming developments from SiFive. Randy Allen, vice president of software development at SiFive, will present the RISC-V software state of the union key session. Dany Nativel, director of SiFive security, will present SiFive Shield, including new details on secure boot using an open, secure platform architecture. Many other panels and technical presentations will be provided by SiFive over the course of the three-day event.\r\n\r\n\"The RISC-V Summit is the premier technology event of the year for companies who want to unlock their roadmap and create high-performance, high-efficiency products,\" said Dr. Naveed Sherwani, president and CEO of SiFive. \"I'm excited to see all the great developments in the ecosystem and unveil our own to continue to push the boundaries of what is possible with domain-specific IP and silicon.\"\r\n\r\nSiFive is a founding platinum member of the RISC-V Foundation, and a Ruby sponsor of the RISC-V Summit 2019. Please visit the SiFive booth at the RISC-V Summit 2019 to see the recently announced SiFive Learn Inventor board in action; it's the world's first RISC-V based IoT device to be qualified for use with Amazon FreeRTOS and AWS IoT Core services. You'll also experience the latest hardware, software, tools, and try out the rapid, simple power of SiFive Core Designer to create your own processor core first-hand.\r\n\r\n## About SiFive\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [visit SiFive.com](https://www.sifive.com/)\n\r\nStay current with the latest SiFive updates via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\r\n\r\nAmazon, Amazon Web Services, and AWS are registered trademarks of Amazon.com, Inc. All brands or product names are the property of their respective holders.\r\n\r\n**Media Contact**\u003cbr\u003e\r\nSara Dodrill\u003cbr\u003e \r\nSHIFT Communications for SiFive\u003cbr\u003e\r\n(415) 591-8429\u003cbr\u003e\r\nsifive@shiftcomm.com\u003cbr\u003e\r\n\n","spans":[]}]}},{"id":"XX-i0BAAACQADdpV","uid":"sifive-to-present-at-linley-fall-processor-conference","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XX-i0BAAACQADdpV%22%29+%5D%5D","tags":[],"first_publication_date":"2019-09-16T16:20:09+0000","last_publication_date":"2022-08-08T21:11:31+0000","slugs":["sifive-to-present-at-linley-fall-processor-conference"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive to Present at Linley Fall Processor Conference","spans":[]}],"publish_to":"Archive","publish_date":"2019-09-16","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*SiFive Keynote and Presentation detail new technology for Intelligence and Security*\n\n**SAN MATEO, Calif. – September 16th, 2019** – [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, announced today that Yunsup Lee, co-inventor of RISC-V, CTO and co-Founder of SiFive, and Dany Nativel, Director, SiFive Security, will present at the Linley Fall Processor Conference in Santa Clara, Calif. The two-day Linley Fall Processor Conference features keynotes and conference presentations from leading technology companies sharing the next-generation processors and IP for AI, IoT, Embedded, and Server designs. \n\n## Scalable IP for High-Performance Configurable SoC Design\n\nThis year, Yunsup Lee will present the latest SiFive Core IP for high-performance processor designs for high-performance configurable SoC designs. The convergence of AI, 5G, and Data Analytics is driving the need for diverse computing solutions in many markets. \n\nIn this keynote, SiFive will detail new, high-performance processor Core IP with significant compute capability enhancements to meet the needs of the New Golden Age of Computing. Modern computing workloads are rapidly evolving to require the ability to scale performance on-demand and have real-time, deterministic requirements which demand scalable solutions beyond what legacy architectures provide. \n\nYunsup Lee is SiFive’s Chief Technology Officer and co-founder. Yunsup received his Ph.D. from UC Berkeley, where he co-designed the RISC‑V ISA and the first RISC-V microprocessors with Andrew Waterman and led the development of the Hwacha decoupled vector-fetch extension. Yunsup also holds an MS in Computer Science from UC Berkeley and a BS in Computer Science and Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST).\n\n## Secure Embedded Processor Design\n\nThe need for secure-by-design processors in embedded systems is rising, requiring a new security architecture based on a holistic view of processor architecture. In this presentation, Dany Nativel, Director of SiFive Security, introduces a new SiFive scalable security architecture that will deliver more than a single trusted world in a configurable SoC design tailored to industry needs.\n\nDany Nativel is the managing director of SiFive France and is responsible for SiFive's platform security, leading a talented team of hardware and software security experts. In the last 20 years in the semiconductor industry, he has held roles tightly connected to security at companies including Maxim Integrated, Innovacard, Atmel (now Microchip), Infineon, and IBM. Dany holds an MS in Electrical Engineering and Computer Science from Pierre and Marie Curie University (UPMC, Paris) and a BS in Electrical Engineering.\n\n“As host of the industry’s premier processor event, I’m thrilled to showcase SiFive’s latest technology innovations,” said Linley Gwenapp, Principal Analyst, Linley Group. “SiFive’s consistent IP innovation and execution to deliver new IP and silicon for key growth markets continues to demonstrate their leadership in the space, and a very welcome presence at the conference.” \n\nThe Linley Fall Processor Conference will take place on October 23 and 24 at the Hyatt Regency, 5101 Great American Parkway in Santa Clara. For more information visit [linleygroup.com](https://www.linleygroup.com/events/event.php?num=47).\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 14 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.\n\n## MEDIA CONTACTS\n\nSara Dodrill \nSHIFT Communications for SiFive \n415-591-8429 \nsdodrill@shiftcomm.com","spans":[]}]}},{"id":"Xeg3-BIAACQAJnnO","uid":"sifive-learn-inventor-development-system-now-aws-qualified","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Xeg3-BIAACQAJnnO%22%29+%5D%5D","tags":[],"first_publication_date":"2019-12-05T00:42:18+0000","last_publication_date":"2022-08-08T21:11:38+0000","slugs":["sifive-learn-inventor-development-system-now-aws-qualified"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Learn Inventor Development System Now AWS Qualified","spans":[]}],"publish_to":"Archive","publish_date":"2019-12-03","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*SiFive RISC-V-based rapid design methodology enables fast development of IoT devices connected to AWS*\u003cbr/\u003e\n\n*11/19/20 The SiFive Learn Inventor is Discontinued*\n\r\n*SAN MATEO, Calif., Dec. 3, 2019* -- SiFive, Inc., a leading provider of commercial RISC-V processor IP and silicon solutions, announced today the SiFive Learn Inventor Development System is now recognized as an Amazon FreeRTOS-qualified device, one of the leading-edge RISC-V based devices to receive this status. This product heralds another step forward in SiFive's vision to enable companies to rapidly create new market-focused devices customized to their target application workload requirements. Amazon FreeRTOS devices can connect directly to services from Amazon Web Services (AWS), like AWS IoT Core.\r\n\r\n## Amazon FreeRTOS Qualification\r\nTo enable this qualification, the Amazon FreeRTOS real-time operating system has been enabled with RISC-V support and paired with a freely available open-source support package. Based on the SiFive FE310 SoC, the SiFive Learn Inventor features the SiFive E31 standard core supporting the RISC-V RV32IMAFC instruction set, 16KB instruction cache, and 64KB data cache. The SiFive Learn Inventor offers a broad array of interfaces and sensors, including accelerometer, thermometer, compass and ambient light detection, with Wi-Fi and Bluetooth connectivity built-in. Low-power operation is enabled through multiple power domains and a low-power standby mode.\r\n\r\nFollowing the Amazon FreeRTOS qualification process, the SiFive Learn Inventor Development System was tested extensively for Amazon FreeRTOS interoperability, resulting in a qualified device that can be used with AWS IoT Core services to enable reliable, secure and easy interaction of connected devices with cloud applications and other devices.\r\n\r\nAs an Amazon FreeRTOS-qualified RISC-V based device, the SiFive Learn Inventor Development System provides a platform for RISC-V product and software development of Internet-of-Things (IoT) devices connected to AWS IoT Core services. The FE310 SoC and supporting software was created using SiFive's Core Designer and unique methodology; companies wishing to create an AWS-connected SoC optimized for their target application can use Core Designer to generate the appropriate SiFive Core IP. The qualified SiFive Learn Inventor development system serves as a starting point for future designs, enabling them to be simply and easily updated and re-qualified. SiFive's vision is to extend the automatic generation to the software components as well as the IP, accelerating the qualification process.\r\n\r\n## Scalable SiFive RISC-V SoCs for IoT\r\nThe free and open RISC-V instruction set architecture (ISA) is a popular new choice for developing efficient, low-power devices specifically intended for focused IoT market segments. Domain-optimized designs enable fully featured devices without additional legacy ISA burden or unused silicon. With the IoT market projected to scale into a trillion devices in the coming years, domain-specific designs can be enabled with SiFive's ability to quickly and easily create customized, low-power SoCs at scale.\r\n\r\n\"We are excited to see the AWS qualification of a RISC-V-based product as it is an important milestone,\" said Calista Redmond, CEO of RISC-V Foundation. \"The Amazon FreeRTOS qualification gives designers confidence in being able to design RISC-V-based IoT edge computing systems that can take advantage of AWS IoT Core services.\"\r\n\r\nSiFive CEO Naveed Sherwani said: \"The SiFive Learn Inventor Development System qualification for AWS Core IoT services underscores our leadership in RISC-V development and enablement. SiFive's mission is to enable companies to quickly and cost-effectively design custom SoCs. The SiFive Learn Inventor is one of the first RISC-V based AWS Core IoT devices and it continues to deliver on the vision for designers of edge compute IoT SoCs simply and easily connecting to the cloud.\"\r\n\r\nVisit SiFive and see the SiFive Learn Inventor Development System in person at the AWS re:Invent 2019 event, Dec. 3 – 5, Kiosk #2704 at the Sands Expo Hall B, Level 2, at the Venetian Hotel in Las Vegas. SiFive will show multiple demonstrations of applications running on the new SiFive Learn Inventor Development System connected to AWS, including AWS IoT Core, Amazon FreeRTOS, AWS Lambda, Amazon Cognito, Amazon API Gateway, and Amazon Simple Storage Service (Amazon S3).\r\n\r\nThe SiFive Learn Inventor Development System is available for purchase today through pimoroni.com/sifive. Supported with a free, open-source comprehensive software package, the SiFive Learn Inventor will be a valuable tool for developers and researchers to support the rapid adoption of RISC-V based IoT devices.\r\n\r\nOpen-source software for the SiFive Learn Inventor Development System, including the FreeRTOS port, is available for free download today at [https://github.com/sifive/Amazon-FreeRTOS](https://github.com/sifive/Amazon-FreeRTOS)\r\n\r\nMore information on the AWS IoT Core Services supported by the SiFive Learn Inventor board is available at [https://devices.amazonaws.com/detail/a3G0h0000077I8lEAE/SiFive-Learn-Inventor](https://devices.amazonaws.com/detail/a3G0h0000077I8lEAE/SiFive-Learn-Inventor).\r\n\r\n## About SiFive\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital and Western Digital. For more information, [visit SiFive.com](https://www.sifive.com).\r\n\n**Media Contact**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\nsifive@ink-co.com\u003c/br\u003e\r\n203.858.7259\u003cbr/\u003e ","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqu","uid":"esilicon-licenses-industry-leading-sifive-e2-core-ip-for-next-generation-serdes-ip","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqu%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T21:13:05+0000","slugs":["esilicon-licenses-industry-leading-sifive-e2-core-ip-for-next-generation-serdes-ip"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"eSilicon Licenses Industry-Leading SiFive E2 Core IP for Next-Generation SerDes IP","spans":[]}],"publish_to":"Archive","publish_date":"2018-08-07","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. and SAN JOSE, Calif. – August 7, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, and eSilicon, an independent provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, today announced that, after extensive review and testing of available options in the market, eSilicon has selected the SiFive E2 Core IP Series as the best solution for its next-generation SerDes IP at 7nm.\n\neSilicon’s 7nm SerDes IP represents a new breed of performance and versatility based on a novel DSP-based architecture. Two 7nm PHYs support 56G and 112G NRZ/PAM4 operation to provide the best power efficiency tradeoffs for server, fabric and line-card applications. The clocking architecture provides extreme flexibility to support multi-link and multi-rate operations per SerDes lane.\n\n“Today’s high-performance networking applications require the ability to balance power and density to effectively address increasing performance demands,” said Hugh Durdan, vice president of strategy and products at eSilicon. “SiFive’s E2 Core IP allows eSilicon to provide the flexibility and configurability that our customers require while achieving industry-leading power, performance, and area.”\n\nThe SiFive E2 Core IP is designed for markets that require extremely low-cost, low-power computing, but can benefit from being fully integrated within the RISC-V software ecosystem. At one-third the area and one-third the power consumption of similar competitor cores, the SiFive E2 Core series is the natural selection for companies like eSilicon that are looking to address the challenges of advanced ASIC designs.\n\n“eSilicon has a successful track record for leveraging the most advanced technologies to develop high-bandwidth, power-efficient IP for ASIC design,” said Brad Holtzinger, vice president of sales, SiFive. “Our E2 Core Series IP takes advantage of the inherent scalability of RISC-V to bring the highest performance possible to the demands of advanced ASICs. We look forward to working with eSilicon on its next-generation SerDes to address these demands.”\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom, Western Digital and Intel Capital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## About eSilicon\n\neSilicon is an independent provider of complex FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete 2.5D/HBM2 and TCAM platforms for FinFET technology at 16/14/7nm as well as SerDes, specialized memory compilers and I/O libraries. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. [www.esilicon.com](https://www.esilicon.com?utm_source=pr\u0026utm_medium=marketwirebaydistro\u0026utm_campaign=sifive-e2-20180731)\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Sally Slemons\u003cbr\u003e\n eSilicon Corporation\u003cbr\u003e\n (408) 635-6409\u003cbr\u003e\n sslemons@esilicon.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"XRZgIBIAACAAsBk6","uid":"sifive-expands-designshare-ip-ecosystem-to-20-partner","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XRZgIBIAACAAsBk6%22%29+%5D%5D","tags":[],"first_publication_date":"2019-07-01T14:10:59+0000","last_publication_date":"2022-08-08T21:15:11+0000","slugs":["sifive-expands-designshare-ip-ecosystem-to-20-partner-companies"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Expands DesignShare IP Ecosystem to 20 Partner Companies","spans":[]}],"publish_to":"Archive","publish_date":"2019-07-01","share_image":{"link_type":"Media","kind":"image","id":"XRqiEBIAACEAwr7o","url":"https://images.prismic.io/sifive%2F68f8630c-5350-4c5f-ad0b-2bafaad6141d_designshare-diagram.png?auto=compress,format","name":"designshare-diagram.png","size":"81847","width":"691","height":"456"},"body":[{"type":"preformatted","text":"*Signature third-party IP ecosystem allows low-cost, rapid prototyping and innovative IP licensing for AI, edge computing*\n\n\r\n## SAN MATEO, Calif., - July 1, 2019 –\n\n[SiFive](https://c212.net/c/link/?t=0\u0026amp;l=en\u0026amp;o=2513916-1\u0026amp;h=3772567767\u0026amp;u=https%3A%2F%2Fwww.sifive.com%2F\u0026amp;a=SiFive), Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, announced today that it has expanded its DesignShare ecosystem to 20 portfolio companies and strengthened the third-party IP available to developers of SoCs designed for use in artificial intelligence (AI) and edge inference. As SoC design and IP costs rise for advanced nodes, SiFive continues to deliver innovative business models in order to democratize access to optimized silicon by improving design efficiency for driving differentiated System-on-Chip (SoC) solutions to market.\r\n\r\nWith the AI silicon market forecast to reach $30 billion by 2023, SiFive is developing AI platforms in leading FinFET nodes for computer vision, edge inferencing and training applications. The deployment of highly optimized silicon at the edge will require the customizability and capabilities afforded by SiFive\u0026#39;s 64-bit RISC-V processors. The cost and effort of acquiring IP for such use cases, however, has traditionally been a high barrier to building new custom SoCs. SiFive\u0026#39;s DesignShare ecosystem addresses these challenges by providing key IP for any silicon engagement as well as selected, tested and integrated IP solutions for targeted applications.\r\n\r\nFollowing its recent announcements of securing over 100 design wins and the introduction of the industry\u0026#39;s first template SoCs, SiFive\u0026#39;s latest DesignShare IP ecosystem additions include cryptographic security solutions, in-chip monitoring, memory compilers, interconnects and controllers, clock management and SerDes. With existing offerings such as GPUs and accelerators, SiFive\u0026#39;s DesignShare ecosystem offers a complete portfolio of leading and differentiating IP for custom SoC and Template SoC development, optimized for AI, IoT and edge inference.\r\n\r\n\u0026quot;AI development is driving semiconductor design in many markets,\u0026quot; said Mohit Gupta, vice president, SoC IP solutions, SiFive. \u0026quot;As we continue to develop complete solutions on advanced FinFET nodes, it is critical to bundle key and differentiating IP from market leaders with our RISC-V core IP and silicon expertise in order to realize the much-needed higher TOPS per milliwatt with low latency performance, while balancing the needs for low power and smaller area footprints. We bring unique capabilities to edge inference use cases and our enhanced DesignShare ecosystem now provides all critical IP for next generation SoCs and accelerators.\u0026quot;\r\n\r\nThe need for highly specialized IP is only deepening with increased silicon specialization for specific workloads and the demand for domain-specific architectures. To meet these needs directly for customers, SiFive has added numerous key offerings to its DesignShare ecosystem, including:\n\n![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2F68f8630c-5350-4c5f-ad0b-2bafaad6141d_designshare-diagram.png)\n\n\r\n- Imagination Technologies for its industry-leading PowerVR GPU and neural network accelerator (NNA), which is needed for computationally intensive graphical and matrix multiplication workloads;\r\n- Savarti for its innovative standard and specialty memory compilers for single and dual port SRAMs and TCAMs that allow for multiple, user-selectable PPA optimization points and comprehensive DFT modes with massive memory libraries for an optimized embedded memory architecture;\r\n- Silicon Creations, which is providing its leading PCIe SerDes as well as its fully integrated and versatile integer and fractional PLLs that allow for advanced clock signal management in very low and ultra-low power conditions with low to ultra-low jitter;\r\n- Openedges, for its bus fabric, OIC — the ORBITTM High Speed On-chip Interconnect IP —which delivers high-performance network-on-chip capability and SoC design flexibility based on an automated end-to-end interconnect generation flow. OIC delivers significant synergy in terms of maximum performance, reduced SoC design efforts and easier post-silicon debugging and tuning. Openedges\u0026#39; Memory Controller, the ORBITTM DDR Memory Controller — OMC, delivers exceptional performance including high utilization and very low latency;\r\n- Moortec is providing its process, voltage and temperature (PVT) monitoring subsystem for embedded sensing solutions. In-chip PVT monitoring is now a key consideration for FinFET designs where it is used to increase SoC performance and reliability, especially in AI and accelerator use cases where sensing die temperature, detecting logic speed and monitoring voltage supply levels to a high accuracy can be used intelligently to dynamically optimize performance for lower power or higher data throughput;\r\n- SiFive is enabling security solutions for differentiated RISC-V based SoC\u0026#39;s and are collaborating with DesignShare ecosystem member SecureRF. SecureRF, a recognized leader in security for small computing platforms, has developed quantum-resistant, public-key security tools for low-resource processors powering IoT devices; SecureRF delivers fast, low-energy and future-proof authentication, identification and data protection solutions for RISC-V based SoCs.\r\n\r\n\u0026quot;With the depth and breadth of our third-party IP portfolio coupled with our highly efficient RISC-V Core IP, we can now truly offer customers and partners a \u0026#39;your block here\u0026#39; solution to advanced AI SoCs,\u0026quot; said Naveed Sherwani, president and CEO, SiFive. \u0026quot;With the leading IP for IoT, edge and AI workloads in our DesignShare ecosystem, we extend deep customization and selection of differentiating IP to our customers to power the latest IP, algorithms and accelerators. Our architectural and implementation expertise allows our customers and partners to focus on their unique capabilities while we improve PPA and provide a fast path to silicon.\u0026quot;\r\n\r\n## About SiFive\n\n\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [www.sifive.com](https://c212.net/c/link/?t=0\u0026amp;l=en\u0026amp;o=2513916-1\u0026amp;h=2470118817\u0026amp;u=http%3A%2F%2Fwww.sifive.com%2F\u0026amp;a=www.sifive.com).","spans":[]}]}},{"id":"Xe6YIhEAAAgIGvRt","uid":"sifive-retains-title-of-most-respected-private-semiconductor","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22Xe6YIhEAAAgIGvRt%22%29+%5D%5D","tags":[],"first_publication_date":"2019-12-09T19:31:31+0000","last_publication_date":"2022-08-08T21:07:39+0000","slugs":["sifive-retains-title-of-most-respected-private-semiconductor-company"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Retains Title of Most Respected Private Semiconductor Company","spans":[]}],"publish_to":"Archive","publish_date":"2019-12-09","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*RISC-V leader honored for second consecutive year for its hypergrowth, products and performance by Global Semiconductor Alliance*\n\nSAN MATEO, Calif., Dec. 9, 2019 /PRNewswire/ -- [SiFive.com](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced it has been recognized for the second consecutive year as the Most Respected Private Semiconductor Company by the Global Semiconductor Alliance (GSA) at the GSA Awards Dinner on Dec. 5, 2019. This recognition tops a milestone year for the company, which announced more than 130 design wins, completed Series D investments to secure over $100M total funding to date and continued to attract the industry's top talent. \r\n\r\n\"SiFive continues to push the boundaries of innovation, driving the semiconductor industry forward,\" said Jodi Shelton, GSA CEO and Co-Founder. \"The private company award is ultimately awarded not by the GSA but its voting membership, so the award is truly a testament to SiFive's reputation among its peers. It's rewarding to see the company's ongoing leadership.\"\r\n\r\nThe GSA Most Respected Private Semiconductor Company award honors companies that garner the most respect from the industry in terms of its products, vision and future opportunities. Since its founding in 2015, SiFive has grown its RISC-V product range of Core IP to 16 distinct 32- and 64-bit standard cores, suitable for use in high-performance, real-time, embedded and Linux application use cases. Most recently, the company announced the SiFive U8 Series Core IP, a configurable superscalar out-of-order design, and the world's first RISC-V OoO processor core IP. SiFive also has attracted an all-star team of key executives and engineers from industry leaders such as Arm, Rambus, Intel and NVIDIA.\r\n\r\n\"Retaining the title of Most Respected Privately Held Company is truly an honor,\" said Naveed Sherwani, CEO and president, SiFive. \"It's rewarding to see the dedication and hard work put forward by everyone at SiFive be recognized by our industry year after year. This recognition will fuel our collective passion to bring new innovations to market as we drive toward 2020. I applaud our team for their efforts to effect change in everything they do.\"\r\n\r\n## About SiFive\r\n\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital and Western Digital. For more information, visit [SiFive.com](https://www.sifive.com).\n\r\nStay current with the latest SiFive updates via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\r\n\r\n## About GSA\r\n\r\nGSA is Where Leaders Meet to establish an efficient, profitable and sustainable semiconductor and high technology global ecosystems encompassing semiconductors, software, solutions, systems, and services. It is a leading industry organization that provides a unique neutral platform for collaboration, where global executives interface and innovate with peers, partners and customers to accelerate industry growth and maximize return on invested and intellectual capital.\r\n\r\nGSA has an impressive global footprint representing over 30 countries and 350 corporate members comprised of top companies in the semiconductor industry. The global membership ranges from the most exciting emerging companies to industry stalwarts and technology leaders—representing 75% of industry revenues. Members value collaboration as a key to the advancement of their companies and industry.\r\n\r\nGSA offers the broadest and most efficient thought-leadership platform through curated regional and global executive and technology events, networking forums, dinners, workshops and working groups. These gatherings allow members to engage in thought leading dialogues shaping the industry, expand business opportunities and remain up-to-date on relevant topical issues, share best practices and gain precious visibility opportunities. GSA members also have access to a repository of data and information including financial reports and resources, company data, surveys and technology and market reports.\r\n\r\nTo learn more about the GSA please visit: [www.gsaglobal.org](https://www.gsaglobal.org/)\n\n**Media Contact**\u003cbr\u003e\r\nSara Dodrill\u003cbr\u003e \r\nSHIFT Communications for SiFive\u003cbr\u003e\r\n(415) 591-8429\u003cbr\u003e\r\nsifive@shiftcomm.com\u003cbr\u003e\r\n","spans":[]}]}},{"id":"XKu25xEAAB4AvsOS","uid":"sifive-to-present-at-leading-ip-processor-conferences","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XKu25xEAAB4AvsOS%22%29+%5D%5D","tags":[],"first_publication_date":"2019-04-08T21:33:57+0000","last_publication_date":"2022-08-08T21:15:04+0000","slugs":["sifive-to-present-at-leading-ip-processor-conferences"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive to Present at Leading IP, Processor Conferences","spans":[]}],"publish_to":"Archive","publish_date":"2019-04-08","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Executives to discuss new business models, optimizing RISC-V based processors and customizing architectures for AI implementations at Design and Reuse IP-SOC day and Linley Group events*\n\n**WHO:** SiFive, the leading provider of commercial RISC-V processor IP, and the following executives:\r\n\r\n- Sunil Shenoy, SVP/GM RISC-V IP BU\n- Yunsup Lee, co-founder and chief technology officer\r\n- Krste Asanovic, co-founder and chief architect\r\n\n**WHAT:** SiFive executives will present at Design and Reuse IP-SOC Day 2019 and the Linley Spring Processor Conference 2019, both in Santa Clara, Calif. As SiFive continues its mission to democratize access to custom silicon, the company will present the following sessions:\r\n\r\n- **Tuesday, April 9 at Design and Reuse, IP-SOC Day** \n - 12:15 p.m. \"IP Democratization: Which Enablers? New Business Model, IP Central or Design Marketplace?\"\r\n - Sunil Shenoy will participate on a panel with executives from Andes Technology Corp., ARM, efabless Corp., Intel and Sankalp Semiconductor to discuss the need for vendors to adopt new business models and democratize access to semiconductor IP to survive in today's global economy.\r\n\n- **Wednesday, April 10 at the Linley Spring Processor Conference**\r\n - 10:20 a.m. – \"Extending and Optimizing 64-Bit RISC-V Processors\"\r\n - Yunsup Lee will discuss the changing nature of modern compute loads, and the impact of intelligence moving from the enterprise core to the edge. This presentation will highlight recent advancements in extending and optimizing SiFive's 64-bit RISC-V processors to enable heterogeneous compute and efficiency.\r\n\n- **Thursday, April 11 at the Linley Spring Processor Conference**\r\n - 1:15 p.m. – \"Freedom Revolution: Customizable RISC-V AI SoC Platform\"\r\n - Krste Asanovic will outline a new domain-specific architecture approach for AI SoCs, centered on high-performance machine-learning processors based on customizable RISC-V cores with vector extensions, HBM2 high-bandwidth memory interfaces, and Interlaken chip-to-chip interconnects carrying the TileLink coherence protocol.\r\nAdditionally, SiFive will have demos at each event.\r\n\r\n**WHEN:** Tuesday, April 9, 2019 to Thursday, April 11, 2019\r\n\r\n**WHERE:** Hyatt Regency, Santa Clara, Calif.\r\n\r\n## About SiFive\r\n\r\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [www.sifive.com](https://www.sifive.com).\r\n","spans":[]}]}},{"id":"YzJouhIAACMAjy9g","uid":"sifive-and-provenrun-collaborate-to-deliver-best-in-class","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YzJouhIAACMAjy9g%22%29+%5D%5D","tags":[],"first_publication_date":"2022-09-27T07:05:03+0000","last_publication_date":"2022-09-27T07:05:03+0000","slugs":["sifive-and-provenrun-collaborate-to-deliver-best-in-class-security-for-risc-v-microprocessors"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and ProvenRun Collaborate to deliver Best-in-Class Security for RISC-V Microprocessors ","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-09-27","share_image":{"link_type":"Media","kind":"image","id":"YzHMhBIAACMAjHqO","url":"https://images.prismic.io/sifive/51bb4f75-7a08-48ed-bdca-200cff196a53_ProvenRun-Logo-RVB-v1.png?auto=compress,format","name":"ProvenRun-Logo-RVB-v1.png","size":"10263","width":"406","height":"124"},"body":[{"type":"preformatted","text":"Paris, France, September 27, 2022 – ProvenRun, a global leader in embedded security, today announced the availability of its flagship secure OS / TEE product called ProvenCore, integrated with SiFive® WorldGuard technology, providing powerful SoC-level mechanism for software isolation.\r\n\r\nModern microprocessor SoCs are designed to reduce cost by housing all functionality in a single device. This race for more features, which inevitably increases the size of the code and introduces pieces of code from multiple origins, can lead to security risks when one vulnerable piece of code can affect another, intentionally or not. Add to this the significant increase in the device's interactions with the environment, which greatly increases the attack surface, and it makes sense to develop solutions that can guarantee that the failure of one part of the software does not affect the correct and complete functioning of other software running on the same platform.\r\n\r\nSiFive is the leading provider of market-ready processor core IP based on the open RISC-V instruction set architecture. As part of their open platform secure architecture called SiFive Shield, SiFive offers the SiFive WorldGuard solution to enable Trusted Execution Environment on its RISC-V platforms. SiFive WorldGuard is a hardware-enhanced software isolation solution that provides protection against improper access to memory or devices by software applications and other initiators (such as DMAs). WorldGuard enables designers to create domains, also known as “worlds,” for isolated code execution and data protection. The isolation is based on multiple levels of privilege for each world, to offer SoC-level information control.\r\n\r\nThe WorldGuard solution provides a system-level approach to securing access to system resources (memory, peripherals) by software applications. This approach is ideal for creating a trusted environment, enabling a Trusted Computing Base (TCB) where the highest level of trust is limited to the secure ROM boot, the Machine-mode firmware, the secure applications, and the OperatingSystems (OSs) that implement them. This base of trust is also referred to as the “Trusted Agent.”\r\n \r\nProvenCore is a secure OS developed by ProvenRun using deductive formal method, to guarantee security properties such as integrity, confidentiality, correctness, and isolation in order to get as close as possible to zero defect, leaving almost no attack surface for hackers. ProvenCore is resilient against the most sophisticated attacks and has received a Common Criteria EAL7 certification. It is a key component for being able to develop security services with a high security assurance level in a cost-effective way. These security services include key services for establishing a Root of Trust (key management service (secure storage), cryptographic operation services, TRNG) but can also address advanced use cases such as Secure Firmware Update, Runtime Integrity Monitoring, Trusted UI, and more.\r\n\r\nUsing ProvenCore as a “trusted agent” in a WorldGuard configuration achieves best-in-class security for RISC-V architectures, for a scalable and flexible solution with a well-identified and auditable TCB that will meet all security requirements, up to the highest. The implementation of ProvenCore with SiFive WorldGuard can be done by dedicating a core for security, or by isolating two software domains using the same core. The latter is referred to as Trusted Execution Environment, where ProvenCore will coexist with a Rich environment on the same core. A secure monitor will ensure the coordination between the two environments while maintaining the isolation.\r\n\r\n“Combining ProvenRun ProvenCore software and SiFive WorldGuard hardware is the best way to address system-level hardware and software isolation with a certifiable solution,” said Chris Jones, VP Products at SiFive.\r\n\r\nProvenRun also offers a variety of services to help device makers securing products for their entire life cycle:\r\n•\tConsulting services such as risk analysis, security architecture definition, certification support, and secure provisioning\r\n•\tEngineering services such as secure boot implementation and security applications development (cryptographic operation, key management, secure firmware update…) \r\n\r\nABOUT PROVENRUN\r\nProvenRun’s mission is to provide customers with the Trusted Products and Services that will help them Embed Security within their infrastructure of connected devices wherever this is required, at the chip, device, edge or cloud levels. With our security consulting services and secure-by-design off-the-shelf product solutions, we resolve the security challenges arising from the IoT revolution while dramatically improving the protection against remote cyberattacks. For more information, www.provenrun.com\r\n\r\n","spans":[]}]}},{"id":"YFuzyRAAACAAwMn4","uid":"sifive-and-darpa-collaborate-to-bring-the-power-of","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YFuzyRAAACAAwMn4%22%29+%5D%5D","tags":[],"first_publication_date":"2021-03-31T13:00:00+0000","last_publication_date":"2022-08-09T21:50:44+0000","slugs":["sifive-and-darpa-collaborate-to-bring-the-power-of-risc-v-to-technology-innovation"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and DARPA collaborate to bring the power of RISC-V to Technology Innovation","spans":[]}],"publish_to":"Archive","publish_date":"2021-03-31","share_image":{"link_type":"Media","kind":"image","id":"YFu1mhAAACIAwNH6","url":"https://images.prismic.io/sifive/25005290-e982-45a0-8fc0-812e1f8f908b_darpa-toolbox-sifive.png?auto=compress,format","name":"darpa-toolbox-sifive.png","size":"232681","width":"472","height":"314"},"body":[{"type":"preformatted","text":"**Licensing agreement provides access to a broad portfolio of IP from the inventors of RISC-V**\n\n**SAN MATEO, Calif. – March 31, 2021** – [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced an open licensing agreement with the U.S. Defense Advanced Research Projects Agency (DARPA) to accelerate technology innovation as part of the [DARPA Toolbox Initiative](https://www.darpa.mil/work-with-us/darpa-toolbox-initiative). SiFive will provide access to a broad portfolio of IP to create differentiated processor cores, using the free, open RISC-V ISA standard invented by the founders of SiFive. \u003cbr/\u003e\n\n“Extending access to SiFive’s industry-leading portfolio of RISC-V-based processor, security, trace, and debug IP to the DARPA Toolbox program will help participants develop new and innovative solutions to modern computing challenges,” said Chris Jones, VP, Product Marketing, SiFive. “SiFive’s silicon-proven portfolio of RISC-V processor IP includes the tools and support needed to enable next-generation research and development projects.”\u003cbr/\u003e\n\r\nDARPA Toolbox is an agency-wide effort aimed at providing open licensing opportunities with commercial technology vendors to the researchers behind DARPA programs. Through DARPA Toolbox, successful proposers will receive access to commercial vendors' technologies and tools via pre-negotiated, low-cost, non-production access frameworks and simplified legal terms. For commercial vendors, DARPA Toolbox will provide an opportunity to leverage the agency's forward-looking research and a chance to develop new revenue streams based on achievements developed with their technologies.\u003cbr/\u003e\r\n\r\n“DARPA Toolbox participants benefit from simpler and lower-cost access to IP without having to negotiate licensing and access terms, leaving them more time to advance science to benefit the nation,” said Serge Leef, Program Manager, DARPA Microsystems Technology Office. “SiFive’s participation in the program will enable research and development based on their wide range of configurable IP based on the open specification RISC-V ISA.”\u003cbr/\u003e \r\n\r\nSiFive will offer DARPA Toolbox participants access to 64- and 32-bit processor cores for application-capable or embedded use, based on multiple RISC-V ISA microarchitectures aligned to different use cases. The SiFive Core IP portfolio of U, S, and E cores are available in pre-configured standard cores of varying performance levels (known as 2, 3, 5, and 7-series). SiFive Core IP is configurable using the award-winning SiFive Core Designer and can scale from mix+match multi-core cluster capabilities to single-core instances. SiFive also offers SiFive Shield, a pre-integrated SoC security solution, SiFive Insight, a pre-integrated advanced trace and debug solution, and a hardware cryptographic accelerator (HCA).\u003cbr/\u003e\r\n\r\nSiFive Core IP has been adopted worldwide and is available in products by leading technology companies including Architek, BBC Learning, BeagleBoard, Bouffalo Lab, Coherent Logix, eTopus, Innovium, FADU, Huami, MicroChip, Synaptics, Qualcomm, and Samsung.\u003cbr/\u003e\r\n\r\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\n\r\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e\n203.858.7259\u003cbr/\u003e\r\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqm","uid":"sifive-launches-cpu-ip-industry-into-the-cloud-with-new-risc-v-cores-and-an-easy-online-business-model","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqm%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T21:53:13+0000","slugs":["sifive-launches-cpu-ip-industry-into-the-cloud-with-new-risc-v-cores-and-an-easy-online-business-model"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Launches CPU IP Industry into the Cloud with New RISC-V Cores and an Easy Online Business Model","spans":[]}],"publish_to":"Archive","publish_date":"2017-05-04","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN FRANCISCO – May 4, 2017\u003c/span\u003e – [SiFive](https://www.sifive.com/), the company founded by the inventors of the free and open RISC-V instruction set architecture (ISA), today announced the immediate availability of its Coreplex IP, the fastest and easiest way to license RISC-V cores. With the rapid growth in the RISC-V ecosystem, SiFive Coreplex IP designs have become the de facto leader for RISC-V cores, with more public customers, silicon and development boards than any other RISC-V vendor. SiFive’s hassle-free “study-evaluate-buy” purchase process means that designers can get their hands on Coreplex IP RTL in a matter of minutes.\n\n“As an engineer, trying to get information from your average IP vendor is an exercise in futility,” said Yunsup Lee, CTO and co-founder, SiFive. “The countless number of NDAs, partial answers and sales meetings you must agree to just to get basic evaluation material makes it feel like they don’t want your business. It’s unbelievable how far behind the industry is compared to the ease in which SaaS companies provide their products. When we founded SiFive, we wanted to change that. Through our ‘study-evaluate-buy’ model, we’ve made Coreplex IP licensing as easy as buying a subscription to any modern software service.”\n\nSiFive’s website has all the information a designer needs to study the IP, including full datasheets, specifications and app notes, all available without an NDA. With one click, the designer can get instant access to full FPGA bitstream models to test software, SDK and tools. Fully functional, synthesizable evaluation RTL is also available instantly, allowing the designer to synthesize and simulate in their own design environment and process nodes. Finally, a simple seven-page contract with transparent pricing makes it straightforward and easy to license the IP for commercial use.\n\n## RISC-V Ecosystem\n\nRISC-V has developed a strong ecosystem comprising over 60 companies including Google, HPE, Microsoft, IBM, Qualcomm, NVIDIA, Samsung and Microsemi to name a few. Member companies as well as third-party open-source contributors are actively contributing to a maturing stable of software and toolchains, including GCC and binutils, both of which have been upstreamed. SiFive maintains an easy to install toolchain, SDK and BSPs with binaries of the latest open source tools, including OpenOCD, GNU Debugger, Arduino IDE, and the Eclipse integrated development environment. More updates are expected at the [6th RISC-V Workshop](https://riscv.org/2017/03/6th-risc-v-workshop-registration-and-call-for-papers/), May 8-11 in Shanghai.\n\n## SiFive Coreplex IP\n\nSiFive Coreplex IP is silicon proven and developed by the inventors of the RISC-V ISA. Built on years of research and continuous refinement throughout multiple tapeouts, SiFive’s Coreplex IP has demonstrated significantly better power efficiency compared to other, competing ISAs. Two initial Coreplex design configurations are available at launch:\n\n- E31 Coreplex – The most deployed RISC-V core in the world, the E31 Coreplex is designed for low power, high performance, 32-bit embedded applications such as Edge Computing, Smart IoT or Wearables.\n- E51 Coreplex – A 64-bit embedded core, the E51 Coreplex is the ideal solution to act as a system or host control core inside larger 64-bit SoCs, as its small size and performance efficiency set it apart from the typical, bloated and large 64-bit processors while still maintaining full software compatibility with mainstream toolchains.\n\n## Coreplex Ecosystem\n\nSiFive has partnered with multiple companies that are making the Coreplex IP available to their downstream customers. This development of this expanded distribution network has come as a result of the expanding popularity and demand for RISC-V hardware.\n\n“We’ve collaborated with SiFive to bring its Coreplex IP technology to our IGLOO2 and RTG4 FPGA platform,” said Bruce Weyer, vice president and business unit manager for the SoC Products Group at Microsemi. “Led by the inventors of RISC-V, SiFive brings a huge amount of credibility to the quality of their RISC-V cores when we worked with our downstream customers.”\n\n“SiFive has significantly streamlined the licensing process for RISC-V cores,” said Vicson Liu, executive vice president of United Design Service. “Through Coreplex IP, our customers can now easily evaluate and buy 32-bit and 64-bit RISC-V IP to enable their high-performance chip designs.”\n\n“We have been excited by the growth and demand for RISC-V cores from our customers,” said Flash Lin, Chief Operation Officer at Faraday. “By partnering with SiFive to deliver high performance and proven IP, we can quickly service our customer requirements in this rapidly growing ecosystem.”\n\nLearn more about the [Coreplex IP partners](/partners).\n\nFor more information about the “study-evaluate-buy” path to SiFive’s Coreplex IP, please visit the [SiFive Core Designer](/core-designer) page.\n\n## About SiFive\n\nSiFive is the first fabless semiconductor company to build customized silicon based on the open-source RISC-V instruction set architecture. Founded by RISC-V inventors Yunsup Lee, Andrew Waterman and Krste Asanovic, SiFive is democratizing access to custom silicon and drastically reducing the ease at which system designers and makers alike can get access to licensable IP. SiFive is located in San Francisco and has venture backing from Sutter Hill Ventures. For more information visit [www.sifive.com](https://www.sifive.com/).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Alex Trulio\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8452\u003cbr\u003e\n atrulio@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"YeBZARIAACQAfOeg","uid":"deep-vision-adopts-sifive-risc-v-to-add-opencv-enabled","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YeBZARIAACQAfOeg%22%29+%5D%5D","tags":[],"first_publication_date":"2022-01-17T14:00:03+0000","last_publication_date":"2022-08-08T21:53:23+0000","slugs":["deep-vision-adopts-sifive-risc-v-to-add-opencv-enabled-ai-support"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Deep Vision Adopts SiFive RISC-V to Add OpenCV-Enabled AI Support","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-01-17","share_image":{"link_type":"Media","kind":"image","id":"YeBY9xIAACQAfOdw","url":"https://images.prismic.io/sifive/6c6567c0-941a-4ee5-b133-7455dc3b3b33_SiFive_DeepVision_Jan2022.png?auto=compress,format","name":"SiFive_DeepVision_Jan2022.png","size":"1002778","width":"1620","height":"1080"},"body":[{"type":"preformatted","text":"**Deep Vision licenses SiFive Intelligence X280 processor to deliver greater flexibility and AI inference pre-processing for many markets**\n\n**SAN MATEO, Calif., January 17, 2022** – [SiFive, Inc.](https://www.sifive.com), the founder and leader of RISC-V computing, today announced that [Deep Vision](http://www.deepvision.io/) will integrate SiFive RISC-V processor IP into its next-generation inference accelerators to enable more comprehensive computer vision and voice in edge devices. Specifically, Deep Vision will license SiFive Intelligence™ X280 and SiFive Essential™ S7 processor IP to enhance the flexibility and functionality of their products to better support customers building applications for markets like smart city, smart retail, automotive, and industrial.\u003cbr/\u003e\n \r\nSemiCo Research(1) estimates the AI SoC market to reach 25B units by 2027, with revenue reaching $291B, with RISC-V-based AI SoCs unit CAGR of 73.6% by 2027. The SiFive Intelligence X280 processor enables Deep Vision accelerators to offer broader neural network model support and optimizations for floating-point operations. SiFive Intelligence processors feature SiFive Intelligence Extensions to support TensorFlow Lite and a broad range of AI/ML data types, including BFLOAT16. The flexibility and programmability of the SiFive Intelligence X280 processor as an application class AI processor extends the proven capabilities and performance of Deep Vision accelerators to rapidly support new and evolving AI inference models in hardware, as well as AI pre-processing tasks such as image scaling, color conversion, and white noise subtraction.\r\nThe SiFive Essential S7 processor features real-time, deterministic processing capabilities to enable command and control applications within a heterogeneous compute cluster, alongside other SiFive RISC-V processors. Ideally suited to latency-sensitive edge compute applications, the SiFive Essential S7 processor architecture features enhanced security and real-time determinism while offering area-efficient performance-per-watt.\u003cbr/\u003e \n\r\n“We are excited to increase the flexibility and capabilities of our next-generation AI accelerators with the performance and features of SiFive RISC-V processors,” said Ravi Annavajjhala, CEO, Deep Vision. “We can address a broader range of AI use cases and applications, thanks to SiFive Intelligence and SiFive Essential processors, as well as accelerate customer adoption of our solutions. With the AI market evolving rapidly, flexibility and more comprehensive AI support are crucial for success.”\u003cbr/\u003e\n\r\n“Combining the strengths of SiFive Intelligence RISC-V processors with Deep Vision inference accelerators is a natural way to quickly and efficiently build new hardware for the rapidly evolving AI processor market,” said Dr. Yunsup Lee, CTO and co-founder, SiFive. “The requirements for modern AI are well matched to RISC-V, RISC-V Vectors, and SiFive Intelligence Extensions, as implemented in the SiFive Intelligence X280. With our industry-leading RISC-V processor IP portfolio, SiFive is perfectly positioned to enable AI companies who seek to quickly develop market-focused platforms.”\u003cbr/\u003e \n\r\nRecently, SiFive introduced the SiFive 21G3 update with enhancements and performance improvements for a wide range of products, including support for the recently ratified RISC-V Vector and Hypervisor specifications. For more information, please read our blog covering recent announcements, [here](https://www.sifive.com/blog/when-you-reach-the-summit-keep-climbing).\u003cbr/\u003e\n \r\n**About Deep Vision**\u003cbr/\u003e\r\nDeep Vision, an Edge AI processor company, develops specialized deep learning solutions for the edge. Deep Vision silicon and software deliver the power, performance, and ease of use application developers need to enable pervasive edge AI. Deep Vision's products are based on groundbreaking research into the architecture and tools needed to build and offer a leading-edge AI processor for a rapidly growing Edge AI market. Application markets include smart retail, driver-monitoring systems, smart city, drones, factory automation, and more. More information is available at [DeepVision.io](http://www.deepvision.io/).\u003cbr/\u003e\r\n\n**About SiFive**\u003cbr/\u003e\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\n\n1 - Analyzing the RISC-V CPU Market for SIP, SoCs, AI and Design Starts (CC330-21), [SemiCo research](https://semico.com/content/analyzing-risc-v-cpu-market-sip-socs-ai-and-design-starts)","spans":[]}]}},{"id":"YNEkLhUAACgA1qx7","uid":"sifive-performance-p550-core-sets-new-standard-as-highest","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YNEkLhUAACgA1qx7%22%29+%5D%5D","tags":[],"first_publication_date":"2021-06-22T13:00:00+0000","last_publication_date":"2022-08-09T21:48:21+0000","slugs":["sifive-performance-p550-core-sets-new-standard-as-highest-performance-risc-v-processor-ip"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Performance P550 Core Sets New Standard as Highest Performance RISC-V Processor IP","spans":[]}],"publish_to":"Archive","publish_date":"2021-06-22","share_image":{"link_type":"Media","kind":"image","id":"YNEx_xUAACgA1ujC","url":"https://images.prismic.io/sifive/fde93e21-bcd9-4018-8913-fec54a2be23a_SiFivePIE-Quotes.png?auto=compress,format","name":"SiFivePIE-Quotes.png","size":"2070830","width":"1778","height":"1000"},"body":[{"type":"preformatted","text":"**New SiFive Performance Family of application processors offers best in class performance, area, and efficiency for a wide variety of markets**\n\n**SAN MATEO, Calif., June 22, 2021** – [SiFive, Inc.](https://www.sifive.com), the industry leader in RISC-V processors and silicon solutions, today launched the new SiFive Performance family of processors. The SiFive Performance family debuts with two new processor cores, the P270, SiFive’s first Linux capable processor with full support for the RISC-V vector extension v1.0 rc, and the SiFive Performance P550 core, SiFive’s highest performance processor to date. The new SiFive Performance P550 delivers a SPECInt 2006 score of 8.65/GHz, making it the highest performance RISC-V processor available today, and comparable to existing proprietary solutions in the application processor space.\u003cbr/\u003e \r\n\r\n“SiFive Performance is a significant milestone in our commitment to deliver a complete, scalable portfolio of RISC-V cores to customers in all markets who are at the vanguard of SOC design and are dissatisfied with the status quo,” said Dr. Yunsup Lee, Co-Founder and CTO of SiFive. “These two new products cover new performance points and a wide range of application areas, from efficient vector processors that easily displace yesterday’s SIMD architectures, to the bleeding edge that the P550 represents. SiFive is proud to set the standard for RISC-V processing and is ready to deliver these products to customers today.”\u003cbr/\u003e\r\n\r\n“We are pleased to be a lead development partner with SiFive to showcase to mutual customers the impressive performance of their P550 on our 7nm Horse Creek platform,\" said Amber Huffman, Intel Fellow and CTO of IP engineering group at Intel. \"By combining Intel's leading-edge interface IP such as DDR and PCIe with SiFive's highest performance processor, Horse Creek will provide a valuable and expandable development vehicle for cutting-edge RISC-V applications.\"\u003cbr/\u003e \r\n\r\n“Growing from its initial success in embedded processors to tackle the application processor market requires the performance, efficiency, and features demonstrated in the new SiFive Performance P550 core,” said Kevin Krewell, Principal Analyst, TIRIAS Research. “Combined with the maturing and growing open-source software ecosystem for RISC-V developed by leading technology industry companies, chip designers have a real choice for their next SoC application processor core.”\u003cbr/\u003e\r\n\r\nThe SiFive Performance P550 features a thirteen-stage, triple-issue, out-of-order pipeline compatible with the RISC-V RV64GC ISA. Evolved from the previously announced SiFive U84 microarchitecture, Performance P550 scales up to four-core complex configurations that use a similar amount of area as a single Arm Cortex-A75 while delivering a significant performance-per-area advantage.\u003cbr/\u003e\r\n\r\nThe SiFive Performance P270 is an 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA. With full support for the RISC-V Vector Extension v 1.0RC, and combined with SiFive Recode, which translates existing SIMD software from popular legacy architectures to RISC-V Vector assembly code, the SiFive Performance P270 is an ideal replacement for dated SIMD architectures.\u003cbr/\u003e \r\n\r\nThe new SiFive Performance family joins the recently announced SiFive Intelligence family that is focused on AI \u0026 ML applications, and the broadly adopted SiFive Essential family of configurable cores that includes the U/S/E-Series of 64-bit and 32-bit processors.\u003cbr/\u003e\r\n \r\nFor more on the complete SiFive processor portfolio, see CEO Patrick Little’s blog [here](https://www.sifive.com/blog/the-heart-of-sifive-is-performance-intelligence-). Both products in the SiFive Performance family are available [now](https://www.sifive.com/cores/performance). SiFive will conduct a webinar with details about the SiFive Performance, Intelligence, and Essential product families on July 14th with registration available [here](https://www.sifive.com/resources/webinar/introducing-sifive-performance-family).\u003cbr/\u003e\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, AI accelerators, and SoC IP to enable domain-specific designs based on the open RISC-V instruction set architecture specification. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications for SiFive\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e\n\n(Remarks)\u003cbr/\u003e\n1 – Based on SiFive Internal Engineering measurement of SPECInt2k6 performance of SiFive Performance P550\u003cbr/\u003e\r\nArm and Cortex-A75 are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.\u003cbr/\u003e","spans":[]}]}},{"id":"YjFDGRAAACMAs-Kl","uid":"sifive-leadership-in-risc-v-powers-2.5b-company-valuation","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YjFDGRAAACMAs-Kl%22%29+%5D%5D","tags":[],"first_publication_date":"2022-03-16T12:00:00+0000","last_publication_date":"2022-08-08T21:53:41+0000","slugs":["sifive-leadership-in-risc-v-powers-2.5b-company-valuation"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Leadership in RISC-V Powers $2.5B+ Company Valuation","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-03-16","share_image":{"link_type":"Media","kind":"image","id":"YjFCZxAAACAAs9-U","url":"https://images.prismic.io/sifive/9f6615c3-4001-42d5-aac8-1ca32934aa62_SiFiveLeadership2.5B.png?auto=compress,format","name":"SiFiveLeadership2.5B.png","size":"203047","width":"1440","height":"1440"},"body":[{"type":"preformatted","text":"*$175M Series F Investment Led by Coatue Validates Relentless Pursuit of Processor Innovation*\n\n**SAN MATEO, Calif., March 16, 2022** – [SiFive, Inc.](https://www.sifive.com), the founder and leader of RISC-V computing, today announced it has raised $175 million in a Series F financing round, valuing the company at over $2.5 billion. The Series F round was led by Coatue Management, a global technology investment firm that invests in companies at all stages – from venture to growth through public markets. SiFive is substantially accelerating the development of the company’s RISC-V products, future roadmap, and ecosystem to achieve the unlimited potential that RISC-V has for SiFive’s customers and partners.\u003cbr/\u003e \r\n\r\nFounded six years ago by the inventors of RISC-V, SiFive introduced the world to the open standard ISA and transformed the future of compute. Today, RISC-V is firmly established as one of the major global compute platforms, with adoption all around the world, as evidenced by recent industry announcements including the [Intel $1B innovation fund](https://www.intel.com/content/www/us/en/newsroom/news/intel-launches-1-billion-fund-build-foundry-innovation-ecosystem.html), featuring a goal of [catalyzing the RISC-V ecosystem](https://download.intel.com/newsroom/2022/manufacturing/Intel-RISC-V-Fact-Sheet.pdf). SiFive has design wins with more than 100 customers including several of the world’s largest hyperscale companies and 8 of the top 10 semiconductor companies, in applications ranging from automotive, AR/VR, client computing, data center, and intelligent edge.\u003cbr/\u003e\r\n \r\n“The market has spoken and made it abundantly clear that RISC-V computing will be competing for the heart of all future computing platforms. As the founder and market leader of RISC-V computing it’s our role to lead this ecosystem forward and offer customers advanced computing alternative to Arm and others,” said Patrick Little, CEO and Chairman, SiFive. “This valuation is a validation of our strategy, our incredible team, and our singular focus on building the leading portfolio of high-performance RISC-V compute products in the market. Our customers are signaling strong demand for SiFive to deliver the highest level of performance as quickly as possible.”\u003cbr/\u003e \r\n\r\n“We continue to be impressed by SiFive’s growth and challenge to proprietary legacy architecture IP providers,” said Jaimin Rangwalla, Senior Managing Director at Coatue Management. “SiFive’s accomplishments in high-performance RISC-V IP enables future computing platforms to be built on an open, industry-wide base, allowing technology companies to design differentiated products for their target markets. We are proud to partner with and support the team as they create an exciting future for the company.”\u003cbr/\u003e\r\n\r\n“Intel believes in enabling a multi-ISA strategy, including RISC-V as the open compute base for future platforms,” said Bob Brennan, VP \u0026 GM, Customer Solutions Engineering, Intel Foundry Services. “Our IFS investment in RISC-V includes partnering with RISC-V leader SiFive to build the Horse Creek developer platform that will be broadly available in late 2022, based on Intel 4 process technology.”\u003cbr/\u003e\n\r\nTo date, the company has raised over $350 million to fuel its trajectory to the top of the performance processor IP market. SiFive will use the funds to invest in global hiring, the acceleration of new product development, and the software ecosystem. Coatue joins existing investors AMD (through Xilinx Ventures), Ibex Investors, Intel Capital, Osage University Partners, Prosperity7 ventures, Qualcomm Ventures, Samsung Ventures, SK hynix, Spark Capital, Sutter Hill Ventures, and Western Digital Capital.\u003cbr/\u003e\r\n\n**About SiFive**\u003cbr/\u003e\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\r\n\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\n\nSiFive Fact Sheet - [Link](https://prismic-io.s3.amazonaws.com/sifive/d4fe07c1-0242-4bff-a2ec-5e4329904f0e_SiFive+Corporate+Update+Q1+2022+-+Media+%26+Analysts+FINAL.pdf)\n\n![Nasdaq Congratulates SiFive](https://images.prismic.io/sifive/15b2c88c-d9ac-4d1b-b226-0e578f088933_SiFive_031522-2.jpg?auto=compress,format)","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrc","uid":"sifive-unveils-smallest-lowest-power-risc-v-designs","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrc%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T21:50:23+0000","slugs":["sifive-unveils-e2-core-ip-series-for-smallest-lowest-power-risc-v-designs"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Unveils E2 Core IP Series for Smallest, Lowest Power RISC-V Designs","spans":[]}],"publish_to":"Archive","publish_date":"2018-06-25","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSan Mateo, Calif. – June 25, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today announced the availability of its E2 Core IP Series, configurable low-area, low-power microcontroller (MCU) cores designed for use in embedded devices. The E2 Series extends SiFive’s product line with two new standard cores, the E21, which provides mainstream performance for MCUs, sensor fusion, minion cores and smart IoT markets; and the E20, the most power-efficient SiFive standard core designed for microcontrollers, IoT, analog mixed signal and finite state machine applications. Additionally, the company announced enhancements to its existing standard E3 and E5 Core IP Series.\n\nThe SiFive E20 and E21 are designed for markets that require extremely low-cost, low-power computing, but can benefit from being fully integrated within the RISC-V software ecosystem. Fully compatible with the exact same software stack, tools, compilers and ecosystem vendors as other higher performance SiFive cores, the E2 Series enables these new markets to take advantage of the robust software ecosystem that has been exponentially growing since SiFive first introduced commercial RISC-V cores in 2016. Both cores are fully synthesizable and verified soft IP implementations that scale across multiple design nodes. The new product series provides a variety of new features, including a fully configurable memory map, multiple configurable ports, tightly integrated memory (TIM), fast IO access and a new CLIC interrupt controller for extremely fast interrupt response, hardware prioritization and pre-emption.\n\nFurthermore, SiFive gives designers the ability to configure a SiFive RISC-V Core Series to their specific application needs, with the ability to fine-tune performance, microarchitectural features, area density, memory subsystems and more within a given Core Series. Customers can either directly leverage the silicon-proven standard SiFive Core IP like the E21, or use it as a starting point for their own customizations.\n\n“SiFive’s Core IP is the foundation of the most widely deployed RISC-V cores in the world, and represent the lowest risk and fastest path to customized RISC-V based SoCs,” said Yunsup Lee, co-founder and CTO, SiFive. “Our Core IP Series takes advantage of the inherent scalability of RISC-V to provide a full set of customizable cores for any application - from tiny microcontrollers based on our new E2 Core IP Series to our previously announced, Linux-capable, multicore U Core IP Series.”\n\nIn addition to announcing the new E2 Core Series, SiFive also expanded its E3 and E5 Series to support coherent multicore configurations for high-performance embedded applications. In addition to multicore support, the E3 and E5 Series have a new enhanced multiplication unit which allows the E31 and E51 Standard Cores to achieve over 3 CoreMarks/MHz while still using open-source GCC compilers. The E3 and E5 Series are ideal for high-performance, real-time applications such as storage, industrial, modems and networking.\n\nSiFive will demonstrate the E21 at the Design Automation Conference at San Francisco’s Moscone Convention Center through June 27 in the RISC-V Foundation booth, No. 2638. For more information on SiFive’s RISC-V Core IP including full datasheets, specifications and app notes, visit our [Core Designer Page](/core-designer).\n\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom, Western Digital and Intel Capital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"YICe3xMAACIA_XiP","uid":"tenstorrent-selects-sifive-intelligence-x280-for-next-generation1","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YICe3xMAACIA_XiP%22%29+%5D%5D","tags":[],"first_publication_date":"2021-04-22T13:00:00+0000","last_publication_date":"2022-08-09T21:49:16+0000","slugs":["tenstorrent-selects-sifive-intelligence-x280-for-next-generation-ai-processors"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Tenstorrent Selects SiFive Intelligence X280 for Next-Generation AI Processors","spans":[]}],"publish_to":"Archive","publish_date":"2021-04-22","share_image":{"link_type":"Media","kind":"image","id":"YICoAxMAACEA_Z_d","url":"https://images.prismic.io/sifive/6f7ed86f-3881-4bb0-b55b-4c873eda1255_tenstorrentsifiveintelligence04222021.png?auto=compress,format","name":"tenstorrentsifiveintelligence04222021.png","size":"699009","width":"1200","height":"700"},"body":[{"type":"preformatted","text":"**SiFive Intelligence IP integral component of future Tenstorrent AI architectures**\n\n**SAN MATEO, Calif., April 22, 2021** – [SiFive, Inc.](https://www.sifive.com), the industry leader in RISC-V processors and silicon solutions, today announced that Tenstorrent, an AI semiconductor and software start-up developing next-generation computers, will license the new SiFive Intelligence X280 processor in its AI training and inference processor. SiFive will deliver more details of its SiFive Intelligence initiative including the SiFive Intelligence X280 processor at the Linley Spring Processor Conference on April 23rd.\u003cbr/\u003e\r\n\r\nTenstorrent’s novel approach to inference and training effectively and efficiently accommodates the exponential growth in the size of machine learning models while offering best-in-class performance.\u003cbr/\u003e\n\r\n“The Tenstorrent architecture addresses the growing demands that come with data-written code as part of Software 2.0,” said Jim Keller, President and CTO, Tenstorrent. “We’re excited to partner with SiFive because of their ability to deliver CPUs and software for the modern RISC-V ecosystem.”\u003cbr/\u003e\n \r\nThe combination of Tenstorrent’s Tensix processing cores alongside the SiFive Intelligence X280 processor reflects the growing trend of heterogeneous multi-core compute to stay ahead of the requirements of next-generation AI workloads.\u003cbr/\u003e\n\r\n“SiFive Intelligence is a new initiative dedicated to bringing cutting-edge software and hardware technologies to those looking to innovate in the AI market,” said Chris Lattner, President of Engineering and Product at SiFive. “Tenstorrent, with its team of industry leaders and an already impressive track record of silicon success, is an ideal partner for SiFive’s new products targeted at machine learning applications.”\u003cbr/\u003e\r\n\r\nSiFive’s newest processor, the SiFive Intelligence X280, is a 64-bit, multi-core capable RISC-V-based processor with fully integrated RISC-V Vector extension (RVV) support. The SiFive Intelligence X280 processor features SiFive Intelligence Extensions, a comprehensive suite of vector instructions specifically designed to accelerate modern machine learning workloads. SiFive Intelligence is available now, and more information can be found on the [SiFive Intelligence](/cores/intelligence) page.\u003cbr/\u003e\r\n\r\n**About Tenstorrent**\u003cbr/\u003e\r\nTenstorrent is a next-generation computing company with the mission of addressing the rapidly growing compute demands for software 2.0. Headquartered in Toronto, Canada, with U.S. offices in Austin, Texas, and Silicon Valley, Tenstorrent brings together experts in the field of computer architecture, ASIC design, advanced systems, and neural network compilers. Tenstorrent is backed by Eclipse Ventures and Real Ventures, among others.\u003cbr/\u003e\r\n\r\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, AI accelerators, and SoC IP to enable domain-specific designs based on the open RISC-V instruction set architecture specification. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has design centers worldwide and backing from Sutter Hill Ventures, SK hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures. For more information, please visit [www.sifive.com](https://www.sifive.com).\u003cbr/\u003e\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\r\n(Remarks) All names of products or services mentioned in this press release are trademarks or registered trademarks of their respective owners.\u003cbr/\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications for SiFive\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\nsifive@ink-co.com\u003cbr/\u003e","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqw","uid":"lauterbach-and-sifive-bring-trace32-support-for-high-performance-risc-v-cores","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqw%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T21:28:09+0000","slugs":["lauterbach-and-sifive-bring-trace32-support-for-high-performance-risc-v-cores"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Lauterbach and SiFive Bring TRACE32 Support for High-Performance RISC-V Cores","spans":[]}],"publish_to":"Archive","publish_date":"2017-10-24","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eHÖHENKIRCHEN-SIEGERTSBRUNN, Germany, and SAN MATEO, Calif. – Oct. 24, 2017 –\u003c/span\u003e\n[Lauterbach](http://www.lauterbach.com/), the leading manufacturer of microprocessor development tools,\nand [SiFive](https://www.sifive.com/), the first\nfabless provider of customized, open-source-enabled semiconductors, today announced the\navailability of Lauterbach’s TRACE32 toolset to provide debug capabilities for SiFive’s E31 and\nE51 RISC-V Core IP, based on the free and open RISC-V ISA. Lauterbach support for SiFive cores is\nthe latest addition to the growing ecosystem of industry-leading development tools to become\navailable for RISC-V based silicon.\n\nFounded by the inventors of RISC-V, SiFive IP addresses the need to combat the rapidly\nincreasing cost of designing and manufacturing new chip architectures, and fulfills the\ncompany’s mission of democratizing access to custom silicon. Since its launch, SiFive IP has\nbecome the de facto leader for RISC-V cores, with more public customers and working silicon in\nthe market than any other RISC-V vendor.\n\n\"The addition of Lauterbach’s TRACE32 toolset to the SiFive arsenal is a milestone in the\ncontinued development of the RISC-V ecosystem,\" said Yunsup Lee, co-founder and chief\ntechnology officer, SiFive. \"We have worked closely with Lauterbach to ensure that its TRACE32\ntoolset provides the highest level of support for the RISC-V debug specification. We look forward\nto our continued collaboration with Lauterbach to bring additional world-class tools for\ndevelopers working with SiFive IP.\"\n\nLauterbach TRACE32 provides multicore debugging on individual hardware threads of SiFive\ncores, enabling debugging right from the reset vector, which analyzes startup codes and other\nkey functions. Lauterbach also provides high-level and assembler debugging for a variety of\nstandard ISA extensions, such as compressed instructions and floating point. It also fully\nsupports the JTAG Debug Transport Module (DTM) in all SiFive chips, and has planned support\nfor other debug interfaces such as USB.\n\n\"We’ve seen a growing interest in RISC-V across the industry, and we are pleased to extend our\nleading toolset to this segment of the market,\" said Stephan Lauterbach, general manager of\nLauterbach. \"The availability of TRACE32 debugging tools will help build on the initial success of\nRISC-V and continue its adoption in a wide array of deployments.\"\n\nSaid Rick O’Connor, chairman of the RISC-V Foundation: \"The addition of Lauterbach’s world-\nclass solutions to the RISC-V toolset is a testament to the market potential of this new approach\nto silicon design. Continued collaboration between SiFive and Lauterbach will ensure seamless\ninteroperability between RISC-V hardware and TRACE32.\"\n\nLearn more about [Lauterbach’s TRACE32](http://www.lauterbach.com/bdmriscv.html).\n\nLearn more about [SiFive’s Core IP](/risc-v-core-ip).\n\n## About Lauterbach\n\nLauterbach is the leading manufacturer of complete, modular and upgradeable microprocessor\ndevelopment tools worldwide with experience in the field of embedded designs since 1979. It is\nan international, well-established company with blue chip customers in every corner of the\nglobe and has a close working relationship with all semiconductor manufacturers. At the\nheadquarters in Höhenkirchen, near Munich, the engineering team develops and produces\nhighly proficient and specialized Development Tools, which are utilized all over the world under\nthe brand TRACE32®. Our branch offices exist in the United Kingdom, Italy, France, Tunisia, on\nthe east and west coasts of the United States, Japan and China. Highly qualified sales and\nsupport engineers are also available in many other countries. For more information visit\n[www.lauterbach.com](http://www.lauterbach.com).\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the free and open\nRISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee\nand Krste Asanovic, SiFive democratizes access to custom silicon by helping system designers\nreduce time-to-market and realize cost savings with customized RISC-V based semiconductors.\nSiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital\nand Osage University Partners. For more information, visit [www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Norbert Weiss\u003cbr\u003e\n International Sales Manager at Lauterbach\u003cbr\u003e\n +49 (8102) 9876-183\u003cbr\u003e\n norbert.weiss@lauterbach.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n +1 (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n +1 (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"XelAvRIAACIAKwaQ","uid":"another-leading-industry-veteran-joins-sifive-as-svp","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XelAvRIAACIAKwaQ%22%29+%5D%5D","tags":[],"first_publication_date":"2019-12-05T17:58:07+0000","last_publication_date":"2022-08-08T21:02:43+0000","slugs":["another-leading-industry-veteran-joins-sifive-as-svp-of-ex-employee-experience"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Another Leading Industry Veteran Joins SiFive As SVP of EX (Employee eXperience)","spans":[]}],"publish_to":"Archive","publish_date":"2019-12-05","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Mike Schroeder to Lead Talent Acquisition and Employee Engagement to Guide SiFive's Hypergrowth*\n\nSAN MATEO, Calif., Dec. 5, 2019 /PRNewswire/ -- SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Mike Schroeder has joined the company as senior vice president of employee experience (EX). Schroeder will lead SiFive employee experience, culture, talent acquisition and employee engagement to guide SiFive's hypergrowth. SiFive continues to invest in ensuring a highly engaged workforce to bring the power of open source to processor IP and the principles of automation to the next generation of domain-specific SoC design.\r\n\r\n\"SiFive's hypergrowth and future market opportunity mean investing in people is crucial for success,\" said Schroeder. \"I'm excited to lead the ongoing commitment to an inclusive and vibrant culture where people who come to SiFive do the best work of their careers.\"\r\n\r\nSchroeder has a background in human resources and employee development, bringing over 20 years of experience to SiFive. Schroeder worked at Rambus for 12 years as senior vice president of human resources and facilities and was most recently chief people officer (CPO) for Wave Computing. Schroeder's career spans three decades at many leading tech companies, from successful startups to tech leaders such as Apple, Rambus, and Synopsys.\r\n\r\n\"We're pleased to welcome Mike to SiFive to guide our employee engagement as we continue to grow,\" said Naveed Sherwani, president and CEO of SiFive. \"Mike's leadership and experience will be very valuable in ensuring the success of SiFive as we invest in our people to ensure continued business growth.\"\r\n\r\nSchroeder attended the University of Wisconsin at Milwaukee and majored in Russian language. He also completed the Stanford University Graduate School of Business AEA Executive Management Program.\r\n\r\n## About SiFive\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital and Western Digital. For more information, visit [SiFive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), [Facebook](https://www.facebook.com/SiFive/), and [YouTube](https://www.youtube.com/channel/UCqpdhncf4nxTfy0QZh1YWLQ/featured).\r\n\r\nAll brands or product names are the property of their respective holders.\n\n**Media Contact**\u003cbr\u003e\r\nSara Dodrill\u003cbr\u003e \r\nSHIFT Communications for SiFive\u003cbr\u003e\r\n(415) 591-8429\u003cbr\u003e\r\nsifive@shiftcomm.com\u003cbr\u003e\r\n","spans":[]}]}},{"id":"XPVCvxAAACUAPqfW","uid":"avatar-integrated-systems-partnership-strengthens-sifive","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XPVCvxAAACUAPqfW%22%29+%5D%5D","tags":[],"first_publication_date":"2019-06-03T17:02:35+0000","last_publication_date":"2022-08-08T21:08:37+0000","slugs":["avatar-integrated-systems-partnership-strengthens-sifive-cloud-based-design"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Avatar Integrated Systems Partnership Strengthens SiFive Cloud-Based Design","spans":[]}],"publish_to":"Archive","publish_date":"2019-06-03","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*LAS VEGAS, June 3, 2019 -- Design Automation Conference -- SiFive, the leading provider of commercial RISC-V processor IP, design platforms, and custom SoC solutions, announced today a new partnership with Avatar Integrated Systems, a leader in next-generation physical design solutions. The partnership enables SiFive to use Avatar\u0026#39;s physical design implementation tools within the SiFive cloud design environment.*\n\nSiFive is now enabled with Avatar\u0026#39;s industry-leading physical design implementation platform, a complete top-level prototyping, floor-planning, chip assembly, and full function block-level implementation solution. The integration of place and route tools into the SiFive cloud design environment promotes democratized access to custom silicon, accelerating the pace of innovation for businesses large and small that are working with SiFive.\r\n\r\n\u0026quot;We are pleased to partner with Avatar to further enhance the power of our cloud design environment enabling physical design teams to collaborate with teams worldwide,\u0026quot; said Naveed Sherwani, president and CEO of SiFive. \u0026quot;The addition of the Avatar physical design implementation solutions underscores our commitment to offering a fully-integrated cloud environment for SOC design.\u0026quot;\r\n\r\n\u0026quot;Our partnership with SiFive is key to Avatar\u0026#39;s mission to revolutionize the EDA industry,\u0026quot; said Ping-San Tzeng, CTO of Avatar Integrated Systems. \u0026quot;Together we will advance breakthrough automation technologies to democratize custom silicon for design teams. As a next generation EDA player, our goal is to promote silicon innovation at system level by best automation with easy customization.\u0026quot;\r\n\r\nSiFive and Avatar are appearing at the Design Automation Conference (DAC) in Las Vegas, where details of a fully cloud-designed Linux-capable application processor SoC, from concept to boot in six months, will be presented. Visit the SiFive booth, No.1037, and Avatar booth No. 967, to discover how custom silicon can be yours in months, not years.\r\n\r\n**About Avatar Integrated Systems**\r\n\nAvatar Integrated Systems is a leading software company in the Electronic Design Automation (EDA) industry focused on Physical Design Implementation. The company\u0026#39;s products enable integrated circuit (IC) designers to create semiconductor chips, which enable today\u0026#39;s electronic devices, such as smartphones, computers, internet equipment, IoT wearables, etc. Avatar\u0026#39;s products are built on the proven technologies acquired from ATopTech, Inc. Avatar Integrated Systems is headquartered in Santa Clara, California, USA, with subsidiaries and offices in Taiwan, India, Japan, and Korea. The company serves global customers with cutting-edge digital place and route technology and closely partners with customers to reach their design successes. For more information visit: [www.avatar-da.com](https://www.avatar-da.com/).\r\n\r\n**About SiFive**\n\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [www.sifive.com](https://www.sifive.com/).","spans":[]}]}},{"id":"XzHM2xAAACIAuZmW","uid":"sifive-secures-61-million-in-series-e-funding","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XzHM2xAAACIAuZmW%22%29+%5D%5D","tags":[],"first_publication_date":"2020-08-11T13:00:03+0000","last_publication_date":"2022-08-08T21:13:12+0000","slugs":["sifive-secures-61-million-in-series-e-funding"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Secures $61 Million in Series E Funding","spans":[]}],"publish_to":"Archive","publish_date":"2020-08-11","share_image":{"link_type":"Media","kind":"image","id":"XzHMzBAAACEAuZlU","url":"https://images.prismic.io/sifive/2fbdc102-cca4-4a36-b92c-b55a25984add_sifive-seriese-socialimg.png?auto=compress,format","name":"sifive-seriese-socialimg.png","size":"141825","width":"1280","height":"722"},"body":[{"type":"preformatted","text":"*Demand for Domain-Specific Architecture Drives Continued Investment in Processor Innovation*\n\n**SAN MATEO, Calif. Aug 11, 2020** - [SiFive, Inc.](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, today announced it raised $61 million in a Series E round led by SK hynix, joined by new investor Prosperity7 Ventures, with additional funding from existing investors, Sutter Hill Ventures, Western Digital Capital, Qualcomm Ventures, Intel Capital, Osage University Partners, and Spark Capital.\u003cbr/\u003e \r\n\n“Global demand for storage and memory in the data center is increasing as AI-powered business intelligence and data processing growth continues”, said Youjong Kang, VP of Growth Strategy, SK hynix. “SiFive is well-positioned to grow with opportunities created from data center, enterprise, storage and networking requirements for workload-focused processor IP.”\u003cbr/\u003e\n\nSiFive develops a range of processor cores, accelerators, and SoC IP to create domain-specific architecture that will enable efficient, high-performance computing solutions. SiFive innovates by developing processor microarchitecture, SoC IP, and accelerator IP for use in workload-specific silicon. With this new investment, SiFive will help leading semiconductor companies bring to market new products for aerospace, automotive, artificial intelligence, data center, mobile, networking, and storage applications.\u003cbr/\u003e\n\nSiFive’s product portfolio of RISC-V-based microarchitectures are the perfect choice to replace and augment legacy, general-purpose proprietary architectures in workload-focused designs. Recently, SiFive announced the SiFive 20G1 update for SiFive Core IP, enabling significant enhancements for performance, power, area, and features, with pre-integrated SiFive Shield, for whole SoC security, and SiFive Insight advanced trace and debug capabilities.\u003cbr/\u003e\n\n“SiFive is well-positioned to capture the opportunity enabled by workload focused products,”, said Aysar Tayeb, Executive Managing Director at Prosperity7 Ventures. “We’re pleased to be part of the global shift to workload-focused designs, and believe SiFive’s domain-specific architecture IP will fuel innovation and solutions for computing challenges we see today.”\u003cbr/\u003e\n\nDomain-specific architecture designs are further enabled by SiFive Custom Instruction Extensions (SCIE), permitting the inclusion of workload-focused IP through hardware and software optimization. SiFive heterogeneous architecture allows the integration of mixed processor core designs in a coherent cluster for scale-out problems, leveraging SCIE to accelerate workload processing in an efficient manner.\u003cbr/\u003e\n\n“We are very pleased by the new and renewed investment in the SiFive vision and mission,”, said Dr. Naveed Sherwani, Chairman, President, and CEO of SiFive. “SiFive’s winning product portfolio will continue to expand and be adopted for solutions that require domain-specific architectures.”\u003cbr/\u003e\n\nFor more information on SiFive’s market-leading RISC-V IP portfolio, please visit SiFive.com.\u003cbr/\u003e\n\n**About SK hynix**\u003cbr/\u003e\r\nSK hynix Inc., headquartered in Korea, is the world’s top tier semiconductor supplier offering Dynamic Random Access Memory chips (“DRAM”), Flash memory chips (“NAND Flash”) and CMOS Image Sensors (“CIS”) for a wide range of distinguished customers globally. The Company’s shares are traded on the Korea Exchange, and the Global Depository shares are listed on the Luxemburg Stock Exchange. Further information about SK hynix is available at [www.skhynix.com](https://www.skhynix.com), [news.skhynix.com](https://news.skhynix.com).\u003cbr/\u003e\n\n**About Prosperity7 Ventures**\u003cbr/\u003e\r\nProsperity7 Ventures is the diversified growth VC fund of Aramco Ventures, a subsidiary of Aramco. Prosperity7 Ventures invests globally in startups, with a longer-term view to develop next generation technologies and business models that will bring prosperity and a positive impact on a vast scale.\r\n\u003cbr/\u003e\n\n**About SiFive**\u003cbr/\u003e\r\nSiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK hynix, Intel Capital, and Western Digital. For more information, please visit [www.sifive.com](https://www.sifive.com).\r\n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003c/br\u003e\r\n\r\n**Media Contact**\u003cbr/\u003e\n\n**SK hynix**\u003cbr/\u003e\r\nGlobal Public Relations\u003cbr/\u003e\nKorea\u003cbr/\u003e\nE-Mail: global_newsroom@skhynix.com\u003cbr/\u003e\n\n**Prosperity7 Ventures**\u003cbr/\u003e\r\nProsperity7 Ventures Communications\u003cbr/\u003e\r\nAlya Sairafi\u003cbr/\u003e\r\nalya.sairafi@aramco.com\u003cbr/\u003e\r\nDhahran, Saudi Arabia.\u003cbr/\u003e\r\n\r\n**SiFive**\u003cbr/\u003e\r\nHilary Livingston Castle\u003cbr/\u003e\r\nINK Communications\u003cbr/\u003e\r\n203.858.7259\u003cbr/\u003e\r\n","spans":[]}]}},{"id":"YxZxtRIAACMAhtKa","uid":"nasa-selects-sifive-and-makes-risc-v-the-go-to-ecosystem","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22YxZxtRIAACMAhtKa%22%29+%5D%5D","tags":[],"first_publication_date":"2022-09-06T16:00:00+0000","last_publication_date":"2022-09-27T23:47:55+0000","slugs":["nasa-makes-risc-v-the-go-to-ecosystem-for-future-space-missions","nasa-selects-sifive-and-makes-risc-v-the-go-to-ecosystem-for-future-space-missions"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"NASA Makes RISC-V the Go-to Ecosystem for Future Space Missions","spans":[]}],"publish_to":"Current Releases","publish_date":"2022-09-06","share_image":{"link_type":"Media","kind":"image","id":"Yo_bdxAAACAAGbXk","url":"https://images.prismic.io/sifive/0bbdc08b-9aa2-44f3-88ce-f94e7e97bc10_sifive-vectors-card-big-logo.png?auto=compress,format","name":"sifive-vectors-card-big-logo.png","size":"14842","width":"780","height":"440"},"body":[{"type":"preformatted","text":"**SiFive X280 delivers 100x increase in computational capability with leading power efficiency, fault tolerance, and compute flexibility to propel next-generation planetary and surface missions**\n\r\n**San Mateo, Calif., September 6, 2022** - SiFive, Inc., the founder and leader of RISC-V computing, today announced it is providing the core CPU for NASA’s next generation High-Performance Spaceflight Computing (HPSC) processor. HPSC is expected to be used in virtually every future space mission, from planetary exploration to lunar and Mars surface missions. HPSC will utilize a multiple SiFive® Intelligence™ X280 RISC-V vector core, with additional SiFive RISC-V cores, to deliver 100x the computational capability of today’s space computers. This massive increase in computing performance will help usher in new possibilities for a variety of mission elements such as autonomous rovers, vision processing, space flight, guidance systems, communications, and other applications. \r\n\r\n“As the leading RISC-V, U.S. based, semiconductor company we are very proud to be chosen as part of the most mission critical applications for the World's premier world space agency,” said Jack Kang, SVP Business Development, SiFive. “The X280 demonstrates orders of magnitude performance gains over competing processor technology and our SiFive RISC-V IP allows NASA to take advantage of the support, flexibility, and long-term viability of the fast-growing global RISC-V ecosystem. We’ve always said that with SiFive the future has no limits, and we’re excited to see the impact of our innovations extend well beyond our planet.” \r\n\r\nThe SiFive X280 is a multi-core capable RISC-V processor with vector extensions and SiFive Intelligence Extensions and is optimized for AI/ML compute at the edge. The X280 is ideal for applications requiring high-throughput, single-thread performance while under significant power constraints. The X280 has demonstrated a 100x increase in compute capabilities compared to today’s space computers. In scientific and space workloads, the X280 provides several orders of magnitude improvement compared to competitive CPU solutions. \r\n\r\nThe open and collaborative nature of RISC-V will allow the broad academic and scientific software development community to contribute and develop scientific applications and algorithms, as well optimizing the many math functions, filters, transforms, neural net libraries, and other software libraries, as part of a robust and long-term software ecosystem.\r\n\r\nThe HPSC processor and X280 compute subsystem is expected to be useful to other government agencies in a variety of applications including industrial automation, edge computing, ratification intelligence, and aerospace applications. \r\n\r\nFor more information on SiFive’s market-leading RISC-V IP portfolio and how it is well-suited for Aerospace and Defense applications, please visit SiFive.com.\r\n\n**About SiFive**\r\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit SiFive.com. \n\r\nStay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).\u003cbr/\u003e\r\n\n**Media Contacts** \nRacepoint Global for SiFive,\nSiFive@racepointglobal.com, \r\nTel.: +1(415)694-6711 \r\n\r\nDavid Miller,\r\nCorporate Communications,\r\nSiFive,\r\nDavid.Miller@sifive.com\r\n\r\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vri","uid":"sifive-challenge-calls-for-risc-v-hardware-innovations","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vri%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:41:15+0000","slugs":["sifive-challenge-calls-for-risc-v-hardware-innovations"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Challenge Calls for RISC-V Hardware Innovations","spans":[]}],"publish_to":"Archive","publish_date":"2018-05-08","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – May 8, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today opened the call for partnership applications for the Democratizing Ideas partnership initiative, which aims to support new, innovative ideas from academia, research institutions, students and the open source community based on the company’s Freedom Unleashed or Freedom Everywhere platforms. Announced at the RISC-V Workshop in Barcelona, the initiative is designed to further the company’s mission to democratize access to custom silicon to anyone who wants it.\n\n“We believe that some of the best, yet most underutilized, ideas come from academia, students, research institutions and the open source community,” said Yunsup Lee, co-founder and CTO of SiFive. “By leveraging the Freedom Platform, today anyone can get access to the custom silicon needed to bring their idea to life. We are excited to see what customizations the community dreams up, and look forward to reviewing a wide range of new, innovative concepts.”\n\n\nThe opportunity to partner is open to both individuals and teams. Proposals are welcome from any non-commercial entity, including universities, students, research groups, non-profits or individuals. Submissions will be reviewed for creativity, innovation and technical feasibility, and selected partners are eligible to receive SiFive’s support in the form of access to custom CPU IP, design support and help delivering working chip samples. Entries are currently being accepted via the [SiFive Democratizing Ideas website](https://info.sifive.com/democratizing-ideas) through Oct. 31, 2018. All approved partnerships will be announced at the RISC-V Summit at the Santa Clara Convention Center, planned for Dec. 3-5, 2018.\n\nThe SiFive Freedom platforms comprise a complete software specification, board OS support packages (BSPs), development boards and base silicon. Freedom HiFive Unleashed is the first RISC-V development board with full support for Linux-capable applications including networking, storage and machine learning, while Freedom Everywhere is suited for embedded microcontroller use cases such as wearables and other Internet of Things enabled devices. For more information on the Democratizing Ideas challenge visit, [https://info.sifive.com/democratizing-ideas](https://info.sifive.com/democratizing-ideas).\n\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrA","uid":"dover-microsystems-brings-secure-silicon-ip-to-designshare","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrA%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:46:10+0000","slugs":["dover-microsystems-brings-secure-silicon-ip-to-designshare"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Dover Microsystems Brings Secure Silicon IP to DesignShare","spans":[]}],"publish_to":"Archive","publish_date":"2018-04-12","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – April 12, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today announced that Dover Microsystems, a cybersecurity solutions provider, is the latest vendor to join the DesignShare ecosystem.\n\nDover Microsystems will make available its CoreGuard Silicon IP, which comprises hardware technology that enables processors to defend themselves in real-time from all network-based attacks. With CoreGuard, system designers have assurance that their SiFive-based host processor is protected at the instruction level. CoreGuard prevents illegal instructions from executing before any damage can be done. Its security rules define the difference between legal and illegal instructions, and can be customized to meet the needs of a wide variety of systems.\n\n“As the inventors of RISC-V and the industry’s first RISC-V based chip platform, SiFive is leading the way in the transformation of the semiconductor market,” said Jothy Rosenberg, CEO and co-founder of Dover Microsystems. “We are excited to partner with SiFive to bring secure computing to the RISC-V community. Our revolutionary CoreGuard technology goes far beyond traditional solutions by hardwiring cybersecurity directly into the silicon of the host processor to guarantee security, safety, and privacy.”\n\nAny company, inventor or maker can harness the power of custom silicon with little to no upfront risk through the SiFive DesignShare program. To lower the costs of bringing a chip from design to realization, DesignShare partners like Dover Microsystems offer pre-integrated solutions that enable users to develop their prototypes without the investment in upfront engineering costs typically required.\n\n“Dover Microsystems provides a new and unique security solution previously unavailable to the RISC-V community,” said Shafy Eltoukhy, vice president of operations and head of DesignShare at SiFive. “With CoreGuard as part of the DesignShare catalog, RISC-V users now have a secure computing solution available.”\n\nSince DesignShare launched last year, the ecosystem has grown to include a wide range of IP solutions, from debug and trace technology to reconfigurable FPGA.\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n\n## About Dover Microsystems\n\nDover’s lineage began in 2010 as the largest performer on the DARPA CRASH program. In 2015, Dover began incubation inside Draper before spinning out in 2017.\n\nBased in Boston, Dover is the first company to bring real security, safety, and privacy enforcement to silicon. Dover’s patented CoreGuard solution integrates with RISC processors to protect against cyberattacks, flawed software, and safety violations. For more information about the company, please visit [www.dovermicrosystems.com](https://www.dovermicrosystems.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (646) 756-3713\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Mara Stefan\u003cbr\u003e\n Emerge Public Relations for Dover Microsystems\u003cbr\u003e\n (781) 771-6911\u003cbr\u003e\n mstefan@emergepr.com \n\u003c/address\u003e\n","spans":[]}]}},{"id":"XHc81hEAACEAeCdv","uid":"sifive-welcomes-former-intel-capital-vp-to-executive","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XHc81hEAACEAeCdv%22%29+%5D%5D","tags":[],"first_publication_date":"2019-02-28T13:30:10+0000","last_publication_date":"2022-08-08T20:57:17+0000","slugs":["sifive-welcomes-former-intel-capital-vp-to-executive-team"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Welcomes Former Intel Capital VP to Executive Team","spans":[]}],"publish_to":"Archive","publish_date":"2019-02-28","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Hiren Majmudar joins RISC-V leader to head business development efforts*\n\n**SAN MATEO, Calif. – Feb 28, 2019 –**\n\nSiFive, the leading provider of commercial RISC-V processor IP and silicon solutions, today named Hiren Majmudar vice president of business development. The rapidly growing company released the industry’s first Linux-capable RISC-V SoC and has been releasing new classes of Core IP in quick succession. Most recently, SiFive released the Core IP 7 Series in 32- and 64-bit variants across the E7, S7, and U7 product families with coherent heterogenous support to enable high performance embedded intelligence.\n\n\"SiFive is leading the disruption of the semiconductor industry with effective implementation of the Open Source RISC-V instruction set architecture, and it is well on its way to democratizing access to silicon for the masses,\" said Majmudar. \"I'm thrilled to be a part of this revolution, contributing to corporate development and sales strategy for customer expansion.\"\r\n\nMajmudar recently led Intel Capital’s corporate development practice for silicon and IP and brings more than 25 years of business and technology leadership experience to SiFive. During his time at Intel Capital, the world’s largest corporate venture capital group, Majmudar spearheaded a renewed focus on equity investments, and mergers and acquisitions for silicon design and intellectual property (IP). He also led Intel Capital’s investment in SiFive and served as a board observer for the company. Prior to this role, Majmudar built Intel’s third-party IP ecosystem and enabled Intel’s corporate transition to the world of SoCs. Majmudar also has 15 years of engineering leadership in chip design, EDA development, and software tools sales and marketing. \n\n\"We're excited to bring in Hiren to help propel SiFive’s growth,\" said Naveed Sherwani, SiFive president and CEO. \"Hiren has been a champion of SiFive and a valuable member of our board. His experience in engineering-driven corporate development activities, especially for CPU and other emerging compute engines, will enable us to refine and execute our corporate development strategy, raise capital and significantly expand our strategic customer base”. \r\n\nMajmudar has a master's degree in electrical engineering from State University of New York, Stony Brook.\r\n\n**About SiFive**\n\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [www.sifive.com](https://www.sifive.com)\n\n**MEDIA CONTACT**\r\n\nLeslie Clavin\u003cbr/\u003e\r\nSHIFT Communications for SiFive\u003cbr/\u003e\r\n(415) 591-8440\u003cbr/\u003e\r\nsifive@shiftcomm.com\u003cbr/\u003e\r\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqU","uid":"sifive-and-ememory-bring-embedded-memory-to-designshare-economy-to-accelerate-development-of-risc-v-silicon","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqU%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:25:27+0000","slugs":["sifive-and-ememory-bring-embedded-memory-to-the-designshare-economy-to-accelerate-development-of-risc-v-silicon"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and eMemory Bring Embedded Memory to the DesignShare Economy to Accelerate Development of RISC-V Silicon","spans":[]}],"publish_to":"Archive","publish_date":"2017-11-07","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Nov. 7, 2017 – \u003c/span\u003e\n[SiFive](https://www.sifive.com/), the first fabless provider of customized, open-source-enabled semiconductors, today announced the addition of eMemory, the IP provider of\nlogic-based, non-volatile memory (Logic NVM), to the DesignShare economy. eMemory will\nmake its embedded NVM silicon IP technology available for the SiFive RISC-V based Freedom\nplatform as part of the DesignShare initiative.\n\nThe DesignShare concept opens a new range of applications and gives any company, inventor\nor maker the ability to harness the power of custom silicon. Companies like SiFive, eMemory\nand other DesignShare partners have developed efficient, pre-integrated solutions to enable\nusers to develop their prototypes without the significant investment in upfront engineering\ncosts typically required to bring a custom chip design to realization. The partnership between\nSiFive, founded by the inventors of RISC-V, and eMemory, the world’s largest pure-play\ndeveloper and provider of Logic NVM technology, strengthens the ecosystem surrounding the\nopen source RISC-V instruction set architecture.\n\n\"We view DesignShare as a key platform to enable the democratization of custom silicon and to\ncontinue SiFive’s mission to encourage more innovation in the semiconductor industry,\" said\nNaveed Sherwani, CEO of SiFive. \"The addition of eMemory to the DesignShare ecosystem\nmeans that designers at all levels have access to the industry’s leading embedded memory\nsolutions. We are excited at the potential innovations eMemory will help bring to market as\npart of the DesignShare ecosystem.\"\n\neMemory Technology Inc. is the world’s largest pure-play developer and provider of logic-based\nnon-volatile memory (Logic NVM) technology. The company licenses its silicon intellectual\nproperty (Silicon IP) to semiconductor foundries, integrated devices manufacturers (IDMs), and\nfabless design houses around the world. eMemory’s proprietary silicon IP technologies include\nNeoBit, NeoFuse, NeoMTP, NeoFlash, and NeoEE. Products developed from these core\ntechnologies have already been embedded in more than 27 billion integrated circuits used in\nvarious applications, such as consumer, industrial, and automotive, etc..\n\n\"Initiatives like DesignShare will help eMemory expand its innovative memory technologies into\nthe next 20 billion devices, and provide system developers with superior flexibility and process\nportability,\" said Michael Ho, Vice President of Business Development, eMemory. \"We are\nexcited to partner with SiFive and other DesignShare participants in helping to provide a full-service solution that encourages customer success in bringing new innovations to life.\"\n\n## About Sifive\n\nSiFive is the first fabless provider of customized semiconductors based on the free and open\nRISC-V instruction set architecture. Founded by RISC-V inventors Yunsup Lee, Andrew\nWaterman and Krste Asanovic, SiFive democratizes access to custom silicon by helping system\ndesigners reduce time-to-market and realize cost savings with customized RISC-V based\nsemiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill\nVentures, Spark Capital and Osage University Partners. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqc","uid":"sifive-to-hold-inaugural-technical-symposium-in-shanghai","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqc%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:12:38+0000","slugs":["sifive-to-hold-inaugural-technical-symposium-in-shanghai"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive to Hold Inaugural Technical Symposium in Shanghai","spans":[]}],"publish_to":"Archive","publish_date":"2018-05-15","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – May 15, 2018\u003c/span\u003e\n\n**WHO:** SiFive, the leading provider of commercial RISC-V processor IP.\n\n**WHAT:** SiFive will hold its 2018 Technical Symposium in Shanghai. As the first company to bring commercial RISC-V IP to market, SiFive will provide an overview of the RISC-V instruction set architecture, its history and future trends; an introduction to the RISC-V ecosystem; a summary of the latest RISC-V cores and platforms; and demonstrations from SiFive and its partners.\n\nSpeakers at the event include:\n\n* Thomas Xu, CEO of Brite Semi\n* Dr. Naveed Sherwani, CEO of SiFive\n* Martin Fink, CTO of Western Digital\n* Dr. Yunsup Lee, CTO of SiFive\n* Venkatesh Narayanan, Senior Director at MicroSemi\n* Dr. Shafy Eltoukhy, VP of Operations at SiFive\n* Dr. Krste Asanovic, Chief Architect at SiFive\n* Dr. John Zhuang, CTO of Brite Semi\n* Dr. Yungang Bao, Director of Research at the Center for Advanced Computer Systems\n\n**WHEN:** 8:30 a.m. to 4:45 p.m., Thursday, May 17, 2018\n\n**WHERE:** Shanghai Evergreen Laurel Hotel, 1136 Zuchongzhi Rd, Pudong Xinqu, Shanghai Shi, China, 201203\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom, Western Digital and Intel Capital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n 646-756-3713\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrS","uid":"sifive-announces-first-open-source-risc-v-based-soc-platform-with-nvidia-deep-learning-accelerator-technology","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrS%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:12:48+0000","slugs":["sifive-announces-first-open-source-risc-v-based-soc-platform-with-nvidia-deep-learning-accelerator-technology"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Announces First Open-Source RISC-V-Based SoC Platform with Nvidia Deep Learning Accelerator Technology","spans":[]}],"publish_to":"Archive","publish_date":"2018-08-20","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eCupertino, Calif. – August 20, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today announced the first open-source RISC-V-based SoC platform for edge inference applications based on NVIDIA's Deep Learning Accelerator (NVDLA) technology.\n\nThe demo will be shown this week at the Hot Chips conference and consists of NVDLA running on an FPGA connected via ChipLink to SiFive’s HiFive Unleashed board powered by the Freedom U540, the world’s first Linux-capable RISC-V processor. The complete SiFive implementation is well suited for intelligence at the edge, where high-performance with improved power and area profiles are crucial. SiFive’s silicon design capabilities and innovative business model enables a simplified path to building custom silicon on the RISC-V architecture with NVDLA. \n\nNVIDIA open-sourced its leading deep learning accelerator over a year ago to spark the creation of more AI silicon solutions. Open-source architectures such as NVDLA and RISC-V are essential building blocks of innovation for Big Data and AI solutions.\n\n“It is great to see open-source collaborations, where leading technologies such as NVDLA can make the way for more custom silicon to enhance the applications that require inference engines and accelerators,” said Yunsup Lee, co-founder and CTO, SiFive. “This is exactly how companies can extend the reach of their platforms.”\n\n\"NVIDIA open sourced its NVDLA architecture to drive the adoption of AI,” said Deepu Talla, vice president and general manager of Autonomous Machines at NVIDIA. \"Our collaboration with SiFive enables customized AI silicon solutions for emerging applications and markets where the combination of RISC-V and NVDLA will be very attractive.”\n\nSiFive will be demonstrating its platform at Hot Chips at the Flint Center for the Performing Arts in Cupertino, on Aug. 20-21, 2018. For more information, visit [www.sifive.com](https://www.sifive.com).\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Intel Capital and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vry","uid":"sifive-and-rambus-to-provide-ip-to-the-designshare-economy","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vry%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:17:14+0000","slugs":["sifive-and-rambus-to-provide-ip-to-the-designshare-economy"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and Rambus to Provide IP to the 'DesignShare' Economy","spans":[]}],"publish_to":"Archive","publish_date":"2017-08-21","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – August 21, 2017\u003c/span\u003e – [SiFive](https://www.sifive.com/), the first fabless provider of customized, open-source-enabled semiconductors, today announced it will partner with [Rambus](https://www.rambus.com), (NASDAQ: RMBS), a leader in digital security, semiconductor and IP products and services, to make Rambus cryptography technology available for the SiFive Freedom platforms. To speed time to market and remove the barriers that traditionally have blocked smaller players from developing custom silicon, leading companies in the semiconductor ecosystem have developed a new DesignShare concept, which offers IP at a reduced cost.\n\nThe DesignShare model gives any company, inventor or maker the ability to harness the power of custom silicon, enabling an entirely new range of applications. Companies like SiFive, Rambus and other ecosystem partners provide low- or no-cost IP to emerging companies, lowering the upfront engineering costs required to bring a custom chip design based on the SiFive Freedom platform to realization.\n\n“To fulfill our mission to democratize access to custom silicon and upend the stagnant semiconductor industry, SiFive is committed to recruiting leading-edge companies like Rambus to help us revolutionize SoC design,” said Naveed Sherwani, CEO of SiFive. “The growing ecosystem of DesignShare IP providers ensures that aspiring system designers have a catalog of IP from which to choose when designing their SoC. We’re thrilled that Rambus has joined us in enabling innovation through DesignShare, and we look forward to future success together.”\n\n\nRambus will collaborate with SiFive to provide critical security components such as cryptographic cores, hardware root-of- trust, key provisioning and high-value services that are enabled by design.\n\n“Rambus and SiFive share a similar philosophy of easing the path to designing innovative and cost-effective SoCs,” said Martin Scott, senior vice president and general manager of Rambus Security Division. “SiFive and Rambus have agreed to partner with an intent of providing chip- to-cloud- to-crowd security solutions that easily integrate with the SiFive Freedom platform and support the open and growing RISC-V hardware ecosystem. Our security cores embedded in Freedom Platform SOCs will enable secure in-field device connection and attestation for updates and diagnostics.”\n\nSiFive was founded by the inventors of RISC-V – Yunsup Lee, Andrew Waterman and Krste Asanovic – with a mission to democratize access to custom silicon. In its first six months of availability, more than 1,000 HiFive1 software development boards have been purchased and delivered to developers in over 40 countries. Additionally, the company has engaged with multiple customers across its IP and SoC products, started shipping the industry’s first RISC-V SoC in November 2016 and announced the availability of its Coreplex RISC-V based IP earlier this month. SiFive’s innovative “study, evaluate, buy” licensing model dramatically simplifies the IP licensing process, and removes traditional road blocks that have limited access to customized, leading edge silicon.\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive democratizes access to custom silicon by helping system designers reduce time-to- market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit [www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Alex Trulio\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8452\u003cbr\u003e\n atrulio@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrY","uid":"sifive-to-discuss-latest-technology-developments-at-risc-v-workshop","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrY%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:16:48+0000","slugs":["sifive-to-discuss-latest-technology-developments-at-risc-v-workshop"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive To Discuss Latest Technology Developments at RISC-V Workshop","spans":[]}],"publish_to":"Archive","publish_date":"2018-05-02","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – May 2, 2018 – \u003c/span\u003e\n\n**WHO:** SiFive, the leading provider of commercial RISC-V processor IP, and the following executives: \n\n* Krste Asanovic, co-founder and chief architect \n* Yunsup Lee, co-founder and chief technology officer \n* Andrew Waterman, co-founder and chief engineer \n* Palmer Dabbelt, lead engineer \n\n**WHAT:** SiFive, the leading provider of commercial RISC-V processor IP, will present five key sessions and tutorials at this year’s RISC-V Workshop in Barcelona. As SiFive continues its mission to democratize access to custom silicon, the company will present the following Workshop sessions: \n\n* **Monday, May 7: Workshop Tutorial Day**\n * 1:15 p.m. – “Base ISA” with Andrew Waterman\n* **Tuesday, May 8: Workshop Day 1**\n * 9 a.m. – “State of the Union: RISC-V” with Krste Asanovic\n * 9:30 a.m. – “The State of RISC-V Software” with Palmer Dabbelt, SiFive; and Arun Thomas, Draper Labs\n * 2:45 p.m. – “HiFive Unleashed: World’s First Multi-Core RISC-V Linux Dev Board” with Yunsup Lee\n* **Wednesday, May 9: Workshop Day 2**\n * 9 a.m. – “Fast Interrupts for RISC-V” with Krste Asanovic\n\nSiFive also will demo the industry’s first RISC-V development board with Linux support, HiFive Unleashed. For more information, visit: [https://tmt.knect365.com/risc-v-workshop-barcelona/](https://tmt.knect365.com/risc-v-workshop-barcelona/)\n\n**WHEN:** Monday, May 7, to Thursday, May 10, 2018\n\n**WHERE:** Universitat Politècnica de Catalunya, Campus Nord, Calle Jordi Girona, 1-3, 08034 Barcelona, Spain\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n 646-756-3713\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vq-","uid":"flex-logix-to-provide-embedded-fpga-ip-to-designshare-for-sifive-freedom-platform","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vq-%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:17:21+0000","slugs":["flex-logix-to-provide-embedded-fpga-ip-to-designshare-for-sifive-freedom-platform"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Flex Logix to Provide Embedded FPGA IP to 'DesignShare' for SiFive Freedom Platform","spans":[]}],"publish_to":"Archive","publish_date":"2017-10-31","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO AND MOUNTAIN VIEW, Calif. – Oct. 31, 2017 – \u003c/span\u003e\n[SiFive](https://www.sifive.com/), the first fabless provider of\ncustomized, open-source-enabled semiconductors, and Flex Logix™, a leader in embedded\nFPGA IP and software, today announced they will partner to make Flex Logix EFLX\u003csup\u003e®\u003c/sup\u003e embedded\nFPGA available for the SiFive Freedom Platform as part of the DesignShare program. The\navailability of Flex Logix IP through DesignShare eases time to market and removes traditional\nbarriers to entry that have blocked smaller companies from developing custom silicon.\n\n\"The addition of Flex Logix’s best-in-class embedded FPGA platform to the DesignShare\necosystem provides engineers with a new and better way to bring SoCs to market,\" said Naveed\nSherwani, CEO of SiFive. \"The adoption of the RISC-V architecture continues to experience\nsignificant growth, and the addition of embedded FPGA technologies through DesignShare will\nmake it easier and more flexible for designers to employ RISC-V in their future designs across a\nwide range of implementations, from embedded devices to the data center.\"\n\nThe Freedom Platform gives any company, inventor or maker the ability to harness the power\nof custom silicon and incorporate world-class IP into their products. Unlike the traditional ASIC\nmodel, which greatly restricts the number of viable designs by requiring a significant upfront\ninvestment for IP and development, the SiFive Freedom Platform and its DesignShare partners\nreduce and defer this investment by providing low- or no-cost IP during the prototyping phase.\nBy reducing the investment cost and streamlining the IP acquisition process, the DesignShare\nprogram aims to significantly increase the number of new silicon designs starts.\n\nSiFive will collaborate with Flex Logix to make its EFLX\u003csup\u003e®\u003c/sup\u003e embedded FPGA available for the SiFive\nFreedom Platform of SoCs at 28nm and 180 nm, with several embedded FPGA array size\noptions available for each node. The EFLX embedded FPGA also will be integrated into a future\ntape-out of the SiFive U500 base platform for customer evaluation using SiFive evaluation\nboards and software. Flex Logix embedded FPGA for the SiFive Freedom Platform can directly\nconnect up to 64 GPIO while acting as a reconfigurable accelerator for specific tasks, increasing\nbattery life, improving programmable serial I/O functions and offloading low-level, repetitive\nprocessing from the CPU.\n\n\"There is a critical need in the chip industry to provide a faster, cheaper way for innovative\ncompanies to rapidly prototype new, advanced chip architectures,\" said Geoff Tate, CEO of Flex\nLogix. \"Through DesignShare, SiFive and Flex Logix can give customers a highly programmable,\nflexible chip design for both microcontroller SoCs and multicore process SoCs. The RISC-V\narchitecture provides excellent performance, and – when combined with embedded FPGA\nfunctionality, can provide higher performance in a reconfigurable way.\"\n\n\nSiFive was founded by the inventors of RISC-V – Andrew Waterman, Yunsup Lee and Krste\nAsanovic – with a mission to democratize access to custom silicon. In its first six months of\navailability, more than 1,000 HiFive1 software development boards have been purchased and\ndelivered to developers in over 40 countries. Additionally, the company has engaged with\nmultiple customers across its IP and SoC products, started shipping the industry’s first RISC-V\nSoC in November 2016 and announced the availability of its RISC-V Core IP in September.\nSiFive’s innovative \"study, evaluate, buy\" licensing model dramatically simplifies the IP licensing\nprocess, and removes traditional road blocks that have limited access to customized, leading\nedge silicon.\n\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the free and open\nRISC-V instruction set architecture. Founded by RISC-V inventors Yunsup Lee, Andrew\nWaterman and Krste Asanovic, SiFive democratizes access to custom silicon by helping system\ndesigners reduce time-to-market and realize cost savings with customized RISC-V based\nsemiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill\nVentures, Spark Capital and Osage University Partners. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## About Flex Logix\n\nFlex Logix, founded in March 2014, provides solutions for reconfigurable RTL in chip and system\ndesigns using embedded FPGA IP cores and software. The company's technology platform\ndelivers significant customer benefits by dramatically reducing design and manufacturing risks,\naccelerating technology roadmaps, and bringing greater flexibility to customers’ hardware. Flex\nLogix has secured approximately $13 million of venture backed capital, is headquartered in\nMountain View, California and has sales rep offices in China, Europe, Israel, Japan, Taiwan and\nTexas. More information can be obtained at [http://www.flex-logix.com](http://www.flex-logix.com)\nor follow on Twitter at @efpga.\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Kelly Karr\u003cbr\u003e\n Tanis Communications for Flex Logix\u003cbr\u003e\n kelly.karr@taniscomm.com\u003cbr\u003e\n +408-718-9350\u003cbr\u003e\n\u003c/address\u003e\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqS","uid":"fadu-launches-industry-leading-ssd-solutions-powered-by-sifive-risc-v-core-ip","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqS%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:24:51+0000","slugs":["fadu-launches-industry-leading-ssd-solutions-powered-by-sifive-risc-v-core-ip"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"FADU Launches Industry Leading SSD Solutions Powered by SiFive RISC-V Core IP","spans":[]}],"publish_to":"Archive","publish_date":"2018-08-07","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. and SANTA CLARA, Calif. – August 7, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, and FADU, a fabless company developing solutions and systems for the memory and storage market, today announced the availability of FADU’s Annapurna SSD Controller and FADU Bravo Series Enterprise SSD, powered by SiFive’s industry leading 64-bit, E51 multicore RISC-V Core IP.\n\nThe FADU Annapurna SSD controller is the world’s first RISC-V based SSD Controller and provides the highest throughput (3.5GB) and IOPS (800K) among its peers, while consuming less than 1.8W active power. Powered by FADU Annapurna, the FADU Bravo SSD is the first 7mm low-power U.2 supporting dual port and offers 3-4X IOPS / watt greater efficiency, 30% lower power, and the most consistent latency QoS in its class. Despite consuming only 6-8W of active power, FADU Bravo easily outperforms competing solutions at 25W, due to its innovative design, advanced flash memory controller, and use of SiFive’s high-performance 64-bit embedded RISC-V Core IP.\n\n“FADU is focused on building the most advanced memory and storage devices for our customers and addressing their ongoing needs,” said Jihyo Lee, CEO, FADU. “SiFive’s RISC-V Core IP was 1/3 the power and 1/3 the area of competing solutions, and gave FADU the flexibility we needed in optimizing our architecture to achieve these groundbreaking products.”\n\nFADU expects to become a leader in the enterprise SSD market, particularly in the hyperscale datacenter. FADU is currently demoing its Annapurna controller and Bravo SSD at the Flash Memory Summit in booth 715, at the Santa Clara Convention Center.\n\n“The flexibility, 64-bit, embedded and multicore features of the E51 RISC-V Core IP is ideal for the storage market and we’re excited to be closely partnered with FADU, who was able to quickly take advantage of RISC-V and deliver a true world-leading product,” said Jack Kang, Vice President of Product, SiFive. “SiFive looks forward to working with FADU as they continue to build next-generation products for the SSD industry.”\n\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom, Western Digital and Intel Capital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## About FADU\n\nFADU is a fabless company focusing on memory and storage solutions and systems. Explosively increasing data requires next generation storage and advanced solutions. FADU believes that new and innovative ideas are required in this fast-changing environment. Built based on 3 groups of talented people--brilliant architects including Ph.Ds, high caliber ASIC experts, and seasoned SSD engineers from leading memory and storage companies, the FADU team has comprehensive capabilities to take innovation to the next level in this industry. FADU introduces true next generation products and seeks to raise the bar for the entire industry. For more information, visit [www.fadu.io](http://www.fadu.io).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vq6","uid":"sifive-appoints-naveed-sherwani-as-ceo","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vq6%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:25:05+0000","slugs":["sifive-appoints-naveed-sherwani-as-ceo"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Appoints Naveed Sherwani as CEO","spans":[]}],"publish_to":"Archive","publish_date":"2017-08-15","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN FRANCISCO – August 15, 2017\u003c/span\u003e – \n[SiFive](https://www.sifive.com/), the first fabless provider of customized, open-source-enabled semiconductors, today announced that industry veteran Naveed Sherwani has joined the company as CEO to lead it through its next phase of growth. Stefan Dyckerhoff, who had held the top spot at the company since its inception, will remain a member of the SiFive board of directors.\n\n“Naveed brings a lifetime of experience not only in the semiconductor and open source sectors, but also in growing successful startups into industry leaders,” Dyckerhoff said. “SiFive has achieved significant industry milestones since its founding, and we continue to drive innovations that are leveling the playing field for those priced out of the traditional silicon market. We are excited to have Naveed join the team, and look forward to further growth under his leadership.”\n\nSherwani joins SiFive with more than 25 years of experience in the industry at companies including Intel, Brite Semiconductor and Open Silicon. Over the course of his career, Sherwani has been involved in the development of more than 300 chips, and, through his work as founder and CEO of Open Silicon, was instrumental in leading the development of ASIC technologies, which offered lower cost alternatives to traditional, less reliable legacy offerings. \n\nSherwani’s appointment is the latest in a string of key additions to the SiFive team, which continues to grow, attracting top talent from companies including Altera, ARM, Atmel, Cadence Design Systems, Cisco, Intel, Juniper, Marvell, Nvidia, Qualcomm, Synopsys and Xilinx. To accommodate this growing team, SiFive has recently moved to a new San Mateo location. The company also recently raised $8.5 million in Series B funding, led by Spark Capital, with participation from Osage University Partners and Sutter Hill Ventures. \n\n“SiFive is leading a revolution in the semiconductor industry,” Sherwani said. “By democratizing the design process, the entire spectrum of innovation will shift from a handful of centralized design centers to every corner of the world. When this happens, our industry will see a renaissance of new ideas, brought to life by new talent attracted by the prospect of changing the status quo.”\n\nSiFive was founded by the inventors of RISC-V – Andrew Waterman, Yunsup Lee and Krste Asanovic – with a mission to democratize access to custom silicon. In its first six months of availability, more than 1,000 HiFive1 software development boards have been purchased and delivered to developers in over 40 countries. Additionally, the company has engaged with multiple customers across its IP and SoC products, started shipping the industry’s first RISC-V SoC in November 2016 and announcing the availability of its Coreplex RISC-V based IP earlier this year. SiFive’s innovative “study, evaluate, buy” licensing model dramatically simplifies the IP licensing process, and removes traditional barriers that have limited access to customized, leading edge silicon.\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Yunsup Lee, Andrew Waterman and Krste Asanovic, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit [www.sifive.com.](https://www.sifive.com/)\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@sifive.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"XNnUAxAAACQAPah2","uid":"sifive-expands-into-silicon-forest-with-new-development","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XNnUAxAAACQAPah2%22%29+%5D%5D","tags":[],"first_publication_date":"2019-05-13T21:05:47+0000","last_publication_date":"2022-08-08T20:58:58+0000","slugs":["sifive-expands-into-silicon-forest-with-new-development-office-in-beaverton-oregon"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Expands into Silicon Forest With new Development Office in Beaverton, Oregon","spans":[]}],"publish_to":"Archive","publish_date":"2019-05-01","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"_Metropolitan Portland area has evolved into an international center of open source hardware development_\n\n**SAN MATEO, Calif., May 1, 2019 -** [SiFive](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and custom SoC solutions, today announced it is expanding into the metropolitan Portland area with the opening of a development office in Beaverton, Oregon. The primary mission of the office is to provide local support to existing SiFive customers and partners as well as to help fuel the mass adoption of the RISC-V Instruction Set Architecture (ISA) that is taking place in the region and throughout the world. The office will be managed by Sunil Shenoy, senior vice president and general manager of the RISC-V Business Unit at SiFive, and Ahmet Houssein, vice president of business development for HPC and data center solutions at SiFive. SiFive\u0026#39;s current development tools team, established in September 2018 and headed by Rick Leatherman, a local technology entrepreneur and now director of development tools for SiFive, will also operate from the new Beaverton office space.\r\n\r\n\u0026quot;The Portland area has become an international center of open source hardware development,\u0026quot; Shenoy said. \u0026quot;There is a steady stream of RISC-V based innovation at both large and small companies in the area. Establishing a presence in the robust Silicon Forest underscores our commitment to fostering the momentum of the RISC-V revolution.\u0026quot;\r\n\r\nHoussein added: \u0026quot;Having a team in Beaverton will help us better address the needs of data center designers and partners who are utilizing RISC-V based processors to achieve optimal performance. We look forward to accelerating their RISC-V based product development efforts and enabling many new and innovative use cases.\u0026quot;\r\n\r\nThe opening of the SiFive office in Beaverton coincides with the FOSSi Foundation\u0026#39;s premier North American open source digital design conference, Latch-Up. SiFive is proudly sponsoring this event to further the advancement of the RISC-V ISA. SiFive co-founder and chief engineer, Andrew Waterman, an ardent supporter of open source hardware development, will attend. Jack Koenig, software engineer at SiFive and a maintainer of the Chisel (Constructing Hardware in a Scala Embedded Language) and FIRRTL (Flexible Intermediate Representation for RTL) projects, will present \u0026quot;Higher-Order Hardware Design with Chisel3.\u0026quot; Additionally, Aliaksei Chapyzhenka, software engineer at SiFive, will present \u0026quot;Diagrams and System Visualization in Chip Design.\u0026quot; SiFive will also demonstrate its Linux-capable HiFive Unleashed RISC-V reference platform. The conference will take place in Portland, May 4-5, 2019. For more information, or to register to attend, please visit [fossi-foundation.org/latchup/](https://fossi-foundation.org/latchup/).\r\n\r\n**About SiFive**\n\r\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [www.sifive.com](https://www.sifive.com).","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrw","uid":"openedges-joins-sifives-designshare","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrw%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:48:25+0000","slugs":["openedges-joins-sifives-designshare"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"OPENEDGES Joins SiFive’s DesignShare","spans":[]}],"publish_to":"Archive","publish_date":"2018-08-14","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Aug. 14, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today announced a new member to its growing DesignShare economy: OPENEDGES, a provider of IPs for smart computing. The partnership makes available OPENEDGES’ ORBIT\u003csup\u003eTM\u003c/sup\u003e Memory Controller IP to system developers via DesignShare, which enables customers incorporate world-class IP into their prototypes without having to pay for IP costs upfront.\n\nWith the ORBIT\u003csup\u003eTM\u003c/sup\u003e Memory Controller, system designers can add DDR3, DDR4, LPDDR3, LPDDR4, LPDDR4x, GDDR6 and HBM2 to their SoCs. Its high-performance and low-power features unlock the full potential of DRAM technologies for many SoC use cases. OPENEDGES also will work with SiFive to extend its DesignShare IP portfolio to include ORBIT\u003csup\u003eTM\u003c/sup\u003e Interconnect (OIC), Memory Management Unit, Last Level Cache and AI Accelerator.\n\n“We are excited and proud to be a part of the DesignShare economy,” said Sean Lee, CEO and founder of OPENEDGES. “With our technologies, we hope to empower DesignShare customers to build their own SoC products, eventually contributing to and advancing the healthy growth of the broader SoC industry.”\n\nDesignShare helps lower common barriers to entry that have historically blocked smaller companies from developing custom silicon. Companies like SiFive, OPENEDGES and other DesignShare partners provide low- or no-cost IP to emerging companies, reducing the upfront engineering costs typically required to bring a custom chip from design to realization. Through DesignShare’s secure ecosystem, OPENEDGES and other partnered IP companies can provide solutions for developers to quickly optimize their SoCs with the open platform.\n\n“In an era where software is outpacing hardware, we strive to democratize the semiconductor industry and spur much-needed innovation,” said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. “With the addition of OPENEDGES to the DesignShare network, SiFive continues to level the playing field and simplify the SoC design process for all inventors and startups.”\n\nSince DesignShare launched in 2017, the program has grown to include a wide range of IP solutions, from complete ASIC solutions and trace technology to embedded memory and precision PLL.\n\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Intel Capital and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n\n## About OPENEDGES\n\nOPENEDGES is a semiconductor IP provider for smart computing empowering Internet of Smart Things. Committed to democratizing artificial intelligence technology at the edge devices, OPENEDGES delivers IPs in two key technology areas of smart computing; highly efficient Artificial Intelligence Acceleration and high-performance Memory Subsystem. By synergy of these two technologies, OPENEDGES offers sorely needed boost to performance, efficiency and reliability for Internet of Smart Things. For more information about OPENEDGES, visit [www.openedges.com](https://openedges.com/)\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (646) 756-3713\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W--tahAAAC0A3Opp","uid":"sifive-appoints-vp-of-soc-ip-to-lead-innovative-ip","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W--tahAAAC0A3Opp%22%29+%5D%5D","tags":[],"first_publication_date":"2018-11-17T06:07:10+0000","last_publication_date":"2022-08-08T20:51:28+0000","slugs":["sifive-appoints-vp-of-soc-ip-to-lead-innovative-ip-ecosystem"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Appoints VP of SoC IP to Lead Innovative IP Ecosystem","spans":[]}],"publish_to":"Archive","publish_date":"2018-11-16","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Mohit Gupta will oversee the rapidly expanding DesignShare program*\n\n**SAN MATEO, Calif. -- Nov. 16, 2018** -- SiFive, the leading provider\nof commercial RISC-V processor IP, today announced the appointment of\nMohit Gupta as vice president of SoC IP. Mohit will play a key role in\nleadership and business development of the company's SoC IP portfolio,\nincluding the DesignShare program, an IP ecosystem which has been\ninstrumental in lowering the cost of bringing chips from design to\nsilicon realization. He will report to Shafy Eltoukhy, senior vice\npresident and general manager of SiFive's Custom SoC Division.\n\n\"SiFive's SoC IP, and its popular DesignShare program, has contributed\nsignificantly to the entire semiconductor ecosystem by leveling the\nplaying field and democratizing access to custom silicon, which\npreviously was not possible due to upfront IP cost,\" said Mohit. \"I'm\nvery proud to be joining this team as we work toward expanding\ninnovation through shared knowledge and innovation.\"\n\nMohit has extensive expertise in semiconductor IP across product\nmarketing, business development and engineering. He recently served as\nsenior director of product marketing for the high speed SerDes and\ninterface IP cores portfolio at Rambus. Prior to that, he was the\ndirector of ASIC IP development at Open-Silicon, a SiFive company, where\nhe was instrumental in managing various SoC/ASIC and IP projects. Mohit\nhas also held various positions in design and applications engineering\nat Infineon Technologies and STMicroelectronics.\n\n\"Mohit brings a deep understanding of the SoC IP ecosystem, as well as a\nreputation for business development and strong IP partner engagement,\"\nsaid Shafy Eltoukhy SVP and GM of SiFive's Custom SoC Division. \"His\nexperience and leadership will be instrumental in fostering the\ncontinued growth and expansion of our DesignShare program and continuing\nthe mission of our SoC IP growth to meet the high quality and\nreliability expectations of our customers and ecosystem partners.\"\n\nMohit earned an executive MBA degree from the Indian Institute of\nManagement in Calcutta, India. He also holds a master's degree in\nmicroelectronics from the Birla Institute of Technology and Science in\nIndia, and a bachelor's degree in electronics and communication from\nThapar University in India.\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP,\ndevelopment tools and silicon solutions based on the free and open\nRISC-V instruction set architecture. Led by a team of seasoned silicon\nexecutives and the RISC-V inventors, SiFive helps SoC designers reduce\ntime-to-market and realize cost savings with customized,\nopen-architecture processor cores, and democratizes access to optimized\nsilicon by enabling system designers in all market verticals to build\ncustomized RISC-V based semiconductors. SiFive is located in Silicon\nValley and has backing from Sutter Hill Ventures, Spark Capital, Osage\nUniversity Partners, Chengwei, Huami, SK Hynix, Intel Capital, and\nWestern Digital. For more information, visit www.sifive.com.\n\n## Contact\n\n\u003caddress\u003e\nJamie Feller\u003cbr\u003e\nSHIFT Communications for SiFive\u003cbr\u003e\n\u003ca href=\"mailto:sifive@shiftcomm.com\"\u003esifive@shiftcomm.com\u003c/a\u003e\u003cbr\u003e\n(415) 591-8432\n\u003c/address\u003e\n","spans":[]}]}},{"id":"XMH1TBUAAJFPQlNV","uid":"sifive-announces-strategic-partnership-with-quicklogic","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XMH1TBUAAJFPQlNV%22%29+%5D%5D","tags":[],"first_publication_date":"2019-04-25T20:30:54+0000","last_publication_date":"2022-08-08T20:58:40+0000","slugs":["sifive-announces-strategic-partnership-with-quicklogic-and-launches-soc-templates-for-rapid-chip-design"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Announces Strategic Partnership with QuickLogic and Launches SoC Templates for Rapid Chip Design","spans":[]}],"publish_to":"Archive","publish_date":"2019-04-25","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"_RISC-V pioneer and ultra-low power leader bring Freedom Aware SoC Templates to market_\n\n**SAN MATEO, Calif. - April 25, 2019 -** [SiFive](https://www.sifive.com), the leading provider of RISC-V core IP, development tools, and silicon solutions, announced today the Freedom Aware (FA) family of SoC Templates and its strategic development partnership with QuickLogic Corporation (NASDAQ: QUIK), an innovator of ultra-low power voice-enabled SoCs, embedded FPGA IP, and endpoint AI software tools and solutions. The Freedom Aware family of SoC Templates extends SiFive\u0026#39;s chip design capabilities and radically lowers the cost and development time associated with new SoC designs.\r\n\r\nFreedom Aware SoC Templates revolutionize the SoC development process and lower risk through the use of tested building blocks and a full suite of sophisticated development tools that ensure finished SoCs mirror the results of pre-fabrication software emulations. Taking advantage of SoC Templates, users can greatly reduce the design cycle to only a few months, reduce the total cost to first silicon by an order of magnitude, and most importantly, provide custom silicon solutions while removing the dependency on large semiconductor design teams.\r\n\r\n\u0026quot;We are extremely proud of our strategic partnership with SiFive and the role we are playing in the development of the industry\u0026#39;s first family of SoC Templates,\u0026quot; said Brian Faith, president and CEO of QuickLogic. \u0026quot;SoC Templates are what the industry needs to accelerate the development and introduction of the highly diverse products that are broadly referred to as the Internet of Things. SoC Templates further our shared vision of democratizing technology and with that, significantly extend the potential and reach of our IP business model.\u0026quot;\r\n\r\nThe Freedom Aware SoC Templates leverage SiFive\u0026#39;s heterogeneous multi-core architecture and QuickLogic\u0026#39;s AI subsystem that is available with programmable acceleration and sophisticated power-management technology that delivers ultra-low power solutions optimized for battery-powered consumer and industrial IoT applications.\r\n\r\nThe Freedom Aware family of SoC Templates includes:\r\n\r\n**FA MCU for IoT**\r\n\r\nOptimized for industrial and commercial IoT devices, featuring multiple processors, security cores, hardware accelerators and always-on sensing. Applications include consumer IoT, industrial IoT, and wearables.\r\n\r\n**FA Predictive Maintenance (PdM 4.0)**\r\n\r\nDesigned to support digital and analog sensors used in Industry 4.0 predictive maintenance protocols. Optimized for power-efficient performance in industrial, automotive and AI/ML applications.\r\n\r\n**FA Always-on Voice Processor**\r\n\r\nOptimized for smart devices and mobile handsets, featuring multiple microphone processors and accelerators to enable superior far and near field, close talk and acoustic use cases.Applications include smart speakers, voice assistants, smart appliances and smartphones.\r\n\r\nSiFive and QuickLogic are working with a select number of pioneering potential customers via the FA Early Adopter program. Companies that join the Early Adopter program will have exclusive, early access to the Freedom Aware SoC Templates, the ability to add features and will be able to develop SoC designs that will be ready to launch next year.\r\n\r\n\u0026quot;Our Core IP Series has driven greater intelligence at the edge. Now, with the new Freedom Aware family of SoC Templates, we are responding to the need for a complete, economical, and rapid time-to-market SoC solution,\u0026quot; said Naveed Sherwani, president and CEO of SiFive. \u0026quot;Freedom Aware combines QuickLogic\u0026#39;s IP and expertise in ultra-low-power SoC design with SiFive\u0026#39;s leadership in RISC-V processing and design platforms to produce powerful and agile SoC Templates for the targeted applications. With these resources, and the sophisticated development tools that support them, we are opening vast new markets for innovation by democratizing SoC design.\u0026quot;\r\n\r\n**About SiFive:**\r\n\r\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 9 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [www.sifive.com](https://www.sifive.com).\r\n\r\n**About QuickLogic:**\r\n\r\nQuickLogic develops low power, multi-core semiconductor platforms and Intellectual Property (IP) for Artificial Intelligence (AI), voice and sensor processing. The solutions include an embedded FPGA IP (eFPGA) for hardware acceleration and pre-processing, and heterogeneous multi-core SoCs that integrate eFPGA with other processors and peripherals. The Analytics Toolkit from the company\u0026#39;s wholly-owned subsidiary, SensiML completes the \u0026#39;full stack\u0026#39; end-to-end solution with accurate sensor algorithms using AI technology. The full range of platforms, software tools and eFPGA IP enables the practical and efficient adoption of AI, voice and sensor processing across the multitude of mobile, wearable, hearable, consumer, industrial, edge and endpoint IoT applications. For more information, visit [www.quicklogic.com](https://www.quicklogic.com) and [www.quicklogic.com/blog/](https://www.quicklogic.com/blog/).","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrk","uid":"sifive-and-microsemi-expand-relationship-with-strategic-roadmap-alignment-and-linux-capable-risc-v-development-board","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrk%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:41:04+0000","slugs":["sifive-and-microsemi-expand-relationship-with-strategic-roadmap-alignment-and-a-linux-capable-risc-v-development-board"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and Microsemi Expand Relationship with Strategic Roadmap Alignment and a Linux-Capable, RISC-V Development Board","spans":[]}],"publish_to":"Archive","publish_date":"2017-11-28","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN JOSE, Calif. – Nov. 28, 2017 – \u003c/span\u003e\n[SiFive](https://www.sifive.com/),\nthe first fabless provider of customized, open-source-enabled semiconductors,\nand Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor\nsolutions differentiated by power, security, reliability and performance, at\nthe 7th RISC-V Workshop today announced the companies have formed a strategic\nrelationship to meet the growing interest and demand in the RISC-V instruction\nset architecture. The companies have previously collaborated to provide RISC-V\nsoft CPU cores for Microsemi’s PolarFire\u003csup\u003e®\u003c/sup\u003e FPGAs, IGLOO™2 FPGAs, SmartFusion™2\nsystem-on-chip (SoC) FPGAs and RTG4™ FPGAs, currently available as part of the\nMicrosemi Mi-V RISC-V ecosystem.\n\nThe expanded relationship includes roadmap alignment on future CPU features to\nfacilitate additional end markets and applications, and expand adoption of the\nfree and open RISC-V instruction set architecture in areas such as machine\nlearning, storage, networking, gateways and smart IoT devices. The\ncollaboration between the two RISC-V leaders will enable clear targets and\nroadmaps for ecosystem software and tools vendors.\n\nThe companies also announced the HiFive Unleashed, a development board based on\nSiFive’s RISC-V-based Freedom Unleashed platform and Microsemi’s PolarFire\u003csup\u003e®\u003c/sup\u003e\nFPGAs, to be available in the first quarter of 2018 for software developers\nworldwide.\n\n\"Our strategic relationship with SiFive is the latest demonstration of\nMicrosemi's continued leadership in driving the advancement of the RISC-V\necosystem,\" said Jim Aralis, chief technology officer and vice president of\nadvanced development at Microsemi. \"The powerful combination of PolarFire and\nFreedom Unleashed will further enable the development of RISC-V-based designs\nand, ultimately, extend the reach of custom silicon.\"\n\nThe HiFive Unleashed development board will enable firmware, kernel and driver\ndevelopment, enabling RISC-V designs with full operating systems such as Linux,\nUnix or FreeBSD. Engineers will be able to develop custom RISC-V designs by\nprototyping with the combination of the Freedom U500 SoC and PolarFire FPGA.\nRunning at over 1.5GHz, the Freedom U500 is the first Linux-capable, RISC-V\nbased SoC in the market. The Freedom U500, designed in 28nm, features the\nrecently announced SiFive U54-MC RISC-V core complex, which includes five\ncache-coherent 64-bit CPU cores and a coherent 2MB L2 cache subsystem. The\nHiFive Unleashed development board enables easy software development with a\nwide variety of peripherals including DDR4, Gigabit Ethernet, PCIe, USB and\nChipLink.\n\nMicrosemi’s PolarFire FPGAs are cost-optimized, lowest power, mid-range density\ndevices making them ideal for developing a wide variety of RISC-V-based\napplications. The PolarFire FPGA will interface to the SiFive Freedom U500 via\na ChipLink interconnect and a variety of additional peripherals will be\nsupported. \n\n\"SiFive is excited to expand our work with Microsemi, which will allow both\ncompanies to continue to reduce the risk and ease the path to develop custom\nsilicon,\" said Naveed Sherwani, CEO, SiFive. \"By combining SiFive’s\nindustry-leading, RISC-V-based Freedom Unleashed platform with Microsemi’s\ncost-optimized PolarFire family of FPGAs, we are continuing to expand the\nresources available to the growing RISC-V community of developers and system\ndesigners. We can’t wait to see the innovations that will be made possible\nthrough HiFive Unleashed.\"\n\nThe HiFive Unleashed will be commercially available in the first quarter of 2018.\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the\nfree and open RISC-V instruction set architecture. Founded by RISC-V inventors\nAndrew Waterman, Yunsup Lee and Krste Asanovic, SiFive democratizes access to\ncustom silicon by helping system designers reduce time-to-market and realize\ncost savings with customized RISC-V based semiconductors. SiFive is located in\nSilicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital\nand Osage University Partners. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## About Microsemi\n\nMicrosemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of\nsemiconductor and system solutions for aerospace \u0026 defense, communications,\ndata center and industrial markets. Products include high-performance and\nradiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and\nASICs; power management products; timing and synchronization devices and\nprecise time solutions, setting the world's standard for time; voice processing\ndevices; RF solutions; discrete components; enterprise storage and\ncommunication solutions, security technologies and scalable anti-tamper\nproducts; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as\ncustom design capabilities and services. Microsemi is headquartered in Aliso\nViejo, California, and has approximately 4,800 employees globally. Learn more\nat www.microsemi.com.\n\nMicrosemi and the Microsemi logo are registered trademarks or service marks of\nMicrosemi Corporation and/or its affiliates. Third-party trademarks and service\nmarks mentioned herein are the property of their respective owners.\n\n\"Safe Harbor\" Statement under the Private Securities Litigation Reform Act of\n1995: Any statements set forth in this news release that are not entirely\nhistorical and factual in nature, including without limitation statements\nrelated to SiFive and Microsemi at the 7th RISC-V Workshop here today\nannouncing the companies have formed a strategic relationship to meet the\ngrowing interest and demand in the RISC-V instruction set architecture, and its\npotential effects on future business, are forward-looking statements. These\nforward-looking statements are based on our current expectations and are\ninherently subject to risks and uncertainties that could cause actual results\nto differ materially from those expressed in the forward-looking statements.\nThe potential risks and uncertainties include, but are not limited to, such\nfactors as rapidly changing technology and product obsolescence, potential cost\nincreases, variations in customer order preferences, weakness or competitive\npricing environment of the marketplace, uncertain demand for and acceptance of\nthe company's products, adverse circumstances in any of our end markets,\nresults of in-process or planned development or marketing and promotional\ncampaigns, difficulties foreseeing future demand, potential non-realization of\nexpected orders or non-realization of backlog, product returns, product\nliability, and other potential unexpected business and economic conditions or\nadverse changes in current or expected industry conditions, difficulties and\ncosts of protecting patents and other proprietary rights, inventory\nobsolescence and difficulties regarding customer qualification of products. In\naddition to these factors and any other factors mentioned elsewhere in this\nnews release, the reader should refer as well to the factors, uncertainties or\nrisks identified in the company's most recent Form 10-K and all subsequent Form\n10-Q reports filed by Microsemi with the SEC. Additional risk factors may be\nidentified from time to time in Microsemi's future filings. The forward-looking\nstatements included in this release speak only as of the date hereof, and\nMicrosemi does not undertake any obligation to update these forward-looking\nstatements to reflect subsequent events or circumstances.\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com \n\u003c/address\u003e\n\n\u003caddress\u003e\n Beth P. Quezada\u003cbr\u003e\n Microsemi Corporation\u003cbr\u003e\n (949) 380-6102\u003cbr\u003e\n Beth.quezada@microsemi.com \n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vq8","uid":"wasiela-brings-encryption-fec-and-connectivity-ip-to-designshare","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vq8%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:44:28+0000","slugs":["wasiela-brings-encryption-fec-and-connectivity-ip-to-designshare"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Wasiela Brings Encryption, FEC and Connectivity IP to DesignShare","spans":[]}],"publish_to":"Archive","publish_date":"2018-09-13","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Sept. 13, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today announced that Wasiela, a provider of innovative PHY-layer IP from the system and algorithmic levels all the way to implementation, has joined the DesignShare ecosystem. The availability of Wasiela encryption, forward error correction (FEC) and connectivity IP through the program will ease the development of reliable and secure high-throughput data communications for the RISC-V platform.\n\nSpecific IP Wasiela plans to make available through DesignShare’s secure ecosystem includes its AES IP core and ECC for encryption; BCH, Reed Solomon, LDPC and Turbo Encoders/Decoders for FEC; and ZigBee Transceiver PHY and OFDM-based cores for connectivity. All Wasiela cores serve as accelerators or slave peripherals to RISC-V processors and are easily integrated via the TileLink interface.\n\n“RISC-V represents a new wave of growth and innovation in the semiconductor industry, and we are excited to join SiFive in the DesignShare ecosystem,” said Ahmed Shalash, President, Wasiela. “Wasiela enables system designers to incorporate leading IP to ensure the quality and consistency of data communications for consumer electronics on any platform, now including RISC-V.”\n\nAny company, inventor or maker can harness the power of custom silicon with little to no upfront risk through the SiFive DesignShare program. To lower the costs of bringing a chip from design to realization, DesignShare partners like Wasiela offer pre-integrated solutions that enable users to develop their prototypes without the investment in upfront engineering costs typically required.\n\n“Wasiela’s IP can offer DesignShare participants an edge in developing ultra-low power, configurable designs to ensure the integrity of data communications,” said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. “The growing ecosystem of DesignShare IP providers like Wasiela ensures that aspiring system designers have a catalog of IP from which to choose when designing their SoC.”\n\nSince DesignShare launched in 2017, the ecosystem has grown to include a wide range of IP solutions, from debug and trace technology to security cores and reconfigurable FPGA.\n\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Intel Capital and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jamie Feller\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8432\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"XYQ9JhAAACcApmZm","uid":"intensivate-engages-sifives-risc-v-expertise-to-develop","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XYQ9JhAAACcApmZm%22%29+%5D%5D","tags":[],"first_publication_date":"2019-09-20T16:27:08+0000","last_publication_date":"2022-08-08T20:59:34+0000","slugs":["intensivate-engages-sifives-risc-v-expertise-to-develop-leading-accelerator"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Intensivate Engages SiFive’s RISC-V Expertise to Develop Leading Accelerator","spans":[]}],"publish_to":"Archive","publish_date":"2019-09-19","share_image":{"link_type":"Media","kind":"image","id":"XYQ8hRAAACgApmOe","url":"https://images.prismic.io/sifive%2Fd7442e69-0a15-471e-86a5-8afe28537e28_intensivate-accelerator.png?auto=compress,format","name":"intensivate-accelerator.png","size":"428839","width":"1178","height":"659"},"body":[{"type":"preformatted","text":"*Proven Expertise In Developing Custom Silicon Drives Datacenter Innovation*\n\n**SAN MATEO, Calif. – September 19th, 2019** – [SiFive, Inc.](Https://www.sifive.com), the leading provider of commercial RISC-V processor IP and silicon solutions, announced today that [Intensivate](http://intensivate.com/), an innovative new provider of acceleration for clustered computing within datacenters and edge deployments, has begun its production ramp after successfully implementing SiFive Tilelink and cache technologies to provide a chip-scale coherent fabric as part of the new, high-performance Intensivate PCIe Card. \r\n\r\n## Business Intelligence\r\n\r\nIntensivate’s accelerator card provides 12x more compute per dollar on platforms such as Hadoop, Kafka, Spark, NoSQL databases and other custom applications running on clusters. These performance increases will enable rapid, agile decision making while improving datacenter efficiency and lowering TCO. \r\n\r\n“The era of the general-purpose processor for all workloads is fading,” said Peter Rutten, IDC's research director for its Infrastructure Systems, Platforms and Technologies Group. “Instead new processors and co-processors – or accelerators – have started to take over specific compute tasks for greater performance and efficiency. Our research shows that the worldwide accelerated server market, for example, will rapidly grow to $25.6B by 2022. If successful, the technology that Intensivate is developing could address a large class of applications that are currently not well served by existing accelerators, expanding the opportunities for server consolidation.”\r\n\r\n## Intensivate Cluster Compute Accelerator\r\n\r\nThe Intensivate accelerator card is designed to focus on compute performance improvements for the business operations software key to modern business. AI accelerators, GPUs, FPGAs, and Custom ASICs are focused on deep learning or narrow function accelerations. Intensivate is going outside this class of acceleration by addressing applications that run on clusters and imposing no specialized software requirements typically seen with accelerator technologies. Leveraging the robust RISC-V ISA tools, software, and industry ecosystem, Intensivate, in partnership with SiFive, has created a high performance, high-efficiency chip that consumes only 14W. \r\n\r\nA high-speed 120Gbps chip-to-chip mesh network allows the twenty-one chips on the accelerator to support network-intensive scale-out applications. Each chip is combined with 32GB of quad-channel LP-DDR4 to feed data into the 16 Intensivate designed cores inside. Each combination of chip and memory is equivalent to a 1U server node, providing twenty-one server nodes on a single PCIe card. \r\n\r\nThe high-speed, compute-dense accelerator card offers superb ROI savings, with a 1000-Node Hadoop cluster able to be matched in performance by just 84-Nodes when equipped with Intensivate accelerator cards, delivering over $1M in CapEx and Power savings over a 3-year period. \r\n\r\n## Enabling New Solutions\r\n\r\n“Enabling innovative new solutions to augment the performance capabilities of today’s datacenters is central to SiFive’s mission,” said Naveed Sherwani, president and CEO of SiFive. “SiFive is proud to support the rapid introduction of high-performance RISC-V based accelerators developed by Intensivate to reduce analysis cycle time while increasing ROI for Scale Out Accelerator equipped datacenters.”\r\n\r\n“Our product development strategy is aimed at bringing a product up relatively quickly and cost effectively while tapping into the fast-growing ecosystem of RISC-V,” said Sam Sirisena, chief strategy officer and co-founder of Intensivate. “We intend to build our alliances using the RISC-V ecosystem while contributing towards it. This is a winning situation for everyone involved: our end users, channel partners and the open source community at large.”\r\n\r\nFirst Silicon is scheduled for early 4Q20. PCIe accelerator cards for first customer shipment is early 2021. \r\n\r\n## About SiFive\r\n\r\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [www.sifive.com](https://www.sifive.com).\r\n\r\n## About Intensivate\r\n\r\nIntensivate is a developer of high performance, low power server acceleration products for\r\napplications running on clusters. Intensivate’s accelerator card provides a 12x boost in\r\ncomputational power with no added data center costs and no required software changes for the user. For more information please visit [www.intensivate.com](http://intensivate.com/).\r\n\r\n## MEDIA CONTACTS\n\nSara Dodrill \nSHIFT Communications for SiFive \n415-591-8429 \nsdodrill@shiftcomm.com\n\r\nIntensivate \nSerge Sirisena \nVP Business Development \nserge@intensivate.com \n\n## Press References: \nPeter Rutten \nResearch Director, Infrastructure Systems, Platforms, and Technologies Group \nIDC \nprutten@idc.com \r\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrE","uid":"corigine-adds-certified-usb-ip-to-sifives-growing-designshare-economy-to-accelerate-adoption-of-risc-v","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrE%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:47:03+0000","slugs":["corigine-adds-certified-usb-ip-to-sifives-growing-designshare-economy-to-accelerate-adoption-of-risc-v"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Corigine adds certified USB IP to SiFive’s Growing DesignShare Economy to Accelerate Adoption of RISC-V","spans":[]}],"publish_to":"Archive","publish_date":"2018-03-08","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – March 8, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com), the leading provider of commercial RISC-V processor IP, today announced the addition of Corigine, a fabless semiconductor and IP company, to the DesignShare economy.\n\nThrough this partnership, Corigine will make available its USB-IF certified USB 3.1 Gen 1 and Gen 2, and USB 2.0 device, PC host and dual-role controller IP solutions for SiFive’s Freedom platform as part of the DesignShare initiative.\n\nAdoption of USB 3.1 Gen 2 is being driven by a broad range of applications, most many involving large file sizes or high-resolution video streams, that demand high bandwidth. System designers will benefit from Corigine’s optimized, next-generation USB architecture that delivers the smallest size, lowest power and maximum configuration. The reduced gate count will contribute to less memory requirement, which lowers overall system cost. The logic sharing between device and host will further reduce the area consumption, providing the most economical and efficient solution for customers.\n\n“The cost to bring a chip from design to realization continues to increase. This severely limits innovation to a handful of companies and inventors that have the money and time to come up with new designs,” said Shafy Eltoukhy, VP of operations and head of DesignShare at SiFive. “Companies like Corigine recognize the opportunities DesignShare provides, and we’re excited to bring new alternatives for aspiring inventors.”\n\nThe DesignShare ecosystem provides any company, inventor or maker the ability to harness the power of custom silicon with little to no upfront risk. Companies like SiFive, Corigine and other DesignShare partners have developed efficient, pre-integrated solutions to enable users to develop their prototypes without the significant investment in upfront engineering costs typically required to bring a custom chip design to realization.\n\n“The innovative approach of DesignShare is encouraging more silicon designs in an area where we see tremendous growth,” said Ali Khan, VP of business and product development, Corigine. “Corigine is committed to providing differentiating IP solutions to benefit more customers, and we believe that participating in DesignShare will help lower the design barriers and add value to the semiconductor ecosystem.”\n\nSince DesignShare launched last year, the ecosystem has grown to include a wide range of IP solutions, from debug and trace technology to reconfigurable FPGA.\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit \n[www.sifive.com](https://www.sifive.com).\n\n## About Corigine\n\nCorigine, Inc. is a fabless semiconductor and IP company headquartered in Santa Clara, Calif., with design centers in Shanghai, Nanjing and Hong Kong, China. Corigine delivers intellectual property (IP) solutions for high-speed I/O as well as semiconductor products for connectivity, storage and machine learning applications targeted at cloud, automotive and smart city markets. Corigine's seasoned IP experts from top fabless semiconductor companies leverage an advanced architecture to deliver innovations for emerging applications for reduced power, area and memory utilization while ensuring maximum performance and configurability.\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (646) 756-3713\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Miranda Chen\u003cbr\u003e\n Corigine\u003cbr\u003e\n (415) 653-9977\u003cbr\u003e\n miranda.chen@corigine.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"XHRWTREAACEAa6Cg","uid":"dinoplusai-partners-with-sifive-to-develop-mission-critical","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XHRWTREAACEAa6Cg%22%29+%5D%5D","tags":[],"first_publication_date":"2019-02-25T21:28:07+0000","last_publication_date":"2022-08-08T20:57:25+0000","slugs":["dinoplusai-partners-with-sifive-to-develop-mission-critical-ai-processor-platform-for-high-performance-processing-with-ultra-low-latency"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"DinoplusAI Partners with SiFive to Develop Mission-Critical AI Processor Platform for High Performance Processing with Ultra-Low Latency","spans":[]}],"publish_to":"Archive","publish_date":"2019-02-25","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Optimized for data centers, 5G/edge cloud and autonomous vehicles*\n\n*Includes SiFive RISC-V E34 Management Core and proprietary DinoplusAI engine, and will be realized into working silicon by SiFive's Custom SoC Division using robust ASIC design and manufacturing methodology*\n\n**SAN MATEO, Calif. – Feb. 25, 2019 –**\n\nSiFive, the leading provider of commercial RISC-V processor core IP, design platforms and silicon solutions, today announced that it was selected by DinoplusAI, an innovator in artificial intelligence (AI) processors and software for high performance mission-critical applications, to develop its mission-critical AI processor platform, which is optimized for ultra-low latency applications, such as data centers, 5G/edge cloud and autonomous vehicles. The DinoplusAI processor platform combines the SiFive RISC-V E34 Management Core with a proprietary AI engine from DinoplusAI. In addition, SiFive's Custom SoC Division will provide industry-proven robust RTL-to-physical design custom SoC implementation methodology to ensure first-time working silicon and enable high-volume production.\r\n\r\nThe DinoplusAI processor platform provides consistent ultra-low latency, mitigating the common constraints of high-performance AI processing. The DinoplusAI processor features a scalable architecture, software stack and user interfaces. It not only addresses the computing power and energy efficiency required in AI applications, but also the latency, security and reliability that designers of AI products and services rely on. The processor platform is highly consistent and predictable, and has achieved the industry's lowest latency at low batch size, which is critical in AI applications.\r\n\r\n\"We chose to partner with SiFive because of the company's leadership in RISC-V cores, and its proven success in ASIC design and manufacturing of fully optimized SoCs,\" said Jay Hu, CEO of DinoplusAI. \"This expertise, combined with our IP blocks for AI, will result in a truly unique solution that optimizes inference with a focus on performance, power efficiency, ultra-low latency, assured security and reliability.\"\r\n\r\n\"The DinoplusAI processor, with superior DeepBench LSTM performance, enables more than 4,000 real-time audio streams with a computation latency of less than 1ms for Rokid's acoustic model, an industry leading cloud speech recognition algorithm,\" said Dr. Yi Rao, director of the R-lab at Rokid.\r\n\r\n\"Meeting the ultra-low latency challenges of AI applications requires a successful platform approach that comprises of a new class of silicon IP, cores and advanced physical implementation techniques,\" said Naveed Sherwani, CEO of SiFive. \"The DinoplusAI processor platform features powerful IP, specifically designed by DinoplusAI for next-generation AI applications. We will integrate these AI IP blocks into our 16nm FinFET design platform based on the SiFive RISC-V E34 management core to deliver a complete silicon solution.\"\r\n\r\n**About DinoplusAI**\r\n\r\n\nDinoplusAI designs and produces AI processors and software for data centers, 5G/edge cloud computing, autonomous driving and other mission-critical applications. The company's unique approach optimizes performance, power efficiency and ease of use, while also enabling cost-effective training. DinoplusAI was founded in 2017 and is headquartered in Fremont, CA. For more information, visit http://dinoplus.ai/.\r\n\r\n**About SiFive**\r\n\r\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [https://www.sifive.com](https://www.sifive.com).\r\n\r\n**SOURCE: SiFive**\r\n\r\nRelated Links\r\n[https://www.sifive.com](https://www.sifive.com)","spans":[]}]}},{"id":"XPl3CxEAACAAQEjs","uid":"sifive-secures-65.4-million-in-series-d-funding2","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XPl3CxEAACAAQEjs%22%29+%5D%5D","tags":[],"first_publication_date":"2019-06-06T20:35:58+0000","last_publication_date":"2022-08-08T20:59:17+0000","slugs":["sifive-secures-65.4-million-in-series-d-funding"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Secures $65.4 Million In Series D Funding","spans":[]}],"publish_to":"Archive","publish_date":"2019-06-06","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*RISC-V Leader\u0026#39;s Global Hypergrowth Attracts Strong Venture Backing*\n\n## SAN MATEO, Calif., - June 6, 2019 –\n\n[SiFive](https://c212.net/c/link/?t=0\u0026amp;l=en\u0026amp;o=2489984-1\u0026amp;h=791941090\u0026amp;u=https%3A%2F%2Fwww.sifive.com%2F\u0026amp;a=SiFive), Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced it raised $65.4 million in a Series D round led by existing investors Sutter Hill Ventures, Chengwei Capital, Spark Capital, Osage University Partners and Huami, alongside new investor Qualcomm Ventures LLC. This Series D round brings the total investment to date in SiFive to more than $125 million.\r\n\r\n\u0026quot;SiFive continues to drive rapid RISC-V growth, development and adoption,\u0026quot; said Stefan Dyckerhoff, managing director at Sutter Hill Ventures and member of the SiFive board of directors. \u0026quot;We are seeing significant traction across numerous markets and verticals, as evidenced by SiFive\u0026#39;s [101 design wins](https://c212.net/c/link/?t=0\u0026amp;l=en\u0026amp;o=2489984-1\u0026amp;h=3244622178\u0026amp;u=https%3A%2F%2Fwww.sifive.com%2Fpress%2Fsifive-celebrates-historic-100-design-win-milestone\u0026amp;a=101+design+wins). SiFive\u0026#39;s expertise in RISC-V Core IP, complete silicon solutions and a native cloud environment is a key differentiator. Sutter Hill Ventures continues to strongly believe in – and invest in – SiFive\u0026#39;s vision to democratize access to custom silicon.\u0026quot;\r\n\r\nThis latest round of investment will further enable and accelerate SiFive\u0026#39;s global expansion and technology development. In the past 18 months, SiFive has grown from fewer than 40 employees in a single office to more than 400 employees across 15 locations globally. SiFive now has offices in Beaverton, Ore.; San Mateo and Milpitas, Calif.; Austin, Texas; Boston; Bangalore and Pune, India; Shanghai; Seoul, Korea and Hsinchu, Taiwan.\r\n\r\n\u0026quot;Qualcomm Ventures invests in innovative technology companies that have the potential to transform industries.\u0026quot; said Quinn Li, senior vice president, Qualcomm Technologies Inc. and global head of Qualcomm Ventures. \u0026quot;SiFive has established itself as a leader in the RISC-V space making significant contributions to the broader semiconductor industry through its unique design methodology. We are excited to invest in SiFive to bring the potential of RISC-V to wireless and mobile.\u0026quot;\r\n\r\nSiFive is uniquely positioned to take advantage of the need for custom silicon as device manufacturers rapidly adopt domain-specific application processor designs in response to the point of compute migrating to the Edge. Both customers and investors seek SiFive\u0026#39;s compelling portfolio of solutions, strategic partnerships, and its cloud platform.\r\n\r\n\u0026quot;We are honored and privileged to have the backing, expertise, and experience of our investors and our board,\u0026quot; said Naveed Sherwani, president and CEO of SiFive. \u0026quot;Hypergrowth and industry disruption cannot happen without bold commitment. We are proud to count on our incredible investors and champions as a key part of how we grow in select markets and verticals, access platforms and technologies, find talent, and partner with giants in order to realize our vision.\u0026quot;\r\n\r\n## **About SiFive**\r\n\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [www.sifive.com](https://c212.net/c/link/?t=0\u0026amp;l=en\u0026amp;o=2489984-1\u0026amp;h=1557387924\u0026amp;u=http%3A%2F%2Fwww.sifive.com%2F\u0026amp;a=www.sifive.com).","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrO","uid":"think-silicon-joins-sifives-growing-designshare-ecosystem","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrO%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:48:09+0000","slugs":["think-silicon-joins-sifives-growing-designshare-ecosystem"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Think Silicon Joins SiFive’s Growing DesignShare Ecosystem","spans":[]}],"publish_to":"Archive","publish_date":"2017-12-05","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN JOSE, Calif. – Nov. 28, 2017 – \u003c/span\u003e\n[SiFive](https://www.sifive.com/),\nthe first fabless provider of customized, open-source-enabled semiconductors,\ntoday announced that Think Silicon, a leader in developing ultra-low power\ngraphics IP technology, has joined the growing \nDesignShare economy. Through\nDesignShare, Think Silicon will make its complementary NEMA\u003csup\u003e®\u003c/sup\u003e\u0026#124;GPU and\nNEMA\u003csup\u003e®\u003c/sup\u003e\u0026#124;dc IP available for SiFive’s Freedom SoCs Platform at reduced\nupfront investment from customers.\n\nWith a silicon footprint 2.5 times smaller than competitive IP, Think Silicon’s\nproprietary compression techniques reduce the memory size six-fold, eliminating\nthe need for external DDR memory. The result is a reduction of active power\nconsumption by 73 percent, and 58 percent in idle mode.\n\n“The DesignShare concept is the key platform that will help Think Silicon\nextend its ultra-low power GPU technology into the next generation of mobile\nand embedded display devices and provide developers with the necessary tool\nchain for an easy integration and application development,” said Ulli Mueller,\nvice president of marketing and business development, Think Silicon. “We are\nexcited to partner with SiFive and the other DesignShare participants breaking\ndown barriers to assist and encourage customers developing innovative\nproducts.” \n\nSince the launch of the DesignShare initiative earlier this summer, companies\nlike Think Silicon have provided low- or no-cost IP for proof of concept\nprojects and to emerging companies, lowering the upfront engineering costs\nrequired to bring a custom chip design based on the SiFive Freedom platform to\nrealization. In turn, this gives any company, inventor or maker the ability to\nharness the power of custom silicon, enabling an entirely new range of\napplications.\n\n“It’s exciting to see SiFive’s DesignShare movement grow as more companies are\ntaking up the mantle to help reduce the barriers that have traditionally\nblocked system designers from developing custom silicon,” said Shafy Eltoukhy,\nhead of the DesignShare program at SiFive. “With Think Silicon on board the\nDesignShare initiative, we look forward to seeing the inventions inspired by\nour collaboration.”\n\nIn addition to Think Silicon’s ultra-low power graphics and memory IP,\ndevelopers can access cryptographic cores, precision clocking macros, embedded\nanalytics, debug and trace technology, embedded, reconfigurable FPGA and\nlogic-based, non-volatile memory through the DesignShare program.\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the\nfree and open RISC-V instruction set architecture. Founded by RISC-V inventors\nAndrew Waterman, Yunsup Lee and Krste Asanovic, SiFive democratizes access to\ncustom silicon by helping system designers reduce time-to-market and realize\ncost savings with customized RISC-V based semiconductors. SiFive is located in\nSilicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital\nand Osage University Partners. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## About Think Silicon\n\nThink Silicon S.A. is a privately held Limited Company located in: Patras/\nGreece (HQ), Toronto/ Canada (Business Development \u0026 Marketing office), San\nJose/CA, USA (Sales office), Cologne, Germany/EMEA region (Sales office),\nTaipei/TW (Sales office), Tokyo/JP (Sales office). Think Silicon is specialized\nin developing and licensing high-performance graphics and AI IP technology for\nultra-low power and area limited digital mobile, wearable, embedded devices and\nIoT end-nodes for fabless semiconductor technology customers. \n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (646) 756-3713\u003cbr\u003e\n sifive@shiftcomm.com \n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8_wgxQAALZs6F7P","uid":"berkeley-skydeck-launches-first-official-chip-track","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8_wgxQAALZs6F7P%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-24T04:33:50+0000","last_publication_date":"2022-08-08T20:51:13+0000","slugs":["berkeley-skydeck-launches-first-official-chip-track-for-startups-to-help-bring-silicon-back-to-silicon-valley"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Berkeley SkyDeck Launches First Official ‘Chip Track’ for Startups to Help Bring Silicon Back to Silicon Valley","spans":[]}],"publish_to":"Archive","publish_date":"2018-10-22","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"**Berkeley SkyDeck Collaborates with TSMC, Cadence, and SiFive to Provide Expertise and Support for its New Accelerator Chip Track**\n\n\u003cspan class=\"dateline\"\u003eBerkeley, CA – October 22, 2018 — \u003c/span\u003e [UC Berkeley SkyDeck](http://skydeck.berkeley.edu/), the premier startup accelerator of the University of California at Berkeley (UC Berkeley), is leading a resurgence of semiconductor innovation by introducing a new Chip Track at the Berkeley SkyDeck startup accelerator. Starting with the first cohort of 2019, startups focused on semiconductor design and other related technologies will be offered the dedicated resources necessary to help them achieve their goals, including expertise from key scientific and industry advisors. \n\nAs part of the SkyDeck program, Cadence, a leading IC design tool company, TSMC (Taiwan Semiconductor Manufacturing Co), the world’s largest independent semiconductor foundry, and SiFive, a rapidly expanding startup building processor cores and SoC’s based on UC Berkeley’s open-source RISC-V architecture, are collaborating to support SkyDeck’s plans for the design environment of the new Chip Track. \n\nBerkeley SkyDeck is accepting applications for the Chip Track and its entire Spring 2019 Accelerator and Incubator (Hot Desk) programs now through October 31st.\n\nOver the past two decades Silicon Valley has become increasingly focused on software and business model innovation, while startups in the semiconductor industry have struggled to gain traction and raise early stage venture funding. The greatest challenge semiconductor startups face today is the high initial cost involved with prototyping new chip designs. Without functioning prototypes and firm customer commitments, founders in the semiconductor space can often struggle to attract initial funding. \n\nBy participating in the 12-month long Chip Track, startups developing chips for applications ranging from machine learning to computer vision, from high-performance data centers to low-power embedded IoT, will receive $100k in investment from the Berkeley SkyDeck Fund and access to a variety of resources from industry collaborators. For founders, this could be an opportunity to materialize their initial design in silicon, and even take their product to market before having to raise outside funding.\n\nThe one-of-a-kind service offerings and technical expertise from these industry companies are not available to these founders anywhere else. “The real-world industry guidance of these collaborators coupled with the top engineers and professors from UC Berkeley’s academic ecosystem will provide chip companies with a unique opportunity to excel, thrive and make deep connections to help them develop extraordinary technology that could change the world,” said Caroline Winnett, Executive Director, Berkeley SkyDeck.\n\n“This new program will help bring the silicon back to Silicon Valley,” said Chon Tang, managing director, Berkeley SkyDeck Fund. “By collaborating with key industry leaders like Cadence, TSMC and SiFive - and with the long history of Berkeley’s research labs and alumni responsible for many of the semiconductor companies which defined this space, Berkeley SkyDeck is going to enable a new generation of semiconductor startup founders.”\n\nAdvisors to the new chip startups include leading UC Berkeley faculty such as the inventor of RISC-V, Professor Krste Asanovic, and Professor Emeritus and Turing Award winner David Patterson. Says Professor Patterson, “The market need for break-through technologies in the semiconductor space have become increasingly obvious; Moore’s Law is beginning to fail, just as novel use cases for AI and IoT places new demands on chip designs. It is time for a specialized Chip Track to bring the best talent, the most in-depth guidance and industry experience together to support creative startup founders as they develop the next chip architecture.”\n\nFor more information visit Berkeley SkyDeck at [http://skydeck.berkeley.edu/](http://skydeck.berkeley.edu/). Applications for the Spring 2019 cohort are available here: [http://skydeck.berkeley.edu/about/apply/](http://skydeck.berkeley.edu/about/apply/)\n \n## ABOUT BERKELEY SKYDECK\nAs UC Berkeley’s premier startup accelerator, Berkeley SkyDeck is a joint program of the UC Berkeley Haas School of Business, the College of Engineering, and the Office of the Vice Chancellor for Research. SkyDeck combines the hands-on mentorship of traditional accelerators with the vast resources of its research university. This holistic partnership is coupled with SkyDeck’s unique accelerator program to create a powerful environment for startups. Participating startups have access to over 150 advisers, 30 industry partners, and a large network of accredited investors who connect SkyTeams to the expertise and capital they need to launch and grow their world-changing innovations. For more information, see [http://skydeck.berkeley.edu/](http://skydeck.berkeley.edu/).\n\nMedia Contact:\n\u003caddress\u003e\nErica Zeidenberg\u003cbr\u003e\nerica@hottomato.net\u003cbr\u003e\n925-631-0553 office\u003cbr\u003e\n925-518-8159 mobile\n\u003c/address\u003e","spans":[]}]}},{"id":"XGNKLhMAACMAUSyQ","uid":"sifive-to-host-50-risc-v-technology-symposia-throughout","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XGNKLhMAACMAUSyQ%22%29+%5D%5D","tags":[],"first_publication_date":"2019-02-12T22:38:35+0000","last_publication_date":"2022-08-08T20:57:09+0000","slugs":["sifive-to-host-50-risc-v-technology-symposia-throughout-the-world"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive to Host 50+ RISC-V Technology Symposia Throughout the World","spans":[]}],"publish_to":"Archive","publish_date":"2019-02-12","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Powerful and engaging events advance global knowledge about the RISC-V ISA and foster greater collaboration and opportunity within the open-source community*\n\n*Attendees will learn about the available design platforms, software and IP solutions that are democratizing access to custom silicon*\n\n**SAN MATEO, Calif. – Feb. 12, 2019 –**\n[SiFive](https://www.sifive.com), the leading provider of commercial RISC-V processor core IP, design platforms and silicon solutions, today announced it will host more than 50 [RISC-V Technology Symposia](https://sifivetechsymposium.com/) throughout the world in 2019. In partnership with co-hosts and many other key participants in the RISC-V ecosystem, these events will promote the open instruction set architecture and foster deeper collaboration and engagement within the global open-source community. These events are open to anyone interested in learning more and/or engaging in the RISC-V ecosystem, including electronics professionals, academicians and students, government bodies and electronics associations, as well as developers, implementers, and hobbyists.\n\nThe Technology Symposia are free to attend and will feature presentations by industry veterans, academic luminaries, and many others who have been instrumental in democratizing access to custom silicon through RISC-V based tools and platforms. Attendees will learn about customizable CPU cores, SoCs and IP blocks, and the SaaS-based approach that is enabling fast and easy access to them. There will be presentations and exhibits showcasing the myriad hardware and software tools for new and innovative RISC-V based solutions for IoT, AI, networking and storage applications.\n\n\"We believe the RISC-V ISA has spawned a revolution in the global semiconductor industry by democratizing access to custom silicon with robust design platforms and custom accelerators, thus paving the way for the next 50 years of computing design and innovation,\" said Naveed Sherwani, CEO, SiFive. \"These Technology Symposia underscore our commitment to the open instruction set architecture, and to ensuring that any and all stakeholders within the semiconductor design community have a platform for meaningful collaboration and exploration of available technologies and solution platforms.\"\n\nThe Technology Symposia will take place in over 50 cities throughout the United States, China, Pakistan, Europe, Asia, India, Bangladesh, Australia, the Middle East, Mexico and other South American countries. For more information, or to find the symposium closest to you, or to learn about sponsorship opportunities, please visit [www.sifivetechsymposium.com](https://sifivetechsymposium.com/).\n\n**About SiFive**\n\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [www.sifive.com](https://www.sifive.com).","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqs","uid":"sifive-named-startup-of-the-year","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqs%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:44:13+0000","slugs":["sifive-named-startup-of-the-year"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Named Startup of the Year","spans":[]}],"publish_to":"Archive","publish_date":"2016-12-13","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"![SiFive receiving ACE Startup of the Year Award](https://prismic-io.s3.amazonaws.com/sifive%2F80998444-0db3-4f03-b5de-f4dacda96976_sifive-ace-award-photo.jpg)\n\nSAN FRANCISCO – Dec. 13, 2016 – [SiFive](http://www.sifive.com/), the first fabless provider of customized, open-source-enabled semiconductors, has been named \"Startup of the Year\" at the UBM Annual Creativity in Electronics (ACE) Awards held in conjunction with the Embedded Systems Conference Silicon Valley in San Jose.\n\nThe ACE Awards, given in partnership with EE Times and EDN at an awards ceremony on Wednesday, Dec. 7, showcase the best of the best in today's electronics industry. The \"Startup of the Year\" category recognizes companies less than three years old with working prototypes or proof of concepts of innovative new electronics technologies. The award was judged by a panel comprising UBM editors and dignitaries from the electronics industry.\n\n\"This award caps a banner year for SiFive, one in which we not only brought to market the first ever commercial open-source RISC-V-based silicon but also sold out of our development kits in less than a week,\" said Krste Asanovic, co-founder and chief architect, SiFive. \"The momentum and excitement around RISC-V – and SiFive – was palpable during ESC, and we can't wait to see what's in store for 2017. We are proud to receive this recognition of the team's efforts, and humbled to join the ranks of the other innovative companies who have received this distinction in the past.\"\n\n\"The innovation and thought leadership introduced by this year's ACE Awards finalists and winners is true a testament to their hard work and dedication to their craft,\" said Nina Brown, VP Events, UBM Americas. \"We'd like to thank each of this year's participants for their incredible work in the electronics field and celebrate their accomplishments as they help to further the industry in new and exciting ways.\"\n\n## About the Embedded Systems Conference\n\nThe Embedded Systems Conference (ESC) is where the global design engineering community gathers to learn, collaborate, and celebrate innovation. Held in Silicon Valley, Boston, and Minneapolis, ESC empowers the design engineering community with hundreds of essential technical training classes and accreditation opportunities. For more information and to register for ESC, visit: [www.embeddedconf.com](http://www.embeddedconf.com/). ESC is organized by UBM Americas, a part of UBM plc, an Events First marketing and communication services business. For more information, visit ubmamericas.com.\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Krste Asanovic, Yunsup Lee and Andrew Waterman, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in San Francisco and has venture backing from Sutter Hill Ventures. For more information, visit [www.sifive.com](https://www.sifive.com/).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vre","uid":"sifive-joins-fdxcelerator-program-to-bring-risc-v-core-ip-to-globalfoundries-22fdx-process-technology","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vre%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:57:00+0000","slugs":["sifive-joins-fdxcelerator-program-to-bring-risc-v-core-ip-to-globalfoundries-22fdx-process-technology","sifive-joins-fdxcelerator-program-to-bring-risc-v-core-ip-to-globalfoundries-22fdxsupsup-process-technology"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Joins FDXcelerator™ Program to Bring RISC-V Core IP to GLOBALFOUNDRIES’ 22FDX® Process Technology","spans":[]}],"publish_to":"Archive","publish_date":"2017-11-28","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Nov. 28, 2017 – \u003c/span\u003e\nSiFive announced today that it has joined GLOBALFOUNDRIES’ FDXcelerator™\nPartner Program, and will be making RISC-V CPU IP including SiFive’s E31 and\nE51 RISC-V cores available on GF’s 22FDX® process technology. Based\non the open source RISC-V ISA, the SiFive E31 offers embedded chip designers\nnew capabilities in high performance within strict area and power requirements,\nand the SiFive E51 offers a full 64-bit performance at 32-bit price, power and\narea.\n\n“As the RISC-V ecosystem continues to grow, SiFive’s leading CPU IP is seeing\nincreased adoption. Our partnership with GF is going to enable an even larger\npool of system designers to build on an industry-leading process platform,”\nsaid Naveed Sherwani, CEO, SiFive. “SiFive has led the RISC-V ecosystem from\nearly on and we are excited to continue extending RISC-V into new market\nsegments.”\n\n“As members of the RISC-V Foundation, we are excited to see more RISC-V IP\nofferings made available on our processes,” said Gregg Bartlett, senior vice\npresident of CMOS business at GF. “SiFive’s wide range of cores makes them an\nideal partner for our FDXcelerator program.”\n\nGF's FDXcelerator Program brings together select partners to integrate their\nproducts or services into validated, plug-and-play design solutions, giving\ncustomers access to a broad set of quality offerings specific to 22FDX\ntechnology. The program's open framework enables members to minimize\ndevelopment time and cost while simultaneously leveraging the inherent power\nand performance advantages of FDX technology.\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the\nfree and open RISC-V instruction set architecture. Founded by RISC-V developers\nAndrew Waterman, Yunsup Lee and Krste Asanovic, SiFive democratizes access to\ncustom silicon by helping system designers reduce time-to-market and realize\ncost savings with customized RISC-V based semiconductors. SiFive is located in\nSilicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital\nand Osage University Partners. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrI","uid":"sifive-to-speak-at-linley-processor-conference","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrI%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:25:20+0000","slugs":["media-alert-sifive-to-speak-at-linley-processor-conference"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"MEDIA ALERT: SiFive to Speak at Linley Processor Conference","spans":[]}],"publish_to":"Archive","publish_date":"2018-04-09","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO – April 9, 2018\u003c/span\u003e\n\n**WHO**: SiFive, the leading provider of commercial RISC-V processor IP.\n\n**WHAT**: Jack Kang, vice president of product at SiFive, will present “RISC-V Core IP: From Microcontrollers to Linux” at the Linley Spring Processor Conference 2018. RISC-V has emerged as a compelling alternative to existing ISAs. Recent developments have seen RISC-V products announced for a wide variety of markets, ranging from microcontrollers all the way to vector computing for AI and machine learning. Kang will discuss what makes RISC-V so well suited for these diverse markets. He will also provide an update on current silicon RISC-V devices, market opportunities for RISC-V adoption, upcoming plans for RISC-V, and what this all means for system designers and architects.\n\nSiFive also will demo its latest development board, HiFive Unleashed, during the opening day reception starting at 4:40 p.m. PDT on April 11, 2018.\n\n**WHEN**: 1:30 to 3 p.m. PDT, Thursday, April 12, 2018\n\n**WHERE**: The Linley Spring Processor Conference 2018, April 11-12, 2018, at the Hyatt Regency Santa Clara, 5101 Great America Parkway, Santa Clara, Calif. 95054\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n 415-591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrQ","uid":"media-alert-sifive-to-exhibit-at-the-tsmc-2017-open-innovation-platform-ecosystem-forum-pavilion-sept-13","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrQ%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:17:06+0000","slugs":["media-alert-sifive-to-exhibit-at-the-tsmc-2017-open-innovation-platform-ecosystem-forum-pavilion-sept.-13"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"MEDIA ALERT: SiFive to Exhibit at the TSMC 2017 Open Innovation Platform Ecosystem Forum Pavilion Sept. 13","spans":[]}],"publish_to":"Archive","publish_date":"2017-09-12","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSANTA CLARA, Calif. – 9/12/2017\u003c/span\u003e\n\n**WHO**: SiFive, the first fabless provider of customized, open-source-enabled semiconductors founded by the inventors of the RISC-V instruction set architecture.\n\n**WHEN**: Wednesday, Sept. 13, 2017, during the TSMC 2017 Open Innovation Platform® (OIP) Ecosystem Forum. The Ecosystem Forum Pavilion will be open from 8 a.m. until 6 p.m.\n\n**WHERE**:\u003cbr\u003e\nBooth No. 215\u003cbr\u003e\nSanta Clara Convention Center\u003cbr\u003e\n5001 Great America Parkway\u003cbr\u003e\nHalls C and D\u003cbr\u003e\nSanta Clara, Calif. 95054\n\n**WHAT**: SiFive will showcase its RISC-V based Coreplex IP, the most widely deployed RISC-V cores in the world and the lowest risk, easiest path to RISC-V. SiFive Coreplex IP are fully synthesizable and verified soft IP implementations that scale across multiple design nodes, making them ideal for next-generation SoC designs.\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Yunsup Lee, Andrew Waterman and Krste Asanovic, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit [www.sifive.com](https://www.sifive.com).\n\nTo learn more about the [TSMC 2017 Open Innovation Platform Ecosystem Forum, please click here](http://www.hwacomms.com/TSMC2017/OIP/vna/Attendee/index.html).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrm","uid":"sifive-joins-tsmc-ip-alliance-program","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrm%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:24:58+0000","slugs":["sifive-joins-tsmc-ip-alliance-program"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Joins TSMC IP Alliance Program","spans":[]}],"publish_to":"Archive","publish_date":"2017-09-26","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Sept. 26, 2017 –\u003c/span\u003e\n[SiFive](https://www.sifive.com), the first fabless provider of customized,\nopen-source-enabled semiconductors, today announced it has joined the TSMC\n(NYSE: TSM) IP Alliance Program, part of the TSMC Open Innovation Platform®,\nwhich accelerates innovation in the semiconductor design community. As an\nalliance member, SiFive’s RISC-V based Coreplex IP are made available to its\ncustomers to reduce time-to-market, increase return on investment and reduce\nwaste in the manufacturing process.\n\nWith the significant increases in non-recurring engineering and design costs\nrequired to bring to life new silicon designs, TSMC’s IP Alliance Program\nmakes it easier for fabless chipmakers to innovate and produce custom\nsemiconductors. By participating in the TSMC IP Alliance Program, SiFive\nbecomes the first RISC-V solution provider to make its IP readily available\nfor fabless chipmakers leveraging the industry’s most comprehensive\nsemiconductor IP portfolio.\n\n“Acceptance into the TSMC IP Alliance is an honor and a significant validation\nnot only of SiFive, but of the RISC-V architecture as a whole,” said Jack\nKang, vice president of Product and Business Development, SiFive. “Having the\nSiFive Coreplex IP platform available through the program makes designing a\nchip based on the latest in open source hardware even easier. We look forward\nto continued collaboration with TSMC and the other members of the IP Alliance\necosystem.”\n\n“The TSMC Open Innovation Platform forms the center of our open innovation\nmodel that addresses the needs of our customers looking to reduce design time\nand speed time-to-market,” said Suk Lee, TSMC senior director, Design\nInfrastructure Marketing Division. “The addition of SiFive’s IP to the TSMC IP\ncatalog will streamline the process of fabricating custom silicon designs\nbased on the RISC-V implementation.”\n\nSiFive was founded by the inventors of RISC-V – Andrew Waterman, Yunsup Lee\nand Krste Asanovic – with a mission to democratize access to custom silicon.\nIn its first six months of availability, more than 1,000 HiFive1 software\ndevelopment boards have been purchased and delivered to developers in over 40\ncountries. Additionally, the company has engaged with multiple customers\nacross its IP and SoC products, started shipping the industry’s first RISC-V\nSoC in November 2016 and announced the availability of its Coreplex RISC-V\nbased IP earlier this year. SiFive’s innovative “study, evaluate, buy”\nlicensing model dramatically simplifies the IP licensing process, and removes\ntraditional road blocks that have limited access to customized, leading edge\nsilicon.\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the\nfree and open RISC-V instruction set architecture. Founded by RISC-V inventors\nYunsup Lee, Andrew Waterman and Krste Asanovic, SiFive democratizes access to\ncustom silicon by helping system designers reduce time-to market and realize\ncost savings with customized RISC-V based semiconductors. SiFive is located in\nSilicon Valley and has venture backing from Sutter Hill Ventures, Spark\nCapital and Osage University Partners. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrU","uid":"sifive-launches-industrys-first-open-source-risc-v-soc","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrU%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:12:31+0000","slugs":["sifive-launches-industrys-first-open-source-risc-v-soc"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Launches Industry's First Open-Source RISC-V SoC","spans":[]}],"publish_to":"Archive","publish_date":"2016-11-29","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN FRANCISCO – Nov. 29, 2016\u003c/span\u003e – [SiFive](http://www.sifive.com/), the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of its Freedom Everywhere 310 (FE310) system on a chip (SoC), the industry’s first commercially available SoC based on the free and open RISC-V instruction set architecture, along with the corresponding low-cost HiFive1 software development board. As part of this availability, SiFive also has contributed the register-transfer level (RTL) code for FE310 to the open-source community, which the company revealed today at the 5th RISC-V Workshop in Mountain View, Calif.\n\n“We started with this revolutionary concept — that instruction sets should be free and open – and were amazed by the incredible rippling effect this has had on the semiconductor industry because it provided a viable alternative to what was previously closed and proprietary,” said Krste Asanovic, co-founder and chief architect, SiFive. “In the few short months since we’ve announced the Freedom Platforms, we’ve seen a tremendous response to our vision of customizable SoCs. The FE310 is a major step forward in the movement toward open-source and mass customization, and SiFive is excited to bring the opportunity for innovation back into the hands of system architects.”\n\nThe FE310 is the first member of the Freedom Everywhere family of customizable SoCs designed for microcontroller, embedded, IoT and wearable applications. By contributing the FE310 RTL code to the open-source community, SiFive aims to encourage open-source development of both software support for RISC-V as well as other open hardware development. The RTL code also empowers chip designers with the ability to customize their own SoC on top of the base FE310. For system architects, developers or companies without chip design capabilities, SiFive’s “chips-as-a-service” offering can customize the FE310 to meet their unique needs.\n\n“SiFive has achieved a significant milestone for the RISC-V ecosystem,” said Rick O’Connor, executive director of the non-profit RISC-V Foundation. “We are thrilled to see the first commercial silicon based on RISC-V standards come to market and look forward to continued technology leadership from the SiFive team.”\n\nThe FE310 features SiFive’s E31 CPU Coreplex, a 32-bit RV32IMAC core running at 320+ MHz. Additional features include a 16KB L1 Instruction Cache, a 16KB Data SRAM scratchpad, hardware multiply/divide, debug module, one-time programmable non-volatile memory (OTP), flexible clock generation with on-chip oscillators and PLLs, and a wide variety of peripherals including UARTs, QSPI, PWMs and timers. Multiple power domains and a low-power standby mode ensure a variety of applications can benefit from the FE310, which was fabricated in TSMC 180nm.\n\nThe HiFive1 is an Arduino-Compatible development board featuring the FE310.\n\n## Availability\n\nThe HiFive1 can be ordered via Crowd Supply at \u003chttps://www.crowdsupply.com/sifive/hifive1\u003e. The RTL code for FE310 can be accessed at \u003chttps://github.com/sifive/freedom\u003e.\n\nSiFive is showcasing the HiFive1 at the [5th RISC-V Workshop](https://riscv.org/2016/10/5th-risc-v-workshop-agenda/), in Mountain View Nov. 29-30. The company also will have HiFive1 demos at Booth No. 1522 at [ESC Silicon Valley](http://www.escsiliconvalley.com/) in San Jose from Dec. 6-8.\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Krste Asanovic, Yunsup Lee and Andrew Waterman, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in San Francisco and has venture backing from Sutter Hill Ventures. For more information, visit [www.sifive.com](https://www.sifive.com/).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqa","uid":"sifive-and-ultrasoc-partner-to-accelerate-risc-v-development-through-designshare","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqa%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:12:13+0000","slugs":["sifive-and-ultrasoc-partner-to-accelerate-risc-v-development-through-designshare"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive and UltraSoC partner to accelerate RISC-V development through DesignShare","spans":[]}],"publish_to":"Archive","publish_date":"2017-09-07","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Sept. 7, 2017\u003c/span\u003e – [SiFive](https://www.sifive.com/), the first fabless provider of customized, open-source-enabled semiconductors, today announced that UltraSoC will provide debug and trace technology for the SiFive Freedom platform, based on the RISC-V open source processor specification as part of the DesignShare initiative. UltraSoC’s embedded analytics IP will be available through the recently announced SiFive DesignShare ecosystem that gives any company, inventor or maker the ability to harness the power of custom silicon. UltraSoC’s debug and trace functionality will enable users of the Freedom platform to access a wide variety of tools and interfaces to use in their developments.\n\nThe DesignShare concept enables an entirely new range of applications. Companies like SiFive, UltraSoC and other ecosystem partners have developed efficient, pre-integrated solutions to lower the upfront engineering costs required to bring a custom chip design based on the SiFive Freedom platform to realization. The partnership between SiFive, originator of the industry’s first open-source chip platform, and UltraSoC, the industry leader in vendor-neutral on-chip debug and analytics tools, significantly strengthens the ecosystem surrounding RISC-V, the open source processor specification which is often dubbed “the Linux of the semiconductor industry.”\n\n“SiFive was founded with the mission to disrupt the semiconductor industry by leveling the playing field for anyone who wants to develop custom silicon,” said Naveed Sherwani, CEO of SiFive. “The DesignShare ecosystem enables aspiring system designers with the tools they need when designing their SoC. We’re thrilled to welcome UltraSoC to the DesignShare ecosystem and look forward to seeing the innovations our collaboration brings to the market.” \n\nUltraSoC’s IP simplifies the development of systems on chip (SoCs) and provides embedded analytics features that enable chip makers to cut development costs significantly and increase the profitability of their projects. The company has taken a leading role in producing a specification for RISC-V processor trace functionality, which UltraSoC and SiFive intend to work together with the RISC-V Foundation to incorporate fully into the RISC-V standard. Trace is a fundamental requirement for developers working with any processor architecture, allowing engineers to view the behavior of their programs in detail, isolating bugs and identifying areas for improvement. UltraSoC and SiFive IP fully supports this recently released trace specification. \n\n“UltraSoC is committed to increasing the number of silicon design starts, and our participation in DesignShare with SiFive is a natural extension of that work,” said Rupert Baines, CEO of UltraSoC. “We are committed to driving the acceleration of the democratization of the semiconductor industry, both through our membership in the RISC-V Foundation and via individual partnerships like this one with SiFive. Making UltraSoC’s IP available through the DesignShare model will enable chipmakers everywhere to leverage the benefits of open source hardware and introduces new innovative designs to the market.” \n\nRick O’Connor, executive director of the RISC-V Foundation, commented: “The idea behind the open source movement is that one doesn’t have to design everything from scratch. The idea behind DesignShare is to help speed the development of new silicon designs by reducing the barriers of cost, process and integration that have traditionally held back innovation in the semiconductor industry. SiFive, UltraSoC and the other companies that are making their IP available through DesignShare are fundamentally enabling this revolution in an otherwise stagnant industry.”\n\nSiFive was founded by the inventors of RISC-V – Andrew Waterman, Yunsup Lee and Krste Asanovic – with a mission to democratize access to custom silicon. In its first six months of availability, more than 1,000 HiFive1 software development boards have been purchased and delivered to developers in over 40 countries. Additionally, the company has engaged with multiple customers across its IP and SoC products, started shipping the industry’s first RISC-V SoC in November 2016 and announced the availability of its Coreplex RISC-V based IP earlier this month. SiFive’s innovative “study, evaluate, buy” licensing model dramatically simplifies the IP licensing process, and removes traditional road blocks that have limited access to customized, leading edge silicon.\n\nUltraSoC allows designers to create an on-chip infrastructure that non-intrusively monitors a chip’s behavior – both hardware and software. In development, engineers can use this IP to gain an intimate understanding of the interactions between on-chip processor blocks, custom logic, and system software. The company joined the RISC-V Foundation in 2016, with a mission to provide the RISC-V community with secure, independent on-chip development and debug capabilities; earlier in 2017 it offered its RISC-V processor trace specification for adoption by the RISC-V Foundation as part of the open source specification.\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Yunsup Lee, Andrew Waterman and Krste Asanovic, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit [www.sifive.com](https://www.sifive.com). \n \n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqo","uid":"sifive-named-as-finalist-for-two-ace-awards","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqo%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:16:57+0000","slugs":["sifive-named-as-finalist-for-two-ace-awards"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Named as Finalist for Two ACE Awards","spans":[]}],"publish_to":"Archive","publish_date":"2017-11-08","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Nov. 8, 2017 – \u003c/span\u003e\n[SiFive](https://www.sifive.com/),\nthe first fabless provider of customized, open-source-enabled semiconductors,\nhas once again made the shortlist for two UBM Annual Creativity in Electronics\n(ACE) Awards. Honored this year were the developers of the HiFive1 for \"Design\nTeam of the Year,\" and Jack Kang, SiFive vice president of product and business\ndevelopment as one of the finalists for \"Executive of the Year.\"\n\nThe ACE Awards, which will be given in partnership with EE Times and EDN at an\nawards ceremony on Wednesday, Dec. 6, showcase the best of the best in today’s\nelectronics industry. The \"Design Team of the Year\" category honors teams with\ncreative, efficient and inspiring capabilities that contributed to the\nadvancement of technology. The \"Executive of the Year\" category recognizes\nleaders who have a significant impact in the electronics market and demonstrate\noutstanding growth in business. The awards are judged by a panel comprising UBM\neditors and dignitaries from the electronics industry. \n\nThe HiFive1 dramatically redefined the process by which companies, system\narchitects, makers and dreamers can get their hands on custom silicon. HiFive1\nand the open-source FE310 SoC that it features share a completely new approach\nto the traditional process of designing and producing silicon. The HiFive1\ndevelopment team was led by engineer Megan Wachs and includes Albert Ou, Han\nChen, Henry Cook, Henry Styles, Jacob Chang, Richard Xia and Wesley Terpstra,\nas well as SiFive co-founders Andrew Waterman, Yunsup Lee and Krste Asanovic.\n\n\"To make the shortlist against such competition shows our continued dedication\nto progress in the semiconductor industry,\" said Naveed Sherwani, CEO, SiFive.\n\"We are honored to be nominated for two consecutive years and are excited to\ncontinue our mission to democratize access to custom silicon.\"\n\nSiFive was recognized as \"Startup of the Year\" by the UBM ACE Awards in 2016.\nSince then, the company has developed and launched several new initiatives\nincluding its RISC-V Core IP and spearheading the DesignShare economy that\nenables any company, inventor or maker the ability to harness the power of\ncustom silicon.\n\nThe ACE Awards event will take place at the San Jose Convention Center in\nconjunction with Embedded Systems Conference (ESC) Silicon Valley. \n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the\nfree and open RISC-V instruction set architecture. Founded by RISC-V inventors\nYunsup Lee, Andrew Waterman and Krste Asanovic, SiFive democratizes access to\ncustom silicon by helping system designers reduce time-to-market and realize\ncost savings with customized RISC-V based semiconductors. SiFive is located in\nSilicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital\nand Osage University Partners. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vra","uid":"sifive-to-host-risc-v-hackathon-at-embedded-linux-conference","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vra%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:18:28+0000","slugs":["media-alert-sifive-to-host-risc-v-hackathon-at-embedded-linux-conference"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"MEDIA ALERT: SiFive to Host RISC-V Hackathon at Embedded Linux Conference","spans":[]}],"publish_to":"Archive","publish_date":"2018-02-26","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Feb. 26, 2018\u003c/span\u003e\n\n**WHO:** SiFive, the leading provider of commercial RISC-V processor IP.\n\n**WHAT:** SiFive will hold its first hackathon at the [Embedded Linux Conference](https://events.linuxfoundation.org/events/elc-openiot-north-america-2018/features-and-add-ons/co-located-events/), providing an opportunity for developers to test SiFive’s HiFive Unleashed board featuring the Freedom U540 SoC, the industry’s first RISC-V based, 64-bit quadcore processor running Linux.\n\nEach developer or team at the hackathon will be provided with a HiFive Unleashed and a HiFive1 board (based on the Freedom E310 SoC) along with a designated challenge for each board. The winners of each challenge will be among the very first to take home their own HiFive Unleashed board and a cash prize of $1,000.\n\nThe HiFive Unleashed board was announced in October 2017, with the first real-world Linux demo at FOSDEM in February. Developers can purchase the HiFive Unleashed board [online](https://www.sifive.com/products/hifive-unleashed/). The board will ship in late March for early access users; more boards will ship in late June.\n\nThe hackathon is free for conference attendees. To register for the hackathon, visit [https://www.regonline.com/ELCIOTNA18](https://www.regonline.com/ELCIOTNA18).\n\n**WHEN:** 10:30 a.m. Monday, March 12, 2018 through 1 p.m. Wednesday, March 14, 2018\n\n**WHERE:** The Embedded Linux Conference at the Hilton Portland in Portland, Ore.\n\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Jamie Feller\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8432\u003cbr\u003e\n sifive@shiftcomm.com\u003cbr\u003e\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vru","uid":"sifive-appoints-cfo-to-executive-team","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vru%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:34:13+0000","slugs":["sifive-appoints-cfo-to-executive-team"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Appoints CFO to Executive Team","spans":[]}],"publish_to":"Archive","publish_date":"2018-02-14","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Feb. 14, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com/),\nthe leading provider of commercial RISC-V processor IP, continues to grow its\nexecutive staff with the appointment of Shiva Natarajan as chief financial\nofficer. Natarajan joins SiFive with more than two decades of financial\nmanagement, accounting and strategic planning experience in both public and\nprivate technology companies.\n\nAs CFO, Natarajan will help to structure the company’s financial systems and\noversee SiFive’s continued growth as it rolls out its innovative business\nmodel.\n\n“I am excited to join one of the most unique teams in the world that is\ndisrupting the semiconductor market using RISC-V technology,” said Natarajan.\n“I look forward to applying my experience to help guide the company through its\ncontinued, explosive growth.”\n\nSince its founding in 2015, SiFive has grown exponentially with the RISC-V\necosystem, and the company is projecting to double its employee count in 2018\nto support the increased demand for its market-leading RISC-V product\nofferings. The expansion includes the recent appointments of Sunil Shenoy as\nvice president of hardware engineering and Shafy Eltoukhy as vice president of\noperations.\n\n“SiFive is at a crucial point in its development, and Shiva’s experience in\nnavigating the growth path of expanding companies will help guide the next\nphase of SiFive’s growth,” said Naveed Sherwani, SiFive CEO. “Shiva will\nprovide us with the financial vision, strategy and leadership to advance SiFive\nto the next level.”\n\n\nBefore joining SiFive, Natarajan was vice president of finance at A10 Networks.\nEarlier in his career, Natarajan served as vice president, corporate\ncontroller, chief accounting officer and interim CFO during his eight years at\nApplied Micro Circuits Corporation.\n\nNatarajan began his career in public accounting and worked for PwC and Ernst \u0026\nYoung. He is a certified public accountant and holds a bachelor’s degree in\nscience from the University of Calcutta.\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit \n[www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Jamie Feller\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8432\u003cbr\u003e\n sifive@shiftcomm.com\u003cbr\u003e\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrM","uid":"mobiveil-inc-and-sifive-inc-partner-to-develop-risc-v-based-configurable-ssd-platform-for-data-center-and-enterprise-storage-applications","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrM%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:12:22+0000","slugs":["mobiveil-inc.-and-sifive-partner-to-develop-risc-v-based-configurable-ssd-platform-for-data-center-and-enterprise-storage-applications"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Mobiveil Inc. and SiFive partner to develop RISC-V based configurable SSD Platform For Data Center and Enterprise storage Applications","spans":[]}],"publish_to":"Archive","publish_date":"2018-08-07","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eMilpitas, Calif. – August 7, 2018 – \u003c/span\u003e\nMobiveil, Inc. a provider of Serial Interconnect IP blocks and platforms targeting Flash Storage, IoT and Communication markets, has selected SiFive’s multicore E51 and U54 Core IPs to power Mobiveil’s new advanced configurable Gen4 PCIe-NVMe SSD platform offering a high performance and low power SSD solution for data center storage applications. SiFive’s heterogenous, coherent RISC-V core complex in a high-performance FPGA along with Mobiveil's Silicon Proven IP blocks (Gen4 PCIe, NVMe , LDPC, ONFI and Memory controller IP), provides data center customers a platform to develop their unique applications on RISC-V processors. \n\n“RISC-V is the ideal processor for data center storage applications,” said Shafy Eltoukhy, SVP of Operations at SiFive Inc. “The cores’ highly efficient microarchitecture and configurability provide the optimal performance needed to execute the latest storage programs data centers are employing to accelerate access to the exploding amounts of information being compiled today. Working together with Mobiveil to make this RISC-V based SSD platform enables customers to accelerate their RISC-V based product development efforts.”\n\n“We chose to partner with SiFive on this SSD platform solution as their cores offer the lowest area and highest power efficiency of any similar cores in the market,” said Ravi Thummarukudy, Mobiveil CEO. “Mobiveil’s advanced FPGA-based board enables reliable and robust system solutions that can be easily tailored by enterprise and data center designers. Having a RISC-V CPU in an FPGA, designers can optimize their solution to target latest flash devices from multiple suppliers. Furthermore, the FPGA-based board solution enables enterprise and data center designers the flexibility to re-architect how storage is deployed in their high-performance cloud.”\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom, Western Digital and Intel Capital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## About Mobiveil\n\nMobiveil is a fast‐growing technology company that specializes in the development of Silicon Intellectual Property (SIP), platforms and solutions for the storage, IoT and networking markets. It leverages decades of experience in delivering high‐quality, production‐proven, high-speed serial interconnect SIP cores, and custom and standard form factor hardware boards to leading semiconductor companies worldwide. For the PCI Express-based Flash Storage market, Mobiveil developed an FPGA based NVMe SSD platform (NVMStor-Ultra™) comprised of GPEX™, Gen4 PCI Express Controller, NVM Express Controller (UNEX™), Universal Memory Controller (UMMC™), Low Density Parity Check (LDPC) Encoder/Decoder and Flash Memory Controller(ONFI/Toggle). Mobiveil is headquartered in Milpitas, Calif., with engineering development centers located in Bangalore, Chennai and Hyderabad, India, and sales offices and representatives located in U.S., Europe, Israel, Japan, Taiwan and China.\n\nEngage with Mobiveil at:\u003cbr\u003e\nWebsite: [www.mobiveil.com](http://www.mobiveil.com)\u003cbr\u003e\nEmail: [info@mobiveil.com](mailto:info@mobiveil.com)\u003cbr\u003e\nTwitter: @Mobiveil\u003cbr\u003e\nLinkedIn: [https://www.linkedin.com/company-beta/2725746/](https://www.linkedin.com/company-beta/2725746/)\u003cbr\u003e\nFacebook: [https://www.facebook.com/Mobiveil](https://www.facebook.com/Mobiveil)\u003cbr\u003e\nMarketing contact Jonah Mcleod. [jonah@mobiveil.com](mailto:jonah@mobiveil.com)\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrg","uid":"custom-silicon-veteran-joins-sifive-executive-team","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrg%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:18:13+0000","slugs":["custom-silicon-veteran-joins-sifive-executive-team"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Custom Silicon Veteran Joins SiFive Executive Team","spans":[]}],"publish_to":"Archive","publish_date":"2018-01-30","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Jan. 30, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com/),\nthe leading provider of commercial RISC-V processor IP, today announced Shafy Eltoukhy as vice president of operations. Eltoukhy, a veteran of Microsemi and Intel, will lead SiFive’s DesignShare activities and ensure the smooth rollout of new Core IP, SoCs and services.\n\nOver the course of his career, Eltoukhy has been awarded 24 patents, and is the author of more than 20 technical articles. He brings this expertise to SiFive with a goal to help the company expand its DesignShare program, which gives any SoC designer, inventor or maker the ability to harness the power of custom silicon with little to no upfront risk. Since its inception, companies including Analog Bits, eMemory, FlexLogix, Rambus, Think Silicon and UltraSoC have joined the DesignShare ecosystem. He will also help to coordinate SiFive’s fast-growing hardware and software engineering teams with key partners as the company launches new products and services.\n\n“SiFive’s mission - to lower the barriers for innovation in the silicon industry - immediately resonated with me when presented with the opportunity to work with the team,” Eltoukhy said. “Knowing firsthand the challenges involved in bringing a new SoC to market, I immediately recognized SiFive’s ability to resolve the issues that customers and designers have faced for decades. I am thrilled to join the SiFive team and am honored to have the opportunity to help revolutionize the semiconductor industry.”\n\nEltoukhy brings three decades of experience to his role at SiFive, having most recently served as vice president and business unit manager for the analog mixed signal division at Microsemi. Earlier in his career, Eltoukhy was vice president of operations and technology at Open-Silicon, where he released to production over 150 ASIC and complex SoC products. He also served as Vice President of Technology at Lightspeed Semiconductor, where he joined the founding team that invented structured ASIC technology with a goal to simplify ASIC design cycle and reduce development cost. As Director of Technology Development at Actel Corporation (now Microsemi), he participated in the early development of the first and second generation of Antifuse FPGA products. He has also held senior engineering positions at semiconductor pioneers Intel and Fairchild. Eltoukhy holds a doctorate in electrical engineering from the University of Waterloo as well as master’s and bachelor’s degrees from Cairo University.\n\n“We are thrilled to have someone with Shafy’s credentials join the SiFive executive team,” said Naveed Sherwani, CEO of SiFive. “His experience as a founder and leader of numerous startups is invaluable to SiFive as we strive to breathe new life into a stagnant industry. His perspective will benefit not only to SiFive but the semiconductor market writ large as we work to simplify the design process.”\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information,\nvisit [www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n lclavin@shiftcomm.com \n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrG","uid":"segger-adds-support-for-sifives-coreplex-ip-to-its-industry-leading-j-link-debug-probe","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrG%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-04T19:18:20+0000","slugs":["segger-adds-support-for-sifives-coreplex-ip-to-its-industry-leading-j-link-debug-probe"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SEGGER Adds Support for SiFive's Coreplex IP to Its Industry Leading J-Link Debug Probe","spans":[]}],"publish_to":"Archive","publish_date":"2017-09-19","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eHILDEN, Germany, and SAN MATEO, Calif. – Sept. 19,\n2017 – \u003c/span\u003e [SEGGER Microcontroller](https://www.segger.com/downloads/jlink), a\nleading supplier of software, hardware and development tools for embedded\nsystems, and [SiFive](https://www.sifive.com), the first fabless provider of\ncustomized, open-source-enabled semiconductors, today announced the\navailability of SEGGER J-Link support for SiFive Coreplex IP, based on the\nRISC-V architecture. The growing interest in Coreplex IP is increasingly\nprompting vendors like SEGGER to make its industry leading tools available as\npart of the RISC-V ecosystem.\n\nRISC-V was born from the dire need to address the skyrocketing cost of\ndesigning and manufacturing increasingly complex new chip architectures, a\nresult of the economic demise of Moore’s Law. SiFive was founded by the\ninventors of RISC-V – Yunsup Lee, Andrew Waterman and Krste Asanovic – with a\nmission to democratize access to custom silicon. In its first six months of\navailability, its HiFive1 software development boards have been delivered to\nthousands of developers in over 40 countries, making SiFive Coreplex IP the de\nfacto leader for RISC-V cores, with more public customers, working silicon and\ndevelopment boards than any other RISC-V vendor.\n\n“In order to bring RISC-V and custom silicon to its full potential, the\necosystem needs a full complement of established commercial tools with which to\nvalidate designs,” said Jack Kang, vice president of product and business\ndevelopment at SiFive. “Support from SEGGER’s industry-leading J-Link debug\nprobe family is a huge step for embedded developers who wish to debug software\nand production program chips using RISC-V cores. We look forward to our\ncontinued partnership with SEGGER and are excited to see how this development\nimpacts the entire RISC-V community.”\n\nAll current J-Link models now support debugging of RV32 RISC-V cores. This\nincludes support from SEGGER's GDB Server, which is part of the J-Link\nsoftware package that supports SiFive’s free Eclipse-based Freedom Studio.\nJ-Link’s high performance and functionality allows it to be easily used and it\nprovides reliable, professional support to RISC-V cores. Features also include\na direct Flash memory download via an open flash loader interface giving SiFive\nand the RISC-V ecosystem access to SEGGER’s vast catalog of supported flash\ndevices. For systems running code from flash memory instead of RAM, there is an\nunlimited number of breakpoints not only in RAM, but also in Flash (with higher\nend J-Link PLUS, J-Link Ultra + and J-Link PRO models).\n\n\"RISC-V is a great CPU architecture. With various open-source and commercial\nimplementations, we believe that it will become very popular, very fast,” said\nAlex Grüner, J-Link product manager and CTO of SEGGER. “J-Link’s family of\nprofessional debug probes are now available to help contribute to and build on\nthe success of RISC-V.\"\n\nSaid Rick O’Connor, chairman of the RISC-V Foundation: “The fact that SEGGER is\nseeing commercial demand for RISC-V is evidence that open-source semiconductors\nare enabling a new wave of silicon design. SiFive and others implementing\nRISC-V cores based on SiFive’s Coreplex IP will now have the necessary tools to\nsimplify their development workflow.”\n\nThe low-cost version J-Link EDU allows students and hobbyists to use\nprofessional debug technology with RISC-V. Using J-Link with RISC-V is easy –\ndownload examples [here](https://wiki.segger.com/SiFive_Arty_FPGA_Dev_Kit).\n\nMore information about J-Link can be found\n[here](https://www.segger.com/products/debug-probes/j-link/).\n\nFor more information on the SiFive’s Coreplex IP, click [here](https://www.sifive.com/products/coreplex-risc-v-ip/).\n\n## About J-Link/J-Trace\n\nThe SEGGER J-Link / J-Trace is the most popular debug probe family on the\nmarket. It is tool chain independent and works with free GDB-based tool chains\nas well as commercial IDEs. J-Trace PRO works with all currently available\nCortex-M devices up to a 300MHz maximum trace clock. It supports tracing on\nCortexM0/M0+/M1/M3/M4/M7 targets. J-Trace PRO also provides all the features of\nJ-Link technology for Cortex-M, such as unlimited flash breakpoints and Monitor\nMode Debugging. With the J-Link family, investments in the debug probe are\npreserved when changing compiler or even CPU architecture. J-Link supports\nmultiple CPU families; there is no need to buy a new J-Link or new license when\nswitching to a different yet supported CPU family or toolchain. All J-Links\nare fully compatible to each other, so an upgrade from a lower-end model to a\nhigher-end model is a matter of a simple plug-and-play. Full product\nspecifications are available at:\n[https://www.segger.com/products/debug-probes/j-link/](https://www.segger.com/products/debug-probes/j-link/)\nThe J-Link - Software is available at:\n[https://www.segger.com/downloads/jlink](https://www.segger.com/downloads/jlink)\n\n## About Segger\n\nSEGGER Microcontroller is a full-range supplier of software, hardware and development tools for\nembedded systems. The company offers support throughout the whole development process with\naffordable, high quality, flexible and easy-to-use tools and components. SEGGER offers solutions for\nsecure communication as well as data and product security, meeting the needs of the rapidly evolving\nIoT. SEGGER was founded in 1997, is privately held, and is growing steadily. Headquartered in Germany\nwith a US office in the Boston area and distributors in all continents, SEGGER offers its full product range\nworldwide. For additional information, visit: [https://www.segger.com](https://www.segger.com)\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the\nfree and open RISC-V instruction set architecture. Founded by RISC-V inventors\nAndrew Waterman, Yunsup Lee and Krste Asanovic, SiFive democratizes access to\ncustom silicon by helping system designers reduce time-to-market and realize\ncost savings with customized RISC-V based semiconductors. SiFive is located in\nSilicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital\nand Osage University Partners. For more information, visit [www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Harald Shober\u003cbr\u003e\n SEGGER\u003cbr\u003e\n +49 2103-2878-181\u003cbr\u003e\n Harald.Schober@segger.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n +1 (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"XPlo8BEAACEAQAsN","uid":"sifive-celebrates-historic-100-design-win-milestone","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XPlo8BEAACEAQAsN%22%29+%5D%5D","tags":[],"first_publication_date":"2019-06-06T19:49:54+0000","last_publication_date":"2022-08-08T20:59:06+0000","slugs":["sifive-celebrates-historic-100-design-win-milestone"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Celebrates Historic 100 Design Win Milestone","spans":[]}],"publish_to":"Archive","publish_date":"2019-06-06","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Compelling Portfolio and Strategic Partnerships Propel RISC-V Leader into Hypergrowth*\n\n## SAN MATEO, Calif. - June 6, 2019 - \n[SiFive](https://c212.net/c/link/?t=0\u0026amp;l=en\u0026amp;o=2489547-1\u0026amp;h=694590873\u0026amp;u=https%3A%2F%2Fwww.sifive.com%2F\u0026amp;a=SiFive), Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, announced today that it has secured its 101st design win. SiFive has gained significant traction in embedded markets as device manufacturers rapidly adopt domain-specific application processor designs to enable powerful, secure, efficient computing in Edge devices. As a trillion smart, connected devices are forecasted to come online by 2025, SiFive\u0026#39;s proven capabilities for high-performance embedded solutions are crucial for success in this new era of Edge IoT. The scalable capabilities of RISC-V and SiFive\u0026#39;s excellence in innovation, design and engineering have enabled leading semiconductor companies to move through the selection, customization and enhancement phases of design in just two months.\r\n\r\n## **RISC-V Ecosystem**\r\n\r\nThe growth experienced by SiFive, a founding platinum member of the RISC-V Foundation, is driven by the mainstream adoption of RISC-V, a free, open and mature ISA that is suitable for all levels of compute from microcontrollers to hyperscale computing. The RISC-V Foundation has grown to 235 members, including Alibaba, Cadence Design Systems, Google, Microchip, Micron, NVIDIA, Tesla, TSMC, Samsung and Western Digital. The RISC-V Foundation is chartered to standardize and promote RISC-V together with its hardware and software ecosystem.\r\n\r\nSiFive is uniquely positioned to take advantage of the need for custom silicon designs, as traditional business models with legacy architectures force customers to have an architecture prescribed to them after selecting a vendor. RISC-V allows customers to select a core closely matched to their needs and then proceed to select a vendor based on differentiating expertise and capabilities. This is where SiFive\u0026#39;s expertise, RISC-V Core IP portfolio with in-house SoC and PHY IPs, industry partnerships and unique DesignShare IP portfolio provide the perfect mix of purpose-driven design and proven technology.\r\n\r\n## **SiFive Core IP Product Portfolio**\r\n\r\nSiFive\u0026#39;s RISC-V Core IP portfolio of 7, 5, 3 and 2-series cores scale RISC-V designs at every performance level, from the 8-stage, dual-issue superscalar pipeline processor cores down to power and area optimized 2-stage, single-issue pipeline cores. 32-bit embedded cores for microcontrollers, Edge computing and IoT devices are complemented by 64-bit embedded cores for storage, augmented reality (AR), virtual reality (VR) and machine learning. The performance oriented 7- and 5-series cores also available in 64-bit application processor variants for use in datacenters, network baseband or similar Linux-based applications.\r\n\r\nThe SiFive 2 series has seen the fastest uptake of feature upgrades by customers, as they take advantage of the regularly scheduled enhancements to Core IP, features and tools. Critically, the 64-bit S2 enables SoCs to have an always-on, low-power CPU that can be combined with high-performance CPUs that switch on only when applications demand performance, such as in voice-activated smart devices.\r\n\r\nSiFive delivers its configurable Core IP via its industry-first online core configurator, SiFive Core Designer. By adopting a native cloud licensing model for Core IP evaluation, customization and RTL delivery, customers gain several advantages. Unlike legacy architectures, which depreciate over time and are replaced on developmental roadmaps, SiFive\u0026#39;s Core IP is continually maintained and improved. The 7 series core has increased performance from 4.9 to 5.1 in the important industry benchmark CoreMark®, due to ongoing performance optimizations since its launch.\r\n\r\n## **SiFive Product Templates**\r\n\r\nSiFive launched the industry\u0026#39;s first SoC Templates, Freedom Aware, in partnership with QuickLogic. These templates are optimized for ultra-low power solutions in consumer and industrial IoT applications. By taking advantage of SiFive Freedom Aware SoC Templates, silicon designers can reduce the design cycle to just a few months, decrease the total cost to first silicon by an order of magnitude and, most importantly, provide custom silicon solutions while removing the dependency on large semiconductor design teams.\r\n\r\n\u0026quot;Through our strategic partnership, we are working very closely with SiFive to combine the success of its RISC-V Core IP and demonstrated quick-turn design capabilities with QuickLogic\u0026#39;s signature ultra-low-power SoC design expertise, AI subsystems and end-to-end AI development tools to introduce the world\u0026#39;s first SoC Templates,\u0026quot; said Brian Faith, president and CEO of QuickLogic. \u0026quot;The Freedom Aware SoC Template family will enable OEMs to address the rapidly emerging markets for consumer and industrial end-point applications with unique and high-value solutions. Our shared vision to democratize SoC design by significantly lowering the cost and development time has been validated by the response to the April 2019 introduction of the Freedom Aware SoC Template family and interest in our Early Adopter program.\u0026quot;\r\n\r\n## **SiFive Custom SoC Business Unit**\r\n\r\nSiFive\u0026#39;s Custom SoC (CSOC) division creates fully custom SoCs from specification to final production silicon, leveraging SiFive\u0026#39;s core IP portfolio with in house SoC and PHY IPs, DesignShare IP, customer IP and SiFive\u0026#39;s prestigious industry partnerships. CSOC can further offer full custom SoCs with a silicon track record of over 300 tape-outs, nearly 150 million SoC units shipped with an average 25 DPPM and ISO 9001:2015 certification.\r\n\r\n\u0026quot;The paradigm has shifted,\u0026quot; said Naveed Sherwani, president and CEO of SiFive. \u0026quot;One-hundred-and-one design wins represents the fact that our hallmark power-efficient cores have been rapidly adopted by manufacturers in embedded markets, putting RISC-V cores firmly on the map and the RISC-V revolution well and truly established. SiFive customers value innovation and execution at speed, and, currently, SiFive remains the only company to offer commercial 64-bit embedded RISC-V cores. SiFive offers market-leading features such as heterogeneous coherent clusters where our E, S and U cores ranging from 7- to 2-series can be combined coherently in the same cluster. With these comprehensive offerings, the choice to partner with SiFive is clear.\u0026quot;\r\n\r\n## **About SiFive**\r\n\r\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 14 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [www.sifive.com](https://c212.net/c/link/?t=0\u0026amp;l=en\u0026amp;o=2489547-1\u0026amp;h=1518422255\u0026amp;u=http%3A%2F%2Fwww.sifive.com%2F\u0026amp;a=www.sifive.com).","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqe","uid":"sifive-brings-in-mobiveil-as-newest-partner-in-the-designshare-economy","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqe%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:45:32+0000","slugs":["sifive-brings-in-mobiveil-as-newest-partner-in-the-designshare-economy"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Brings in Mobiveil as Newest Partner in the DesignShare Economy","spans":[]}],"publish_to":"Archive","publish_date":"2018-03-22","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – March 22, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today announced that Mobiveil, a provider of Serial Interconnect IP blocks and platforms targeted for Flash Storage, IoT and Communication markets, has joined the growing DesignShare economy.\n\nMobiveil will make available its high-speed, serial interconnect IP blocks such as PCI Express, RapidIO, Memory Controllers and AXI Interconnect Fabric for DesignShare users to accelerate RISC-V based SOC development.\n\n“At Mobiveil, we’re dedicated to helping customers meet their product development goals within budget and on time,” said Ravi Thummarukudy, CEO, Mobiveil. “It’s why DesignShare aligns with our values. We hope this partnership lowers the barriers for all system designers to bring their innovations to life.”\n\n\nAny company, inventor or maker can harness the power of custom silicon with little to no upfront risk through the SiFive DesignShare program. To lower the costs of bringing a chip from design to realization, DesignShare partners like Mobiveil offer pre-integrated solutions that enable users to develop their prototypes without the investment in upfront engineering costs typically required.\n\n\n“The DesignShare initiative streamlines the process of IP acquisition for system designers,” said Shafy Eltoukhy, VP of operations and head of DesignShare at SiFive. “Partners like Mobiveil share our passion to reduce the number of obstacles that keep customers from creating prototypes, and significantly increase the new number of silicon design starts.”\n\nSince DesignShare launched last year, the ecosystem has grown to include a wide range of IP solutions, from debug and trace technology to reconfigurable FPGA.\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit [www.sifive.com](https://www.sifive.com).\n\n\n## About Mobiveil\n\nMobiveil is a fast-growing Technology company that specializes in silicon intellectual properties, platforms, and solutions for the Storage, IoT and Communications markets. The Mobiveil team leverages decades of experience in delivering high-quality, production-proven, high-speed serial interconnect Silicon IP cores and custom and standard form factor hardware platforms to leading customers worldwide. For the Flash Storage market, Mobiveil developed a PCI Gen4-based NVMe SSD Platform and for IoT market Mobiveil has developed an AXI based SOC platform. Mobiveil is headquartered in the Silicon Valley with engineering development centers located in Milpitas, California, Chennai, Bangalore and Hyderabad, India, and sales offices and representatives located worldwide. For more information, visit www.mobiveil.com\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (646) 756-3713\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Ravi Thummarukudy\u003cbr\u003e\n Mobiveil\u003cbr\u003e\n Ravi@mobiveil.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqW","uid":"terminus-circuits-brings-complete-asic-solutions-to-designshare","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqW%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:46:03+0000","slugs":["terminus-circuits-brings-complete-asic-solutions-to-designshare"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Terminus Circuits Brings Complete ASIC Solutions to DesignShare","spans":[]}],"publish_to":"Archive","publish_date":"2018-07-10","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – July 10, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today announced that [Terminus Circuits](http://www.terminuscircuits.com/), a provider of interconnect solutions, has joined the expanding DesignShare economy. Through DesignShare, Terminus Circuits will offer complete ASIC solutions for products that are modular and scalable.\n\n“At Terminus Circuits, we strive to offer our partners the best off-the-shelf, high-speed serial link products with high throughput and low latency,” said Dr. Sankar Reddy, founder and CEO of Terminus Circuits. “Through DesignShare, we hope to empower more system designers to create the future generations of enterprise-class servers, networks and storage products based on the SiFive Freedom platform.”\n\nThe DesignShare model democratizes access to custom silicon, allowing any company, maker or inventor to create an entirely new range of applications. The DesignShare program helps remove traditional barriers to entry that have blocked users from developing custom silicon by providing companies with low- or no-cost IP, reducing the upfront engineering costs required to bring a custom chip design based on the SiFive Freedom platform to realization.\n\n“Terminus Circuits contributions to the DesignShare ecosystem provides engineers faster and easier access to interconnect solutions,” said Shafy Eltoukhy, VP of operations and head of the DesignShare program. “The RISC-V architecture continues to grow significantly, and with Terminus Circuits as part of the DesignShare movement, it will create simpler processes for system developers to employ RISC-V in their future designs across a wide range of implementations.”\n\nSince the launch of the DesignShare ecosystem, the initiative has granted engineers access to a wide range of technology. In addition to ASIC solutions, developers can include cryptographic cores, embedded analytics, debug and trace technology, embedded, reconfigurable FPGA and logic-based, non-volatile memory to their SoCs.\n\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Intel Capital and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## About Terminus Circuits\n\nTerminus Circuits offers high-speed, serial-link IPs and provides interconnect solutions across many standards like USB.org, PCIe-SIG, IEEE, SATA etc. Our products are an integral part of any HPC systems, providing the interconnect solutions that scale bandwidth and deliver end-to-end signal integrity in next-generation platforms. These robust interface IPs are available for different foundries and broad spectrum of process technologies. Terminus Circuits delivers low power, small form factor, low latency, integrated clocking, interconnect IPs that are pervasive in virtually all of today's enterprise solutions in big data, digital storage and networks. For more information, visit [www.terminuscircuits.com](http://www.terminuscircuits.com/).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (646) 756-3713\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8jCMBQAACoAyHVX","uid":"sifive-welcomes-former-tesla-executive-to-lead-global-growth-strategy","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8jCMBQAACoAyHVX%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-18T17:26:11+0000","last_publication_date":"2022-08-08T20:44:05+0000","slugs":["sifive-welcomes-former-tesla-executive-to-lead-global-growth-strategy"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Welcomes Former Tesla Executive to Lead Global Growth Strategy","spans":[]}],"publish_to":"Archive","publish_date":"2018-10-02","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Oct. 2, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today announced the appointment of Keith Witek as Senior Vice President of Corporate Development and General Counsel.\n\n\"SiFive is creating and driving new technologies and business models to ensure that everyone has affordable access to RISC-V component and system development capabilities,\" said Witek. \"I'm excited to be a part of this team, as we continue to collaborate extensively across a wide range of technology partners, market segments, and geographies.\"\n\nKeith brings 30 years of technology, strategy, legal, operations, and business experience to SiFive. He holds more than 30 patents in semiconductor and related technologies, and has worked on or led notable projects including: the formation and execution of Tesla's custom development ecosystem for autopilot solutions, auto communications systems, and other Tesla strategic programs; the ATI and Global Foundries M\u0026A transactions for AMD; and the transfer of technology into joint partnerships and ventures in China, Russia, and other countries. During his time at Motorola, Wilson Sonsini Goodrich and Rosati, AMD, and Tesla, Witek led legal, business development, corporate development, engineering, and strategy teams to drive multi-national, strategic programs\n\n\n\"It is a great pleasure and honor that Keith has joined the SiFive team,\" said Naveed Sherwani, SiFive CEO. \"Our rapidly growing company can greatly benefit from his insights, wisdom, and years of experience in technology disruptors to become global industry leaders.\"\n\nKeith holds bachelors' degrees in electrical engineering and computer science from the University of Wisconsin-Madison, and holds a juris doctorate from the University of Texas at Austin.\n\n## About SiFive\n\n\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit [www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e","spans":[]}]}},{"id":"XK-WGhIAACIAlZXy","uid":"sifive-tapes-out-first-in-a-series-of-7nm-ip-enablement","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XK-WGhIAACIAlZXy%22%29+%5D%5D","tags":[],"first_publication_date":"2019-04-11T21:35:30+0000","last_publication_date":"2022-08-08T20:58:31+0000","slugs":["sifive-tapes-out-first-in-a-series-of-7nm-ip-enablement-platforms"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Tapes Out First in a Series of 7nm IP Enablement Platforms","spans":[]}],"publish_to":"Archive","publish_date":"2019-04-11","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"_Includes critical IP validation for HBM2E 3.2Gbps Interface, TCAM and more_\n\n**SAN MATEO, Calif. \u0026mdash; April 11, 2019 \u0026mdash;**\n\n[SiFive](https://www.sifive.com), the leading provider of commercial RISC-V processor IP and custom SoC solutions, today announced it has successfully taped out an IP enablement platform in 7nm FinFET technology that includes critical IP validation for SiFive's high bandwidth memory (HBM2E) 3.2Gbps interface, 2GHz Ternary Content-Addressable Memory (TCAM) partner IP, a low-voltage differential signaling (LVDS) interface and other key IP building blocks. The high-speed IP interface enablement platform is the first in a series of SiFive's next-generation platforms for high-performance and high-bandwidth applications. The forthcoming 7nm IP enablement platforms are:\r\n\r\n- HBM2E 2.5D ASIC SiP based on SiFive's RISC-V Core IP with vector extension, TileLink - a high-performance, scalable, cache-coherent fabric; high-performance caches; HBM2E controller and PHY; support for low latency HBM memory; DMA and peripherals. \r\n\n- Customizable Freedom Revolution AI SoC platform based on SiFive's 64-bit U7 and S7 Series RISC-V Multi-Core IP, TileLink, accelerator bays to connect a custom accelerator into the system, security IP, LPDDR5, an HBM2E controller and PHY, a PCIe5 SerDes and 56/112G SerDes.\r\n\n\"The design revolution taking place in the semiconductor industry has created unprecedented architectural freedom through customizable SoCs,\" said Shafy Eltoukhy, senior vice president and general manager of the Custom SoC Business Unit at SiFive. \"Our IP enablement platforms include internally developed IP along with the most robust, high-performance partner IP on the market for next-generation AI, networking and other high-performance applications in 7nm.\"\r\n\r\n## About SiFive\r\n\r\nSiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [www.sifive.com](http://www.sifive.com).","spans":[]}]}},{"id":"W_torBUAAC0Az3Nl","uid":"plda-offers-xpressrich-pcie-and-ccix-controller-ip","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W_torBUAAC0Az3Nl%22%29+%5D%5D","tags":[],"first_publication_date":"2018-11-26T14:00:00+0000","last_publication_date":"2022-08-08T20:51:35+0000","slugs":["plda-offers-xpressrich-pcie-and-ccix-controller-ip-through-sifive-designshare-program"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"PLDA Offers XpressRICH PCIe and CCIX Controller IP Through SiFive DesignShare Program","spans":[]}],"publish_to":"Archive","publish_date":"2018-11-26","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"_Latest contribution to ecosystem enables connectivity solutions for storage, networking, artificial intelligence, accelerators and high-performance computing applications_\n\n**SAN MATEO, Calif.** – Nov. 26, 2018 – [SiFive](http://www.sifive.com/), the leading provider of commercial RISC-V processor IP, today announced that PLDA, the leader in PCIe and CCIX Controller IP solutions has joined the DesignShare™ ecosystem. Through this collaboration, PLDA will provide its rich suite of XpressRICH core IP that enables high-speed connectivity solutions for many applications like enterprise storage, networking, high-performance computing and artificial intelligence to name a few.\n\nPLDA\u0026#39;s extensive suite of IP includes PCIe controllers, which can be configured to support endpoint, root port, and dual-mode topologies, allowing for a variety of use models, and exposes a configurable, flexible interconnect interface to the user. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling and adjusting a vast array of parameters, including number, type and width of AXI interfaces, PIPE interface width, low-power support, SR-IOV, ECC and AER for optimal throughput, latency, size and power. Users may optionally enable a built-in DMA engine for handling data transfers between the PCIe domain and the AXI domain. PLDA\u0026#39;s IP are verified using multiple PCIe VIPs and test suites and is proven in production silicon in hundreds of designs using a variety of commercial and proprietary PCIe PHYs.\n\n\u0026quot;Our configurable and scalable XpressRICH Controller IP product line fills a need in the SiFive DesignShare ecosystem. Teaming with SiFive will help us provide embedded designers around the world with access to PLDA\u0026#39;s interface IPs at little to no cost at the start of a design program,\u0026quot; said Arnaud Schleich, CEO, PLDA.\n\nThe availability of PLDA IP through the DesignShare program shortens the time to market and removes common barriers to entry that have traditionally prevented smaller companies from developing custom silicon. Companies like SiFive, PLDA and other DesignShare partners provide low- or no-cost IP to emerging companies, minimizing the upfront engineering costs needed to bring a custom chip from design to realization.\n\n\u0026quot;The ability to connect chips using PCIe or CCIX Interface is a must for technically advanced applications, and the addition of PLDA\u0026#39;s IP is an asset to the DesignShare program,\u0026quot; said Mohit Gupta, vice president, SoC IP, SiFive. \u0026quot;With the addition of PLDA to the DesignShare ecosystem, we continue to grow the portfolio of IP from which designers can choose when beginning work on a new prototype device.\u0026quot;\n\nSince DesignShare launched in 2017, the program has grown to include a wide range of IP solutions, from complete ASIC solutions and trace technology to embedded memory and precision PLL. For more information on DesignShare and to see the complete list of available technologies, visit [www.sifive.com/designshare](http://www.sifive.com/designshare).\n\n**About SiFive**\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Intel Capital and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit [www.sifive.com](http://www.sifive.com/).\n\n**About PLDA**\n\nPLDA is a developer and licensor of Semiconductor Intellectual Property (SIP) specializing in high-speed interconnect supporting multi-gigabit rates (2.5G, 5G, 8G, 16G, 25G, 32G, 56G, 112G), and protocols such as PCI Express, CCIX, and Gen-Z. PLDA has established itself as a leader in that space with over 3,200 customers and 6,800 licenses in 62 countries. PLDA is a global technology company with offices in Silicon Valley, France, Bulgaria, Taiwan, and China.\n\n**Media Contact:**\n\nLeslie Clavin\u003cbr/\u003e\nSHIFT Communications for SiFive\u003cbr/\u003e\n(415) 591-8440\u003cbr/\u003e\n[sifive@shiftcomm.com](mailto:sifive@shiftcomm.com)\n\n###\n\n_SiFive and DesignShare are trademarks and service marks of SiFive, Inc. which may be registered in the United States and other jurisdictions. All other trademarks are the property of their respective holders._","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vq4","uid":"brite-semiconductor-joins-sifives-designshare-program","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vq4%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:44:20+0000","slugs":["brite-semiconductor-joins-sifives-designshare-program"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Brite Semiconductor Joins SiFive's DesignShare Program","spans":[]}],"publish_to":"Archive","publish_date":"2018-05-22","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSan Mateo, Calif. – May 22, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today welcomed Brite Semiconductor, an ASIC service company invested by SMIC, to the growing DesignShare ecosystem.\n\nThe partnership enables Brite Semiconductor to offer DDR IP, which complies with DDR2/3/4 and LPDDR2/3/4, up to 2667MT/s. Brite Semiconductor's DDR technology will make it easier for SiFive customers to speed data transfer rates on their RISC-V based SoCs within a reduced power envelope. Brite Semiconductor's proven silicon will not only lower costs to designers, but also enable them to shorten production time.\n\n\"Brite is committed to promote innovation in ASIC business through collaboration and ecosystem development,\" said Thomas Xu, CEO of Brite Semiconductor. \"The demand for open-source hardware is increasing, and DesignShare offered by SiFive is a great platform to provide designers access to what they want.\"\n\nThe availability of Brite Semiconductor's DDR IP through the DesignShare program shortens the time to market and removes common barriers to entry that have historically blocked smaller companies from developing custom silicon. Companies like SiFive, Brite Semiconductor and other ecosystem partners provide low- or no-cost IP to emerging companies, reducing the upfront engineering costs required to bring a custom chip design to realization.\n\n\"Brite Semiconductor's DDR IP makes it simpler for engineers to use RISC-V in their future designs.\" said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. \"We're excited to see the innovations stemming from our DesignShare ecosystem.\"\n\nSince DesignShare launched in 2017, the program has grown to include a wide range of IP solutions, from debug and trace technology to embedded memory and reconfigurable FPGA.\n\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## About Brite Semiconductor\n\nBrite Semiconductor is a world-leading ASIC design solution provider and DDR controller/PHY provider, targeting at ULSI ASIC/SoC chip design on SMIC process technologies and turn-Key solutions. Brite Semiconductor provides flexible one-stop services from RTL/netlist to chip delivery, seamless, cost effective, and low-risk solutions to customers. Brite Semiconductor was founded in 2008 by venture capital firms from China and abroad, and invested by Semiconductor Manufacturing International Corporation (SMIC) as a strategic partner in 2010. Headquarter in Shanghai, Brite has offices in Beijing, Hefei, US, Europe, Japan and Taiwan.\n\nFor more information, please visit [www.britesemi.com](http://www.britesemi.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"XQhJbxEAACMAgQHe","uid":"sifive-enhances-silicon-hills-operations-with-office","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XQhJbxEAACMAgQHe%22%29+%5D%5D","tags":[],"first_publication_date":"2019-06-18T13:38:50+0000","last_publication_date":"2022-08-08T20:59:24+0000","slugs":["sifive-enhances-silicon-hills-operations-with-office-in-austin-texas"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Enhances Silicon Hills Operations with Office in Austin, Texas","spans":[]}],"publish_to":"Archive","publish_date":"2019-06-18","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Central Texas\u0026#39; Hill Country area populated by high-tech companies is joined by the latest office of the leader in RISC-V semiconductor IP design and development*\n\n## SAN MATEO, Calif., -- June 18, 2019 -- \n[SiFive](https://c212.net/c/link/?t=0\u0026amp;l=en\u0026amp;o=2500380-1\u0026amp;h=1778759696\u0026amp;u=https%3A%2F%2Fwww.sifive.com%2F\u0026amp;a=SiFive), Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, announced today it has further expanded its existing presence in the Austin, Texas, \u0026quot;Silicon Hills\u0026quot; area with the opening of an office to support all aspects of SiFive\u0026#39;s business operations. The Austin office will drive company-wide corporate development, business development, legal, and strategy operations, led by long-time semiconductor executives, Keith Witek, SiFive\u0026#39;s SVP of corporate development and general counsel, and Hiren Majmudar, the company\u0026#39;s VP of business development. There are 14 employees at the SiFive office, located in Bee Cave, covering sales, field application engineering, product, and marketing functions. The office is hiring more employees this year.\n\n\u0026quot;Strong relationships with technology companies are key to SiFive\u0026#39;s future success and growth,\u0026quot; Witek said. \u0026quot;Austin is a large and growing technology hub, and SiFive\u0026#39;s presence here will allow us to strengthen critical business alliances. Our goal is to help customers create new system-on-a-chip (SoC) solutions with the advantages of reduced cost, faster time-to-market, more efficient use of headcount and lower risk, all accelerated through pervasive ecosystem support and the rapid customization and innovation that an open source business models can enable.\u0026quot;\r\n\r\nThe Austin expansion is just the latest demonstration of SiFive\u0026#39;s growth and momentum, including marking more than 100 SiFive Core IP design wins and the announcement of key relationships with companies like Qualcomm and Imagination Technologies. SiFive also recently secured $65 million in Series D funding to continue to fuel the innovation and leadership shown by SiFive in the RISC-V ecosystem. Additionally, SiFive has announced a partnership with Avatar Integrated Systems to strengthen cloud-based design capabilities, and a partnership with Quicklogic Corp., to create System-on-Chip (SoC) RISC-V templates to dramatically reduce development cost and time for custom silicon SoC solutions.\r\n\r\n\u0026quot;Our mission is to enable everyone, from individual innovators to startups to large multi-national corporations, to create custom hardware for their products with customizable RISC-V IP and cloud-based SoC development,\u0026quot; said Majmudar. \u0026quot;With a RISC-V strategy top of mind for many leading semiconductor companies, we will make RISC-V cores, efficient cloud SoC design and SiFive solutions the clear choice for improving design efficiency for teams driving differentiated SoC solutions to market.\u0026quot;\r\n\r\nWitek brings 30 years of technology, strategy, legal, operations and business experience to SiFive. He holds more than 30 patents in semiconductor and related technologies, and has driven teams that contributed to the formation and execution of Tesla\u0026#39;s custom development ecosystem for autopilot solutions, auto communications systems and other Tesla strategic programs; various strategic transactions at AMD involving ATI, GlobalFoundries, outsourced assembly and test operations, DTV business, mobile divisions, and IP development; and the transfer of various technologies into joint partnerships and ventures in China, Russia and other countries. During his time at Motorola, Wilson Sonsini Goodrich and Rosati, AMD and Tesla, Witek led legal, business development, corporate development, venture capital, engineering and strategy teams to drive multinational, strategic programs.\r\n\r\nMajmudar recently led Intel Capital\u0026#39;s corporate development practice for silicon and IP and brings more than 25 years of business and technology leadership experience to SiFive. During his time at Intel Capital, the world\u0026#39;s largest corporate venture capital group, Majmudar spearheaded a renewed focus on equity investments and mergers and acquisitions for silicon design and intellectual property. He also led Intel Capital\u0026#39;s investment in SiFive and served as a board observer for the company. Prior to this role, Majmudar built Intel\u0026#39;s third-party IP ecosystem and enabled Intel\u0026#39;s corporate transition to the world of SoCs. Majmudar also has 15 years of engineering leadership in chip design, EDA development, and software tools sales and marketing.\r\n\r\n\u0026quot;Like many other leading semiconductor companies, investing in a physical presence in Austin is a necessary step for SiFive\u0026#39;s continued success,\u0026quot; said Naveed Sherwani, SiFive CEO. \u0026quot;We have covered Austin extensively since our early days, and now we have a complete infrastructure that is connected to our global operations. This shows not only the talent pool in Austin but the robust capabilities of SiFive. Every semiconductor company needs an answer to continued efficiency and innovation, and we believe this means they need SiFive as their partner for their RISC-V solutions and their cloud SoC development strategy.\u0026quot;\r\n\r\n## **About SiFive**\r\n\r\nSiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, [www.sifive.com](https://c212.net/c/link/?t=0\u0026amp;l=en\u0026amp;o=2500380-1\u0026amp;h=434269542\u0026amp;u=http%3A%2F%2Fwww.sifive.com%2F\u0026amp;a=www.sifive.com).","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrq","uid":"analog-bits-to-provide-precision-pll-and-serdes-ip-to-designshare-for-sifive-freedom-platform","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrq%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:48:17+0000","slugs":["analog-bits-to-provide-precision-pll-and-serdes-ip-to-designshare-for-sifive-freedom-platform"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Analog Bits to Provide Precision PLL and SERDES IP to DesignShare for SiFive Freedom Platform","spans":[]}],"publish_to":"Archive","publish_date":"2017-11-14","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Nov. 14, 2017 – \u003c/span\u003e\n[SiFive](https://www.sifive.com/),\nthe first fabless provider of customized, open-source-enabled semiconductors,\ntoday announced that Analog Bits, the industry’s leading provider of low-power\nmixed-signal IP (Intellectual Property) solutions, has joined the growing\nDesignShare economy. Analog Bits will provide precision clocking macros such as\nPLLs and SERDES IP available for the SiFive Freedom platforms through the\nDesignShare initiative.\n\n\"For two decades, Analog Bits has been an important supplier of low-power IP\nfor use in SoC devices and helped spawn the mobile and computing revolution,\"\nsaid Mahesh Tirupattur, Executive Vice President, Analog Bits. \"Through\nDesignShare, we hope to empower more system developers and provide them\nwith the competitive edge they need to deliver innovative SoC products in a\ntimely manner.\"\n\nThe DesignShare model democratizes access to custom silicon and allows any\ncompany, maker or inventor to create an entirely new range of applications.\nCompanies like SiFive, Analog Bits and other DesignShare partners help remove\ntraditional barriers to entry that traditionally have blocked users from\ndeveloping custom silicon. This provides companies with low- or no-cost IP,\nreducing the upfront engineering costs required to bring a custom chip design\nbased on the SiFive Freedom platform to realization. \n\n\"The addition of Analog Bits to the DesignShare ecosystem provides engineers\nwith a faster and more efficient way to bring SoCs to market,\" said Shafy\nEltoukhy, who leads the DesignShare program for SiFive. \"The adoption of the\nRISC-V architecture continues to experience significant growth, and with Analog\nBits as part of the DesignShare movement, it will be easier and more flexible\nfor designers to employ RISC-V in their future designs across a wide range of\nimplementations.\"\n\nWithin months of launching the DesignShare ecosystem, the initiative has\ngranted system designers access to a wide range of technology. In addition to\nPLLs and SERDES IP, developers can include cryptographic cores, embedded\nanalytics, debug and trace technology, embedded, reconfigurable FPGA and\nlogic-based, non-volatile memory to their SoCs.\n\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the\nfree and open RISC-V instruction set architecture. Founded by RISC-V inventors\nAndrew Waterman, Yunsup Lee and Krste Asanovic, SiFive democratizes access to\ncustom silicon by helping system designers reduce time-to-market and realize\ncost savings with customized RISC-V based semiconductors. SiFive is located in\nSilicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital\nand Osage University Partners. For more information, visit [www.sifive.com](https://www.sifive.com).\n\n\n## About Analog Bits\n\nFounded in 1995, Analog Bits, Inc. ([www.analogbits.com](http://www.analogbits.com)), is a leading supplier\nof mixed-signal IP with a reputation for easy and reliable integration into\nadvanced SOCs. Products include precision clocking macros such as PLLs \u0026 DLLs,\nprogrammable interconnect solutions such as multi-protocol SERDES and\nprogrammable I/O’s as well as specialized memories such as high-speed SRAMs and\nTCAMs. With billions of IP cores fabricated in customer silicon and design\nkits supporting processes from 0.35-micron to 7-nm, Analog Bits has an\noutstanding heritage of \"first-time-working\" with foundries and IDMs.\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (646) 756-3713\u003cbr\u003e\n sifive@shiftcomm.com \n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vq0","uid":"sifive-welcomes-former-intel-corporate-vp-to-executive-team","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vq0%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:41:24+0000","slugs":["sifive-welcomes-former-intel-corporate-vp-to-executive-team"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Welcomes Former Intel Corporate VP to Executive Team","spans":[]}],"publish_to":"Archive","publish_date":"2018-01-22","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Jan. 22, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com/),\nthe leading provider of commercial RISC-V processor IP, today announced the\nappointment of Sunil Shenoy as vice president of hardware engineering. The news\nfollows SiFive’s momentous expansion last quarter with its strategic\npartnerships, launch of the first Linux-capable RISC-V core and growth of the\nDesignShare program. \n\n“SiFive is leading the disruption of the semiconductor industry with effective\nimplementation of the RISC-V instruction set architecture,” said Shenoy. “I’m\nthrilled to be a part of this revolution, leading the charge on a new\narchitecture and changing the way the industry does hardware design.”\n\nShenoy brings more than 30 years of technology experience to SiFive, holding 16\npatents in microprocessor design, and working on or leading notable projects\nincluding the Intel PentiumTM 4 generation of microprocessors, highly\nintegrated multi-core Intel XeonTM microprocessors for datacenter and\nenterprise servers,and the family of massively parallel Intel Xeon PhiTM\nmicroprocessors. During his time at Intel, Shenoy led silicon development teams\nconsisting of several thousand engineers across the world, helping to bring\nproducts successfully to market. He also drove collaborative programs with\nmajor EDA vendors. Sunil was promoted to Corporate VP at Intel in 2010. In 2013\nhe joined the Intel management committee reporting to the CEO.\n\n“We’re excited to bring in Sunil to help SiFive support the growth of RISC-V\nand meet rising demands of the industry,” said Naveed Sherwani, SiFive CEO.\n“His experience in leading large processor design teams that generated multiple\nmarket-leading products will help us advance SiFive’s Core IP and processors\nfor expanding market segments, and expand our position in the marketplace.”\n\nSunil has a master’s degree in computer engineering from Syracuse University, a\nmaster’s degree in business administration from University of Oregon and\nrecently has completed extensive graduate studies in computer science.\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the\nfree and open RISC-V instruction set architecture. Founded by RISC-V inventors\nAndrew Waterman, Yunsup Lee and Krste Asanovic, SiFive helps SoC designers\nreduce time-to-market and realize cost savings with customized,\nopen-architecture processor cores, and democratizes access to optimized silicon\nby enabling system designers to build customized RISC-V based semiconductors.\nSiFive is located in Silicon Valley and has venture backing from Sutter Hill\nVentures, Spark Capital and Osage University Partners. For more information,\nvisit [www.sifive.com](https://www.sifive.com).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (646) 756-3713\u003cbr\u003e\n sifive@shiftcomm.com \n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrC","uid":"intel-capital-event","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrC%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:43:56+0000","slugs":["sifive-announces-investment-from-intel-capital"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Announces Investment from Intel Capital","spans":[]}],"publish_to":"Archive","publish_date":"2018-05-08","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – May 8, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today announced that Intel Capital participated in its recent Series C funding round. The investment was revealed at the Intel Capital Global Summit, at which SiFive CEO Naveed Sherwani pushed for the democratization of the semiconductor industry.\n\nSiFive’s hardware designs leverage the body of software and tools available from the open-source community under the guidance of the [RISC-V Foundation](https://riscv.org/), dramatically reducing the cost of developing custom silicon. RISC-V was born from the dire need to address the skyrocketing cost of designing and manufacturing increasingly complex new chip architectures. System designers can use the SiFive Freedom platforms and DesignShare catalog to focus on their own differentiated processor without having the overhead of developing a modern SoC, fabric or software infrastructure.\n\n“We have long led the call for a revolution in the semiconductor industry, and believe SiFive, and our technologies, demonstrate a significant path forward for the industry,” said SiFive CEO Naveed Sherwani. “This investment by Intel Capital will enable SiFive to empower any individual or company to produce a silicon solution that meets their needs, quickly and affordably.”\n\n“RISC-V offers a fresh approach to low power microcontrollers combined with agile development tools that have the potential to help reduce SoC development time and cost significantly,” said Raja Koduri, senior vice president of the Core and Visual Computing Group, general manager of edge computing solutions and chief architect at Intel Corporation. “SiFive’s cloud-based SaaS approach provides another level of flexibility and ease for design teams, and we look forward to exploring its benefits.”\n\nIn April, SiFive announced it had raised $50.6 million in Series C funding led by existing investors Sutter Hill Ventures, Spark Capital and Osage University Partners, as well as new investors Chengwei Capital, Huami, SK Telecom and Western Digital.\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com)\n\n\n## About Intel Capital\n\nIntel Capital invests in innovative startups targeting artificial intelligence, autonomous driving, workload accelerators, 5G connectivity, virtual reality and a wide range of other disruptive technologies. Since 1991, Intel Capital has invested more than $12.3 billion in 1,530 companies worldwide, and more than 660 portfolio companies have gone public or been acquired. Through its business development programs, Intel Capital curates thousands of introductions each year between its portfolio executives and Intel's customers and partners in the Global 2000. For more information on what makes Intel Capital one of the world’s most powerful venture capital firms, visit [www.intelcapital.com](http://www.intelcapital.com/) or follow [@intelcapital](https://twitter.com/intelcapital).\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqk","uid":"chipus-brings-ultra-low-power-ip-to-sifives-designshare-ecosystem","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqk%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:45:54+0000","slugs":["chipus-brings-ultra-low-power-ip-to-sifives-designshare-ecosystem"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Chipus Brings Ultra-Low-Power IP to SiFive’s DesignShare Ecosystem","spans":[]}],"publish_to":"Archive","publish_date":"2018-07-27","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – July 27, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\nthe leading provider of commercial RISC-V processor IP, today welcomed [Chipus Microelectronics](http://chipus-ip.com/), a semiconductor company with proven expertise in the development of ultra-low-power (ULP), low-voltage, analog and mixed-signal integrated circuits, to the growing DesignShare ecosystem. Through the partnership, Chipus will provide ULP IP for power management and ULP RF Front-Ends.\n\nChipus’ customizable technology will make it easier for SiFive customers to save power and extend battery life for IoT edge devices. Chipus also plans to add temperature sensors and switched regulators to the DesignShare program in the near future.\n\n“Chipus is thrilled to partner up with SiFive to bring more chip design opportunities to reality, enabling innovation with our Ultra-Low-Power and simple-to-customize IP solutions,” said Murilo Pilon Pessatti, CEO and co-founder of Chipus. “Our mission, together with SiFive, is to enable innovation. With our expertise, Chipus looks forward to contributing to new IoT applications and edge devices.”\n\nThe availability of Chipus’ ULP IP through the DesignShare program shortens the time to market and removes common barriers to entry that have traditionally prevented smaller companies from developing custom silicon. Companies like SiFive, Chipus and other DesignShare partners provide low- or no-entry fee IP to emerging companies, minimizing the upfront engineering costs needed to bring a custom chip from design to realization.\n\n“Startups today go through extensive processes, from sourcing viable IP to negotiating legal contracts, before they can even develop a prototype,” said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. “With Chipus joining our growing DesignShare economy, we continue to simplify the prototyping process and spur innovation across the industry.”\n\nSince DesignShare launched in 2017, the program has grown to include a wide range of IP solutions, from complete ASIC solutions and trace technology to embedded memory and precision PLL.\n\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Intel Capital and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n\n## About Chipus Microelectronics\n\nChipus Microelectronics is a semiconductor company with proven expertise in the development of ultra-low-power, low-voltage, analog and mixed-signal integrated circuits (ICs) and systems on chip (SoCs).\n\nRelying on a strong experience in power management and data converters, the company has more than 200 IP mixed-signal blocks in process nodes from 40nm to 0.35um of various foundries. Since its foundation in 2008, Chipus has provided IC design services in leading edge technologies also, including down to 28nm and 10nm, with firm commitment and flexible client support to customers worldwide (USA and Americas, Europe, and Asia).\n\nHeadquartered in Florianópolis, Brazil, Chipus has a US subsidiary in Silicon Valley and sales team in Europe.\n\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Stephanie Chan\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (646) 756-3713\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vqg","uid":"asic-design-services-adds-core-deep-learning-ip-to-sifive-designshare-program","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vqg%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:45:44+0000","slugs":["asic-design-services-adds-core-deep-learning-ip-to-sifive-designshare-program"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"ASIC Design Services Adds Core Deep Learning IP to SiFive DesignShare Program","spans":[]}],"publish_to":"Archive","publish_date":"2018-08-21","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Aug. 21, 2018 – \u003c/span\u003e\n[SiFive](https://www.sifive.com),\n the leading provider of commercial RISC-V processor IP, today announced that ASIC Design Services, a design house, IP provider, and a distributor for FPGA and EDA software, has joined the DesignShare ecosystem. Through this partnership, ASIC Design Services will provide its Core Deep Learning (CDL) technology that accelerates Convolutional Neural Networks (CNNs) on power-constrained embedded hardware platforms.\n\nASIC Design Services’ CDL technology optimizes its CNN accelerator FPGA core for performance, logic resources, and low power – making CDL suitable for IoT edge and node applications. The CDL Coldbrew software stack performs quantization and compression of CNNs, design space exploration, and generates a solution optimized for performance, resources, and low power. Coldbrew is built on the Caffe deep learning framework, and provides a simple user interface to bridge the gap between high-level CNN specification and FPGA design.\n\n“We are excited about the increased performance and energy efficiency offered by FPGAs,” said Tony Dal Maso, CEO of ASIC Design Services. “Today, we can achieve 100 Gops/s/Watt on a low-power FPGA solution. By partnering with SiFive we enable the global community of embedded designers to accelerate deep learning solutions on embedded platforms.” \n\nThe availability of ASIC Design Services’ CDL IP through the DesignShare program shortens the time to market and removes common barriers to entry that have traditionally prevented smaller companies from developing custom silicon. Companies like SiFive, ASIC Design Services and other DesignShare partners provide low- or no-cost IP to emerging companies, minimizing the upfront engineering costs needed to bring a custom chip from design to realization. \n\n“Adding artificial intelligence and neural networks to edge devices is increasingly in demand,” said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. “With ASIC Design Services addition to the DesignShare ecosystem, we continue to expand the range of IP available to designers looking to bring prototype devices to life. \n\nSince DesignShare launched in 2017, the program has grown to include a wide range of IP solutions, from complete ASIC solutions and trace technology to embedded memory and precision PLL.\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Intel Capital and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n\n## About ASIC Design Services\n\nASIC Design Services is a design house, IP provider, and a distributor for FPGA devices and electronic design automation software. Founded in 1989, the company has its origins as a design house for ASICs. ASIC Design Services has developed a core generator for accelerating Deep Learning applications in hardware. IP solutions include Deep Learning and SATA cores. ASIC Design Services is based in Midrand, South Africa. For more information on CDL, visit [www.coredeeplearning.ai](https://www.coredeeplearning.ai). For more information on ASIC Design Services, visit [www.asic.co.za](https://www.asic.co.za). \n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n","spans":[]}]}},{"id":"XAa3YBEAAC8Aoa2e","uid":"industrys-first-risc-v-soc-fpga-architecture-brings","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XAa3YBEAAC8Aoa2e%22%29+%5D%5D","tags":[],"first_publication_date":"2018-12-04T17:37:24+0000","last_publication_date":"2022-08-08T20:51:52+0000","slugs":["industrys-first-risc-v-soc-fpga-architecture-brings-real-time-to-linux-giving-developers-the-freedom-to-innovate-in-low-power-secure-and-reliable-designs"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"Industry's First RISC-V SoC FPGA Architecture Brings Real-Time to Linux, Giving Developers the Freedom to Innovate in Low-Power, Secure and Reliable Designs","spans":[]}],"publish_to":"Archive","publish_date":"2018-12-04","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Demonstrations at RISC-V Summit Dec. 4-5 to Show Size, Power and\nPerformance Benefits of Integrating PolarFire SoC's Hard CPU Subsystem\nwith Programmable Logic*\n\n**RISC-V Summit, SANTA CLARA, Calif.—Dec. 4, 2018—** In a new era of\ncomputing driven by the convergence of 5G, machine learning and the\ninternet of things (IoT), embedded developers need the richness of\nLinux-based operating systems. These must meet deterministic system\nrequirements in ever lower power, thermally constrained design\nenvironments---all while addressing critical security and reliability\nrequirements. Traditional system-on-chip (SoC) field programmable gate\narrays (FPGAs) blending reconfigurable hardware with Linux-capable\nprocessing on a single chip provide developers ideal devices for\ncustomization, yet consume too much power, lack proven levels of\nsecurity and reliability, or use inflexible and expensive processing\narchitectures. In response, Microchip Technology Inc. (**Nasdaq:\nMCHP**), via its Microsemi Corporation subsidiary, today extended its\nMi-V ecosystem by unveiling the **architecture for a new class of SoC\nFPGAs** that combine the industry's lowest power mid-range PolarFire™\nFPGA family with a complete microprocessor subsystem based on the open,\nroyalty-free RISC-V instruction set architecture (ISA).\n\nAnnounced today at the RISC-V Summit in Santa Clara, California,\nMicrochip's new PolarFire SoC architecture brings real-time\ndeterministic asymmetric multiprocessing (AMP) capability to Linux\nplatforms in a multi-core coherent central processing unit (CPU)\ncluster. The PolarFire SoC architecture, developed in collaboration with\nSiFive, features a flexible 2 MB L2 memory subsystem that can be\nconfigured as a cache, scratchpad or a direct access memory. This allows\ndesigners to implement deterministic real-time embedded applications\nsimultaneously with a rich operating system for a variety of thermal and\nspace constrained applications in collaborative, networked IoT systems.\n\n\"The PolarFire SoC architecture is a compelling combination of low\npower, security and reliability in a configurable device that brings\nreal-time to Linux,\" said Bruce Weyer, vice president of the\nProgrammable Solutions business unit at Microchip. \"Coupled with our\nrobust Mi-V RISC-V ecosystem and Microchip's extensive portfolio of\nsystem solutions, the PolarFire SoC architecture gives customers an\nexcellent platform to meet computing's next great challenges.\"\n\nPolarFire SoC includes extensive debug capabilities including\ninstruction trace, 50 breakpoints, passive run-time configurable\nAdvanced eXtensible Interface (AXI) bus monitors and FPGA fabric\nmonitors, and Microchip's built-in two-channel logic analyzer\nSmartDebug. The PolarFire SoC architecture includes reliability and\nsecurity features such as single error correction and double error\ndetection (SEC-DED) on all memories, physical memory protection, a\ndifferential power analysis (DPA) safe crypto core, defense-grade secure\nboot and 128Kb flash boot read-only memory (ROM).\n\n\"As a fully customizable, programmable RISC-V platform, the PolarFire\nSoC architecture gives designers the freedom to create innovative\nLinux-based SoCs in novel and interesting ways tailored for their\ndistinct, domain-specific requirements,\" said SiFive CEO Naveed\nSherwami. \"By leveraging SiFive's market-leading U54-MC CPU core\ncomplex, PolarFire SoC will enable designers to overcome the universal\nchallenge of building real-time systems with predictable behaviors.\"\n\n## Development Tools\n\nEvaluate and begin PolarFire SoC designs today using the **antmicro\nRenode™** system modeling platform, which is now integrated with\nMicrochip's SoftConsole integrated design environment (IDE) for embedded\ndesigns targeting PolarFire SoCs. A PolarFire SoC development kit is\nalso available now, consisting of the PolarFire FPGA-enabled HiFive\nUnleashed Expansion Board and SiFive's HiFive Unleashed Development\nBoard with its RISC-V microprocessor subsystem. For more information,\nvisit **www.microsemi.com/polarfiresoc** or contact\n**sales.support\\@microsemi.com**.\n\n## Microchip's New Mi-V Embedded Experts Program\n\nAs part of today's announcement, Microchip is launching a new Mi-V\nEmbedded Experts Program, a worldwide partner network to assist\ncustomers in hardware/software designs for PolarFire SoC. The addition\nof this program ensures support throughout the entire lifecycle of\ncustomer products, and helps to jump-start designs and shorten time to\nmarket. Members also get access to direct technical support and early\naccess to development platforms and silicon. Visit\n**www.microsemi.com/product-directory/fpga-soc/5210-mi-v-embedded-ecosystem**\nor contact **Mi-V-EmbeddedPartner\\@microchip.com** for more information.\n\n## About Microchip\n\nMicrochip Technology Inc. is a leading provider of microcontroller,\nanalog, FPGA, connectivity and power management semiconductors. Its\neasy-to-use development tools and comprehensive product portfolio enable\ncustomers to create optimal designs which reduce risk while lowering\ntotal system cost and time to market. The company's solutions serve more\nthan 130,000 customers across the industrial, automotive, consumer,\naerospace and defense, communications and computing markets.\nHeadquartered in Chandler, Arizona, Microchip offers outstanding\ntechnical support along with dependable delivery and quality. For more\ninformation, visit the Microchip website at **www.microchip.com**.\n\nSource: Microchip Technology Inc.\n\nNote: The Microchip name and logo, the Microchip logo and Microsemi are\nregistered trademarks of Microchip Technology Incorporated in the U.S.A.\nand other countries. PolarFire is a trademark of Microchip Technology\nInc. in the U.S.A. and other countries. All other trademarks mentioned\nherein are the property of their respective companies.\n\n## EDITORIAL CONTACT:\n\nBeth P. Quezada\n\n949-380-6102\n\npress\\@microsemi.com","spans":[]}]}},{"id":"W8Zy0xAAAGcn4vrK","uid":"sifive-advances-custom-silicon-industry-with-new-partnerships-products-at-7th-risc-v-workshop","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22W8Zy0xAAAGcn4vrK%22%29+%5D%5D","tags":[],"first_publication_date":"2018-10-16T23:23:17+0000","last_publication_date":"2022-08-08T20:47:11+0000","slugs":["sifive-advances-custom-silicon-industry-with-new-partnerships-products-at-7th-risc-v-workshop"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"SiFive Advances Custom Silicon Industry with New Partnerships, Products at 7th RISC-V Workshop","spans":[]}],"publish_to":"Archive","publish_date":"2017-11-28","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"\u003cspan class=\"dateline\"\u003eSAN MATEO, Calif. – Nov. 28, 2017 – \u003c/span\u003e\nAt the 7th RISC-V Workshop today,\n[SiFive](https://www.sifive.com/),\nthe first fabless provider of customized, open-source-enabled semiconductors,\nannounced a number of new partnerships and products that exemplify the\ncompany’s rapid growth over the past year. These announcements provide further\nproof of SiFive’s leadership in aligning with industry leaders to spur\ninnovation in the plateauing semiconductor industry as well as the company’s\nability to meet increased demand for open access to custom silicon. The\nadoption of SiFive’s RISC-V Core IP continues to grow, with more than 150\nevaluation licenses in progress.\n\nSiFive news and activities at the workshop include:\n\n* **An extended partnership with Microsemi:** Microsemi and SiFive formed a\nstrategic partnership to create and market a development board based on\nSiFive’s RISC-V based Freedom Unleashed 500 (U500) platform and Microsemi’s\nPolarFire FPGAs. (See related press release, “SiFive and Microsemi Expand\nRelationship with Strategic Roadmap Alignment and a Linux-Capable, RISC-V\nDevelopment Board.”)\n\n* **Membership in GLOBALFOUNDRIES’ FDXcelerator Partner Program:** SiFive has\njoined the GF program that brings together select partners to\nintegrate their products or services into validated, plug-and-play design\nsolutions. This provides GF customers access to SiFive RISC-V Core IP alongside\na broad set of quality offerings specific to GF’s 22FDX technology.\n\n* **OnChip demonstration:** SiFive partner OnChip will unveil and demonstrate\na suite of IP to support analog peripherals and an always-on power domain,\nwhich will be available through the DesignShare program to create mixed-signal\nRISC-V SoCs.\n\nThe news comes on the heels of SiFive’s recent release of the industry’s first\nRISC-V based Linux core: U54-MC Coreplex IP, a 64-bit, quadcore real-time\ncapable application processor with support for full featured operating systems.\nThe standard U54-MC Coreplex contains four U54 CPUs along with a single E51\nCPU, and is the first commercial RISC-V core to include multicore support and\ncache coherence.\n\nSiFive also forged a string of new partnerships recently including:\n\n* **SEGGER Microcontroller:** SEGGER in September added support for SiFive’s\n Coreplex IP to its J-Link debug probe, making it the first commercial\n debugging tool available for RISC-V cores.\n\n* **Lauterbach:** In October, Lauterbach partnered with SiFive to bring\n TRACE32 support for high-performance RISC-V cores, providing multicore\n debugging on individual hardware threads of SiFive cores, enabling debugging\n right from the reset vector, which analyzes startup codes and other key\n functions.\n\nBoth products will be available for demos at the 7th RISC-V Workshop.\n\nIn addition to new partnerships and products, SiFive launched the\nDesignShare\ninitiative earlier this year to give any company, inventor or maker the ability\nto harness the power of custom silicon with little to no upfront risk. Within a\nfew months of its debut, companies including Rambus, Flex Logix, UltraSoC,\nAnalog Bits and other industry leaders have joined SiFive’s DesignShare\nmovement to provide low- or no-cost IP to emerging companies, lowering the\ninitial engineering costs required to bring a custom chip design based on the\nSiFive Freedom platform to realization.\n\n“From the beginning, SiFive has helped lead the charge in driving the\nadvancement of RISC-V in the market,” said Rick O’Connor, executive director of\nthe non-profit RISC-V Foundation. “Its work in expanding the RISC-V IP catalog\nhas been instrumental in the monumental momentum that RISC-V has achieved over\nthe past two years.”\n\nSiFive’s continued commitment to the industry have led to multiple nominations\nfor awards such as “Start-Up to Watch” by Global Semiconductor Alliance Award\nand two UBM Annual Creativity in Electronics (ACE) Awards.\n\n“This has been a banner year for SiFive,” said Naveed Sherwani, CEO, SiFive.\n“The progress we have achieved is a direct result of the market’s overwhelming\ninterest in RISC-V as an alternative to legacy architectures. SiFive’s ability\nto push the barriers of what’s possible and engage with industry leaders has\nplaced us in a strong position as we look ahead to 2018.”\n\n## About SiFive\n\nSiFive is the first fabless provider of customized semiconductors based on the\nfree and open RISC-V instruction set architecture. Founded by RISC-V inventors\nYunsup Lee, Andrew Waterman and Krste Asanovic, SiFive democratizes access to\ncustom silicon by helping system designers reduce time-to-market and realize\ncost savings with customized RISC-V based semiconductors. SiFive is located in\nSilicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital\nand Osage University Partners. For more information, visit\n[www.sifive.com](https://www.sifive.com).\n\n## MEDIA CONTACTS\n\n\u003caddress\u003e\n Jack Kang\u003cbr\u003e\n SiFive\u003cbr\u003e\n (510) 673-1309\u003cbr\u003e\n jack@sifive.com\n\u003c/address\u003e\n\n\u003caddress\u003e\n Leslie Clavin\u003cbr\u003e\n SHIFT Communications for SiFive\u003cbr\u003e\n (415) 591-8440\u003cbr\u003e\n sifive@shiftcomm.com\n\u003c/address\u003e\n\n\n","spans":[]}]}},{"id":"XAa2xhEAAC0Aoary","uid":"iar-systems-and-sifive-partner-to-meet-customers-demands","url":null,"type":"press_release","href":"https://sifive.cdn.prismic.io/api/v2/documents/search?ref=Z1AK-xAAALKMKrvW\u0026q=%5B%5B%3Ad+%3D+at%28document.id%2C+%22XAa2xhEAAC0Aoary%22%29+%5D%5D","tags":[],"first_publication_date":"2018-12-04T17:37:24+0000","last_publication_date":"2022-08-08T20:51:44+0000","slugs":["iar-systems-and-sifive-partner-to-meet-customers-demands-for-professional-solutions-for-risc-v"],"linked_documents":[],"lang":"en-us","alternate_languages":[],"data":{"page_title":null,"meta_description":null,"title":[{"type":"heading1","text":"IAR Systems and SiFive partner to meet customers' demands for professional solutions for RISC-V","spans":[]}],"publish_to":"Archive","publish_date":"2018-12-04","share_image":{"link_type":"Media"},"body":[{"type":"preformatted","text":"*Establish partnership for delivering increased possibilities for powerful RISC-V implementations*\n\n**RISC-V Summit, Santa Clara, California—December 3, 2018—** IAR\nSystems®, the future-proof supplier of software tools and services for\nembedded development, and SiFive, the leading provider of commercial\nRISC-V processor IP, announce that they have formed a partnership in\norder to deliver increased possibilities for powerful RISC-V\nimplementations with compact code and high performance.\n\nThe RISC-V technology and ecosystem are evolving rapidly. With the rapid\ngrowth, the need for professional development tools is increasing. IAR\nSystems and SiFive are responding to this need with an increased\ncollaboration to bring IAR Systems' leading compiler and debugger\ntechnology to users of SiFive's high-performance and highly configurable\ncore IP. By tightly integrating IAR Systems' industry leading compiler\nand debugging tools with SiFive's industry leading RISC-V core IP, the\ncompanies will provide developers with powerful, easy-to-use, complete\nsolutions enabling users to get started quickly.\n\nSiFive brings a unique platform for rapidly designing, testing and\nbuilding RISC‑V-based core IP and chips, accelerating the pace of\ninnovation for large and small businesses. IAR Systems, the provider of\nthe mostly widely used toolchain for building embedded applications, now\nbrings its expertise in compiler and debugger technology to RISC-V,\nproviding new possibilities for maximized performance and minimized code\nsize.\n\n\"We are dedicated to help our customers find the right solution for\ntheir specific needs,\" says Anders Holmberg, Chief Strategy Officer, IAR\nSystems. \"SiFive is a leader in commercial RISC-V core IP, and our\ntoolchain IAR Embedded Workbench is the most widely used toolchain for\nbuilding embedded applications. Together, we can help companies to boost\ntheir productivity and focus on innovation.\"\n\n\"Modern compute workloads is creating Embedded Intelligence everywhere,\nwith significant innovation at the hardware-software interface,\"\ncomments Jack Kang, VP Product Marketing, SiFive. \"In order to stay\nahead, companies need scalable, efficient custom silicon solutions and\npowerful development tools. We are excited to join forces with IAR\nSystems to provide new possibilities for the RISC-V community.\"\n\nIAR Embedded Workbench® for RISC-V will be available mid-2019. The\ntoolchain will offer leading code quality, size and speed as well as\nextensive debug functionality with a fully integrated debugger with\nsimulator and hardware debugging support. The significant development\nmilestones will be showcased at the SiFive booth (\\#202) at the RISC-V\nSummit on December 4th and 5th. As always, the strong technology\noffering is accompanied by IAR Systems' renowned technical support and\nservices.\n\n## Ends\n\n***Editor\\'s Note:** IAR Systems, IAR Embedded Workbench, Embedded\nTrust, IAR Connect, C-SPY, C-RUN, C-STAT, IAR Visual State, IAR\nKickStart Kit, I-jet, I-jet Trace, I-scope, IAR Academy, IAR, and the\nlogotype of IAR Systems are trademarks or registered trademarks owned by\nIAR Systems AB. All other product names are trademarks of their\nrespective owners.*\n\n## IAR Systems Contacts\n\nAnnaMaria Tahlén, Media Relations, IAR Systems\n\nTel: +46 18 16 78 00 Email: \u003cannamaria.tahlen@iar.com\u003e\n\nStefan Skarin, CEO and President, IAR Systems\n\nTel: +46 18 16 78 00 Email: \u003cstefan.skarin@iar.com\u003e\n\nSIFive Contact\n\nJamie Feller, SHIFT Communications for SiFive\n\nTel: +1 (415) 591-8432 Email: \u003csifive@shiftcomm.com\u003e\n\n## About IAR Systems\n\nIAR Systems supplies future-proof software tools and services for\nembedded development, enabling companies worldwide to create the\nproducts of today and the innovations of tomorrow. Since 1983, IAR\nSystems' solutions have ensured quality, reliability and efficiency in\nthe development of over one million embedded applications. The company\nis headquartered in Uppsala, Sweden and has sales and support offices\nall over the world. Since 2018, Secure Thingz, a provider of advanced\nsecurity solutions for embedded systems in the IoT, is part of IAR\nSystems. IAR Systems Group AB is listed on NASDAQ OMX Stockholm, Mid\nCap. Learn more at [www.iar.com](http://www.iar.com).\n\n## About SiFive\n\nSiFive is the leading provider of market-ready processor core IP,\ndevelopment tools and silicon solutions based on the free and open\nRISC-V instruction set architecture. Led by a team of seasoned silicon\nexecutives and the RISC-V inventors, SiFive helps SoC designers reduce\ntime-to-market and realize cost savings with customized,\nopen-architecture processor cores, and democratizes access to optimized\nsilicon by enabling system designers in all market verticals to build\ncustomized RISC-V based semiconductors. SiFive is located in Silicon\nValley and has backing from Sutter Hill Ventures, Spark Capital, Osage\nUniversity Partners, Chengwei, Huami, SK Hynix, Intel Capital, and\nWestern Digital. For more information, visit\n[www.sifive.com](http://www.sifive.com).\n","spans":[]}]}}]},"__N_SSG":true},"page":"/press","query":{},"buildId":"rOIuzcDCX1911bPXtr7-t","isFallback":false,"isExperimentalCompile":false,"gsp":true,"locale":"en-us","locales":["en-us","zh-cn"],"defaultLocale":"en-us","domainLocales":[{"domain":"www.sifive.com","defaultLocale":"en-us"},{"domain":"www.sifive.cn","defaultLocale":"zh-cn"}],"scriptLoader":[{"id":"google-tag-manager","strategy":"afterInteractive","children":"\n (function (w, d, s, l, i) {\n w[l] = w[l] || [];\n w[l].push({ \"gtm.start\": new Date().getTime(), event: \"gtm.js\" });\n var f = d.getElementsByTagName(s)[0],\n j = d.createElement(s),\n dl = l != \"dataLayer\" ? \"\u0026l=\" + l : \"\";\n j.async = true;\n j.src = \"https://www.googletagmanager.com/gtm.js?id=\" + i + dl;\n f.parentNode.insertBefore(j, f);\n })(window, document, \"script\", \"dataLayer\", \"GTM-TTH6HTM\");\n "},{"src":"https://www.googletagmanager.com/gtag/js?id=G-41SWBNHLEK","strategy":"afterInteractive"},{"id":"google-analytics","strategy":"afterInteractive","children":"\n window.dataLayer = window.dataLayer || []; \n function gtag(){dataLayer.push(arguments);} \n gtag('js', new Date()); \n gtag('config', 'G-41SWBNHLEK');\n "},{"id":"segment","strategy":"afterInteractive","children":"\n !function(){\n var analytics=window.analytics=window.analytics||[];\n if(!analytics.initialize)if(analytics.invoked)window.console\u0026\u0026console.error\u0026\u0026console.error(\"Segment snippet included twice.\");else{analytics.invoked=!0;analytics.methods=[\"trackSubmit\",\"trackClick\",\"trackLink\",\"trackForm\",\"pageview\",\"identify\",\"reset\",\"group\",\"track\",\"ready\",\"alias\",\"debug\",\"page\",\"once\",\"off\",\"on\"];analytics.factory=function(t){return function(){var e=Array.prototype.slice.call(arguments);e.unshift(t);analytics.push(e);return analytics}};for(var t=0;t\u003canalytics.methods.length;t++){var e=analytics.methods[t];analytics[e]=analytics.factory(e)}analytics.load=function(t,e){var n=document.createElement(\"script\");n.type=\"text/javascript\";n.async=!0;n.src=\"https://cdn.segment.com/analytics.js/v1/\"+t+\"/analytics.min.js\";var a=document.getElementsByTagName(\"script\")[0];a.parentNode.insertBefore(n,a);analytics._loadOptions=e};\n analytics.SNIPPET_VERSION=\"4.1.0\";\n analytics.load(\"sOS7puT996WV5wh0V6QR1AYps6trxHJQ\");\n }}();\n "},{"id":"hs-script-loader","src":"//js.hs-scripts.com/3020607.js","strategy":"afterInteractive"}]}</script></body></html>